[PATCH v6 2/2] dt-bindings: mfd: Add DT compatible string "google,cros_ec_uart"
Add DT compatible string in Documentation/devicetree/bindings/mfd/google,cros-ec.yaml Signed-off-by: Bhanu Prakash Maiya Reviewed-by: Rob Herring --- Changes in v6: - No change Changes in v5: - No change Changes in v4: - Changes in commit message. Changes in v3: - Rebased changes on google,cros-ec.yaml Changes in v2: - No change Documentation/devicetree/bindings/mfd/google,cros-ec.yaml | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml b/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml index 6a7279a85ec1c..552d1c9bf3de4 100644 --- a/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml +++ b/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml @@ -10,11 +10,12 @@ maintainers: - Benson Leung - Enric Balletbo i Serra - Guenter Roeck + - Bhanu Prakash Maiya description: Google's ChromeOS EC is a microcontroller which talks to the AP and implements various functions such as keyboard and battery charging. - The EC can be connected through various interfaces (I2C, SPI, and others) + The EC can be connected through various interfaces (I2C, SPI, UART and others) and the compatible string specifies which interface is being used. properties: @@ -29,6 +30,9 @@ properties: - description: For implementations of the EC is connected through RPMSG. const: google,cros-ec-rpmsg + - description: + For implementations of the EC is connected through UART. +const: google,cros-ec-uart google,cros-ec-spi-pre-delay: description: -- 2.26.2
[PATCH v6 1/2] platform/chrome: cros_ec_uart: Add cros-ec-uart transport layer
This patch does following: 1. Adds a new cros-ec-uart driver. This driver can send EC requests on UART and process response packets received on UART transport. 2. Once probed, this driver will initialize the serdev device based on the underlying information in the ACPI resource. After serdev device properties are set, this driver will register itself cros-ec. 3. High level driver can use this implementation to talk to ChromeOS Embedded Controller device in case it supports UART as transport. 4. When cros-ec driver initiates a request packet, outgoing message is processed in buffer and sent via serdev. Once bytes are sent, driver enables a wait_queue. 5. Since ChromeOS EC device sends response asynchronously, AP's TTY driver accumulates response bytes and calls the registered callback. TTY driver can send multiple callback for bytes ranging from 1 to MAX bytes supported by EC device. 6. Driver waits for EC_MSG_DEADLINE_MS to collect and process received bytes. It wakes wait_queue if expected bytes are received or else wait_queue timeout. Based on the error condition, driver returns data_len or error to cros_ec. Signed-off-by: Bhanu Prakash Maiya --- Changes in v6: - Tuning EC_MSG_DEADLINE_MS from 1 sec to 500 msec. Since the EC's UART response buffer was tuned and redeuced to 256 byte, 500 msec timeout should give enough time for 256 bytes to be recieved from SoC UART buffer. Changes in v5: - Fixed checkpatch.pl warnings. Changes in v4: - Change EC_MSG_DEADLINE_MS from 3 secs to 1 sec. 3 secs timeout prevents driver from intercepting EC in RO stage. In case of request failure, 1 sec allows driver to retry and send HC when EC is in RO. - Add more information in commit message. Changes in v3: - checkpatch.pl script warns about char len 80 even though we have relaxed view guideline for line below 100 chars. Currently sticking with 80 chars in v3. - Fixed style issues Changes in v2: - Fixed build error on v1. - Changed EC timeout for response packet to 3 Sec and added comments. - Fixed cros_ec_uart_rx_bytes function to handle rx buffer < size of response header. MAINTAINERS| 6 + drivers/platform/chrome/Kconfig| 10 + drivers/platform/chrome/Makefile | 1 + drivers/platform/chrome/cros_ec_uart.c | 415 + 4 files changed, 432 insertions(+) create mode 100644 drivers/platform/chrome/cros_ec_uart.c diff --git a/MAINTAINERS b/MAINTAINERS index 9a54806ebf020..d027e53777e15 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4154,6 +4154,12 @@ S: Maintained F: Documentation/devicetree/bindings/sound/google,cros-ec-codec.yaml F: sound/soc/codecs/cros_ec_codec.* +CHROMEOS EC UART DRIVER +M: Bhanu Prakash Maiya +R: Enric Balletbo i Serra +S: Maintained +F: drivers/platform/chrome/cros_ec_uart.c + CHROMEOS EC SUBDRIVERS M: Benson Leung M: Enric Balletbo i Serra diff --git a/drivers/platform/chrome/Kconfig b/drivers/platform/chrome/Kconfig index a056031dee811..90fcebba2a904 100644 --- a/drivers/platform/chrome/Kconfig +++ b/drivers/platform/chrome/Kconfig @@ -118,6 +118,16 @@ config CROS_EC_SPI response time cannot be guaranteed, we support ignoring 'pre-amble' bytes before the response actually starts. +config CROS_EC_UART + tristate "ChromeOS Embedded Controller (UART)" + depends on CROS_EC && ACPI && SERIAL_DEV_BUS + help + If you say Y here, you get support for talking to the ChromeOS EC + through a UART, using a byte-level protocol. + + To compile this driver as a module, choose M here: the + module will be called cros_ec_uart. + config CROS_EC_LPC tristate "ChromeOS Embedded Controller (LPC)" depends on CROS_EC && ACPI && (X86 || COMPILE_TEST) diff --git a/drivers/platform/chrome/Makefile b/drivers/platform/chrome/Makefile index 41baccba033f7..47d8d0f890ca2 100644 --- a/drivers/platform/chrome/Makefile +++ b/drivers/platform/chrome/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_CROS_EC_I2C) += cros_ec_i2c.o obj-$(CONFIG_CROS_EC_ISHTP)+= cros_ec_ishtp.o obj-$(CONFIG_CROS_EC_RPMSG)+= cros_ec_rpmsg.o obj-$(CONFIG_CROS_EC_SPI) += cros_ec_spi.o +obj-$(CONFIG_CROS_EC_UART) += cros_ec_uart.o cros_ec_lpcs-objs := cros_ec_lpc.o cros_ec_lpc_mec.o obj-$(CONFIG_CROS_EC_TYPEC)+= cros_ec_typec.o obj-$(CONFIG_CROS_EC_LPC) += cros_ec_lpcs.o diff --git a/drivers/platform/chrome/cros_ec_uart.c b/drivers/platform/chrome/cros_ec_uart.c new file mode 100644 index 0..aaa290075d42b --- /dev/null +++ b/drivers/platform/chrome/cros_ec_uart.c @@ -0,0 +1,415 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * UART interface for ChromeOS Embedded Controller + * + * Copyright 2020 Google LLC. + */ + +#include
[PATCH v5 1/2] platform/chrome: cros_ec_uart: Add cros-ec-uart transport layer
From: Bhanu Prakash Maiya This patch does following: 1. Adds a new cros-ec-uart driver. This driver can send EC requests on UART and process response packets received on UART transport. 2. Once probed, this driver will initialize the serdev device based on the underlying information in the ACPI resource. After serdev device properties are set, this driver will register itself cros-ec. 3. High level driver can use this implementation to talk to ChromeOS Embedded Controller device in case it supports UART as transport. 4. When cros-ec driver initiates a request packet, outgoing message is processed in buffer and sent via serdev. Once bytes are sent, driver enables a wait_queue. 5. Since ChromeOS EC device sends response asynchronously, AP's TTY driver accumulates response bytes and calls the registered callback. TTY driver can send multiple callback for bytes ranging from 1 to MAX bytes supported by EC device. 6. Driver waits for EC_MSG_DEADLINE_MS to collect and process received bytes. It wakes wait_queue if expected bytes are received or else wait_queue timeout. Based on the error condition, driver returns data_len or error to cros_ec. Signed-off-by: Bhanu Prakash Maiya --- Changes in v5: - Fixed checkpatch.pl warnings. Changes in v4: - Change EC_MSG_DEADLINE_MS from 3 secs to 1 sec. 3 secs timeout prevents driver from intercepting EC in RO stage. In case of request failure, 1 sec allows driver to retry and send HC when EC is in RO. - Add more information in commit message. Changes in v3: - checkpatch.pl script warns about char len 80 even though we have relaxed view guideline for line below 100 chars. Currently sticking with 80 chars in v3. - Fixed style issues Changes in v2: - Fixed build error on v1. - Changed EC timeout for response packet to 3 Sec and added comments. - Fixed cros_ec_uart_rx_bytes function to handle rx buffer < size of response header. MAINTAINERS| 6 + drivers/platform/chrome/Kconfig| 10 + drivers/platform/chrome/Makefile | 1 + drivers/platform/chrome/cros_ec_uart.c | 415 + 4 files changed, 432 insertions(+) create mode 100644 drivers/platform/chrome/cros_ec_uart.c diff --git a/MAINTAINERS b/MAINTAINERS index c8e8232c65da9..1603efb897a18 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4133,6 +4133,12 @@ S: Maintained F: Documentation/devicetree/bindings/sound/google,cros-ec-codec.yaml F: sound/soc/codecs/cros_ec_codec.* +CHROMEOS EC UART DRIVER +M: Bhanu Prakash Maiya +R: Enric Balletbo i Serra +S: Maintained +F: drivers/platform/chrome/cros_ec_uart.c + CHROMEOS EC SUBDRIVERS M: Benson Leung M: Enric Balletbo i Serra diff --git a/drivers/platform/chrome/Kconfig b/drivers/platform/chrome/Kconfig index cf072153bdc5d..88b1b7b277ba3 100644 --- a/drivers/platform/chrome/Kconfig +++ b/drivers/platform/chrome/Kconfig @@ -118,6 +118,16 @@ config CROS_EC_SPI response time cannot be guaranteed, we support ignoring 'pre-amble' bytes before the response actually starts. +config CROS_EC_UART + tristate "ChromeOS Embedded Controller (UART)" + depends on CROS_EC && ACPI && SERIAL_DEV_BUS + help + If you say Y here, you get support for talking to the ChromeOS EC + through a UART, using a byte-level protocol. + + To compile this driver as a module, choose M here: the + module will be called cros_ec_uart. + config CROS_EC_LPC tristate "ChromeOS Embedded Controller (LPC)" depends on CROS_EC && ACPI && (X86 || COMPILE_TEST) diff --git a/drivers/platform/chrome/Makefile b/drivers/platform/chrome/Makefile index 41baccba033f7..47d8d0f890ca2 100644 --- a/drivers/platform/chrome/Makefile +++ b/drivers/platform/chrome/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_CROS_EC_I2C) += cros_ec_i2c.o obj-$(CONFIG_CROS_EC_ISHTP)+= cros_ec_ishtp.o obj-$(CONFIG_CROS_EC_RPMSG)+= cros_ec_rpmsg.o obj-$(CONFIG_CROS_EC_SPI) += cros_ec_spi.o +obj-$(CONFIG_CROS_EC_UART) += cros_ec_uart.o cros_ec_lpcs-objs := cros_ec_lpc.o cros_ec_lpc_mec.o obj-$(CONFIG_CROS_EC_TYPEC)+= cros_ec_typec.o obj-$(CONFIG_CROS_EC_LPC) += cros_ec_lpcs.o diff --git a/drivers/platform/chrome/cros_ec_uart.c b/drivers/platform/chrome/cros_ec_uart.c new file mode 100644 index 0..6b4510e26bd12 --- /dev/null +++ b/drivers/platform/chrome/cros_ec_uart.c @@ -0,0 +1,415 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * UART interface for ChromeOS Embedded Controller + * + * Copyright 2020 Google LLC. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "cros_ec.h" + +/* + * EC sends contiguous bytes of response pack
[PATCH v5 2/2] dt-bindings: mfd: Add DT compatible string "google,cros_ec_uart"
From: Bhanu Prakash Maiya Add DT compatible string in Documentation/devicetree/bindings/mfd/google,cros-ec.yaml Signed-off-by: Bhanu Prakash Maiya Reviewed-by: Rob Herring --- Changes in v5: None Changes in v4: - Changes in commit message. Changes in v3: - Rebased changes on google,cros-ec.yaml Changes in v2: - No change Documentation/devicetree/bindings/mfd/google,cros-ec.yaml | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml b/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml index 6a7279a85ec1c..552d1c9bf3de4 100644 --- a/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml +++ b/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml @@ -10,11 +10,12 @@ maintainers: - Benson Leung - Enric Balletbo i Serra - Guenter Roeck + - Bhanu Prakash Maiya description: Google's ChromeOS EC is a microcontroller which talks to the AP and implements various functions such as keyboard and battery charging. - The EC can be connected through various interfaces (I2C, SPI, and others) + The EC can be connected through various interfaces (I2C, SPI, UART and others) and the compatible string specifies which interface is being used. properties: @@ -29,6 +30,9 @@ properties: - description: For implementations of the EC is connected through RPMSG. const: google,cros-ec-rpmsg + - description: + For implementations of the EC is connected through UART. +const: google,cros-ec-uart google,cros-ec-spi-pre-delay: description: -- 2.26.2
[PATCH v4 1/2] platform/chrome: cros_ec_uart: Add cros-ec-uart transport layer
From: Bhanu Prakash Maiya This patch does following: 1. Adds a new cros-ec-uart driver. This driver can send EC requests on UART and process response packets received on UART transport. 2. Once probed, this driver will initialize the serdev device based on the underlying information in the ACPI resource. After serdev device properties are set, this driver will register itself cros-ec. 3. High level driver can use this implementation to talk to ChromeOS Embedded Controller device in case it supports UART as transport. 4. When cros-ec driver initiates a request packet, outgoing message is processed in buffer and sent via serdev. Once bytes are sent, driver enables a wait_queue. 5. Since ChromeOS EC device sends response asynchronously, AP's TTY driver accumulates response bytes and calls the registered callback. TTY driver can send multiple callback for bytes ranging from 1 to MAX bytes supported by EC device. 6. Driver waits for EC_MSG_DEADLINE_MS to collect and process received bytes. It wakes wait_queue if expected bytes are received or else wait_queue timeout. Based on the error condition, driver returns data_len or error to cros_ec. Signed-off-by: Bhanu Prakash Maiya --- Changes in v4: - Change EC_MSG_DEADLINE_MS from 3 secs to 1 sec. 3 secs timeout prevents driver from intercepting EC in RO stage. In case of request failure, 1 sec allows driver to retry and send HC when EC is in RO. - Add more information in commit message. Changes in v3: - checkpatch.pl script warns about char len 80 even though we have relaxed view guideline for line below 100 chars. Currently sticking with 80 chars in v3. - Fixed style issues Changes in v2: - Fixed build error on v1. - Changed EC timeout for response packet to 3 Sec and added comments. - Fixed cros_ec_uart_rx_bytes function to handle rx buffer < size of response header. MAINTAINERS| 6 + drivers/platform/chrome/Kconfig| 10 + drivers/platform/chrome/Makefile | 1 + drivers/platform/chrome/cros_ec_uart.c | 414 + 4 files changed, 431 insertions(+) create mode 100644 drivers/platform/chrome/cros_ec_uart.c diff --git a/MAINTAINERS b/MAINTAINERS index c8e8232c65da9..1603efb897a18 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4133,6 +4133,12 @@ S: Maintained F: Documentation/devicetree/bindings/sound/google,cros-ec-codec.yaml F: sound/soc/codecs/cros_ec_codec.* +CHROMEOS EC UART DRIVER +M: Bhanu Prakash Maiya +R: Enric Balletbo i Serra +S: Maintained +F: drivers/platform/chrome/cros_ec_uart.c + CHROMEOS EC SUBDRIVERS M: Benson Leung M: Enric Balletbo i Serra diff --git a/drivers/platform/chrome/Kconfig b/drivers/platform/chrome/Kconfig index cf072153bdc5d..88b1b7b277ba3 100644 --- a/drivers/platform/chrome/Kconfig +++ b/drivers/platform/chrome/Kconfig @@ -118,6 +118,16 @@ config CROS_EC_SPI response time cannot be guaranteed, we support ignoring 'pre-amble' bytes before the response actually starts. +config CROS_EC_UART + tristate "ChromeOS Embedded Controller (UART)" + depends on CROS_EC && ACPI && SERIAL_DEV_BUS + help + If you say Y here, you get support for talking to the ChromeOS EC + through a UART, using a byte-level protocol. + + To compile this driver as a module, choose M here: the + module will be called cros_ec_uart. + config CROS_EC_LPC tristate "ChromeOS Embedded Controller (LPC)" depends on CROS_EC && ACPI && (X86 || COMPILE_TEST) diff --git a/drivers/platform/chrome/Makefile b/drivers/platform/chrome/Makefile index 41baccba033f7..47d8d0f890ca2 100644 --- a/drivers/platform/chrome/Makefile +++ b/drivers/platform/chrome/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_CROS_EC_I2C) += cros_ec_i2c.o obj-$(CONFIG_CROS_EC_ISHTP)+= cros_ec_ishtp.o obj-$(CONFIG_CROS_EC_RPMSG)+= cros_ec_rpmsg.o obj-$(CONFIG_CROS_EC_SPI) += cros_ec_spi.o +obj-$(CONFIG_CROS_EC_UART) += cros_ec_uart.o cros_ec_lpcs-objs := cros_ec_lpc.o cros_ec_lpc_mec.o obj-$(CONFIG_CROS_EC_TYPEC)+= cros_ec_typec.o obj-$(CONFIG_CROS_EC_LPC) += cros_ec_lpcs.o diff --git a/drivers/platform/chrome/cros_ec_uart.c b/drivers/platform/chrome/cros_ec_uart.c new file mode 100644 index 0..9ec964c0b96ce --- /dev/null +++ b/drivers/platform/chrome/cros_ec_uart.c @@ -0,0 +1,414 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * UART interface for ChromeOS Embedded Controller + * + * Copyright 2020 Google LLC. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "cros_ec.h" + +/* + * EC sends contiguous bytes of response packet on UART AP RX. + * TTY driver in AP accumulat
[PATCH v4 2/2] dt-bindings: mfd: Add DT compatible string "google,cros_ec_uart"
From: Bhanu Prakash Maiya Add DT compatible string in Documentation/devicetree/bindings/mfd/google,cros-ec.yaml Signed-off-by: Bhanu Prakash Maiya Reviewed-by: Rob Herring --- Changes in v4: - Changes in commit message. Changes in v3: - Rebased changes on google,cros-ec.yaml Changes in v2: - No change Documentation/devicetree/bindings/mfd/google,cros-ec.yaml | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml b/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml index 6a7279a85ec1c..552d1c9bf3de4 100644 --- a/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml +++ b/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml @@ -10,11 +10,12 @@ maintainers: - Benson Leung - Enric Balletbo i Serra - Guenter Roeck + - Bhanu Prakash Maiya description: Google's ChromeOS EC is a microcontroller which talks to the AP and implements various functions such as keyboard and battery charging. - The EC can be connected through various interfaces (I2C, SPI, and others) + The EC can be connected through various interfaces (I2C, SPI, UART and others) and the compatible string specifies which interface is being used. properties: @@ -29,6 +30,9 @@ properties: - description: For implementations of the EC is connected through RPMSG. const: google,cros-ec-rpmsg + - description: + For implementations of the EC is connected through UART. +const: google,cros-ec-uart google,cros-ec-spi-pre-delay: description: -- 2.26.2
[PATCH v3 2/2] dt-bindings: mfd: Add DT compatible string "google,cros_ec_uart"
From: Bhanu Prakash Maiya Add DT compatible string in Documentation/devicetree/bindings/mfd/cros_ec.txt Signed-off-by: Bhanu Prakash Maiya --- Changes in v3: - Rebased changes on google,cros-ec.yaml Changes in v2: - No change Documentation/devicetree/bindings/mfd/google,cros-ec.yaml | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml b/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml index 6a7279a85ec1c..552d1c9bf3de4 100644 --- a/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml +++ b/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml @@ -10,11 +10,12 @@ maintainers: - Benson Leung - Enric Balletbo i Serra - Guenter Roeck + - Bhanu Prakash Maiya description: Google's ChromeOS EC is a microcontroller which talks to the AP and implements various functions such as keyboard and battery charging. - The EC can be connected through various interfaces (I2C, SPI, and others) + The EC can be connected through various interfaces (I2C, SPI, UART and others) and the compatible string specifies which interface is being used. properties: @@ -29,6 +30,9 @@ properties: - description: For implementations of the EC is connected through RPMSG. const: google,cros-ec-rpmsg + - description: + For implementations of the EC is connected through UART. +const: google,cros-ec-uart google,cros-ec-spi-pre-delay: description: -- 2.26.2
[PATCH v3 1/2] platform/chrome: cros_ec_uart: Add cros-ec-uart transport layer
From: Bhanu Prakash Maiya This patch enables uart transport layer for cros_ec framework. The cros-ec-uart binds with EC device working on uart transport to send request and receive response. Signed-off-by: Bhanu Prakash Maiya --- Changes in v3: - checkpatch.pl script warns about char len 80 even though we have relaxed view guildeline for line below 100 chars. Currently sticking with 80 chars in v3. - Fixed style issues Changes in v2: - Fixed build error on v1. - Changed EC timeout for response packet to 3 Sec and added comments. - Fixed cros_ec_uart_rx_bytes function to handle rx buffer < size of response header. MAINTAINERS| 6 + drivers/platform/chrome/Kconfig| 10 + drivers/platform/chrome/Makefile | 1 + drivers/platform/chrome/cros_ec_uart.c | 410 + 4 files changed, 427 insertions(+) create mode 100644 drivers/platform/chrome/cros_ec_uart.c diff --git a/MAINTAINERS b/MAINTAINERS index 50659d76976b7..ee28a1da41c50 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4033,6 +4033,12 @@ S: Maintained F: Documentation/devicetree/bindings/sound/google,cros-ec-codec.yaml F: sound/soc/codecs/cros_ec_codec.* +CHROMEOS EC UART DRIVER +M: Bhanu Prakash Maiya +R: Enric Balletbo i Serra +S: Maintained +F: drivers/platform/chrome/cros_ec_uart.c + CHROMEOS EC SUBDRIVERS M: Benson Leung M: Enric Balletbo i Serra diff --git a/drivers/platform/chrome/Kconfig b/drivers/platform/chrome/Kconfig index 3822e5e111caa..2082fafe08a6a 100644 --- a/drivers/platform/chrome/Kconfig +++ b/drivers/platform/chrome/Kconfig @@ -125,6 +125,16 @@ config CROS_EC_SPI response time cannot be guaranteed, we support ignoring 'pre-amble' bytes before the response actually starts. +config CROS_EC_UART + tristate "ChromeOS Embedded Controller (UART)" + depends on CROS_EC && ACPI && SERIAL_DEV_BUS + help + If you say Y here, you get support for talking to the ChromeOS EC + through a UART, using a byte-level protocol. + + To compile this driver as a module, choose M here: the + module will be called cros_ec_uart. + config CROS_EC_LPC tristate "ChromeOS Embedded Controller (LPC)" depends on CROS_EC && ACPI && (X86 || COMPILE_TEST) diff --git a/drivers/platform/chrome/Makefile b/drivers/platform/chrome/Makefile index 8ed1e33033b38..fc449351fc794 100644 --- a/drivers/platform/chrome/Makefile +++ b/drivers/platform/chrome/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_CROS_EC_I2C) += cros_ec_i2c.o obj-$(CONFIG_CROS_EC_ISHTP)+= cros_ec_ishtp.o obj-$(CONFIG_CROS_EC_RPMSG)+= cros_ec_rpmsg.o obj-$(CONFIG_CROS_EC_SPI) += cros_ec_spi.o +obj-$(CONFIG_CROS_EC_UART) += cros_ec_uart.o cros_ec_lpcs-objs := cros_ec_lpc.o cros_ec_lpc_mec.o obj-$(CONFIG_CROS_EC_TYPEC)+= cros_ec_typec.o obj-$(CONFIG_CROS_EC_LPC) += cros_ec_lpcs.o diff --git a/drivers/platform/chrome/cros_ec_uart.c b/drivers/platform/chrome/cros_ec_uart.c new file mode 100644 index 0..45755061370a7 --- /dev/null +++ b/drivers/platform/chrome/cros_ec_uart.c @@ -0,0 +1,410 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * UART interface for ChromeOS Embedded Controller + * + * Copyright 2020 Google LLC. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "cros_ec.h" + +/* + * EC sends contiguous bytes of response packet on UART AP RX. + * TTY driver in AP accumulates incoming bytes and calls the registered callback + * function. Byte count can range from 1 to Max count supported by TTY driver. + * This driver should wait for long time for all callbacks to be processed. + * Considering the worst case scenario, wait for ~3 secs. This timeout should + * account for max latency and some additional guard time. + * In case the packet is received in ms, wait queue will be released and packet + * will be processed. + */ +#define EC_MSG_DEADLINE_MS (300 * 10) + +/** + * struct response_info - Encapsulate EC response related + * information for passing between function + * cros_ec_uart_pkt_xfer() and cros_ec_uart_rx_bytes() + * callback. + * @data: Copy the data received from EC here. + * @max_size: Max size allocated for the @data buffer. If the + * received data exceeds this value, we log an error. + * @size: Actual size of data received from EC. This is also + * used to accumulate byte count with response is received + * in dma chunks. + * @exp_len: Expected bytes of response from EC including header. + * @error: 0 for succes
[PATCH v2 2/2] dt-bindings: mfd: Add DT compatible string "google,cros_ec_uart"
From: Bhanu Prakash Maiya
Add DT compatible string in
Documentation/devicetree/bindings/mfd/cros_ec.txt
Series-to: LKML
Series-cc: Raul E Rangel , Furquan Shaikh
, Duncan Laurie , Eric Peers
, Benson Leung , Enric Balletbo i Serra
, Guenter Roeck ,
linux-kernel@vger.kernel.org, Lee Jones , Rob Herring
, devicet...@vger.kernel.org
Signed-off-by: Bhanu Prakash Maiya
Change-Id: Icfeab15fa04daaffc61280faf5a75cd9b23ee822
Signed-off-by: Bhanu Prakash Maiya
---
Documentation/devicetree/bindings/mfd/cros-ec.txt | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/mfd/cros-ec.txt
b/Documentation/devicetree/bindings/mfd/cros-ec.txt
index 4860eabd0f729..ec8c5d7ecc266 100644
--- a/Documentation/devicetree/bindings/mfd/cros-ec.txt
+++ b/Documentation/devicetree/bindings/mfd/cros-ec.txt
@@ -3,7 +3,7 @@ ChromeOS Embedded Controller
Google's ChromeOS EC is a Cortex-M device which talks to the AP and
implements various function such as keyboard and battery charging.
-The EC can be connect through various means (I2C, SPI, LPC, RPMSG) and the
+The EC can be connect through various means (I2C, SPI, UART, LPC, RPMSG) and
the
compatible string used depends on the interface. Each connection method has
its own driver which connects to the top level interface-agnostic EC driver.
Other Linux driver (such as cros-ec-keyb for the matrix keyboard) connect to
@@ -17,6 +17,10 @@ Required properties (SPI):
- compatible: "google,cros-ec-spi"
- reg: SPI chip select
+Required properties (UART):
+- compatible: "google,cros-ec-uart"
+- reg: UART baudrate, flowcontrol
+
Required properties (RPMSG):
- compatible: "google,cros-ec-rpmsg"
@@ -72,5 +76,6 @@ spi@131b {
};
};
-
Example for LPC is not supplied as it is not yet implemented.
+
+Example for UART is not supplied as it is not yet implemented.
--
2.27.0.389.gc38d7665816-goog
[PATCH v2 1/2] cros: platform/chrome: Add cros-ec-uart driver for uart support
From: Bhanu Prakash Maiya This patch enables uart transport layer for cros_ec framework. The cros-ec-uart binds with EC device working on uart transport to send request and receive response. Signed-off-by: Bhanu Prakash Maiya Reported-by: kernel test robot Change-Id: Icb23b633700f1ef4d123e3f21fd26fad21a3f207 Signed-off-by: Bhanu Prakash Maiya --- Changes in v2: 1: Fixed build error on v1. 2: Changed EC timeout for response packet to 3 Sec and added comments. 3: Fixed cros_ec_uart_rx_bytes function to handle rx buffer < size of response header. MAINTAINERS| 1 + drivers/platform/chrome/Kconfig| 10 + drivers/platform/chrome/Makefile | 1 + drivers/platform/chrome/cros_ec_uart.c | 411 + 4 files changed, 423 insertions(+) create mode 100644 drivers/platform/chrome/cros_ec_uart.c diff --git a/MAINTAINERS b/MAINTAINERS index 50659d76976b7..aa8e1d121c1d7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4036,6 +4036,7 @@ F:sound/soc/codecs/cros_ec_codec.* CHROMEOS EC SUBDRIVERS M: Benson Leung M: Enric Balletbo i Serra +M: Bhanu Prakash Maiya R: Guenter Roeck S: Maintained F: drivers/power/supply/cros_usbpd-charger.c diff --git a/drivers/platform/chrome/Kconfig b/drivers/platform/chrome/Kconfig index 3822e5e111caa..2082fafe08a6a 100644 --- a/drivers/platform/chrome/Kconfig +++ b/drivers/platform/chrome/Kconfig @@ -125,6 +125,16 @@ config CROS_EC_SPI response time cannot be guaranteed, we support ignoring 'pre-amble' bytes before the response actually starts. +config CROS_EC_UART + tristate "ChromeOS Embedded Controller (UART)" + depends on CROS_EC && ACPI && SERIAL_DEV_BUS + help + If you say Y here, you get support for talking to the ChromeOS EC + through a UART, using a byte-level protocol. + + To compile this driver as a module, choose M here: the + module will be called cros_ec_uart. + config CROS_EC_LPC tristate "ChromeOS Embedded Controller (LPC)" depends on CROS_EC && ACPI && (X86 || COMPILE_TEST) diff --git a/drivers/platform/chrome/Makefile b/drivers/platform/chrome/Makefile index 8ed1e33033b38..fc449351fc794 100644 --- a/drivers/platform/chrome/Makefile +++ b/drivers/platform/chrome/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_CROS_EC_I2C) += cros_ec_i2c.o obj-$(CONFIG_CROS_EC_ISHTP)+= cros_ec_ishtp.o obj-$(CONFIG_CROS_EC_RPMSG)+= cros_ec_rpmsg.o obj-$(CONFIG_CROS_EC_SPI) += cros_ec_spi.o +obj-$(CONFIG_CROS_EC_UART) += cros_ec_uart.o cros_ec_lpcs-objs := cros_ec_lpc.o cros_ec_lpc_mec.o obj-$(CONFIG_CROS_EC_TYPEC)+= cros_ec_typec.o obj-$(CONFIG_CROS_EC_LPC) += cros_ec_lpcs.o diff --git a/drivers/platform/chrome/cros_ec_uart.c b/drivers/platform/chrome/cros_ec_uart.c new file mode 100644 index 0..9a0ba884b6812 --- /dev/null +++ b/drivers/platform/chrome/cros_ec_uart.c @@ -0,0 +1,411 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * UART interface for ChromeOS Embedded Controller + * + * Copyright 2020 Google LLC. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "cros_ec.h" + +/* + * EC sends contiguous bytes of response packet on UART AP RX. + * TTY driver in AP accumulates incoming bytes and calls the registered callback + * function. Byte count can range from 1 to Max count supported by TTY driver. + * This driver should wait for long time for all callbacks to be processed. + * Considering the worst case scenario, wait for ~3 secs. This timeout should + * account for max latency and some additional guard time. + * In case the packet is received in ms, wait queue will be released and packet + * will be processed. + */ +#define EC_MSG_DEADLINE_MS (300 * 10) + +/** + * struct response_info - Encapsulate EC response related + * information for passing between function + * cros_ec_uart_pkt_xfer() and cros_ec_uart_rx_bytes() + * callback. + * @data: Copy the data received from EC here. + * @max_size: Max size allocated for the @data buffer. If the + * received data exceeds this value, we log an error. + * @size: Actual size of data received from EC. This is also + * used to accumulate byte count with response is received + * in dma chunks. + * @exp_len: Expected bytes of response from EC including header. + * @error: 0 for success, negative error code for a failure. + * @received: Set to true on receiving a valid EC response. + * @wait_queue:Wait queue EC response where the cros_ec sends request +
[PATCH 1/2] cros: platform/chrome: Add cros-ec-uart driver for uart support
From: Bhanu Prakash Maiya This patch enables uart transport layer for cros_ec framework. The cros-ec-uart binds with EC device working on uart transport to send request and receive response. Signed-off-by: Bhanu Prakash Maiya Reported-by: kernel test robot Change-Id: Icb23b633700f1ef4d123e3f21fd26fad21a3f207 --- Changes in v2: 1: Fixed build error on v1. 2: Changed EC timeout for response packet to 3 Sec and added comments. 3: Fixed cros_ec_uart_rx_bytes function to handle rx buffer < size of response header. MAINTAINERS| 1 + drivers/platform/chrome/Kconfig| 10 + drivers/platform/chrome/Makefile | 1 + drivers/platform/chrome/cros_ec_uart.c | 411 + 4 files changed, 423 insertions(+) create mode 100644 drivers/platform/chrome/cros_ec_uart.c diff --git a/MAINTAINERS b/MAINTAINERS index 50659d76976b7..aa8e1d121c1d7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4036,6 +4036,7 @@ F:sound/soc/codecs/cros_ec_codec.* CHROMEOS EC SUBDRIVERS M: Benson Leung M: Enric Balletbo i Serra +M: Bhanu Prakash Maiya R: Guenter Roeck S: Maintained F: drivers/power/supply/cros_usbpd-charger.c diff --git a/drivers/platform/chrome/Kconfig b/drivers/platform/chrome/Kconfig index 3822e5e111caa..2082fafe08a6a 100644 --- a/drivers/platform/chrome/Kconfig +++ b/drivers/platform/chrome/Kconfig @@ -125,6 +125,16 @@ config CROS_EC_SPI response time cannot be guaranteed, we support ignoring 'pre-amble' bytes before the response actually starts. +config CROS_EC_UART + tristate "ChromeOS Embedded Controller (UART)" + depends on CROS_EC && ACPI && SERIAL_DEV_BUS + help + If you say Y here, you get support for talking to the ChromeOS EC + through a UART, using a byte-level protocol. + + To compile this driver as a module, choose M here: the + module will be called cros_ec_uart. + config CROS_EC_LPC tristate "ChromeOS Embedded Controller (LPC)" depends on CROS_EC && ACPI && (X86 || COMPILE_TEST) diff --git a/drivers/platform/chrome/Makefile b/drivers/platform/chrome/Makefile index 8ed1e33033b38..fc449351fc794 100644 --- a/drivers/platform/chrome/Makefile +++ b/drivers/platform/chrome/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_CROS_EC_I2C) += cros_ec_i2c.o obj-$(CONFIG_CROS_EC_ISHTP)+= cros_ec_ishtp.o obj-$(CONFIG_CROS_EC_RPMSG)+= cros_ec_rpmsg.o obj-$(CONFIG_CROS_EC_SPI) += cros_ec_spi.o +obj-$(CONFIG_CROS_EC_UART) += cros_ec_uart.o cros_ec_lpcs-objs := cros_ec_lpc.o cros_ec_lpc_mec.o obj-$(CONFIG_CROS_EC_TYPEC)+= cros_ec_typec.o obj-$(CONFIG_CROS_EC_LPC) += cros_ec_lpcs.o diff --git a/drivers/platform/chrome/cros_ec_uart.c b/drivers/platform/chrome/cros_ec_uart.c new file mode 100644 index 0..9a0ba884b6812 --- /dev/null +++ b/drivers/platform/chrome/cros_ec_uart.c @@ -0,0 +1,411 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * UART interface for ChromeOS Embedded Controller + * + * Copyright 2020 Google LLC. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "cros_ec.h" + +/* + * EC sends contiguous bytes of response packet on UART AP RX. + * TTY driver in AP accumulates incoming bytes and calls the registered callback + * function. Byte count can range from 1 to Max count supported by TTY driver. + * This driver should wait for long time for all callbacks to be processed. + * Considering the worst case scenario, wait for ~3 secs. This timeout should + * account for max latency and some additional guard time. + * In case the packet is received in ms, wait queue will be released and packet + * will be processed. + */ +#define EC_MSG_DEADLINE_MS (300 * 10) + +/** + * struct response_info - Encapsulate EC response related + * information for passing between function + * cros_ec_uart_pkt_xfer() and cros_ec_uart_rx_bytes() + * callback. + * @data: Copy the data received from EC here. + * @max_size: Max size allocated for the @data buffer. If the + * received data exceeds this value, we log an error. + * @size: Actual size of data received from EC. This is also + * used to accumulate byte count with response is received + * in dma chunks. + * @exp_len: Expected bytes of response from EC including header. + * @error: 0 for success, negative error code for a failure. + * @received: Set to true on receiving a valid EC response. + * @wait_queue:Wait queue EC response where the cros_ec sends request + * to EC and wait
[PATCH v2 2/2] dt-bindings: mfd: Add DT compatible string "google,cros_ec_uart"
From: Bhanu Prakash Maiya
Add DT compatible string in
Documentation/devicetree/bindings/mfd/cros_ec.txt
Series-to: LKML
Series-cc: Raul E Rangel , Furquan Shaikh
, Duncan Laurie , Eric Peers
, Benson Leung , Enric Balletbo i Serra
, Guenter Roeck ,
linux-kernel@vger.kernel.org, Lee Jones , Rob Herring
, devicet...@vger.kernel.org
Signed-off-by: Bhanu Prakash Maiya
Change-Id: Icfeab15fa04daaffc61280faf5a75cd9b23ee822
Signed-off-by: Bhanu Prakash Maiya
---
Documentation/devicetree/bindings/mfd/cros-ec.txt | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/mfd/cros-ec.txt
b/Documentation/devicetree/bindings/mfd/cros-ec.txt
index 4860eabd0f729..ec8c5d7ecc266 100644
--- a/Documentation/devicetree/bindings/mfd/cros-ec.txt
+++ b/Documentation/devicetree/bindings/mfd/cros-ec.txt
@@ -3,7 +3,7 @@ ChromeOS Embedded Controller
Google's ChromeOS EC is a Cortex-M device which talks to the AP and
implements various function such as keyboard and battery charging.
-The EC can be connect through various means (I2C, SPI, LPC, RPMSG) and the
+The EC can be connect through various means (I2C, SPI, UART, LPC, RPMSG) and
the
compatible string used depends on the interface. Each connection method has
its own driver which connects to the top level interface-agnostic EC driver.
Other Linux driver (such as cros-ec-keyb for the matrix keyboard) connect to
@@ -17,6 +17,10 @@ Required properties (SPI):
- compatible: "google,cros-ec-spi"
- reg: SPI chip select
+Required properties (UART):
+- compatible: "google,cros-ec-uart"
+- reg: UART baudrate, flowcontrol
+
Required properties (RPMSG):
- compatible: "google,cros-ec-rpmsg"
@@ -72,5 +76,6 @@ spi@131b {
};
};
-
Example for LPC is not supplied as it is not yet implemented.
+
+Example for UART is not supplied as it is not yet implemented.
--
2.27.0.389.gc38d7665816-goog
[PATCH v2 1/2] cros: platform/chrome: Add cros-ec-uart driver for uart support
From: Bhanu Prakash Maiya
This patch enables uart transport layer for cros_ec framework.
The cros-ec-uart binds with EC device working on uart transport to
send request and receive response.
Signed-off-by: Bhanu Prakash Maiya
Reported-by: kernel test robot
Change-Id: Icb23b633700f1ef4d123e3f21fd26fad21a3f207
Signed-off-by: Bhanu Prakash Maiya
---
MAINTAINERS| 1 +
drivers/platform/chrome/Kconfig| 10 +
drivers/platform/chrome/Makefile | 1 +
drivers/platform/chrome/cros_ec_uart.c | 411 +
4 files changed, 423 insertions(+)
create mode 100644 drivers/platform/chrome/cros_ec_uart.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 50659d76976b7..aa8e1d121c1d7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -4036,6 +4036,7 @@ F:sound/soc/codecs/cros_ec_codec.*
CHROMEOS EC SUBDRIVERS
M: Benson Leung
M: Enric Balletbo i Serra
+M: Bhanu Prakash Maiya
R: Guenter Roeck
S: Maintained
F: drivers/power/supply/cros_usbpd-charger.c
diff --git a/drivers/platform/chrome/Kconfig b/drivers/platform/chrome/Kconfig
index 3822e5e111caa..2082fafe08a6a 100644
--- a/drivers/platform/chrome/Kconfig
+++ b/drivers/platform/chrome/Kconfig
@@ -125,6 +125,16 @@ config CROS_EC_SPI
response time cannot be guaranteed, we support ignoring
'pre-amble' bytes before the response actually starts.
+config CROS_EC_UART
+ tristate "ChromeOS Embedded Controller (UART)"
+ depends on CROS_EC && ACPI && SERIAL_DEV_BUS
+ help
+ If you say Y here, you get support for talking to the ChromeOS EC
+ through a UART, using a byte-level protocol.
+
+ To compile this driver as a module, choose M here: the
+ module will be called cros_ec_uart.
+
config CROS_EC_LPC
tristate "ChromeOS Embedded Controller (LPC)"
depends on CROS_EC && ACPI && (X86 || COMPILE_TEST)
diff --git a/drivers/platform/chrome/Makefile b/drivers/platform/chrome/Makefile
index 8ed1e33033b38..fc449351fc794 100644
--- a/drivers/platform/chrome/Makefile
+++ b/drivers/platform/chrome/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_CROS_EC_I2C) += cros_ec_i2c.o
obj-$(CONFIG_CROS_EC_ISHTP)+= cros_ec_ishtp.o
obj-$(CONFIG_CROS_EC_RPMSG)+= cros_ec_rpmsg.o
obj-$(CONFIG_CROS_EC_SPI) += cros_ec_spi.o
+obj-$(CONFIG_CROS_EC_UART) += cros_ec_uart.o
cros_ec_lpcs-objs := cros_ec_lpc.o cros_ec_lpc_mec.o
obj-$(CONFIG_CROS_EC_TYPEC)+= cros_ec_typec.o
obj-$(CONFIG_CROS_EC_LPC) += cros_ec_lpcs.o
diff --git a/drivers/platform/chrome/cros_ec_uart.c
b/drivers/platform/chrome/cros_ec_uart.c
new file mode 100644
index 0..9a0ba884b6812
--- /dev/null
+++ b/drivers/platform/chrome/cros_ec_uart.c
@@ -0,0 +1,411 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * UART interface for ChromeOS Embedded Controller
+ *
+ * Copyright 2020 Google LLC.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "cros_ec.h"
+
+/*
+ * EC sends contiguous bytes of response packet on UART AP RX.
+ * TTY driver in AP accumulates incoming bytes and calls the registered
callback
+ * function. Byte count can range from 1 to Max count supported by TTY driver.
+ * This driver should wait for long time for all callbacks to be processed.
+ * Considering the worst case scenario, wait for ~3 secs. This timeout should
+ * account for max latency and some additional guard time.
+ * In case the packet is received in ms, wait queue will be released and packet
+ * will be processed.
+ */
+#define EC_MSG_DEADLINE_MS (300 * 10)
+
+/**
+ * struct response_info - Encapsulate EC response related
+ * information for passing between function
+ * cros_ec_uart_pkt_xfer() and cros_ec_uart_rx_bytes()
+ * callback.
+ * @data: Copy the data received from EC here.
+ * @max_size: Max size allocated for the @data buffer. If the
+ * received data exceeds this value, we log an error.
+ * @size: Actual size of data received from EC. This is also
+ * used to accumulate byte count with response is received
+ * in dma chunks.
+ * @exp_len: Expected bytes of response from EC including header.
+ * @error: 0 for success, negative error code for a failure.
+ * @received: Set to true on receiving a valid EC response.
+ * @wait_queue:Wait queue EC response where the cros_ec sends
request
+ * to EC and waits
+ */
+struct response_info {
+ void *data;
+ size_t max_size;
+ size_t size;
+ int error;
+ size_t exp_len;
+ bool received;
+ wa
[PATCH 1/2] cros: platform/chrome: Add cros-ec-uart driver for uart support
From: Bhanu Prakash Maiya
This patch enables uart transport layer for cros_ec framework.
The cros-ec-uart binds with EC device working on uart transport to
send request and receive response.
Signed-off-by: Bhanu Prakash Maiya
Reported-by: kernel test robot
Change-Id: Icb23b633700f1ef4d123e3f21fd26fad21a3f207
---
MAINTAINERS| 1 +
drivers/platform/chrome/Kconfig| 10 +
drivers/platform/chrome/Makefile | 1 +
drivers/platform/chrome/cros_ec_uart.c | 411 +
4 files changed, 423 insertions(+)
create mode 100644 drivers/platform/chrome/cros_ec_uart.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 50659d76976b7..aa8e1d121c1d7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -4036,6 +4036,7 @@ F:sound/soc/codecs/cros_ec_codec.*
CHROMEOS EC SUBDRIVERS
M: Benson Leung
M: Enric Balletbo i Serra
+M: Bhanu Prakash Maiya
R: Guenter Roeck
S: Maintained
F: drivers/power/supply/cros_usbpd-charger.c
diff --git a/drivers/platform/chrome/Kconfig b/drivers/platform/chrome/Kconfig
index 3822e5e111caa..2082fafe08a6a 100644
--- a/drivers/platform/chrome/Kconfig
+++ b/drivers/platform/chrome/Kconfig
@@ -125,6 +125,16 @@ config CROS_EC_SPI
response time cannot be guaranteed, we support ignoring
'pre-amble' bytes before the response actually starts.
+config CROS_EC_UART
+ tristate "ChromeOS Embedded Controller (UART)"
+ depends on CROS_EC && ACPI && SERIAL_DEV_BUS
+ help
+ If you say Y here, you get support for talking to the ChromeOS EC
+ through a UART, using a byte-level protocol.
+
+ To compile this driver as a module, choose M here: the
+ module will be called cros_ec_uart.
+
config CROS_EC_LPC
tristate "ChromeOS Embedded Controller (LPC)"
depends on CROS_EC && ACPI && (X86 || COMPILE_TEST)
diff --git a/drivers/platform/chrome/Makefile b/drivers/platform/chrome/Makefile
index 8ed1e33033b38..fc449351fc794 100644
--- a/drivers/platform/chrome/Makefile
+++ b/drivers/platform/chrome/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_CROS_EC_I2C) += cros_ec_i2c.o
obj-$(CONFIG_CROS_EC_ISHTP)+= cros_ec_ishtp.o
obj-$(CONFIG_CROS_EC_RPMSG)+= cros_ec_rpmsg.o
obj-$(CONFIG_CROS_EC_SPI) += cros_ec_spi.o
+obj-$(CONFIG_CROS_EC_UART) += cros_ec_uart.o
cros_ec_lpcs-objs := cros_ec_lpc.o cros_ec_lpc_mec.o
obj-$(CONFIG_CROS_EC_TYPEC)+= cros_ec_typec.o
obj-$(CONFIG_CROS_EC_LPC) += cros_ec_lpcs.o
diff --git a/drivers/platform/chrome/cros_ec_uart.c
b/drivers/platform/chrome/cros_ec_uart.c
new file mode 100644
index 0..9a0ba884b6812
--- /dev/null
+++ b/drivers/platform/chrome/cros_ec_uart.c
@@ -0,0 +1,411 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * UART interface for ChromeOS Embedded Controller
+ *
+ * Copyright 2020 Google LLC.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "cros_ec.h"
+
+/*
+ * EC sends contiguous bytes of response packet on UART AP RX.
+ * TTY driver in AP accumulates incoming bytes and calls the registered
callback
+ * function. Byte count can range from 1 to Max count supported by TTY driver.
+ * This driver should wait for long time for all callbacks to be processed.
+ * Considering the worst case scenario, wait for ~3 secs. This timeout should
+ * account for max latency and some additional guard time.
+ * In case the packet is received in ms, wait queue will be released and packet
+ * will be processed.
+ */
+#define EC_MSG_DEADLINE_MS (300 * 10)
+
+/**
+ * struct response_info - Encapsulate EC response related
+ * information for passing between function
+ * cros_ec_uart_pkt_xfer() and cros_ec_uart_rx_bytes()
+ * callback.
+ * @data: Copy the data received from EC here.
+ * @max_size: Max size allocated for the @data buffer. If the
+ * received data exceeds this value, we log an error.
+ * @size: Actual size of data received from EC. This is also
+ * used to accumulate byte count with response is received
+ * in dma chunks.
+ * @exp_len: Expected bytes of response from EC including header.
+ * @error: 0 for success, negative error code for a failure.
+ * @received: Set to true on receiving a valid EC response.
+ * @wait_queue:Wait queue EC response where the cros_ec sends
request
+ * to EC and waits
+ */
+struct response_info {
+ void *data;
+ size_t max_size;
+ size_t size;
+ int error;
+ size_t exp_len;
+ bool received;
+ wait_queue_head_t wait_queue;
+};
+
+/*
[PATCH 2/2] dt-bindings: mfd: Add DT compatible string "google,cros_ec_uart"
From: Bhanu Prakash Maiya
Add DT compatible string in
Documentation/devicetree/bindings/mfd/cros_ec.txt
Series-to: LKML
Series-cc: Raul E Rangel , Furquan Shaikh
, Duncan Laurie , Eric Peers
, Benson Leung , Enric Balletbo i Serra
, Guenter Roeck ,
linux-kernel@vger.kernel.org, Lee Jones , Rob Herring
, devicet...@vger.kernel.org
Signed-off-by: Bhanu Prakash Maiya
Change-Id: Icfeab15fa04daaffc61280faf5a75cd9b23ee822
---
Documentation/devicetree/bindings/mfd/cros-ec.txt | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/mfd/cros-ec.txt
b/Documentation/devicetree/bindings/mfd/cros-ec.txt
index 4860eabd0f729..ec8c5d7ecc266 100644
--- a/Documentation/devicetree/bindings/mfd/cros-ec.txt
+++ b/Documentation/devicetree/bindings/mfd/cros-ec.txt
@@ -3,7 +3,7 @@ ChromeOS Embedded Controller
Google's ChromeOS EC is a Cortex-M device which talks to the AP and
implements various function such as keyboard and battery charging.
-The EC can be connect through various means (I2C, SPI, LPC, RPMSG) and the
+The EC can be connect through various means (I2C, SPI, UART, LPC, RPMSG) and
the
compatible string used depends on the interface. Each connection method has
its own driver which connects to the top level interface-agnostic EC driver.
Other Linux driver (such as cros-ec-keyb for the matrix keyboard) connect to
@@ -17,6 +17,10 @@ Required properties (SPI):
- compatible: "google,cros-ec-spi"
- reg: SPI chip select
+Required properties (UART):
+- compatible: "google,cros-ec-uart"
+- reg: UART baudrate, flowcontrol
+
Required properties (RPMSG):
- compatible: "google,cros-ec-rpmsg"
@@ -72,5 +76,6 @@ spi@131b {
};
};
-
Example for LPC is not supplied as it is not yet implemented.
+
+Example for UART is not supplied as it is not yet implemented.
--
2.26.2
[PATCH 1/2] cros: platform/chrome: Add cros-ec-uart driver for uart support
This patch enables uart transport layer for cros_ec framework.
The cros-ec-uart binds with EC device working on uart transport to
send request and receive response.
Signed-off-by: Bhanu Prakash Maiya
---
MAINTAINERS| 1 +
drivers/platform/chrome/Kconfig| 10 +
drivers/platform/chrome/Makefile | 1 +
drivers/platform/chrome/cros_ec_uart.c | 399 +
4 files changed, 411 insertions(+)
create mode 100644 drivers/platform/chrome/cros_ec_uart.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 7b5ffd646c6b9..d4a089673429a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -4095,6 +4095,7 @@ F:sound/soc/codecs/cros_ec_codec.*
CHROMEOS EC SUBDRIVERS
M: Benson Leung
M: Enric Balletbo i Serra
+M: Bhanu Prakash Maiya
R: Guenter Roeck
S: Maintained
F: drivers/power/supply/cros_usbpd-charger.c
diff --git a/drivers/platform/chrome/Kconfig b/drivers/platform/chrome/Kconfig
index cf072153bdc5d..88b1b7b277ba3 100644
--- a/drivers/platform/chrome/Kconfig
+++ b/drivers/platform/chrome/Kconfig
@@ -118,6 +118,16 @@ config CROS_EC_SPI
response time cannot be guaranteed, we support ignoring
'pre-amble' bytes before the response actually starts.
+config CROS_EC_UART
+ tristate "ChromeOS Embedded Controller (UART)"
+ depends on CROS_EC && ACPI && SERIAL_DEV_BUS
+ help
+ If you say Y here, you get support for talking to the ChromeOS EC
+ through a UART, using a byte-level protocol.
+
+ To compile this driver as a module, choose M here: the
+ module will be called cros_ec_uart.
+
config CROS_EC_LPC
tristate "ChromeOS Embedded Controller (LPC)"
depends on CROS_EC && ACPI && (X86 || COMPILE_TEST)
diff --git a/drivers/platform/chrome/Makefile b/drivers/platform/chrome/Makefile
index 41baccba033f7..47d8d0f890ca2 100644
--- a/drivers/platform/chrome/Makefile
+++ b/drivers/platform/chrome/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_CROS_EC_I2C) += cros_ec_i2c.o
obj-$(CONFIG_CROS_EC_ISHTP)+= cros_ec_ishtp.o
obj-$(CONFIG_CROS_EC_RPMSG)+= cros_ec_rpmsg.o
obj-$(CONFIG_CROS_EC_SPI) += cros_ec_spi.o
+obj-$(CONFIG_CROS_EC_UART) += cros_ec_uart.o
cros_ec_lpcs-objs := cros_ec_lpc.o cros_ec_lpc_mec.o
obj-$(CONFIG_CROS_EC_TYPEC)+= cros_ec_typec.o
obj-$(CONFIG_CROS_EC_LPC) += cros_ec_lpcs.o
diff --git a/drivers/platform/chrome/cros_ec_uart.c
b/drivers/platform/chrome/cros_ec_uart.c
new file mode 100644
index 0..fe17c2a28b6ef
--- /dev/null
+++ b/drivers/platform/chrome/cros_ec_uart.c
@@ -0,0 +1,399 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * UART interface for ChromeOS Embedded Controller
+ *
+ * Copyright 2020 Google LLC.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/*
+ * Allow for a long time for EC to respond.
+ */
+#define EC_MSG_DEADLINE_MS 200
+
+/**
+ * struct response_info - Encapsulate EC response related
+ * information for passing between function
+ * cros_ec_uart_pkt_xfer() and cros_ec_uart_rx_bytes()
+ * callback.
+ * @data: Copy the data received from EC here.
+ * @max_size: Max size allocated for the @data buffer. If the
+ * received data exceeds this value, we log an error.
+ * @size: Actual size of data received from EC. This is also
+ * used to accumulate byte count with response is received
+ * in dma chunks.
+ * @exp_len: Expected bytes of response from EC.
+ * @error: 0 for success, negative error code for a failure.
+ * @received: Set to true on receiving a valid EC response.
+ * @wait_queue:Wait queue EC response where the cros_ec sends
request
+ * to EC and waits
+ */
+struct response_info {
+ void *data;
+ size_t max_size;
+ size_t size;
+ int error;
+ size_t exp_len;
+ bool received;
+ wait_queue_head_t wait_queue;
+};
+
+/**
+ * struct cros_ec_uart - information about a uart-connected EC
+ *
+ * @serdev_device: serdev uart device we are connected to.
+ * @baudrate: UART baudrate of attached EC device.
+ * @flowcontrol: UART flowcontrol of attached device.
+ * @irq: Linux IRQ number of associated serial device.
+ * @response: Response info passing between cros_ec_uart_pkt_xfer()
+ * and cros_ec_uart_rx_bytes()
+ */
+struct cros_ec_uart {
+ struct serdev_device *serdev;
+ u32 baudrate;
+ u8 flowcontrol;
+ u32 irq;
+ struct response_info response;
+};
+
+static in
[PATCH 2/2] dt-bindings: mfd: Add DT compatible string "google,cros_ec_uart"
Add DT compatible string in
Documentation/devicetree/bindings/mfd/cros_ec.txt
Signed-off-by: Bhanu Prakash Maiya
---
Documentation/devicetree/bindings/mfd/cros-ec.txt | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/mfd/cros-ec.txt
b/Documentation/devicetree/bindings/mfd/cros-ec.txt
index 4860eabd0f729..ec8c5d7ecc266 100644
--- a/Documentation/devicetree/bindings/mfd/cros-ec.txt
+++ b/Documentation/devicetree/bindings/mfd/cros-ec.txt
@@ -3,7 +3,7 @@ ChromeOS Embedded Controller
Google's ChromeOS EC is a Cortex-M device which talks to the AP and
implements various function such as keyboard and battery charging.
-The EC can be connect through various means (I2C, SPI, LPC, RPMSG) and the
+The EC can be connect through various means (I2C, SPI, UART, LPC, RPMSG) and
the
compatible string used depends on the interface. Each connection method has
its own driver which connects to the top level interface-agnostic EC driver.
Other Linux driver (such as cros-ec-keyb for the matrix keyboard) connect to
@@ -17,6 +17,10 @@ Required properties (SPI):
- compatible: "google,cros-ec-spi"
- reg: SPI chip select
+Required properties (UART):
+- compatible: "google,cros-ec-uart"
+- reg: UART baudrate, flowcontrol
+
Required properties (RPMSG):
- compatible: "google,cros-ec-rpmsg"
@@ -72,5 +76,6 @@ spi@131b {
};
};
-
Example for LPC is not supplied as it is not yet implemented.
+
+Example for UART is not supplied as it is not yet implemented.
--
2.26.2
