Re: [PATCH v4] arm64: dts: add all hi6220 i2c nodes
On 2015/12/2 18:13, Xinwei Kong wrote:
This patch adds all I2C nodes for the Hi6220 SoC. This hi6220 Soc
use this I2C IP of Synopsys Designware for HiKey board.
Signed-off-by: Xinwei Kong
Signed-off-by: Chen Feng
---
arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 34 +++
1 file changed, 34 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
index 82d2488..8cec56a 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -208,5 +208,39 @@
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
+
+ i2c0: i2c@f710 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0xf710 0x0 0x1000>;
+ interrupts = <0 44 4>;
+ clocks = <_ctrl HI6220_I2C0_CLK>;
+ i2c-sda-hold-time-ns = <300>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pmx_func _cfg_func>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@f7101000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0xf7101000 0x0 0x1000>;
+ clocks = <_ctrl HI6220_I2C1_CLK>;
+ interrupts = <0 45 4>;
+ i2c-sda-hold-time-ns = <300>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pmx_func _cfg_func>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@f7102000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0xf7102000 0x0 0x1000>;
+ clocks = <_ctrl HI6220_I2C2_CLK>;
+ interrupts = <0 46 4>;
+ i2c-sda-hold-time-ns = <300>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pmx_func _cfg_func>;
+ status = "disabled";
+ };
+
};
};
Looks good to me!
Reviewed-by: Bintian Wang
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v4] arm64: dts: add all hi6220 i2c nodes
On 2015/12/2 18:13, Xinwei Kong wrote:
This patch adds all I2C nodes for the Hi6220 SoC. This hi6220 Soc
use this I2C IP of Synopsys Designware for HiKey board.
Signed-off-by: Xinwei Kong <kong.kongxin...@hisilicon.com>
Signed-off-by: Chen Feng <puck.c...@hisilicon.com>
---
arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 34 +++
1 file changed, 34 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
index 82d2488..8cec56a 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -208,5 +208,39 @@
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
+
+ i2c0: i2c@f710 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0xf710 0x0 0x1000>;
+ interrupts = <0 44 4>;
+ clocks = <_ctrl HI6220_I2C0_CLK>;
+ i2c-sda-hold-time-ns = <300>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pmx_func _cfg_func>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@f7101000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0xf7101000 0x0 0x1000>;
+ clocks = <_ctrl HI6220_I2C1_CLK>;
+ interrupts = <0 45 4>;
+ i2c-sda-hold-time-ns = <300>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pmx_func _cfg_func>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@f7102000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0xf7102000 0x0 0x1000>;
+ clocks = <_ctrl HI6220_I2C2_CLK>;
+ interrupts = <0 46 4>;
+ i2c-sda-hold-time-ns = <300>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pmx_func _cfg_func>;
+ status = "disabled";
+ };
+
};
};
Looks good to me!
Reviewed-by: Bintian Wang<bintian.w...@huawei.com>
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH RESEND net-next 3/3] arm64: hip05-d02: Document devicetree bindings for Hisilicon D02 Board
On 2015/12/7 21:16, Rob Herring wrote:
On Sat, Dec 05, 2015 at 03:54:48PM +0800, yankejian wrote:
This patch adds documentation for the devicetree bindings used by the
DT files of Hisilicon Hip05-D02 development board.
Signed-off-by: yankejian
You may need to configure as "Kejian Yan " :)
BR,
Bintian
---
.../devicetree/bindings/arm/hisilicon/hisilicon.txt | 16
1 file changed, 16 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
index 6ac7c00..5318d78 100644
--- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
+++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
@@ -187,6 +187,22 @@ Example:
reg = <0xb000 0x1>;
};
+Hisilicon HiP05 PERISUB system controller
+
+Required properties:
+- compatible : "hisilicon,peri-c-subctrl", "syscon";
This should be more specific and have the SOC name in it.
+- reg : Register address and size
+
+The HiP05 PERISUB system controller is shared by peripheral controllers in
+HiP05 Soc to implement some basic configurations. the peripheral
+ controllers include mdio, ddr, iic, uart, timer and so on.
+
+Example:
+ /* for HiP05 PCIe-SAS system */
+ pcie_sas: system_controller@0xb000 {
+ compatible = "hisilicon,pcie-sas-subctrl", "syscon";
The example doesn't match.
+ reg = <0xb000 0x1>;
+ };
---
Hisilicon CPU controller
--
1.9.1
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
.
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH RESEND net-next 3/3] arm64: hip05-d02: Document devicetree bindings for Hisilicon D02 Board
On 2015/12/7 21:16, Rob Herring wrote:
On Sat, Dec 05, 2015 at 03:54:48PM +0800, yankejian wrote:
This patch adds documentation for the devicetree bindings used by the
DT files of Hisilicon Hip05-D02 development board.
Signed-off-by: yankejian <yankej...@huawei.com>
You may need to configure as "Kejian Yan <yankej...@huawei.com>" :)
BR,
Bintian
---
.../devicetree/bindings/arm/hisilicon/hisilicon.txt | 16
1 file changed, 16 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
index 6ac7c00..5318d78 100644
--- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
+++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
@@ -187,6 +187,22 @@ Example:
reg = <0xb000 0x1>;
};
+Hisilicon HiP05 PERISUB system controller
+
+Required properties:
+- compatible : "hisilicon,peri-c-subctrl", "syscon";
This should be more specific and have the SOC name in it.
+- reg : Register address and size
+
+The HiP05 PERISUB system controller is shared by peripheral controllers in
+HiP05 Soc to implement some basic configurations. the peripheral
+ controllers include mdio, ddr, iic, uart, timer and so on.
+
+Example:
+ /* for HiP05 PCIe-SAS system */
+ pcie_sas: system_controller@0xb000 {
+ compatible = "hisilicon,pcie-sas-subctrl", "syscon";
The example doesn't match.
+ reg = <0xb000 0x1>;
+ };
---
Hisilicon CPU controller
--
1.9.1
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
.
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] amba: Support clk parents and rates assigned in DT
On 2015/7/7 17:33, Russell King - ARM Linux wrote: On Tue, Jul 07, 2015 at 04:47:33PM +0800, Bintian wrote: Hi Russell, Could you spend several minutes to review Stephen's patch? Sorry, I'm busy this week, I need to sort out my git tree, get some fixes out which should've been pushed during the merge window, and other stuff. I'm not going to have much time to read email, let alone do reviews. Please be patient. No problem, just keep your own pace. Thanks, Bintian -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] amba: Support clk parents and rates assigned in DT
Hi Russell, Could you spend several minutes to review Stephen's patch? Thanks, Bintian On 2015/7/7 7:57, Stephen Boyd wrote: On 05/28/2015 01:52 PM, Stephen Boyd wrote: Add the call to of_clk_set_defaults() into the amba probe path so that devices on the amba bus can use the assigned rates and parents feature of the common clock framework. Signed-off-by: Stephen Boyd --- Shall I put this into the patch tracker? Turns out it wasn't needed for the hisi stuff immediately. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] amba: Support clk parents and rates assigned in DT
Hi Russell, Could you spend several minutes to review Stephen's patch? Thanks, Bintian On 2015/7/7 7:57, Stephen Boyd wrote: On 05/28/2015 01:52 PM, Stephen Boyd wrote: Add the call to of_clk_set_defaults() into the amba probe path so that devices on the amba bus can use the assigned rates and parents feature of the common clock framework. Signed-off-by: Stephen Boyd sb...@codeaurora.org --- Shall I put this into the patch tracker? Turns out it wasn't needed for the hisi stuff immediately. -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] amba: Support clk parents and rates assigned in DT
On 2015/7/7 17:33, Russell King - ARM Linux wrote: On Tue, Jul 07, 2015 at 04:47:33PM +0800, Bintian wrote: Hi Russell, Could you spend several minutes to review Stephen's patch? Sorry, I'm busy this week, I need to sort out my git tree, get some fixes out which should've been pushed during the merge window, and other stuff. I'm not going to have much time to read email, let alone do reviews. Please be patient. No problem, just keep your own pace. Thanks, Bintian -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v9 5/6] arm64: dts: Add dts files for Hisilicon Hi6220 SoC
Hello Arnd, Hello Olof, Hello Kevin,
I checked the git log of Linux 4.1-rc7 from Linus, he says Linux 4.1
will have an rc8, so we may have time to review the following two pull
requests from Wei Xu?
[GIT PULL v2]Hisilicon 64-bit SoC changes for 4.2
[GIT PULL]Hisilicon 64-bit soc hi6220 DT changes for 4.2
Thanks for your time.
BR,
Bintian
On 2015/6/9 9:39, Bintian wrote:
Hello Shawn,
On 2015/6/9 8:55, Shawn Guo wrote:
A minor random comment below.
On Sat, May 30, 2015 at 09:51:00AM +0800, Bintian Wang wrote:
+ao_ctrl: ao_ctrl {
+compatible = "hisilicon,hi6220-aoctrl", "syscon";
+reg = <0x0 0xf780 0x0 0x2000>;
+#clock-cells = <1>;
+};
+
+sys_ctrl: sys_ctrl {
+compatible = "hisilicon,hi6220-sysctrl", "syscon";
+reg = <0x0 0xf703 0x0 0x2000>;
+#clock-cells = <1>;
+};
+
+media_ctrl: media_ctrl {
+compatible = "hisilicon,hi6220-mediactrl", "syscon";
+reg = <0x0 0xf441 0x0 0x1000>;
+#clock-cells = <1>;
+};
+
+pm_ctrl: pm_ctrl {
An unit-address should be coded in the node name, when it has a 'reg'
property.
Thanks for your suggestion, Rob also gives me the same suggestion :)
In fact, I added the reg to node name in the "[GIT PULL]Hisilicon 64-bit
soc hi6220 DT changes for 4.2", but it seems the pull is too late for
kernel 4.2, I will prepare it for 4.3.
Thanks,
Bintian
Shawn
+compatible = "hisilicon,hi6220-pmctrl", "syscon";
+reg = <0x0 0xf7032000 0x0 0x1000>;
+#clock-cells = <1>;
+};
.
.
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v9 5/6] arm64: dts: Add dts files for Hisilicon Hi6220 SoC
Hello Shawn,
On 2015/6/9 8:55, Shawn Guo wrote:
A minor random comment below.
On Sat, May 30, 2015 at 09:51:00AM +0800, Bintian Wang wrote:
+ ao_ctrl: ao_ctrl {
+ compatible = "hisilicon,hi6220-aoctrl", "syscon";
+ reg = <0x0 0xf780 0x0 0x2000>;
+ #clock-cells = <1>;
+ };
+
+ sys_ctrl: sys_ctrl {
+ compatible = "hisilicon,hi6220-sysctrl", "syscon";
+ reg = <0x0 0xf703 0x0 0x2000>;
+ #clock-cells = <1>;
+ };
+
+ media_ctrl: media_ctrl {
+ compatible = "hisilicon,hi6220-mediactrl", "syscon";
+ reg = <0x0 0xf441 0x0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ pm_ctrl: pm_ctrl {
An unit-address should be coded in the node name, when it has a 'reg'
property.
Thanks for your suggestion, Rob also gives me the same suggestion :)
In fact, I added the reg to node name in the "[GIT PULL]Hisilicon 64-bit
soc hi6220 DT changes for 4.2", but it seems the pull is too late for
kernel 4.2, I will prepare it for 4.3.
Thanks,
Bintian
Shawn
+ compatible = "hisilicon,hi6220-pmctrl", "syscon";
+ reg = <0x0 0xf7032000 0x0 0x1000>;
+ #clock-cells = <1>;
+ };
.
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v9 5/6] arm64: dts: Add dts files for Hisilicon Hi6220 SoC
Hello Arnd, Hello Olof, Hello Kevin,
I checked the git log of Linux 4.1-rc7 from Linus, he says Linux 4.1
will have an rc8, so we may have time to review the following two pull
requests from Wei Xu?
[GIT PULL v2]Hisilicon 64-bit SoC changes for 4.2
[GIT PULL]Hisilicon 64-bit soc hi6220 DT changes for 4.2
Thanks for your time.
BR,
Bintian
On 2015/6/9 9:39, Bintian wrote:
Hello Shawn,
On 2015/6/9 8:55, Shawn Guo wrote:
A minor random comment below.
On Sat, May 30, 2015 at 09:51:00AM +0800, Bintian Wang wrote:
+ao_ctrl: ao_ctrl {
+compatible = hisilicon,hi6220-aoctrl, syscon;
+reg = 0x0 0xf780 0x0 0x2000;
+#clock-cells = 1;
+};
+
+sys_ctrl: sys_ctrl {
+compatible = hisilicon,hi6220-sysctrl, syscon;
+reg = 0x0 0xf703 0x0 0x2000;
+#clock-cells = 1;
+};
+
+media_ctrl: media_ctrl {
+compatible = hisilicon,hi6220-mediactrl, syscon;
+reg = 0x0 0xf441 0x0 0x1000;
+#clock-cells = 1;
+};
+
+pm_ctrl: pm_ctrl {
An unit-address should be coded in the node name, when it has a 'reg'
property.
Thanks for your suggestion, Rob also gives me the same suggestion :)
In fact, I added the reg to node name in the [GIT PULL]Hisilicon 64-bit
soc hi6220 DT changes for 4.2, but it seems the pull is too late for
kernel 4.2, I will prepare it for 4.3.
Thanks,
Bintian
Shawn
+compatible = hisilicon,hi6220-pmctrl, syscon;
+reg = 0x0 0xf7032000 0x0 0x1000;
+#clock-cells = 1;
+};
.
.
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v9 5/6] arm64: dts: Add dts files for Hisilicon Hi6220 SoC
Hello Shawn,
On 2015/6/9 8:55, Shawn Guo wrote:
A minor random comment below.
On Sat, May 30, 2015 at 09:51:00AM +0800, Bintian Wang wrote:
+ ao_ctrl: ao_ctrl {
+ compatible = hisilicon,hi6220-aoctrl, syscon;
+ reg = 0x0 0xf780 0x0 0x2000;
+ #clock-cells = 1;
+ };
+
+ sys_ctrl: sys_ctrl {
+ compatible = hisilicon,hi6220-sysctrl, syscon;
+ reg = 0x0 0xf703 0x0 0x2000;
+ #clock-cells = 1;
+ };
+
+ media_ctrl: media_ctrl {
+ compatible = hisilicon,hi6220-mediactrl, syscon;
+ reg = 0x0 0xf441 0x0 0x1000;
+ #clock-cells = 1;
+ };
+
+ pm_ctrl: pm_ctrl {
An unit-address should be coded in the node name, when it has a 'reg'
property.
Thanks for your suggestion, Rob also gives me the same suggestion :)
In fact, I added the reg to node name in the [GIT PULL]Hisilicon 64-bit
soc hi6220 DT changes for 4.2, but it seems the pull is too late for
kernel 4.2, I will prepare it for 4.3.
Thanks,
Bintian
Shawn
+ compatible = hisilicon,hi6220-pmctrl, syscon;
+ reg = 0x0 0xf7032000 0x0 0x1000;
+ #clock-cells = 1;
+ };
.
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v9 2/6] arm64: hi6220: Document devicetree bindings for Hisilicon hi6220 SoC
On 2015/6/4 12:36, Rob Herring wrote:
On Fri, May 29, 2015 at 8:50 PM, Bintian Wang wrote:
This patch adds documentation for the devicetree bindings used by the
DT files of Hisilicon hi6220 SoC mobile platform.
Signed-off-by: Bintian Wang
Suggested-by: Arnd Bergmann
Acked-by: Haojian Zhuang
Acked-by: Stephen Boyd
Acked-by: Rob Herring
One minor comment below.
Thank you Rob, I will fix in version 10.
BR,
Bintian
---
.../bindings/arm/hisilicon/hisilicon.txt | 87
1 file changed, 87 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
index 35b1bd4..f67d0f3 100644
--- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
+++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
@@ -1,5 +1,8 @@
Hisilicon Platforms Device Tree Bindings
+Hi6220 SoC
+Required root node properties:
+ - compatible = "hisilicon,hi6220";
Hi4511 Board
Required root node properties:
@@ -13,6 +16,9 @@ HiP01 ca9x2 Board
Required root node properties:
- compatible = "hisilicon,hip01-ca9x2";
+HiKey Board
+Required root node properties:
+ - compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220";
Hisilicon system controller
@@ -41,6 +47,87 @@ Example:
};
---
+Hisilicon Hi6220 system controller
+
+Required properties:
+- compatible : "hisilicon,hi6220-sysctrl"
+- reg : Register address and size
+- #clock-cells: should be set to 1, many clock registers are defined
+ under this controller and this property must be present.
+
+Hisilicon designs this controller as one of the system controllers,
+its main functions are the same as Hisilicon system controller, but
+the register offset of some core modules are different.
+
+Example:
+ /*for Hi6220*/
+ sys_ctrl: sys_ctrl {
You should have the unit address in the name here. Same with the
follow examples.
+ compatible = "hisilicon,hi6220-sysctrl", "syscon";
+ reg = <0x0 0xf703 0x0 0x2000>;
+ #clock-cells = <1>;
+ };
+
+
+Hisilicon Hi6220 Power Always ON domain controller
+
+Required properties:
+- compatible : "hisilicon,hi6220-aoctrl"
+- reg : Register address and size
+- #clock-cells: should be set to 1, many clock registers are defined
+ under this controller and this property must be present.
+
+Hisilicon designs this system controller to control the power always
+on domain for mobile platform.
+
+Example:
+ /*for Hi6220*/
+ ao_ctrl: ao_ctrl {
+ compatible = "hisilicon,hi6220-aoctrl", "syscon";
+ reg = <0x0 0xf780 0x0 0x2000>;
+ #clock-cells = <1>;
+ };
+
+
+Hisilicon Hi6220 Media domain controller
+
+Required properties:
+- compatible : "hisilicon,hi6220-mediactrl"
+- reg : Register address and size
+- #clock-cells: should be set to 1, many clock registers are defined
+ under this controller and this property must be present.
+
+Hisilicon designs this system controller to control the multimedia
+domain(e.g. codec, G3D ...) for mobile platform.
+
+Example:
+ /*for Hi6220*/
+ media_ctrl: media_ctrl {
+ compatible = "hisilicon,hi6220-mediactrl", "syscon";
+ reg = <0x0 0xf441 0x0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+
+Hisilicon Hi6220 Power Management domain controller
+
+Required properties:
+- compatible : "hisilicon,hi6220-pmctrl"
+- reg : Register address and size
+- #clock-cells: should be set to 1, some clock registers are define
+ under this controller and this property must be present.
+
+Hisilicon designs this system controller to control the power management
+domain for mobile platform.
+
+Example:
+ /*for Hi6220*/
+ pm_ctrl: pm_ctrl {
+ compatible = "hisilicon,hi6220-pmctrl", "syscon";
+ reg = <0x0 0xf7032000 0x0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+---
Hisilicon HiP01 system controller
Required properties:
--
1.7.9.5
.
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v9 2/6] arm64: hi6220: Document devicetree bindings for Hisilicon hi6220 SoC
On 2015/6/4 12:36, Rob Herring wrote:
On Fri, May 29, 2015 at 8:50 PM, Bintian Wang bintian.w...@huawei.com wrote:
This patch adds documentation for the devicetree bindings used by the
DT files of Hisilicon hi6220 SoC mobile platform.
Signed-off-by: Bintian Wang bintian.w...@huawei.com
Suggested-by: Arnd Bergmann a...@arndb.de
Acked-by: Haojian Zhuang haojian.zhu...@linaro.org
Acked-by: Stephen Boyd sb...@codeaurora.org
Acked-by: Rob Herring r...@kernel.org
One minor comment below.
Thank you Rob, I will fix in version 10.
BR,
Bintian
---
.../bindings/arm/hisilicon/hisilicon.txt | 87
1 file changed, 87 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
index 35b1bd4..f67d0f3 100644
--- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
+++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
@@ -1,5 +1,8 @@
Hisilicon Platforms Device Tree Bindings
+Hi6220 SoC
+Required root node properties:
+ - compatible = hisilicon,hi6220;
Hi4511 Board
Required root node properties:
@@ -13,6 +16,9 @@ HiP01 ca9x2 Board
Required root node properties:
- compatible = hisilicon,hip01-ca9x2;
+HiKey Board
+Required root node properties:
+ - compatible = hisilicon,hi6220-hikey, hisilicon,hi6220;
Hisilicon system controller
@@ -41,6 +47,87 @@ Example:
};
---
+Hisilicon Hi6220 system controller
+
+Required properties:
+- compatible : hisilicon,hi6220-sysctrl
+- reg : Register address and size
+- #clock-cells: should be set to 1, many clock registers are defined
+ under this controller and this property must be present.
+
+Hisilicon designs this controller as one of the system controllers,
+its main functions are the same as Hisilicon system controller, but
+the register offset of some core modules are different.
+
+Example:
+ /*for Hi6220*/
+ sys_ctrl: sys_ctrl {
You should have the unit address in the name here. Same with the
follow examples.
+ compatible = hisilicon,hi6220-sysctrl, syscon;
+ reg = 0x0 0xf703 0x0 0x2000;
+ #clock-cells = 1;
+ };
+
+
+Hisilicon Hi6220 Power Always ON domain controller
+
+Required properties:
+- compatible : hisilicon,hi6220-aoctrl
+- reg : Register address and size
+- #clock-cells: should be set to 1, many clock registers are defined
+ under this controller and this property must be present.
+
+Hisilicon designs this system controller to control the power always
+on domain for mobile platform.
+
+Example:
+ /*for Hi6220*/
+ ao_ctrl: ao_ctrl {
+ compatible = hisilicon,hi6220-aoctrl, syscon;
+ reg = 0x0 0xf780 0x0 0x2000;
+ #clock-cells = 1;
+ };
+
+
+Hisilicon Hi6220 Media domain controller
+
+Required properties:
+- compatible : hisilicon,hi6220-mediactrl
+- reg : Register address and size
+- #clock-cells: should be set to 1, many clock registers are defined
+ under this controller and this property must be present.
+
+Hisilicon designs this system controller to control the multimedia
+domain(e.g. codec, G3D ...) for mobile platform.
+
+Example:
+ /*for Hi6220*/
+ media_ctrl: media_ctrl {
+ compatible = hisilicon,hi6220-mediactrl, syscon;
+ reg = 0x0 0xf441 0x0 0x1000;
+ #clock-cells = 1;
+ };
+
+
+Hisilicon Hi6220 Power Management domain controller
+
+Required properties:
+- compatible : hisilicon,hi6220-pmctrl
+- reg : Register address and size
+- #clock-cells: should be set to 1, some clock registers are define
+ under this controller and this property must be present.
+
+Hisilicon designs this system controller to control the power management
+domain for mobile platform.
+
+Example:
+ /*for Hi6220*/
+ pm_ctrl: pm_ctrl {
+ compatible = hisilicon,hi6220-pmctrl, syscon;
+ reg = 0x0 0xf7032000 0x0 0x1000;
+ #clock-cells = 1;
+ };
+
+---
Hisilicon HiP01 system controller
Required properties:
--
1.7.9.5
.
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v8 6/7] clk: hi6220: Clock driver support for Hisilicon hi6220 SoC
On 2015/6/4 6:39, Michael Turquette wrote:
Quoting Bintian Wang (2015-05-28 19:08:38)
Add clock drivers for hi6220 SoC, this driver controls the SoC
registers to supply different clocks to different IPs in the SoC.
We add one divider clock for hi6220 because the divider in hi6220
also has a mask bit but it doesnot obey the rule defined by flag
"CLK_DIVIDER_HIWORD_MASK", we can not get index of the mask bit by
left shift fixed bits (e.g. 16 bits), so we add this divider clock
to handle it.
Signed-off-by: Jorge Ramirez-Ortiz
Signed-off-by: Bintian Wang
Acked-by: Haojian Zhuang
Reviewed-by: Zhangfei Gao
Tested-by: Will Deacon
Tested-by: Tyler Baker
Tested-by: Kevin Hilman
I've applied patches #4-6 to the clk tree.
Thank you Mike.
Best Regards,
Bintian
Regards,
Mike
---
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile | 4 +-
drivers/clk/hisilicon/Kconfig | 6 +
drivers/clk/hisilicon/Makefile| 3 +-
drivers/clk/hisilicon/clk-hi6220.c| 284 ++
drivers/clk/hisilicon/clk.c | 29 +++
drivers/clk/hisilicon/clk.h | 17 ++
drivers/clk/hisilicon/clkdivider-hi6220.c | 156
8 files changed, 496 insertions(+), 4 deletions(-)
create mode 100644 drivers/clk/hisilicon/Kconfig
create mode 100644 drivers/clk/hisilicon/clk-hi6220.c
create mode 100644 drivers/clk/hisilicon/clkdivider-hi6220.c
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index de8c58f..cd6029d4 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -151,6 +151,7 @@ config COMMON_CLK_CDCE706
This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
source "drivers/clk/bcm/Kconfig"
+source "drivers/clk/hisilicon/Kconfig"
source "drivers/clk/qcom/Kconfig"
endmenu
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index d2d5e6c..440ef72 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -47,9 +47,7 @@ obj-$(CONFIG_COMMON_CLK_PWM) += clk-pwm.o
obj-$(CONFIG_COMMON_CLK_AT91) += at91/
obj-$(CONFIG_ARCH_BCM_MOBILE) += bcm/
obj-$(CONFIG_ARCH_BERLIN) += berlin/
-obj-$(CONFIG_ARCH_HI3xxx) += hisilicon/
-obj-$(CONFIG_ARCH_HIP04) += hisilicon/
-obj-$(CONFIG_ARCH_HIX5HD2) += hisilicon/
+obj-$(CONFIG_ARCH_HISI)+= hisilicon/
obj-$(CONFIG_ARCH_MXC) += imx/
obj-$(CONFIG_COMMON_CLK_KEYSTONE) += keystone/
obj-$(CONFIG_ARCH_MEDIATEK)+= mediatek/
diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
new file mode 100644
index 000..b4165ba
--- /dev/null
+++ b/drivers/clk/hisilicon/Kconfig
@@ -0,0 +1,6 @@
+config COMMON_CLK_HI6220
+ bool "Hi6220 Clock Driver"
+ depends on ARCH_HISI || COMPILE_TEST
+ default ARCH_HISI
+ help
+ Build the Hisilicon Hi6220 clock driver based on the common clock
framework.
diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile
index 038c02f..48f0116 100644
--- a/drivers/clk/hisilicon/Makefile
+++ b/drivers/clk/hisilicon/Makefile
@@ -2,8 +2,9 @@
# Hisilicon Clock specific Makefile
#
-obj-y += clk.o clkgate-separated.o
+obj-y += clk.o clkgate-separated.o clkdivider-hi6220.o
obj-$(CONFIG_ARCH_HI3xxx) += clk-hi3620.o
obj-$(CONFIG_ARCH_HIP04) += clk-hip04.o
obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o
+obj-$(CONFIG_COMMON_CLK_HI6220)+= clk-hi6220.o
diff --git a/drivers/clk/hisilicon/clk-hi6220.c
b/drivers/clk/hisilicon/clk-hi6220.c
new file mode 100644
index 000..4563343
--- /dev/null
+++ b/drivers/clk/hisilicon/clk-hi6220.c
@@ -0,0 +1,284 @@
+/*
+ * Hisilicon Hi6220 clock driver
+ *
+ * Copyright (c) 2015 Hisilicon Limited.
+ *
+ * Author: Bintian Wang
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include "clk.h"
+
+
+/* clocks in AO (always on) controller */
+static struct hisi_fixed_rate_clock hi6220_fixed_rate_clks[] __initdata = {
+ { HI6220_REF32K,"ref32k", NULL, CLK_IS_ROOT, 32764, },
+ { HI6220_CLK_TCXO, "clk_tcxo", NULL, CLK_IS_ROOT, 1920, },
+ { HI6220_MMC1_PAD, "mmc1_pad", NULL, CLK_IS_ROOT, 1, },
+ { HI6220_MMC2_PAD, "mmc2_pad", NULL, CLK_IS_ROOT, 1, },
+ { HI6220_MMC0_PAD, "mmc0_pad", NULL, CLK_IS_ROOT, 2, },
+ { HI6220_PLL_BBP, "bbppll0", NULL, CLK_IS_ROOT, 24576, },
+ { HI6220_PLL_GPU, "
Re: [PATCH v8 6/7] clk: hi6220: Clock driver support for Hisilicon hi6220 SoC
On 2015/6/4 6:39, Michael Turquette wrote:
Quoting Bintian Wang (2015-05-28 19:08:38)
Add clock drivers for hi6220 SoC, this driver controls the SoC
registers to supply different clocks to different IPs in the SoC.
We add one divider clock for hi6220 because the divider in hi6220
also has a mask bit but it doesnot obey the rule defined by flag
CLK_DIVIDER_HIWORD_MASK, we can not get index of the mask bit by
left shift fixed bits (e.g. 16 bits), so we add this divider clock
to handle it.
Signed-off-by: Jorge Ramirez-Ortiz jorge.ramirez-or...@linaro.org
Signed-off-by: Bintian Wang bintian.w...@huawei.com
Acked-by: Haojian Zhuang haojian.zhu...@linaro.org
Reviewed-by: Zhangfei Gao zhangfei@linaro.org
Tested-by: Will Deacon will.dea...@arm.com
Tested-by: Tyler Baker tyler.ba...@linaro.org
Tested-by: Kevin Hilman khil...@linaro.org
I've applied patches #4-6 to the clk tree.
Thank you Mike.
Best Regards,
Bintian
Regards,
Mike
---
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile | 4 +-
drivers/clk/hisilicon/Kconfig | 6 +
drivers/clk/hisilicon/Makefile| 3 +-
drivers/clk/hisilicon/clk-hi6220.c| 284 ++
drivers/clk/hisilicon/clk.c | 29 +++
drivers/clk/hisilicon/clk.h | 17 ++
drivers/clk/hisilicon/clkdivider-hi6220.c | 156
8 files changed, 496 insertions(+), 4 deletions(-)
create mode 100644 drivers/clk/hisilicon/Kconfig
create mode 100644 drivers/clk/hisilicon/clk-hi6220.c
create mode 100644 drivers/clk/hisilicon/clkdivider-hi6220.c
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index de8c58f..cd6029d4 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -151,6 +151,7 @@ config COMMON_CLK_CDCE706
This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
source drivers/clk/bcm/Kconfig
+source drivers/clk/hisilicon/Kconfig
source drivers/clk/qcom/Kconfig
endmenu
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index d2d5e6c..440ef72 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -47,9 +47,7 @@ obj-$(CONFIG_COMMON_CLK_PWM) += clk-pwm.o
obj-$(CONFIG_COMMON_CLK_AT91) += at91/
obj-$(CONFIG_ARCH_BCM_MOBILE) += bcm/
obj-$(CONFIG_ARCH_BERLIN) += berlin/
-obj-$(CONFIG_ARCH_HI3xxx) += hisilicon/
-obj-$(CONFIG_ARCH_HIP04) += hisilicon/
-obj-$(CONFIG_ARCH_HIX5HD2) += hisilicon/
+obj-$(CONFIG_ARCH_HISI)+= hisilicon/
obj-$(CONFIG_ARCH_MXC) += imx/
obj-$(CONFIG_COMMON_CLK_KEYSTONE) += keystone/
obj-$(CONFIG_ARCH_MEDIATEK)+= mediatek/
diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
new file mode 100644
index 000..b4165ba
--- /dev/null
+++ b/drivers/clk/hisilicon/Kconfig
@@ -0,0 +1,6 @@
+config COMMON_CLK_HI6220
+ bool Hi6220 Clock Driver
+ depends on ARCH_HISI || COMPILE_TEST
+ default ARCH_HISI
+ help
+ Build the Hisilicon Hi6220 clock driver based on the common clock
framework.
diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile
index 038c02f..48f0116 100644
--- a/drivers/clk/hisilicon/Makefile
+++ b/drivers/clk/hisilicon/Makefile
@@ -2,8 +2,9 @@
# Hisilicon Clock specific Makefile
#
-obj-y += clk.o clkgate-separated.o
+obj-y += clk.o clkgate-separated.o clkdivider-hi6220.o
obj-$(CONFIG_ARCH_HI3xxx) += clk-hi3620.o
obj-$(CONFIG_ARCH_HIP04) += clk-hip04.o
obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o
+obj-$(CONFIG_COMMON_CLK_HI6220)+= clk-hi6220.o
diff --git a/drivers/clk/hisilicon/clk-hi6220.c
b/drivers/clk/hisilicon/clk-hi6220.c
new file mode 100644
index 000..4563343
--- /dev/null
+++ b/drivers/clk/hisilicon/clk-hi6220.c
@@ -0,0 +1,284 @@
+/*
+ * Hisilicon Hi6220 clock driver
+ *
+ * Copyright (c) 2015 Hisilicon Limited.
+ *
+ * Author: Bintian Wang bintian.w...@huawei.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/kernel.h
+#include linux/clk-provider.h
+#include linux/clkdev.h
+#include linux/io.h
+#include linux/of.h
+#include linux/of_address.h
+#include linux/of_device.h
+#include linux/slab.h
+
+#include dt-bindings/clock/hi6220-clock.h
+
+#include clk.h
+
+
+/* clocks in AO (always on) controller */
+static struct hisi_fixed_rate_clock hi6220_fixed_rate_clks[] __initdata = {
+ { HI6220_REF32K,ref32k, NULL, CLK_IS_ROOT, 32764, },
+ { HI6220_CLK_TCXO, clk_tcxo, NULL, CLK_IS_ROOT, 1920, },
+ { HI6220_MMC1_PAD, mmc1_pad, NULL, CLK_IS_ROOT, 1, },
+ { HI6220_MMC2_PAD, mmc2_pad, NULL, CLK_IS_ROOT, 1, },
+ { HI6220_MMC0_PAD
Re: [PATCH v9 5/6] arm64: dts: Add dts files for Hisilicon Hi6220 SoC
Hello Mark, Rob and other ARM64 DT maintainers,
Could you help to ack this patch?
Thanks for your time.
Bintian
On 2015/5/30 9:51, Bintian Wang wrote:
Add initial dtsi file to support Hisilicon Hi6220 SoC with
support of Octal core CPUs in two clusters and each cluster
has quard Cortex-A53.
Also add dts file to support HiKey development board which
based on Hi6220 SoC.
Signed-off-by: Bintian Wang
Acked-by: Haojian Zhuang
Reviewed-by: Yiping Xu
Tested-by: Will Deacon
Tested-by: Tyler Baker
Tested-by: Kevin Hilman
---
arch/arm64/boot/dts/Makefile |1 +
arch/arm64/boot/dts/hisilicon/Makefile |5 +
arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 31 +
arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 172
4 files changed, 209 insertions(+)
create mode 100644 arch/arm64/boot/dts/hisilicon/Makefile
create mode 100644 arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
create mode 100644 arch/arm64/boot/dts/hisilicon/hi6220.dtsi
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index ad26a75..38913be 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -4,6 +4,7 @@ dts-dirs += arm
dts-dirs += cavium
dts-dirs += exynos
dts-dirs += freescale
+dts-dirs += hisilicon
dts-dirs += mediatek
dts-dirs += qcom
dts-dirs += sprd
diff --git a/arch/arm64/boot/dts/hisilicon/Makefile
b/arch/arm64/boot/dts/hisilicon/Makefile
new file mode 100644
index 000..fa81a6e
--- /dev/null
+++ b/arch/arm64/boot/dts/hisilicon/Makefile
@@ -0,0 +1,5 @@
+dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb
+
+always := $(dtb-y)
+subdir-y := $(dts-dirs)
+clean-files:= *.dtb
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
new file mode 100644
index 000..e36a539
--- /dev/null
+++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
@@ -0,0 +1,31 @@
+/*
+ * dts file for Hisilicon HiKey Development Board
+ *
+ * Copyright (C) 2015, Hisilicon Ltd.
+ *
+ */
+
+/dts-v1/;
+
+/*Reserved 1MB memory for MCU*/
+/memreserve/ 0x05e0 0x0010;
+
+#include "hi6220.dtsi"
+
+/ {
+ model = "HiKey Development Board";
+ compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220";
+
+ aliases {
+ serial0 =
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x4000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
new file mode 100644
index 000..229937f
--- /dev/null
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -0,0 +1,172 @@
+/*
+ * dts file for Hisilicon Hi6220 SoC
+ *
+ * Copyright (C) 2015, Hisilicon Ltd.
+ */
+
+#include
+#include
+
+/ {
+ compatible = "hisilicon,hi6220";
+ interrupt-parent = <>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <>;
+ };
+ core1 {
+ cpu = <>;
+ };
+ core2 {
+ cpu = <>;
+ };
+ core3 {
+ cpu = <>;
+ };
+ };
+ cluster1 {
+ core0 {
+ cpu = <>;
+ };
+ core1 {
+ cpu = <>;
+ };
+ core2 {
+ cpu = <>;
+ };
+ core3 {
+ cpu = <>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+
Re: [PATCH v9 4/6] Documentation: DT: PL011: hi6220: add compatible string for Hisilicon designed UART
Hello Russell, On 2015/6/2 19:24, Russell King - ARM Linux wrote: On Tue, Jun 02, 2015 at 06:55:20PM +0800, Bintian wrote: On 2015/6/2 16:59, Linus Walleij wrote: On Sat, May 30, 2015 at 3:50 AM, Bintian Wang wrote: Hisilicon does some performance enhancements based on PL011(e.g. larger FIFO length), so add one compatible string "hisilicon,hi6220-uart" for That compatible string in the commit message is not even the same as in the patch. The UART0 is PL011 compatible, the UART1/2 have some performance enhancements features, so based on Mark's suggestion and I add this compatible string just for future use. Please don't submit it with this series. This patch should not be part of this series, it should be part of the series which modifies the PL011 driver, so it can be reviewed along with those changes. I agree with you and it's OK to me to remove this patch now. Could you help to ack the reset patches or I should send the version 10 without this patch? Until then, I'm going to NAK this patch. The thing that worries me though is that the subject line says this is a "Hisilicon *designed* UART". If Hisilicon _designed_ this UART, presumably they have changed the *vendor* field of the UART ID _not_ to indicate that ARM Ltd designed it? > If they've merely modified the parameters, and given the ARM Ltd PL011 a larger fifo, then there isn't really much of a problem - we've been here before, except the vendor has had a real vendor ID for the field (in the case of ST), plus we've had different FIFO lengths for ARM hardware too (32 bytes instead of 16 for revision 3 and above.) I think there is problem with my subject description, it's ARM designed indeed and Hisilicon just did some performance enhancements but not for UART0 in hi6220. Lastly, if you're not having to modify the PL011 driver in any way, you don't need to have a compatible. In any case, you _shouldn't_ for AMBA devices. AMBA does not match drivers based on OF compatible strings, so using OF compatible strings with the AMBA bus is just wrong. The AMBA compatible strings are there so that the generic OF code knows how to create the devices. Right. Thank you Russell. BR, Bintian -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v9 4/6] Documentation: DT: PL011: hi6220: add compatible string for Hisilicon designed UART
On 2015/6/2 16:59, Linus Walleij wrote:
On Sat, May 30, 2015 at 3:50 AM, Bintian Wang wrote:
Hisilicon does some performance enhancements based on PL011(e.g. larger
FIFO length), so add one compatible string "hisilicon,hi6220-uart" for
That compatible string in the commit message is not even
the same as in the patch.
The UART0 is PL011 compatible, the UART1/2 have some performance
enhancements features, so based on Mark's suggestion and I add this
compatible string just for future use.
future optimisations or workarounds works.
Signed-off-by: Bintian Wang
Suggested-by: Mark Rutland
Maybe I missed out on the earlier conversation, but do you
mean that the PrimeCell ID has not been properly set up
to something unique in this HiSilicon version of the PL011
block?
Even if so: do not override the compatible string like this,
that is not the PrimeCell style.
Define an 8 bit vendor ID (like tha ASCII for 'H' 0x48
or whatever) and encode it for these variants, if the
hardware is just using the ARM default PrimeCell
ID, override it in the device tree like Broadcom
are doing in arch/arm/boot/dts/bcm2835.dtsi:
arm,primecell-periphid = <0x00241011>;
Maybe yours would be:
arm,primecell-periphid = <0x00048011>;
For a first HiSilicon variant, then do some
:
enum amba_vendor {
AMBA_VENDOR_ARM = 0x41,
+ AMBA_VENDOR_HISILICON = 0x48,
Then patch drivers/tty/serial/amba_pl011.c to add vendor_hisilicon
and a match table for 0x00048011 just like everyone else.
Thanks and BR,
Bintian
Yours,
Linus Walleij
.
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v9 5/6] arm64: dts: Add dts files for Hisilicon Hi6220 SoC
Hello Mark, Rob and other ARM64 DT maintainers,
Could you help to ack this patch?
Thanks for your time.
Bintian
On 2015/5/30 9:51, Bintian Wang wrote:
Add initial dtsi file to support Hisilicon Hi6220 SoC with
support of Octal core CPUs in two clusters and each cluster
has quard Cortex-A53.
Also add dts file to support HiKey development board which
based on Hi6220 SoC.
Signed-off-by: Bintian Wang bintian.w...@huawei.com
Acked-by: Haojian Zhuang haojian.zhu...@linaro.org
Reviewed-by: Yiping Xu xuyip...@hisilicon.com
Tested-by: Will Deacon will.dea...@arm.com
Tested-by: Tyler Baker tyler.ba...@linaro.org
Tested-by: Kevin Hilman khil...@linaro.org
---
arch/arm64/boot/dts/Makefile |1 +
arch/arm64/boot/dts/hisilicon/Makefile |5 +
arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 31 +
arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 172
4 files changed, 209 insertions(+)
create mode 100644 arch/arm64/boot/dts/hisilicon/Makefile
create mode 100644 arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
create mode 100644 arch/arm64/boot/dts/hisilicon/hi6220.dtsi
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index ad26a75..38913be 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -4,6 +4,7 @@ dts-dirs += arm
dts-dirs += cavium
dts-dirs += exynos
dts-dirs += freescale
+dts-dirs += hisilicon
dts-dirs += mediatek
dts-dirs += qcom
dts-dirs += sprd
diff --git a/arch/arm64/boot/dts/hisilicon/Makefile
b/arch/arm64/boot/dts/hisilicon/Makefile
new file mode 100644
index 000..fa81a6e
--- /dev/null
+++ b/arch/arm64/boot/dts/hisilicon/Makefile
@@ -0,0 +1,5 @@
+dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb
+
+always := $(dtb-y)
+subdir-y := $(dts-dirs)
+clean-files:= *.dtb
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
new file mode 100644
index 000..e36a539
--- /dev/null
+++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
@@ -0,0 +1,31 @@
+/*
+ * dts file for Hisilicon HiKey Development Board
+ *
+ * Copyright (C) 2015, Hisilicon Ltd.
+ *
+ */
+
+/dts-v1/;
+
+/*Reserved 1MB memory for MCU*/
+/memreserve/ 0x05e0 0x0010;
+
+#include hi6220.dtsi
+
+/ {
+ model = HiKey Development Board;
+ compatible = hisilicon,hi6220-hikey, hisilicon,hi6220;
+
+ aliases {
+ serial0 = uart0;
+ };
+
+ chosen {
+ stdout-path = serial0:115200n8;
+ };
+
+ memory@0 {
+ device_type = memory;
+ reg = 0x0 0x0 0x0 0x4000;
+ };
+};
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
new file mode 100644
index 000..229937f
--- /dev/null
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -0,0 +1,172 @@
+/*
+ * dts file for Hisilicon Hi6220 SoC
+ *
+ * Copyright (C) 2015, Hisilicon Ltd.
+ */
+
+#include dt-bindings/clock/hi6220-clock.h
+#include dt-bindings/interrupt-controller/arm-gic.h
+
+/ {
+ compatible = hisilicon,hi6220;
+ interrupt-parent = gic;
+ #address-cells = 2;
+ #size-cells = 2;
+
+ psci {
+ compatible = arm,psci-0.2;
+ method = smc;
+ };
+
+ cpus {
+ #address-cells = 2;
+ #size-cells = 0;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = cpu0;
+ };
+ core1 {
+ cpu = cpu1;
+ };
+ core2 {
+ cpu = cpu2;
+ };
+ core3 {
+ cpu = cpu3;
+ };
+ };
+ cluster1 {
+ core0 {
+ cpu = cpu4;
+ };
+ core1 {
+ cpu = cpu5;
+ };
+ core2 {
+ cpu = cpu6;
+ };
+ core3 {
+ cpu = cpu7;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ compatible = arm,cortex-a53, arm,armv8;
+ device_type = cpu;
+ reg = 0x0 0x0;
+ enable-method = psci;
+ };
+
+ cpu1: cpu@1 {
+ compatible = arm,cortex-a53, arm,armv8;
+ device_type = cpu
Re: [PATCH v9 4/6] Documentation: DT: PL011: hi6220: add compatible string for Hisilicon designed UART
On 2015/6/2 16:59, Linus Walleij wrote:
On Sat, May 30, 2015 at 3:50 AM, Bintian Wang bintian.w...@huawei.com wrote:
Hisilicon does some performance enhancements based on PL011(e.g. larger
FIFO length), so add one compatible string hisilicon,hi6220-uart for
That compatible string in the commit message is not even
the same as in the patch.
The UART0 is PL011 compatible, the UART1/2 have some performance
enhancements features, so based on Mark's suggestion and I add this
compatible string just for future use.
future optimisations or workarounds works.
Signed-off-by: Bintian Wang bintian.w...@huawei.com
Suggested-by: Mark Rutland mark.rutl...@arm.com
Maybe I missed out on the earlier conversation, but do you
mean that the PrimeCell ID has not been properly set up
to something unique in this HiSilicon version of the PL011
block?
Even if so: do not override the compatible string like this,
that is not the PrimeCell style.
Define an 8 bit vendor ID (like tha ASCII for 'H' 0x48
or whatever) and encode it for these variants, if the
hardware is just using the ARM default PrimeCell
ID, override it in the device tree like Broadcom
are doing in arch/arm/boot/dts/bcm2835.dtsi:
arm,primecell-periphid = 0x00241011;
Maybe yours would be:
arm,primecell-periphid = 0x00048011;
For a first HiSilicon variant, then do some
include/linux/amba/bus.h:
enum amba_vendor {
AMBA_VENDOR_ARM = 0x41,
+ AMBA_VENDOR_HISILICON = 0x48,
Then patch drivers/tty/serial/amba_pl011.c to add vendor_hisilicon
and a match table for 0x00048011 just like everyone else.
Thanks and BR,
Bintian
Yours,
Linus Walleij
.
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v9 4/6] Documentation: DT: PL011: hi6220: add compatible string for Hisilicon designed UART
Hello Russell, On 2015/6/2 19:24, Russell King - ARM Linux wrote: On Tue, Jun 02, 2015 at 06:55:20PM +0800, Bintian wrote: On 2015/6/2 16:59, Linus Walleij wrote: On Sat, May 30, 2015 at 3:50 AM, Bintian Wang bintian.w...@huawei.com wrote: Hisilicon does some performance enhancements based on PL011(e.g. larger FIFO length), so add one compatible string hisilicon,hi6220-uart for That compatible string in the commit message is not even the same as in the patch. The UART0 is PL011 compatible, the UART1/2 have some performance enhancements features, so based on Mark's suggestion and I add this compatible string just for future use. Please don't submit it with this series. This patch should not be part of this series, it should be part of the series which modifies the PL011 driver, so it can be reviewed along with those changes. I agree with you and it's OK to me to remove this patch now. Could you help to ack the reset patches or I should send the version 10 without this patch? Until then, I'm going to NAK this patch. The thing that worries me though is that the subject line says this is a Hisilicon *designed* UART. If Hisilicon _designed_ this UART, presumably they have changed the *vendor* field of the UART ID _not_ to indicate that ARM Ltd designed it? If they've merely modified the parameters, and given the ARM Ltd PL011 a larger fifo, then there isn't really much of a problem - we've been here before, except the vendor has had a real vendor ID for the field (in the case of ST), plus we've had different FIFO lengths for ARM hardware too (32 bytes instead of 16 for revision 3 and above.) I think there is problem with my subject description, it's ARM designed indeed and Hisilicon just did some performance enhancements but not for UART0 in hi6220. Lastly, if you're not having to modify the PL011 driver in any way, you don't need to have a compatible. In any case, you _shouldn't_ for AMBA devices. AMBA does not match drivers based on OF compatible strings, so using OF compatible strings with the AMBA bus is just wrong. The AMBA compatible strings are there so that the generic OF code knows how to create the devices. Right. Thank you Russell. BR, Bintian -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v9 0/6] arm64,hi6220: Enable Hisilicon Hi6220 SoC
Hi Will, Mark and other ARM64 DT maintainers, Could you help ack this version? although Will, Kevin and Tyler have tested this patch set, I think also need an ack from you. The clock driver has been merged to linux-next, so I just add the clock header file to this patch set to avoid compilation error. Thanks, Bintian On 2015/5/30 9:50, Bintian Wang wrote: Hi6220 is one mobile solution of Hisilicon, this patchset contains initial support for Hi6220 SoC and HiKey development board, which supports octal ARM Cortex A53 cores. Initial support is minimal and includes just the arch configuration, device tree configuration, the clock driver has been picked up by clock maintainers in clk tree. PSCI is enabled in device tree and there is no problem to boot all the octal cores, and the CPU hotplug is also working now, you can download and compile the latest firmware based on the following link to run this patch set: https://github.com/96boards/documentation/wiki/UEFI Chnages v9: * Rebase to linus/master 4.1-rc1 * Remove the clock driver from this version because the clock maintainers have queued up the clock driver: git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next-hi6220 * This version also includes clock header file: [PATCH v9 6/6] dt-bindings: Add header file of hi6220 clock driver Although above patch is included in clock driver, I add to this series because the device tree file includes it, there will be compile error without it. At last, we just need to keep one when merged together. Changes v6~v8: This three versions only modified the clock drivers based on the Stephen's review advices. * clk-hi6220.c: ** Split the clock header file from clock driver ** Delete setting the parents clock of UART1 to HI6220_150M in clock driver, we can do that using assigned-clock in dts when enable UART1 in the future. * clkdivider-hi6220.c: ** Reuse some functions exported by clk-divider.c ** Remove "pr_err" and CLK_IS_BASIC flag ** Fix some programing style problems * hisilicon/clk.h: remove the "__init" markings on some funcition prototypes. Changes v5: * Rebase to kernel 4.1-rc2 * Add compatible string "hisilicon,hi6220-pl011" for Hisilicon designed UART * clk-hi6220.c: use __initdata for non-const arrays based on the commit 692d8328e8c039f9497eb862c6cf835de922c061 Changes v4: * Rebase to kernel 4.1-rc1 * Delete "arm,cortex-a15-gic" from the gic node in dts Changes v3: * Verified the CPU hotplug based on the new released firmware * Redefined the compatible strings of four system controllers in dts * Setting COMMON_CLK_HI6220 to a bool symbol * Keep CONFGI_ARCH_HISI sorted alphabetically Changes v2: * Split the DT bindings documents into earlier patches * Change SMP enable method from spin-table to PSCI in device tree * Remove "clock-frequency" from armv8-timer device node in device tree * Add more description about Hisilicon designed system controllers in DT bindings document * Enable high speed clock on UART1 mux * Other changes based on the discussion in the mailing list: https://lkml.org/lkml/2015/2/5/147 Bintian Wang (6): arm64: Enable Hisilicon ARMv8 SoC family in Kconfig and defconfig arm64: hi6220: Document devicetree bindings for Hisilicon hi6220 SoC clk: hi6220: Document devicetree bindings for hi6220 clock Documentation: DT: PL011: hi6220: add compatible string for Hisilicon designed UART arm64: dts: Add dts files for Hisilicon Hi6220 SoC dt-bindings: Add header file of hi6220 clock driver .../bindings/arm/hisilicon/hisilicon.txt | 87 ++ .../devicetree/bindings/clock/hi6220-clock.txt | 34 Documentation/devicetree/bindings/serial/pl011.txt |4 +- arch/arm64/Kconfig |5 + arch/arm64/boot/dts/Makefile |1 + arch/arm64/boot/dts/hisilicon/Makefile |5 + arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 31 arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 172 +++ arch/arm64/configs/defconfig |1 + include/dt-bindings/clock/hi6220-clock.h | 173 10 files changed, 512 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/clock/hi6220-clock.txt create mode 100644 arch/arm64/boot/dts/hisilicon/Makefile create mode 100644 arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts create mode 100644 arch/arm64/boot/dts/hisilicon/hi6220.dtsi create mode 100644 include/dt-bindings/clock/hi6220-clock.h -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v9 0/6] arm64,hi6220: Enable Hisilicon Hi6220 SoC
Hi Will, Mark and other ARM64 DT maintainers, Could you help ack this version? although Will, Kevin and Tyler have tested this patch set, I think also need an ack from you. The clock driver has been merged to linux-next, so I just add the clock header file to this patch set to avoid compilation error. Thanks, Bintian On 2015/5/30 9:50, Bintian Wang wrote: Hi6220 is one mobile solution of Hisilicon, this patchset contains initial support for Hi6220 SoC and HiKey development board, which supports octal ARM Cortex A53 cores. Initial support is minimal and includes just the arch configuration, device tree configuration, the clock driver has been picked up by clock maintainers in clk tree. PSCI is enabled in device tree and there is no problem to boot all the octal cores, and the CPU hotplug is also working now, you can download and compile the latest firmware based on the following link to run this patch set: https://github.com/96boards/documentation/wiki/UEFI Chnages v9: * Rebase to linus/master 4.1-rc1 * Remove the clock driver from this version because the clock maintainers have queued up the clock driver: git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next-hi6220 * This version also includes clock header file: [PATCH v9 6/6] dt-bindings: Add header file of hi6220 clock driver Although above patch is included in clock driver, I add to this series because the device tree file includes it, there will be compile error without it. At last, we just need to keep one when merged together. Changes v6~v8: This three versions only modified the clock drivers based on the Stephen's review advices. * clk-hi6220.c: ** Split the clock header file from clock driver ** Delete setting the parents clock of UART1 to HI6220_150M in clock driver, we can do that using assigned-clock in dts when enable UART1 in the future. * clkdivider-hi6220.c: ** Reuse some functions exported by clk-divider.c ** Remove pr_err and CLK_IS_BASIC flag ** Fix some programing style problems * hisilicon/clk.h: remove the __init markings on some funcition prototypes. Changes v5: * Rebase to kernel 4.1-rc2 * Add compatible string hisilicon,hi6220-pl011 for Hisilicon designed UART * clk-hi6220.c: use __initdata for non-const arrays based on the commit 692d8328e8c039f9497eb862c6cf835de922c061 Changes v4: * Rebase to kernel 4.1-rc1 * Delete arm,cortex-a15-gic from the gic node in dts Changes v3: * Verified the CPU hotplug based on the new released firmware * Redefined the compatible strings of four system controllers in dts * Setting COMMON_CLK_HI6220 to a bool symbol * Keep CONFGI_ARCH_HISI sorted alphabetically Changes v2: * Split the DT bindings documents into earlier patches * Change SMP enable method from spin-table to PSCI in device tree * Remove clock-frequency from armv8-timer device node in device tree * Add more description about Hisilicon designed system controllers in DT bindings document * Enable high speed clock on UART1 mux * Other changes based on the discussion in the mailing list: https://lkml.org/lkml/2015/2/5/147 Bintian Wang (6): arm64: Enable Hisilicon ARMv8 SoC family in Kconfig and defconfig arm64: hi6220: Document devicetree bindings for Hisilicon hi6220 SoC clk: hi6220: Document devicetree bindings for hi6220 clock Documentation: DT: PL011: hi6220: add compatible string for Hisilicon designed UART arm64: dts: Add dts files for Hisilicon Hi6220 SoC dt-bindings: Add header file of hi6220 clock driver .../bindings/arm/hisilicon/hisilicon.txt | 87 ++ .../devicetree/bindings/clock/hi6220-clock.txt | 34 Documentation/devicetree/bindings/serial/pl011.txt |4 +- arch/arm64/Kconfig |5 + arch/arm64/boot/dts/Makefile |1 + arch/arm64/boot/dts/hisilicon/Makefile |5 + arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 31 arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 172 +++ arch/arm64/configs/defconfig |1 + include/dt-bindings/clock/hi6220-clock.h | 173 10 files changed, 512 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/clock/hi6220-clock.txt create mode 100644 arch/arm64/boot/dts/hisilicon/Makefile create mode 100644 arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts create mode 100644 arch/arm64/boot/dts/hisilicon/hi6220.dtsi create mode 100644 include/dt-bindings/clock/hi6220-clock.h -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v9 0/6] arm64,hi6220: Enable Hisilicon Hi6220 SoC
Hi6220 is one mobile solution of Hisilicon, this patchset contains initial support for Hi6220 SoC and HiKey development board, which supports octal ARM Cortex A53 cores. Initial support is minimal and includes just the arch configuration, device tree configuration, the clock driver has been picked up by clock maintainers in clk tree. PSCI is enabled in device tree and there is no problem to boot all the octal cores, and the CPU hotplug is also working now, you can download and compile the latest firmware based on the following link to run this patch set: https://github.com/96boards/documentation/wiki/UEFI Chnages v9: * Rebase to linus/master 4.1-rc1 * Remove the clock driver from this version because the clock maintainers have queued up the clock driver: git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next-hi6220 * This version also includes clock header file: [PATCH v9 6/6] dt-bindings: Add header file of hi6220 clock driver Although above patch is included in clock driver, I add to this series because the device tree file includes it, there will be compile error without it. At last, we just need to keep one when merged together. Changes v6~v8: This three versions only modified the clock drivers based on the Stephen's review advices. * clk-hi6220.c: ** Split the clock header file from clock driver ** Delete setting the parents clock of UART1 to HI6220_150M in clock driver, we can do that using assigned-clock in dts when enable UART1 in the future. * clkdivider-hi6220.c: ** Reuse some functions exported by clk-divider.c ** Remove "pr_err" and CLK_IS_BASIC flag ** Fix some programing style problems * hisilicon/clk.h: remove the "__init" markings on some funcition prototypes. Changes v5: * Rebase to kernel 4.1-rc2 * Add compatible string "hisilicon,hi6220-pl011" for Hisilicon designed UART * clk-hi6220.c: use __initdata for non-const arrays based on the commit 692d8328e8c039f9497eb862c6cf835de922c061 Changes v4: * Rebase to kernel 4.1-rc1 * Delete "arm,cortex-a15-gic" from the gic node in dts Changes v3: * Verified the CPU hotplug based on the new released firmware * Redefined the compatible strings of four system controllers in dts * Setting COMMON_CLK_HI6220 to a bool symbol * Keep CONFGI_ARCH_HISI sorted alphabetically Changes v2: * Split the DT bindings documents into earlier patches * Change SMP enable method from spin-table to PSCI in device tree * Remove "clock-frequency" from armv8-timer device node in device tree * Add more description about Hisilicon designed system controllers in DT bindings document * Enable high speed clock on UART1 mux * Other changes based on the discussion in the mailing list: https://lkml.org/lkml/2015/2/5/147 Bintian Wang (6): arm64: Enable Hisilicon ARMv8 SoC family in Kconfig and defconfig arm64: hi6220: Document devicetree bindings for Hisilicon hi6220 SoC clk: hi6220: Document devicetree bindings for hi6220 clock Documentation: DT: PL011: hi6220: add compatible string for Hisilicon designed UART arm64: dts: Add dts files for Hisilicon Hi6220 SoC dt-bindings: Add header file of hi6220 clock driver .../bindings/arm/hisilicon/hisilicon.txt | 87 ++ .../devicetree/bindings/clock/hi6220-clock.txt | 34 Documentation/devicetree/bindings/serial/pl011.txt |4 +- arch/arm64/Kconfig |5 + arch/arm64/boot/dts/Makefile |1 + arch/arm64/boot/dts/hisilicon/Makefile |5 + arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 31 arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 172 +++ arch/arm64/configs/defconfig |1 + include/dt-bindings/clock/hi6220-clock.h | 173 10 files changed, 512 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/clock/hi6220-clock.txt create mode 100644 arch/arm64/boot/dts/hisilicon/Makefile create mode 100644 arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts create mode 100644 arch/arm64/boot/dts/hisilicon/hi6220.dtsi create mode 100644 include/dt-bindings/clock/hi6220-clock.h -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v9 4/6] Documentation: DT: PL011: hi6220: add compatible string for Hisilicon designed UART
Hisilicon does some performance enhancements based on PL011(e.g. larger FIFO length), so add one compatible string "hisilicon,hi6220-uart" for future optimisations or workarounds works. Signed-off-by: Bintian Wang Suggested-by: Mark Rutland --- Documentation/devicetree/bindings/serial/pl011.txt |4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/serial/pl011.txt b/Documentation/devicetree/bindings/serial/pl011.txt index ba3ecb8..cb9fd9d 100644 --- a/Documentation/devicetree/bindings/serial/pl011.txt +++ b/Documentation/devicetree/bindings/serial/pl011.txt @@ -1,7 +1,9 @@ * ARM AMBA Primecell PL011 serial UART Required properties: -- compatible: must be "arm,primecell", "arm,pl011" +- compatible: should contain one of the following sequences: + * "arm,pl011", "arm,primecell" + * "hisilicon,hi6220-pl011", "arm,pl011", "arm,primecell" - reg: exactly one register range with length 0x1000 - interrupts: exactly one interrupt specifier -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v9 1/6] arm64: Enable Hisilicon ARMv8 SoC family in Kconfig and defconfig
This patch introduces ARCH_HISI to enable Hisilicon SoC family in Kconfig and defconfig. Signed-off-by: Bintian Wang Acked-by: Haojian Zhuang Reviewed-by: Wei Xu Tested-by: Will Deacon Tested-by: Tyler Baker Tested-by: Kevin Hilman --- arch/arm64/Kconfig |5 + arch/arm64/configs/defconfig |1 + 2 files changed, 6 insertions(+) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 4269dba..2af5efe 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -180,6 +180,11 @@ config ARCH_FSL_LS2085A help This enables support for Freescale LS2085A SOC. +config ARCH_HISI + bool "Hisilicon SoC Family" + help + This enables support for Hisilicon ARMv8 SoC family + config ARCH_MEDIATEK bool "Mediatek MT65xx & MT81xx ARMv8 SoC" select ARM_GIC diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 2ed7449..1d293ea 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -33,6 +33,7 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_IOSCHED_DEADLINE is not set CONFIG_ARCH_EXYNOS7=y CONFIG_ARCH_FSL_LS2085A=y +CONFIG_ARCH_HISI=y CONFIG_ARCH_MEDIATEK=y CONFIG_ARCH_SEATTLE=y CONFIG_ARCH_TEGRA=y -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v9 3/6] clk: hi6220: Document devicetree bindings for hi6220 clock
Document DT files bindings for Hisilicon hi6220 clock.
Signed-off-by: Bintian Wang
Acked-by: Haojian Zhuang
Suggested-by: Arnd Bergmann
Acked-by: Stephen Boyd
---
.../devicetree/bindings/clock/hi6220-clock.txt | 34
1 file changed, 34 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/hi6220-clock.txt
diff --git a/Documentation/devicetree/bindings/clock/hi6220-clock.txt
b/Documentation/devicetree/bindings/clock/hi6220-clock.txt
new file mode 100644
index 000..53ddb19
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/hi6220-clock.txt
@@ -0,0 +1,34 @@
+* Hisilicon Hi6220 Clock Controller
+
+Clock control registers reside in different Hi6220 system controllers,
+please refer the following document to know more about the binding rules
+for these system controllers:
+
+Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
+
+Required Properties:
+
+- compatible: the compatible should be one of the following strings to
+ indicate the clock controller functionality.
+
+ - "hisilicon,hi6220-aoctrl"
+ - "hisilicon,hi6220-sysctrl"
+ - "hisilicon,hi6220-mediactrl"
+ - "hisilicon,hi6220-pmctrl"
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- #clock-cells: should be 1.
+
+For example:
+ sys_ctrl: sys_ctrl {
+ compatible = "hisilicon,hi6220-sysctrl", "syscon";
+ reg = <0x0 0xf703 0x0 0x2000>;
+ #clock-cells = <1>;
+ };
+
+Each clock is assigned an identifier and client nodes use this identifier
+to specify the clock which they consume.
+
+All these identifier could be found in .
--
1.7.9.5
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[PATCH v9 6/6] dt-bindings: Add header file of hi6220 clock driver
Add the header file "hi6220-clock.h" used by both hi6220 clock driver and hi6220 device tree file. Suggested-by: Stephen Boyd Signed-off-by: Bintian Wang Tested-by: Will Deacon Tested-by: Tyler Baker Tested-by: Kevin Hilman --- include/dt-bindings/clock/hi6220-clock.h | 173 ++ 1 file changed, 173 insertions(+) create mode 100644 include/dt-bindings/clock/hi6220-clock.h diff --git a/include/dt-bindings/clock/hi6220-clock.h b/include/dt-bindings/clock/hi6220-clock.h new file mode 100644 index 000..70ee383 --- /dev/null +++ b/include/dt-bindings/clock/hi6220-clock.h @@ -0,0 +1,173 @@ +/* + * Copyright (c) 2015 Hisilicon Limited. + * + * Author: Bintian Wang + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __DT_BINDINGS_CLOCK_HI6220_H +#define __DT_BINDINGS_CLOCK_HI6220_H + +/* clk in Hi6220 AO (always on) controller */ +#define HI6220_NONE_CLOCK 0 + +/* fixed rate clocks */ +#define HI6220_REF32K 1 +#define HI6220_CLK_TCXO2 +#define HI6220_MMC1_PAD3 +#define HI6220_MMC2_PAD4 +#define HI6220_MMC0_PAD5 +#define HI6220_PLL_BBP 6 +#define HI6220_PLL_GPU 7 +#define HI6220_PLL1_DDR8 +#define HI6220_PLL_SYS 9 +#define HI6220_PLL_SYS_MEDIA 10 +#define HI6220_DDR_SRC 11 +#define HI6220_PLL_MEDIA 12 +#define HI6220_PLL_DDR 13 + +/* fixed factor clocks */ +#define HI6220_300M14 +#define HI6220_150M15 +#define HI6220_PICOPHY_SRC 16 +#define HI6220_MMC0_SRC_SEL17 +#define HI6220_MMC1_SRC_SEL18 +#define HI6220_MMC2_SRC_SEL19 +#define HI6220_VPU_CODEC 20 +#define HI6220_MMC0_SMP21 +#define HI6220_MMC1_SMP22 +#define HI6220_MMC2_SMP23 + +/* gate clocks */ +#define HI6220_WDT0_PCLK 24 +#define HI6220_WDT1_PCLK 25 +#define HI6220_WDT2_PCLK 26 +#define HI6220_TIMER0_PCLK 27 +#define HI6220_TIMER1_PCLK 28 +#define HI6220_TIMER2_PCLK 29 +#define HI6220_TIMER3_PCLK 30 +#define HI6220_TIMER4_PCLK 31 +#define HI6220_TIMER5_PCLK 32 +#define HI6220_TIMER6_PCLK 33 +#define HI6220_TIMER7_PCLK 34 +#define HI6220_TIMER8_PCLK 35 +#define HI6220_UART0_PCLK 36 + +#define HI6220_AO_NR_CLKS 37 + +/* clk in Hi6220 systrl */ +/* gate clock */ +#define HI6220_MMC0_CLK1 +#define HI6220_MMC0_CIUCLK 2 +#define HI6220_MMC1_CLK3 +#define HI6220_MMC1_CIUCLK 4 +#define HI6220_MMC2_CLK5 +#define HI6220_MMC2_CIUCLK 6 +#define HI6220_USBOTG_HCLK 7 +#define HI6220_CLK_PICOPHY 8 +#define HI6220_HIFI9 +#define HI6220_DACODEC_PCLK10 +#define HI6220_EDMAC_ACLK 11 +#define HI6220_CS_ATB 12 +#define HI6220_I2C0_CLK13 +#define HI6220_I2C1_CLK14 +#define HI6220_I2C2_CLK15 +#define HI6220_I2C3_CLK16 +#define HI6220_UART1_PCLK 17 +#define HI6220_UART2_PCLK 18 +#define HI6220_UART3_PCLK 19 +#define HI6220_UART4_PCLK 20 +#define HI6220_SPI_CLK 21 +#define HI6220_TSENSOR_CLK 22 +#define HI6220_MMU_CLK 23 +#define HI6220_HIFI_SEL24 +#define HI6220_MMC0_SYSPLL 25 +#define HI6220_MMC1_SYSPLL 26 +#define HI6220_MMC2_SYSPLL 27 +#define HI6220_MMC0_SEL28 +#define HI6220_MMC1_SEL29 +#define HI6220_BBPPLL_SEL 30 +#define HI6220_MEDIA_PLL_SRC 31 +#define HI6220_MMC2_SEL32 +#define HI6220_CS_ATB_SYSPLL 33 + +/* mux clocks */ +#define HI6220_MMC0_SRC34 +#define HI6220_MMC0_SMP_IN 35 +#define HI6220_MMC1_SRC36 +#define HI6220_MMC1_SMP_IN 37 +#define HI6220_MMC2_SRC38 +#define HI6220_MMC2_SMP_IN 39 +#define HI6220_HIFI_SRC40 +#define HI6220_UART1_SRC 41 +#define HI6220_UART2_SRC 42 +#define HI6220_UART3_SRC 43 +#define HI6220_UART4_SRC 44 +#define HI6220_MMC0_MUX0 45 +#define HI6220_MMC1_MUX0 46 +#define HI6220_MMC2_MUX0 47 +#define HI6220_MMC0_MUX1 48 +#define HI6220_MMC1_MUX1 49 +#define HI6220_MMC2_MUX1 50 + +/* divider clocks */ +#define HI6220_CLK_BUS 51 +#define HI6220_MMC0_DIV52 +#define HI6220_MMC1_DIV53 +#define HI6220_MMC2_DIV54 +#define HI6220_HIFI_DIV55 +#define HI6220_BBPPLL0_DIV 56 +#define HI6220_CS_DAPB 57 +#define HI6220_CS_ATB_DIV 58 + +#define HI6220_SYS_NR_CLKS 59 + +/* clk in Hi6220 media controller */ +/* gate clocks */ +#define HI6220_DSI_PCLK1 +#define HI6220_G3D_PCLK2 +#define HI6220_ACLK_CODEC_VPU
[PATCH v9 5/6] arm64: dts: Add dts files for Hisilicon Hi6220 SoC
Add initial dtsi file to support Hisilicon Hi6220 SoC with
support of Octal core CPUs in two clusters and each cluster
has quard Cortex-A53.
Also add dts file to support HiKey development board which
based on Hi6220 SoC.
Signed-off-by: Bintian Wang
Acked-by: Haojian Zhuang
Reviewed-by: Yiping Xu
Tested-by: Will Deacon
Tested-by: Tyler Baker
Tested-by: Kevin Hilman
---
arch/arm64/boot/dts/Makefile |1 +
arch/arm64/boot/dts/hisilicon/Makefile |5 +
arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 31 +
arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 172
4 files changed, 209 insertions(+)
create mode 100644 arch/arm64/boot/dts/hisilicon/Makefile
create mode 100644 arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
create mode 100644 arch/arm64/boot/dts/hisilicon/hi6220.dtsi
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index ad26a75..38913be 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -4,6 +4,7 @@ dts-dirs += arm
dts-dirs += cavium
dts-dirs += exynos
dts-dirs += freescale
+dts-dirs += hisilicon
dts-dirs += mediatek
dts-dirs += qcom
dts-dirs += sprd
diff --git a/arch/arm64/boot/dts/hisilicon/Makefile
b/arch/arm64/boot/dts/hisilicon/Makefile
new file mode 100644
index 000..fa81a6e
--- /dev/null
+++ b/arch/arm64/boot/dts/hisilicon/Makefile
@@ -0,0 +1,5 @@
+dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb
+
+always := $(dtb-y)
+subdir-y := $(dts-dirs)
+clean-files:= *.dtb
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
new file mode 100644
index 000..e36a539
--- /dev/null
+++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
@@ -0,0 +1,31 @@
+/*
+ * dts file for Hisilicon HiKey Development Board
+ *
+ * Copyright (C) 2015, Hisilicon Ltd.
+ *
+ */
+
+/dts-v1/;
+
+/*Reserved 1MB memory for MCU*/
+/memreserve/ 0x05e0 0x0010;
+
+#include "hi6220.dtsi"
+
+/ {
+ model = "HiKey Development Board";
+ compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220";
+
+ aliases {
+ serial0 =
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x4000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
new file mode 100644
index 000..229937f
--- /dev/null
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -0,0 +1,172 @@
+/*
+ * dts file for Hisilicon Hi6220 SoC
+ *
+ * Copyright (C) 2015, Hisilicon Ltd.
+ */
+
+#include
+#include
+
+/ {
+ compatible = "hisilicon,hi6220";
+ interrupt-parent = <>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <>;
+ };
+ core1 {
+ cpu = <>;
+ };
+ core2 {
+ cpu = <>;
+ };
+ core3 {
+ cpu = <>;
+ };
+ };
+ cluster1 {
+ core0 {
+ cpu = <>;
+ };
+ core1 {
+ cpu = <>;
+ };
+ core2 {
+ cpu = <>;
+ };
+ core3 {
+ cpu = <>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x1>;
+ enable-method = &q
[PATCH v9 2/6] arm64: hi6220: Document devicetree bindings for Hisilicon hi6220 SoC
This patch adds documentation for the devicetree bindings used by the
DT files of Hisilicon hi6220 SoC mobile platform.
Signed-off-by: Bintian Wang
Suggested-by: Arnd Bergmann
Acked-by: Haojian Zhuang
Acked-by: Stephen Boyd
---
.../bindings/arm/hisilicon/hisilicon.txt | 87
1 file changed, 87 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
index 35b1bd4..f67d0f3 100644
--- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
+++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
@@ -1,5 +1,8 @@
Hisilicon Platforms Device Tree Bindings
+Hi6220 SoC
+Required root node properties:
+ - compatible = "hisilicon,hi6220";
Hi4511 Board
Required root node properties:
@@ -13,6 +16,9 @@ HiP01 ca9x2 Board
Required root node properties:
- compatible = "hisilicon,hip01-ca9x2";
+HiKey Board
+Required root node properties:
+ - compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220";
Hisilicon system controller
@@ -41,6 +47,87 @@ Example:
};
---
+Hisilicon Hi6220 system controller
+
+Required properties:
+- compatible : "hisilicon,hi6220-sysctrl"
+- reg : Register address and size
+- #clock-cells: should be set to 1, many clock registers are defined
+ under this controller and this property must be present.
+
+Hisilicon designs this controller as one of the system controllers,
+its main functions are the same as Hisilicon system controller, but
+the register offset of some core modules are different.
+
+Example:
+ /*for Hi6220*/
+ sys_ctrl: sys_ctrl {
+ compatible = "hisilicon,hi6220-sysctrl", "syscon";
+ reg = <0x0 0xf703 0x0 0x2000>;
+ #clock-cells = <1>;
+ };
+
+
+Hisilicon Hi6220 Power Always ON domain controller
+
+Required properties:
+- compatible : "hisilicon,hi6220-aoctrl"
+- reg : Register address and size
+- #clock-cells: should be set to 1, many clock registers are defined
+ under this controller and this property must be present.
+
+Hisilicon designs this system controller to control the power always
+on domain for mobile platform.
+
+Example:
+ /*for Hi6220*/
+ ao_ctrl: ao_ctrl {
+ compatible = "hisilicon,hi6220-aoctrl", "syscon";
+ reg = <0x0 0xf780 0x0 0x2000>;
+ #clock-cells = <1>;
+ };
+
+
+Hisilicon Hi6220 Media domain controller
+
+Required properties:
+- compatible : "hisilicon,hi6220-mediactrl"
+- reg : Register address and size
+- #clock-cells: should be set to 1, many clock registers are defined
+ under this controller and this property must be present.
+
+Hisilicon designs this system controller to control the multimedia
+domain(e.g. codec, G3D ...) for mobile platform.
+
+Example:
+ /*for Hi6220*/
+ media_ctrl: media_ctrl {
+ compatible = "hisilicon,hi6220-mediactrl", "syscon";
+ reg = <0x0 0xf441 0x0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+
+Hisilicon Hi6220 Power Management domain controller
+
+Required properties:
+- compatible : "hisilicon,hi6220-pmctrl"
+- reg : Register address and size
+- #clock-cells: should be set to 1, some clock registers are define
+ under this controller and this property must be present.
+
+Hisilicon designs this system controller to control the power management
+domain for mobile platform.
+
+Example:
+ /*for Hi6220*/
+ pm_ctrl: pm_ctrl {
+ compatible = "hisilicon,hi6220-pmctrl", "syscon";
+ reg = <0x0 0xf7032000 0x0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+---
Hisilicon HiP01 system controller
Required properties:
--
1.7.9.5
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v8 0/7] arm64,hi6220: Enable Hisilicon Hi6220 SoC
Hello Kevin, On 2015/5/30 7:00, Kevin Hilman wrote: Hi Bintian, Bintian Wang writes: From: Bintian Wang Hi6220 is one mobile solution of Hisilicon, this patchset contains initial support for Hi6220 SoC and HiKey development board, which supports octal ARM Cortex A53 cores. Initial support is minimal and includes just the arch configuration, clock driver, device tree configuration. PSCI is enabled in device tree and there is no problem to boot all the octal cores, and the CPU hotplug is also working now, you can download and compile the latest firmware based on the following link to run this patch set: https://github.com/96boards/documentation/wiki/UEFI Changes v6~v8: This three versions only modified the clock drivers based on the Stephen's review advices. * clk-hi6220.c: ** Split the clock header file from clock driver ** Delete setting the parents clock of UART1 to HI6220_150M in clock driver, we can do that using assigned-clock in dts when enable UART1 in the future. * clkdivider-hi6220.c: ** Reuse some functions exported by clk-divider.c ** Remove "pr_err" and CLK_IS_BASIC flag ** Fix some programing style problems * hisilicon/clk.h: remove the "__init" markings on some funcition prototypes. It's not clear what kernel this series is meant to apply to. It doesn't apply cleanly to v4.1-rc2 (the version stated for v5) or the current -rc (v4.1-rc5) it also doesn't apply cleanly to linus/master or linux-next. If the series doesn't apply to Linus tree, please state clearly in the changelog what tree it should apply to as well as any dependncies. Also, this version is missing patch 1 from the v6 series, which adds the Kconfig/defconfig changes. Without that patch, nothing in this series is even compiled (clk driver or DTS files.) So my recommendation, since the clock driver is very close to being merged: Please create a v9 series with *only* the patches that are not already queued up on the clk tree[1]. That should be patches 1-3 and 7 of this series, plus patch 1 from v6. That series should apply cleanly to v4.1-rc1 (or a newer -rc if there are dependencies.) In the changelog to that series, state the version that it applies to, and also state that it depends on the clk-next branch where the clock maintainers have queued up the driver[1]. Then all that's left is to collect an ack from a DT maintainer, and these can be queued up via the arm-soc tree. FWIW, I've boot tested patches 1-3 and 7 of this series, plus patch 1 from v6 combined with the clk-next-hi6220 branch[1] on my board (which uses ATF + mainline u-boot) and all 8 A53 cores are coming up, so feel free to add: Tested-by: Kevin Hilman to your v9 series. Very good and detailed instructions, I will prepare the v9 soon. Thanks, Bintian Thanks, Kevin [1] git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next-hi6220 . -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: linux-next: manual merge of the clk tree with the imx-mxs tree
Hello Stephen,
Thank you very much for this fix.
BR,
Bintian
On 2015/5/29 18:45, Stephen Rothwell wrote:
Hi all,
Today's linux-next merge of the clk tree got a conflict in
drivers/clk/Makefile between commit 33156149fc4a ("ARM: imx: move clock
drivers into drivers/clk") from the imx-mxs tree and commit
b1691707eccd ("clk: hi6220: Clock driver support for Hisilicon hi6220
SoC") from the clk tree.
I fixed it up (see below) and can carry the fix as necessary (no action
is required).
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: linux-next: manual merge of the clk tree with the imx-mxs tree
Hello Stephen, Thank you very much for this fix. BR, Bintian On 2015/5/29 18:45, Stephen Rothwell wrote: Hi all, Today's linux-next merge of the clk tree got a conflict in drivers/clk/Makefile between commit 33156149fc4a (ARM: imx: move clock drivers into drivers/clk) from the imx-mxs tree and commit b1691707eccd (clk: hi6220: Clock driver support for Hisilicon hi6220 SoC) from the clk tree. I fixed it up (see below) and can carry the fix as necessary (no action is required). -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v8 0/7] arm64,hi6220: Enable Hisilicon Hi6220 SoC
Hello Kevin, On 2015/5/30 7:00, Kevin Hilman wrote: Hi Bintian, Bintian Wang bintian.w...@huawei.com writes: From: Bintian Wang wangbint...@gmail.com Hi6220 is one mobile solution of Hisilicon, this patchset contains initial support for Hi6220 SoC and HiKey development board, which supports octal ARM Cortex A53 cores. Initial support is minimal and includes just the arch configuration, clock driver, device tree configuration. PSCI is enabled in device tree and there is no problem to boot all the octal cores, and the CPU hotplug is also working now, you can download and compile the latest firmware based on the following link to run this patch set: https://github.com/96boards/documentation/wiki/UEFI Changes v6~v8: This three versions only modified the clock drivers based on the Stephen's review advices. * clk-hi6220.c: ** Split the clock header file from clock driver ** Delete setting the parents clock of UART1 to HI6220_150M in clock driver, we can do that using assigned-clock in dts when enable UART1 in the future. * clkdivider-hi6220.c: ** Reuse some functions exported by clk-divider.c ** Remove pr_err and CLK_IS_BASIC flag ** Fix some programing style problems * hisilicon/clk.h: remove the __init markings on some funcition prototypes. It's not clear what kernel this series is meant to apply to. It doesn't apply cleanly to v4.1-rc2 (the version stated for v5) or the current -rc (v4.1-rc5) it also doesn't apply cleanly to linus/master or linux-next. If the series doesn't apply to Linus tree, please state clearly in the changelog what tree it should apply to as well as any dependncies. Also, this version is missing patch 1 from the v6 series, which adds the Kconfig/defconfig changes. Without that patch, nothing in this series is even compiled (clk driver or DTS files.) So my recommendation, since the clock driver is very close to being merged: Please create a v9 series with *only* the patches that are not already queued up on the clk tree[1]. That should be patches 1-3 and 7 of this series, plus patch 1 from v6. That series should apply cleanly to v4.1-rc1 (or a newer -rc if there are dependencies.) In the changelog to that series, state the version that it applies to, and also state that it depends on the clk-next branch where the clock maintainers have queued up the driver[1]. Then all that's left is to collect an ack from a DT maintainer, and these can be queued up via the arm-soc tree. FWIW, I've boot tested patches 1-3 and 7 of this series, plus patch 1 from v6 combined with the clk-next-hi6220 branch[1] on my board (which uses ATF + mainline u-boot) and all 8 A53 cores are coming up, so feel free to add: Tested-by: Kevin Hilman khil...@linaro.org to your v9 series. Very good and detailed instructions, I will prepare the v9 soon. Thanks, Bintian Thanks, Kevin [1] git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next-hi6220 . -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v9 1/6] arm64: Enable Hisilicon ARMv8 SoC family in Kconfig and defconfig
This patch introduces ARCH_HISI to enable Hisilicon SoC family in Kconfig and defconfig. Signed-off-by: Bintian Wang bintian.w...@huawei.com Acked-by: Haojian Zhuang haojian.zhu...@linaro.org Reviewed-by: Wei Xu xuw...@hisilicon.com Tested-by: Will Deacon will.dea...@arm.com Tested-by: Tyler Baker tyler.ba...@linaro.org Tested-by: Kevin Hilman khil...@linaro.org --- arch/arm64/Kconfig |5 + arch/arm64/configs/defconfig |1 + 2 files changed, 6 insertions(+) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 4269dba..2af5efe 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -180,6 +180,11 @@ config ARCH_FSL_LS2085A help This enables support for Freescale LS2085A SOC. +config ARCH_HISI + bool Hisilicon SoC Family + help + This enables support for Hisilicon ARMv8 SoC family + config ARCH_MEDIATEK bool Mediatek MT65xx MT81xx ARMv8 SoC select ARM_GIC diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 2ed7449..1d293ea 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -33,6 +33,7 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_IOSCHED_DEADLINE is not set CONFIG_ARCH_EXYNOS7=y CONFIG_ARCH_FSL_LS2085A=y +CONFIG_ARCH_HISI=y CONFIG_ARCH_MEDIATEK=y CONFIG_ARCH_SEATTLE=y CONFIG_ARCH_TEGRA=y -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v9 4/6] Documentation: DT: PL011: hi6220: add compatible string for Hisilicon designed UART
Hisilicon does some performance enhancements based on PL011(e.g. larger FIFO length), so add one compatible string hisilicon,hi6220-uart for future optimisations or workarounds works. Signed-off-by: Bintian Wang bintian.w...@huawei.com Suggested-by: Mark Rutland mark.rutl...@arm.com --- Documentation/devicetree/bindings/serial/pl011.txt |4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/serial/pl011.txt b/Documentation/devicetree/bindings/serial/pl011.txt index ba3ecb8..cb9fd9d 100644 --- a/Documentation/devicetree/bindings/serial/pl011.txt +++ b/Documentation/devicetree/bindings/serial/pl011.txt @@ -1,7 +1,9 @@ * ARM AMBA Primecell PL011 serial UART Required properties: -- compatible: must be arm,primecell, arm,pl011 +- compatible: should contain one of the following sequences: + * arm,pl011, arm,primecell + * hisilicon,hi6220-pl011, arm,pl011, arm,primecell - reg: exactly one register range with length 0x1000 - interrupts: exactly one interrupt specifier -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v9 6/6] dt-bindings: Add header file of hi6220 clock driver
Add the header file hi6220-clock.h used by both hi6220 clock driver and hi6220 device tree file. Suggested-by: Stephen Boyd sb...@codeaurora.org Signed-off-by: Bintian Wang bintian.w...@huawei.com Tested-by: Will Deacon will.dea...@arm.com Tested-by: Tyler Baker tyler.ba...@linaro.org Tested-by: Kevin Hilman khil...@linaro.org --- include/dt-bindings/clock/hi6220-clock.h | 173 ++ 1 file changed, 173 insertions(+) create mode 100644 include/dt-bindings/clock/hi6220-clock.h diff --git a/include/dt-bindings/clock/hi6220-clock.h b/include/dt-bindings/clock/hi6220-clock.h new file mode 100644 index 000..70ee383 --- /dev/null +++ b/include/dt-bindings/clock/hi6220-clock.h @@ -0,0 +1,173 @@ +/* + * Copyright (c) 2015 Hisilicon Limited. + * + * Author: Bintian Wang bintian.w...@huawei.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __DT_BINDINGS_CLOCK_HI6220_H +#define __DT_BINDINGS_CLOCK_HI6220_H + +/* clk in Hi6220 AO (always on) controller */ +#define HI6220_NONE_CLOCK 0 + +/* fixed rate clocks */ +#define HI6220_REF32K 1 +#define HI6220_CLK_TCXO2 +#define HI6220_MMC1_PAD3 +#define HI6220_MMC2_PAD4 +#define HI6220_MMC0_PAD5 +#define HI6220_PLL_BBP 6 +#define HI6220_PLL_GPU 7 +#define HI6220_PLL1_DDR8 +#define HI6220_PLL_SYS 9 +#define HI6220_PLL_SYS_MEDIA 10 +#define HI6220_DDR_SRC 11 +#define HI6220_PLL_MEDIA 12 +#define HI6220_PLL_DDR 13 + +/* fixed factor clocks */ +#define HI6220_300M14 +#define HI6220_150M15 +#define HI6220_PICOPHY_SRC 16 +#define HI6220_MMC0_SRC_SEL17 +#define HI6220_MMC1_SRC_SEL18 +#define HI6220_MMC2_SRC_SEL19 +#define HI6220_VPU_CODEC 20 +#define HI6220_MMC0_SMP21 +#define HI6220_MMC1_SMP22 +#define HI6220_MMC2_SMP23 + +/* gate clocks */ +#define HI6220_WDT0_PCLK 24 +#define HI6220_WDT1_PCLK 25 +#define HI6220_WDT2_PCLK 26 +#define HI6220_TIMER0_PCLK 27 +#define HI6220_TIMER1_PCLK 28 +#define HI6220_TIMER2_PCLK 29 +#define HI6220_TIMER3_PCLK 30 +#define HI6220_TIMER4_PCLK 31 +#define HI6220_TIMER5_PCLK 32 +#define HI6220_TIMER6_PCLK 33 +#define HI6220_TIMER7_PCLK 34 +#define HI6220_TIMER8_PCLK 35 +#define HI6220_UART0_PCLK 36 + +#define HI6220_AO_NR_CLKS 37 + +/* clk in Hi6220 systrl */ +/* gate clock */ +#define HI6220_MMC0_CLK1 +#define HI6220_MMC0_CIUCLK 2 +#define HI6220_MMC1_CLK3 +#define HI6220_MMC1_CIUCLK 4 +#define HI6220_MMC2_CLK5 +#define HI6220_MMC2_CIUCLK 6 +#define HI6220_USBOTG_HCLK 7 +#define HI6220_CLK_PICOPHY 8 +#define HI6220_HIFI9 +#define HI6220_DACODEC_PCLK10 +#define HI6220_EDMAC_ACLK 11 +#define HI6220_CS_ATB 12 +#define HI6220_I2C0_CLK13 +#define HI6220_I2C1_CLK14 +#define HI6220_I2C2_CLK15 +#define HI6220_I2C3_CLK16 +#define HI6220_UART1_PCLK 17 +#define HI6220_UART2_PCLK 18 +#define HI6220_UART3_PCLK 19 +#define HI6220_UART4_PCLK 20 +#define HI6220_SPI_CLK 21 +#define HI6220_TSENSOR_CLK 22 +#define HI6220_MMU_CLK 23 +#define HI6220_HIFI_SEL24 +#define HI6220_MMC0_SYSPLL 25 +#define HI6220_MMC1_SYSPLL 26 +#define HI6220_MMC2_SYSPLL 27 +#define HI6220_MMC0_SEL28 +#define HI6220_MMC1_SEL29 +#define HI6220_BBPPLL_SEL 30 +#define HI6220_MEDIA_PLL_SRC 31 +#define HI6220_MMC2_SEL32 +#define HI6220_CS_ATB_SYSPLL 33 + +/* mux clocks */ +#define HI6220_MMC0_SRC34 +#define HI6220_MMC0_SMP_IN 35 +#define HI6220_MMC1_SRC36 +#define HI6220_MMC1_SMP_IN 37 +#define HI6220_MMC2_SRC38 +#define HI6220_MMC2_SMP_IN 39 +#define HI6220_HIFI_SRC40 +#define HI6220_UART1_SRC 41 +#define HI6220_UART2_SRC 42 +#define HI6220_UART3_SRC 43 +#define HI6220_UART4_SRC 44 +#define HI6220_MMC0_MUX0 45 +#define HI6220_MMC1_MUX0 46 +#define HI6220_MMC2_MUX0 47 +#define HI6220_MMC0_MUX1 48 +#define HI6220_MMC1_MUX1 49 +#define HI6220_MMC2_MUX1 50 + +/* divider clocks */ +#define HI6220_CLK_BUS 51 +#define HI6220_MMC0_DIV52 +#define HI6220_MMC1_DIV53 +#define HI6220_MMC2_DIV54 +#define HI6220_HIFI_DIV55 +#define HI6220_BBPPLL0_DIV 56 +#define HI6220_CS_DAPB 57 +#define HI6220_CS_ATB_DIV 58 + +#define HI6220_SYS_NR_CLKS 59 + +/* clk in Hi6220 media controller */ +/* gate clocks */ +#define
[PATCH v9 5/6] arm64: dts: Add dts files for Hisilicon Hi6220 SoC
Add initial dtsi file to support Hisilicon Hi6220 SoC with
support of Octal core CPUs in two clusters and each cluster
has quard Cortex-A53.
Also add dts file to support HiKey development board which
based on Hi6220 SoC.
Signed-off-by: Bintian Wang bintian.w...@huawei.com
Acked-by: Haojian Zhuang haojian.zhu...@linaro.org
Reviewed-by: Yiping Xu xuyip...@hisilicon.com
Tested-by: Will Deacon will.dea...@arm.com
Tested-by: Tyler Baker tyler.ba...@linaro.org
Tested-by: Kevin Hilman khil...@linaro.org
---
arch/arm64/boot/dts/Makefile |1 +
arch/arm64/boot/dts/hisilicon/Makefile |5 +
arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 31 +
arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 172
4 files changed, 209 insertions(+)
create mode 100644 arch/arm64/boot/dts/hisilicon/Makefile
create mode 100644 arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
create mode 100644 arch/arm64/boot/dts/hisilicon/hi6220.dtsi
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index ad26a75..38913be 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -4,6 +4,7 @@ dts-dirs += arm
dts-dirs += cavium
dts-dirs += exynos
dts-dirs += freescale
+dts-dirs += hisilicon
dts-dirs += mediatek
dts-dirs += qcom
dts-dirs += sprd
diff --git a/arch/arm64/boot/dts/hisilicon/Makefile
b/arch/arm64/boot/dts/hisilicon/Makefile
new file mode 100644
index 000..fa81a6e
--- /dev/null
+++ b/arch/arm64/boot/dts/hisilicon/Makefile
@@ -0,0 +1,5 @@
+dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb
+
+always := $(dtb-y)
+subdir-y := $(dts-dirs)
+clean-files:= *.dtb
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
new file mode 100644
index 000..e36a539
--- /dev/null
+++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
@@ -0,0 +1,31 @@
+/*
+ * dts file for Hisilicon HiKey Development Board
+ *
+ * Copyright (C) 2015, Hisilicon Ltd.
+ *
+ */
+
+/dts-v1/;
+
+/*Reserved 1MB memory for MCU*/
+/memreserve/ 0x05e0 0x0010;
+
+#include hi6220.dtsi
+
+/ {
+ model = HiKey Development Board;
+ compatible = hisilicon,hi6220-hikey, hisilicon,hi6220;
+
+ aliases {
+ serial0 = uart0;
+ };
+
+ chosen {
+ stdout-path = serial0:115200n8;
+ };
+
+ memory@0 {
+ device_type = memory;
+ reg = 0x0 0x0 0x0 0x4000;
+ };
+};
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
new file mode 100644
index 000..229937f
--- /dev/null
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -0,0 +1,172 @@
+/*
+ * dts file for Hisilicon Hi6220 SoC
+ *
+ * Copyright (C) 2015, Hisilicon Ltd.
+ */
+
+#include dt-bindings/clock/hi6220-clock.h
+#include dt-bindings/interrupt-controller/arm-gic.h
+
+/ {
+ compatible = hisilicon,hi6220;
+ interrupt-parent = gic;
+ #address-cells = 2;
+ #size-cells = 2;
+
+ psci {
+ compatible = arm,psci-0.2;
+ method = smc;
+ };
+
+ cpus {
+ #address-cells = 2;
+ #size-cells = 0;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = cpu0;
+ };
+ core1 {
+ cpu = cpu1;
+ };
+ core2 {
+ cpu = cpu2;
+ };
+ core3 {
+ cpu = cpu3;
+ };
+ };
+ cluster1 {
+ core0 {
+ cpu = cpu4;
+ };
+ core1 {
+ cpu = cpu5;
+ };
+ core2 {
+ cpu = cpu6;
+ };
+ core3 {
+ cpu = cpu7;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ compatible = arm,cortex-a53, arm,armv8;
+ device_type = cpu;
+ reg = 0x0 0x0;
+ enable-method = psci;
+ };
+
+ cpu1: cpu@1 {
+ compatible = arm,cortex-a53, arm,armv8;
+ device_type = cpu;
+ reg = 0x0 0x1;
+ enable-method = psci;
+ };
+
+ cpu2: cpu@2 {
+ compatible = arm,cortex-a53
[PATCH v9 0/6] arm64,hi6220: Enable Hisilicon Hi6220 SoC
Hi6220 is one mobile solution of Hisilicon, this patchset contains initial support for Hi6220 SoC and HiKey development board, which supports octal ARM Cortex A53 cores. Initial support is minimal and includes just the arch configuration, device tree configuration, the clock driver has been picked up by clock maintainers in clk tree. PSCI is enabled in device tree and there is no problem to boot all the octal cores, and the CPU hotplug is also working now, you can download and compile the latest firmware based on the following link to run this patch set: https://github.com/96boards/documentation/wiki/UEFI Chnages v9: * Rebase to linus/master 4.1-rc1 * Remove the clock driver from this version because the clock maintainers have queued up the clock driver: git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next-hi6220 * This version also includes clock header file: [PATCH v9 6/6] dt-bindings: Add header file of hi6220 clock driver Although above patch is included in clock driver, I add to this series because the device tree file includes it, there will be compile error without it. At last, we just need to keep one when merged together. Changes v6~v8: This three versions only modified the clock drivers based on the Stephen's review advices. * clk-hi6220.c: ** Split the clock header file from clock driver ** Delete setting the parents clock of UART1 to HI6220_150M in clock driver, we can do that using assigned-clock in dts when enable UART1 in the future. * clkdivider-hi6220.c: ** Reuse some functions exported by clk-divider.c ** Remove pr_err and CLK_IS_BASIC flag ** Fix some programing style problems * hisilicon/clk.h: remove the __init markings on some funcition prototypes. Changes v5: * Rebase to kernel 4.1-rc2 * Add compatible string hisilicon,hi6220-pl011 for Hisilicon designed UART * clk-hi6220.c: use __initdata for non-const arrays based on the commit 692d8328e8c039f9497eb862c6cf835de922c061 Changes v4: * Rebase to kernel 4.1-rc1 * Delete arm,cortex-a15-gic from the gic node in dts Changes v3: * Verified the CPU hotplug based on the new released firmware * Redefined the compatible strings of four system controllers in dts * Setting COMMON_CLK_HI6220 to a bool symbol * Keep CONFGI_ARCH_HISI sorted alphabetically Changes v2: * Split the DT bindings documents into earlier patches * Change SMP enable method from spin-table to PSCI in device tree * Remove clock-frequency from armv8-timer device node in device tree * Add more description about Hisilicon designed system controllers in DT bindings document * Enable high speed clock on UART1 mux * Other changes based on the discussion in the mailing list: https://lkml.org/lkml/2015/2/5/147 Bintian Wang (6): arm64: Enable Hisilicon ARMv8 SoC family in Kconfig and defconfig arm64: hi6220: Document devicetree bindings for Hisilicon hi6220 SoC clk: hi6220: Document devicetree bindings for hi6220 clock Documentation: DT: PL011: hi6220: add compatible string for Hisilicon designed UART arm64: dts: Add dts files for Hisilicon Hi6220 SoC dt-bindings: Add header file of hi6220 clock driver .../bindings/arm/hisilicon/hisilicon.txt | 87 ++ .../devicetree/bindings/clock/hi6220-clock.txt | 34 Documentation/devicetree/bindings/serial/pl011.txt |4 +- arch/arm64/Kconfig |5 + arch/arm64/boot/dts/Makefile |1 + arch/arm64/boot/dts/hisilicon/Makefile |5 + arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 31 arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 172 +++ arch/arm64/configs/defconfig |1 + include/dt-bindings/clock/hi6220-clock.h | 173 10 files changed, 512 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/clock/hi6220-clock.txt create mode 100644 arch/arm64/boot/dts/hisilicon/Makefile create mode 100644 arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts create mode 100644 arch/arm64/boot/dts/hisilicon/hi6220.dtsi create mode 100644 include/dt-bindings/clock/hi6220-clock.h -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v9 2/6] arm64: hi6220: Document devicetree bindings for Hisilicon hi6220 SoC
This patch adds documentation for the devicetree bindings used by the
DT files of Hisilicon hi6220 SoC mobile platform.
Signed-off-by: Bintian Wang bintian.w...@huawei.com
Suggested-by: Arnd Bergmann a...@arndb.de
Acked-by: Haojian Zhuang haojian.zhu...@linaro.org
Acked-by: Stephen Boyd sb...@codeaurora.org
---
.../bindings/arm/hisilicon/hisilicon.txt | 87
1 file changed, 87 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
index 35b1bd4..f67d0f3 100644
--- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
+++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
@@ -1,5 +1,8 @@
Hisilicon Platforms Device Tree Bindings
+Hi6220 SoC
+Required root node properties:
+ - compatible = hisilicon,hi6220;
Hi4511 Board
Required root node properties:
@@ -13,6 +16,9 @@ HiP01 ca9x2 Board
Required root node properties:
- compatible = hisilicon,hip01-ca9x2;
+HiKey Board
+Required root node properties:
+ - compatible = hisilicon,hi6220-hikey, hisilicon,hi6220;
Hisilicon system controller
@@ -41,6 +47,87 @@ Example:
};
---
+Hisilicon Hi6220 system controller
+
+Required properties:
+- compatible : hisilicon,hi6220-sysctrl
+- reg : Register address and size
+- #clock-cells: should be set to 1, many clock registers are defined
+ under this controller and this property must be present.
+
+Hisilicon designs this controller as one of the system controllers,
+its main functions are the same as Hisilicon system controller, but
+the register offset of some core modules are different.
+
+Example:
+ /*for Hi6220*/
+ sys_ctrl: sys_ctrl {
+ compatible = hisilicon,hi6220-sysctrl, syscon;
+ reg = 0x0 0xf703 0x0 0x2000;
+ #clock-cells = 1;
+ };
+
+
+Hisilicon Hi6220 Power Always ON domain controller
+
+Required properties:
+- compatible : hisilicon,hi6220-aoctrl
+- reg : Register address and size
+- #clock-cells: should be set to 1, many clock registers are defined
+ under this controller and this property must be present.
+
+Hisilicon designs this system controller to control the power always
+on domain for mobile platform.
+
+Example:
+ /*for Hi6220*/
+ ao_ctrl: ao_ctrl {
+ compatible = hisilicon,hi6220-aoctrl, syscon;
+ reg = 0x0 0xf780 0x0 0x2000;
+ #clock-cells = 1;
+ };
+
+
+Hisilicon Hi6220 Media domain controller
+
+Required properties:
+- compatible : hisilicon,hi6220-mediactrl
+- reg : Register address and size
+- #clock-cells: should be set to 1, many clock registers are defined
+ under this controller and this property must be present.
+
+Hisilicon designs this system controller to control the multimedia
+domain(e.g. codec, G3D ...) for mobile platform.
+
+Example:
+ /*for Hi6220*/
+ media_ctrl: media_ctrl {
+ compatible = hisilicon,hi6220-mediactrl, syscon;
+ reg = 0x0 0xf441 0x0 0x1000;
+ #clock-cells = 1;
+ };
+
+
+Hisilicon Hi6220 Power Management domain controller
+
+Required properties:
+- compatible : hisilicon,hi6220-pmctrl
+- reg : Register address and size
+- #clock-cells: should be set to 1, some clock registers are define
+ under this controller and this property must be present.
+
+Hisilicon designs this system controller to control the power management
+domain for mobile platform.
+
+Example:
+ /*for Hi6220*/
+ pm_ctrl: pm_ctrl {
+ compatible = hisilicon,hi6220-pmctrl, syscon;
+ reg = 0x0 0xf7032000 0x0 0x1000;
+ #clock-cells = 1;
+ };
+
+---
Hisilicon HiP01 system controller
Required properties:
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[PATCH v9 3/6] clk: hi6220: Document devicetree bindings for hi6220 clock
Document DT files bindings for Hisilicon hi6220 clock.
Signed-off-by: Bintian Wang bintian.w...@huawei.com
Acked-by: Haojian Zhuang haojian.zhu...@linaro.org
Suggested-by: Arnd Bergmann a...@arndb.de
Acked-by: Stephen Boyd sb...@codeaurora.org
---
.../devicetree/bindings/clock/hi6220-clock.txt | 34
1 file changed, 34 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/hi6220-clock.txt
diff --git a/Documentation/devicetree/bindings/clock/hi6220-clock.txt
b/Documentation/devicetree/bindings/clock/hi6220-clock.txt
new file mode 100644
index 000..53ddb19
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/hi6220-clock.txt
@@ -0,0 +1,34 @@
+* Hisilicon Hi6220 Clock Controller
+
+Clock control registers reside in different Hi6220 system controllers,
+please refer the following document to know more about the binding rules
+for these system controllers:
+
+Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
+
+Required Properties:
+
+- compatible: the compatible should be one of the following strings to
+ indicate the clock controller functionality.
+
+ - hisilicon,hi6220-aoctrl
+ - hisilicon,hi6220-sysctrl
+ - hisilicon,hi6220-mediactrl
+ - hisilicon,hi6220-pmctrl
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- #clock-cells: should be 1.
+
+For example:
+ sys_ctrl: sys_ctrl {
+ compatible = hisilicon,hi6220-sysctrl, syscon;
+ reg = 0x0 0xf703 0x0 0x2000;
+ #clock-cells = 1;
+ };
+
+Each clock is assigned an identifier and client nodes use this identifier
+to specify the clock which they consume.
+
+All these identifier could be found in dt-bindings/clock/hi6220-clock.h.
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v8 6/7] clk: hi6220: Clock driver support for Hisilicon hi6220 SoC
Hello Mike, On 2015/5/29 9:07, Michael Turquette wrote: Quoting Kevin Hilman (2015-05-28 10:32:05) Bintian writes: Hello Mike, On 2015/5/28 13:26, Michael Turquette wrote: Quoting Bintian Wang (2015-05-23 21:11:11) Add clock drivers for hi6220 SoC, this driver controls the SoC registers to supply different clocks to different IPs in the SoC. We add one divider clock for hi6220 because the divider in hi6220 also has a mask bit but it doesnot obey the rule defined by flag "CLK_DIVIDER_HIWORD_MASK", we can not get index of the mask bit by left shift fixed bits (e.g. 16 bits), so we add this divider clock to handle it. Signed-off-by: Jorge Ramirez-Ortiz Signed-off-by: Bintian Wang Acked-by: Haojian Zhuang Reviewed-by: Zhangfei Gao Tested-by: Will Deacon Tested-by: Tyler Baker Hi Bintian, Thanks for making the changes requested by Stephen. I've taken his patch to add assigned-clock-rate/parent support for AMBA interconnects and applied it to 4.1-rc1, and then I've applied your v8 patches #4-6 on top of that. You can find it at: git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next-hi6220 Thank you very much! I think you also need to pick patch "[PATCH v5 3/6] clk: hi6220: Document devicetree bindings for hi6220 clock", which described the dt binding of clk, and it is also acked by Stephen(v4 is the same to v5). I have merged this into clk-next so it can get some cycles in linux-next. Stephen, Can you send your patch out to Russell properly? It needs his ack (or for him to take it outright) in order to unblock the hi6220 clock driver from being merged. It doesn't block hi6220 clock driver now, because the UART1 is not enabled in hi6220 dts now. Now that the clk changes are queued up, can you (re)post the remaining hikey patches with a changelog stating the dependency on the clk-next branch. I believe what's left is just the DT and Kconfig/defconfig changes, correct? Just to be clear, clk-next-hi6220 is not an immutable branch. I just put it up to get some testing done on it. Depending on whether or not Russell acks Stephen's patch then it may be changed. Stephen's patch can help UART1 to switch to the higher clock, so we can remove the "clk_set_parent" from the "clk-hi6220.c" safely and don't need to do that workaround in advance. You know, we don't enable the UART1 in this series, and we can submit other patch to enable it after Stephen's patch is merged. Thanks, Bintian Regards, Mike With some acks from the DT maintainers, these should be ready to be merged through arm-soc. Thanks, Kevin . -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v8 4/7] clk: hisilicon: Remove __init for marking function prototypes
Hello Kevin, On 2015/5/29 0:50, Kevin Hilman wrote: Bintian Wang writes: __init markings on function prototypes are useless, so remove them. Suggested-by: Stephen Boyd Signed-off-by: Bintian Wang Can you repost the whole series please? The number of patches has increased and it's not terribly obvious how to combine your v7 or v8 patches with the v8 patches for proper testing. I have sent the whole series, please help check. Thanks, Bintian Thanks, Kevin . -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v8 5/7] dt-bindings: Add header file of hi6220 clock driver
Add the header file "hi6220-clock.h" used by both hi6220 clock driver and hi6220 device tree file. Suggested-by: Stephen Boyd Signed-off-by: Bintian Wang Tested-by: Will Deacon Tested-by: Tyler Baker Tested-by: Kevin Hilman --- include/dt-bindings/clock/hi6220-clock.h | 173 +++ 1 file changed, 173 insertions(+) create mode 100644 include/dt-bindings/clock/hi6220-clock.h diff --git a/include/dt-bindings/clock/hi6220-clock.h b/include/dt-bindings/clock/hi6220-clock.h new file mode 100644 index 000..70ee383 --- /dev/null +++ b/include/dt-bindings/clock/hi6220-clock.h @@ -0,0 +1,173 @@ +/* + * Copyright (c) 2015 Hisilicon Limited. + * + * Author: Bintian Wang + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __DT_BINDINGS_CLOCK_HI6220_H +#define __DT_BINDINGS_CLOCK_HI6220_H + +/* clk in Hi6220 AO (always on) controller */ +#define HI6220_NONE_CLOCK 0 + +/* fixed rate clocks */ +#define HI6220_REF32K 1 +#define HI6220_CLK_TCXO2 +#define HI6220_MMC1_PAD3 +#define HI6220_MMC2_PAD4 +#define HI6220_MMC0_PAD5 +#define HI6220_PLL_BBP 6 +#define HI6220_PLL_GPU 7 +#define HI6220_PLL1_DDR8 +#define HI6220_PLL_SYS 9 +#define HI6220_PLL_SYS_MEDIA 10 +#define HI6220_DDR_SRC 11 +#define HI6220_PLL_MEDIA 12 +#define HI6220_PLL_DDR 13 + +/* fixed factor clocks */ +#define HI6220_300M14 +#define HI6220_150M15 +#define HI6220_PICOPHY_SRC 16 +#define HI6220_MMC0_SRC_SEL17 +#define HI6220_MMC1_SRC_SEL18 +#define HI6220_MMC2_SRC_SEL19 +#define HI6220_VPU_CODEC 20 +#define HI6220_MMC0_SMP21 +#define HI6220_MMC1_SMP22 +#define HI6220_MMC2_SMP23 + +/* gate clocks */ +#define HI6220_WDT0_PCLK 24 +#define HI6220_WDT1_PCLK 25 +#define HI6220_WDT2_PCLK 26 +#define HI6220_TIMER0_PCLK 27 +#define HI6220_TIMER1_PCLK 28 +#define HI6220_TIMER2_PCLK 29 +#define HI6220_TIMER3_PCLK 30 +#define HI6220_TIMER4_PCLK 31 +#define HI6220_TIMER5_PCLK 32 +#define HI6220_TIMER6_PCLK 33 +#define HI6220_TIMER7_PCLK 34 +#define HI6220_TIMER8_PCLK 35 +#define HI6220_UART0_PCLK 36 + +#define HI6220_AO_NR_CLKS 37 + +/* clk in Hi6220 systrl */ +/* gate clock */ +#define HI6220_MMC0_CLK1 +#define HI6220_MMC0_CIUCLK 2 +#define HI6220_MMC1_CLK3 +#define HI6220_MMC1_CIUCLK 4 +#define HI6220_MMC2_CLK5 +#define HI6220_MMC2_CIUCLK 6 +#define HI6220_USBOTG_HCLK 7 +#define HI6220_CLK_PICOPHY 8 +#define HI6220_HIFI9 +#define HI6220_DACODEC_PCLK10 +#define HI6220_EDMAC_ACLK 11 +#define HI6220_CS_ATB 12 +#define HI6220_I2C0_CLK13 +#define HI6220_I2C1_CLK14 +#define HI6220_I2C2_CLK15 +#define HI6220_I2C3_CLK16 +#define HI6220_UART1_PCLK 17 +#define HI6220_UART2_PCLK 18 +#define HI6220_UART3_PCLK 19 +#define HI6220_UART4_PCLK 20 +#define HI6220_SPI_CLK 21 +#define HI6220_TSENSOR_CLK 22 +#define HI6220_MMU_CLK 23 +#define HI6220_HIFI_SEL24 +#define HI6220_MMC0_SYSPLL 25 +#define HI6220_MMC1_SYSPLL 26 +#define HI6220_MMC2_SYSPLL 27 +#define HI6220_MMC0_SEL28 +#define HI6220_MMC1_SEL29 +#define HI6220_BBPPLL_SEL 30 +#define HI6220_MEDIA_PLL_SRC 31 +#define HI6220_MMC2_SEL32 +#define HI6220_CS_ATB_SYSPLL 33 + +/* mux clocks */ +#define HI6220_MMC0_SRC34 +#define HI6220_MMC0_SMP_IN 35 +#define HI6220_MMC1_SRC36 +#define HI6220_MMC1_SMP_IN 37 +#define HI6220_MMC2_SRC38 +#define HI6220_MMC2_SMP_IN 39 +#define HI6220_HIFI_SRC40 +#define HI6220_UART1_SRC 41 +#define HI6220_UART2_SRC 42 +#define HI6220_UART3_SRC 43 +#define HI6220_UART4_SRC 44 +#define HI6220_MMC0_MUX0 45 +#define HI6220_MMC1_MUX0 46 +#define HI6220_MMC2_MUX0 47 +#define HI6220_MMC0_MUX1 48 +#define HI6220_MMC1_MUX1 49 +#define HI6220_MMC2_MUX1 50 + +/* divider clocks */ +#define HI6220_CLK_BUS 51 +#define HI6220_MMC0_DIV52 +#define HI6220_MMC1_DIV53 +#define HI6220_MMC2_DIV54 +#define HI6220_HIFI_DIV55 +#define HI6220_BBPPLL0_DIV 56 +#define HI6220_CS_DAPB 57 +#define HI6220_CS_ATB_DIV 58 + +#define HI6220_SYS_NR_CLKS 59 + +/* clk in Hi6220 media controller */ +/* gate clocks */ +#define HI6220_DSI_PCLK1 +#define HI6220_G3D_PCLK2 +#define HI6220_ACLK_CODEC_VPU
[PATCH v8 6/7] clk: hi6220: Clock driver support for Hisilicon hi6220 SoC
Add clock drivers for hi6220 SoC, this driver controls the SoC
registers to supply different clocks to different IPs in the SoC.
We add one divider clock for hi6220 because the divider in hi6220
also has a mask bit but it doesnot obey the rule defined by flag
"CLK_DIVIDER_HIWORD_MASK", we can not get index of the mask bit by
left shift fixed bits (e.g. 16 bits), so we add this divider clock
to handle it.
Signed-off-by: Jorge Ramirez-Ortiz
Signed-off-by: Bintian Wang
Acked-by: Haojian Zhuang
Reviewed-by: Zhangfei Gao
Tested-by: Will Deacon
Tested-by: Tyler Baker
Tested-by: Kevin Hilman
---
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile | 4 +-
drivers/clk/hisilicon/Kconfig | 6 +
drivers/clk/hisilicon/Makefile| 3 +-
drivers/clk/hisilicon/clk-hi6220.c| 284 ++
drivers/clk/hisilicon/clk.c | 29 +++
drivers/clk/hisilicon/clk.h | 17 ++
drivers/clk/hisilicon/clkdivider-hi6220.c | 156
8 files changed, 496 insertions(+), 4 deletions(-)
create mode 100644 drivers/clk/hisilicon/Kconfig
create mode 100644 drivers/clk/hisilicon/clk-hi6220.c
create mode 100644 drivers/clk/hisilicon/clkdivider-hi6220.c
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index de8c58f..cd6029d4 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -151,6 +151,7 @@ config COMMON_CLK_CDCE706
This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
source "drivers/clk/bcm/Kconfig"
+source "drivers/clk/hisilicon/Kconfig"
source "drivers/clk/qcom/Kconfig"
endmenu
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index d2d5e6c..440ef72 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -47,9 +47,7 @@ obj-$(CONFIG_COMMON_CLK_PWM) += clk-pwm.o
obj-$(CONFIG_COMMON_CLK_AT91) += at91/
obj-$(CONFIG_ARCH_BCM_MOBILE) += bcm/
obj-$(CONFIG_ARCH_BERLIN) += berlin/
-obj-$(CONFIG_ARCH_HI3xxx) += hisilicon/
-obj-$(CONFIG_ARCH_HIP04) += hisilicon/
-obj-$(CONFIG_ARCH_HIX5HD2) += hisilicon/
+obj-$(CONFIG_ARCH_HISI)+= hisilicon/
obj-$(CONFIG_ARCH_MXC) += imx/
obj-$(CONFIG_COMMON_CLK_KEYSTONE) += keystone/
obj-$(CONFIG_ARCH_MEDIATEK)+= mediatek/
diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
new file mode 100644
index 000..b4165ba
--- /dev/null
+++ b/drivers/clk/hisilicon/Kconfig
@@ -0,0 +1,6 @@
+config COMMON_CLK_HI6220
+ bool "Hi6220 Clock Driver"
+ depends on ARCH_HISI || COMPILE_TEST
+ default ARCH_HISI
+ help
+ Build the Hisilicon Hi6220 clock driver based on the common clock
framework.
diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile
index 038c02f..48f0116 100644
--- a/drivers/clk/hisilicon/Makefile
+++ b/drivers/clk/hisilicon/Makefile
@@ -2,8 +2,9 @@
# Hisilicon Clock specific Makefile
#
-obj-y += clk.o clkgate-separated.o
+obj-y += clk.o clkgate-separated.o clkdivider-hi6220.o
obj-$(CONFIG_ARCH_HI3xxx) += clk-hi3620.o
obj-$(CONFIG_ARCH_HIP04) += clk-hip04.o
obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o
+obj-$(CONFIG_COMMON_CLK_HI6220)+= clk-hi6220.o
diff --git a/drivers/clk/hisilicon/clk-hi6220.c
b/drivers/clk/hisilicon/clk-hi6220.c
new file mode 100644
index 000..4563343
--- /dev/null
+++ b/drivers/clk/hisilicon/clk-hi6220.c
@@ -0,0 +1,284 @@
+/*
+ * Hisilicon Hi6220 clock driver
+ *
+ * Copyright (c) 2015 Hisilicon Limited.
+ *
+ * Author: Bintian Wang
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include "clk.h"
+
+
+/* clocks in AO (always on) controller */
+static struct hisi_fixed_rate_clock hi6220_fixed_rate_clks[] __initdata = {
+ { HI6220_REF32K,"ref32k", NULL, CLK_IS_ROOT, 32764, },
+ { HI6220_CLK_TCXO, "clk_tcxo", NULL, CLK_IS_ROOT, 1920, },
+ { HI6220_MMC1_PAD, "mmc1_pad", NULL, CLK_IS_ROOT, 1, },
+ { HI6220_MMC2_PAD, "mmc2_pad", NULL, CLK_IS_ROOT, 1, },
+ { HI6220_MMC0_PAD, "mmc0_pad", NULL, CLK_IS_ROOT, 2, },
+ { HI6220_PLL_BBP, "bbppll0", NULL, CLK_IS_ROOT, 24576, },
+ { HI6220_PLL_GPU, "gpupll", NULL, CLK_IS_ROOT, 10,},
+ { HI6220_PLL1_DDR, "ddrpll1", NULL, CLK_IS_ROOT, 106600,},
+ { HI6220_PLL_SYS, "syspll", NULL, CLK_IS_ROOT, 12
[PATCH v8 2/7] clk: hi6220: Document devicetree bindings for hi6220 clock
Document DT files bindings for Hisilicon hi6220 clock.
Signed-off-by: Bintian Wang
Acked-by: Haojian Zhuang
Suggested-by: Arnd Bergmann
Acked-by: Stephen Boyd
---
.../devicetree/bindings/clock/hi6220-clock.txt | 34 ++
1 file changed, 34 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/hi6220-clock.txt
diff --git a/Documentation/devicetree/bindings/clock/hi6220-clock.txt
b/Documentation/devicetree/bindings/clock/hi6220-clock.txt
new file mode 100644
index 000..53ddb19
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/hi6220-clock.txt
@@ -0,0 +1,34 @@
+* Hisilicon Hi6220 Clock Controller
+
+Clock control registers reside in different Hi6220 system controllers,
+please refer the following document to know more about the binding rules
+for these system controllers:
+
+Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
+
+Required Properties:
+
+- compatible: the compatible should be one of the following strings to
+ indicate the clock controller functionality.
+
+ - "hisilicon,hi6220-aoctrl"
+ - "hisilicon,hi6220-sysctrl"
+ - "hisilicon,hi6220-mediactrl"
+ - "hisilicon,hi6220-pmctrl"
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- #clock-cells: should be 1.
+
+For example:
+ sys_ctrl: sys_ctrl {
+ compatible = "hisilicon,hi6220-sysctrl", "syscon";
+ reg = <0x0 0xf703 0x0 0x2000>;
+ #clock-cells = <1>;
+ };
+
+Each clock is assigned an identifier and client nodes use this identifier
+to specify the clock which they consume.
+
+All these identifier could be found in .
--
1.9.1
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[PATCH v8 7/7] arm64: dts: Add dts files for Hisilicon Hi6220 SoC
Add initial dtsi file to support Hisilicon Hi6220 SoC with
support of Octal core CPUs in two clusters and each cluster
has quard Cortex-A53.
Also add dts file to support HiKey development board which
based on Hi6220 SoC.
Signed-off-by: Bintian Wang
Acked-by: Haojian Zhuang
Reviewed-by: Yiping Xu
Tested-by: Will Deacon
Tested-by: Tyler Baker
Tested-by: Kevin Hilman
---
arch/arm64/boot/dts/Makefile | 1 +
arch/arm64/boot/dts/hisilicon/Makefile | 5 +
arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 31 +
arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 172 +
4 files changed, 209 insertions(+)
create mode 100644 arch/arm64/boot/dts/hisilicon/Makefile
create mode 100644 arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
create mode 100644 arch/arm64/boot/dts/hisilicon/hi6220.dtsi
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index ad26a75..38913be 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -4,6 +4,7 @@ dts-dirs += arm
dts-dirs += cavium
dts-dirs += exynos
dts-dirs += freescale
+dts-dirs += hisilicon
dts-dirs += mediatek
dts-dirs += qcom
dts-dirs += sprd
diff --git a/arch/arm64/boot/dts/hisilicon/Makefile
b/arch/arm64/boot/dts/hisilicon/Makefile
new file mode 100644
index 000..fa81a6e
--- /dev/null
+++ b/arch/arm64/boot/dts/hisilicon/Makefile
@@ -0,0 +1,5 @@
+dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb
+
+always := $(dtb-y)
+subdir-y := $(dts-dirs)
+clean-files:= *.dtb
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
new file mode 100644
index 000..e36a539
--- /dev/null
+++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
@@ -0,0 +1,31 @@
+/*
+ * dts file for Hisilicon HiKey Development Board
+ *
+ * Copyright (C) 2015, Hisilicon Ltd.
+ *
+ */
+
+/dts-v1/;
+
+/*Reserved 1MB memory for MCU*/
+/memreserve/ 0x05e0 0x0010;
+
+#include "hi6220.dtsi"
+
+/ {
+ model = "HiKey Development Board";
+ compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220";
+
+ aliases {
+ serial0 =
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x4000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
new file mode 100644
index 000..229937f
--- /dev/null
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -0,0 +1,172 @@
+/*
+ * dts file for Hisilicon Hi6220 SoC
+ *
+ * Copyright (C) 2015, Hisilicon Ltd.
+ */
+
+#include
+#include
+
+/ {
+ compatible = "hisilicon,hi6220";
+ interrupt-parent = <>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <>;
+ };
+ core1 {
+ cpu = <>;
+ };
+ core2 {
+ cpu = <>;
+ };
+ core3 {
+ cpu = <>;
+ };
+ };
+ cluster1 {
+ core0 {
+ cpu = <>;
+ };
+ core1 {
+ cpu = <>;
+ };
+ core2 {
+ cpu = <>;
+ };
+ core3 {
+ cpu = <>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x1>;
+ enable-method = &q
[PATCH v8 1/7] arm64: hi6220: Document devicetree bindings for Hisilicon hi6220 SoC
This patch adds documentation for the devicetree bindings used by the
DT files of Hisilicon hi6220 SoC mobile platform.
Signed-off-by: Bintian Wang
Suggested-by: Arnd Bergmann
Acked-by: Haojian Zhuang
Acked-by: Stephen Boyd
---
.../bindings/arm/hisilicon/hisilicon.txt | 87 ++
1 file changed, 87 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
index 35b1bd4..f67d0f3 100644
--- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
+++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
@@ -1,5 +1,8 @@
Hisilicon Platforms Device Tree Bindings
+Hi6220 SoC
+Required root node properties:
+ - compatible = "hisilicon,hi6220";
Hi4511 Board
Required root node properties:
@@ -13,6 +16,9 @@ HiP01 ca9x2 Board
Required root node properties:
- compatible = "hisilicon,hip01-ca9x2";
+HiKey Board
+Required root node properties:
+ - compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220";
Hisilicon system controller
@@ -41,6 +47,87 @@ Example:
};
---
+Hisilicon Hi6220 system controller
+
+Required properties:
+- compatible : "hisilicon,hi6220-sysctrl"
+- reg : Register address and size
+- #clock-cells: should be set to 1, many clock registers are defined
+ under this controller and this property must be present.
+
+Hisilicon designs this controller as one of the system controllers,
+its main functions are the same as Hisilicon system controller, but
+the register offset of some core modules are different.
+
+Example:
+ /*for Hi6220*/
+ sys_ctrl: sys_ctrl {
+ compatible = "hisilicon,hi6220-sysctrl", "syscon";
+ reg = <0x0 0xf703 0x0 0x2000>;
+ #clock-cells = <1>;
+ };
+
+
+Hisilicon Hi6220 Power Always ON domain controller
+
+Required properties:
+- compatible : "hisilicon,hi6220-aoctrl"
+- reg : Register address and size
+- #clock-cells: should be set to 1, many clock registers are defined
+ under this controller and this property must be present.
+
+Hisilicon designs this system controller to control the power always
+on domain for mobile platform.
+
+Example:
+ /*for Hi6220*/
+ ao_ctrl: ao_ctrl {
+ compatible = "hisilicon,hi6220-aoctrl", "syscon";
+ reg = <0x0 0xf780 0x0 0x2000>;
+ #clock-cells = <1>;
+ };
+
+
+Hisilicon Hi6220 Media domain controller
+
+Required properties:
+- compatible : "hisilicon,hi6220-mediactrl"
+- reg : Register address and size
+- #clock-cells: should be set to 1, many clock registers are defined
+ under this controller and this property must be present.
+
+Hisilicon designs this system controller to control the multimedia
+domain(e.g. codec, G3D ...) for mobile platform.
+
+Example:
+ /*for Hi6220*/
+ media_ctrl: media_ctrl {
+ compatible = "hisilicon,hi6220-mediactrl", "syscon";
+ reg = <0x0 0xf441 0x0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+
+Hisilicon Hi6220 Power Management domain controller
+
+Required properties:
+- compatible : "hisilicon,hi6220-pmctrl"
+- reg : Register address and size
+- #clock-cells: should be set to 1, some clock registers are define
+ under this controller and this property must be present.
+
+Hisilicon designs this system controller to control the power management
+domain for mobile platform.
+
+Example:
+ /*for Hi6220*/
+ pm_ctrl: pm_ctrl {
+ compatible = "hisilicon,hi6220-pmctrl", "syscon";
+ reg = <0x0 0xf7032000 0x0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+---
Hisilicon HiP01 system controller
Required properties:
--
1.9.1
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[PATCH v8 4/7] clk: hisilicon: Remove __init for marking function prototypes
__init markings on function prototypes are useless, so remove them. Suggested-by: Stephen Boyd Signed-off-by: Bintian Wang Tested-by: Will Deacon Tested-by: Tyler Baker Tested-by: Kevin Hilman --- drivers/clk/hisilicon/clk.h | 22 +++--- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/clk/hisilicon/clk.h b/drivers/clk/hisilicon/clk.h index 31083ff..6b6f994 100644 --- a/drivers/clk/hisilicon/clk.h +++ b/drivers/clk/hisilicon/clk.h @@ -95,17 +95,17 @@ struct clk *hisi_register_clkgate_sep(struct device *, const char *, void __iomem *, u8, u8, spinlock_t *); -struct hisi_clock_data __init *hisi_clk_init(struct device_node *, int); -void __init hisi_clk_register_fixed_rate(struct hisi_fixed_rate_clock *, - int, struct hisi_clock_data *); -void __init hisi_clk_register_fixed_factor(struct hisi_fixed_factor_clock *, - int, struct hisi_clock_data *); -void __init hisi_clk_register_mux(struct hisi_mux_clock *, int, +struct hisi_clock_data *hisi_clk_init(struct device_node *, int); +void hisi_clk_register_fixed_rate(struct hisi_fixed_rate_clock *, + int, struct hisi_clock_data *); +void hisi_clk_register_fixed_factor(struct hisi_fixed_factor_clock *, + int, struct hisi_clock_data *); +void hisi_clk_register_mux(struct hisi_mux_clock *, int, struct hisi_clock_data *); -void __init hisi_clk_register_divider(struct hisi_divider_clock *, +void hisi_clk_register_divider(struct hisi_divider_clock *, + int, struct hisi_clock_data *); +void hisi_clk_register_gate(struct hisi_gate_clock *, + int, struct hisi_clock_data *); +void hisi_clk_register_gate_sep(struct hisi_gate_clock *, int, struct hisi_clock_data *); -void __init hisi_clk_register_gate(struct hisi_gate_clock *, - int, struct hisi_clock_data *); -void __init hisi_clk_register_gate_sep(struct hisi_gate_clock *, - int, struct hisi_clock_data *); #endif /* __HISI_CLK_H */ -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v8 0/7] arm64,hi6220: Enable Hisilicon Hi6220 SoC
From: Bintian Wang Hi6220 is one mobile solution of Hisilicon, this patchset contains initial support for Hi6220 SoC and HiKey development board, which supports octal ARM Cortex A53 cores. Initial support is minimal and includes just the arch configuration, clock driver, device tree configuration. PSCI is enabled in device tree and there is no problem to boot all the octal cores, and the CPU hotplug is also working now, you can download and compile the latest firmware based on the following link to run this patch set: https://github.com/96boards/documentation/wiki/UEFI Changes v6~v8: This three versions only modified the clock drivers based on the Stephen's review advices. * clk-hi6220.c: ** Split the clock header file from clock driver ** Delete setting the parents clock of UART1 to HI6220_150M in clock driver, we can do that using assigned-clock in dts when enable UART1 in the future. * clkdivider-hi6220.c: ** Reuse some functions exported by clk-divider.c ** Remove "pr_err" and CLK_IS_BASIC flag ** Fix some programing style problems * hisilicon/clk.h: remove the "__init" markings on some funcition prototypes. Changes v5: * Rebase to kernel 4.1-rc2 * Add compatible string "hisilicon,hi6220-pl011" for Hisilicon designed UART * clk-hi6220.c: use __initdata for non-const arrays based on the commit 692d8328e8c039f9497eb862c6cf835de922c061 Changes v4: * Rebase to kernel 4.1-rc1 * Delete "arm,cortex-a15-gic" from the gic node in dts Changes v3: * Verified the CPU hotplug based on the new released firmware * Redefined the compatible strings of four system controllers in dts * Setting COMMON_CLK_HI6220 to a bool symbol * Keep CONFGI_ARCH_HISI sorted alphabetically Changes v2: * Split the DT bindings documents into earlier patches * Change SMP enable method from spin-table to PSCI in device tree * Remove "clock-frequency" from armv8-timer device node in device tree * Add more description about Hisilicon designed system controllers in DT bindings document * Enable high speed clock on UART1 mux * Other changes based on the discussion in the mailing list: https://lkml.org/lkml/2015/2/5/147 Bintian Wang (7): arm64: hi6220: Document devicetree bindings for Hisilicon hi6220 SoC clk: hi6220: Document devicetree bindings for hi6220 clock Documentation: DT: PL011: hi6220: add compatible string for Hisilicon designed UART clk: hisilicon: Remove __init for marking function prototypes dt-bindings: Add header file of hi6220 clock driver clk: hi6220: Clock driver support for Hisilicon hi6220 SoC arm64: dts: Add dts files for Hisilicon Hi6220 SoC .../bindings/arm/hisilicon/hisilicon.txt | 87 +++ .../devicetree/bindings/clock/hi6220-clock.txt | 34 +++ Documentation/devicetree/bindings/serial/pl011.txt | 4 +- arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/hisilicon/Makefile | 5 + arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 31 +++ arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 172 + drivers/clk/Kconfig| 1 + drivers/clk/Makefile | 4 +- drivers/clk/hisilicon/Kconfig | 6 + drivers/clk/hisilicon/Makefile | 3 +- drivers/clk/hisilicon/clk-hi6220.c | 284 + drivers/clk/hisilicon/clk.c| 29 +++ drivers/clk/hisilicon/clk.h| 39 ++- drivers/clk/hisilicon/clkdivider-hi6220.c | 156 +++ include/dt-bindings/clock/hi6220-clock.h | 173 + 16 files changed, 1013 insertions(+), 16 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/hi6220-clock.txt create mode 100644 arch/arm64/boot/dts/hisilicon/Makefile create mode 100644 arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts create mode 100644 arch/arm64/boot/dts/hisilicon/hi6220.dtsi create mode 100644 drivers/clk/hisilicon/Kconfig create mode 100644 drivers/clk/hisilicon/clk-hi6220.c create mode 100644 drivers/clk/hisilicon/clkdivider-hi6220.c create mode 100644 include/dt-bindings/clock/hi6220-clock.h -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v8 3/7] Documentation: DT: PL011: hi6220: add compatible string for Hisilicon designed UART
Hisilicon does some performance enhancements based on PL011(e.g. larger FIFO length), so add one compatible string "hisilicon,hi6220-uart" for future optimisations or workarounds works. Signed-off-by: Bintian Wang Suggested-by: Mark Rutland --- Documentation/devicetree/bindings/serial/pl011.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/serial/pl011.txt b/Documentation/devicetree/bindings/serial/pl011.txt index ba3ecb8..cb9fd9d 100644 --- a/Documentation/devicetree/bindings/serial/pl011.txt +++ b/Documentation/devicetree/bindings/serial/pl011.txt @@ -1,7 +1,9 @@ * ARM AMBA Primecell PL011 serial UART Required properties: -- compatible: must be "arm,primecell", "arm,pl011" +- compatible: should contain one of the following sequences: + * "arm,pl011", "arm,primecell" + * "hisilicon,hi6220-pl011", "arm,pl011", "arm,primecell" - reg: exactly one register range with length 0x1000 - interrupts: exactly one interrupt specifier -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v8 6/7] clk: hi6220: Clock driver support for Hisilicon hi6220 SoC
Hello Kevin, On 2015/5/29 1:32, Kevin Hilman wrote: Bintian writes: Hello Mike, On 2015/5/28 13:26, Michael Turquette wrote: Quoting Bintian Wang (2015-05-23 21:11:11) Add clock drivers for hi6220 SoC, this driver controls the SoC registers to supply different clocks to different IPs in the SoC. We add one divider clock for hi6220 because the divider in hi6220 also has a mask bit but it doesnot obey the rule defined by flag "CLK_DIVIDER_HIWORD_MASK", we can not get index of the mask bit by left shift fixed bits (e.g. 16 bits), so we add this divider clock to handle it. Signed-off-by: Jorge Ramirez-Ortiz Signed-off-by: Bintian Wang Acked-by: Haojian Zhuang Reviewed-by: Zhangfei Gao Tested-by: Will Deacon Tested-by: Tyler Baker Hi Bintian, Thanks for making the changes requested by Stephen. I've taken his patch to add assigned-clock-rate/parent support for AMBA interconnects and applied it to 4.1-rc1, and then I've applied your v8 patches #4-6 on top of that. You can find it at: git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next-hi6220 Thank you very much! I think you also need to pick patch "[PATCH v5 3/6] clk: hi6220: Document devicetree bindings for hi6220 clock", which described the dt binding of clk, and it is also acked by Stephen(v4 is the same to v5). I have merged this into clk-next so it can get some cycles in linux-next. Stephen, Can you send your patch out to Russell properly? It needs his ack (or for him to take it outright) in order to unblock the hi6220 clock driver from being merged. It doesn't block hi6220 clock driver now, because the UART1 is not enabled in hi6220 dts now. Now that the clk changes are queued up, can you (re)post the remaining hikey patches with a changelog stating the dependency on the clk-next branch. I believe what's left is just the DT and Kconfig/defconfig changes, correct? Yes, you are right. I will post the remaining hikey patches soon. Thank you Kevin, BR, Bintian With some acks from the DT maintainers, these should be ready to be merged through arm-soc. Thanks, Kevin . -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v8 6/7] clk: hi6220: Clock driver support for Hisilicon hi6220 SoC
Hello Mike, On 2015/5/28 13:26, Michael Turquette wrote: Quoting Bintian Wang (2015-05-23 21:11:11) Add clock drivers for hi6220 SoC, this driver controls the SoC registers to supply different clocks to different IPs in the SoC. We add one divider clock for hi6220 because the divider in hi6220 also has a mask bit but it doesnot obey the rule defined by flag "CLK_DIVIDER_HIWORD_MASK", we can not get index of the mask bit by left shift fixed bits (e.g. 16 bits), so we add this divider clock to handle it. Signed-off-by: Jorge Ramirez-Ortiz Signed-off-by: Bintian Wang Acked-by: Haojian Zhuang Reviewed-by: Zhangfei Gao Tested-by: Will Deacon Tested-by: Tyler Baker Hi Bintian, Thanks for making the changes requested by Stephen. I've taken his patch to add assigned-clock-rate/parent support for AMBA interconnects and applied it to 4.1-rc1, and then I've applied your v8 patches #4-6 on top of that. You can find it at: git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next-hi6220 Thank you very much! I think you also need to pick patch "[PATCH v5 3/6] clk: hi6220: Document devicetree bindings for hi6220 clock", which described the dt binding of clk, and it is also acked by Stephen(v4 is the same to v5). I have merged this into clk-next so it can get some cycles in linux-next. Stephen, Can you send your patch out to Russell properly? It needs his ack (or for him to take it outright) in order to unblock the hi6220 clock driver from being merged. It doesn't block hi6220 clock driver now, because the UART1 is not enabled in hi6220 dts now. Thanks! Bintian Regards, Mike . -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v8 6/7] clk: hi6220: Clock driver support for Hisilicon hi6220 SoC
Hello Kevin, On 2015/5/29 1:32, Kevin Hilman wrote: Bintian bintian.w...@huawei.com writes: Hello Mike, On 2015/5/28 13:26, Michael Turquette wrote: Quoting Bintian Wang (2015-05-23 21:11:11) Add clock drivers for hi6220 SoC, this driver controls the SoC registers to supply different clocks to different IPs in the SoC. We add one divider clock for hi6220 because the divider in hi6220 also has a mask bit but it doesnot obey the rule defined by flag CLK_DIVIDER_HIWORD_MASK, we can not get index of the mask bit by left shift fixed bits (e.g. 16 bits), so we add this divider clock to handle it. Signed-off-by: Jorge Ramirez-Ortiz jorge.ramirez-or...@linaro.org Signed-off-by: Bintian Wang bintian.w...@huawei.com Acked-by: Haojian Zhuang haojian.zhu...@linaro.org Reviewed-by: Zhangfei Gao zhangfei@linaro.org Tested-by: Will Deacon will.dea...@arm.com Tested-by: Tyler Baker tyler.ba...@linaro.org Hi Bintian, Thanks for making the changes requested by Stephen. I've taken his patch to add assigned-clock-rate/parent support for AMBA interconnects and applied it to 4.1-rc1, and then I've applied your v8 patches #4-6 on top of that. You can find it at: git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next-hi6220 Thank you very much! I think you also need to pick patch [PATCH v5 3/6] clk: hi6220: Document devicetree bindings for hi6220 clock, which described the dt binding of clk, and it is also acked by Stephen(v4 is the same to v5). I have merged this into clk-next so it can get some cycles in linux-next. Stephen, Can you send your patch out to Russell properly? It needs his ack (or for him to take it outright) in order to unblock the hi6220 clock driver from being merged. It doesn't block hi6220 clock driver now, because the UART1 is not enabled in hi6220 dts now. Now that the clk changes are queued up, can you (re)post the remaining hikey patches with a changelog stating the dependency on the clk-next branch. I believe what's left is just the DT and Kconfig/defconfig changes, correct? Yes, you are right. I will post the remaining hikey patches soon. Thank you Kevin, BR, Bintian With some acks from the DT maintainers, these should be ready to be merged through arm-soc. Thanks, Kevin . -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v8 4/7] clk: hisilicon: Remove __init for marking function prototypes
Hello Kevin, On 2015/5/29 0:50, Kevin Hilman wrote: Bintian Wang bintian.w...@huawei.com writes: __init markings on function prototypes are useless, so remove them. Suggested-by: Stephen Boyd sb...@codeaurora.org Signed-off-by: Bintian Wang bintian.w...@huawei.com Can you repost the whole series please? The number of patches has increased and it's not terribly obvious how to combine your v7 or v8 patches with the v8 patches for proper testing. I have sent the whole series, please help check. Thanks, Bintian Thanks, Kevin . -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v8 3/7] Documentation: DT: PL011: hi6220: add compatible string for Hisilicon designed UART
Hisilicon does some performance enhancements based on PL011(e.g. larger FIFO length), so add one compatible string hisilicon,hi6220-uart for future optimisations or workarounds works. Signed-off-by: Bintian Wang bintian.w...@huawei.com Suggested-by: Mark Rutland mark.rutl...@arm.com --- Documentation/devicetree/bindings/serial/pl011.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/serial/pl011.txt b/Documentation/devicetree/bindings/serial/pl011.txt index ba3ecb8..cb9fd9d 100644 --- a/Documentation/devicetree/bindings/serial/pl011.txt +++ b/Documentation/devicetree/bindings/serial/pl011.txt @@ -1,7 +1,9 @@ * ARM AMBA Primecell PL011 serial UART Required properties: -- compatible: must be arm,primecell, arm,pl011 +- compatible: should contain one of the following sequences: + * arm,pl011, arm,primecell + * hisilicon,hi6220-pl011, arm,pl011, arm,primecell - reg: exactly one register range with length 0x1000 - interrupts: exactly one interrupt specifier -- 1.9.1 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v8 4/7] clk: hisilicon: Remove __init for marking function prototypes
__init markings on function prototypes are useless, so remove them. Suggested-by: Stephen Boyd sb...@codeaurora.org Signed-off-by: Bintian Wang bintian.w...@huawei.com Tested-by: Will Deacon will.dea...@arm.com Tested-by: Tyler Baker tyler.ba...@linaro.org Tested-by: Kevin Hilman khil...@linaro.org --- drivers/clk/hisilicon/clk.h | 22 +++--- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/clk/hisilicon/clk.h b/drivers/clk/hisilicon/clk.h index 31083ff..6b6f994 100644 --- a/drivers/clk/hisilicon/clk.h +++ b/drivers/clk/hisilicon/clk.h @@ -95,17 +95,17 @@ struct clk *hisi_register_clkgate_sep(struct device *, const char *, void __iomem *, u8, u8, spinlock_t *); -struct hisi_clock_data __init *hisi_clk_init(struct device_node *, int); -void __init hisi_clk_register_fixed_rate(struct hisi_fixed_rate_clock *, - int, struct hisi_clock_data *); -void __init hisi_clk_register_fixed_factor(struct hisi_fixed_factor_clock *, - int, struct hisi_clock_data *); -void __init hisi_clk_register_mux(struct hisi_mux_clock *, int, +struct hisi_clock_data *hisi_clk_init(struct device_node *, int); +void hisi_clk_register_fixed_rate(struct hisi_fixed_rate_clock *, + int, struct hisi_clock_data *); +void hisi_clk_register_fixed_factor(struct hisi_fixed_factor_clock *, + int, struct hisi_clock_data *); +void hisi_clk_register_mux(struct hisi_mux_clock *, int, struct hisi_clock_data *); -void __init hisi_clk_register_divider(struct hisi_divider_clock *, +void hisi_clk_register_divider(struct hisi_divider_clock *, + int, struct hisi_clock_data *); +void hisi_clk_register_gate(struct hisi_gate_clock *, + int, struct hisi_clock_data *); +void hisi_clk_register_gate_sep(struct hisi_gate_clock *, int, struct hisi_clock_data *); -void __init hisi_clk_register_gate(struct hisi_gate_clock *, - int, struct hisi_clock_data *); -void __init hisi_clk_register_gate_sep(struct hisi_gate_clock *, - int, struct hisi_clock_data *); #endif /* __HISI_CLK_H */ -- 1.9.1 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v8 0/7] arm64,hi6220: Enable Hisilicon Hi6220 SoC
From: Bintian Wang wangbint...@gmail.com Hi6220 is one mobile solution of Hisilicon, this patchset contains initial support for Hi6220 SoC and HiKey development board, which supports octal ARM Cortex A53 cores. Initial support is minimal and includes just the arch configuration, clock driver, device tree configuration. PSCI is enabled in device tree and there is no problem to boot all the octal cores, and the CPU hotplug is also working now, you can download and compile the latest firmware based on the following link to run this patch set: https://github.com/96boards/documentation/wiki/UEFI Changes v6~v8: This three versions only modified the clock drivers based on the Stephen's review advices. * clk-hi6220.c: ** Split the clock header file from clock driver ** Delete setting the parents clock of UART1 to HI6220_150M in clock driver, we can do that using assigned-clock in dts when enable UART1 in the future. * clkdivider-hi6220.c: ** Reuse some functions exported by clk-divider.c ** Remove pr_err and CLK_IS_BASIC flag ** Fix some programing style problems * hisilicon/clk.h: remove the __init markings on some funcition prototypes. Changes v5: * Rebase to kernel 4.1-rc2 * Add compatible string hisilicon,hi6220-pl011 for Hisilicon designed UART * clk-hi6220.c: use __initdata for non-const arrays based on the commit 692d8328e8c039f9497eb862c6cf835de922c061 Changes v4: * Rebase to kernel 4.1-rc1 * Delete arm,cortex-a15-gic from the gic node in dts Changes v3: * Verified the CPU hotplug based on the new released firmware * Redefined the compatible strings of four system controllers in dts * Setting COMMON_CLK_HI6220 to a bool symbol * Keep CONFGI_ARCH_HISI sorted alphabetically Changes v2: * Split the DT bindings documents into earlier patches * Change SMP enable method from spin-table to PSCI in device tree * Remove clock-frequency from armv8-timer device node in device tree * Add more description about Hisilicon designed system controllers in DT bindings document * Enable high speed clock on UART1 mux * Other changes based on the discussion in the mailing list: https://lkml.org/lkml/2015/2/5/147 Bintian Wang (7): arm64: hi6220: Document devicetree bindings for Hisilicon hi6220 SoC clk: hi6220: Document devicetree bindings for hi6220 clock Documentation: DT: PL011: hi6220: add compatible string for Hisilicon designed UART clk: hisilicon: Remove __init for marking function prototypes dt-bindings: Add header file of hi6220 clock driver clk: hi6220: Clock driver support for Hisilicon hi6220 SoC arm64: dts: Add dts files for Hisilicon Hi6220 SoC .../bindings/arm/hisilicon/hisilicon.txt | 87 +++ .../devicetree/bindings/clock/hi6220-clock.txt | 34 +++ Documentation/devicetree/bindings/serial/pl011.txt | 4 +- arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/hisilicon/Makefile | 5 + arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 31 +++ arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 172 + drivers/clk/Kconfig| 1 + drivers/clk/Makefile | 4 +- drivers/clk/hisilicon/Kconfig | 6 + drivers/clk/hisilicon/Makefile | 3 +- drivers/clk/hisilicon/clk-hi6220.c | 284 + drivers/clk/hisilicon/clk.c| 29 +++ drivers/clk/hisilicon/clk.h| 39 ++- drivers/clk/hisilicon/clkdivider-hi6220.c | 156 +++ include/dt-bindings/clock/hi6220-clock.h | 173 + 16 files changed, 1013 insertions(+), 16 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/hi6220-clock.txt create mode 100644 arch/arm64/boot/dts/hisilicon/Makefile create mode 100644 arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts create mode 100644 arch/arm64/boot/dts/hisilicon/hi6220.dtsi create mode 100644 drivers/clk/hisilicon/Kconfig create mode 100644 drivers/clk/hisilicon/clk-hi6220.c create mode 100644 drivers/clk/hisilicon/clkdivider-hi6220.c create mode 100644 include/dt-bindings/clock/hi6220-clock.h -- 1.9.1 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v8 5/7] dt-bindings: Add header file of hi6220 clock driver
Add the header file hi6220-clock.h used by both hi6220 clock driver and hi6220 device tree file. Suggested-by: Stephen Boyd sb...@codeaurora.org Signed-off-by: Bintian Wang bintian.w...@huawei.com Tested-by: Will Deacon will.dea...@arm.com Tested-by: Tyler Baker tyler.ba...@linaro.org Tested-by: Kevin Hilman khil...@linaro.org --- include/dt-bindings/clock/hi6220-clock.h | 173 +++ 1 file changed, 173 insertions(+) create mode 100644 include/dt-bindings/clock/hi6220-clock.h diff --git a/include/dt-bindings/clock/hi6220-clock.h b/include/dt-bindings/clock/hi6220-clock.h new file mode 100644 index 000..70ee383 --- /dev/null +++ b/include/dt-bindings/clock/hi6220-clock.h @@ -0,0 +1,173 @@ +/* + * Copyright (c) 2015 Hisilicon Limited. + * + * Author: Bintian Wang bintian.w...@huawei.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __DT_BINDINGS_CLOCK_HI6220_H +#define __DT_BINDINGS_CLOCK_HI6220_H + +/* clk in Hi6220 AO (always on) controller */ +#define HI6220_NONE_CLOCK 0 + +/* fixed rate clocks */ +#define HI6220_REF32K 1 +#define HI6220_CLK_TCXO2 +#define HI6220_MMC1_PAD3 +#define HI6220_MMC2_PAD4 +#define HI6220_MMC0_PAD5 +#define HI6220_PLL_BBP 6 +#define HI6220_PLL_GPU 7 +#define HI6220_PLL1_DDR8 +#define HI6220_PLL_SYS 9 +#define HI6220_PLL_SYS_MEDIA 10 +#define HI6220_DDR_SRC 11 +#define HI6220_PLL_MEDIA 12 +#define HI6220_PLL_DDR 13 + +/* fixed factor clocks */ +#define HI6220_300M14 +#define HI6220_150M15 +#define HI6220_PICOPHY_SRC 16 +#define HI6220_MMC0_SRC_SEL17 +#define HI6220_MMC1_SRC_SEL18 +#define HI6220_MMC2_SRC_SEL19 +#define HI6220_VPU_CODEC 20 +#define HI6220_MMC0_SMP21 +#define HI6220_MMC1_SMP22 +#define HI6220_MMC2_SMP23 + +/* gate clocks */ +#define HI6220_WDT0_PCLK 24 +#define HI6220_WDT1_PCLK 25 +#define HI6220_WDT2_PCLK 26 +#define HI6220_TIMER0_PCLK 27 +#define HI6220_TIMER1_PCLK 28 +#define HI6220_TIMER2_PCLK 29 +#define HI6220_TIMER3_PCLK 30 +#define HI6220_TIMER4_PCLK 31 +#define HI6220_TIMER5_PCLK 32 +#define HI6220_TIMER6_PCLK 33 +#define HI6220_TIMER7_PCLK 34 +#define HI6220_TIMER8_PCLK 35 +#define HI6220_UART0_PCLK 36 + +#define HI6220_AO_NR_CLKS 37 + +/* clk in Hi6220 systrl */ +/* gate clock */ +#define HI6220_MMC0_CLK1 +#define HI6220_MMC0_CIUCLK 2 +#define HI6220_MMC1_CLK3 +#define HI6220_MMC1_CIUCLK 4 +#define HI6220_MMC2_CLK5 +#define HI6220_MMC2_CIUCLK 6 +#define HI6220_USBOTG_HCLK 7 +#define HI6220_CLK_PICOPHY 8 +#define HI6220_HIFI9 +#define HI6220_DACODEC_PCLK10 +#define HI6220_EDMAC_ACLK 11 +#define HI6220_CS_ATB 12 +#define HI6220_I2C0_CLK13 +#define HI6220_I2C1_CLK14 +#define HI6220_I2C2_CLK15 +#define HI6220_I2C3_CLK16 +#define HI6220_UART1_PCLK 17 +#define HI6220_UART2_PCLK 18 +#define HI6220_UART3_PCLK 19 +#define HI6220_UART4_PCLK 20 +#define HI6220_SPI_CLK 21 +#define HI6220_TSENSOR_CLK 22 +#define HI6220_MMU_CLK 23 +#define HI6220_HIFI_SEL24 +#define HI6220_MMC0_SYSPLL 25 +#define HI6220_MMC1_SYSPLL 26 +#define HI6220_MMC2_SYSPLL 27 +#define HI6220_MMC0_SEL28 +#define HI6220_MMC1_SEL29 +#define HI6220_BBPPLL_SEL 30 +#define HI6220_MEDIA_PLL_SRC 31 +#define HI6220_MMC2_SEL32 +#define HI6220_CS_ATB_SYSPLL 33 + +/* mux clocks */ +#define HI6220_MMC0_SRC34 +#define HI6220_MMC0_SMP_IN 35 +#define HI6220_MMC1_SRC36 +#define HI6220_MMC1_SMP_IN 37 +#define HI6220_MMC2_SRC38 +#define HI6220_MMC2_SMP_IN 39 +#define HI6220_HIFI_SRC40 +#define HI6220_UART1_SRC 41 +#define HI6220_UART2_SRC 42 +#define HI6220_UART3_SRC 43 +#define HI6220_UART4_SRC 44 +#define HI6220_MMC0_MUX0 45 +#define HI6220_MMC1_MUX0 46 +#define HI6220_MMC2_MUX0 47 +#define HI6220_MMC0_MUX1 48 +#define HI6220_MMC1_MUX1 49 +#define HI6220_MMC2_MUX1 50 + +/* divider clocks */ +#define HI6220_CLK_BUS 51 +#define HI6220_MMC0_DIV52 +#define HI6220_MMC1_DIV53 +#define HI6220_MMC2_DIV54 +#define HI6220_HIFI_DIV55 +#define HI6220_BBPPLL0_DIV 56 +#define HI6220_CS_DAPB 57 +#define HI6220_CS_ATB_DIV 58 + +#define HI6220_SYS_NR_CLKS 59 + +/* clk in Hi6220 media controller */ +/* gate clocks */ +#define
[PATCH v8 6/7] clk: hi6220: Clock driver support for Hisilicon hi6220 SoC
Add clock drivers for hi6220 SoC, this driver controls the SoC
registers to supply different clocks to different IPs in the SoC.
We add one divider clock for hi6220 because the divider in hi6220
also has a mask bit but it doesnot obey the rule defined by flag
CLK_DIVIDER_HIWORD_MASK, we can not get index of the mask bit by
left shift fixed bits (e.g. 16 bits), so we add this divider clock
to handle it.
Signed-off-by: Jorge Ramirez-Ortiz jorge.ramirez-or...@linaro.org
Signed-off-by: Bintian Wang bintian.w...@huawei.com
Acked-by: Haojian Zhuang haojian.zhu...@linaro.org
Reviewed-by: Zhangfei Gao zhangfei@linaro.org
Tested-by: Will Deacon will.dea...@arm.com
Tested-by: Tyler Baker tyler.ba...@linaro.org
Tested-by: Kevin Hilman khil...@linaro.org
---
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile | 4 +-
drivers/clk/hisilicon/Kconfig | 6 +
drivers/clk/hisilicon/Makefile| 3 +-
drivers/clk/hisilicon/clk-hi6220.c| 284 ++
drivers/clk/hisilicon/clk.c | 29 +++
drivers/clk/hisilicon/clk.h | 17 ++
drivers/clk/hisilicon/clkdivider-hi6220.c | 156
8 files changed, 496 insertions(+), 4 deletions(-)
create mode 100644 drivers/clk/hisilicon/Kconfig
create mode 100644 drivers/clk/hisilicon/clk-hi6220.c
create mode 100644 drivers/clk/hisilicon/clkdivider-hi6220.c
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index de8c58f..cd6029d4 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -151,6 +151,7 @@ config COMMON_CLK_CDCE706
This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
source drivers/clk/bcm/Kconfig
+source drivers/clk/hisilicon/Kconfig
source drivers/clk/qcom/Kconfig
endmenu
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index d2d5e6c..440ef72 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -47,9 +47,7 @@ obj-$(CONFIG_COMMON_CLK_PWM) += clk-pwm.o
obj-$(CONFIG_COMMON_CLK_AT91) += at91/
obj-$(CONFIG_ARCH_BCM_MOBILE) += bcm/
obj-$(CONFIG_ARCH_BERLIN) += berlin/
-obj-$(CONFIG_ARCH_HI3xxx) += hisilicon/
-obj-$(CONFIG_ARCH_HIP04) += hisilicon/
-obj-$(CONFIG_ARCH_HIX5HD2) += hisilicon/
+obj-$(CONFIG_ARCH_HISI)+= hisilicon/
obj-$(CONFIG_ARCH_MXC) += imx/
obj-$(CONFIG_COMMON_CLK_KEYSTONE) += keystone/
obj-$(CONFIG_ARCH_MEDIATEK)+= mediatek/
diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
new file mode 100644
index 000..b4165ba
--- /dev/null
+++ b/drivers/clk/hisilicon/Kconfig
@@ -0,0 +1,6 @@
+config COMMON_CLK_HI6220
+ bool Hi6220 Clock Driver
+ depends on ARCH_HISI || COMPILE_TEST
+ default ARCH_HISI
+ help
+ Build the Hisilicon Hi6220 clock driver based on the common clock
framework.
diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile
index 038c02f..48f0116 100644
--- a/drivers/clk/hisilicon/Makefile
+++ b/drivers/clk/hisilicon/Makefile
@@ -2,8 +2,9 @@
# Hisilicon Clock specific Makefile
#
-obj-y += clk.o clkgate-separated.o
+obj-y += clk.o clkgate-separated.o clkdivider-hi6220.o
obj-$(CONFIG_ARCH_HI3xxx) += clk-hi3620.o
obj-$(CONFIG_ARCH_HIP04) += clk-hip04.o
obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o
+obj-$(CONFIG_COMMON_CLK_HI6220)+= clk-hi6220.o
diff --git a/drivers/clk/hisilicon/clk-hi6220.c
b/drivers/clk/hisilicon/clk-hi6220.c
new file mode 100644
index 000..4563343
--- /dev/null
+++ b/drivers/clk/hisilicon/clk-hi6220.c
@@ -0,0 +1,284 @@
+/*
+ * Hisilicon Hi6220 clock driver
+ *
+ * Copyright (c) 2015 Hisilicon Limited.
+ *
+ * Author: Bintian Wang bintian.w...@huawei.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/kernel.h
+#include linux/clk-provider.h
+#include linux/clkdev.h
+#include linux/io.h
+#include linux/of.h
+#include linux/of_address.h
+#include linux/of_device.h
+#include linux/slab.h
+
+#include dt-bindings/clock/hi6220-clock.h
+
+#include clk.h
+
+
+/* clocks in AO (always on) controller */
+static struct hisi_fixed_rate_clock hi6220_fixed_rate_clks[] __initdata = {
+ { HI6220_REF32K,ref32k, NULL, CLK_IS_ROOT, 32764, },
+ { HI6220_CLK_TCXO, clk_tcxo, NULL, CLK_IS_ROOT, 1920, },
+ { HI6220_MMC1_PAD, mmc1_pad, NULL, CLK_IS_ROOT, 1, },
+ { HI6220_MMC2_PAD, mmc2_pad, NULL, CLK_IS_ROOT, 1, },
+ { HI6220_MMC0_PAD, mmc0_pad, NULL, CLK_IS_ROOT, 2, },
+ { HI6220_PLL_BBP, bbppll0, NULL, CLK_IS_ROOT, 24576, },
+ { HI6220_PLL_GPU, gpupll, NULL, CLK_IS_ROOT, 10
[PATCH v8 2/7] clk: hi6220: Document devicetree bindings for hi6220 clock
Document DT files bindings for Hisilicon hi6220 clock.
Signed-off-by: Bintian Wang bintian.w...@huawei.com
Acked-by: Haojian Zhuang haojian.zhu...@linaro.org
Suggested-by: Arnd Bergmann a...@arndb.de
Acked-by: Stephen Boyd sb...@codeaurora.org
---
.../devicetree/bindings/clock/hi6220-clock.txt | 34 ++
1 file changed, 34 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/hi6220-clock.txt
diff --git a/Documentation/devicetree/bindings/clock/hi6220-clock.txt
b/Documentation/devicetree/bindings/clock/hi6220-clock.txt
new file mode 100644
index 000..53ddb19
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/hi6220-clock.txt
@@ -0,0 +1,34 @@
+* Hisilicon Hi6220 Clock Controller
+
+Clock control registers reside in different Hi6220 system controllers,
+please refer the following document to know more about the binding rules
+for these system controllers:
+
+Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
+
+Required Properties:
+
+- compatible: the compatible should be one of the following strings to
+ indicate the clock controller functionality.
+
+ - hisilicon,hi6220-aoctrl
+ - hisilicon,hi6220-sysctrl
+ - hisilicon,hi6220-mediactrl
+ - hisilicon,hi6220-pmctrl
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- #clock-cells: should be 1.
+
+For example:
+ sys_ctrl: sys_ctrl {
+ compatible = hisilicon,hi6220-sysctrl, syscon;
+ reg = 0x0 0xf703 0x0 0x2000;
+ #clock-cells = 1;
+ };
+
+Each clock is assigned an identifier and client nodes use this identifier
+to specify the clock which they consume.
+
+All these identifier could be found in dt-bindings/clock/hi6220-clock.h.
--
1.9.1
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[PATCH v8 7/7] arm64: dts: Add dts files for Hisilicon Hi6220 SoC
Add initial dtsi file to support Hisilicon Hi6220 SoC with
support of Octal core CPUs in two clusters and each cluster
has quard Cortex-A53.
Also add dts file to support HiKey development board which
based on Hi6220 SoC.
Signed-off-by: Bintian Wang bintian.w...@huawei.com
Acked-by: Haojian Zhuang haojian.zhu...@linaro.org
Reviewed-by: Yiping Xu xuyip...@hisilicon.com
Tested-by: Will Deacon will.dea...@arm.com
Tested-by: Tyler Baker tyler.ba...@linaro.org
Tested-by: Kevin Hilman khil...@linaro.org
---
arch/arm64/boot/dts/Makefile | 1 +
arch/arm64/boot/dts/hisilicon/Makefile | 5 +
arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 31 +
arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 172 +
4 files changed, 209 insertions(+)
create mode 100644 arch/arm64/boot/dts/hisilicon/Makefile
create mode 100644 arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
create mode 100644 arch/arm64/boot/dts/hisilicon/hi6220.dtsi
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index ad26a75..38913be 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -4,6 +4,7 @@ dts-dirs += arm
dts-dirs += cavium
dts-dirs += exynos
dts-dirs += freescale
+dts-dirs += hisilicon
dts-dirs += mediatek
dts-dirs += qcom
dts-dirs += sprd
diff --git a/arch/arm64/boot/dts/hisilicon/Makefile
b/arch/arm64/boot/dts/hisilicon/Makefile
new file mode 100644
index 000..fa81a6e
--- /dev/null
+++ b/arch/arm64/boot/dts/hisilicon/Makefile
@@ -0,0 +1,5 @@
+dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb
+
+always := $(dtb-y)
+subdir-y := $(dts-dirs)
+clean-files:= *.dtb
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
new file mode 100644
index 000..e36a539
--- /dev/null
+++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
@@ -0,0 +1,31 @@
+/*
+ * dts file for Hisilicon HiKey Development Board
+ *
+ * Copyright (C) 2015, Hisilicon Ltd.
+ *
+ */
+
+/dts-v1/;
+
+/*Reserved 1MB memory for MCU*/
+/memreserve/ 0x05e0 0x0010;
+
+#include hi6220.dtsi
+
+/ {
+ model = HiKey Development Board;
+ compatible = hisilicon,hi6220-hikey, hisilicon,hi6220;
+
+ aliases {
+ serial0 = uart0;
+ };
+
+ chosen {
+ stdout-path = serial0:115200n8;
+ };
+
+ memory@0 {
+ device_type = memory;
+ reg = 0x0 0x0 0x0 0x4000;
+ };
+};
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
new file mode 100644
index 000..229937f
--- /dev/null
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -0,0 +1,172 @@
+/*
+ * dts file for Hisilicon Hi6220 SoC
+ *
+ * Copyright (C) 2015, Hisilicon Ltd.
+ */
+
+#include dt-bindings/clock/hi6220-clock.h
+#include dt-bindings/interrupt-controller/arm-gic.h
+
+/ {
+ compatible = hisilicon,hi6220;
+ interrupt-parent = gic;
+ #address-cells = 2;
+ #size-cells = 2;
+
+ psci {
+ compatible = arm,psci-0.2;
+ method = smc;
+ };
+
+ cpus {
+ #address-cells = 2;
+ #size-cells = 0;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = cpu0;
+ };
+ core1 {
+ cpu = cpu1;
+ };
+ core2 {
+ cpu = cpu2;
+ };
+ core3 {
+ cpu = cpu3;
+ };
+ };
+ cluster1 {
+ core0 {
+ cpu = cpu4;
+ };
+ core1 {
+ cpu = cpu5;
+ };
+ core2 {
+ cpu = cpu6;
+ };
+ core3 {
+ cpu = cpu7;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ compatible = arm,cortex-a53, arm,armv8;
+ device_type = cpu;
+ reg = 0x0 0x0;
+ enable-method = psci;
+ };
+
+ cpu1: cpu@1 {
+ compatible = arm,cortex-a53, arm,armv8;
+ device_type = cpu;
+ reg = 0x0 0x1;
+ enable-method = psci;
+ };
+
+ cpu2: cpu@2 {
+ compatible = arm,cortex-a53, arm
[PATCH v8 1/7] arm64: hi6220: Document devicetree bindings for Hisilicon hi6220 SoC
This patch adds documentation for the devicetree bindings used by the
DT files of Hisilicon hi6220 SoC mobile platform.
Signed-off-by: Bintian Wang bintian.w...@huawei.com
Suggested-by: Arnd Bergmann a...@arndb.de
Acked-by: Haojian Zhuang haojian.zhu...@linaro.org
Acked-by: Stephen Boyd sb...@codeaurora.org
---
.../bindings/arm/hisilicon/hisilicon.txt | 87 ++
1 file changed, 87 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
index 35b1bd4..f67d0f3 100644
--- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
+++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
@@ -1,5 +1,8 @@
Hisilicon Platforms Device Tree Bindings
+Hi6220 SoC
+Required root node properties:
+ - compatible = hisilicon,hi6220;
Hi4511 Board
Required root node properties:
@@ -13,6 +16,9 @@ HiP01 ca9x2 Board
Required root node properties:
- compatible = hisilicon,hip01-ca9x2;
+HiKey Board
+Required root node properties:
+ - compatible = hisilicon,hi6220-hikey, hisilicon,hi6220;
Hisilicon system controller
@@ -41,6 +47,87 @@ Example:
};
---
+Hisilicon Hi6220 system controller
+
+Required properties:
+- compatible : hisilicon,hi6220-sysctrl
+- reg : Register address and size
+- #clock-cells: should be set to 1, many clock registers are defined
+ under this controller and this property must be present.
+
+Hisilicon designs this controller as one of the system controllers,
+its main functions are the same as Hisilicon system controller, but
+the register offset of some core modules are different.
+
+Example:
+ /*for Hi6220*/
+ sys_ctrl: sys_ctrl {
+ compatible = hisilicon,hi6220-sysctrl, syscon;
+ reg = 0x0 0xf703 0x0 0x2000;
+ #clock-cells = 1;
+ };
+
+
+Hisilicon Hi6220 Power Always ON domain controller
+
+Required properties:
+- compatible : hisilicon,hi6220-aoctrl
+- reg : Register address and size
+- #clock-cells: should be set to 1, many clock registers are defined
+ under this controller and this property must be present.
+
+Hisilicon designs this system controller to control the power always
+on domain for mobile platform.
+
+Example:
+ /*for Hi6220*/
+ ao_ctrl: ao_ctrl {
+ compatible = hisilicon,hi6220-aoctrl, syscon;
+ reg = 0x0 0xf780 0x0 0x2000;
+ #clock-cells = 1;
+ };
+
+
+Hisilicon Hi6220 Media domain controller
+
+Required properties:
+- compatible : hisilicon,hi6220-mediactrl
+- reg : Register address and size
+- #clock-cells: should be set to 1, many clock registers are defined
+ under this controller and this property must be present.
+
+Hisilicon designs this system controller to control the multimedia
+domain(e.g. codec, G3D ...) for mobile platform.
+
+Example:
+ /*for Hi6220*/
+ media_ctrl: media_ctrl {
+ compatible = hisilicon,hi6220-mediactrl, syscon;
+ reg = 0x0 0xf441 0x0 0x1000;
+ #clock-cells = 1;
+ };
+
+
+Hisilicon Hi6220 Power Management domain controller
+
+Required properties:
+- compatible : hisilicon,hi6220-pmctrl
+- reg : Register address and size
+- #clock-cells: should be set to 1, some clock registers are define
+ under this controller and this property must be present.
+
+Hisilicon designs this system controller to control the power management
+domain for mobile platform.
+
+Example:
+ /*for Hi6220*/
+ pm_ctrl: pm_ctrl {
+ compatible = hisilicon,hi6220-pmctrl, syscon;
+ reg = 0x0 0xf7032000 0x0 0x1000;
+ #clock-cells = 1;
+ };
+
+---
Hisilicon HiP01 system controller
Required properties:
--
1.9.1
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v8 6/7] clk: hi6220: Clock driver support for Hisilicon hi6220 SoC
Hello Mike, On 2015/5/29 9:07, Michael Turquette wrote: Quoting Kevin Hilman (2015-05-28 10:32:05) Bintian bintian.w...@huawei.com writes: Hello Mike, On 2015/5/28 13:26, Michael Turquette wrote: Quoting Bintian Wang (2015-05-23 21:11:11) Add clock drivers for hi6220 SoC, this driver controls the SoC registers to supply different clocks to different IPs in the SoC. We add one divider clock for hi6220 because the divider in hi6220 also has a mask bit but it doesnot obey the rule defined by flag CLK_DIVIDER_HIWORD_MASK, we can not get index of the mask bit by left shift fixed bits (e.g. 16 bits), so we add this divider clock to handle it. Signed-off-by: Jorge Ramirez-Ortiz jorge.ramirez-or...@linaro.org Signed-off-by: Bintian Wang bintian.w...@huawei.com Acked-by: Haojian Zhuang haojian.zhu...@linaro.org Reviewed-by: Zhangfei Gao zhangfei@linaro.org Tested-by: Will Deacon will.dea...@arm.com Tested-by: Tyler Baker tyler.ba...@linaro.org Hi Bintian, Thanks for making the changes requested by Stephen. I've taken his patch to add assigned-clock-rate/parent support for AMBA interconnects and applied it to 4.1-rc1, and then I've applied your v8 patches #4-6 on top of that. You can find it at: git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next-hi6220 Thank you very much! I think you also need to pick patch [PATCH v5 3/6] clk: hi6220: Document devicetree bindings for hi6220 clock, which described the dt binding of clk, and it is also acked by Stephen(v4 is the same to v5). I have merged this into clk-next so it can get some cycles in linux-next. Stephen, Can you send your patch out to Russell properly? It needs his ack (or for him to take it outright) in order to unblock the hi6220 clock driver from being merged. It doesn't block hi6220 clock driver now, because the UART1 is not enabled in hi6220 dts now. Now that the clk changes are queued up, can you (re)post the remaining hikey patches with a changelog stating the dependency on the clk-next branch. I believe what's left is just the DT and Kconfig/defconfig changes, correct? Just to be clear, clk-next-hi6220 is not an immutable branch. I just put it up to get some testing done on it. Depending on whether or not Russell acks Stephen's patch then it may be changed. Stephen's patch can help UART1 to switch to the higher clock, so we can remove the clk_set_parent from the clk-hi6220.c safely and don't need to do that workaround in advance. You know, we don't enable the UART1 in this series, and we can submit other patch to enable it after Stephen's patch is merged. Thanks, Bintian Regards, Mike With some acks from the DT maintainers, these should be ready to be merged through arm-soc. Thanks, Kevin . -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v8 6/7] clk: hi6220: Clock driver support for Hisilicon hi6220 SoC
Hello Mike, On 2015/5/28 13:26, Michael Turquette wrote: Quoting Bintian Wang (2015-05-23 21:11:11) Add clock drivers for hi6220 SoC, this driver controls the SoC registers to supply different clocks to different IPs in the SoC. We add one divider clock for hi6220 because the divider in hi6220 also has a mask bit but it doesnot obey the rule defined by flag CLK_DIVIDER_HIWORD_MASK, we can not get index of the mask bit by left shift fixed bits (e.g. 16 bits), so we add this divider clock to handle it. Signed-off-by: Jorge Ramirez-Ortiz jorge.ramirez-or...@linaro.org Signed-off-by: Bintian Wang bintian.w...@huawei.com Acked-by: Haojian Zhuang haojian.zhu...@linaro.org Reviewed-by: Zhangfei Gao zhangfei@linaro.org Tested-by: Will Deacon will.dea...@arm.com Tested-by: Tyler Baker tyler.ba...@linaro.org Hi Bintian, Thanks for making the changes requested by Stephen. I've taken his patch to add assigned-clock-rate/parent support for AMBA interconnects and applied it to 4.1-rc1, and then I've applied your v8 patches #4-6 on top of that. You can find it at: git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next-hi6220 Thank you very much! I think you also need to pick patch [PATCH v5 3/6] clk: hi6220: Document devicetree bindings for hi6220 clock, which described the dt binding of clk, and it is also acked by Stephen(v4 is the same to v5). I have merged this into clk-next so it can get some cycles in linux-next. Stephen, Can you send your patch out to Russell properly? It needs his ack (or for him to take it outright) in order to unblock the hi6220 clock driver from being merged. It doesn't block hi6220 clock driver now, because the UART1 is not enabled in hi6220 dts now. Thanks! Bintian Regards, Mike . -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v8 4/7] clk: hisilicon: Remove __init for marking function prototypes
__init markings on function prototypes are useless, so remove them. Suggested-by: Stephen Boyd Signed-off-by: Bintian Wang --- drivers/clk/hisilicon/clk.h | 22 +++--- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/clk/hisilicon/clk.h b/drivers/clk/hisilicon/clk.h index 31083ff..6b6f994 100644 --- a/drivers/clk/hisilicon/clk.h +++ b/drivers/clk/hisilicon/clk.h @@ -95,17 +95,17 @@ struct clk *hisi_register_clkgate_sep(struct device *, const char *, void __iomem *, u8, u8, spinlock_t *); -struct hisi_clock_data __init *hisi_clk_init(struct device_node *, int); -void __init hisi_clk_register_fixed_rate(struct hisi_fixed_rate_clock *, - int, struct hisi_clock_data *); -void __init hisi_clk_register_fixed_factor(struct hisi_fixed_factor_clock *, - int, struct hisi_clock_data *); -void __init hisi_clk_register_mux(struct hisi_mux_clock *, int, +struct hisi_clock_data *hisi_clk_init(struct device_node *, int); +void hisi_clk_register_fixed_rate(struct hisi_fixed_rate_clock *, + int, struct hisi_clock_data *); +void hisi_clk_register_fixed_factor(struct hisi_fixed_factor_clock *, + int, struct hisi_clock_data *); +void hisi_clk_register_mux(struct hisi_mux_clock *, int, struct hisi_clock_data *); -void __init hisi_clk_register_divider(struct hisi_divider_clock *, +void hisi_clk_register_divider(struct hisi_divider_clock *, + int, struct hisi_clock_data *); +void hisi_clk_register_gate(struct hisi_gate_clock *, + int, struct hisi_clock_data *); +void hisi_clk_register_gate_sep(struct hisi_gate_clock *, int, struct hisi_clock_data *); -void __init hisi_clk_register_gate(struct hisi_gate_clock *, - int, struct hisi_clock_data *); -void __init hisi_clk_register_gate_sep(struct hisi_gate_clock *, - int, struct hisi_clock_data *); #endif /* __HISI_CLK_H */ -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v8 6/7] clk: hi6220: Clock driver support for Hisilicon hi6220 SoC
Add clock drivers for hi6220 SoC, this driver controls the SoC
registers to supply different clocks to different IPs in the SoC.
We add one divider clock for hi6220 because the divider in hi6220
also has a mask bit but it doesnot obey the rule defined by flag
"CLK_DIVIDER_HIWORD_MASK", we can not get index of the mask bit by
left shift fixed bits (e.g. 16 bits), so we add this divider clock
to handle it.
Signed-off-by: Jorge Ramirez-Ortiz
Signed-off-by: Bintian Wang
Acked-by: Haojian Zhuang
Reviewed-by: Zhangfei Gao
Tested-by: Will Deacon
Tested-by: Tyler Baker
---
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile | 4 +-
drivers/clk/hisilicon/Kconfig | 6 +
drivers/clk/hisilicon/Makefile| 3 +-
drivers/clk/hisilicon/clk-hi6220.c| 284 ++
drivers/clk/hisilicon/clk.c | 29 +++
drivers/clk/hisilicon/clk.h | 17 ++
drivers/clk/hisilicon/clkdivider-hi6220.c | 156
8 files changed, 496 insertions(+), 4 deletions(-)
create mode 100644 drivers/clk/hisilicon/Kconfig
create mode 100644 drivers/clk/hisilicon/clk-hi6220.c
create mode 100644 drivers/clk/hisilicon/clkdivider-hi6220.c
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index de8c58f..cd6029d4 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -151,6 +151,7 @@ config COMMON_CLK_CDCE706
This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
source "drivers/clk/bcm/Kconfig"
+source "drivers/clk/hisilicon/Kconfig"
source "drivers/clk/qcom/Kconfig"
endmenu
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index d2d5e6c..440ef72 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -47,9 +47,7 @@ obj-$(CONFIG_COMMON_CLK_PWM) += clk-pwm.o
obj-$(CONFIG_COMMON_CLK_AT91) += at91/
obj-$(CONFIG_ARCH_BCM_MOBILE) += bcm/
obj-$(CONFIG_ARCH_BERLIN) += berlin/
-obj-$(CONFIG_ARCH_HI3xxx) += hisilicon/
-obj-$(CONFIG_ARCH_HIP04) += hisilicon/
-obj-$(CONFIG_ARCH_HIX5HD2) += hisilicon/
+obj-$(CONFIG_ARCH_HISI)+= hisilicon/
obj-$(CONFIG_ARCH_MXC) += imx/
obj-$(CONFIG_COMMON_CLK_KEYSTONE) += keystone/
obj-$(CONFIG_ARCH_MEDIATEK)+= mediatek/
diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
new file mode 100644
index 000..b4165ba
--- /dev/null
+++ b/drivers/clk/hisilicon/Kconfig
@@ -0,0 +1,6 @@
+config COMMON_CLK_HI6220
+ bool "Hi6220 Clock Driver"
+ depends on ARCH_HISI || COMPILE_TEST
+ default ARCH_HISI
+ help
+ Build the Hisilicon Hi6220 clock driver based on the common clock
framework.
diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile
index 038c02f..48f0116 100644
--- a/drivers/clk/hisilicon/Makefile
+++ b/drivers/clk/hisilicon/Makefile
@@ -2,8 +2,9 @@
# Hisilicon Clock specific Makefile
#
-obj-y += clk.o clkgate-separated.o
+obj-y += clk.o clkgate-separated.o clkdivider-hi6220.o
obj-$(CONFIG_ARCH_HI3xxx) += clk-hi3620.o
obj-$(CONFIG_ARCH_HIP04) += clk-hip04.o
obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o
+obj-$(CONFIG_COMMON_CLK_HI6220)+= clk-hi6220.o
diff --git a/drivers/clk/hisilicon/clk-hi6220.c
b/drivers/clk/hisilicon/clk-hi6220.c
new file mode 100644
index 000..4563343
--- /dev/null
+++ b/drivers/clk/hisilicon/clk-hi6220.c
@@ -0,0 +1,284 @@
+/*
+ * Hisilicon Hi6220 clock driver
+ *
+ * Copyright (c) 2015 Hisilicon Limited.
+ *
+ * Author: Bintian Wang
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include "clk.h"
+
+
+/* clocks in AO (always on) controller */
+static struct hisi_fixed_rate_clock hi6220_fixed_rate_clks[] __initdata = {
+ { HI6220_REF32K,"ref32k", NULL, CLK_IS_ROOT, 32764, },
+ { HI6220_CLK_TCXO, "clk_tcxo", NULL, CLK_IS_ROOT, 1920, },
+ { HI6220_MMC1_PAD, "mmc1_pad", NULL, CLK_IS_ROOT, 1, },
+ { HI6220_MMC2_PAD, "mmc2_pad", NULL, CLK_IS_ROOT, 1, },
+ { HI6220_MMC0_PAD, "mmc0_pad", NULL, CLK_IS_ROOT, 2, },
+ { HI6220_PLL_BBP, "bbppll0", NULL, CLK_IS_ROOT, 24576, },
+ { HI6220_PLL_GPU, "gpupll", NULL, CLK_IS_ROOT, 10,},
+ { HI6220_PLL1_DDR, "ddrpll1", NULL, CLK_IS_ROOT, 106600,},
+ { HI6220_PLL_SYS, "syspll", NULL, CLK_IS_ROOT, 12,},
+
[PATCH v8 5/7] dt-bindings: Add header file of hi6220 clock driver
Add the header file "hi6220-clock.h" used by both hi6220 clock driver and hi6220 device tree file. Suggested-by: Stephen Boyd Signed-off-by: Bintian Wang --- include/dt-bindings/clock/hi6220-clock.h | 173 +++ 1 file changed, 173 insertions(+) create mode 100644 include/dt-bindings/clock/hi6220-clock.h diff --git a/include/dt-bindings/clock/hi6220-clock.h b/include/dt-bindings/clock/hi6220-clock.h new file mode 100644 index 000..70ee383 --- /dev/null +++ b/include/dt-bindings/clock/hi6220-clock.h @@ -0,0 +1,173 @@ +/* + * Copyright (c) 2015 Hisilicon Limited. + * + * Author: Bintian Wang + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __DT_BINDINGS_CLOCK_HI6220_H +#define __DT_BINDINGS_CLOCK_HI6220_H + +/* clk in Hi6220 AO (always on) controller */ +#define HI6220_NONE_CLOCK 0 + +/* fixed rate clocks */ +#define HI6220_REF32K 1 +#define HI6220_CLK_TCXO2 +#define HI6220_MMC1_PAD3 +#define HI6220_MMC2_PAD4 +#define HI6220_MMC0_PAD5 +#define HI6220_PLL_BBP 6 +#define HI6220_PLL_GPU 7 +#define HI6220_PLL1_DDR8 +#define HI6220_PLL_SYS 9 +#define HI6220_PLL_SYS_MEDIA 10 +#define HI6220_DDR_SRC 11 +#define HI6220_PLL_MEDIA 12 +#define HI6220_PLL_DDR 13 + +/* fixed factor clocks */ +#define HI6220_300M14 +#define HI6220_150M15 +#define HI6220_PICOPHY_SRC 16 +#define HI6220_MMC0_SRC_SEL17 +#define HI6220_MMC1_SRC_SEL18 +#define HI6220_MMC2_SRC_SEL19 +#define HI6220_VPU_CODEC 20 +#define HI6220_MMC0_SMP21 +#define HI6220_MMC1_SMP22 +#define HI6220_MMC2_SMP23 + +/* gate clocks */ +#define HI6220_WDT0_PCLK 24 +#define HI6220_WDT1_PCLK 25 +#define HI6220_WDT2_PCLK 26 +#define HI6220_TIMER0_PCLK 27 +#define HI6220_TIMER1_PCLK 28 +#define HI6220_TIMER2_PCLK 29 +#define HI6220_TIMER3_PCLK 30 +#define HI6220_TIMER4_PCLK 31 +#define HI6220_TIMER5_PCLK 32 +#define HI6220_TIMER6_PCLK 33 +#define HI6220_TIMER7_PCLK 34 +#define HI6220_TIMER8_PCLK 35 +#define HI6220_UART0_PCLK 36 + +#define HI6220_AO_NR_CLKS 37 + +/* clk in Hi6220 systrl */ +/* gate clock */ +#define HI6220_MMC0_CLK1 +#define HI6220_MMC0_CIUCLK 2 +#define HI6220_MMC1_CLK3 +#define HI6220_MMC1_CIUCLK 4 +#define HI6220_MMC2_CLK5 +#define HI6220_MMC2_CIUCLK 6 +#define HI6220_USBOTG_HCLK 7 +#define HI6220_CLK_PICOPHY 8 +#define HI6220_HIFI9 +#define HI6220_DACODEC_PCLK10 +#define HI6220_EDMAC_ACLK 11 +#define HI6220_CS_ATB 12 +#define HI6220_I2C0_CLK13 +#define HI6220_I2C1_CLK14 +#define HI6220_I2C2_CLK15 +#define HI6220_I2C3_CLK16 +#define HI6220_UART1_PCLK 17 +#define HI6220_UART2_PCLK 18 +#define HI6220_UART3_PCLK 19 +#define HI6220_UART4_PCLK 20 +#define HI6220_SPI_CLK 21 +#define HI6220_TSENSOR_CLK 22 +#define HI6220_MMU_CLK 23 +#define HI6220_HIFI_SEL24 +#define HI6220_MMC0_SYSPLL 25 +#define HI6220_MMC1_SYSPLL 26 +#define HI6220_MMC2_SYSPLL 27 +#define HI6220_MMC0_SEL28 +#define HI6220_MMC1_SEL29 +#define HI6220_BBPPLL_SEL 30 +#define HI6220_MEDIA_PLL_SRC 31 +#define HI6220_MMC2_SEL32 +#define HI6220_CS_ATB_SYSPLL 33 + +/* mux clocks */ +#define HI6220_MMC0_SRC34 +#define HI6220_MMC0_SMP_IN 35 +#define HI6220_MMC1_SRC36 +#define HI6220_MMC1_SMP_IN 37 +#define HI6220_MMC2_SRC38 +#define HI6220_MMC2_SMP_IN 39 +#define HI6220_HIFI_SRC40 +#define HI6220_UART1_SRC 41 +#define HI6220_UART2_SRC 42 +#define HI6220_UART3_SRC 43 +#define HI6220_UART4_SRC 44 +#define HI6220_MMC0_MUX0 45 +#define HI6220_MMC1_MUX0 46 +#define HI6220_MMC2_MUX0 47 +#define HI6220_MMC0_MUX1 48 +#define HI6220_MMC1_MUX1 49 +#define HI6220_MMC2_MUX1 50 + +/* divider clocks */ +#define HI6220_CLK_BUS 51 +#define HI6220_MMC0_DIV52 +#define HI6220_MMC1_DIV53 +#define HI6220_MMC2_DIV54 +#define HI6220_HIFI_DIV55 +#define HI6220_BBPPLL0_DIV 56 +#define HI6220_CS_DAPB 57 +#define HI6220_CS_ATB_DIV 58 + +#define HI6220_SYS_NR_CLKS 59 + +/* clk in Hi6220 media controller */ +/* gate clocks */ +#define HI6220_DSI_PCLK1 +#define HI6220_G3D_PCLK2 +#define HI6220_ACLK_CODEC_VPU 3 +#define HI6220_ISP_SCLK4 +#define HI6220_ADE_CORE
[PATCH v8 6/7] clk: hi6220: Clock driver support for Hisilicon hi6220 SoC
Add clock drivers for hi6220 SoC, this driver controls the SoC
registers to supply different clocks to different IPs in the SoC.
We add one divider clock for hi6220 because the divider in hi6220
also has a mask bit but it doesnot obey the rule defined by flag
CLK_DIVIDER_HIWORD_MASK, we can not get index of the mask bit by
left shift fixed bits (e.g. 16 bits), so we add this divider clock
to handle it.
Signed-off-by: Jorge Ramirez-Ortiz jorge.ramirez-or...@linaro.org
Signed-off-by: Bintian Wang bintian.w...@huawei.com
Acked-by: Haojian Zhuang haojian.zhu...@linaro.org
Reviewed-by: Zhangfei Gao zhangfei@linaro.org
Tested-by: Will Deacon will.dea...@arm.com
Tested-by: Tyler Baker tyler.ba...@linaro.org
---
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile | 4 +-
drivers/clk/hisilicon/Kconfig | 6 +
drivers/clk/hisilicon/Makefile| 3 +-
drivers/clk/hisilicon/clk-hi6220.c| 284 ++
drivers/clk/hisilicon/clk.c | 29 +++
drivers/clk/hisilicon/clk.h | 17 ++
drivers/clk/hisilicon/clkdivider-hi6220.c | 156
8 files changed, 496 insertions(+), 4 deletions(-)
create mode 100644 drivers/clk/hisilicon/Kconfig
create mode 100644 drivers/clk/hisilicon/clk-hi6220.c
create mode 100644 drivers/clk/hisilicon/clkdivider-hi6220.c
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index de8c58f..cd6029d4 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -151,6 +151,7 @@ config COMMON_CLK_CDCE706
This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
source drivers/clk/bcm/Kconfig
+source drivers/clk/hisilicon/Kconfig
source drivers/clk/qcom/Kconfig
endmenu
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index d2d5e6c..440ef72 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -47,9 +47,7 @@ obj-$(CONFIG_COMMON_CLK_PWM) += clk-pwm.o
obj-$(CONFIG_COMMON_CLK_AT91) += at91/
obj-$(CONFIG_ARCH_BCM_MOBILE) += bcm/
obj-$(CONFIG_ARCH_BERLIN) += berlin/
-obj-$(CONFIG_ARCH_HI3xxx) += hisilicon/
-obj-$(CONFIG_ARCH_HIP04) += hisilicon/
-obj-$(CONFIG_ARCH_HIX5HD2) += hisilicon/
+obj-$(CONFIG_ARCH_HISI)+= hisilicon/
obj-$(CONFIG_ARCH_MXC) += imx/
obj-$(CONFIG_COMMON_CLK_KEYSTONE) += keystone/
obj-$(CONFIG_ARCH_MEDIATEK)+= mediatek/
diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
new file mode 100644
index 000..b4165ba
--- /dev/null
+++ b/drivers/clk/hisilicon/Kconfig
@@ -0,0 +1,6 @@
+config COMMON_CLK_HI6220
+ bool Hi6220 Clock Driver
+ depends on ARCH_HISI || COMPILE_TEST
+ default ARCH_HISI
+ help
+ Build the Hisilicon Hi6220 clock driver based on the common clock
framework.
diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile
index 038c02f..48f0116 100644
--- a/drivers/clk/hisilicon/Makefile
+++ b/drivers/clk/hisilicon/Makefile
@@ -2,8 +2,9 @@
# Hisilicon Clock specific Makefile
#
-obj-y += clk.o clkgate-separated.o
+obj-y += clk.o clkgate-separated.o clkdivider-hi6220.o
obj-$(CONFIG_ARCH_HI3xxx) += clk-hi3620.o
obj-$(CONFIG_ARCH_HIP04) += clk-hip04.o
obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o
+obj-$(CONFIG_COMMON_CLK_HI6220)+= clk-hi6220.o
diff --git a/drivers/clk/hisilicon/clk-hi6220.c
b/drivers/clk/hisilicon/clk-hi6220.c
new file mode 100644
index 000..4563343
--- /dev/null
+++ b/drivers/clk/hisilicon/clk-hi6220.c
@@ -0,0 +1,284 @@
+/*
+ * Hisilicon Hi6220 clock driver
+ *
+ * Copyright (c) 2015 Hisilicon Limited.
+ *
+ * Author: Bintian Wang bintian.w...@huawei.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/kernel.h
+#include linux/clk-provider.h
+#include linux/clkdev.h
+#include linux/io.h
+#include linux/of.h
+#include linux/of_address.h
+#include linux/of_device.h
+#include linux/slab.h
+
+#include dt-bindings/clock/hi6220-clock.h
+
+#include clk.h
+
+
+/* clocks in AO (always on) controller */
+static struct hisi_fixed_rate_clock hi6220_fixed_rate_clks[] __initdata = {
+ { HI6220_REF32K,ref32k, NULL, CLK_IS_ROOT, 32764, },
+ { HI6220_CLK_TCXO, clk_tcxo, NULL, CLK_IS_ROOT, 1920, },
+ { HI6220_MMC1_PAD, mmc1_pad, NULL, CLK_IS_ROOT, 1, },
+ { HI6220_MMC2_PAD, mmc2_pad, NULL, CLK_IS_ROOT, 1, },
+ { HI6220_MMC0_PAD, mmc0_pad, NULL, CLK_IS_ROOT, 2, },
+ { HI6220_PLL_BBP, bbppll0, NULL, CLK_IS_ROOT, 24576, },
+ { HI6220_PLL_GPU, gpupll, NULL, CLK_IS_ROOT, 10,},
+ { HI6220_PLL1_DDR, ddrpll1, NULL
[PATCH v8 5/7] dt-bindings: Add header file of hi6220 clock driver
Add the header file hi6220-clock.h used by both hi6220 clock driver and hi6220 device tree file. Suggested-by: Stephen Boyd sb...@codeaurora.org Signed-off-by: Bintian Wang bintian.w...@huawei.com --- include/dt-bindings/clock/hi6220-clock.h | 173 +++ 1 file changed, 173 insertions(+) create mode 100644 include/dt-bindings/clock/hi6220-clock.h diff --git a/include/dt-bindings/clock/hi6220-clock.h b/include/dt-bindings/clock/hi6220-clock.h new file mode 100644 index 000..70ee383 --- /dev/null +++ b/include/dt-bindings/clock/hi6220-clock.h @@ -0,0 +1,173 @@ +/* + * Copyright (c) 2015 Hisilicon Limited. + * + * Author: Bintian Wang bintian.w...@huawei.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __DT_BINDINGS_CLOCK_HI6220_H +#define __DT_BINDINGS_CLOCK_HI6220_H + +/* clk in Hi6220 AO (always on) controller */ +#define HI6220_NONE_CLOCK 0 + +/* fixed rate clocks */ +#define HI6220_REF32K 1 +#define HI6220_CLK_TCXO2 +#define HI6220_MMC1_PAD3 +#define HI6220_MMC2_PAD4 +#define HI6220_MMC0_PAD5 +#define HI6220_PLL_BBP 6 +#define HI6220_PLL_GPU 7 +#define HI6220_PLL1_DDR8 +#define HI6220_PLL_SYS 9 +#define HI6220_PLL_SYS_MEDIA 10 +#define HI6220_DDR_SRC 11 +#define HI6220_PLL_MEDIA 12 +#define HI6220_PLL_DDR 13 + +/* fixed factor clocks */ +#define HI6220_300M14 +#define HI6220_150M15 +#define HI6220_PICOPHY_SRC 16 +#define HI6220_MMC0_SRC_SEL17 +#define HI6220_MMC1_SRC_SEL18 +#define HI6220_MMC2_SRC_SEL19 +#define HI6220_VPU_CODEC 20 +#define HI6220_MMC0_SMP21 +#define HI6220_MMC1_SMP22 +#define HI6220_MMC2_SMP23 + +/* gate clocks */ +#define HI6220_WDT0_PCLK 24 +#define HI6220_WDT1_PCLK 25 +#define HI6220_WDT2_PCLK 26 +#define HI6220_TIMER0_PCLK 27 +#define HI6220_TIMER1_PCLK 28 +#define HI6220_TIMER2_PCLK 29 +#define HI6220_TIMER3_PCLK 30 +#define HI6220_TIMER4_PCLK 31 +#define HI6220_TIMER5_PCLK 32 +#define HI6220_TIMER6_PCLK 33 +#define HI6220_TIMER7_PCLK 34 +#define HI6220_TIMER8_PCLK 35 +#define HI6220_UART0_PCLK 36 + +#define HI6220_AO_NR_CLKS 37 + +/* clk in Hi6220 systrl */ +/* gate clock */ +#define HI6220_MMC0_CLK1 +#define HI6220_MMC0_CIUCLK 2 +#define HI6220_MMC1_CLK3 +#define HI6220_MMC1_CIUCLK 4 +#define HI6220_MMC2_CLK5 +#define HI6220_MMC2_CIUCLK 6 +#define HI6220_USBOTG_HCLK 7 +#define HI6220_CLK_PICOPHY 8 +#define HI6220_HIFI9 +#define HI6220_DACODEC_PCLK10 +#define HI6220_EDMAC_ACLK 11 +#define HI6220_CS_ATB 12 +#define HI6220_I2C0_CLK13 +#define HI6220_I2C1_CLK14 +#define HI6220_I2C2_CLK15 +#define HI6220_I2C3_CLK16 +#define HI6220_UART1_PCLK 17 +#define HI6220_UART2_PCLK 18 +#define HI6220_UART3_PCLK 19 +#define HI6220_UART4_PCLK 20 +#define HI6220_SPI_CLK 21 +#define HI6220_TSENSOR_CLK 22 +#define HI6220_MMU_CLK 23 +#define HI6220_HIFI_SEL24 +#define HI6220_MMC0_SYSPLL 25 +#define HI6220_MMC1_SYSPLL 26 +#define HI6220_MMC2_SYSPLL 27 +#define HI6220_MMC0_SEL28 +#define HI6220_MMC1_SEL29 +#define HI6220_BBPPLL_SEL 30 +#define HI6220_MEDIA_PLL_SRC 31 +#define HI6220_MMC2_SEL32 +#define HI6220_CS_ATB_SYSPLL 33 + +/* mux clocks */ +#define HI6220_MMC0_SRC34 +#define HI6220_MMC0_SMP_IN 35 +#define HI6220_MMC1_SRC36 +#define HI6220_MMC1_SMP_IN 37 +#define HI6220_MMC2_SRC38 +#define HI6220_MMC2_SMP_IN 39 +#define HI6220_HIFI_SRC40 +#define HI6220_UART1_SRC 41 +#define HI6220_UART2_SRC 42 +#define HI6220_UART3_SRC 43 +#define HI6220_UART4_SRC 44 +#define HI6220_MMC0_MUX0 45 +#define HI6220_MMC1_MUX0 46 +#define HI6220_MMC2_MUX0 47 +#define HI6220_MMC0_MUX1 48 +#define HI6220_MMC1_MUX1 49 +#define HI6220_MMC2_MUX1 50 + +/* divider clocks */ +#define HI6220_CLK_BUS 51 +#define HI6220_MMC0_DIV52 +#define HI6220_MMC1_DIV53 +#define HI6220_MMC2_DIV54 +#define HI6220_HIFI_DIV55 +#define HI6220_BBPPLL0_DIV 56 +#define HI6220_CS_DAPB 57 +#define HI6220_CS_ATB_DIV 58 + +#define HI6220_SYS_NR_CLKS 59 + +/* clk in Hi6220 media controller */ +/* gate clocks */ +#define HI6220_DSI_PCLK1 +#define HI6220_G3D_PCLK2 +#define HI6220_ACLK_CODEC_VPU 3 +#define HI6220_ISP_SCLK
[PATCH v8 4/7] clk: hisilicon: Remove __init for marking function prototypes
__init markings on function prototypes are useless, so remove them. Suggested-by: Stephen Boyd sb...@codeaurora.org Signed-off-by: Bintian Wang bintian.w...@huawei.com --- drivers/clk/hisilicon/clk.h | 22 +++--- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/clk/hisilicon/clk.h b/drivers/clk/hisilicon/clk.h index 31083ff..6b6f994 100644 --- a/drivers/clk/hisilicon/clk.h +++ b/drivers/clk/hisilicon/clk.h @@ -95,17 +95,17 @@ struct clk *hisi_register_clkgate_sep(struct device *, const char *, void __iomem *, u8, u8, spinlock_t *); -struct hisi_clock_data __init *hisi_clk_init(struct device_node *, int); -void __init hisi_clk_register_fixed_rate(struct hisi_fixed_rate_clock *, - int, struct hisi_clock_data *); -void __init hisi_clk_register_fixed_factor(struct hisi_fixed_factor_clock *, - int, struct hisi_clock_data *); -void __init hisi_clk_register_mux(struct hisi_mux_clock *, int, +struct hisi_clock_data *hisi_clk_init(struct device_node *, int); +void hisi_clk_register_fixed_rate(struct hisi_fixed_rate_clock *, + int, struct hisi_clock_data *); +void hisi_clk_register_fixed_factor(struct hisi_fixed_factor_clock *, + int, struct hisi_clock_data *); +void hisi_clk_register_mux(struct hisi_mux_clock *, int, struct hisi_clock_data *); -void __init hisi_clk_register_divider(struct hisi_divider_clock *, +void hisi_clk_register_divider(struct hisi_divider_clock *, + int, struct hisi_clock_data *); +void hisi_clk_register_gate(struct hisi_gate_clock *, + int, struct hisi_clock_data *); +void hisi_clk_register_gate_sep(struct hisi_gate_clock *, int, struct hisi_clock_data *); -void __init hisi_clk_register_gate(struct hisi_gate_clock *, - int, struct hisi_clock_data *); -void __init hisi_clk_register_gate_sep(struct hisi_gate_clock *, - int, struct hisi_clock_data *); #endif /* __HISI_CLK_H */ -- 1.9.1 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v7 6/7] clk: hi6220: Clock driver support for Hisilicon hi6220 SoC
Hello Stephen,
On 2015/5/22 2:00, Stephen Boyd wrote:
On 05/20/15 20:57, Bintian wrote:
+
+static void __init hi6220_clk_sys_init(struct device_node *np)
+{
+struct hisi_clock_data *clk_data;
+
+clk_data = hisi_clk_init(np, HI6220_SYS_NR_CLKS);
+if (!clk_data)
+return;
+
+hisi_clk_register_gate_sep(hi6220_separated_gate_clks_sys,
+ARRAY_SIZE(hi6220_separated_gate_clks_sys), clk_data);
+
+hisi_clk_register_mux(hi6220_mux_clks_sys,
+ARRAY_SIZE(hi6220_mux_clks_sys), clk_data);
+
+hi6220_clk_register_divider(hi6220_div_clks_sys,
+ARRAY_SIZE(hi6220_div_clks_sys), clk_data);
+
+if (!clk_data_ao)
+return;
+
+/* enable high speed clock on UART1 mux */
+clk_set_parent(clk_data->clk_data.clks[HI6220_UART1_SRC],
+clk_data_ao->clk_data.clks[HI6220_150M]);
Sorry I missed this one earlier. Can we do this clk_set_parent() through
assigned-parents instead?
Uart1 has two clock parents in hi6220, and use "clk_tcxo" by default,
we use uart1 to connect BT in HiKey, and switch to "clk_150m" for high
speed mode of BT, but pl011 has no code to set clock rate or set clock
parents operation, so it's a easy way to do that here.
Is pl011 the uart device? Does it have a node in DT somewhere? If it
does, then we could put the assigned-parents properties in that node so
that when the pl011 probes the uart1 clock has its parent set to
clk_150m. See the "Assigned clock parents and rates" section of
Documentation/devicetree/bindings/clock/clock-bindings.txt.
I will verify this.
If it is OK, I will remove "clk_set_parent" from this patch.
Thanks,
Bintian
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v7 6/7] clk: hi6220: Clock driver support for Hisilicon hi6220 SoC
Hello Stephen,
On 2015/5/22 2:00, Stephen Boyd wrote:
On 05/20/15 20:57, Bintian wrote:
+
+static void __init hi6220_clk_sys_init(struct device_node *np)
+{
+struct hisi_clock_data *clk_data;
+
+clk_data = hisi_clk_init(np, HI6220_SYS_NR_CLKS);
+if (!clk_data)
+return;
+
+hisi_clk_register_gate_sep(hi6220_separated_gate_clks_sys,
+ARRAY_SIZE(hi6220_separated_gate_clks_sys), clk_data);
+
+hisi_clk_register_mux(hi6220_mux_clks_sys,
+ARRAY_SIZE(hi6220_mux_clks_sys), clk_data);
+
+hi6220_clk_register_divider(hi6220_div_clks_sys,
+ARRAY_SIZE(hi6220_div_clks_sys), clk_data);
+
+if (!clk_data_ao)
+return;
+
+/* enable high speed clock on UART1 mux */
+clk_set_parent(clk_data-clk_data.clks[HI6220_UART1_SRC],
+clk_data_ao-clk_data.clks[HI6220_150M]);
Sorry I missed this one earlier. Can we do this clk_set_parent() through
assigned-parents instead?
Uart1 has two clock parents in hi6220, and use clk_tcxo by default,
we use uart1 to connect BT in HiKey, and switch to clk_150m for high
speed mode of BT, but pl011 has no code to set clock rate or set clock
parents operation, so it's a easy way to do that here.
Is pl011 the uart device? Does it have a node in DT somewhere? If it
does, then we could put the assigned-parents properties in that node so
that when the pl011 probes the uart1 clock has its parent set to
clk_150m. See the Assigned clock parents and rates section of
Documentation/devicetree/bindings/clock/clock-bindings.txt.
I will verify this.
If it is OK, I will remove clk_set_parent from this patch.
Thanks,
Bintian
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v7 6/7] clk: hi6220: Clock driver support for Hisilicon hi6220 SoC
Hello Stephen, Arnd,
On 2015/5/21 6:25, Stephen Boyd wrote:
On 05/20/15 03:29, Bintian Wang wrote:
Add clock drivers for hi6220 SoC, this driver controls the SoC
registers to supply different clocks to different IPs in the SoC.
We add one divider clock for hi6220 because the divider in hi6220
also has a mask bit but it doesnot obey the rule defined by flag
"CLK_DIVIDER_HIWORD_MASK", we can not get index of the mask bit by
left shift fixed bits (e.g. 16 bits), so we add this divider clock
to handle it.
Signed-off-by: Jorge Ramirez-Ortiz
Signed-off-by: Bintian Wang
Acked-by: Haojian Zhuang
Reviewed-by: Zhangfei Gao
Tested-by: Will Deacon
Tested-by: Tyler Baker
---
drivers/clk/Kconfig |2 +
drivers/clk/Makefile |4 +-
drivers/clk/hisilicon/Kconfig |6 +
drivers/clk/hisilicon/Makefile|3 +-
drivers/clk/hisilicon/clk-hi6220.c| 291 +
drivers/clk/hisilicon/clk.c | 29 +++
drivers/clk/hisilicon/clk.h | 17 ++
drivers/clk/hisilicon/clkdivider-hi6220.c | 156
include/dt-bindings/clock/hi6220-clock.h | 173 +
9 files changed, 677 insertions(+), 4 deletions(-)
create mode 100644 drivers/clk/hisilicon/Kconfig
create mode 100644 drivers/clk/hisilicon/clk-hi6220.c
create mode 100644 drivers/clk/hisilicon/clkdivider-hi6220.c
create mode 100644 include/dt-bindings/clock/hi6220-clock.h
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 9897f35..18bb930 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -150,6 +150,8 @@ config COMMON_CLK_CDCE706
---help---
This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
+source "drivers/clk/hisilicon/Kconfig"
+
source "drivers/clk/qcom/Kconfig"
There's going to be a merge conflict here if this doesn't go through the
clk tree.
Hello Arnd, how about the clk driver of hi6220 goes through the clk
tree and those dts and arch patches go through arm-soc?
If there is no problem, I will split the clock header file to a
single patch for your convenience.
+
+static void __init hi6220_clk_sys_init(struct device_node *np)
+{
+ struct hisi_clock_data *clk_data;
+
+ clk_data = hisi_clk_init(np, HI6220_SYS_NR_CLKS);
+ if (!clk_data)
+ return;
+
+ hisi_clk_register_gate_sep(hi6220_separated_gate_clks_sys,
+ ARRAY_SIZE(hi6220_separated_gate_clks_sys), clk_data);
+
+ hisi_clk_register_mux(hi6220_mux_clks_sys,
+ ARRAY_SIZE(hi6220_mux_clks_sys), clk_data);
+
+ hi6220_clk_register_divider(hi6220_div_clks_sys,
+ ARRAY_SIZE(hi6220_div_clks_sys), clk_data);
+
+ if (!clk_data_ao)
+ return;
+
+ /* enable high speed clock on UART1 mux */
+ clk_set_parent(clk_data->clk_data.clks[HI6220_UART1_SRC],
+ clk_data_ao->clk_data.clks[HI6220_150M]);
Sorry I missed this one earlier. Can we do this clk_set_parent() through
assigned-parents instead?
Uart1 has two clock parents in hi6220, and use "clk_tcxo" by default,
we use uart1 to connect BT in HiKey, and switch to "clk_150m" for high
speed mode of BT, but pl011 has no code to set clock rate or set clock
parents operation, so it's a easy way to do that here.
I expected an #include for the
usage of clk_set_parent() here so I didn't look hard to see if consumer
APIs were being used.
OK, I will add in next version 8.
Thanks,
Bintian
Otherwise the patch looks fine.
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[PATCH v7 6/7] clk: hi6220: Clock driver support for Hisilicon hi6220 SoC
Add clock drivers for hi6220 SoC, this driver controls the SoC
registers to supply different clocks to different IPs in the SoC.
We add one divider clock for hi6220 because the divider in hi6220
also has a mask bit but it doesnot obey the rule defined by flag
"CLK_DIVIDER_HIWORD_MASK", we can not get index of the mask bit by
left shift fixed bits (e.g. 16 bits), so we add this divider clock
to handle it.
Signed-off-by: Jorge Ramirez-Ortiz
Signed-off-by: Bintian Wang
Acked-by: Haojian Zhuang
Reviewed-by: Zhangfei Gao
Tested-by: Will Deacon
Tested-by: Tyler Baker
---
drivers/clk/Kconfig |2 +
drivers/clk/Makefile |4 +-
drivers/clk/hisilicon/Kconfig |6 +
drivers/clk/hisilicon/Makefile|3 +-
drivers/clk/hisilicon/clk-hi6220.c| 291 +
drivers/clk/hisilicon/clk.c | 29 +++
drivers/clk/hisilicon/clk.h | 17 ++
drivers/clk/hisilicon/clkdivider-hi6220.c | 156
include/dt-bindings/clock/hi6220-clock.h | 173 +
9 files changed, 677 insertions(+), 4 deletions(-)
create mode 100644 drivers/clk/hisilicon/Kconfig
create mode 100644 drivers/clk/hisilicon/clk-hi6220.c
create mode 100644 drivers/clk/hisilicon/clkdivider-hi6220.c
create mode 100644 include/dt-bindings/clock/hi6220-clock.h
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 9897f35..18bb930 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -150,6 +150,8 @@ config COMMON_CLK_CDCE706
---help---
This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
+source "drivers/clk/hisilicon/Kconfig"
+
source "drivers/clk/qcom/Kconfig"
endmenu
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 3d00c25..9719954 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -47,9 +47,7 @@ obj-$(CONFIG_COMMON_CLK_PWM) += clk-pwm.o
obj-$(CONFIG_COMMON_CLK_AT91) += at91/
obj-$(CONFIG_ARCH_BCM_MOBILE) += bcm/
obj-$(CONFIG_ARCH_BERLIN) += berlin/
-obj-$(CONFIG_ARCH_HI3xxx) += hisilicon/
-obj-$(CONFIG_ARCH_HIP04) += hisilicon/
-obj-$(CONFIG_ARCH_HIX5HD2) += hisilicon/
+obj-$(CONFIG_ARCH_HISI)+= hisilicon/
obj-$(CONFIG_COMMON_CLK_KEYSTONE) += keystone/
ifeq ($(CONFIG_COMMON_CLK), y)
obj-$(CONFIG_ARCH_MMP) += mmp/
diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
new file mode 100644
index 000..b4165ba
--- /dev/null
+++ b/drivers/clk/hisilicon/Kconfig
@@ -0,0 +1,6 @@
+config COMMON_CLK_HI6220
+ bool "Hi6220 Clock Driver"
+ depends on ARCH_HISI || COMPILE_TEST
+ default ARCH_HISI
+ help
+ Build the Hisilicon Hi6220 clock driver based on the common clock
framework.
diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile
index 038c02f..48f0116 100644
--- a/drivers/clk/hisilicon/Makefile
+++ b/drivers/clk/hisilicon/Makefile
@@ -2,8 +2,9 @@
# Hisilicon Clock specific Makefile
#
-obj-y += clk.o clkgate-separated.o
+obj-y += clk.o clkgate-separated.o clkdivider-hi6220.o
obj-$(CONFIG_ARCH_HI3xxx) += clk-hi3620.o
obj-$(CONFIG_ARCH_HIP04) += clk-hip04.o
obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o
+obj-$(CONFIG_COMMON_CLK_HI6220)+= clk-hi6220.o
diff --git a/drivers/clk/hisilicon/clk-hi6220.c
b/drivers/clk/hisilicon/clk-hi6220.c
new file mode 100644
index 000..438326f
--- /dev/null
+++ b/drivers/clk/hisilicon/clk-hi6220.c
@@ -0,0 +1,291 @@
+/*
+ * Hisilicon Hi6220 clock driver
+ *
+ * Copyright (c) 2015 Hisilicon Limited.
+ *
+ * Author: Bintian Wang
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include "clk.h"
+
+
+/* clocks in AO (always on) controller */
+static struct hisi_fixed_rate_clock hi6220_fixed_rate_clks[] __initdata = {
+ { HI6220_REF32K,"ref32k", NULL, CLK_IS_ROOT, 32764, },
+ { HI6220_CLK_TCXO, "clk_tcxo", NULL, CLK_IS_ROOT, 1920, },
+ { HI6220_MMC1_PAD, "mmc1_pad", NULL, CLK_IS_ROOT, 1, },
+ { HI6220_MMC2_PAD, "mmc2_pad", NULL, CLK_IS_ROOT, 1, },
+ { HI6220_MMC0_PAD, "mmc0_pad", NULL, CLK_IS_ROOT, 2, },
+ { HI6220_PLL_BBP, "bbppll0", NULL, CLK_IS_ROOT, 24576, },
+ { HI6220_PLL_GPU, "gpupll", NULL, CLK_IS_ROOT, 10,},
+ { HI6220_PLL1_DDR, "ddrpll1", NULL, CLK_IS_ROOT, 106600,},
+ { HI6220
[PATCH v7 5/7] clk: hisilicon: Remove __init for marking function prototypes
__init markings on function prototypes are useless, so remove them. Suggested-by: Stephen Boyd Signed-off-by: Bintian Wang --- drivers/clk/hisilicon/clk.h | 22 +++--- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/clk/hisilicon/clk.h b/drivers/clk/hisilicon/clk.h index 31083ff..6b6f994 100644 --- a/drivers/clk/hisilicon/clk.h +++ b/drivers/clk/hisilicon/clk.h @@ -95,17 +95,17 @@ struct clk *hisi_register_clkgate_sep(struct device *, const char *, void __iomem *, u8, u8, spinlock_t *); -struct hisi_clock_data __init *hisi_clk_init(struct device_node *, int); -void __init hisi_clk_register_fixed_rate(struct hisi_fixed_rate_clock *, - int, struct hisi_clock_data *); -void __init hisi_clk_register_fixed_factor(struct hisi_fixed_factor_clock *, - int, struct hisi_clock_data *); -void __init hisi_clk_register_mux(struct hisi_mux_clock *, int, +struct hisi_clock_data *hisi_clk_init(struct device_node *, int); +void hisi_clk_register_fixed_rate(struct hisi_fixed_rate_clock *, + int, struct hisi_clock_data *); +void hisi_clk_register_fixed_factor(struct hisi_fixed_factor_clock *, + int, struct hisi_clock_data *); +void hisi_clk_register_mux(struct hisi_mux_clock *, int, struct hisi_clock_data *); -void __init hisi_clk_register_divider(struct hisi_divider_clock *, +void hisi_clk_register_divider(struct hisi_divider_clock *, + int, struct hisi_clock_data *); +void hisi_clk_register_gate(struct hisi_gate_clock *, + int, struct hisi_clock_data *); +void hisi_clk_register_gate_sep(struct hisi_gate_clock *, int, struct hisi_clock_data *); -void __init hisi_clk_register_gate(struct hisi_gate_clock *, - int, struct hisi_clock_data *); -void __init hisi_clk_register_gate_sep(struct hisi_gate_clock *, - int, struct hisi_clock_data *); #endif /* __HISI_CLK_H */ -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v6 5/6] clk: hi6220: Clock driver support for Hisilicon hi6220 SoC
Hello Stephen,
I will fix in version 7 based on all comments.
Thanks,
Bintian
On 2015/5/20 9:39, Stephen Boyd wrote:
On 05/16, Bintian Wang wrote:
@@ -94,18 +106,23 @@ struct clk *hisi_register_clkgate_sep(struct device *,
const char *,
const char *, unsigned long,
void __iomem *, u8,
u8, spinlock_t *);
+struct clk *hi6220_register_clkdiv(struct device *dev, const char *name,
+ const char *parent_name, unsigned long flags, void __iomem *reg,
+ u8 shift, u8 width, u32 mask_bit, spinlock_t *lock);
-struct hisi_clock_data __init *hisi_clk_init(struct device_node *, int);
-void __init hisi_clk_register_fixed_rate(struct hisi_fixed_rate_clock *,
+struct hisi_clock_data *hisi_clk_init(struct device_node *, int);
+void hisi_clk_register_fixed_rate(struct hisi_fixed_rate_clock *,
int, struct hisi_clock_data *);
-void __init hisi_clk_register_fixed_factor(struct hisi_fixed_factor_clock *,
+void hisi_clk_register_fixed_factor(struct hisi_fixed_factor_clock *,
int, struct hisi_clock_data *);
-void __init hisi_clk_register_mux(struct hisi_mux_clock *, int,
+void hisi_clk_register_mux(struct hisi_mux_clock *, int,
struct hisi_clock_data *);
-void __init hisi_clk_register_divider(struct hisi_divider_clock *,
+void hisi_clk_register_divider(struct hisi_divider_clock *,
int, struct hisi_clock_data *);
-void __init hisi_clk_register_gate(struct hisi_gate_clock *,
+void hisi_clk_register_gate(struct hisi_gate_clock *,
+ int, struct hisi_clock_data *);
+void hisi_clk_register_gate_sep(struct hisi_gate_clock *,
int, struct hisi_clock_data *);
-void __init hisi_clk_register_gate_sep(struct hisi_gate_clock *,
+void hi6220_clk_register_divider(struct hi6220_divider_clock *,
int, struct hisi_clock_data *);
Please don't do the mass __init removal in this patch. Do it in a
separate patch.
#endif/* __HISI_CLK_H */
diff --git a/drivers/clk/hisilicon/clkdivider-hi6220.c
b/drivers/clk/hisilicon/clkdivider-hi6220.c
new file mode 100644
index 000..bc85ef6
--- /dev/null
+++ b/drivers/clk/hisilicon/clkdivider-hi6220.c
@@ -0,0 +1,157 @@
+/*
+ * Hisilicon hi6220 SoC divider clock driver
+ *
+ * Copyright (c) 2015 Hisilicon Limited.
+ *
+ * Author: Bintian Wang
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
#include ?
+
+#define div_mask(width)((1 << (width)) - 1)
+
[..]
+
+struct clk *hi6220_register_clkdiv(struct device *dev, const char *name,
+ const char *parent_name, unsigned long flags, void __iomem *reg,
+ u8 shift, u8 width, u32 mask_bit, spinlock_t *lock)
+{
+ struct hi6220_clk_divider *div;
+ struct clk *clk;
+ struct clk_init_data init;
+ struct clk_div_table *table;
+ u32 max_div, min_div;
+ int i;
+
+ /* allocate the divider */
+ div = kzalloc(sizeof(struct hi6220_clk_divider), GFP_KERNEL);
nitpick: Use sizeof(*div) please.
+ if (!div)
+ return ERR_PTR(-ENOMEM);
+
+ /* Init the divider table */
+ max_div = div_mask(width) + 1;
+ min_div = 1;
+
+ table = kzalloc(sizeof(struct clk_div_table) * (max_div + 1),
And kcalloc() here please
+ GFP_KERNEL);
+ if (!table) {
+ kfree(div);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ for (i = 0; i < max_div; i++) {
+ table[i].div = min_div + i;
+ table[i].val = table[i].div - 1;
+ }
+
+ init.name = name;
+ init.ops = _clkdiv_ops;
+ init.flags = flags;
+ init.parent_names = parent_name ? _name : NULL;
+ init.num_parents = parent_name ? 1 : 0;
+
+ /* struct hi6220_clk_divider assignments */
+ div->reg = reg;
+ div->shift = shift;
+ div->width = width;
+ div->mask = mask_bit ? BIT(mask_bit) : 0;
+ div->lock = lock;
+ div->hw.init =
+ div->table = table;
+
+ /* register the clock */
+ clk = clk_register(dev, >hw);
+
Drop the newline here.
+ if (IS_ERR(clk)) {
+ kfree(table);
+ kfree(div);
+ }
+
+ return clk;
+}
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v6 5/6] clk: hi6220: Clock driver support for Hisilicon hi6220 SoC
Hello Stephen,
I will fix in version 7 based on all comments.
Thanks,
Bintian
On 2015/5/20 9:39, Stephen Boyd wrote:
On 05/16, Bintian Wang wrote:
@@ -94,18 +106,23 @@ struct clk *hisi_register_clkgate_sep(struct device *,
const char *,
const char *, unsigned long,
void __iomem *, u8,
u8, spinlock_t *);
+struct clk *hi6220_register_clkdiv(struct device *dev, const char *name,
+ const char *parent_name, unsigned long flags, void __iomem *reg,
+ u8 shift, u8 width, u32 mask_bit, spinlock_t *lock);
-struct hisi_clock_data __init *hisi_clk_init(struct device_node *, int);
-void __init hisi_clk_register_fixed_rate(struct hisi_fixed_rate_clock *,
+struct hisi_clock_data *hisi_clk_init(struct device_node *, int);
+void hisi_clk_register_fixed_rate(struct hisi_fixed_rate_clock *,
int, struct hisi_clock_data *);
-void __init hisi_clk_register_fixed_factor(struct hisi_fixed_factor_clock *,
+void hisi_clk_register_fixed_factor(struct hisi_fixed_factor_clock *,
int, struct hisi_clock_data *);
-void __init hisi_clk_register_mux(struct hisi_mux_clock *, int,
+void hisi_clk_register_mux(struct hisi_mux_clock *, int,
struct hisi_clock_data *);
-void __init hisi_clk_register_divider(struct hisi_divider_clock *,
+void hisi_clk_register_divider(struct hisi_divider_clock *,
int, struct hisi_clock_data *);
-void __init hisi_clk_register_gate(struct hisi_gate_clock *,
+void hisi_clk_register_gate(struct hisi_gate_clock *,
+ int, struct hisi_clock_data *);
+void hisi_clk_register_gate_sep(struct hisi_gate_clock *,
int, struct hisi_clock_data *);
-void __init hisi_clk_register_gate_sep(struct hisi_gate_clock *,
+void hi6220_clk_register_divider(struct hi6220_divider_clock *,
int, struct hisi_clock_data *);
Please don't do the mass __init removal in this patch. Do it in a
separate patch.
#endif/* __HISI_CLK_H */
diff --git a/drivers/clk/hisilicon/clkdivider-hi6220.c
b/drivers/clk/hisilicon/clkdivider-hi6220.c
new file mode 100644
index 000..bc85ef6
--- /dev/null
+++ b/drivers/clk/hisilicon/clkdivider-hi6220.c
@@ -0,0 +1,157 @@
+/*
+ * Hisilicon hi6220 SoC divider clock driver
+ *
+ * Copyright (c) 2015 Hisilicon Limited.
+ *
+ * Author: Bintian Wang bintian.w...@huawei.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include linux/kernel.h
+#include linux/clk-provider.h
+#include linux/slab.h
+#include linux/io.h
+#include linux/err.h
#include linux/spinlock.h ?
+
+#define div_mask(width)((1 (width)) - 1)
+
[..]
+
+struct clk *hi6220_register_clkdiv(struct device *dev, const char *name,
+ const char *parent_name, unsigned long flags, void __iomem *reg,
+ u8 shift, u8 width, u32 mask_bit, spinlock_t *lock)
+{
+ struct hi6220_clk_divider *div;
+ struct clk *clk;
+ struct clk_init_data init;
+ struct clk_div_table *table;
+ u32 max_div, min_div;
+ int i;
+
+ /* allocate the divider */
+ div = kzalloc(sizeof(struct hi6220_clk_divider), GFP_KERNEL);
nitpick: Use sizeof(*div) please.
+ if (!div)
+ return ERR_PTR(-ENOMEM);
+
+ /* Init the divider table */
+ max_div = div_mask(width) + 1;
+ min_div = 1;
+
+ table = kzalloc(sizeof(struct clk_div_table) * (max_div + 1),
And kcalloc() here please
+ GFP_KERNEL);
+ if (!table) {
+ kfree(div);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ for (i = 0; i max_div; i++) {
+ table[i].div = min_div + i;
+ table[i].val = table[i].div - 1;
+ }
+
+ init.name = name;
+ init.ops = hi6220_clkdiv_ops;
+ init.flags = flags;
+ init.parent_names = parent_name ? parent_name : NULL;
+ init.num_parents = parent_name ? 1 : 0;
+
+ /* struct hi6220_clk_divider assignments */
+ div-reg = reg;
+ div-shift = shift;
+ div-width = width;
+ div-mask = mask_bit ? BIT(mask_bit) : 0;
+ div-lock = lock;
+ div-hw.init = init;
+ div-table = table;
+
+ /* register the clock */
+ clk = clk_register(dev, div-hw);
+
Drop the newline here.
+ if (IS_ERR(clk)) {
+ kfree(table);
+ kfree(div);
+ }
+
+ return clk;
+}
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ
[PATCH v7 6/7] clk: hi6220: Clock driver support for Hisilicon hi6220 SoC
Add clock drivers for hi6220 SoC, this driver controls the SoC
registers to supply different clocks to different IPs in the SoC.
We add one divider clock for hi6220 because the divider in hi6220
also has a mask bit but it doesnot obey the rule defined by flag
CLK_DIVIDER_HIWORD_MASK, we can not get index of the mask bit by
left shift fixed bits (e.g. 16 bits), so we add this divider clock
to handle it.
Signed-off-by: Jorge Ramirez-Ortiz jorge.ramirez-or...@linaro.org
Signed-off-by: Bintian Wang bintian.w...@huawei.com
Acked-by: Haojian Zhuang haojian.zhu...@linaro.org
Reviewed-by: Zhangfei Gao zhangfei@linaro.org
Tested-by: Will Deacon will.dea...@arm.com
Tested-by: Tyler Baker tyler.ba...@linaro.org
---
drivers/clk/Kconfig |2 +
drivers/clk/Makefile |4 +-
drivers/clk/hisilicon/Kconfig |6 +
drivers/clk/hisilicon/Makefile|3 +-
drivers/clk/hisilicon/clk-hi6220.c| 291 +
drivers/clk/hisilicon/clk.c | 29 +++
drivers/clk/hisilicon/clk.h | 17 ++
drivers/clk/hisilicon/clkdivider-hi6220.c | 156
include/dt-bindings/clock/hi6220-clock.h | 173 +
9 files changed, 677 insertions(+), 4 deletions(-)
create mode 100644 drivers/clk/hisilicon/Kconfig
create mode 100644 drivers/clk/hisilicon/clk-hi6220.c
create mode 100644 drivers/clk/hisilicon/clkdivider-hi6220.c
create mode 100644 include/dt-bindings/clock/hi6220-clock.h
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 9897f35..18bb930 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -150,6 +150,8 @@ config COMMON_CLK_CDCE706
---help---
This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
+source drivers/clk/hisilicon/Kconfig
+
source drivers/clk/qcom/Kconfig
endmenu
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 3d00c25..9719954 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -47,9 +47,7 @@ obj-$(CONFIG_COMMON_CLK_PWM) += clk-pwm.o
obj-$(CONFIG_COMMON_CLK_AT91) += at91/
obj-$(CONFIG_ARCH_BCM_MOBILE) += bcm/
obj-$(CONFIG_ARCH_BERLIN) += berlin/
-obj-$(CONFIG_ARCH_HI3xxx) += hisilicon/
-obj-$(CONFIG_ARCH_HIP04) += hisilicon/
-obj-$(CONFIG_ARCH_HIX5HD2) += hisilicon/
+obj-$(CONFIG_ARCH_HISI)+= hisilicon/
obj-$(CONFIG_COMMON_CLK_KEYSTONE) += keystone/
ifeq ($(CONFIG_COMMON_CLK), y)
obj-$(CONFIG_ARCH_MMP) += mmp/
diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
new file mode 100644
index 000..b4165ba
--- /dev/null
+++ b/drivers/clk/hisilicon/Kconfig
@@ -0,0 +1,6 @@
+config COMMON_CLK_HI6220
+ bool Hi6220 Clock Driver
+ depends on ARCH_HISI || COMPILE_TEST
+ default ARCH_HISI
+ help
+ Build the Hisilicon Hi6220 clock driver based on the common clock
framework.
diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile
index 038c02f..48f0116 100644
--- a/drivers/clk/hisilicon/Makefile
+++ b/drivers/clk/hisilicon/Makefile
@@ -2,8 +2,9 @@
# Hisilicon Clock specific Makefile
#
-obj-y += clk.o clkgate-separated.o
+obj-y += clk.o clkgate-separated.o clkdivider-hi6220.o
obj-$(CONFIG_ARCH_HI3xxx) += clk-hi3620.o
obj-$(CONFIG_ARCH_HIP04) += clk-hip04.o
obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o
+obj-$(CONFIG_COMMON_CLK_HI6220)+= clk-hi6220.o
diff --git a/drivers/clk/hisilicon/clk-hi6220.c
b/drivers/clk/hisilicon/clk-hi6220.c
new file mode 100644
index 000..438326f
--- /dev/null
+++ b/drivers/clk/hisilicon/clk-hi6220.c
@@ -0,0 +1,291 @@
+/*
+ * Hisilicon Hi6220 clock driver
+ *
+ * Copyright (c) 2015 Hisilicon Limited.
+ *
+ * Author: Bintian Wang bintian.w...@huawei.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/kernel.h
+#include linux/clk-provider.h
+#include linux/clkdev.h
+#include linux/io.h
+#include linux/of.h
+#include linux/of_address.h
+#include linux/of_device.h
+#include linux/slab.h
+
+#include dt-bindings/clock/hi6220-clock.h
+
+#include clk.h
+
+
+/* clocks in AO (always on) controller */
+static struct hisi_fixed_rate_clock hi6220_fixed_rate_clks[] __initdata = {
+ { HI6220_REF32K,ref32k, NULL, CLK_IS_ROOT, 32764, },
+ { HI6220_CLK_TCXO, clk_tcxo, NULL, CLK_IS_ROOT, 1920, },
+ { HI6220_MMC1_PAD, mmc1_pad, NULL, CLK_IS_ROOT, 1, },
+ { HI6220_MMC2_PAD, mmc2_pad, NULL, CLK_IS_ROOT, 1, },
+ { HI6220_MMC0_PAD, mmc0_pad, NULL, CLK_IS_ROOT, 2, },
+ { HI6220_PLL_BBP, bbppll0, NULL, CLK_IS_ROOT, 24576, },
+ { HI6220_PLL_GPU
[PATCH v7 5/7] clk: hisilicon: Remove __init for marking function prototypes
__init markings on function prototypes are useless, so remove them. Suggested-by: Stephen Boyd sb...@codeaurora.org Signed-off-by: Bintian Wang bintian.w...@huawei.com --- drivers/clk/hisilicon/clk.h | 22 +++--- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/clk/hisilicon/clk.h b/drivers/clk/hisilicon/clk.h index 31083ff..6b6f994 100644 --- a/drivers/clk/hisilicon/clk.h +++ b/drivers/clk/hisilicon/clk.h @@ -95,17 +95,17 @@ struct clk *hisi_register_clkgate_sep(struct device *, const char *, void __iomem *, u8, u8, spinlock_t *); -struct hisi_clock_data __init *hisi_clk_init(struct device_node *, int); -void __init hisi_clk_register_fixed_rate(struct hisi_fixed_rate_clock *, - int, struct hisi_clock_data *); -void __init hisi_clk_register_fixed_factor(struct hisi_fixed_factor_clock *, - int, struct hisi_clock_data *); -void __init hisi_clk_register_mux(struct hisi_mux_clock *, int, +struct hisi_clock_data *hisi_clk_init(struct device_node *, int); +void hisi_clk_register_fixed_rate(struct hisi_fixed_rate_clock *, + int, struct hisi_clock_data *); +void hisi_clk_register_fixed_factor(struct hisi_fixed_factor_clock *, + int, struct hisi_clock_data *); +void hisi_clk_register_mux(struct hisi_mux_clock *, int, struct hisi_clock_data *); -void __init hisi_clk_register_divider(struct hisi_divider_clock *, +void hisi_clk_register_divider(struct hisi_divider_clock *, + int, struct hisi_clock_data *); +void hisi_clk_register_gate(struct hisi_gate_clock *, + int, struct hisi_clock_data *); +void hisi_clk_register_gate_sep(struct hisi_gate_clock *, int, struct hisi_clock_data *); -void __init hisi_clk_register_gate(struct hisi_gate_clock *, - int, struct hisi_clock_data *); -void __init hisi_clk_register_gate_sep(struct hisi_gate_clock *, - int, struct hisi_clock_data *); #endif /* __HISI_CLK_H */ -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v7 6/7] clk: hi6220: Clock driver support for Hisilicon hi6220 SoC
Hello Stephen, Arnd,
On 2015/5/21 6:25, Stephen Boyd wrote:
On 05/20/15 03:29, Bintian Wang wrote:
Add clock drivers for hi6220 SoC, this driver controls the SoC
registers to supply different clocks to different IPs in the SoC.
We add one divider clock for hi6220 because the divider in hi6220
also has a mask bit but it doesnot obey the rule defined by flag
CLK_DIVIDER_HIWORD_MASK, we can not get index of the mask bit by
left shift fixed bits (e.g. 16 bits), so we add this divider clock
to handle it.
Signed-off-by: Jorge Ramirez-Ortiz jorge.ramirez-or...@linaro.org
Signed-off-by: Bintian Wang bintian.w...@huawei.com
Acked-by: Haojian Zhuang haojian.zhu...@linaro.org
Reviewed-by: Zhangfei Gao zhangfei@linaro.org
Tested-by: Will Deacon will.dea...@arm.com
Tested-by: Tyler Baker tyler.ba...@linaro.org
---
drivers/clk/Kconfig |2 +
drivers/clk/Makefile |4 +-
drivers/clk/hisilicon/Kconfig |6 +
drivers/clk/hisilicon/Makefile|3 +-
drivers/clk/hisilicon/clk-hi6220.c| 291 +
drivers/clk/hisilicon/clk.c | 29 +++
drivers/clk/hisilicon/clk.h | 17 ++
drivers/clk/hisilicon/clkdivider-hi6220.c | 156
include/dt-bindings/clock/hi6220-clock.h | 173 +
9 files changed, 677 insertions(+), 4 deletions(-)
create mode 100644 drivers/clk/hisilicon/Kconfig
create mode 100644 drivers/clk/hisilicon/clk-hi6220.c
create mode 100644 drivers/clk/hisilicon/clkdivider-hi6220.c
create mode 100644 include/dt-bindings/clock/hi6220-clock.h
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 9897f35..18bb930 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -150,6 +150,8 @@ config COMMON_CLK_CDCE706
---help---
This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
+source drivers/clk/hisilicon/Kconfig
+
source drivers/clk/qcom/Kconfig
There's going to be a merge conflict here if this doesn't go through the
clk tree.
Hello Arnd, how about the clk driver of hi6220 goes through the clk
tree and those dts and arch patches go through arm-soc?
If there is no problem, I will split the clock header file to a
single patch for your convenience.
+
+static void __init hi6220_clk_sys_init(struct device_node *np)
+{
+ struct hisi_clock_data *clk_data;
+
+ clk_data = hisi_clk_init(np, HI6220_SYS_NR_CLKS);
+ if (!clk_data)
+ return;
+
+ hisi_clk_register_gate_sep(hi6220_separated_gate_clks_sys,
+ ARRAY_SIZE(hi6220_separated_gate_clks_sys), clk_data);
+
+ hisi_clk_register_mux(hi6220_mux_clks_sys,
+ ARRAY_SIZE(hi6220_mux_clks_sys), clk_data);
+
+ hi6220_clk_register_divider(hi6220_div_clks_sys,
+ ARRAY_SIZE(hi6220_div_clks_sys), clk_data);
+
+ if (!clk_data_ao)
+ return;
+
+ /* enable high speed clock on UART1 mux */
+ clk_set_parent(clk_data-clk_data.clks[HI6220_UART1_SRC],
+ clk_data_ao-clk_data.clks[HI6220_150M]);
Sorry I missed this one earlier. Can we do this clk_set_parent() through
assigned-parents instead?
Uart1 has two clock parents in hi6220, and use clk_tcxo by default,
we use uart1 to connect BT in HiKey, and switch to clk_150m for high
speed mode of BT, but pl011 has no code to set clock rate or set clock
parents operation, so it's a easy way to do that here.
I expected an #include linux/clk.h for the
usage of clk_set_parent() here so I didn't look hard to see if consumer
APIs were being used.
OK, I will add in next version 8.
Thanks,
Bintian
Otherwise the patch looks fine.
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v4 4/5] clk: hi6220: Clock driver support for Hisilicon hi6220 SoC
Hello Stephen, On 2015/5/20 4:35, Stephen Boyd wrote: On 05/15/15 19:54, Brent Wang wrote: How about just send this patch for review not the whole patch set in next version? Yes a single patch is fine. I take it you want the patch to go through arm-soc with some Ack from us? Yes, exactly. The dts file includes the clock head file, this patch goes through arm-soc is a good choice. One way to avoid that problem is to split the clock header file into its own patch and then duplicate that patch in two trees, one that goes through arm-soc and one that goes through clk. Thanks for your suggestion, I will talk about this with Hisilicon SoC maintainer XuWei. I have updated this patch based on your suggestion, could you help review patch "[PATCH v6 5/6] clk: hi6220: Clock driver support for Hisilicon hi6220 SoC"? Thanks, Bintian -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v6 5/6] clk: hi6220: Clock driver support for Hisilicon hi6220 SoC
Hello Mike, Stephen,
I updated this patch based on Stephen's suggestion, could you spend
several minutes to help review?
If there is no problem, please help to ack.
Thanks,
Bintian
On 2015/5/16 15:40, Bintian Wang wrote:
Add clock drivers for hi6220 SoC, this driver controls the SoC
registers to supply different clocks to different IPs in the SoC.
We add one divider clock for hi6220 because the divider in hi6220
also has a mask bit but it doesnot obey the rule defined by flag
"CLK_DIVIDER_HIWORD_MASK", we can not get index of the mask bit by
left shift fixed bits (e.g. 16 bits), so we add this divider clock
to handle it.
Signed-off-by: Jorge Ramirez-Ortiz
Signed-off-by: Bintian Wang
Acked-by: Haojian Zhuang
Reviewed-by: Zhangfei Gao
Tested-by: Will Deacon
Tested-by: Tyler Baker
---
drivers/clk/Kconfig | 2 +
drivers/clk/Makefile | 4 +-
drivers/clk/hisilicon/Kconfig | 6 +
drivers/clk/hisilicon/Makefile| 3 +-
drivers/clk/hisilicon/clk-hi6220.c| 291 ++
drivers/clk/hisilicon/clk.c | 29 +++
drivers/clk/hisilicon/clk.h | 31 +++-
drivers/clk/hisilicon/clkdivider-hi6220.c | 157
include/dt-bindings/clock/hi6220-clock.h | 173 ++
9 files changed, 685 insertions(+), 11 deletions(-)
create mode 100644 drivers/clk/hisilicon/Kconfig
create mode 100644 drivers/clk/hisilicon/clk-hi6220.c
create mode 100644 drivers/clk/hisilicon/clkdivider-hi6220.c
create mode 100644 include/dt-bindings/clock/hi6220-clock.h
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 9897f35..18bb930 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -150,6 +150,8 @@ config COMMON_CLK_CDCE706
---help---
This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
+source "drivers/clk/hisilicon/Kconfig"
+
source "drivers/clk/qcom/Kconfig"
endmenu
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 3d00c25..9719954 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -47,9 +47,7 @@ obj-$(CONFIG_COMMON_CLK_PWM) += clk-pwm.o
obj-$(CONFIG_COMMON_CLK_AT91) += at91/
obj-$(CONFIG_ARCH_BCM_MOBILE) += bcm/
obj-$(CONFIG_ARCH_BERLIN) += berlin/
-obj-$(CONFIG_ARCH_HI3xxx) += hisilicon/
-obj-$(CONFIG_ARCH_HIP04) += hisilicon/
-obj-$(CONFIG_ARCH_HIX5HD2) += hisilicon/
+obj-$(CONFIG_ARCH_HISI)+= hisilicon/
obj-$(CONFIG_COMMON_CLK_KEYSTONE) += keystone/
ifeq ($(CONFIG_COMMON_CLK), y)
obj-$(CONFIG_ARCH_MMP)+= mmp/
diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
new file mode 100644
index 000..b4165ba
--- /dev/null
+++ b/drivers/clk/hisilicon/Kconfig
@@ -0,0 +1,6 @@
+config COMMON_CLK_HI6220
+ bool "Hi6220 Clock Driver"
+ depends on ARCH_HISI || COMPILE_TEST
+ default ARCH_HISI
+ help
+ Build the Hisilicon Hi6220 clock driver based on the common clock
framework.
diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile
index 038c02f..48f0116 100644
--- a/drivers/clk/hisilicon/Makefile
+++ b/drivers/clk/hisilicon/Makefile
@@ -2,8 +2,9 @@
# Hisilicon Clock specific Makefile
#
-obj-y += clk.o clkgate-separated.o
+obj-y += clk.o clkgate-separated.o clkdivider-hi6220.o
obj-$(CONFIG_ARCH_HI3xxx) += clk-hi3620.o
obj-$(CONFIG_ARCH_HIP04) += clk-hip04.o
obj-$(CONFIG_ARCH_HIX5HD2)+= clk-hix5hd2.o
+obj-$(CONFIG_COMMON_CLK_HI6220)+= clk-hi6220.o
diff --git a/drivers/clk/hisilicon/clk-hi6220.c
b/drivers/clk/hisilicon/clk-hi6220.c
new file mode 100644
index 000..438326f
--- /dev/null
+++ b/drivers/clk/hisilicon/clk-hi6220.c
@@ -0,0 +1,291 @@
+/*
+ * Hisilicon Hi6220 clock driver
+ *
+ * Copyright (c) 2015 Hisilicon Limited.
+ *
+ * Author: Bintian Wang
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include "clk.h"
+
+
+/* clocks in AO (always on) controller */
+static struct hisi_fixed_rate_clock hi6220_fixed_rate_clks[] __initdata = {
+ { HI6220_REF32K,"ref32k", NULL, CLK_IS_ROOT, 32764, },
+ { HI6220_CLK_TCXO, "clk_tcxo", NULL, CLK_IS_ROOT, 1920, },
+ { HI6220_MMC1_PAD, "mmc1_pad", NULL, CLK_IS_ROOT, 1, },
+ { HI6220_MMC2_PAD, "mmc2_pad", NULL, CLK_IS_ROOT, 1, },
+ { HI6220_MMC0_PAD, "mmc0_pad", NULL, CLK_IS_ROOT, 2, },
+ { HI6220_PLL_BBP, "bbppll0",
Re: [PATCH v4 4/5] clk: hi6220: Clock driver support for Hisilicon hi6220 SoC
Hello Stephen, On 2015/5/20 4:35, Stephen Boyd wrote: On 05/15/15 19:54, Brent Wang wrote: How about just send this patch for review not the whole patch set in next version? Yes a single patch is fine. I take it you want the patch to go through arm-soc with some Ack from us? Yes, exactly. The dts file includes the clock head file, this patch goes through arm-soc is a good choice. One way to avoid that problem is to split the clock header file into its own patch and then duplicate that patch in two trees, one that goes through arm-soc and one that goes through clk. Thanks for your suggestion, I will talk about this with Hisilicon SoC maintainer XuWei. I have updated this patch based on your suggestion, could you help review patch [PATCH v6 5/6] clk: hi6220: Clock driver support for Hisilicon hi6220 SoC? Thanks, Bintian -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v6 5/6] clk: hi6220: Clock driver support for Hisilicon hi6220 SoC
Hello Mike, Stephen,
I updated this patch based on Stephen's suggestion, could you spend
several minutes to help review?
If there is no problem, please help to ack.
Thanks,
Bintian
On 2015/5/16 15:40, Bintian Wang wrote:
Add clock drivers for hi6220 SoC, this driver controls the SoC
registers to supply different clocks to different IPs in the SoC.
We add one divider clock for hi6220 because the divider in hi6220
also has a mask bit but it doesnot obey the rule defined by flag
CLK_DIVIDER_HIWORD_MASK, we can not get index of the mask bit by
left shift fixed bits (e.g. 16 bits), so we add this divider clock
to handle it.
Signed-off-by: Jorge Ramirez-Ortiz jorge.ramirez-or...@linaro.org
Signed-off-by: Bintian Wang bintian.w...@huawei.com
Acked-by: Haojian Zhuang haojian.zhu...@linaro.org
Reviewed-by: Zhangfei Gao zhangfei@linaro.org
Tested-by: Will Deacon will.dea...@arm.com
Tested-by: Tyler Baker tyler.ba...@linaro.org
---
drivers/clk/Kconfig | 2 +
drivers/clk/Makefile | 4 +-
drivers/clk/hisilicon/Kconfig | 6 +
drivers/clk/hisilicon/Makefile| 3 +-
drivers/clk/hisilicon/clk-hi6220.c| 291 ++
drivers/clk/hisilicon/clk.c | 29 +++
drivers/clk/hisilicon/clk.h | 31 +++-
drivers/clk/hisilicon/clkdivider-hi6220.c | 157
include/dt-bindings/clock/hi6220-clock.h | 173 ++
9 files changed, 685 insertions(+), 11 deletions(-)
create mode 100644 drivers/clk/hisilicon/Kconfig
create mode 100644 drivers/clk/hisilicon/clk-hi6220.c
create mode 100644 drivers/clk/hisilicon/clkdivider-hi6220.c
create mode 100644 include/dt-bindings/clock/hi6220-clock.h
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 9897f35..18bb930 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -150,6 +150,8 @@ config COMMON_CLK_CDCE706
---help---
This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
+source drivers/clk/hisilicon/Kconfig
+
source drivers/clk/qcom/Kconfig
endmenu
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 3d00c25..9719954 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -47,9 +47,7 @@ obj-$(CONFIG_COMMON_CLK_PWM) += clk-pwm.o
obj-$(CONFIG_COMMON_CLK_AT91) += at91/
obj-$(CONFIG_ARCH_BCM_MOBILE) += bcm/
obj-$(CONFIG_ARCH_BERLIN) += berlin/
-obj-$(CONFIG_ARCH_HI3xxx) += hisilicon/
-obj-$(CONFIG_ARCH_HIP04) += hisilicon/
-obj-$(CONFIG_ARCH_HIX5HD2) += hisilicon/
+obj-$(CONFIG_ARCH_HISI)+= hisilicon/
obj-$(CONFIG_COMMON_CLK_KEYSTONE) += keystone/
ifeq ($(CONFIG_COMMON_CLK), y)
obj-$(CONFIG_ARCH_MMP)+= mmp/
diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
new file mode 100644
index 000..b4165ba
--- /dev/null
+++ b/drivers/clk/hisilicon/Kconfig
@@ -0,0 +1,6 @@
+config COMMON_CLK_HI6220
+ bool Hi6220 Clock Driver
+ depends on ARCH_HISI || COMPILE_TEST
+ default ARCH_HISI
+ help
+ Build the Hisilicon Hi6220 clock driver based on the common clock
framework.
diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile
index 038c02f..48f0116 100644
--- a/drivers/clk/hisilicon/Makefile
+++ b/drivers/clk/hisilicon/Makefile
@@ -2,8 +2,9 @@
# Hisilicon Clock specific Makefile
#
-obj-y += clk.o clkgate-separated.o
+obj-y += clk.o clkgate-separated.o clkdivider-hi6220.o
obj-$(CONFIG_ARCH_HI3xxx) += clk-hi3620.o
obj-$(CONFIG_ARCH_HIP04) += clk-hip04.o
obj-$(CONFIG_ARCH_HIX5HD2)+= clk-hix5hd2.o
+obj-$(CONFIG_COMMON_CLK_HI6220)+= clk-hi6220.o
diff --git a/drivers/clk/hisilicon/clk-hi6220.c
b/drivers/clk/hisilicon/clk-hi6220.c
new file mode 100644
index 000..438326f
--- /dev/null
+++ b/drivers/clk/hisilicon/clk-hi6220.c
@@ -0,0 +1,291 @@
+/*
+ * Hisilicon Hi6220 clock driver
+ *
+ * Copyright (c) 2015 Hisilicon Limited.
+ *
+ * Author: Bintian Wang bintian.w...@huawei.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/kernel.h
+#include linux/clk-provider.h
+#include linux/clkdev.h
+#include linux/io.h
+#include linux/of.h
+#include linux/of_address.h
+#include linux/of_device.h
+#include linux/slab.h
+
+#include dt-bindings/clock/hi6220-clock.h
+
+#include clk.h
+
+
+/* clocks in AO (always on) controller */
+static struct hisi_fixed_rate_clock hi6220_fixed_rate_clks[] __initdata = {
+ { HI6220_REF32K,ref32k, NULL, CLK_IS_ROOT, 32764, },
+ { HI6220_CLK_TCXO, clk_tcxo, NULL, CLK_IS_ROOT, 1920, },
+ { HI6220_MMC1_PAD, mmc1_pad, NULL, CLK_IS_ROOT, 1
[PATCH v6 5/6] clk: hi6220: Clock driver support for Hisilicon hi6220 SoC
Add clock drivers for hi6220 SoC, this driver controls the SoC
registers to supply different clocks to different IPs in the SoC.
We add one divider clock for hi6220 because the divider in hi6220
also has a mask bit but it doesnot obey the rule defined by flag
"CLK_DIVIDER_HIWORD_MASK", we can not get index of the mask bit by
left shift fixed bits (e.g. 16 bits), so we add this divider clock
to handle it.
Signed-off-by: Jorge Ramirez-Ortiz
Signed-off-by: Bintian Wang
Acked-by: Haojian Zhuang
Reviewed-by: Zhangfei Gao
Tested-by: Will Deacon
Tested-by: Tyler Baker
---
drivers/clk/Kconfig | 2 +
drivers/clk/Makefile | 4 +-
drivers/clk/hisilicon/Kconfig | 6 +
drivers/clk/hisilicon/Makefile| 3 +-
drivers/clk/hisilicon/clk-hi6220.c| 291 ++
drivers/clk/hisilicon/clk.c | 29 +++
drivers/clk/hisilicon/clk.h | 31 +++-
drivers/clk/hisilicon/clkdivider-hi6220.c | 157
include/dt-bindings/clock/hi6220-clock.h | 173 ++
9 files changed, 685 insertions(+), 11 deletions(-)
create mode 100644 drivers/clk/hisilicon/Kconfig
create mode 100644 drivers/clk/hisilicon/clk-hi6220.c
create mode 100644 drivers/clk/hisilicon/clkdivider-hi6220.c
create mode 100644 include/dt-bindings/clock/hi6220-clock.h
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 9897f35..18bb930 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -150,6 +150,8 @@ config COMMON_CLK_CDCE706
---help---
This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
+source "drivers/clk/hisilicon/Kconfig"
+
source "drivers/clk/qcom/Kconfig"
endmenu
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 3d00c25..9719954 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -47,9 +47,7 @@ obj-$(CONFIG_COMMON_CLK_PWM) += clk-pwm.o
obj-$(CONFIG_COMMON_CLK_AT91) += at91/
obj-$(CONFIG_ARCH_BCM_MOBILE) += bcm/
obj-$(CONFIG_ARCH_BERLIN) += berlin/
-obj-$(CONFIG_ARCH_HI3xxx) += hisilicon/
-obj-$(CONFIG_ARCH_HIP04) += hisilicon/
-obj-$(CONFIG_ARCH_HIX5HD2) += hisilicon/
+obj-$(CONFIG_ARCH_HISI)+= hisilicon/
obj-$(CONFIG_COMMON_CLK_KEYSTONE) += keystone/
ifeq ($(CONFIG_COMMON_CLK), y)
obj-$(CONFIG_ARCH_MMP) += mmp/
diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
new file mode 100644
index 000..b4165ba
--- /dev/null
+++ b/drivers/clk/hisilicon/Kconfig
@@ -0,0 +1,6 @@
+config COMMON_CLK_HI6220
+ bool "Hi6220 Clock Driver"
+ depends on ARCH_HISI || COMPILE_TEST
+ default ARCH_HISI
+ help
+ Build the Hisilicon Hi6220 clock driver based on the common clock
framework.
diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile
index 038c02f..48f0116 100644
--- a/drivers/clk/hisilicon/Makefile
+++ b/drivers/clk/hisilicon/Makefile
@@ -2,8 +2,9 @@
# Hisilicon Clock specific Makefile
#
-obj-y += clk.o clkgate-separated.o
+obj-y += clk.o clkgate-separated.o clkdivider-hi6220.o
obj-$(CONFIG_ARCH_HI3xxx) += clk-hi3620.o
obj-$(CONFIG_ARCH_HIP04) += clk-hip04.o
obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o
+obj-$(CONFIG_COMMON_CLK_HI6220)+= clk-hi6220.o
diff --git a/drivers/clk/hisilicon/clk-hi6220.c
b/drivers/clk/hisilicon/clk-hi6220.c
new file mode 100644
index 000..438326f
--- /dev/null
+++ b/drivers/clk/hisilicon/clk-hi6220.c
@@ -0,0 +1,291 @@
+/*
+ * Hisilicon Hi6220 clock driver
+ *
+ * Copyright (c) 2015 Hisilicon Limited.
+ *
+ * Author: Bintian Wang
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include "clk.h"
+
+
+/* clocks in AO (always on) controller */
+static struct hisi_fixed_rate_clock hi6220_fixed_rate_clks[] __initdata = {
+ { HI6220_REF32K,"ref32k", NULL, CLK_IS_ROOT, 32764, },
+ { HI6220_CLK_TCXO, "clk_tcxo", NULL, CLK_IS_ROOT, 1920, },
+ { HI6220_MMC1_PAD, "mmc1_pad", NULL, CLK_IS_ROOT, 1, },
+ { HI6220_MMC2_PAD, "mmc2_pad", NULL, CLK_IS_ROOT, 1, },
+ { HI6220_MMC0_PAD, "mmc0_pad", NULL, CLK_IS_ROOT, 2, },
+ { HI6220_PLL_BBP, "bbppll0", NULL, CLK_IS_ROOT, 24576, },
+ { HI6220_PLL_GPU, "gpupll", NULL, CLK_IS_ROOT, 10,},
+ { HI6220_PLL1_DDR, "ddrpll1", NULL, CLK_IS_ROOT, 106600,},
+ { HI6220_PLL_SYS,
[PATCH v6 5/6] clk: hi6220: Clock driver support for Hisilicon hi6220 SoC
Add clock drivers for hi6220 SoC, this driver controls the SoC
registers to supply different clocks to different IPs in the SoC.
We add one divider clock for hi6220 because the divider in hi6220
also has a mask bit but it doesnot obey the rule defined by flag
CLK_DIVIDER_HIWORD_MASK, we can not get index of the mask bit by
left shift fixed bits (e.g. 16 bits), so we add this divider clock
to handle it.
Signed-off-by: Jorge Ramirez-Ortiz jorge.ramirez-or...@linaro.org
Signed-off-by: Bintian Wang bintian.w...@huawei.com
Acked-by: Haojian Zhuang haojian.zhu...@linaro.org
Reviewed-by: Zhangfei Gao zhangfei@linaro.org
Tested-by: Will Deacon will.dea...@arm.com
Tested-by: Tyler Baker tyler.ba...@linaro.org
---
drivers/clk/Kconfig | 2 +
drivers/clk/Makefile | 4 +-
drivers/clk/hisilicon/Kconfig | 6 +
drivers/clk/hisilicon/Makefile| 3 +-
drivers/clk/hisilicon/clk-hi6220.c| 291 ++
drivers/clk/hisilicon/clk.c | 29 +++
drivers/clk/hisilicon/clk.h | 31 +++-
drivers/clk/hisilicon/clkdivider-hi6220.c | 157
include/dt-bindings/clock/hi6220-clock.h | 173 ++
9 files changed, 685 insertions(+), 11 deletions(-)
create mode 100644 drivers/clk/hisilicon/Kconfig
create mode 100644 drivers/clk/hisilicon/clk-hi6220.c
create mode 100644 drivers/clk/hisilicon/clkdivider-hi6220.c
create mode 100644 include/dt-bindings/clock/hi6220-clock.h
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 9897f35..18bb930 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -150,6 +150,8 @@ config COMMON_CLK_CDCE706
---help---
This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
+source drivers/clk/hisilicon/Kconfig
+
source drivers/clk/qcom/Kconfig
endmenu
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 3d00c25..9719954 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -47,9 +47,7 @@ obj-$(CONFIG_COMMON_CLK_PWM) += clk-pwm.o
obj-$(CONFIG_COMMON_CLK_AT91) += at91/
obj-$(CONFIG_ARCH_BCM_MOBILE) += bcm/
obj-$(CONFIG_ARCH_BERLIN) += berlin/
-obj-$(CONFIG_ARCH_HI3xxx) += hisilicon/
-obj-$(CONFIG_ARCH_HIP04) += hisilicon/
-obj-$(CONFIG_ARCH_HIX5HD2) += hisilicon/
+obj-$(CONFIG_ARCH_HISI)+= hisilicon/
obj-$(CONFIG_COMMON_CLK_KEYSTONE) += keystone/
ifeq ($(CONFIG_COMMON_CLK), y)
obj-$(CONFIG_ARCH_MMP) += mmp/
diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
new file mode 100644
index 000..b4165ba
--- /dev/null
+++ b/drivers/clk/hisilicon/Kconfig
@@ -0,0 +1,6 @@
+config COMMON_CLK_HI6220
+ bool Hi6220 Clock Driver
+ depends on ARCH_HISI || COMPILE_TEST
+ default ARCH_HISI
+ help
+ Build the Hisilicon Hi6220 clock driver based on the common clock
framework.
diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile
index 038c02f..48f0116 100644
--- a/drivers/clk/hisilicon/Makefile
+++ b/drivers/clk/hisilicon/Makefile
@@ -2,8 +2,9 @@
# Hisilicon Clock specific Makefile
#
-obj-y += clk.o clkgate-separated.o
+obj-y += clk.o clkgate-separated.o clkdivider-hi6220.o
obj-$(CONFIG_ARCH_HI3xxx) += clk-hi3620.o
obj-$(CONFIG_ARCH_HIP04) += clk-hip04.o
obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o
+obj-$(CONFIG_COMMON_CLK_HI6220)+= clk-hi6220.o
diff --git a/drivers/clk/hisilicon/clk-hi6220.c
b/drivers/clk/hisilicon/clk-hi6220.c
new file mode 100644
index 000..438326f
--- /dev/null
+++ b/drivers/clk/hisilicon/clk-hi6220.c
@@ -0,0 +1,291 @@
+/*
+ * Hisilicon Hi6220 clock driver
+ *
+ * Copyright (c) 2015 Hisilicon Limited.
+ *
+ * Author: Bintian Wang bintian.w...@huawei.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/kernel.h
+#include linux/clk-provider.h
+#include linux/clkdev.h
+#include linux/io.h
+#include linux/of.h
+#include linux/of_address.h
+#include linux/of_device.h
+#include linux/slab.h
+
+#include dt-bindings/clock/hi6220-clock.h
+
+#include clk.h
+
+
+/* clocks in AO (always on) controller */
+static struct hisi_fixed_rate_clock hi6220_fixed_rate_clks[] __initdata = {
+ { HI6220_REF32K,ref32k, NULL, CLK_IS_ROOT, 32764, },
+ { HI6220_CLK_TCXO, clk_tcxo, NULL, CLK_IS_ROOT, 1920, },
+ { HI6220_MMC1_PAD, mmc1_pad, NULL, CLK_IS_ROOT, 1, },
+ { HI6220_MMC2_PAD, mmc2_pad, NULL, CLK_IS_ROOT, 1, },
+ { HI6220_MMC0_PAD, mmc0_pad, NULL, CLK_IS_ROOT, 2, },
+ { HI6220_PLL_BBP, bbppll0, NULL, CLK_IS_ROOT, 24576, },
+ { HI6220_PLL_GPU
Re: [PATCH v4 4/5] clk: hi6220: Clock driver support for Hisilicon hi6220 SoC
Hello Stephen,
On 2015/5/15 8:25, Stephen Boyd wrote:
On 05/05, Bintian Wang wrote:
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 9897f35..935c44b 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -152,6 +152,8 @@ config COMMON_CLK_CDCE706
source "drivers/clk/qcom/Kconfig"
+source "drivers/clk/hisilicon/Kconfig"
+
Please move this above qcom to maintain alphabet sort.
OK, fix in next version.
endmenu
source "drivers/clk/bcm/Kconfig"
diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
new file mode 100644
index 000..8034739
--- /dev/null
+++ b/drivers/clk/hisilicon/Kconfig
@@ -0,0 +1,6 @@
+config COMMON_CLK_HI6220
+ bool "Hi6220 Clock Driver"
+ depends on OF && ARCH_HISI
+ default y
Can this be
depends on ARCH_HISI || COMPILE_TEST
default ARCH_HISI
instead? I'd like to increase build coverage.
No problem, will fix in next version.
+ help
+ Build the Hisilicon Hi6220 clock driver based on the common clock
framework.
diff --git a/drivers/clk/hisilicon/clk-hi6220.c
b/drivers/clk/hisilicon/clk-hi6220.c
new file mode 100644
index 000..91b1cd7
--- /dev/null
+++ b/drivers/clk/hisilicon/clk-hi6220.c
@@ -0,0 +1,292 @@
+/*
+ * Hisilicon Hi6220 clock driver
+ *
+ * Copyright (c) 2015 Hisilicon Limited.
+ *
+ * Author: Bintian Wang
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
Do we need to include linux/clk.h? I don't see any consumer
usage here.
You are right, remove in next version.
+
+#include
+
+#include "clk.h"
+
diff --git a/drivers/clk/hisilicon/clk.c b/drivers/clk/hisilicon/clk.c
index a078e84..5d2305c 100644
--- a/drivers/clk/hisilicon/clk.c
+++ b/drivers/clk/hisilicon/clk.c
@@ -108,4 +123,6 @@ void __init hisi_clk_register_gate(struct hisi_gate_clock *,
int, struct hisi_clock_data *);
void __init hisi_clk_register_gate_sep(struct hisi_gate_clock *,
int, struct hisi_clock_data *);
+void __init hi6220_clk_register_divider(struct hi6220_divider_clock *,
+ int, struct hisi_clock_data *);
__init markings on function prototypes are useless. Please remove them.
OK
#endif/* __HISI_CLK_H */
diff --git a/drivers/clk/hisilicon/clkdivider-hi6220.c
b/drivers/clk/hisilicon/clkdivider-hi6220.c
+
+/**
+ * struct hi6220_clk_divider - divider clock for hi6220
+ *
+ * @hw:handle between common and hardware-specific interfaces
+ * @reg: register containing divider
+ * @shift: shift to the divider bit field
+ * @width: width of the divider bit field
+ * @mask: mask for setting divider rate
+ * @table: the div table that the divider supports
+ * @lock: register lock
+ */
+struct hi6220_clk_divider {
+ struct clk_hw hw;
+ void __iomem*reg;
+ u8 shift;
+ u8 width;
+ u32 mask;
+ const struct clk_div_table *table;
+ spinlock_t *lock;
+};
The clk-divider.c code has been made "reusable". Can you please
try to use the functions that it now exposes instead of
copy/pasting it and modifying it to suit your needs? A lot of
this code looks the same.
In fact, I discussed this problem with Rob Herring and Mike Turquette
in the 96boards internal mail list before.
The divider in hi6220 has a mask bit to guarantee writing the correct
bits in register when setting rate, but the index of this mask bit has
no rules to get (e.g. by left shift some fixed bits), so I add this
divider clock to handle it, we can regard hi6220_clk_divider as a
special case of generic divider clock.
If I don't add this divider clock for hi6220 chip, then I should change
the core APIs "clk_register_divider" and "clk_register_divider_table",
and then many other drivers will be updated.
So I think just add this divider clock is a good solution now.
+
+#define to_hi6220_clk_divider(_hw) \
[..]
+
+static struct clk_ops hi6220_clkdiv_ops = {
const?
Add in next version.
+ .recalc_rate = hi6220_clkdiv_recalc_rate,
+ .round_rate = hi6220_clkdiv_round_rate,
+ .set_rate = hi6220_clkdiv_set_rate,
+};
+
+struct clk *hi6220_register_clkdiv(struct device *dev, const char *name,
+ const char *parent_name, unsigned long flags, void __iomem *reg,
+ u8 shift, u8 width, u32 mask_bit, spinlock_t *lock)
+{
+ struct hi6220_clk_divider *div;
+ struct clk *clk;
+ struct clk_init_data init;
+ struct clk_div_table *table;
+ u32 max_div, min_div;
+ int i;
+
+
Re: [PATCH v4 4/5] clk: hi6220: Clock driver support for Hisilicon hi6220 SoC
Hello Stephen,
On 2015/5/15 8:25, Stephen Boyd wrote:
On 05/05, Bintian Wang wrote:
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 9897f35..935c44b 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -152,6 +152,8 @@ config COMMON_CLK_CDCE706
source drivers/clk/qcom/Kconfig
+source drivers/clk/hisilicon/Kconfig
+
Please move this above qcom to maintain alphabet sort.
OK, fix in next version.
endmenu
source drivers/clk/bcm/Kconfig
diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
new file mode 100644
index 000..8034739
--- /dev/null
+++ b/drivers/clk/hisilicon/Kconfig
@@ -0,0 +1,6 @@
+config COMMON_CLK_HI6220
+ bool Hi6220 Clock Driver
+ depends on OF ARCH_HISI
+ default y
Can this be
depends on ARCH_HISI || COMPILE_TEST
default ARCH_HISI
instead? I'd like to increase build coverage.
No problem, will fix in next version.
+ help
+ Build the Hisilicon Hi6220 clock driver based on the common clock
framework.
diff --git a/drivers/clk/hisilicon/clk-hi6220.c
b/drivers/clk/hisilicon/clk-hi6220.c
new file mode 100644
index 000..91b1cd7
--- /dev/null
+++ b/drivers/clk/hisilicon/clk-hi6220.c
@@ -0,0 +1,292 @@
+/*
+ * Hisilicon Hi6220 clock driver
+ *
+ * Copyright (c) 2015 Hisilicon Limited.
+ *
+ * Author: Bintian Wang bintian.w...@huawei.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/kernel.h
+#include linux/clk-provider.h
+#include linux/clkdev.h
+#include linux/io.h
+#include linux/of.h
+#include linux/of_address.h
+#include linux/of_device.h
+#include linux/slab.h
+#include linux/clk.h
Do we need to include linux/clk.h? I don't see any consumer
usage here.
You are right, remove in next version.
+
+#include dt-bindings/clock/hi6220-clock.h
+
+#include clk.h
+
diff --git a/drivers/clk/hisilicon/clk.c b/drivers/clk/hisilicon/clk.c
index a078e84..5d2305c 100644
--- a/drivers/clk/hisilicon/clk.c
+++ b/drivers/clk/hisilicon/clk.c
@@ -108,4 +123,6 @@ void __init hisi_clk_register_gate(struct hisi_gate_clock *,
int, struct hisi_clock_data *);
void __init hisi_clk_register_gate_sep(struct hisi_gate_clock *,
int, struct hisi_clock_data *);
+void __init hi6220_clk_register_divider(struct hi6220_divider_clock *,
+ int, struct hisi_clock_data *);
__init markings on function prototypes are useless. Please remove them.
OK
#endif/* __HISI_CLK_H */
diff --git a/drivers/clk/hisilicon/clkdivider-hi6220.c
b/drivers/clk/hisilicon/clkdivider-hi6220.c
+
+/**
+ * struct hi6220_clk_divider - divider clock for hi6220
+ *
+ * @hw:handle between common and hardware-specific interfaces
+ * @reg: register containing divider
+ * @shift: shift to the divider bit field
+ * @width: width of the divider bit field
+ * @mask: mask for setting divider rate
+ * @table: the div table that the divider supports
+ * @lock: register lock
+ */
+struct hi6220_clk_divider {
+ struct clk_hw hw;
+ void __iomem*reg;
+ u8 shift;
+ u8 width;
+ u32 mask;
+ const struct clk_div_table *table;
+ spinlock_t *lock;
+};
The clk-divider.c code has been made reusable. Can you please
try to use the functions that it now exposes instead of
copy/pasting it and modifying it to suit your needs? A lot of
this code looks the same.
In fact, I discussed this problem with Rob Herring and Mike Turquette
in the 96boards internal mail list before.
The divider in hi6220 has a mask bit to guarantee writing the correct
bits in register when setting rate, but the index of this mask bit has
no rules to get (e.g. by left shift some fixed bits), so I add this
divider clock to handle it, we can regard hi6220_clk_divider as a
special case of generic divider clock.
If I don't add this divider clock for hi6220 chip, then I should change
the core APIs clk_register_divider and clk_register_divider_table,
and then many other drivers will be updated.
So I think just add this divider clock is a good solution now.
+
+#define to_hi6220_clk_divider(_hw) \
[..]
+
+static struct clk_ops hi6220_clkdiv_ops = {
const?
Add in next version.
+ .recalc_rate = hi6220_clkdiv_recalc_rate,
+ .round_rate = hi6220_clkdiv_round_rate,
+ .set_rate = hi6220_clkdiv_set_rate,
+};
+
+struct clk *hi6220_register_clkdiv(struct device *dev, const char *name,
+ const char *parent_name, unsigned long flags, void __iomem *reg,
+ u8 shift, u8 width, u32 mask_bit, spinlock_t *lock)
+{
+ struct hi6220_clk_divider *div;
+ struct clk *clk;
+ struct clk_init_data init;
+ struct
Re: [PATCH v4 2/5] arm64: hi6220: Document devicetree bindings for Hisilicon hi6220 SoC
Hello Stephen, On 2015/5/15 8:27, Stephen Boyd wrote: On 05/05, Bintian Wang wrote: This patch adds documentation for the devicetree bindings used by the DT files of Hisilicon hi6220 SoC mobile platform. Signed-off-by: Bintian Wang Acked-by: Stephen Boyd Thanks for your ACK! Bintian -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v4 2/5] arm64: hi6220: Document devicetree bindings for Hisilicon hi6220 SoC
Hello Stephen, On 2015/5/15 8:27, Stephen Boyd wrote: On 05/05, Bintian Wang wrote: This patch adds documentation for the devicetree bindings used by the DT files of Hisilicon hi6220 SoC mobile platform. Signed-off-by: Bintian Wang bintian.w...@huawei.com Acked-by: Stephen Boyd sb...@codeaurora.org Thanks for your ACK! Bintian -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v5 0/6] arm64,hi6220: Enable Hisilicon Hi6220 SoC
Hello Wei, >To be more specific here, I expect the patches to be picked up by Wei >Xu >and forwarded to a...@kernel.org when he's made sure that everybody >including himself is happy with the outcome. > >Arnd Could you help review and do those works based on Arnd's suggestion? Thanks, Also thanks to all engineers who help review/test this patch set. Bintian On 2015/5/7 22:00, Bintian Wang wrote: Hi6220 is one mobile solution of Hisilicon, this patchset contains initial support for Hi6220 SoC and HiKey development board, which supports octal ARM Cortex A53 cores. Initial support is minimal and includes just the arch configuration, clock driver, device tree configuration. PSCI is enabled in device tree and there is no problem to boot all the octal cores, and the CPU hotplug is also working now, you can download and compile the latest firmware based on the following link to run this patch set: https://github.com/96boards/documentation/wiki/UEFI Changes v5: * Rebase to kernel 4.1-rc2 * Add compatible string "hisilicon,hi6220-pl011" for Hisilicon designed UART * clk-hi6220.c: use __initdata for non-const arrays based on the commit 692d8328e8c039f9497eb862c6cf835de922c061 Changes v4: * Rebase to kernel 4.1-rc1 * Delete "arm,cortex-a15-gic" from the gic node in dts Changes v3: * Verified the CPU hotplug based on the new released firmware * Redefined the compatible strings of four system controllers in dts * Setting COMMON_CLK_HI6220 to a bool symbol * Keep CONFGI_ARCH_HISI sorted alphabetically Changes v2: * Split the DT bindings documents into earlier patches * Change SMP enable method from spin-table to PSCI in device tree * Remove "clock-frequency" from armv8-timer device node in device tree * Add more description about Hisilicon designed system controllers in DT bindings document * Enable high speed clock on UART1 mux * Other changes based on the discussion in the mailing list: https://lkml.org/lkml/2015/2/5/147 Bintian Wang (6): arm64: Enable Hisilicon ARMv8 SoC family in Kconfig and defconfig arm64: hi6220: Document devicetree bindings for Hisilicon hi6220 SoC clk: hi6220: Document devicetree bindings for hi6220 clock Documentation: DT: PL011: hi6220: add compatible string for Hisilicon designed UART clk: hi6220: Clock driver support for Hisilicon hi6220 SoC arm64: dts: Add dts files for Hisilicon Hi6220 SoC .../bindings/arm/hisilicon/hisilicon.txt | 87 ++ .../devicetree/bindings/clock/hi6220-clock.txt | 34 +++ Documentation/devicetree/bindings/serial/pl011.txt |4 +- arch/arm64/Kconfig |5 + arch/arm64/boot/dts/Makefile |1 + arch/arm64/boot/dts/hisilicon/Makefile |5 + arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 31 +++ arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 172 arch/arm64/configs/defconfig |1 + drivers/clk/Kconfig|2 + drivers/clk/Makefile |4 +- drivers/clk/hisilicon/Kconfig |6 + drivers/clk/hisilicon/Makefile |3 +- drivers/clk/hisilicon/clk-hi6220.c | 292 drivers/clk/hisilicon/clk.c| 29 ++ drivers/clk/hisilicon/clk.h| 17 ++ drivers/clk/hisilicon/clkdivider-hi6220.c | 273 ++ include/dt-bindings/clock/hi6220-clock.h | 173 18 files changed, 1134 insertions(+), 5 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/hi6220-clock.txt create mode 100644 arch/arm64/boot/dts/hisilicon/Makefile create mode 100644 arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts create mode 100644 arch/arm64/boot/dts/hisilicon/hi6220.dtsi create mode 100644 drivers/clk/hisilicon/Kconfig create mode 100644 drivers/clk/hisilicon/clk-hi6220.c create mode 100644 drivers/clk/hisilicon/clkdivider-hi6220.c create mode 100644 include/dt-bindings/clock/hi6220-clock.h -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v4 0/5] arm64,hi6220: Enable Hisilicon Hi6220 SoC
Hello Mark, Will, Any other suggestions for this patch set? Thanks, Bintian On 2015/5/5 20:06, Bintian Wang wrote: Hi6220 is one mobile solution of Hisilicon, this patchset contains initial support for Hi6220 SoC and HiKey development board, which supports octal ARM Cortex A53 cores. Initial support is minimal and includes just the arch configuration, clock driver, device tree configuration. PSCI is enabled in device tree and there is no problem to boot all the octal cores, and the CPU hotplug is also working now, you can download and compile the latest firmware based on the following link to run this patch set: https://github.com/96boards/documentation/wiki/UEFI Changes v4: * Rebase to kernel 4.1-rc1 * Delete "arm,cortex-a15-gic" from the gic node in dts Changes v3: * Verified the CPU hotplug based on the new released firmware * Redefined the compatible strings of four system controllers in dts * Setting COMMON_CLK_HI6220 to a bool symbol * Keep CONFGI_ARCH_HISI sorted alphabetically Changes v2: * Split the DT bindings documents into earlier patches * Change SMP enable method from spin-table to PSCI in device tree * Remove "clock-frequency" from armv8-timer device node in device tree * Add more description about Hisilicon designed system controllers in DT bindings document * Enable high speed clock on UART1 mux * Other changes based on the discussion in the mailing list: https://lkml.org/lkml/2015/2/5/147 Bintian Wang (5): arm64: Enable Hisilicon ARMv8 SoC family in Kconfig and defconfig arm64: hi6220: Document devicetree bindings for Hisilicon hi6220 SoC clk: hi6220: Document devicetree bindings for hi6220 clock clk: hi6220: Clock driver support for Hisilicon hi6220 SoC arm64: dts: Add dts files for Hisilicon Hi6220 SoC .../bindings/arm/hisilicon/hisilicon.txt | 87 ++ .../devicetree/bindings/clock/hi6220-clock.txt | 34 +++ arch/arm64/Kconfig | 5 + arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/hisilicon/Makefile | 5 + arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 31 +++ arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 172 arch/arm64/configs/defconfig | 1 + drivers/clk/Kconfig| 2 + drivers/clk/Makefile | 4 +- drivers/clk/hisilicon/Kconfig | 6 + drivers/clk/hisilicon/Makefile | 3 +- drivers/clk/hisilicon/clk-hi6220.c | 292 + drivers/clk/hisilicon/clk.c| 29 ++ drivers/clk/hisilicon/clk.h| 17 ++ drivers/clk/hisilicon/clkdivider-hi6220.c | 273 +++ include/dt-bindings/clock/hi6220-clock.h | 173 17 files changed, 1131 insertions(+), 4 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/hi6220-clock.txt create mode 100644 arch/arm64/boot/dts/hisilicon/Makefile create mode 100644 arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts create mode 100644 arch/arm64/boot/dts/hisilicon/hi6220.dtsi create mode 100644 drivers/clk/hisilicon/Kconfig create mode 100644 drivers/clk/hisilicon/clk-hi6220.c create mode 100644 drivers/clk/hisilicon/clkdivider-hi6220.c create mode 100644 include/dt-bindings/clock/hi6220-clock.h -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v5 0/6] arm64,hi6220: Enable Hisilicon Hi6220 SoC
Hello Wei, To be more specific here, I expect the patches to be picked up by Wei Xu and forwarded to a...@kernel.org when he's made sure that everybody including himself is happy with the outcome. Arnd Could you help review and do those works based on Arnd's suggestion? Thanks, Also thanks to all engineers who help review/test this patch set. Bintian On 2015/5/7 22:00, Bintian Wang wrote: Hi6220 is one mobile solution of Hisilicon, this patchset contains initial support for Hi6220 SoC and HiKey development board, which supports octal ARM Cortex A53 cores. Initial support is minimal and includes just the arch configuration, clock driver, device tree configuration. PSCI is enabled in device tree and there is no problem to boot all the octal cores, and the CPU hotplug is also working now, you can download and compile the latest firmware based on the following link to run this patch set: https://github.com/96boards/documentation/wiki/UEFI Changes v5: * Rebase to kernel 4.1-rc2 * Add compatible string hisilicon,hi6220-pl011 for Hisilicon designed UART * clk-hi6220.c: use __initdata for non-const arrays based on the commit 692d8328e8c039f9497eb862c6cf835de922c061 Changes v4: * Rebase to kernel 4.1-rc1 * Delete arm,cortex-a15-gic from the gic node in dts Changes v3: * Verified the CPU hotplug based on the new released firmware * Redefined the compatible strings of four system controllers in dts * Setting COMMON_CLK_HI6220 to a bool symbol * Keep CONFGI_ARCH_HISI sorted alphabetically Changes v2: * Split the DT bindings documents into earlier patches * Change SMP enable method from spin-table to PSCI in device tree * Remove clock-frequency from armv8-timer device node in device tree * Add more description about Hisilicon designed system controllers in DT bindings document * Enable high speed clock on UART1 mux * Other changes based on the discussion in the mailing list: https://lkml.org/lkml/2015/2/5/147 Bintian Wang (6): arm64: Enable Hisilicon ARMv8 SoC family in Kconfig and defconfig arm64: hi6220: Document devicetree bindings for Hisilicon hi6220 SoC clk: hi6220: Document devicetree bindings for hi6220 clock Documentation: DT: PL011: hi6220: add compatible string for Hisilicon designed UART clk: hi6220: Clock driver support for Hisilicon hi6220 SoC arm64: dts: Add dts files for Hisilicon Hi6220 SoC .../bindings/arm/hisilicon/hisilicon.txt | 87 ++ .../devicetree/bindings/clock/hi6220-clock.txt | 34 +++ Documentation/devicetree/bindings/serial/pl011.txt |4 +- arch/arm64/Kconfig |5 + arch/arm64/boot/dts/Makefile |1 + arch/arm64/boot/dts/hisilicon/Makefile |5 + arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 31 +++ arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 172 arch/arm64/configs/defconfig |1 + drivers/clk/Kconfig|2 + drivers/clk/Makefile |4 +- drivers/clk/hisilicon/Kconfig |6 + drivers/clk/hisilicon/Makefile |3 +- drivers/clk/hisilicon/clk-hi6220.c | 292 drivers/clk/hisilicon/clk.c| 29 ++ drivers/clk/hisilicon/clk.h| 17 ++ drivers/clk/hisilicon/clkdivider-hi6220.c | 273 ++ include/dt-bindings/clock/hi6220-clock.h | 173 18 files changed, 1134 insertions(+), 5 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/hi6220-clock.txt create mode 100644 arch/arm64/boot/dts/hisilicon/Makefile create mode 100644 arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts create mode 100644 arch/arm64/boot/dts/hisilicon/hi6220.dtsi create mode 100644 drivers/clk/hisilicon/Kconfig create mode 100644 drivers/clk/hisilicon/clk-hi6220.c create mode 100644 drivers/clk/hisilicon/clkdivider-hi6220.c create mode 100644 include/dt-bindings/clock/hi6220-clock.h -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v4 0/5] arm64,hi6220: Enable Hisilicon Hi6220 SoC
Hello Mark, Will, Any other suggestions for this patch set? Thanks, Bintian On 2015/5/5 20:06, Bintian Wang wrote: Hi6220 is one mobile solution of Hisilicon, this patchset contains initial support for Hi6220 SoC and HiKey development board, which supports octal ARM Cortex A53 cores. Initial support is minimal and includes just the arch configuration, clock driver, device tree configuration. PSCI is enabled in device tree and there is no problem to boot all the octal cores, and the CPU hotplug is also working now, you can download and compile the latest firmware based on the following link to run this patch set: https://github.com/96boards/documentation/wiki/UEFI Changes v4: * Rebase to kernel 4.1-rc1 * Delete arm,cortex-a15-gic from the gic node in dts Changes v3: * Verified the CPU hotplug based on the new released firmware * Redefined the compatible strings of four system controllers in dts * Setting COMMON_CLK_HI6220 to a bool symbol * Keep CONFGI_ARCH_HISI sorted alphabetically Changes v2: * Split the DT bindings documents into earlier patches * Change SMP enable method from spin-table to PSCI in device tree * Remove clock-frequency from armv8-timer device node in device tree * Add more description about Hisilicon designed system controllers in DT bindings document * Enable high speed clock on UART1 mux * Other changes based on the discussion in the mailing list: https://lkml.org/lkml/2015/2/5/147 Bintian Wang (5): arm64: Enable Hisilicon ARMv8 SoC family in Kconfig and defconfig arm64: hi6220: Document devicetree bindings for Hisilicon hi6220 SoC clk: hi6220: Document devicetree bindings for hi6220 clock clk: hi6220: Clock driver support for Hisilicon hi6220 SoC arm64: dts: Add dts files for Hisilicon Hi6220 SoC .../bindings/arm/hisilicon/hisilicon.txt | 87 ++ .../devicetree/bindings/clock/hi6220-clock.txt | 34 +++ arch/arm64/Kconfig | 5 + arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/hisilicon/Makefile | 5 + arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 31 +++ arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 172 arch/arm64/configs/defconfig | 1 + drivers/clk/Kconfig| 2 + drivers/clk/Makefile | 4 +- drivers/clk/hisilicon/Kconfig | 6 + drivers/clk/hisilicon/Makefile | 3 +- drivers/clk/hisilicon/clk-hi6220.c | 292 + drivers/clk/hisilicon/clk.c| 29 ++ drivers/clk/hisilicon/clk.h| 17 ++ drivers/clk/hisilicon/clkdivider-hi6220.c | 273 +++ include/dt-bindings/clock/hi6220-clock.h | 173 17 files changed, 1131 insertions(+), 4 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/hi6220-clock.txt create mode 100644 arch/arm64/boot/dts/hisilicon/Makefile create mode 100644 arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts create mode 100644 arch/arm64/boot/dts/hisilicon/hi6220.dtsi create mode 100644 drivers/clk/hisilicon/Kconfig create mode 100644 drivers/clk/hisilicon/clk-hi6220.c create mode 100644 drivers/clk/hisilicon/clkdivider-hi6220.c create mode 100644 include/dt-bindings/clock/hi6220-clock.h -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v5 0/6] arm64,hi6220: Enable Hisilicon Hi6220 SoC
Hello Kevin,
On 2015/5/12 11:05, Leo Yan wrote:
hi Kevin,
On Mon, May 11, 2015 at 05:20:54PM -0700, Kevin Hilman wrote:
On Thu, May 7, 2015 at 4:11 PM, Brent Wang wrote:
Hello Kevin,
2015-05-08 4:30 GMT+08:00 Kevin Hilman :
Bintian Wang writes:
Hi6220 is one mobile solution of Hisilicon, this patchset contains
initial support for Hi6220 SoC and HiKey development board, which
supports octal ARM Cortex A53 cores. Initial support is minimal and
includes just the arch configuration, clock driver, device tree
configuration.
PSCI is enabled in device tree and there is no problem to boot all the
octal cores, and the CPU hotplug is also working now, you can download
and compile the latest firmware based on the following link to run this
patch set:
https://github.com/96boards/documentation/wiki/UEFI
Do you have any tips for booting this using the HiSi bootloader? It
seems that I need to add the magic hisi,boardid property for dtbTool to
work. Could you share what that magic value is?
Yes, you need it.
Hisilicon has many different development boards and those boards have some
different hardware configuration, so we need different device tree
files for them.
the original hisi,boardid is used to distinguish different boards and
used by the
bootloader to judge which device tree to use at boot-up.
and maybe add it to the wiki someplace?
Maybe add to section "Known Issues" in
"https://github.com/96boards/documentation/wiki/UEFI;
is a good choice, I will update this section later.
You updated the wiki, but you didn't specify what the value should be
for this to work with the old bootloader.
Can you please give the value of that property?
hisi,boardid = <0 0 4 3>
It is needed by the old hisilicon bootloader.
I also updated the wiki page.
Also, have you tested this series with the old bootloader as well?
Below are my testing result w/t Bintian's patches and Hisilicon old
bootloader:
- Need add property "hisi,boardid" into dts;
- Need change cpu enable-method from "psci" to "spin-table";
- The bootloader has not initialized register *cntfrq_el0* so will
introduce the failure during init arch timer.
For init cntfrq_el0, we need fix this issue in Hisilicon's old
bootloader, rather than directly add "clock-frequency" for arch
timer's node in DTS. i will try to commit one patch for fix this
issue for Hisilicon's old bootloader.
So i think upper issues mainly are introduced by Hisilicon's old
bootloader but not come from Bintian's patches. How about u think for
this?
Below is my local diff which is used to compatible w/t Hisilicon's
old bootloader; Just for your reference.
Thanks,
Leo Yan
---8<---
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
index e36a539..fd1f89e 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
+++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
@@ -14,6 +14,7 @@
/ {
model = "HiKey Development Board";
+ hisi,boardid = <0 0 4 3>;
compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220";
aliases {
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
index 229937f..8ade3d9 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -13,11 +13,6 @@
#address-cells = <2>;
#size-cells = <2>;
- psci {
- compatible = "arm,psci-0.2";
- method = "smc";
- };
-
cpus {
#address-cells = <2>;
#size-cells = <0>;
@@ -57,56 +52,64 @@
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <0x0 0x0>;
- enable-method = "psci";
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x740fff8>;
};
cpu1: cpu@1 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <0x0 0x1>;
- enable-method = "psci";
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x740fff8>;
};
cpu2: cpu@2 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <0x0 0x2>;
- enable-method = "psci";
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x740fff8>;
Re: [PATCH v5 0/6] arm64,hi6220: Enable Hisilicon Hi6220 SoC
Hello Kevin,
On 2015/5/12 11:05, Leo Yan wrote:
hi Kevin,
On Mon, May 11, 2015 at 05:20:54PM -0700, Kevin Hilman wrote:
On Thu, May 7, 2015 at 4:11 PM, Brent Wang wangbint...@gmail.com wrote:
Hello Kevin,
2015-05-08 4:30 GMT+08:00 Kevin Hilman khil...@linaro.org:
Bintian Wang bintian.w...@huawei.com writes:
Hi6220 is one mobile solution of Hisilicon, this patchset contains
initial support for Hi6220 SoC and HiKey development board, which
supports octal ARM Cortex A53 cores. Initial support is minimal and
includes just the arch configuration, clock driver, device tree
configuration.
PSCI is enabled in device tree and there is no problem to boot all the
octal cores, and the CPU hotplug is also working now, you can download
and compile the latest firmware based on the following link to run this
patch set:
https://github.com/96boards/documentation/wiki/UEFI
Do you have any tips for booting this using the HiSi bootloader? It
seems that I need to add the magic hisi,boardid property for dtbTool to
work. Could you share what that magic value is?
Yes, you need it.
Hisilicon has many different development boards and those boards have some
different hardware configuration, so we need different device tree
files for them.
the original hisi,boardid is used to distinguish different boards and
used by the
bootloader to judge which device tree to use at boot-up.
and maybe add it to the wiki someplace?
Maybe add to section Known Issues in
https://github.com/96boards/documentation/wiki/UEFI;
is a good choice, I will update this section later.
You updated the wiki, but you didn't specify what the value should be
for this to work with the old bootloader.
Can you please give the value of that property?
hisi,boardid = 0 0 4 3
It is needed by the old hisilicon bootloader.
I also updated the wiki page.
Also, have you tested this series with the old bootloader as well?
Below are my testing result w/t Bintian's patches and Hisilicon old
bootloader:
- Need add property hisi,boardid into dts;
- Need change cpu enable-method from psci to spin-table;
- The bootloader has not initialized register *cntfrq_el0* so will
introduce the failure during init arch timer.
For init cntfrq_el0, we need fix this issue in Hisilicon's old
bootloader, rather than directly add clock-frequency for arch
timer's node in DTS. i will try to commit one patch for fix this
issue for Hisilicon's old bootloader.
So i think upper issues mainly are introduced by Hisilicon's old
bootloader but not come from Bintian's patches. How about u think for
this?
Below is my local diff which is used to compatible w/t Hisilicon's
old bootloader; Just for your reference.
Thanks,
Leo Yan
---8---
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
index e36a539..fd1f89e 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
+++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
@@ -14,6 +14,7 @@
/ {
model = HiKey Development Board;
+ hisi,boardid = 0 0 4 3;
compatible = hisilicon,hi6220-hikey, hisilicon,hi6220;
aliases {
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
index 229937f..8ade3d9 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -13,11 +13,6 @@
#address-cells = 2;
#size-cells = 2;
- psci {
- compatible = arm,psci-0.2;
- method = smc;
- };
-
cpus {
#address-cells = 2;
#size-cells = 0;
@@ -57,56 +52,64 @@
compatible = arm,cortex-a53, arm,armv8;
device_type = cpu;
reg = 0x0 0x0;
- enable-method = psci;
+ enable-method = spin-table;
+ cpu-release-addr = 0x0 0x740fff8;
};
cpu1: cpu@1 {
compatible = arm,cortex-a53, arm,armv8;
device_type = cpu;
reg = 0x0 0x1;
- enable-method = psci;
+ enable-method = spin-table;
+ cpu-release-addr = 0x0 0x740fff8;
};
cpu2: cpu@2 {
compatible = arm,cortex-a53, arm,armv8;
device_type = cpu;
reg = 0x0 0x2;
- enable-method = psci;
+ enable-method = spin-table;
+ cpu-release-addr = 0x0 0x740fff8;
};
cpu3: cpu@3 {
compatible = arm,cortex-a53, arm,armv8;
device_type = cpu;
reg = 0x0 0x3;
- enable-method = psci;
+ enable-method = spin-table;
+ cpu-release-addr = 0x0 0x740fff8
Re: [PATCH v5 0/6] arm64,hi6220: Enable Hisilicon Hi6220 SoC
Hello Mike, Could you help to review the patch set especially the clock drivers? if there is no problem, please help ack the clock parts :) Thanks, Bintian On 2015/5/7 22:00, Bintian Wang wrote: Hi6220 is one mobile solution of Hisilicon, this patchset contains initial support for Hi6220 SoC and HiKey development board, which supports octal ARM Cortex A53 cores. Initial support is minimal and includes just the arch configuration, clock driver, device tree configuration. PSCI is enabled in device tree and there is no problem to boot all the octal cores, and the CPU hotplug is also working now, you can download and compile the latest firmware based on the following link to run this patch set: https://github.com/96boards/documentation/wiki/UEFI Changes v5: * Rebase to kernel 4.1-rc2 * Add compatible string "hisilicon,hi6220-pl011" for Hisilicon designed UART * clk-hi6220.c: use __initdata for non-const arrays based on the commit 692d8328e8c039f9497eb862c6cf835de922c061 Changes v4: * Rebase to kernel 4.1-rc1 * Delete "arm,cortex-a15-gic" from the gic node in dts Changes v3: * Verified the CPU hotplug based on the new released firmware * Redefined the compatible strings of four system controllers in dts * Setting COMMON_CLK_HI6220 to a bool symbol * Keep CONFGI_ARCH_HISI sorted alphabetically Changes v2: * Split the DT bindings documents into earlier patches * Change SMP enable method from spin-table to PSCI in device tree * Remove "clock-frequency" from armv8-timer device node in device tree * Add more description about Hisilicon designed system controllers in DT bindings document * Enable high speed clock on UART1 mux * Other changes based on the discussion in the mailing list: https://lkml.org/lkml/2015/2/5/147 Bintian Wang (6): arm64: Enable Hisilicon ARMv8 SoC family in Kconfig and defconfig arm64: hi6220: Document devicetree bindings for Hisilicon hi6220 SoC clk: hi6220: Document devicetree bindings for hi6220 clock Documentation: DT: PL011: hi6220: add compatible string for Hisilicon designed UART clk: hi6220: Clock driver support for Hisilicon hi6220 SoC arm64: dts: Add dts files for Hisilicon Hi6220 SoC .../bindings/arm/hisilicon/hisilicon.txt | 87 ++ .../devicetree/bindings/clock/hi6220-clock.txt | 34 +++ Documentation/devicetree/bindings/serial/pl011.txt |4 +- arch/arm64/Kconfig |5 + arch/arm64/boot/dts/Makefile |1 + arch/arm64/boot/dts/hisilicon/Makefile |5 + arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 31 +++ arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 172 arch/arm64/configs/defconfig |1 + drivers/clk/Kconfig|2 + drivers/clk/Makefile |4 +- drivers/clk/hisilicon/Kconfig |6 + drivers/clk/hisilicon/Makefile |3 +- drivers/clk/hisilicon/clk-hi6220.c | 292 drivers/clk/hisilicon/clk.c| 29 ++ drivers/clk/hisilicon/clk.h| 17 ++ drivers/clk/hisilicon/clkdivider-hi6220.c | 273 ++ include/dt-bindings/clock/hi6220-clock.h | 173 18 files changed, 1134 insertions(+), 5 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/hi6220-clock.txt create mode 100644 arch/arm64/boot/dts/hisilicon/Makefile create mode 100644 arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts create mode 100644 arch/arm64/boot/dts/hisilicon/hi6220.dtsi create mode 100644 drivers/clk/hisilicon/Kconfig create mode 100644 drivers/clk/hisilicon/clk-hi6220.c create mode 100644 drivers/clk/hisilicon/clkdivider-hi6220.c create mode 100644 include/dt-bindings/clock/hi6220-clock.h -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v5 3/6] clk: hi6220: Document devicetree bindings for hi6220 clock
Document DT files bindings for Hisilicon hi6220 clock.
Signed-off-by: Bintian Wang
Acked-by: Haojian Zhuang
Suggested-by: Arnd Bergmann
---
.../devicetree/bindings/clock/hi6220-clock.txt | 34
1 file changed, 34 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/hi6220-clock.txt
diff --git a/Documentation/devicetree/bindings/clock/hi6220-clock.txt
b/Documentation/devicetree/bindings/clock/hi6220-clock.txt
new file mode 100644
index 000..53ddb19
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/hi6220-clock.txt
@@ -0,0 +1,34 @@
+* Hisilicon Hi6220 Clock Controller
+
+Clock control registers reside in different Hi6220 system controllers,
+please refer the following document to know more about the binding rules
+for these system controllers:
+
+Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
+
+Required Properties:
+
+- compatible: the compatible should be one of the following strings to
+ indicate the clock controller functionality.
+
+ - "hisilicon,hi6220-aoctrl"
+ - "hisilicon,hi6220-sysctrl"
+ - "hisilicon,hi6220-mediactrl"
+ - "hisilicon,hi6220-pmctrl"
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- #clock-cells: should be 1.
+
+For example:
+ sys_ctrl: sys_ctrl {
+ compatible = "hisilicon,hi6220-sysctrl", "syscon";
+ reg = <0x0 0xf703 0x0 0x2000>;
+ #clock-cells = <1>;
+ };
+
+Each clock is assigned an identifier and client nodes use this identifier
+to specify the clock which they consume.
+
+All these identifier could be found in .
--
1.7.9.5
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
