Re: [v2 2/3] ARM: dts: STM32 Add USB FS host mode support
On Mon, Jan 16, 2017 at 9:47 AM, Alexandre Torgue
wrote:
>
>
> On 01/16/2017 11:26 AM, Bruno Herrera wrote:
>>
>> Hi Alex,
>>
>> On Mon, Jan 16, 2017 at 6:57 AM, Alexandre Torgue
>> wrote:
>>>
>>> Hi Bruno,
>>>
>>> On 01/16/2017 03:09 AM, Bruno Herrera wrote:
>>>>
>>>>
>>>> This patch adds the USB pins and nodes for USB HS/FS cores working at FS
>>>> speed,
>>>> using embedded PHY.
>>>>
>>>> Signed-off-by: Bruno Herrera
>>>
>>>
>>>
>>> Sorry, but what is patch 1 & pacth 3 status ?
>>
>>
>> My bad, I'll add the status of the patch series version 3.
>>>
>>>
>>> For this one, can split it in 3 patches (one patch for SOC and one for
>>> each
>>> board) please.
>>>
>>
>> No problem.
>>>
>>>
>>>
>>>> ---
>>>> arch/arm/boot/dts/stm32f429-disco.dts | 30
>>>> ++
>>>> arch/arm/boot/dts/stm32f429.dtsi | 35
>>>> ++-
>>>> arch/arm/boot/dts/stm32f469-disco.dts | 30
>>>> ++
>>>> 3 files changed, 94 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/arch/arm/boot/dts/stm32f429-disco.dts
>>>> b/arch/arm/boot/dts/stm32f429-disco.dts
>>>> index 7d0415e..374c5ed 100644
>>>> --- a/arch/arm/boot/dts/stm32f429-disco.dts
>>>> +++ b/arch/arm/boot/dts/stm32f429-disco.dts
>>>> @@ -88,6 +88,16 @@
>>>> gpios = <&gpioa 0 0>;
>>>> };
>>>> };
>>>> +
>>>> + /* This turns on vbus for otg for host mode (dwc2) */
>>>> + vcc5v_otg: vcc5v-otg-regulator {
>>>> + compatible = "regulator-fixed";
>>>> + gpio = <&gpioc 4 0>;
>>>> + pinctrl-names = "default";
>>>> + pinctrl-0 = <&usbotg_pwren_h>;
>>>> + regulator-name = "vcc5_host1";
>>>> + regulator-always-on;
>>>> + };
>>>> };
>>>>
>>>> &clk_hse {
>>>> @@ -99,3 +109,23 @@
>>>> pinctrl-names = "default";
>>>> status = "okay";
>>>> };
>>>> +
>>>> +&usbotg_hs {
>>>> + compatible = "st,stm32-fsotg", "snps,dwc2";
>>>> + dr_mode = "host";
>>>> + pinctrl-0 = <&usbotg_fs_pins_b>;
>>>> + pinctrl-names = "default";
>>>> + status = "okay";
>>>> +};
>>>> +
>>>> +&pinctrl {
>>>> + usb-host {
>>>> + usbotg_pwren_h: usbotg-pwren-h {
>>>> + pins {
>>>> + pinmux = ;
>>>> + bias-disable;
>>>> + drive-push-pull;
>>>> + };
>>>> + };
>>>> + };
>>>> +};
>>>
>>>
>>>
>>> Pinctrl muxing has to be defined/declared in stm32f429.dtsi
>>>
>> This is board specific logic and it vary from board to board, should
>> it be defined here?
>
>
> Pinmuxing definition is a SOC part (as it is a possibility offered by SOC).
> Pinmuxing choice is board specific.
>
> Regarding your code, it should not boot. Ex for disco:
>
> + gpio = <&gpiob 2 0>;
>>>> + pinctrl-names = "default";
>>>> + pinctrl-0 = <&usbotg_pwren_h>;
>
> +
>
> usb-host {
>>>> + usbotg_pwren_h: usbotg-pwren-h {
>>>> + pins {
>>>> + pinmux = ;
>
> Indeed, you are declaring two time the pin PB2 (one time through pinctrl and
> one other time through gpiolib). in strict mode you can't request 2 times
> the same Pin.
> I assume that your driver want controls this GPIO (request/set direction /
> set, get value ...). in this case you only need to declare this part:
>
> gpio = <&gpiob 2 0>;
>
> The GPIO li
Re: [v2 2/3] ARM: dts: STM32 Add USB FS host mode support
Hi Alex,
On Mon, Jan 16, 2017 at 6:57 AM, Alexandre Torgue
wrote:
> Hi Bruno,
>
> On 01/16/2017 03:09 AM, Bruno Herrera wrote:
>>
>> This patch adds the USB pins and nodes for USB HS/FS cores working at FS
>> speed,
>> using embedded PHY.
>>
>> Signed-off-by: Bruno Herrera
>
>
> Sorry, but what is patch 1 & pacth 3 status ?
My bad, I'll add the status of the patch series version 3.
>
> For this one, can split it in 3 patches (one patch for SOC and one for each
> board) please.
>
No problem.
>
>
>> ---
>> arch/arm/boot/dts/stm32f429-disco.dts | 30 ++
>> arch/arm/boot/dts/stm32f429.dtsi | 35
>> ++-
>> arch/arm/boot/dts/stm32f469-disco.dts | 30 ++
>> 3 files changed, 94 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/boot/dts/stm32f429-disco.dts
>> b/arch/arm/boot/dts/stm32f429-disco.dts
>> index 7d0415e..374c5ed 100644
>> --- a/arch/arm/boot/dts/stm32f429-disco.dts
>> +++ b/arch/arm/boot/dts/stm32f429-disco.dts
>> @@ -88,6 +88,16 @@
>> gpios = <&gpioa 0 0>;
>> };
>> };
>> +
>> + /* This turns on vbus for otg for host mode (dwc2) */
>> + vcc5v_otg: vcc5v-otg-regulator {
>> + compatible = "regulator-fixed";
>> + gpio = <&gpioc 4 0>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&usbotg_pwren_h>;
>> + regulator-name = "vcc5_host1";
>> + regulator-always-on;
>> + };
>> };
>>
>> &clk_hse {
>> @@ -99,3 +109,23 @@
>> pinctrl-names = "default";
>> status = "okay";
>> };
>> +
>> +&usbotg_hs {
>> + compatible = "st,stm32-fsotg", "snps,dwc2";
>> + dr_mode = "host";
>> + pinctrl-0 = <&usbotg_fs_pins_b>;
>> + pinctrl-names = "default";
>> + status = "okay";
>> +};
>> +
>> +&pinctrl {
>> + usb-host {
>> + usbotg_pwren_h: usbotg-pwren-h {
>> + pins {
>> + pinmux = ;
>> + bias-disable;
>> + drive-push-pull;
>> + };
>> + };
>> + };
>> +};
>
>
> Pinctrl muxing has to be defined/declared in stm32f429.dtsi
>
This is board specific logic and it vary from board to board, should
it be defined here?
>
>
>> diff --git a/arch/arm/boot/dts/stm32f429.dtsi
>> b/arch/arm/boot/dts/stm32f429.dtsi
>> index e4dae0e..bc07aa8 100644
>> --- a/arch/arm/boot/dts/stm32f429.dtsi
>> +++ b/arch/arm/boot/dts/stm32f429.dtsi
>> @@ -206,7 +206,7 @@
>> reg = <0x40007000 0x400>;
>> };
>>
>> - pin-controller {
>> + pinctrl: pin-controller {
>> #address-cells = <1>;
>> #size-cells = <1>;
>> compatible = "st,stm32f429-pinctrl";
>> @@ -316,6 +316,30 @@
>> };
>> };
>>
>> + usbotg_fs_pins_a: usbotg_fs@0 {
>> + pins {
>> + pinmux =
>> ,
>> +
>> ,
>> +
>> ;
>> + bias-disable;
>> + drive-push-pull;
>> + slew-rate = <2>;
>> + };
>> + };
>> +
>> + usbotg_fs_pins_b: usbotg_fs@1 {
>> + pins {
>> + pinmux =
>> ,
>> +
>> ,
>> +
>> ;
>> + bias-disable;
>> + drive-push-pull;
>> + slew-rate = <2>;
>> + };
>> + };
>> +
>> +
>> +
>> usbotg_hs_pins_a: usbotg_hs@0 {
>> pins {
>> pinmux =
>> ,
>>
[v2 1/3] usb: dwc2: Add support for STM32F429/439/469 USB OTG HS/FS in FS mode (internal PHY)
This patch introduces a new parameter to activate USB OTG HS/FS core embedded
phy transciver. The STM32F4x9 SoC uses the GGPIO register to enable the
transciver.
Signed-off-by: Bruno Herrera
---
drivers/usb/dwc2/core.h | 4
drivers/usb/dwc2/hcd.c| 21 ++-
drivers/usb/dwc2/hw.h | 2 ++
drivers/usb/dwc2/params.c | 51 +++
4 files changed, 73 insertions(+), 5 deletions(-)
diff --git a/drivers/usb/dwc2/core.h b/drivers/usb/dwc2/core.h
index 9548d3e..e3199c5 100644
--- a/drivers/usb/dwc2/core.h
+++ b/drivers/usb/dwc2/core.h
@@ -430,6 +430,9 @@ enum dwc2_ep0_state {
* needed.
* 0 - No (default)
* 1 - Yes
+ * @activate_transceiver: Activate internal transceiver using GGPIO register.
+ * 0 - Deactivate the transceiver (default)
+ * 1 - Activate the transceiver
* @g_dma: Enables gadget dma usage (default: autodetect).
* @g_dma_desc: Enables gadget descriptor DMA (default: autodetect).
* @g_rx_fifo_size:The periodic rx fifo size for the device, in
@@ -501,6 +504,7 @@ struct dwc2_core_params {
int uframe_sched;
int external_id_pin_ctl;
int hibernation;
+ int activate_transceiver;
/*
* The following parameters are *only* set via device
diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c
index 911c3b3..6bc27f1 100644
--- a/drivers/usb/dwc2/hcd.c
+++ b/drivers/usb/dwc2/hcd.c
@@ -118,7 +118,7 @@ static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg
*hsotg)
static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
{
- u32 usbcfg, i2cctl;
+ u32 usbcfg, ggpio, i2cctl;
int retval = 0;
/*
@@ -142,6 +142,17 @@ static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool
select_phy)
return retval;
}
}
+
+ ggpio = dwc2_readl(hsotg->regs + GGPIO);
+ if (!(ggpio & GGPIO_STM32_OTG_GCCFG_PWRDWN) &&
+ (hsotg->params.activate_transceiver > 0)) {
+ dev_dbg(hsotg->dev, "Activating transceiver\n");
+ /* STM32F4xx uses the GGPIO register as general core
+* configuration register.
+*/
+ ggpio |= GGPIO_STM32_OTG_GCCFG_PWRDWN;
+ dwc2_writel(ggpio, hsotg->regs + GGPIO);
+ }
}
/*
@@ -941,7 +952,7 @@ static void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct
dwc2_host_chan *chan)
*
* In slave mode, checks for a free request queue entry, then sets the Channel
* Enable and Channel Disable bits of the Host Channel Characteristics
- * register of the specified channel to intiate the halt. If there is no free
+ * register of the specified channel to initiate the halt. If there is no free
* request queue entry, sets only the Channel Disable bit of the HCCHARn
* register to flush requests for this channel. In the latter case, sets a
* flag to indicate that the host channel needs to be halted when a request
@@ -2359,9 +2370,9 @@ static void dwc2_core_host_init(struct dwc2_hsotg *hsotg)
dwc2_flush_rx_fifo(hsotg);
/* Clear Host Set HNP Enable in the OTG Control Register */
- otgctl = dwc2_readl(hsotg->regs + GOTGCTL);
- otgctl &= ~GOTGCTL_HSTSETHNPEN;
- dwc2_writel(otgctl, hsotg->regs + GOTGCTL);
+ //otgctl = dwc2_readl(hsotg->regs + GOTGCTL);
+ //otgctl &= ~GOTGCTL_HSTSETHNPEN;
+ //dwc2_writel(otgctl, hsotg->regs + GOTGCTL);
if (hsotg->params.dma_desc_enable <= 0) {
int num_channels, i;
diff --git a/drivers/usb/dwc2/hw.h b/drivers/usb/dwc2/hw.h
index 5be056b..a84e93b 100644
--- a/drivers/usb/dwc2/hw.h
+++ b/drivers/usb/dwc2/hw.h
@@ -225,6 +225,8 @@
#define GPVNDCTL HSOTG_REG(0x0034)
#define GGPIO HSOTG_REG(0x0038)
+#define GGPIO_STM32_OTG_GCCFG_PWRDWN (1 << 16)
+
#define GUID HSOTG_REG(0x003c)
#define GSNPSIDHSOTG_REG(0x0040)
#define GHWCFG1HSOTG_REG(0x0044)
diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c
index a786256..a8fdcfc 100644
--- a/drivers/usb/dwc2/params.c
+++ b/drivers/usb/dwc2/params.c
@@ -192,6 +192,37 @@ static const struct dwc2_core_params params_amlogic = {
.hibernation= -1,
};
+static const struct dwc2_core_params params_stm32f4_otgfs = {
+ .otg_cap= DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE,
+ .otg_ver= -1,
+ .dma_desc_enable= 0,
+ .dma_desc_fs_enable = 0,
+ .speed
[v2 2/3] ARM: dts: STM32 Add USB FS host mode support
This patch adds the USB pins and nodes for USB HS/FS cores working at FS speed,
using embedded PHY.
Signed-off-by: Bruno Herrera
---
arch/arm/boot/dts/stm32f429-disco.dts | 30 ++
arch/arm/boot/dts/stm32f429.dtsi | 35 ++-
arch/arm/boot/dts/stm32f469-disco.dts | 30 ++
3 files changed, 94 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/stm32f429-disco.dts
b/arch/arm/boot/dts/stm32f429-disco.dts
index 7d0415e..374c5ed 100644
--- a/arch/arm/boot/dts/stm32f429-disco.dts
+++ b/arch/arm/boot/dts/stm32f429-disco.dts
@@ -88,6 +88,16 @@
gpios = <&gpioa 0 0>;
};
};
+
+ /* This turns on vbus for otg for host mode (dwc2) */
+ vcc5v_otg: vcc5v-otg-regulator {
+ compatible = "regulator-fixed";
+ gpio = <&gpioc 4 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usbotg_pwren_h>;
+ regulator-name = "vcc5_host1";
+ regulator-always-on;
+ };
};
&clk_hse {
@@ -99,3 +109,23 @@
pinctrl-names = "default";
status = "okay";
};
+
+&usbotg_hs {
+ compatible = "st,stm32-fsotg", "snps,dwc2";
+ dr_mode = "host";
+ pinctrl-0 = <&usbotg_fs_pins_b>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&pinctrl {
+ usb-host {
+ usbotg_pwren_h: usbotg-pwren-h {
+ pins {
+ pinmux = ;
+ bias-disable;
+ drive-push-pull;
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index e4dae0e..bc07aa8 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -206,7 +206,7 @@
reg = <0x40007000 0x400>;
};
- pin-controller {
+ pinctrl: pin-controller {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stm32f429-pinctrl";
@@ -316,6 +316,30 @@
};
};
+ usbotg_fs_pins_a: usbotg_fs@0 {
+ pins {
+ pinmux =
,
+
,
+
;
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+ usbotg_fs_pins_b: usbotg_fs@1 {
+ pins {
+ pinmux =
,
+
,
+
;
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+
+
usbotg_hs_pins_a: usbotg_hs@0 {
pins {
pinmux =
,
@@ -420,6 +444,15 @@
status = "disabled";
};
+ usbotg_fs: usb@5000 {
+ compatible = "st,stm32f4xx-fsotg", "snps,dwc2";
+ reg = <0x5000 0x4>;
+ interrupts = <67>;
+ clocks = <&rcc 0 39>;
+ clock-names = "otg";
+ status = "disabled";
+ };
+
rng: rng@50060800 {
compatible = "st,stm32-rng";
reg = <0x50060800 0x400>;
diff --git a/arch/arm/boot/dts/stm32f469-disco.dts
b/arch/arm/boot/dts/stm32f469-disco.dts
index 8877c00..8ae6763 100644
--- a/arch/arm/boot/dts/stm32f469-disco.dts
+++ b/arch/arm/boot/dts/stm32f469-disco.dts
@@ -68,6 +68,17 @@
soc {
dma-ranges = <0xc000 0x0 0x1000>;
};
+
+ /* This turns on vbus for otg for host mode (dwc2) */
+ vcc5v_otg: vcc5v-otg-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpiob 2 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usbotg_pwren_h>;
+ reg
[v2 3/3] dt-bindings: Document the STM32 USB OTG DWC2 core binding
This patch adds the documentation for STM32F4x9 USB OTG FS/HS compatible strings. Signed-off-by: Bruno Herrera --- Documentation/devicetree/bindings/usb/dwc2.txt | 4 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/dwc2.txt b/Documentation/devicetree/bindings/usb/dwc2.txt index 6c7c2bce..637223a 100644 --- a/Documentation/devicetree/bindings/usb/dwc2.txt +++ b/Documentation/devicetree/bindings/usb/dwc2.txt @@ -14,6 +14,10 @@ Required properties: - "amlogic,meson-gxbb-usb": The DWC2 USB controller instance in Amlogic S905 SoCs; - "amcc,dwc-otg": The DWC2 USB controller instance in AMCC Canyonlands 460EX SoCs; - snps,dwc2: A generic DWC2 USB controller with default parameters. + - "st,stm32f4xx-fsotg": The DWC2 USB FS/HS controller instance in STM32F4xx SoCs + configured in FS mode; + - "st,stm32f4xx-hsotg": The DWC2 USB HS controller instance in STM32F4xx SoCs + configured in HS mode; - reg : Should contain 1 register range (address and length) - interrupts : Should contain 1 interrupt - clocks: clock provider specifier -- 2.10.1 (Apple Git-78)
[RESEND PATCH] ARM: dts: stm32f429: Add missing USART3 pin config to STM32F469I-DISCO board
Including new STM32 maintainer. Rebased at stm32-dt-for-v4.10-1 and
stm32-dt-for-v4.10-2 branches. It fix the port/pin initialization in
case boot-loader does not configure/initialize the pins.
This patch adds USART3 pin configuration on PB10/PA11 pins
for STM32F469I-DISCO board.
Signed-off-by: Bruno Herrera
---
arch/arm/boot/dts/stm32f429.dtsi | 13 +
arch/arm/boot/dts/stm32f469-disco.dts | 2 ++
2 files changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 35df462..1d94eba 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -284,6 +284,19 @@
};
};
+ usart3_pins_a: usart3@0 {
+ pins1 {
+ pinmux =
;
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux =
;
+ bias-disable;
+ };
+ };
+
usbotg_hs_pins_a: usbotg_hs@0 {
pins {
pinmux =
,
diff --git a/arch/arm/boot/dts/stm32f469-disco.dts
b/arch/arm/boot/dts/stm32f469-disco.dts
index e911af8..eb3e638 100644
--- a/arch/arm/boot/dts/stm32f469-disco.dts
+++ b/arch/arm/boot/dts/stm32f469-disco.dts
@@ -71,5 +71,7 @@
};
&usart3 {
+ pinctrl-0 = <&usart3_pins_a>;
+ pinctrl-names = "default";
status = "okay";
};
--
2.7.4 (Apple Git-66)
Re: [PATCH 1/3] usb: dwc2: Add support for STM32F429/439/469 USB OTG in FS mode with internal PHY
On Mon, Jun 27, 2016 at 7:51 PM, John Youn wrote:
> On 6/21/2016 7:26 PM, Bruno Herrera wrote:
>> Signed-off-by: Bruno Herrera
>
> Please add a commit message describing the purpose of your changes,
> some information about the platform you're adding, and the special
> handling of the GGPIO.
>
Ok, no problem.
>> ---
>> drivers/usb/dwc2/core.c | 18 ++
>> drivers/usb/dwc2/core.h | 5 +
>> drivers/usb/dwc2/hcd.c | 12 +++-
>> drivers/usb/dwc2/hw.h | 2 ++
>> drivers/usb/dwc2/platform.c | 37 +
>> 5 files changed, 73 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/usb/dwc2/core.c b/drivers/usb/dwc2/core.c
>> index 4135a5f..83fbed6 100644
>> --- a/drivers/usb/dwc2/core.c
>> +++ b/drivers/usb/dwc2/core.c
>> @@ -1276,6 +1276,23 @@ static void dwc2_set_param_hibernation(struct
>> dwc2_hsotg *hsotg,
>> hsotg->core_params->hibernation = val;
>> }
>>
>> +static void dwc2_set_param_stm32_powerdown(struct dwc2_hsotg *hsotg,
>> + int val)
>> +{
>> + if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
>> + if (val >= 0) {
>> + dev_err(hsotg->dev,
>> + "'%d' invalid for parameter power down\n",
>> + val);
>> + dev_err(hsotg->dev, "power down must be 0 or 1\n");
>> + }
>> + val = 0;
>> + dev_dbg(hsotg->dev, "Setting power down to %d\n", val);
>> + }
>> +
>> + hsotg->core_params->stm32_powerdown = val;
>> +}
>> +
>> /*
>> * This function is called during module intialization to pass module
>> parameters
>> * for the DWC_otg core.
>> @@ -1323,6 +1340,7 @@ void dwc2_set_parameters(struct dwc2_hsotg *hsotg,
>> dwc2_set_param_uframe_sched(hsotg, params->uframe_sched);
>> dwc2_set_param_external_id_pin_ctl(hsotg, params->external_id_pin_ctl);
>> dwc2_set_param_hibernation(hsotg, params->hibernation);
>> + dwc2_set_param_stm32_powerdown(hsotg, params->stm32_powerdown);
>> }
>>
>> /*
>> diff --git a/drivers/usb/dwc2/core.h b/drivers/usb/dwc2/core.h
>> index 3c58d63..d3e4fcb 100644
>> --- a/drivers/usb/dwc2/core.h
>> +++ b/drivers/usb/dwc2/core.h
>> @@ -386,6 +386,10 @@ enum dwc2_ep0_state {
>> * needed.
>> * 0 - No (default)
>> * 1 - Yes
>> + * @stm32_powerdown: Enable STM32 specific USB FS transceiver power down
>> + * control.
>> + * 0 = USB FS transceiver disabled (default)
>> + * 1 = USB FS transceiver enabled
>> *
>> * The following parameters may be specified when starting the module. These
>> * parameters define how the DWC_otg controller should be configured. A
>> @@ -426,6 +430,7 @@ struct dwc2_core_params {
>> int uframe_sched;
>> int external_id_pin_ctl;
>> int hibernation;
>> + int stm32_powerdown;
>> };
>>
>> /**
>> diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c
>> index 2df3d04..4f9bb93 100644
>> --- a/drivers/usb/dwc2/hcd.c
>> +++ b/drivers/usb/dwc2/hcd.c
>> @@ -118,7 +118,7 @@ static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg
>> *hsotg)
>>
>> static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
>> {
>> - u32 usbcfg, i2cctl;
>> + u32 usbcfg, usbgpio, i2cctl;
>
> The convention in this driver would be to just call 'usbgpio' -> 'ggpio'
OK.
>
>> int retval = 0;
>>
>> /*
>> @@ -142,6 +142,16 @@ static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg,
>> bool select_phy)
>> return retval;
>> }
>> }
>> +
>> + if (hsotg->core_params->stm32_powerdown > 0) {
>> + dev_dbg(hsotg->dev, "STM32 FS PHY enabling
>> transceiver\n");
>> + /* STM32 uses the GGPIO register as general core
>> + * configuration register.
>> + */
>> + usbgpio = dwc2_readl(hsotg->regs + GGPIO);
>> + usbgpio |= STM32_OTG_GCCFG_PWRDWN;
>> + dwc2_writel(usbgpio, hsotg->regs + GGPIO);
>> + }
>&
Re: [PATCH 3/3] dt-bindings: Document the STM32 USB OTG DWC2 core binding
On Tue, Jun 28, 2016 at 5:54 PM, Rob Herring wrote:
> On Fri, Jun 24, 2016 at 03:51:18PM -0300, Bruno Herrera wrote:
>> On Fri, Jun 24, 2016 at 12:41 PM, Rob Herring wrote:
>> > On Tue, Jun 21, 2016 at 11:25:49PM -0300, Bruno Herrera wrote:
>> >> Signed-off-by: Bruno Herrera
>> >> ---
>> >> Documentation/devicetree/bindings/usb/dwc2.txt | 1 +
>> >> 1 file changed, 1 insertion(+)
>> >>
>> >> diff --git a/Documentation/devicetree/bindings/usb/dwc2.txt
>> >> b/Documentation/devicetree/bindings/usb/dwc2.txt
>> >> index 20a68bf..79e5370 100644
>> >> --- a/Documentation/devicetree/bindings/usb/dwc2.txt
>> >> +++ b/Documentation/devicetree/bindings/usb/dwc2.txt
>> >> @@ -11,6 +11,7 @@ Required properties:
>> >>- "lantiq,arx100-usb": The DWC2 USB controller instance in Lantiq ARX
>> >> SoCs;
>> >>- "lantiq,xrx200-usb": The DWC2 USB controller instance in Lantiq XRX
>> >> SoCs;
>> >>- snps,dwc2: A generic DWC2 USB controller with default parameters.
>> >> + - st,stm32-fsotg: The DWC2 USB controller instance in STM32F4 SoCs in
>> >> FS mode;
>> >
>> > This should go above snps,dwc2.
>> >
>> Ok, tks!
>>
>> > What determines FS mode vs. HS?
>> >
>> Its more HW design decision.
>> STM32F429/439/469 has two OTG controllers, one that is FS (internal
>> phy) and other that is HS (but can also work in FS mode with
>> internal/external phy)
>> This bind work with both cores FS and HS working with the internal PHY.
>>
>> I tested the following configurations:
>> 1 - STM32F429I-DISCOv1 board (OTG HS working in FS mode internal PHY)
>> 2 - STM32F469I-DISCO board (OTG FS)
>>
>> I did not tested OTG HS core working in FS mode with external PHY (I2C).
>
> You shouldn't be setting the compatible string based on which mode you
> want. So for the HS block, you need a different compatible string than
> the FS block and set the speed in another way (not sure if we have a
> standard way). Or perhaps the phy should determine the speed.
I understand but I dont see how to fix it properly unless we add a
some specific STM32 properties in the DT or in the dwc2_core_params.
In fact there are two cores, and they are different in terms of
functionality (despite of the type of the PHY).
One core is for FS and other is for HS, so they could/should have
different compatible strings because they have different
configurations and are different piece of IP/Hardware(The buffer size
are different, the number of end points and so one, DMA)
But the problem is that the HS core can also support the the FS mode
and in this case is misleading to have a HS core with an FS compatible
string.
Something like that (real case for STM32F429I-DISCO):
&usbotg_hs {
compatible = "st,stm32-fsotg", "snps,dwc2";
dr_mode = "host";
pinctrl-0 = <&usbotg_fs_pins_b>;
pinctrl-names = "default";
status = "okay";
};
Even if the decision is phy based it would lead to a STM32 specific
logic and we would need to figure out how to represent the internal
PHY.
Bruno
>
> Rob
Re: [PATCH 3/3] dt-bindings: Document the STM32 USB OTG DWC2 core binding
On Fri, Jun 24, 2016 at 12:41 PM, Rob Herring wrote: > On Tue, Jun 21, 2016 at 11:25:49PM -0300, Bruno Herrera wrote: >> Signed-off-by: Bruno Herrera >> --- >> Documentation/devicetree/bindings/usb/dwc2.txt | 1 + >> 1 file changed, 1 insertion(+) >> >> diff --git a/Documentation/devicetree/bindings/usb/dwc2.txt >> b/Documentation/devicetree/bindings/usb/dwc2.txt >> index 20a68bf..79e5370 100644 >> --- a/Documentation/devicetree/bindings/usb/dwc2.txt >> +++ b/Documentation/devicetree/bindings/usb/dwc2.txt >> @@ -11,6 +11,7 @@ Required properties: >>- "lantiq,arx100-usb": The DWC2 USB controller instance in Lantiq ARX >> SoCs; >>- "lantiq,xrx200-usb": The DWC2 USB controller instance in Lantiq XRX >> SoCs; >>- snps,dwc2: A generic DWC2 USB controller with default parameters. >> + - st,stm32-fsotg: The DWC2 USB controller instance in STM32F4 SoCs in FS >> mode; > > This should go above snps,dwc2. > Ok, tks! > What determines FS mode vs. HS? > Its more HW design decision. STM32F429/439/469 has two OTG controllers, one that is FS (internal phy) and other that is HS (but can also work in FS mode with internal/external phy) This bind work with both cores FS and HS working with the internal PHY. I tested the following configurations: 1 - STM32F429I-DISCOv1 board (OTG HS working in FS mode internal PHY) 2 - STM32F469I-DISCO board (OTG FS) I did not tested OTG HS core working in FS mode with external PHY (I2C). >> - reg : Should contain 1 register range (address and length) >> - interrupts : Should contain 1 interrupt >> - clocks: clock provider specifier >> -- >> 2.7.4 (Apple Git-66) >>
[PATCH 3/3] dt-bindings: Document the STM32 USB OTG DWC2 core binding
Signed-off-by: Bruno Herrera --- Documentation/devicetree/bindings/usb/dwc2.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/usb/dwc2.txt b/Documentation/devicetree/bindings/usb/dwc2.txt index 20a68bf..79e5370 100644 --- a/Documentation/devicetree/bindings/usb/dwc2.txt +++ b/Documentation/devicetree/bindings/usb/dwc2.txt @@ -11,6 +11,7 @@ Required properties: - "lantiq,arx100-usb": The DWC2 USB controller instance in Lantiq ARX SoCs; - "lantiq,xrx200-usb": The DWC2 USB controller instance in Lantiq XRX SoCs; - snps,dwc2: A generic DWC2 USB controller with default parameters. + - st,stm32-fsotg: The DWC2 USB controller instance in STM32F4 SoCs in FS mode; - reg : Should contain 1 register range (address and length) - interrupts : Should contain 1 interrupt - clocks: clock provider specifier -- 2.7.4 (Apple Git-66)
[PATCH 1/3] usb: dwc2: Add support for STM32F429/439/469 USB OTG in FS mode with internal PHY
Signed-off-by: Bruno Herrera
---
drivers/usb/dwc2/core.c | 18 ++
drivers/usb/dwc2/core.h | 5 +
drivers/usb/dwc2/hcd.c | 12 +++-
drivers/usb/dwc2/hw.h | 2 ++
drivers/usb/dwc2/platform.c | 37 +
5 files changed, 73 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/dwc2/core.c b/drivers/usb/dwc2/core.c
index 4135a5f..83fbed6 100644
--- a/drivers/usb/dwc2/core.c
+++ b/drivers/usb/dwc2/core.c
@@ -1276,6 +1276,23 @@ static void dwc2_set_param_hibernation(struct dwc2_hsotg
*hsotg,
hsotg->core_params->hibernation = val;
}
+static void dwc2_set_param_stm32_powerdown(struct dwc2_hsotg *hsotg,
+ int val)
+{
+ if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
+ if (val >= 0) {
+ dev_err(hsotg->dev,
+ "'%d' invalid for parameter power down\n",
+ val);
+ dev_err(hsotg->dev, "power down must be 0 or 1\n");
+ }
+ val = 0;
+ dev_dbg(hsotg->dev, "Setting power down to %d\n", val);
+ }
+
+ hsotg->core_params->stm32_powerdown = val;
+}
+
/*
* This function is called during module intialization to pass module
parameters
* for the DWC_otg core.
@@ -1323,6 +1340,7 @@ void dwc2_set_parameters(struct dwc2_hsotg *hsotg,
dwc2_set_param_uframe_sched(hsotg, params->uframe_sched);
dwc2_set_param_external_id_pin_ctl(hsotg, params->external_id_pin_ctl);
dwc2_set_param_hibernation(hsotg, params->hibernation);
+ dwc2_set_param_stm32_powerdown(hsotg, params->stm32_powerdown);
}
/*
diff --git a/drivers/usb/dwc2/core.h b/drivers/usb/dwc2/core.h
index 3c58d63..d3e4fcb 100644
--- a/drivers/usb/dwc2/core.h
+++ b/drivers/usb/dwc2/core.h
@@ -386,6 +386,10 @@ enum dwc2_ep0_state {
* needed.
* 0 - No (default)
* 1 - Yes
+ * @stm32_powerdown: Enable STM32 specific USB FS transceiver power down
+ * control.
+ * 0 = USB FS transceiver disabled (default)
+ * 1 = USB FS transceiver enabled
*
* The following parameters may be specified when starting the module. These
* parameters define how the DWC_otg controller should be configured. A
@@ -426,6 +430,7 @@ struct dwc2_core_params {
int uframe_sched;
int external_id_pin_ctl;
int hibernation;
+ int stm32_powerdown;
};
/**
diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c
index 2df3d04..4f9bb93 100644
--- a/drivers/usb/dwc2/hcd.c
+++ b/drivers/usb/dwc2/hcd.c
@@ -118,7 +118,7 @@ static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg
*hsotg)
static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
{
- u32 usbcfg, i2cctl;
+ u32 usbcfg, usbgpio, i2cctl;
int retval = 0;
/*
@@ -142,6 +142,16 @@ static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool
select_phy)
return retval;
}
}
+
+ if (hsotg->core_params->stm32_powerdown > 0) {
+ dev_dbg(hsotg->dev, "STM32 FS PHY enabling
transceiver\n");
+ /* STM32 uses the GGPIO register as general core
+* configuration register.
+*/
+ usbgpio = dwc2_readl(hsotg->regs + GGPIO);
+ usbgpio |= STM32_OTG_GCCFG_PWRDWN;
+ dwc2_writel(usbgpio, hsotg->regs + GGPIO);
+ }
}
/*
diff --git a/drivers/usb/dwc2/hw.h b/drivers/usb/dwc2/hw.h
index 281b57b..d5f9294 100644
--- a/drivers/usb/dwc2/hw.h
+++ b/drivers/usb/dwc2/hw.h
@@ -224,6 +224,8 @@
#define GPVNDCTL HSOTG_REG(0x0034)
#define GGPIO HSOTG_REG(0x0038)
+#define STM32_OTG_GCCFG_PWRDWN (1 << 16)
+
#define GUID HSOTG_REG(0x003c)
#define GSNPSIDHSOTG_REG(0x0040)
#define GHWCFG1HSOTG_REG(0x0044)
diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c
index fc6f525..d806b94 100644
--- a/drivers/usb/dwc2/platform.c
+++ b/drivers/usb/dwc2/platform.c
@@ -84,6 +84,7 @@ static const struct dwc2_core_params params_hi6220 = {
.uframe_sched = 0,
.external_id_pin_ctl= -1,
.hibernation= -1,
+ .stm32_powerdown= 0,
};
static const struct dwc2_core_params params_bcm2835 = {
@@ -115,6 +116,7 @@ static const struct dwc2_core_params params_bcm2835 = {
.uframe_sched = 0,
.external_id_pin_ctl= -1,
.hibernation
[PATCH 2/3] ARM: dts: STM32 Add USB FS host mode support
Signed-off-by: Bruno Herrera
---
arch/arm/boot/dts/stm32f429-disco.dts | 30 ++
arch/arm/boot/dts/stm32f429.dtsi | 33 -
arch/arm/boot/dts/stm32f469-disco.dts | 30 ++
3 files changed, 92 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/stm32f429-disco.dts
b/arch/arm/boot/dts/stm32f429-disco.dts
index 0140807..8e0114b 100644
--- a/arch/arm/boot/dts/stm32f429-disco.dts
+++ b/arch/arm/boot/dts/stm32f429-disco.dts
@@ -75,6 +75,16 @@
linux,default-trigger = "heartbeat";
};
};
+
+ /* This turns on vbus for otg for host mode (dwc2) */
+ vcc5v_otg: vcc5v-otg-regulator {
+ compatible = "regulator-fixed";
+ gpio = <&gpioc 4 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usbotg_pwren_h>;
+ regulator-name = "vcc5_host1";
+ regulator-always-on;
+ };
};
&clk_hse {
@@ -86,3 +96,23 @@
pinctrl-names = "default";
status = "okay";
};
+
+&usbotg_hs {
+ compatible = "st,stm32-fsotg", "snps,dwc2";
+ dr_mode = "host";
+ pinctrl-0 = <&usbotg_fs_pins_b>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&pinctrl {
+ usb-host {
+ usbotg_pwren_h: usbotg-pwren-h {
+ pins {
+ pinmux = ;
+ bias-disable;
+ drive-push-pull;
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 35df462..cb33aa2 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -176,7 +176,7 @@
reg = <0x40013800 0x400>;
};
- pin-controller {
+ pinctrl: pin-controller {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stm32f429-pinctrl";
@@ -284,6 +284,28 @@
};
};
+ usbotg_fs_pins_a: usbotg_fs@0 {
+ pins {
+ pinmux =
,
+
,
+
;
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+ usbotg_fs_pins_b: usbotg_fs@1 {
+ pins {
+ pinmux =
,
+
,
+
;
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
usbotg_hs_pins_a: usbotg_hs@0 {
pins {
pinmux =
,
@@ -388,6 +410,15 @@
status = "disabled";
};
+ usbotg_fs: usb@5000 {
+ compatible = "st,stm32-fsotg", "snps,dwc2";
+ reg = <0x5000 0x4>;
+ interrupts = <67>;
+ clocks = <&rcc 0 39>;
+ clock-names = "otg";
+ status = "disabled";
+ };
+
rng: rng@50060800 {
compatible = "st,stm32-rng";
reg = <0x50060800 0x400>;
diff --git a/arch/arm/boot/dts/stm32f469-disco.dts
b/arch/arm/boot/dts/stm32f469-disco.dts
index 83ee90d..46e5279 100644
--- a/arch/arm/boot/dts/stm32f469-disco.dts
+++ b/arch/arm/boot/dts/stm32f469-disco.dts
@@ -64,6 +64,17 @@
aliases {
serial0 = &usart3;
};
+
+ /* This turns on vbus for otg for host mode (dwc2) */
+ vcc5v_otg: vcc5v-otg-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpiob 2 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usbotg_pwren_h>;
+ regulator-name = "vcc5_host1";
+ regulator-always-on;
+ };
};
&clk_hse {
@@ -73,3 +84,22 @@
[PATCH] ARM: dts: stm32f469-disco: Fix memory size from 8Mb to 16Mb
Signed-off-by: Bruno Herrera
---
arch/arm/boot/dts/stm32f469-disco.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/stm32f469-disco.dts
b/arch/arm/boot/dts/stm32f469-disco.dts
index e911af8..83ee90d 100644
--- a/arch/arm/boot/dts/stm32f469-disco.dts
+++ b/arch/arm/boot/dts/stm32f469-disco.dts
@@ -58,7 +58,7 @@
};
memory {
- reg = <0x 0x80>;
+ reg = <0x 0x100>;
};
aliases {
--
2.7.4 (Apple Git-66)
[PATCH] wlcore: sdio: Fix crash on wlcore_probe_of when failing to parse/map irq
pdev_data pointer is being freed with kfree but the pointer is not dynamic
allocated.
Signed-off-by: Bruno Herrera
---
drivers/net/wireless/ti/wlcore/sdio.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/net/wireless/ti/wlcore/sdio.c
b/drivers/net/wireless/ti/wlcore/sdio.c
index c172da5..5839acb 100644
--- a/drivers/net/wireless/ti/wlcore/sdio.c
+++ b/drivers/net/wireless/ti/wlcore/sdio.c
@@ -241,7 +241,6 @@ static int wlcore_probe_of(struct device *dev, int *irq,
*irq = irq_of_parse_and_map(np, 0);
if (!*irq) {
dev_err(dev, "No irq in platform data\n");
- kfree(pdev_data);
return -EINVAL;
}
--
2.7.4 (Apple Git-66)
[PATCH] ARM: dts: stm32f429: Add missing USART3 pin config to STM32F469I-DISCO board
This patch adds USART3 pin configuration on PB10/PA11 pins
for STM32F469I-DISCO board.
Signed-off-by: Bruno Herrera
---
arch/arm/boot/dts/stm32f429.dtsi | 13 +
arch/arm/boot/dts/stm32f469-disco.dts | 2 ++
2 files changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 35df462..1d94eba 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -284,6 +284,19 @@
};
};
+ usart3_pins_a: usart3@0 {
+ pins1 {
+ pinmux =
;
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux =
;
+ bias-disable;
+ };
+ };
+
usbotg_hs_pins_a: usbotg_hs@0 {
pins {
pinmux =
,
diff --git a/arch/arm/boot/dts/stm32f469-disco.dts
b/arch/arm/boot/dts/stm32f469-disco.dts
index e911af8..eb3e638 100644
--- a/arch/arm/boot/dts/stm32f469-disco.dts
+++ b/arch/arm/boot/dts/stm32f469-disco.dts
@@ -71,5 +71,7 @@
};
&usart3 {
+ pinctrl-0 = <&usart3_pins_a>;
+ pinctrl-names = "default";
status = "okay";
};
--
2.7.4 (Apple Git-66)
