[GIT PULL] arm64 fixes for 4.20-rc6

2018-12-07 Thread Catalin Marinas
Hi Linus, Please pull the arm64 fix below. Thanks. The following changes since commit 2595646791c319cadfdbf271563aac97d0843dc7: Linux 4.20-rc5 (2018-12-02 15:07:55 -0800) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux tags/arm64-fixes

Re: [PATCH] mm, kmemleak: Little optimization while scanning

2018-12-07 Thread Catalin Marinas
memleak_scan: > > # echo "scan" > /sys/kernel/debug/kmemleak > > before the patch: > > kmemleak: time spend: 41596 us > > after the patch: > > kmemleak: time spend: 34899 us > > Signed-off-by: Oscar Salvador Acked-by: Catalin Marinas

Re: [PATCH v2 2/2] arm64: uaccess: Implement unsafe accessors

2018-12-06 Thread Catalin Marinas
On Mon, Dec 03, 2018 at 01:55:18PM +, Julien Thierry wrote: > diff --git a/arch/arm64/include/asm/uaccess.h > b/arch/arm64/include/asm/uaccess.h > index 07c3408..cabfcae 100644 > --- a/arch/arm64/include/asm/uaccess.h > +++ b/arch/arm64/include/asm/uaccess.h > @@ -233,6 +233,23 @@ static

Re: [RESEND PATCH] drivers/base: kmemleak ignore a known leak

2018-12-06 Thread Catalin Marinas
this leak has been existed for more than 8-year now and it does not > reference other part of the memory, let kmemleak ignore it, so users don't > need to waste time reporting this in the future. > > Signed-off-by: Qian Cai Acked-by: Catalin Marinas

Re: [PATCH] arm64: hugetlb: Register hugepages during arch init

2018-12-06 Thread Catalin Marinas
It seems that we somehow missed this patch. Cc'ing a few more people that touched hugetlbpage.c. Catalin On Tue, Oct 23, 2018 at 06:36:57AM +0530, Allen Pais wrote: > Add hstate for each supported hugepage size using arch initcall. > > * no hugepage parameters > > Without hugepage

Re: [PATCH v6 10/24] arm64: irqflags: Use ICC_PMR_EL1 for interrupt masking

2018-12-05 Thread Catalin Marinas
On Wed, Dec 05, 2018 at 04:55:54PM +, Julien Thierry wrote: > On 04/12/18 17:36, Catalin Marinas wrote: > > On Mon, Nov 12, 2018 at 11:57:01AM +, Julien Thierry wrote: > >> diff --git a/arch/arm64/include/asm/irqflags.h > >> b/arch/arm64/include/asm/irqflags.h

Re: [PATCH v6 21/24] arm64: Handle serror in NMI context

2018-12-04 Thread Catalin Marinas
On Mon, Nov 12, 2018 at 11:57:12AM +, Julien Thierry wrote: > diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c > index 5f4d9ac..66344cd 100644 > --- a/arch/arm64/kernel/traps.c > +++ b/arch/arm64/kernel/traps.c > @@ -897,13 +897,17 @@ bool arm64_is_fatal_ras_serror(struct

Re: [PATCH v6 15/24] arm64: Switch to PMR masking when starting CPUs

2018-12-04 Thread Catalin Marinas
On Mon, Nov 12, 2018 at 11:57:06AM +, Julien Thierry wrote: > diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c > index 8dc9dde..e495360 100644 > --- a/arch/arm64/kernel/smp.c > +++ b/arch/arm64/kernel/smp.c > @@ -35,6 +35,7 @@ > #include > #include > #include > +#include >

Re: [PATCH v6 10/24] arm64: irqflags: Use ICC_PMR_EL1 for interrupt masking

2018-12-04 Thread Catalin Marinas
On Mon, Nov 12, 2018 at 11:57:01AM +, Julien Thierry wrote: > diff --git a/arch/arm64/include/asm/irqflags.h > b/arch/arm64/include/asm/irqflags.h > index 24692ed..e0a32e4 100644 > --- a/arch/arm64/include/asm/irqflags.h > +++ b/arch/arm64/include/asm/irqflags.h > @@ -18,7 +18,27 @@ > >

Re: [PATCH v6 07/24] arm64: Make PMR part of task context

2018-12-04 Thread Catalin Marinas
On Mon, Nov 12, 2018 at 11:56:58AM +, Julien Thierry wrote: > diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S > index 039144e..eb8120e 100644 > --- a/arch/arm64/kernel/entry.S > +++ b/arch/arm64/kernel/entry.S > @@ -249,6 +249,12 @@ alternative_else_nop_endif > msr

Re: [PATCH v6 05/24] irqchip/gic-v3: Switch to PMR masking before calling IRQ handler

2018-12-04 Thread Catalin Marinas
On Mon, Nov 12, 2018 at 11:56:56AM +, Julien Thierry wrote: > Mask the IRQ priority through PMR and re-enable IRQs at CPU level, > allowing only higher priority interrupts to be received during interrupt > handling. > > Signed-off-by: Julien Thierry > Cc: Catalin Marinas

[GIT PULL] arm64 fixes for 4.20-rc5

2018-11-30 Thread Catalin Marinas
to enable syscall events on arm64 - Fix uninitialised pointer in iort_get_platform_device_domain() Catalin Marinas (1): arm64: Add workaround for Cortex-A76 erratum 1286807 Lorenzo Pieralisi (1): ACPI/IORT: Fix

Re: [PATCH v6 04/24] arm/arm64: gic-v3: Add PMR and RPR accessors

2018-11-30 Thread Catalin Marinas
On Mon, Nov 12, 2018 at 11:56:55AM +, Julien Thierry wrote: > Add helper functions to access system registers related to interrupt > priorities: PMR and RPR. > > Signed-off-by: Julien Thierry > Cc: Russell King > Cc: Catalin Marinas > Cc: Will Deacon > Cc: Marc Zyn

Re: [PATCH v6 03/24] arm64: cpufeature: Add cpufeature for IRQ priority masking

2018-11-30 Thread Catalin Marinas
On Mon, Nov 12, 2018 at 11:56:54AM +, Julien Thierry wrote: > Add a cpufeature indicating whether a cpu supports masking interrupts > by priority. > > The feature will be properly enabled in a later patch. > > Signed-off-by: Julien Thierry > Cc: Catalin Marinas > Cc:

Re: [PATCH v6 02/24] arm64: cpufeature: Set SYSREG_GIC_CPUIF as a boot system feature

2018-11-30 Thread Catalin Marinas
ICC_SRE_EL1.SRE, it cannot be > turned off if found on a CPU. > > Set the feature as STRICT_BOOT, if boot CPU has it, all other CPUs are > required to have it. > > Signed-off-by: Julien Thierry > Suggested-by: Daniel Thompson > Cc: Catalin Marinas > Cc: Will Deacon

Re: [PATCH v6 01/24] arm64: Remove unused daif related functions/macros

2018-11-30 Thread Catalin Marinas
Signed-off-by: Julien Thierry > Cc: Catalin Marinas > Cc: Will Deacon > Cc: James Morse Acked-by: Catalin Marinas IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify

Re: [PATCH v2] mm/memblock: skip kmemleak for kasan_init()

2018-11-29 Thread Catalin Marinas
addr != end) > [3] while (pudp++, addr = next, addr != end && pud_none(READ_ONCE(*pudp))) > [4] while (pmdp++, addr = next, addr != end && pmd_none(READ_ONCE(*pmdp))) > [5] while (ptep++, addr = next, addr != end && pte_none(READ_ONCE(*ptep))) > > Signed-off-by: Qian Cai Acked-by: Catalin Marinas (for both the kmemleak and arm64 changes)

Re: [PATCH v2] arm64: ftrace: Fix to enable syscall events on arm64

2018-11-29 Thread Catalin Marinas
On Thu, Nov 29, 2018 at 02:39:33PM +0900, Masami Hiramatsu wrote: > Since commit 4378a7d4be30 ("arm64: implement syscall wrappers") > introduced "__arm64_" prefix to all syscall wrapper symbols in > sys_call_table, syscall tracer can not find corresponding > metadata from syscall name. In the

Re: [PATCH] mm/memblock: skip kmemleak for kasan_init()

2018-11-28 Thread Catalin Marinas
On Wed, Nov 28, 2018 at 12:40:33PM -0500, Qian Cai wrote: > Kmemleak does not play well with KASAN (tested on both HPE Apollo 70 and > Huawei TaiShan 2280 aarch64 servers). > > After calling start_kernel()->setup_arch()->kasan_init(), kmemleak early > log buffer went from something like 280 to

Re: [PATCH] debugobjects: avoid recursive calls with kmemleak

2018-11-26 Thread Catalin Marinas
_cache_create() to not register a > newly allocated debug objects at all. > > Suggested-by: Catalin Marinas > Signed-off-by: Qian Cai Acked-by: Catalin Marinas

Re: [PATCH v4] debugobjects: scale the static pool size

2018-11-26 Thread Catalin Marinas
On Mon, Nov 26, 2018 at 04:45:54AM -0500, Qian Cai wrote: > On 11/25/18 11:52 PM, Qian Cai wrote: > > BTW, calling debug_objects_mem_init() before kmemleak_init() actually > > could trigger a loop on machines with 160+ CPUs until the pool is filled > > up, > > > > debug_objects_pool_min_level +=

[GIT PULL] arm64 fixes for 4.20-rc4

2018-11-24 Thread Catalin Marinas
Hi Linus, Please pull the arm64 fixes below. Thanks. The following changes since commit 9ff01193a20d391e8dbce4403dd5ef87c7eaaca6: Linux 4.20-rc3 (2018-11-18 13:33:44 -0800) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux tags/arm64-fixes

Re: [PATCH V3 5/5] arm64/mm: Enable HugeTLB migration for contiguous bit HugeTLB pages

2018-11-23 Thread Catalin Marinas
2M32M 1G > 16K:2M 32M 1G > 64K:2M512M16G > > Reviewed-by: Naoya Horiguchi > Signed-off-by: Anshuman Khandual Acked-by: Catalin Marinas

Re: [PATCH V3 4/5] arm64/mm: Enable HugeTLB migration

2018-11-23 Thread Catalin Marinas
CONT PTEPMDCONT PMDPUD >------ > 4K: NA 2M NA 1G > 16K:NA32M NA > 64K:NA 512M NA > > Reviewed-by: Naoya Horiguchi > Signed-off-by: Anshuman Khandual Acked-by: Catalin Marinas

Re: [PATCH v2] kmemleak: Turn kmemleak_lock to raw spinlock on RT

2018-11-23 Thread Catalin Marinas
On Fri, Nov 23, 2018 at 12:06:11PM +0100, Sebastian Andrzej Siewior wrote: > On 2018-11-23 12:02:55 [+0100], Andrea Parri wrote: > > > is this an RT-only problem? Because mainline should not allow read->read > > > locking or read->write locking for reader-writer locks. If this only > > > happens

Re: kmemleak: Early log buffer exceeded (525980) during boot

2018-11-10 Thread Catalin Marinas
On Sat, Nov 10, 2018 at 10:08:10AM -0500, Qian Cai wrote: > On Nov 8, 2018, at 4:23 PM, Qian Cai wrote: > > The maximum value for DEBUG_KMEMLEAK_EARLY_LOG_SIZE is only 4, so it > > disables kmemleak every time on this aarch64 server running the latest > > mainline > > (b00d209). > > > > #

[GIT PULL] arm64 fixes for 4.20-rc2

2018-11-10 Thread Catalin Marinas
Hi Linus, Please pull the arm64 fixes below. Thanks. The following changes since commit 651022382c7f8da46cb4872a545ee1da6d097d2a: Linux 4.20-rc1 (2018-11-04 15:37:52 -0800) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux tags/arm64-fixes

Re: [PATCH v2 1/2] mm: Introduce common STRUCT_PAGE_MAX_SHIFT define

2018-11-08 Thread Catalin Marinas
nstead of > set and checked with a build bug. This also allows us to use the same > define for riscv. > > Signed-off-by: Logan Gunthorpe > Acked-by: Will Deacon > Acked-by: Andrew Morton > Cc: Catalin Marinas > Cc: Arnd Bergmann > Cc: Christoph Hellwig Acked-by: Catalin Marinas

Re: [PATCH] arm64: fix commit style in the comments

2018-11-07 Thread Catalin Marinas
On Wed, Nov 07, 2018 at 11:39:11PM +0800, Peng Hao wrote: > Use git commit description style 'commit <12+ chars of sha1> > ("")' in the comments. > > Signed-off-by: Peng Hao > --- > arch/arm64/kernel/sys32.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git

Re: [PATCH] lib/raid6: Fix arm64 test build

2018-11-06 Thread Catalin Marinas
On Tue, Nov 06, 2018 at 09:16:04AM +0100, Ard Biesheuvel wrote: > (+ Catalin, Will) > > On 6 November 2018 at 01:14, Jeremy Linton wrote: > > The lib/raid6/test fails to build the neon objects > > on arm64 because the correct machine type is 'aarch64'. > > > > Once this is correctly enabled, the

Re: [PATCH] mailmap: Update email for Punit Agrawal

2018-11-05 Thread Catalin Marinas
On Fri, Nov 02, 2018 at 04:57:52PM +, Punit Agrawal wrote: > As I'll no longer be working with Arm, add a mailmap entry so any mail > directed towards me reaches the appropriate mailbox. > > Signed-off-by: Punit Agrawal I'll pick this up for 4.20-rc2 (unless Linus applies it directly).

[GIT PULL] arm64 2nd round of updates for 4.20

2018-11-03 Thread Catalin Marinas
Hi Linus, Please pull the arm64 updates below. Thank you. The following changes since commit 4debef5510071032c6d5dace31ca1cc42a120073: arm64: KVM: Guests can skip __install_bp_hardening_cb()s HYP work (2018-10-19 15:37:25 +0100) are available in the git repository at:

Re: [PATCH] arm64: hide unused swiotlb functions

2018-11-02 Thread Catalin Marinas
On Fri, Nov 02, 2018 at 04:26:07PM +0100, Arnd Bergmann wrote: > After a good chunk of the swiotlb code has been replaced with the generic > version, two functions are only used from inside of an #ifdef: > > arch/arm64/mm/dma-mapping.c:174:12: error: '__swiotlb_mmap_pfn' defined but > not used

Re: [PATCH v2] arm64: kprobe: make page to RO mode when allocate it

2018-11-02 Thread Catalin Marinas
d+0x12c/0x238 > >> [3.253417] ptdump_check_wx+0x68/0xf8 > >> [3.253637] mark_rodata_ro+0x68/0x98 > >> [3.253847] kernel_init+0x38/0x160 > >> [3.254103] ret_from_fork+0x10/0x18 > >> > >> kprobes allocates a writable executa

Re: [PATCH v2] arm64: kprobe: make page to RO mode when allocate it

2018-11-02 Thread Catalin Marinas
0 > [3.254103] ret_from_fork+0x10/0x18 > > kprobes allocates a writable executable page with module_alloc() in > order to store executable code. > Reworked to that when allocate a page it sets mode RO. Inspired by > commit 63fef14fc98a ("kprobes/x86: Make insn buffer alw

Re: [PATCH v2] arm64: kdump: fix small typo

2018-11-02 Thread Catalin Marinas
On Fri, Nov 02, 2018 at 08:36:19AM -0400, Yangtao Li wrote: > This brings the kernel doc in line with the function signature. > > Signed-off-by: Yangtao Li Queued for 4.20. Thanks. -- Catalin IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be

Re: [PATCH V2] kmemleak: Add config to select auto scan

2018-10-29 Thread Catalin Marinas
protect first_run with DEBUG_KMEMLEAK_AUTO_SCAN as this is meant > for only first automatic scan. > > Signed-off-by: Sri Krishna chowdary > Signed-off-by: Sachin Nikam > Signed-off-by: Prateek Looks fine to me. Reviewed-by: Catalin Marinas

[GIT PULL] arm64 updated for 4.20

2018-10-19 Thread Catalin Marinas
Hi Linus, Greg, I'm sending the pull request for 4.20 slightly earlier as I'm on holiday next week (not in Edinburgh). Apart from some new arm64 features and clean-ups, this request also contains the core mmu_gather changes for tracking the levels of the page table being cleared and a minor

Re: [RFC 12/17] arm64: move ptrauth keys to thread_info

2018-10-19 Thread Catalin Marinas
On Fri, Oct 05, 2018 at 09:47:49AM +0100, Kristina Martsenko wrote: > From: Mark Rutland > > To use pointer authentication in the kernel, we'll need to switch keys > in the entry assembly. This patch moves the pointer auth keys into > thread_info to make this possible. > > There should be no

Re: [PATCH] kmemleak: Add config to select auto scan

2018-10-17 Thread Catalin Marinas
On Wed, Oct 17, 2018 at 01:33:28PM +0530, Prateek Patel wrote: > diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug > index e5e7c03..9542852 100644 > --- a/lib/Kconfig.debug > +++ b/lib/Kconfig.debug > @@ -593,6 +593,17 @@ config DEBUG_KMEMLEAK_DEFAULT_OFF > Say Y here to disable kmemleak

Re: [PATCH v2 0/3] arm64: cpufeature: Fix handling of CTR_EL0

2018-10-16 Thread Catalin Marinas
On Tue, Oct 09, 2018 at 02:47:03PM +0100, Suzuki K. Poulose wrote: > This series makes sure that we handle the CTR_EL0 field mismatches > properly, especially for the IDC field. Also, skip trapping CTR > accesses on a CPU if it matches the safe value. > > Applies on arm64 for-next/core. > >

Re: [PATCH 10/10] arm64: use the generic swiotlb_dma_ops

2018-10-12 Thread Catalin Marinas
(dev, size, vaddr, dma_handle, attrs); > + if (!__free_from_pool(vaddr, PAGE_ALIGN(size))) > + void *kaddr = phys_to_virt(dma_to_phys(dev, dma_handle)); > + > + vunmap(vaddr); > + dma_direct_free_pages(dev, size, kaddr, dma_handle, attrs); > + } > } > > long arch_dma_coherent_to_pfn(struct device *dev, void *cpu_addr, With this fix: Acked-by: Catalin Marinas

Re: [PATCH 3/5] arm64: mm: make use of new memblocks_present() helper

2018-10-05 Thread Catalin Marinas
t; arch/arm64/mm/init.c | 20 +--- > 1 file changed, 1 insertion(+), 19 deletions(-) Acked-by: Catalin Marinas

Re: [PATCH v5 07/27] arm64: xen: Use existing helper to check interrupt status

2018-10-03 Thread Catalin Marinas
Stefano Stabellini > Cc: Catalin Marinas > Cc: Will Deacon Queued for 4.20. Thanks. -- Catalin

Re: [PATCH v5 05/27] arm64: Use daifflag_restore after bp_hardening

2018-10-03 Thread Catalin Marinas
ions, daifflags should be properly restored > to a state where IRQs are enabled. > > Enable IRQs by restoring DAIF_PROCCTX state after bp hardening. > > Signed-off-by: Julien Thierry > Cc: Catalin Marinas > Cc: Will Deacon > Cc: Mark Rutland > Cc: James Morse Queued for 4.20. Thanks. -- Catalin

Re: [PATCH v5 04/27] arm64: daifflags: Use irqflags functions for daifflags

2018-10-03 Thread Catalin Marinas
gt; irqflags should alter the behaviour of daifflags. > > Use irqflags_save/restore functions for the corresponding daifflags > operation. > > Signed-off-by: Julien Thierry > Cc: Catalin Marinas > Cc: Will Deacon > Cc: James Morse Queued for 4.20. Thanks. -- Catalin

Re: [PATCH] arm64: arch_timer: avoid unused function warning

2018-10-03 Thread Catalin Marinas
On Tue, Oct 02, 2018 at 11:11:44PM +0200, Arnd Bergmann wrote: > arm64_1188873_read_cntvct_el0() is protected by the correct > CONFIG_ARM64_ERRATUM_1188873 #ifdef, but the only reference to it is > also inside of an CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND section, > and causes a warning if that is

Re: [Problem] Cache line starvation

2018-10-03 Thread Catalin Marinas
On Fri, 21 Sep 2018 at 13:22, Peter Zijlstra wrote: > On Fri, Sep 21, 2018 at 02:02:26PM +0200, Sebastian Andrzej Siewior wrote: > > We reproducibly observe cache line starvation on a Core2Duo E6850 (2 > > cores), a i5-6400 SKL (4 cores) and on a NXP LS2044A ARM Cortex-A72 (4 > > cores). > > > >

Re: RESEND and REBASE arm+arm64+aarch32 vdso rewrite

2018-10-02 Thread Catalin Marinas
On Mon, Oct 01, 2018 at 01:44:52PM -0700, Mark Salyzyn wrote: > On 10/01/2018 11:49 AM, John Stultz wrote: > > On Mon, Oct 1, 2018 at 10:58 AM, Mark Salyzyn wrote: > > > Last sent 23 Nov 2016. > > > > > > The following 23 patches are rebased and resent, and represent a > > > rewrite of the arm

Re: [PATCH 0/2] arm64: remove some extra semicolon

2018-10-01 Thread Catalin Marinas
On Mon, Sep 03, 2018 at 05:59:35PM +0100, Will Deacon wrote: > On Thu, Aug 09, 2018 at 10:20:39PM +0800, zhong jiang wrote: > > There are some extra semicolon in arm64 architecture. Just remove them. > > These are trivial but certainly not urgent, so I guess Catalin can pick > them up for 4.20. >

Re: [RESEND PATCH 0/2] Don't use SIGMINSTKSZ when enforcing alternative signal stack size for compat tasks

2018-10-01 Thread Catalin Marinas
On Fri, Sep 28, 2018 at 02:18:11PM +0100, Steve McIntyre wrote: > On Wed, Sep 05, 2018 at 03:34:41PM +0100, Will Deacon wrote: > >Hi all, > > > >This is a resend of: > > > > http://lists.infradead.org/pipermail/linux-arm-kernel/2018-July/593559.html > > > >now based on 4.19-rc2. > > > >The Debian

Re: linux-next: manual merge of the userns tree with the arm64 tree

2018-09-28 Thread Catalin Marinas
On Fri, Sep 28, 2018 at 01:49:29PM +1000, Stephen Rothwell wrote: > diff --cc arch/arm64/kernel/traps.c > index 21689c6a985f,856b32aa03d8.. > --- a/arch/arm64/kernel/traps.c > +++ b/arch/arm64/kernel/traps.c > @@@ -353,12 -366,6 +368,9 @@@ void force_signal_inject(int signal, in >

Re: [REVIEW][PATCH 00/15] signal/arm64: siginfo cleanups

2018-09-27 Thread Catalin Marinas
On Thu, Sep 27, 2018 at 11:39:35AM +0200, Eric W. Biederman wrote: > Catalin Marinas writes: > > On Mon, Sep 24, 2018 at 11:07:05AM +0200, Eric W. Biederman wrote: > >> After these patches have had a chance to be reviewed I plan to merge > >> them by my siginfo tree

Re: [REVIEW][PATCH 00/15] signal/arm64: siginfo cleanups

2018-09-26 Thread Catalin Marinas
Hi Eric, On Mon, Sep 24, 2018 at 11:07:05AM +0200, Eric W. Biederman wrote: > This is the continuation of my work to sort out signaling of exceptions > with siginfo. The old signal sending functions by taking a siginfo > argument resulted in their callers having to deal with the fiddly nature >

Re: [PATCH v5 0/6] Move swapper_pg_dir to rodata section.

2018-09-25 Thread Catalin Marinas
On Tue, Sep 25, 2018 at 03:06:25PM +0100, Mark Rutland wrote: > On Tue, Sep 25, 2018 at 05:53:16PM +0800, Jun Yao wrote: > > On Mon, Sep 24, 2018 at 06:19:36PM +0100, Mark Rutland wrote: > > > I've pushed a branch with the cleanups I requested [1] folded in. > > > > > > I'm still a bit worried

Re: [PATCH v1 1/3] arm: mm: reordering memory type table

2018-09-24 Thread Catalin Marinas
On Mon, Sep 17, 2018 at 09:44:49AM +0900, Minchan Kim wrote: > To use bit 5 in page table as L_PTE_SPECIAL, we need a room for that. > It seems we don't need 4 bits for the memory type with ARMv6+. > If it's true, let's reorder bits to make bit 5 free. > > We will use the bit for L_PTE_SPECIAL in

Re: linux-next: manual merge of the akpm-current tree with the arm64 tree

2018-09-24 Thread Catalin Marinas
Hi Stephen, On Mon, Sep 24, 2018 at 02:38:53PM +1000, Stephen Rothwell wrote: > diff --cc arch/arm64/Kconfig > index da5e6f085561,f8a618a292f4.. > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@@ -785,7 -786,8 +785,8 @@@ config ARCH_FLATMEM_ENABL > def_bool !NUMA > >

Re: [PATCH v13 3/3] arm64: Implement page table free interfaces

2018-09-21 Thread Catalin Marinas
On Thu, Sep 20, 2018 at 06:25:29PM +0100, Catalin Marinas wrote: > On Wed, Jun 06, 2018 at 12:31:21PM +0530, Chintan Pandya wrote: > > diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c > > index 8ae5d7a..65f8627 100644 > > --- a/arch/arm64/mm/mmu.c > > +++ b/arch/

Re: [PATCH v13 3/3] arm64: Implement page table free interfaces

2018-09-20 Thread Catalin Marinas
Hi Chintan, On Wed, Jun 06, 2018 at 12:31:21PM +0530, Chintan Pandya wrote: > diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c > index 8ae5d7a..65f8627 100644 > --- a/arch/arm64/mm/mmu.c > +++ b/arch/arm64/mm/mmu.c > @@ -45,6 +45,7 @@ > #include > #include > #include > +#include >

Re: [RFC 1/3] arm: mm: reordering memory type table

2018-09-10 Thread Catalin Marinas
On Thu, Sep 06, 2018 at 07:22:10PM +0900, Minchan Kim wrote: > diff --git a/arch/arm/include/asm/pgtable-2level.h > b/arch/arm/include/asm/pgtable-2level.h > index 92fd2c8a9af0..91b99fadcba1 100644 > --- a/arch/arm/include/asm/pgtable-2level.h > +++ b/arch/arm/include/asm/pgtable-2level.h > @@

Re: [PATCH] arm64: defconfig: enable EFI_ARMSTUB_DTB_LOADER

2018-09-09 Thread Catalin Marinas
On Wed, Sep 05, 2018 at 11:04:36AM -0700, Scott Branden wrote: > On 18-09-05 11:00 AM, Grant Likely wrote: > > On Wed, Sep 5, 2018 at 6:27 PM Scott Branden > > wrote: > > > On 18-09-05 02:40 AM, Ard Biesheuvel wrote: > > > > On 4 September 2018 at 19:19, Scott Branden > > > > wrote: > > > > >

Re: [PATCH v3] kmemleak: add module param to print warnings to dmesg

2018-09-03 Thread Catalin Marinas
> v3: Expand use case description. Replace config option with module parameter. > > mm/kmemleak.c | 42 +++++++--- > 1 file changed, 35 insertions(+), 7 deletions(-) Acked-by: Catalin Marinas

Re: [PATCHv2] kmemleak: Add option to print warnings to dmesg

2018-08-31 Thread Catalin Marinas
On Thu, Aug 30, 2018 at 09:43:27AM +0200, Vincent Whitchurch wrote: > On Tue, Aug 28, 2018 at 11:26:22AM +0100, Catalin Marinas wrote: > > On Tue, Aug 28, 2018 at 12:14:12PM +0200, Vincent Whitchurch wrote: > > > On Mon, Aug 27, 2018 at 03:16:41PM -0700, Andrew Morton wrote: >

Re: Query on dma_set_mask_and_coherent() Usage

2018-08-28 Thread Catalin Marinas
On Thu, Aug 23, 2018 at 08:20:36PM +0530, Kedareswararao Appana wrote: > On arm64 platform I have booted Linux only with > 32-bit > Address i.e from 0x8 (reg = <0x8 0x 0x0 0x8000>) So you have 2GB of RAM starting at 0x8__. > In my driver, I am using

Re: [PATCHv2] kmemleak: Add option to print warnings to dmesg

2018-08-28 Thread Catalin Marinas
On Tue, Aug 28, 2018 at 12:14:12PM +0200, Vincent Whitchurch wrote: > On Mon, Aug 27, 2018 at 03:16:41PM -0700, Andrew Morton wrote: > > On Mon, 27 Aug 2018 10:38:21 +0200 Vincent Whitchurch > > wrote: > > > --- a/lib/Kconfig.debug > > > +++ b/lib/Kconfig.debug > > > @@ -593,6 +593,15 @@ config

Re: [PATCH] kmemleak: Always register debugfs file

2018-08-24 Thread Catalin Marinas
ailable but is disabled > by default and can be activated via the kernel command line. > > Signed-off-by: Vincent Whitchurch I think that's also consistent with a late disabling of kmemleak when the debugfs entry sticks around. Acked-by: Catalin Marinas

Re: [PATCH] kmemleak: Add option to print warnings to dmesg

2018-08-24 Thread Catalin Marinas
On Fri, Aug 24, 2018 at 02:40:11PM +0200, Vincent Whitchurch wrote: > diff --git a/mm/kmemleak.c b/mm/kmemleak.c > index 9a085d525bbc..61ba47a357fc 100644 > --- a/mm/kmemleak.c > +++ b/mm/kmemleak.c > @@ -311,6 +311,9 @@ static void hex_dump_object(struct seq_file *seq, > const u8 *ptr =

Re: [RFC PATCH 2/2] mm: mmu_notifier fix for tlb_end_vma

2018-08-23 Thread Catalin Marinas
On Thu, Aug 23, 2018 at 06:47:09PM +1000, Nicholas Piggin wrote: > The generic tlb_end_vma does not call invalidate_range mmu notifier, > and it resets resets the mmu_gather range, which means the notifier > won't be called on part of the range in case of an unmap that spans > multiple vmas. > >

Re: [RESEND PATCH v10 1/6] arm: arm64: introduce CONFIG_HAVE_MEMBLOCK_PFN_VALID

2018-08-17 Thread Catalin Marinas
On Fri, Jul 06, 2018 at 05:01:10PM +0800, Jia He wrote: > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > index 42c090c..26d75f4 100644 > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -778,6 +778,10 @@ config ARCH_SELECT_MEMORY_MODEL > config HAVE_ARCH_PFN_VALID > def_bool

Re: framebuffer corruption due to overlapping stp instructions on arm64

2018-08-08 Thread Catalin Marinas
On Wed, Aug 08, 2018 at 04:01:12PM +0100, Richard Earnshaw wrote: > On 08/08/18 15:12, Mikulas Patocka wrote: > > On Wed, 8 Aug 2018, Catalin Marinas wrote: > >> On Fri, Aug 03, 2018 at 01:09:02PM -0400, Mikulas Patocka wrote: > >>> while (1) { > >>>

Re: framebuffer corruption due to overlapping stp instructions on arm64

2018-08-08 Thread Catalin Marinas
On Wed, Aug 08, 2018 at 02:26:11PM +, David Laight wrote: > From: Mikulas Patocka > > Sent: 08 August 2018 14:47 > ... > > The problem on ARM is that I see data corruption when the overlapping > > unaligned writes are done just by a single core. > > Is this a sequence of unaligned writes

Re: framebuffer corruption due to overlapping stp instructions on arm64

2018-08-08 Thread Catalin Marinas
On Wed, Aug 08, 2018 at 10:12:27AM -0400, Mikulas Patocka wrote: > On Wed, 8 Aug 2018, Catalin Marinas wrote: > > On Fri, Aug 03, 2018 at 01:09:02PM -0400, Mikulas Patocka wrote: > > > while (1) { > > > start = (unsigned)random() % (LEN + 1); > > &

Re: [PATCH] arm64: Trap WFI executed in userspace

2018-08-08 Thread Catalin Marinas
map this to SIGILL rather than be permissive and regret it later. > > I couldn't find any user, and I'm happy to just send userspace to hell > in that case. But it could also been said that since it was never > prevented, it is a de-facto ABI. I wouldn't really go as far as SIGILL on WFI. I think the patch is fine as it is. In case Will plans to merge it: Acked-by: Catalin Marinas

Re: framebuffer corruption due to overlapping stp instructions on arm64

2018-08-08 Thread Catalin Marinas
Hi Matt, On Fri, Aug 03, 2018 at 03:44:44PM -0500, Matt Sealey wrote: > On 3 August 2018 at 13:25, Mikulas Patocka wrote: > > On Fri, 3 Aug 2018, Ard Biesheuvel wrote: > >> Are we still talking about overlapping unaligned accesses here? Or do > >> you see other failures as well? > > > > Yes - it

Re: framebuffer corruption due to overlapping stp instructions on arm64

2018-08-08 Thread Catalin Marinas
On Fri, Aug 03, 2018 at 01:09:02PM -0400, Mikulas Patocka wrote: > while (1) { > start = (unsigned)random() % (LEN + 1); > end = (unsigned)random() % (LEN + 1); > if (start > end) > continue; > for (i = start; i <

Re: framebuffer corruption due to overlapping stp instructions on arm64

2018-08-06 Thread Catalin Marinas
On Mon, Aug 06, 2018 at 05:47:36PM +0200, Ard Biesheuvel wrote: > On 6 August 2018 at 14:42, Robin Murphy wrote: > > On 06/08/18 11:25, Mikulas Patocka wrote: > > [...] > >>> > >>> None of this explains why some transactions fail to make it across > >>> entirely. The overlapping writes in

Re: [PATCH 1/1] arm64: kexec: machine_kexec should call __flush_icache_range

2018-07-30 Thread Catalin Marinas
On Mon, Jul 30, 2018 at 05:22:35PM +0100, Will Deacon wrote: > On Mon, Jul 30, 2018 at 05:16:42PM +0100, Catalin Marinas wrote: > > On Mon, Jul 30, 2018 at 10:29:21AM -0500, Dave Kleikamp wrote: > > > machine_kexec flushes the reboot_code_buffer from the icache > > > af

Re: [PATCH 1/1] arm64: kexec: machine_kexec should call __flush_icache_range

2018-07-30 Thread Catalin Marinas
t; Signed-off-by: Dave Kleikamp > Cc: AKASHI Takahiro > Cc: Catalin Marinas > Cc: Will Deacon > --- > arch/arm64/kernel/machine_kexec.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm64/kernel/machine_kexec.c > b/arch/arm64/kernel/ma

[GIT PULL] arm64 fixes for 4.18-rc4

2018-07-07 Thread Catalin Marinas
Hi Linus, Please pull the arm64 patches below. Thanks. The following changes since commit 021c91791a5e7e85c567452f1be3e4c2c6cb6063: Linux 4.18-rc3 (2018-07-01 16:04:53 -0700) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux tags/arm64-fixes

Re: [PATCH 2/2] arm64: add support for 43bit physical address

2018-07-05 Thread Catalin Marinas
On Tue, Jul 03, 2018 at 06:35:32PM +, Nikunj Kela (nkela) wrote: > We are trying to reduce the memory allocation needed for kdump kernel. > We want to reserve less than 32M for kdump kernel if possible. We are > able to get ~14M saving by the proposed change. Have you tried disabling

Re: [PATCH] arm64: Clear the stack

2018-07-03 Thread Catalin Marinas
On Tue, Jul 03, 2018 at 01:14:41PM +0100, Mark Rutland wrote: > On Mon, Jul 02, 2018 at 11:48:05AM -0700, Laura Abbott wrote: > > On 07/02/2018 06:02 AM, Alexander Popov wrote: > > > On 29.06.2018 22:05, Laura Abbott wrote: > > > > Implementation of stackleak based heavily on the x86 version > > >

Re: [PATCH 2/2] arm64: add support for 43bit physical address

2018-07-03 Thread Catalin Marinas
On Mon, Jul 02, 2018 at 02:04:51PM -0700, Nikunj Kela wrote: > This patch adds support for 43bit physical address. Additionally, > this patch adds support for 27bit section size. This is useful in > reducing kernel memory usage. One usecase is in kdump kernel. Some numbers please. -- Catalin

[GIT PULL] arm64 fixes for 4.18-rc3

2018-06-29 Thread Catalin Marinas
() which itself uses alternatives. Change the code to use an unpatched variant of cache maintenance - Remove unnecessary ISBs from set_{pte,pmd,pud} - perf: xgene_pmu: Fix IOB SLOW PMU parser error Catalin Marinas (1): Merge

[GIT PULL] arm64 fixes for 4.18-rc2

2018-06-22 Thread Catalin Marinas
Hi Linus, Please pull the arm64 fixes below. Thanks. The following changes since commit ce397d215ccd07b8ae3f71db689aedb85d56ab40: Linux 4.18-rc1 (2018-06-17 08:04:49 +0900) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux tags/arm64-fixes

Re: [PATCH] arm64: make secondary_start_kernel() notrace

2018-06-18 Thread Catalin Marinas
On Tue, Jun 12, 2018 at 05:07:37PM +0800, Zhizhou Zhang wrote: > We can't call function trace hook before setup percpu offset. > When entering secondary_start_kernel(), percpu offset has not > been initialized. So this lead hotplug malfunction. > Here is the flow to reproduce this bug: > > echo

[GIT PULL] arm64 patches for 4.18

2018-06-08 Thread Catalin Marinas
Arnd Bergmann (3): drivers/bus: arm-cci: fix build warnings ARM: mcpm, perf/arm-cci: export mcpm_is_available arm64: cpu_errata: include required headers Catalin Marinas (4): Revert "arm64: Increase the max granular size"

Re: [PATCH v2] arm64: topology: Avoid checking numa mask for scheduler MC selection

2018-06-06 Thread Catalin Marinas
On Wed, Jun 06, 2018 at 11:38:46AM -0500, Jeremy Linton wrote: > The numa mask subset check can often lead to system hang or crash during > CPU hotplug and system suspend operation if NUMA is disabled. This is > mostly observed on HMP systems where the CPU compute capacities are > different and

Re: [PATCH v2 2/3] ACPI / PPTT: fix build when CONFIG_ACPI_PPTT is not enabled

2018-06-05 Thread Catalin Marinas
On Tue, Jun 05, 2018 at 03:35:03PM +0100, Sudeep Holla wrote: > Though CONFIG_ACPI_PPTT is selected by platforms and nor user visible, > it may be useful to support the build with CONFIG_ACPI_PPTT disabled. > > This patch adds the missing dummy/boiler plate implementation to fix > the build. > >

Re: [PATCH] arm64: cpu_errata: include required headers

2018-06-05 Thread Catalin Marinas
On Tue, Jun 05, 2018 at 01:50:07PM +0200, Arnd Bergmann wrote: > Without including psci.h and arm-smccc.h, we now get a build failure in > some configurations: > > arch/arm64/kernel/cpu_errata.c: In function 'arm64_update_smccc_conduit': > arch/arm64/kernel/cpu_errata.c:278:10: error: 'psci_ops'

Re: [PATCH v9 00/12] Support PPTT for ARM64

2018-06-04 Thread Catalin Marinas
On Thu, May 17, 2018 at 06:05:24PM +0100, Catalin Marinas wrote: > On Fri, May 11, 2018 at 06:57:55PM -0500, Jeremy Linton wrote: > > Jeremy Linton (12): > > drivers: base: cacheinfo: move cache_setup_of_node() > > drivers: base: cacheinfo: setup DT cache properties

Re: [PATCH v2 00/17] arm64 SSBD (aka Spectre-v4) mitigation

2018-05-31 Thread Catalin Marinas
On Tue, May 29, 2018 at 01:11:04PM +0100, Marc Zyngier wrote: > Marc Zyngier (17): > arm/arm64: smccc: Add SMCCC-specific return codes > arm64: Call ARCH_WORKAROUND_2 on transitions between EL0 and EL1 > arm64: Add per-cpu infrastructure to call ARCH_WORKAROUND_2 > arm64: Add

Re: [PATCH v9 00/12] Support PPTT for ARM64

2018-05-17 Thread Catalin Marinas
On Fri, May 11, 2018 at 06:57:55PM -0500, Jeremy Linton wrote: > Jeremy Linton (12): > drivers: base: cacheinfo: move cache_setup_of_node() > drivers: base: cacheinfo: setup DT cache properties early > cacheinfo: rename of_node to fw_token > arm64/acpi: Create arch specific cpu to acpi id

Re: [PATCH] arm64: remove no-op macro VMLINUX_SYMBOL()

2018-05-16 Thread Catalin Marinas
On Wed, May 09, 2018 at 04:46:26PM +0900, Masahiro Yamada wrote: > VMLINUX_SYMBOL() is no-op unless CONFIG_HAVE_UNDERSCORE_SYMBOL_PREFIX > is defined. It has ever been selected only by BLACKFIN and METAG. > VMLINUX_SYMBOL() is unneeded for ARM64-specific code. > > Signed-off-by: Masahiro Yamada

Re: [PATCH v3 4/4] KVM: arm64: Add support for PUD hugepages at stage 2

2018-05-15 Thread Catalin Marinas
nule) which can be useful on cores that > support mapping larger block sizes in the TLB entries. > > Signed-off-by: Punit Agrawal <punit.agra...@arm.com> > Reviewed-by: Christoffer Dall <christoffer.d...@arm.com> > Cc: Marc Zyngier <marc.zyng...@arm.com> > Cc: Russell

Re: [PATCH v2 4/4] KVM: arm64: Add support for PUD hugepages at stage 2

2018-05-15 Thread Catalin Marinas
nule) which can be useful on cores that > support mapping larger block sizes in the TLB entries. > > Signed-off-by: Punit Agrawal <punit.agra...@arm.com> > Cc: Christoffer Dall <christoffer.d...@arm.com> > Cc: Marc Zyngier <marc.zyng...@arm.com> > Cc: Russell

Re: [GIT PULL] arm64: updates for 4.17

2018-05-11 Thread Catalin Marinas
dependencies, > > so the diffstat strays slightly out of arm64 due to his changes. > {snip} > > > > Catalin Marinas (1): > > arm64: Revert L1_CACHE_SHIFT back to 6 (64-byte cache line size) > > I'm wondering if we are changing the L1_CACHE_SHIFT to 6 in 4.17? &g

Re: [PATCH 4/6] mm, arm64: untag user addresses in mm/gup.c

2018-05-08 Thread Catalin Marinas
On Wed, May 02, 2018 at 07:25:17PM +0200, Andrey Konovalov wrote: > On Wed, May 2, 2018 at 5:36 PM, Kirill A. Shutemov > wrote: > > On Wed, May 02, 2018 at 02:38:42PM +, Andrey Konovalov wrote: > >> > Does having a tagged address here makes any difference? I

Re: [PATCH v8 2/4] arm64: tlbflush: Introduce __flush_tlb_kernel_pgtable

2018-04-27 Thread Catalin Marinas
On Tue, Apr 03, 2018 at 01:30:44PM +0530, Chintan Pandya wrote: > Add an interface to invalidate intermediate page tables > from TLB for kernel. > > Signed-off-by: Chintan Pandya > --- > arch/arm64/include/asm/tlbflush.h | 6 ++ > 1 file changed, 6 insertions(+) > >

Re: [PATCH v8 0/4] Fix issues with huge mapping in ioremap for ARM64

2018-04-27 Thread Catalin Marinas
On Tue, Apr 17, 2018 at 03:55:08PM +0530, Chintan Pandya wrote: > Ping... > > On 4/3/2018 1:30 PM, Chintan Pandya wrote: > > This series of patches are follow up work (and depends on) > > Toshi Kani 's patches "fix memory leak/ > > panic in ioremap huge pages". First of all,

Re: [PATCH 0/6] arm64: untag user pointers passed to the kernel

2018-04-26 Thread Catalin Marinas
On Wed, Apr 25, 2018 at 04:45:37PM +0200, Andrey Konovalov wrote: > On Thu, Apr 19, 2018 at 11:33 AM, Kirill A. Shutemov > wrote: > > On Wed, Apr 18, 2018 at 08:53:09PM +0200, Andrey Konovalov wrote: > >> arm64 has a feature called Top Byte Ignore, which allows to embed

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