Hi,
On Mon, Jan 29, 2024 at 12:09:50PM -0800, Luis Chamberlain wrote:
> On Thu, Dec 21, 2023 at 10:02:46AM +0100, Christophe Leroy wrote:
> > Declaring rodata_enabled and mark_rodata_ro() at all time
> > helps removing related #ifdefery in C files.
> >
> > Signed-off-by: Christophe Leroy
>
>
, 7 insertions(+), 11 deletions(-)
> >
>
> Tested on asurada (spherion) and jacuzzi (juniper). The issue was detected by
> KernelCI, so:
>
> Reported-by: "kernelci.org bot"
> Tested-by: Laura Nao
Reviewed-by: Chen-Yu Tsai
Tested-by: Chen-Yu Tsai
on Hayato (MT8192) and Juniper (MT8183).
On Tue, Sep 19, 2023 at 5:26 PM AngeloGioacchino Del Regno
wrote:
>
> Il 19/09/23 07:03, Chen-Yu Tsai ha scritto:
> > In the just landed multi-core SCP work, detection of single/multi core
> > SCP is done by checking the immediate child node of the SCP complex
> > devi
On Tue, Sep 19, 2023 at 9:17 AM Mathieu Poirier
wrote:
>
> On Mon, Sep 18, 2023 at 06:44:25PM +0800, Chen-Yu Tsai wrote:
> > On Mon, Sep 18, 2023 at 6:32 PM Laura Nao wrote:
> > >
> > > > Other than patch 2 and 14, I have applied this set. The remaining
old device trees working again.
Reported-by: Laura Nao
Fixes: 1fdbf0cdde98 ("remoteproc: mediatek: Probe SCP cluster on multi-core
SCP")
Signed-off-by: Chen-Yu Tsai
---
The patch is based on next-20230918 with a whole bunch of local patches
stacked on top. None of my local patches are r
On Mon, Sep 18, 2023 at 6:32 PM Laura Nao wrote:
>
> > Other than patch 2 and 14, I have applied this set. The remaining patches
> > will
> > have to be resent to Matthias.
>
> > Thanks,
> > Mathieu
>
> Hello,
>
> With patch 2 missing, the SCP is not probed correctly anymore on asurada
>
Hi,
On Mon, Apr 19, 2021 at 10:52 AM Samuel Holland wrote:
>
> Dealing with the inconsistent numbering has been a major pain, and
> there is a solution with (as far as I can tell) no tangible downsides.
> So let's use it.
>
> Yes, I know the kernel supports UUIDs for root=. But UUIDs do not help
On Mon, Apr 19, 2021 at 9:58 AM Samuel Holland wrote:
>
> This device currently reports an "Unknown" type in sysfs.
> Since it is an eFuse hardware device, set its type to OTP.
>
> Signed-off-by: Samuel Holland
Acked-by: Chen-Yu Tsai
On Mon, Apr 12, 2021 at 6:03 PM Johan Jonker wrote:
>
> On 4/12/21 5:15 AM, Chen-Yu Tsai wrote:
> > On Sun, Apr 11, 2021 at 9:11 PM Johan Jonker wrote:
> >>
> >> A test with the command below gives this error:
> >>
> >> /arch/arm/boot/dts/rv1108-e
On Sun, Apr 11, 2021 at 9:11 PM Johan Jonker wrote:
>
> A test with the command below gives this error:
>
> /arch/arm/boot/dts/rv1108-evb.dt.yaml:
> pwm@1028: 'interrupts' does not match any of the regexes:
> 'pinctrl-[0-9]+'
>
> "interrupts" is an undocumented property, so remove them
> from
On Mon, Apr 5, 2021 at 7:03 PM Johan Jonker wrote:
>
> Hi Tianling,
>
> On 4/5/21 11:34 AM, Tianling Shen wrote:
> > From: David Bauer
> >
> > Enable the USB3 port on the FriendlyARM NanoPi R2S.
> > This is required for the USB3 attached LAN port to work.
> >
> > Signed-off-by: David Bauer
> >
On Mon, Apr 5, 2021 at 4:53 PM Tianling Shen wrote:
>
> Hi Chen-Yu,
>
> On 2021-04-05 16:14, Chen-Yu Tsai wrote:
> >
> > Hi,
> >
> > On Mon, Apr 5, 2021 at 3:46 PM Tianling Shen wrote:
> > >
> > > From: David Bauer
> >
Hi,
On Mon, Apr 5, 2021 at 3:46 PM Tianling Shen wrote:
>
> From: David Bauer
>
> Enable the USB3 port on the FriendlyARM NanoPi R2S.
> This is required for the USB3 attached LAN port to work.
>
> Signed-off-by: David Bauer
> Signed-off-by: Tianling Shen
> ---
>
On Fri, Mar 12, 2021 at 11:52 PM Sebastian Reichel
wrote:
>
> Convert the binding to DT schema format.
>
> Cc: Chen-Yu Tsai
> Signed-off-by: Sebastian Reichel
Looks good to me. Though I'm not well versed in the new YAML binding format yet.
Acked-by: Chen-Yu Tsai
On Wed, Mar 24, 2021 at 4:44 AM Jernej Skrabec wrote:
>
> Beelink X2 has power button. Add node for it.
>
> Signed-off-by: Jernej Skrabec
Acked-by: Chen-Yu Tsai
Hi,
On Tue, Mar 23, 2021 at 9:58 PM Matti Vaittinen
wrote:
>
> Few drivers implement remove call-back only for ensuring a delayed
> work gets cancelled prior driver removal. Clean-up these by switching
> to use devm_delayed_work_autocancel() instead.
>
> This change is compile-tested only. All
Hi,
On Mon, Mar 22, 2021 at 3:38 PM Matti Vaittinen
wrote:
>
> Few drivers implement remove call-back only for ensuring a delayed
> work gets cancelled prior driver removal. Clean-up these by switching
> to use devm_delayed_work_autocancel() instead.
>
> This change is compile-tested only. All
Signed-off-by: Jia-Ju Bai
This should have the tag:
Fixes: 5cc7522d8965 ("media: sun6i: Add support for Allwinner CSI V3s")
Please try to add them when fixing bugs. And this should also be tagged
for stable, so
Cc:
Otherwise,
Acked-by: Chen-Yu Tsai
From: Chen-Yu Tsai
The macros for the clock and reset indices for the RSB hardware block
were replaced with raw numbers when the RSB controller node was added.
This was done to avoid cross-tree dependencies.
Now that both the clk and DT changes have been merged, we can switch
back to using
On Thu, Feb 18, 2021 at 4:06 PM Icenowy Zheng wrote:
>
>
>
> 于 2021年2月18日 GMT+08:00 下午3:58:35, Maxime Ripard 写到:
> >Hi,
> >
> >On Fri, Feb 12, 2021 at 02:57:25PM +0100, Tobias Schramm wrote:
> >> Previously the variable rate audio pll output was fixed to a divider
> >of
> >> four. This is
On Sat, Feb 6, 2021 at 12:21 AM Jernej Škrabec wrote:
>
> Dne petek, 05. februar 2021 ob 17:01:30 CET je Maxime Ripard napisal(a):
> > On Fri, Feb 05, 2021 at 11:21:22AM +0800, Chen-Yu Tsai wrote:
> > > On Fri, Feb 5, 2021 at 2:48 AM Jernej Skrabec
> wrote:
> > >
more pronounced with higher frequencies.
>
> Fix that by allowing max. supported frequency in HW and fix the comment.
>
> Fixes: cd9063757a22 ("drm/sun4i: DW HDMI: Lower max. supported rate for H6")
> Tested-by: Andre Heider
> Signed-off-by: Jernej Skrabec
Reviewed-by: Chen-Yu Tsai
On Fri, Feb 5, 2021 at 2:48 AM Jernej Skrabec wrote:
>
> cpce value for 594 MHz is set differently in BSP driver. Fix that.
>
> Fixes: c71c9b2fee17 ("drm/sun4i: Add support for Synopsys HDMI PHY")
> Tested-by: Andre Heider
> Signed-off-by: Jernej Skrabec
Reviewed-by: Chen-Yu Tsai
Fix that by removing set_rate quirk and always set clock rate.
>
> Fixes: 40bb9d3147b2 ("drm/sun4i: Add support for H6 DW HDMI controller")
> Tested-by: Andre Heider
> Signed-off-by: Jernej Skrabec
Reviewed-by: Chen-Yu Tsai
gt; + val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE;
> +
> + regmap_write(tcon->regs, SUN4I_TCON0_IO_POL_REG, val);
> + } else {
> + val = SUN4I_TCON1_IO_POL_UNKNOWN;
I think a comment for the origin of this is warranted.
Otherwise
> Signed-off-by: Jernej Skrabec
Reviewed-by: Chen-Yu Tsai
ber returned by the platform code is
> > valid, before trying to register the irqchip. If not, we skip this
> > registration, to avoid the driver to bail out completely.
> >
> > Signed-off-by: Andre Przywara
>
> Acked-by: Maxime Ripard
Acked-by: Chen-Yu Tsai
On Thu, Jan 28, 2021 at 1:26 AM Andre Przywara wrote:
>
> Add the obvious compatible name to the existing RSB binding, and pair
> it with the existing A23 fallback compatible string, as the devices are
> compatible.
>
> Signed-off-by: Andre Przywara
Acked-by: Chen-Yu Tsai
Hi,
On Thu, Jan 28, 2021 at 1:26 AM Andre Przywara wrote:
>
> The AXP305 PMIC used in AXP805 seems to be fully compatible to the
^
This statement doesn't quite make sense. I assume you wanted to mention
a board or the H616 SoC here?
> AXP805 PMIC, so add the proper
Hi,
On Sun, Jan 31, 2021 at 12:54 AM Corentin Labbe
wrote:
>
> Hello
>
> When booting next-20210128, I got the following warning on by bpim3
> 6.148421] [ cut here ]
> [6.153145] WARNING: CPU: 2 PID: 57 at drivers/thermal/thermal_core.c:563
>
On Mon, Jan 25, 2021 at 6:56 PM Maxime Ripard wrote:
>
> On Sat, Jan 23, 2021 at 12:26:26AM -0600, Samuel Holland wrote:
> > On 1/22/21 4:47 AM, Maxime Ripard wrote:
> > > On Thu, Jan 21, 2021 at 07:33:54PM -0600, Samuel Holland wrote:
> > >> On 1/21/21 2:35 PM, Marc Zyngier wrote:
> > >>> On
On Sun, Jan 24, 2021 at 11:24 PM Samuel Holland wrote:
>
> The IRQ handler calls mod_delayed_work() on power->vbus_detect. However,
> that work item is not initialized until after the IRQs are enabled. If
> an IRQ is already pending when the driver is probed, the driver calls
> mod_delayed_work()
On Fri, Jan 22, 2021 at 3:54 AM Jernej Škrabec wrote:
>
> Dne četrtek, 21. januar 2021 ob 18:08:36 CET je Hermann Lauer napisal(a):
> > BPi Pro needs TX and RX delay for Gbit to work reliable and avoid high
> > packet loss rates. The realtek phy driver overrides the settings of the
> > pull ups
From: Chen-Yu Tsai
The NanoPi M4B is a minor revision of the original M4.
The differences against the original Nanopi M4 that are common with the
other M4V2 revision include:
- microphone header removed
- power button added
- recovery button added
Additional changes specific to the M4B
From: Chen-Yu Tsai
Only the NanoPC T4 hs the PCIe reset pin routed to the SoC. For the
NanoPi M4 family, no such signal is routed to the expansion header on
the base board.
As the schematics for the expansion board were not released, it is
unclear how this is handled, but the likely answer
From: Chen-Yu Tsai
The NanoPi M4B is a minor revision of the original M4.
The differences against the original Nanopi M4 that are common with the
other M4V2 revision include:
- microphone header removed
- power button added
- recovery button added
Additional changes specific to the M4B
From: Chen-Yu Tsai
Hi everyone,
This is v4 of my Nanopi M4B series.
Changes since v3 include:
- Directly return dev_err_probe() instead of having a separate return
statement
Changes since v2 include:
- Replaced dev_err() with dev_err_probe() for gpiod_get_optional() error
- Added
From: Chen-Yu Tsai
The Rockchip PCIe controller DT binding clearly states that 'ep-gpios' is
an optional property. And indeed there are boards that don't require it.
Make the driver follow the binding by using devm_gpiod_get_optional()
instead of devm_gpiod_get().
Fixes: e77f847df54c (&quo
On Thu, Jan 21, 2021 at 12:30 PM Lindsey Stanpoor
wrote:
>
> On Fri, Nov 6, 2020 at 11:42 PM Felipe Balbi wrote:
> >
> >
> > Hi,
> >
> > Lindsey Stanpoor writes:
> > > On Wed, Sep 2, 2020 at 11:12 AM wrote:
> > >>
> > >> From: Cameron Nemo
> > >>
> > >> Document compatible for dwc3 on the
On Tue, Jan 19, 2021 at 5:11 PM Heiko Stübner wrote:
>
> Am Mittwoch, 6. Januar 2021, 14:46:14 CET schrieb Chen-Yu Tsai:
> > From: Chen-Yu Tsai
> >
> > The Rockchip PCIe controller DT binding clearly states that 'ep-gpios' is
> > an optional property. And inde
Hi,
On Wed, Jan 6, 2021 at 9:46 PM Chen-Yu Tsai wrote:
>
> From: Chen-Yu Tsai
>
> Hi everyone,
>
> This is v3 of my Nanopi M4B series. Changes since v2 include:
>
> - Replaced dev_err() with dev_err_probe() for gpiod_get_optional() error
> - Added Reviewed-by tag
On Mon, Jan 18, 2021 at 11:53 PM Andre Przywara wrote:
>
> On Mon, 18 Jan 2021 14:28:54 +0100
> Maxime Ripard wrote:
>
> Hi Maxime,
>
> > On Mon, Jan 18, 2021 at 02:08:29AM +, Andre Przywara wrote:
> > > From: Yangtao Li
> > >
> > > This patch adds support for A100 MMC controller, which use
On Wed, Jan 13, 2021 at 5:16 PM Chen-Yu Tsai wrote:
>
> On Thu, Jan 7, 2021 at 6:27 PM Samuel Holland wrote:
> >
> > On 1/6/21 5:38 AM, Chen-Yu Tsai wrote:
> > > On Wed, Jan 6, 2021 at 7:06 PM Maxime Ripard wrote:
> > >>
> > >> On Mon, Jan
On Wed, Dec 30, 2020 at 11:29 AM Chen-Yu Tsai wrote:
>
> On Tue, Dec 22, 2020 at 4:17 PM Jernej Škrabec
> wrote:
> >
> > Hi!
> >
> > Dne petek, 18. december 2020 ob 20:50:33 CET je Paul Kocialkowski
> > napisal(a):
> > > This adds a device-tree d
From: Chen-Yu Tsai
Radxa ROCK Pi E is a router oriented SBC based on Rockchip's RK3328 SoC.
As the official wiki page puts it, "E for Ethernets".
It features the RK3328 SoC, gigabit and fast Ethernet RJ45 ports, both
directly served by Ethernet controllers in the SoC, a USB 3.0
From: Chen-Yu Tsai
The gmac2phy is integrated with the PHY within the SoC. Any properties
related to this integration can be included in the .dtsi file, instead
of having board dts files specify them separately.
Add the clock_in_out property to specify the direction of the PHY clock
From: Chen-Yu Tsai
Hi everyone,
This is v2 of my ROCK Pi E support series.
Changes since v1:
- Picked up Rob's Ack for the binding
- Dropped comment about LED color
- Dropped max-frequency from emmc node
- Changed pingroup name from "ethernet-phy" to "ephy" to avoid DT bin
From: Chen-Yu Tsai
Radxa ROCK Pi E is a router oriented SBC based on Rockchip's RK3328 SoC.
As the official wiki page puts it, "E for Ethernets".
It features the RK3328 SoC, gigabit and fast Ethernet RJ45 ports, both
directly served by Ethernet controllers in the SoC, a USB 3.0
On Sat, Jan 16, 2021 at 6:37 PM Jernej Skrabec wrote:
>
> Bluetooth module on BananaPi M2 Zero can also be used for streaming
> audio. However, for that case higher UART speed is required.
>
> Add a max-speed property.
>
> Signed-off-by: Jernej Skrabec
Acked-by: Chen-Yu Tsai
On Sat, Jan 16, 2021 at 6:52 PM Jernej Skrabec wrote:
>
> Bluetooth module on BananaPi M2 Plus can also be used for streaming
> audio. However, for that case higher UART speed is required.
>
> Add a max-speed property.
>
> Signed-off-by: Jernej Skrabec
Acked-by: Chen-Yu Tsai
On Thu, Jan 7, 2021 at 6:27 PM Samuel Holland wrote:
>
> On 1/6/21 5:38 AM, Chen-Yu Tsai wrote:
> > On Wed, Jan 6, 2021 at 7:06 PM Maxime Ripard wrote:
> >>
> >> On Mon, Jan 04, 2021 at 10:54:19AM +, André Przywara wrote:
> >>> On 03/01/2021 10:
On Mon, Jan 11, 2021 at 5:16 AM Jernej Skrabec wrote:
>
> PineH64 model B has wifi+bt combo module. Wifi is already supported, so
> lets add also bluetooth node.
>
> Signed-off-by: Jernej Skrabec
Acked-by: Chen-Yu Tsai
Looks good to me, though I couldn't find anything
On Wed, Jan 6, 2021 at 9:46 PM Chen-Yu Tsai wrote:
>
> From: Chen-Yu Tsai
>
> The NanoPi M4B is a minor revision of the original M4.
>
> The differences against the original Nanopi M4 that are common with the
> other M4V2 revision include:
>
> - microphone header
On Mon, Jan 11, 2021 at 3:50 PM Heiko Stübner wrote:
>
> Am Montag, 11. Januar 2021, 04:27:47 CET schrieb Chen-Yu Tsai:
> > On Mon, Jan 11, 2021 at 4:06 AM Heiko Stübner wrote:
> > >
> > > Hi,
> > >
> > > Am Sonntag, 10. Januar 2021, 16:37:15 CE
Hi Rob,
On Mon, Jan 11, 2021 at 3:50 AM Johan Jonker wrote:
>
> A test with the command below gives this error:
> /arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dt.yaml:
> ethernet-phy: 'reg' is a required property
>
> The pinctrl nodename "ethernet-phy" conflicts with the rules
> in the
On Mon, Jan 11, 2021 at 4:17 AM Johan Jonker wrote:
>
> Hi Chen-Yu,
>
> Most is already answered by Heiko.
>
> On 1/10/21 4:37 PM, Chen-Yu Tsai wrote:
> > Hi,
> >
> > On Sun, Jan 10, 2021 at 10:45 PM Johan Jonker wrote:
> >>
> >> Hi Chen-Yu
On Mon, Jan 11, 2021 at 4:06 AM Heiko Stübner wrote:
>
> Hi,
>
> Am Sonntag, 10. Januar 2021, 16:37:15 CET schrieb Chen-Yu Tsai:
> > > > + vcc_sd: sdmmc-regulator {
> > > > + compatible = "regulator-fixed";
> &g
Hi,
On Sun, Jan 10, 2021 at 10:45 PM Johan Jonker wrote:
>
> Hi Chen-Yu,
>
> Some comments, have a look if it is useful...
>
> On 1/10/21 4:58 AM, Chen-Yu Tsai wrote:
> > From: Chen-Yu Tsai
> >
> > Radxa ROCK Pi E is a router oriented SBC based on Rockchip's
From: Chen-Yu Tsai
Radxa ROCK Pi E is a router oriented SBC based on Rockchip's RK3328 SoC.
As the official wiki page puts it, "E for Ethernets".
It features the RK3328 SoC, gigabit and fast Ethernet RJ45 ports, both
directly served by Ethernet controllers in the SoC, a USB 3.0
From: Chen-Yu Tsai
The gmac2phy is integrated with the PHY within the SoC. Any properties
related to this integration can be included in the .dtsi file, instead
of having board dts files specify them separately.
Add the clock_in_out property to specify the direction of the PHY clock
From: Chen-Yu Tsai
Hi everyone,
This series adds support for the Radxa ROCK Pi E. This is a router
oriented SBC based on Rockchip's RK3328 SoC. As the official wiki page
puts it, "E for Ethernets".
It features the RK3328 SoC, gigabit and fast Ethernet RJ45 ports, both
direc
From: Chen-Yu Tsai
Radxa ROCK Pi E is a router oriented SBC based on Rockchip's RK3328 SoC.
As the official wiki page puts it, "E for Ethernets".
It features the RK3328 SoC, gigabit and fast Ethernet RJ45 ports, both
directly served by Ethernet controllers in the SoC, a USB 3.0
From: Chen-Yu Tsai
The custom regulatory ruleset in the rtl8723bs driver lists an incorrect
number of rules: one too many. This results in an out-of-bounds access,
as detected by KASAN. This was possible thanks to the newly added support
for KASAN on ARMv7.
Fix this by filling in the correct
From: Chen-Yu Tsai
Hi everyone,
This is v3 of my Nanopi M4B series. Changes since v2 include:
- Replaced dev_err() with dev_err_probe() for gpiod_get_optional() error
- Added Reviewed-by tag from Robin Murphy for patch 3
Changes since v1 include:
- Rewrite subject of patch 1 to match
From: Chen-Yu Tsai
The Rockchip PCIe controller DT binding clearly states that 'ep-gpios' is
an optional property. And indeed there are boards that don't require it.
Make the driver follow the binding by using devm_gpiod_get_optional()
instead of devm_gpiod_get().
Fixes: e77f847df54c (&quo
From: Chen-Yu Tsai
The NanoPi M4B is a minor revision of the original M4.
The differences against the original Nanopi M4 that are common with the
other M4V2 revision include:
- microphone header removed
- power button added
- recovery button added
Additional changes specific to the M4B
From: Chen-Yu Tsai
The NanoPi M4B is a minor revision of the original M4.
The differences against the original Nanopi M4 that are common with the
other M4V2 revision include:
- microphone header removed
- power button added
- recovery button added
Additional changes specific to the M4B
From: Chen-Yu Tsai
Only the NanoPC T4 hs the PCIe reset pin routed to the SoC. For the
NanoPi M4 family, no such signal is routed to the expansion header on
the base board.
As the schematics for the expansion board were not released, it is
unclear how this is handled, but the likely answer
On Wed, Jan 6, 2021 at 6:50 PM Maxime Ripard wrote:
>
> Hi!
>
> On Sun, Jan 03, 2021 at 05:06:31AM -0600, Samuel Holland wrote:
> > This series adds system (complete power down) and runtime (clock gate)
> > PM hooks to the RSB controller driver. Tested on A64 and H6.
> >
> > Samuel Holland (4):
>
On Wed, Jan 6, 2021 at 7:06 PM Maxime Ripard wrote:
>
> On Mon, Jan 04, 2021 at 10:54:19AM +, André Przywara wrote:
> > On 03/01/2021 10:00, Samuel Holland wrote:
> > > On boards where the only peripheral connected to PL0/PL1 is an X-Powers
> > > PMIC, configure the connection to use the RSB
".
>
> Signed-off-by: Samuel Holland
Reviewed-by: Chen-Yu Tsai
On Sun, Jan 3, 2021 at 7:25 PM Samuel Holland wrote:
>
> Adjust the spacing and use an explicit "return 0" in the success path
> to make the function easier to parse.
>
> Signed-off-by: Samuel Holland
Reviewed-by: Chen-Yu Tsai
On Sun, Jan 3, 2021 at 7:25 PM Samuel Holland wrote:
>
> sun8i_dwmac_unpower_internal_phy already checks if the PHY is powered,
> so there is no need to do it again here.
>
> Signed-off-by: Samuel Holland
Reviewed-by: Chen-Yu Tsai
On Sun, Jan 3, 2021 at 7:25 PM Samuel Holland wrote:
>
> Use the appropriate function instead of reimplementing it,
> and update the error message to match the code.
>
> Signed-off-by: Samuel Holland
Reviewed-by: Chen-Yu Tsai
On Sun, Jan 3, 2021 at 7:25 PM Samuel Holland wrote:
>
> This is a deinitialization function that always returned zero, and that
> return value was always ignored. Have it return void instead.
>
> Signed-off-by: Samuel Holland
Reviewed-by: Chen-Yu Tsai
On Wed, Jan 6, 2021 at 6:35 AM Linus Walleij wrote:
>
> On Sun, Jan 3, 2021 at 11:00 AM Samuel Holland wrote:
>
> > As there is an RSB controller in the H6 SoC, there should be some pin
> > configuration for it. While no such configuration is documented, the
> > "s_i2c" pins are suspiciously on
: stmmac: Add dwmac-sun8i")
> Fixes: 40a1dcee2d18 ("net: ethernet: dwmac-sun8i: Use the correct function in
> exit path")
> Signed-off-by: Samuel Holland
Reviewed-by: Chen-Yu Tsai
gt; removal callback. Also ensure the EPHY is powered down before removal.
>
> Fixes: 634db83b8265 ("net: stmmac: dwmac-sun8i: Handle integrated/external
> MDIOs")
> Signed-off-by: Samuel Holland
Reviewed-by: Chen-Yu Tsai
letions(-)
Looks good to me.
Acked-by: Chen-Yu Tsai
I already queued them up locally, but I think it's best to give other
people some time to review as well.
ChenYu
e pushed
out until that happens.
Regarding patch 3, I replaced the clock and reset macros with raw
numbers to get rid of cross-tree dependencies. The following fix
will be posted for v5.12 later on during its RC cycle.
>8 ----
commit 0b4781666adc5e
th no
> primary function 2 given. This suggests the primary function for these
> pins is actually RSB, and that is indeed the case.
>
> Add the "s_rsb" pin functions so the RSB controller can be used.
>
> Signed-off-by: Samuel Holland
Acked-by: Chen-Yu Tsai
On Tue, Dec 29, 2020 at 11:42 PM Dylan Van Assche
wrote:
>
> All revisions of the PinePhone share most of the hardware.
> This patch makes it easier to detect PinePhone hardware without
> having to check for each possible revision.
Sounds good.
> Signed-off-by: Dylan Van Assche
> ---
>
On Tue, Dec 22, 2020 at 4:17 PM Jernej Škrabec wrote:
>
> Hi!
>
> Dne petek, 18. december 2020 ob 20:50:33 CET je Paul Kocialkowski napisal(a):
> > This adds a device-tree definition for the CSI0 MCLK pin,
> > which can be used for feeding MIPI CSI-2 sensors.
> >
> > Signed-off-by: Paul
On Mon, Dec 28, 2020 at 4:03 AM Jernej Škrabec wrote:
>
> Hi!
>
> Dne nedelja, 27. december 2020 ob 21:00:00 CET je Corentin Labbe napisal(a):
> > Lot of sunxi boards have BRCM wireless device, so let's enable necessary
> > options for it in our defconfig.
>
> Idea is good but modules (=m)
On Wed, Dec 16, 2020 at 4:16 AM Christophe JAILLET
wrote:
>
> Le 15/12/2020 à 20:35, Dan Carpenter a écrit :
> > On Tue, Dec 15, 2020 at 08:08:15PM +0100, Maxime Ripard wrote:
> >> On Tue, Dec 15, 2020 at 07:18:48PM +0100, Christophe JAILLET wrote:
> >>> Le 15/12/2020 à 12:37, Maxime Ripard a
On Mon, Dec 14, 2020 at 8:53 PM Andre Przywara wrote:
>
> On Mon, 14 Dec 2020 10:58:31 +0100
> Maxime Ripard wrote:
>
> Hi,
>
> > On Fri, Dec 11, 2020 at 01:19:32AM +, Andre Przywara wrote:
> > > + reserved-memory {
> > > + #address-cells = <2>;
> > > + #size-cells =
On Mon, Dec 14, 2020 at 12:28 AM Icenowy Zheng wrote:
>
> 在 2020-12-02星期三的 13:54 +，Andre Przywara写道：
> > Port A is used for an internal connection to some analogue circuitry
> > which looks like an AC200 IP (as in the H6), though this is not
> > mentioned in the manual.
>
> When developing
On Mon, Dec 7, 2020 at 10:11 PM Rob Herring wrote:
>
> On Wed, Nov 18, 2020 at 1:17 AM Chen-Yu Tsai wrote:
> >
> > From: Chen-Yu Tsai
> >
> > The Rockchip PCIe controller DT binding clearly states that 'ep-gpios' is
> > an optional property. And indeed
On Mon, Dec 7, 2020 at 5:20 PM Shuosheng Huang
wrote:
>
> Add an Operating Performance Points table for the CPU cores to
> enable Dynamic Voltage & Frequency Scaling on the A100.
>
> Signed-off-by: Shuosheng Huang
> ---
> .../allwinner/sun50i-a100-allwinner-perf1.dts | 5 ++
>
Ping
On Wed, Nov 18, 2020 at 4:49 PM Heiko Stübner wrote:
>
> Am Mittwoch, 18. November 2020, 08:17:21 CET schrieb Chen-Yu Tsai:
> > From: Chen-Yu Tsai
> >
> > The Rockchip PCIe controller DT binding clearly states that 'ep-gpios' is
> > an optional propert
On Sat, Dec 5, 2020 at 1:40 AM Mark Brown wrote:
>
> On Fri, Dec 04, 2020 at 10:34:21AM +0800, Chen-Yu Tsai wrote:
> > On Thu, Dec 3, 2020 at 12:11 AM Mark Brown wrote:
>
> > > No, no sign. You can check if things are at least hitting the list at:
>
> > &
From: Chen-Yu Tsai
For UARTs, the local pull-ups should be on the RX pin, not the TX pin.
UARTs transmit active-low, so a disconnected RX pin should be pulled
high instead of left floating to prevent noise being interpreted as
transmissions.
This gets rid of bogus sysrq events when the UART
On Fri, Dec 4, 2020 at 2:15 AM Martin Cerveny wrote:
>
> VideoEngine (cedrus) needs assign dedicated SRAM for decoding.
> SRAM_C1 is usually used for Allwinner platforms.
> Allwinner V3s scale down chip has not SRAM_C1 but only small SRAM_C (44kB).
>
> Result of additional testing:
>
> SRAM_C is
On Thu, Dec 3, 2020 at 12:11 AM Mark Brown wrote:
>
> On Thu, Dec 03, 2020 at 12:04:05AM +0800, dinghua ma wrote:
> > I sent a new email. I don’t know if you received it. The subject is "[PATCH
> > v3] regulator: axp20x: Fix DLDO2 voltage control register mask for AXP22x"
>
> No, no sign. You
On Fri, Dec 4, 2020 at 12:25 AM Martin Cerveny wrote:
>
> Hello.
>
> On Thu, 3 Dec 2020, Chen-Yu Tsai wrote:
>
> > Hi,
> >
> > On Mon, Nov 16, 2020 at 8:57 PM Martin Cerveny
> > wrote:
> >>
> >> Allwinner V3s has system control and SRAM
On Thu, Dec 3, 2020 at 11:45 PM André Przywara wrote:
>
> On 03/12/2020 15:02, Chen-Yu Tsai wrote:
> > On Thu, Dec 3, 2020 at 6:54 PM André Przywara
> > wrote:
> >>
> >> On 03/12/2020 03:16, Samuel Holland wrote:
> >>
> >> H
On Thu, Dec 3, 2020 at 6:54 PM André Przywara wrote:
>
> On 03/12/2020 03:16, Samuel Holland wrote:
>
> Hi,
>
> > On 12/2/20 7:54 AM, Andre Przywara wrote:
> > ...
> >> +soc {
> >> +compatible = "simple-bus";
> >> +#address-cells = <1>;
> >> +#size-cells =
Hi,
On Mon, Nov 16, 2020 at 8:57 PM Martin Cerveny wrote:
>
> Allwinner V3s has system control and SRAM C1 region similar to H3.
>
> Signed-off-by: Martin Cerveny
> ---
> arch/arm/boot/dts/sun8i-v3s.dtsi | 14 ++
> 1 file changed, 14 insertions(+)
>
> diff --git
From: Chen-Yu Tsai
Now that driver support for the RK3328's audio codec, and the plumbing
is defined at the SoC level, we can enable analog audio at the board
level.
Enable analog audio by enabling the codec and the I2S interface
connected and the simple-audio-card that binds them together
From: Chen-Yu Tsai
The RK3328-ROC-CC already has HDMI display output enabled. Now that
audio for the HDMI controller is supported, it can be enabled as well.
Enable the simple-audio-card, and the I2S interface the audio is fed
from.
Signed-off-by: Chen-Yu Tsai
---
arch/arm64/boot/dts
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