On 12.04.2021 19:02, Rob Herring wrote:
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> On Fri, Apr 09, 2021 at 02:13:37PM +0300, Claudiu Beznea wrote:
>> Add RAM controller and RAM PHY controller DT bindings.
>>
>> Signed-off-by: Claudiu Beznea
On 12.04.2021 21:29, Bartosz Golaszewski wrote:
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> On Mon, Apr 12, 2021 at 9:42 AM wrote:
>>
>> On 07.04.2021 21:37, Bartosz Golaszewski wrote:
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On 07.04.2021 21:37, Bartosz Golaszewski wrote:
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> On Fri, Apr 2, 2021 at 3:24 PM Claudiu Beznea
> wrote:
>>
>> Some EEPROMs could be used only for MAC storage. In this case the
>> EEPROM areas where
On 09.04.2021 11:25, Tudor Ambarus wrote:
> The slew rate was enabled by default for each configuration of the
> pin. In case the pin had more than one configuration, even if
> we set the slew rate as disabled in the device tree, the next pin
> configuration would set again the slew rate enabled by
On 31.03.2021 11:18, Nicolas Ferre wrote:
> On 09/02/2021 at 12:01, Claudiu Beznea wrote:
>> Free resources on exit path (failure path of probe and remove).
>
> I'm not sure we can use this driver as a module anyway.
>
> Otherwise, it looks fine, but isn't it possible to use devm_of_iomap(),
> ev
On 01.04.2021 17:42, Claudiu Beznea - M18063 wrote:
> On 31.03.2021 11:18, Nicolas Ferre wrote:
>> On 09/02/2021 at 12:01, Claudiu Beznea wrote:
>>> Free resources on exit path (failure path of probe and remove).
>>
>> I'm not sure we can use this driver as a module anyway.
>>
>> Otherwise, it look
On 01.04.2021 12:38, Claudiu Beznea - M18063 wrote:
> On 31.03.2021 19:01, Alexandre Belloni wrote:
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>> On 31/03/2021 13:59:06+0300, Claudiu Beznea wrote:
>>> From: Eugen Hristev
>>>
>>> Introduce n
On 31.03.2021 19:01, Alexandre Belloni wrote:
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> On 31/03/2021 13:59:06+0300, Claudiu Beznea wrote:
>> From: Eugen Hristev
>>
>> Introduce new family of SoCs, sama7, and first SoC, sama7g5.
>>
>> Sign
On 31.03.2021 18:54, Alexandre Belloni wrote:
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> On 31/03/2021 13:58:54+0300, Claudiu Beznea wrote:
>> Add SFRBU registers definitions for SAMA7G5.
>>
>> Signed-off-by: Claudiu Beznea
>> ---
>> inclu
On 30.03.2021 20:14, Nicolas Ferre wrote:
> On 24/03/2021 at 10:43, Claudiu Beznea wrote:
>> SAMA5D2 and SAMA7G5 have a special power saving mode (backup mode) where
>> most of the SoC's components are powered off (including PMC). Resuming
>> from this mode is done with the help of bootloader. Peri
Hi Andreas,
On 08.03.2021 21:30, Andreas Schwab wrote:
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> One of the changes to the macb driver between 5.10 and 5.11 has broken
> the SiFive HiFive Unleashed. These are the last messages before the
Hi Mark,
Appologies for late reply, I had to double check some of your questions w/
IP designer.
On 02.03.2021 14:02, Marc Zyngier wrote:
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> On Tue, 02 Mar 2021 10:28:46 +,
> Claudiu Beznea wrot
On 02.03.2021 13:32, Marc Zyngier wrote:
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> On Tue, 02 Mar 2021 10:28:45 +,
> Claudiu Beznea wrote:
>>
>> Add DT bindings for Microchip External Interrupt Controller.
>>
>> Signed-off-by: Claudiu
Hi, Rafael, Pavel,
I know you may be busy. Just a gentle ping on this topic. It would be nice
to have your input in this.
Thank you,
Claudiu Beznea
On 14.01.2021 13:05, Heiner Kallweit wrote:
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> On
On 04.02.2021 18:01, Arnd Bergmann wrote:
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> From: Arnd Bergmann
>
> Compiling with the clang integrated assembler warns about
> a recently added instruction:
>
> :14:13: error: unknown token in e
On 22.01.2021 13:20, Michael Walle wrote:
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> Am 2021-01-22 10:10, schrieb claudiu.bez...@microchip.com:
>> On 21.01.2021 11:41, Michael Walle wrote:
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On 21.01.2021 11:41, Michael Walle wrote:
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> Hi Claudiu,
>
> Am 2021-01-21 10:19, schrieb claudiu.bez...@microchip.com:
>> On 20.01.2021 21:43, Michael Walle wrote:
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Hi Michael,
On 20.01.2021 21:43, Michael Walle wrote:
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> If the MII interface is used, the PHY is the clock master, thus don't
> set the clock rate. On Zynq-7000, this will prevent the following
> war
On 14.01.2021 12:25, Russell King - ARM Linux admin wrote:
>
> As I've said, if phylib/PHY driver is not restoring the state of the
> PHY on resume from suspend-to-ram, then that's an issue with phylib
> and/or the phy driver.
In the patch I proposed in this thread the restoring is done in PHY
Hi, Rafael, Pavel,
I recently posted a patch for re-configuring an ethernet PHY on its
.resume() callback as this PHY is in a setup with SAMA7G5 SoC that supports
a power saving mode (called backup). In this power saving mode most of the
SoC devices' power is cut of (except the RAM + its controlle
On 13.01.2021 13:09, Heiner Kallweit wrote:
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> On 13.01.2021 10:29, claudiu.bez...@microchip.com wrote:
>> Hi Heiner,
>>
>> On 08.01.2021 18:31, Heiner Kallweit wrote:
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Hi Heiner,
On 08.01.2021 18:31, Heiner Kallweit wrote:
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> On 08.01.2021 16:45, Claudiu Beznea wrote:
>> KSZ9131 is used in setups with SAMA7G5. SAMA7G5 supports a special
>> power saving mode (backup
On 05.01.2021 12:44, Viresh Kumar wrote:
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> On 05-01-21, 12:22, Claudiu Beznea wrote:
>> Microchip SAMA7G5 devices supports runtime changes of CPU frequency.
>> This is doable by changing CPUPLL freq
Hi Charles,
On 04.01.2021 12:38, Charles Keepax wrote:
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> A new flag MACB_CAPS_CLK_HW_CHG was added and all callers of
> macb_set_tx_clk were gated on the presence of this flag.
>
> - if (!clk)
> +
On 16.12.2020 15:45, Alexandre Belloni wrote:
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> On 16/12/2020 14:57:33+0200, Claudiu Beznea wrote:
>> Add support for SAMA7G5 by adding proper struct reg_config structure
>> and since SAMA7G5 is not
On 16.12.2020 15:45, Alexandre Belloni wrote:
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> On 16/12/2020 14:57:33+0200, Claudiu Beznea wrote:
>> Add support for SAMA7G5 by adding proper struct reg_config structure
>> and since SAMA7G5 is not
Hi Andrew,
On 05.12.2020 16:30, Andrew Lunn wrote:
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> On Fri, Dec 04, 2020 at 02:34:17PM +0200, Claudiu Beznea wrote:
>> Unprepare clocks in case of any failure in fu540_c000_clk_init().
>
> Hi Claud
On 02.12.2020 14:58, Alexandre Belloni wrote:
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> The sam9x60 doesn't have the MOSCXTBY bit to enable the crystal oscillator
> bypass.
>
> Fixes: 01e2113de9a5 ("clk: at91: add sam9x60 pmc driver")
>
I have just noticed that the title of this cover letter is wrong.
It should have been:
"clk: at91: adapt for dvfs"
Please let me know if you want me to send a new version for this update.
Thank you,
Claudiu
On 19.11.2020 17:43, Claudiu Beznea wrote:
> Hi,
>
> SAMA7G5 is capable of DVFS. The su
On 24.11.2020 15:41, Jon Hunter wrote:
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> On 24/11/2020 11:14, claudiu.bez...@microchip.com wrote:
>
> ...
>
>> I would say that a solution would be to have a new helper to retrieve the
>> linear_m
Hi Jon,
On 24.11.2020 11:36, Jon Hunter wrote:
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> On 13/11/2020 15:21, Claudiu Beznea wrote:
>> There are regulators who's min selector is not zero. Selectors loops
>> (looping b/w zero and regulator:
On 18.11.2020 03:49, Stephen Boyd wrote:
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> Quoting claudiu.bez...@microchip.com (2020-11-16 03:24:54)
>>
>>
>> On 14.11.2020 23:14, Stephen Boyd wrote:
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On 14.11.2020 23:14, Stephen Boyd wrote:
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> Quoting Claudiu Beznea (2020-11-06 01:46:23)
>> diff --git a/drivers/clk/at91/clk-sam9x60-pll.c
>> b/drivers/clk/at91/clk-sam9x60-pll.c
>> index 78f458a7b
Hi,
Please ignore this series for the moment as I will have to run few more
tests on it. Sorry for the noise!
Thank you,
Claudiu Beznea
On 04.11.2020 19:45, Claudiu Beznea wrote:
> Hi,
>
> SAMA7G5 is capable of DVFS. The supported CPU clock frequencies could be
> obtained from CPU PLL. The hard
Hi Dinghao,
On 20.08.2020 08:52, Dinghao Liu wrote:
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> When devm_clk_get() returns -EPROBE_DEFER, spi_priv
> should be freed just like when wilc_cfg80211_init()
> fails.
>
> Fixes: 854d66df74aed ("st
On 20.08.2020 08:48, Dinghao Liu wrote:
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> When devm_clk_get() returns -EPROBE_DEFER, sdio_priv
> should be freed just like when wilc_cfg80211_init()
> fails.
>
> Fixes: 8692b047e86cf ("staging: wil
On 04.08.2020 14:56, Alexandre Belloni wrote:
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> cpu_do_idle() is already the default action for arm_pm_idle, there is no
> need to open code it.
>
> Signed-off-by: Alexandre Belloni
Reviewed-by:
On 04.08.2020 18:08, Alexandre Belloni wrote:
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> On 04/08/2020 15:00:38+, claudiu.bez...@microchip.com wrote:
>>
>>
>> On 04.08.2020 14:42, Alexandre Belloni wrote:
>>> EXTERNAL EMAIL: Do not cli
On 04.08.2020 14:42, Alexandre Belloni wrote:
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> Hello,
>
> On 04/08/2020 14:07:37+0300, Claudiu Beznea wrote:
>> void __init at91rm9200_pm_init(void)
>> {
>> + static const int modes[] __init
On 03.08.2020 19:11, Codrin Ciubotariu - M19940 wrote:
> On 03.08.2020 16:06, Claudiu Beznea - M18063 wrote:
>>
>>
>> On 03.08.2020 11:18, Codrin Ciubotariu wrote:
>>> The new SPDIF TX controller is a serial port compliant with the IEC-
>>> 60958 standard. It also supports programmable User Data
On 03.08.2020 19:11, Codrin Ciubotariu - M19940 wrote:
> On 03.08.2020 16:06, Claudiu Beznea - M18063 wrote:
>>
>>
>> On 03.08.2020 11:18, Codrin Ciubotariu wrote:
>>> The new SPDIF TX controller is a serial port compliant with the IEC-
>>> 60958 standard. It also supports programmable User Data
On 03.08.2020 11:18, Codrin Ciubotariu wrote:
> The new SPDIF TX controller is a serial port compliant with the IEC-
> 60958 standard. It also supports programmable User Data and Channel
> Status fields.
>
> This IP is embedded in Microchip's sama7g5 SoC.
>
> Signed-off-by: Codrin Ciubotariu
>
On 03.08.2020 11:34, Alexandre Belloni wrote:
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> On 03/08/2020 10:25:16+0300, Claudiu Beznea wrote:
>> Not all SoCs supports all the PM mode. User may end up settings,
>> e.g. backup mode, on a non S
On 23.07.2020 21:59, Florian Fainelli wrote:
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> On 7/21/20 10:13 AM, Codrin Ciubotariu wrote:
>> The MACB embeds an MDIO bus controller. For this reason, the PHY nodes
>> were represented as sub-node
On 22.07.2020 17:43, claudiu.bez...@microchip.com wrote:
>
>
> On 22.07.2020 16:44, cristian.bir...@microchip.com wrote:
>> From: Claudiu Beznea
>>
>> Instead of trying to match every possible compatible use
>> of_find_matching_node_and_match() and pass the compatible array.
>>
>> Signed-off-b
On 22.07.2020 14:38, Codrin Ciubotariu - M19940 wrote:
> On 22.07.2020 13:32, Claudiu Beznea - M18063 wrote:
>>
>>
>> On 21.07.2020 20:13, Codrin Ciubotariu wrote:
>>> Adding the PHY nodes directly under the Ethernet node became deprecated,
>>> so the aim of this patch series is to make MACB use
On 22.07.2020 16:44, cristian.bir...@microchip.com wrote:
> From: Claudiu Beznea
>
> Instead of trying to match every possible compatible use
> of_find_matching_node_and_match() and pass the compatible array.
>
> Signed-off-by: Claudiu Beznea
> ---
> drivers/usb/gadget/udc/atmel_usba_udc.c |
On 21.07.2020 20:13, Codrin Ciubotariu wrote:
> Adding the PHY nodes directly under the Ethernet node became deprecated,
> so the aim of this patch series is to make MACB use an MDIO node as
> container for MDIO devices.
> This patch series starts with a small patch to use the device-managed
> de
On 17.07.2020 18:07, Alexandre Belloni wrote:
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>
> Hi,
>
> On 15/07/2020 14:24:18+0300, Claudiu Beznea wrote:
>> Replace conditional operator with double logical not.
>
> I think you need to elaborat
On 17.07.2020 12:12, Alexandre Belloni wrote:
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> On 15/07/2020 14:24:15+0300, Claudiu Beznea wrote:
>> In commit a436c2a447e59 ("clk: at91: add sam9x60 PLL driver")
>> the fractional part of PLL wasn
On 15.07.2020 14:24, Claudiu Beznea wrote:
> Register slow rc with accuracy option.
>
> Fixes: 04bcc4275e601 ("clk: at91: sckc: add support for SAM9X60")
> Signed-off-by: Claudiu Beznea
> ---
> drivers/clk/at91/sckc.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git
Hi Nicolas,
On 13.07.2020 13:05, nicolas.fe...@microchip.com wrote:
> From: Nicolas Ferre
>
> Adapt the Wake-on-Lan feature to the Cadence GEM Ethernet controller.
> This controller has different register layout and cannot be handled by
> previous code.
> We disable completely interrupts on all
On 27.06.2020 00:03, Alexandre Belloni wrote:
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> On 25/06/2020 13:09:28+0300, Claudiu Beznea wrote:
>> Return in clk_main_osc_prepare()/clk_main_rc_osc_prepare() if
>> oscillators are already enabled
Hi Andrew, Florian,
On 30.06.2020 06:35, Florian Fainelli wrote:
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> On 6/29/2020 5:45 PM, Andrew Lunn wrote:
>> On Mon, Jun 29, 2020 at 10:26:36AM +0300, Claudiu Beznea wrote:
>>> In case of_mdiobus_r
Please ignore this one!
I'll send a v2.
On 24.06.2020 10:26, Claudiu Beznea wrote:
> DMA buffers were not freed on failure path of at91ether_open().
> Along with changes for freeing the DMA buffers the enable/disable
> interrupt instructions were moved to at91ether_start()/at91ether_stop()
> funct
Hi Daniel,
On 18.10.2019 23:24, Daniel Lezcano wrote:
> Hi Claudiu,
>
> On 15/10/2019 11:23, claudiu.bez...@microchip.com wrote:
>
> [ ... ]
>
>> The timer clock source could be divided by MR.PRES + 1.
>>
>> So, I used the clock-frequency DT binding to let user choose the timer's
>> frequency.
Hi Daniel,
On 13.10.2019 21:16, Daniel Lezcano wrote:
> Hi Claudiu,
>
> sorry for the delay, I was OoO again.
No problem, thank you for your reply.
>
> On 03/10/2019 12:43, claudiu.bez...@microchip.com wrote:
>>
>>
>> On 02.10.2019 16:35, Claudiu Beznea wrote:
>>> Hi Daniel,
>>>
>>> Taking int
Hi,
On 08.10.2019 19:54, Alexandre Belloni wrote:
> Hi,
>
> On 08/10/2019 19:46:26+0300, Claudiu Beznea wrote:
>> Add compatible for SAM9X60's PMC.
>
> I think the commit log could be clearer and mention why this is needed
> and the compatible string in sam9x60 is not sufficient.
I had issues w
On 04.10.2019 23:39, Uwe Kleine-König wrote:
> External E-Mail
>
>
> On Fri, Oct 04, 2019 at 09:35:23AM +, claudiu.bez...@microchip.com wrote:
>> Hi Kamel,
>>
>> On 02.10.2019 17:46, Kamel Bouhara wrote:
>>> +static int at91_init_twi_recovery_info(struct platform_device *pdev,
>>> +
Hi Kamel,
On 02.10.2019 17:46, Kamel Bouhara wrote:
> +static int at91_init_twi_recovery_info(struct platform_device *pdev,
> +struct at91_twi_dev *dev)
> +{
> + struct i2c_bus_recovery_info *rinfo = &dev->rinfo;
> +
> + dev->pinctrl = devm_pinctrl_get(&
On 02.10.2019 16:35, Claudiu Beznea wrote:
> Hi Daniel,
>
> Taking into account that Rob doesn't agree with the solution proposed in
> this series do you think there is a chance to merge this driver as is?
Sorry, I was talking here about the driver at [1].
[1]
https://lore.kernel.org/lkml/155
Hi Daniel,
Taking into account that Rob doesn't agree with the solution proposed in
this series do you think there is a chance to merge this driver as is?
If you have other suggestion I am open to try it.
Thank you,
Claudiu Beznea
On 26.09.2019 11:42, Claudiu Beznea wrote:
>
>
> On 25.09.2019
On 25.09.2019 20:19, Daniel Lezcano wrote:
> External E-Mail
>
>
> Hi Claudiu,
>
> On 10/09/2019 15:47, Claudiu Beznea wrote:
>> Hi,
>>
>> This series adds support to permit the selection of clocksource/clockevent
>> via DT.
>
> Thanks for the proposal and taking care of making some progress
On 18.09.2019 17:57, Kamel Bouhara wrote:
> Since commit 26202873bb51 ("avr32: remove support for AVR32
> architecture") there is no more user of platform_device_id and we
> should only use dt bindings
>
> Signed-off-by: Kamel Bouhara
Acked-by: Claudiu Beznea
> ---
> Changelog:
> v1->v2
>
On 11.09.2019 12:58, Codrin Ciubotariu wrote:
> External E-Mail
>
>
> After a transfer timeout, some faulty I2C slave devices might hold down
> the SCL or the SDA pins. We can generate a bus clear command, hoping that
> the slave might release the pins.
>
> Signed-off-by: Codrin Ciubotariu
R
On 05.09.2019 17:13, Alexandre Belloni wrote:
> + pr_err("ABE: %d %08x\n", bank, bits[word]);
Is this needed?
Hi Lars,
On 23.08.2019 13:06, Lars Poeschel wrote:
> External E-Mail
>
>
> On Thu, Aug 22, 2019 at 10:09:09AM +, claudiu.bez...@microchip.com wrote:
>> Hi Lars,
>>
>> On 20.08.2019 15:03, Lars Poeschel wrote:
>>> This adds the UART phy interface for the pn533 driver.
>>> The pn533 driver can
Hi Lars,
On 20.08.2019 15:03, Lars Poeschel wrote:
> This adds the UART phy interface for the pn533 driver.
> The pn533 driver can be used through UART interface this way.
> It is implemented as a serdev device.
>
> Cc: Johan Hovold
> Signed-off-by: Lars Poeschel
> ---
> Changes in v6:
> - Reba
On 20.08.2019 15:03, Lars Poeschel wrote:
> There is a problem in the initialisation and setup of the pn533: It
> registers with nfc too early. It could happen, that it finished
> registering with nfc and someone starts using it. But setup of the pn533
> is not yet finished. Bad or at least unint
On 27.06.2019 18:03, Stephen Boyd wrote:
> External E-Mail
>
>
> Quoting claudiu.bez...@microchip.com (2019-06-13 08:37:06)
>> From: Claudiu Beznea
>>
>> Hi,
>>
>> This series tries to improve error path for slow clock registrations
>> by adding functions to free resources and using them on fa
On 26.06.2019 21:36, Stephen Boyd wrote:
> Quoting claudiu.bez...@microchip.com (2019-05-21 03:11:33)
>> From: Claudiu Beznea
>>
>> Add support for SAM9X60's slow clock.
>>
>> Signed-off-by: Claudiu Beznea
>> Acked-by: Alexandre Belloni
>> ---
>
> FYI, this patch is base64 encoded and causes
Hi Daniel,
On 20.06.2019 11:53, Daniel Lezcano wrote:
> Hi Claudiu,
>
> sorry for the late reply.
No problem, I understand.
>
>
> On 13/06/2019 16:12, claudiu.bez...@microchip.com wrote:
>> Hi Daniel,
>>
>> On 31.05.2019 13:41, Daniel Lezcano wrote:
>>>
>>> Hi Claudiu,
>>>
>>>
>>> On 30/05/20
Hi,
On 18.06.2019 12:55, Alexandre Belloni wrote:
> On 13/06/2019 15:37:06+, claudiu.bez...@microchip.com wrote:
>> From: Claudiu Beznea
>>
>> Hi,
>>
>> This series tries to improve error path for slow clock registrations
>> by adding functions to free resources and using them on failures.
>>
From: Claudiu Beznea
Use at91 specific functions to free all resources in case of error.
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/sckc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c
index f7ad3e9414dc..42502
From: Claudiu Beznea
Remove unnecessary line.
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/sckc.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c
index a2b905c91085..c61b6c9ddb94 100644
--- a/drivers/clk/at91/sckc.c
+++ b/drivers/clk/a
From: Claudiu Beznea
Hi,
This series tries to improve error path for slow clock registrations
by adding functions to free resources and using them on failures.
It is created on top of patch series at [1].
Thank you,
Claudiu Beznea
[1]
https://lore.kernel.org/lkml/1558433454-27971-1-git-send-
From: Claudiu Beznea
Improve error path for sam9x5 slow clock registration.
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/sckc.c | 50 +++--
1 file changed, 32 insertions(+), 18 deletions(-)
diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at
From: Claudiu Beznea
Add support to free slow oscillator resources.
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/sckc.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c
index 2c410f41b413..c1d7edd33416 100644
--- a/drivers/clk/
From: Claudiu Beznea
Improve error path for sama5d4 sck registration.
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/sckc.c | 43 ---
1 file changed, 28 insertions(+), 15 deletions(-)
diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c
in
From: Claudiu Beznea
Add support to free slow clock oscillator resources.
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/sckc.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c
index 492b139a7c15..2a677c56f901 100644
--- a/driver
From: Claudiu Beznea
Add support to free slow rc oscillator resources.
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/sckc.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c
index c1d7edd33416..492b139a7c15 100644
--- a/drivers/c
Hi Daniel,
On 31.05.2019 13:41, Daniel Lezcano wrote:
>
> Hi Claudiu,
>
>
> On 30/05/2019 09:46, claudiu.bez...@microchip.com wrote:
>> Hi Daniel,
>>
>> Taking into account the discussion on this tread and the fact that we have
>> no answer from Rob on this topic (I'm talking about [1]), what d
From: Claudiu Beznea
Add compatible string for SAM9X60 HLCDC's PWM.
Signed-off-by: Claudiu Beznea
Acked-by: Thierry Reding
---
Hi Thierry,
This patch was initially part of series at [1]. The rest of the patches in
that series were taken though drm-misc-next. Only this one remained.
[1]
htt
Hi Daniel,
Taking into account the discussion on this tread and the fact that we have
no answer from Rob on this topic (I'm talking about [1]), what do you think
it would be best for this driver to be accepted the soonest? Would it be OK
for you to mimic the approach done by:
drivers/clocksource/
From: Claudiu Beznea
SAMA5D2 SoC has a suspend mode where SoC's power is cut off. Due to this
the registers content is lost after a suspend/resume cycle. The current
suspend/resume implementation covers some of these registers. However
there are few which were not treated (e.g. SCRT2 and USRIO).
From: Claudiu Beznea
Add support for SAM9X60's slow clock.
Signed-off-by: Claudiu Beznea
Acked-by: Alexandre Belloni
---
drivers/clk/at91/sckc.c | 74 +
1 file changed, 74 insertions(+)
diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sc
From: Claudiu Beznea
Hi,
This series add slow clock support for SAM9X60. Apart from previous IPs, this
one uses different offsets in control register for different functionalities.
The series adapt current driver to work for all IPs using per IP
configurations initialized at probe.
Thank you,
C
From: Claudiu Beznea
Add bindings for SAM9X60's slow clock controller.
Signed-off-by: Claudiu Beznea
Reviewed-by: Alexandre Belloni
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/clock/at91-clock.txt | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/D
From: Claudiu Beznea
Different IPs uses different bit offsets in registers for the same
functionality, thus adapt the driver to support this.
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/sckc.c | 93 -
1 file changed, 61 insertions(+), 32 d
From: Claudiu Beznea
The slow clock of SAMA5D4 has no bypass support thus remove it.
Signed-off-by: Claudiu Beznea
Acked-by: Alexandre Belloni
---
drivers/clk/at91/sckc.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c
index e76b1d64e
On 18.05.2019 00:13, Alexandre Belloni wrote:
> External E-Mail
>
>
> On 16/05/2019 08:10:34+, claudiu.bez...@microchip.com wrote:
@@ -69,10 +80,11 @@ static int clk_slow_osc_prepare(struct clk_hw *hw)
void __iomem *sckcr = osc->sckcr;
u32 tmp = readl(sckcr);
>>>
On 11.05.2019 00:32, Alexandre Belloni wrote:
> On 10/05/2019 11:23:31+, claudiu.bez...@microchip.com wrote:
>> From: Claudiu Beznea
>>
>> Different IPs uses different bit offsets in registers for the same
>> functionality, thus adapt the driver to support this.
>>
>> Signed-off-by: Claudiu
From: Claudiu Beznea
The slow clock of SAMA5D4 has no bypass support thus remove it.
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/sckc.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c
index e76b1d64e905..6c55a7a86f79 100644
---
From: Claudiu Beznea
Add support for SAM9X60's slow clock.
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/sckc.c | 74 +
1 file changed, 74 insertions(+)
diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c
index 2a4ac548de80..2c41
From: Claudiu Beznea
Different IPs uses different bit offsets in registers for the same
functionality, thus adapt the driver to support this.
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/sckc.c | 100
1 file changed, 67 insertions(+), 33 d
From: Claudiu Beznea
Hi,
This series add slow clock support for SAM9X60. Apart from previous IPs, this
one uses different offsets in control register for different functionalities.
The series adapt current driver to work for all IPs using per IP
configurations initialized at probe.
Thank you,
C
From: Claudiu Beznea
Add bindings for SAM9X60's slow clock controller.
Signed-off-by: Claudiu Beznea
---
Hi Rob,
I didn't added your Reviewed-by tag to this version since I changed
the driver with regards to clock-cells DT binding (and I though you
may want to comment on this).
Thank you,
Cl
From: Claudiu Beznea
atmel_qspi objects are kept in spi_controller objects, so, first get
pointer to spi_controller object and then get atmel_qspi object from
spi_controller object.
Fixes: 2d30ac5ed633 ("mtd: spi-nor: atmel-quadspi: Use spi-mem interface for
atmel-quadspi driver")
Signed-off-by
Hi Daniel,
On 08.04.2019 11:43, Daniel Lezcano wrote:
> External E-Mail
>
>
> Hi Claudiu,
>
> On 14/03/2019 17:26, claudiu.bez...@microchip.com wrote:
>> From: Claudiu Beznea
>>
>> Add driver for Microchip PIT64B timer. Timer could be used in continuous
>> mode or oneshot mode. The hardware ha
From: Claudiu Beznea
Change Microchip timers section name to be more generic.
Signed-off-by: Claudiu Beznea
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 4d04cebb4a71..0948d6592ea5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
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