Re: [PATCH] riscv: Bump COMMAND_LINE_SIZE value to 1024

[David Abdurachmanov]

On Fri, Apr 2, 2021 at 11:43 AM Dmitry Vyukov  wrote:
>
> On Fri, Apr 2, 2021 at 6:37 AM Palmer Dabbelt  wrote:
> >
> > On Tue, 30 Mar 2021 13:31:45 PDT (-0700), ma...@orcam.me.uk wrote:
> > > On Mon, 29 Mar 2021, Palmer Dabbelt wrote:
> > >
> > >> > --- /dev/null
> > >> > +++ b/arch/riscv/include/uapi/asm/setup.h
> > >> > @@ -0,0 +1,8 @@
> > >> > +/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */
> > >> > +
> > >> > +#ifndef _UAPI_ASM_RISCV_SETUP_H
> > >> > +#define _UAPI_ASM_RISCV_SETUP_H
> > >> > +
> > >> > +#define COMMAND_LINE_SIZE 1024
> > >> > +
> > >> > +#endif /* _UAPI_ASM_RISCV_SETUP_H */
> > >>
> > >> I put this on fixes, but it seemes like this should really be a Kconfig
> > >> enttry.  Either way, ours was quite a bit smaller than most 
> > >> architectures and
> > >> it's great that syzbot has started to find bugs, so I'd rather get this 
> > >> in
> > >> sooner.
> > >
> > >  This macro is exported as a part of the user API so it must not depend on
> > > Kconfig.  Also changing it (rather than say adding COMMAND_LINE_SIZE_V2 or
> > > switching to an entirely new data object that has its dimension set in a
> > > different way) requires careful evaluation as external binaries have and
> > > will have the value it expands to compiled in, so it's a part of the ABI
> > > too.
> >
> > Thanks, I didn't realize this was part of the user BI.  In that case we
> > really can't chage it, so we'll have to sort out some other way do fix
> > whatever is going on.
> >
> > I've dropped this from fixes.
>
> Does increasing COMMAND_LINE_SIZE break user-space binaries? I would
> expect it to work the same way as adding new enum values, or adding
> fields at the end of versioned structs, etc.
> I would assume the old bootloaders/etc will only support up to the
> old, smaller max command line size, while the kernel will support
> larger command line size, which is fine.
> However, if something copies /proc/cmdline into a fixed-size buffer
> and expects that to work, that will break... that's quite unfortunate
> user-space code... is it what we afraid of?
>
> Alternatively, could expose the same COMMAND_LINE_SIZE, but internally
> support a larger command line?

Looking at kernel commit history I see PowerPC switched from 512 to
2048, and I don't see complaints about the ABI on the mailing list.

If COMMAND_LINE_SIZE is used by user space applications and we
increase it there shouldn't be problems. I would expect things to
work, but just get truncated boot args? That is the application will
continue only to look at the initial 512 chars.

https://linuxppc-dev.ozlabs.narkive.com/m4cj8nBa/patch-1-1-powerpc-increase-command-line-size-to-2048-from-512

Re: [PATCH v2 0/3] fix macb phy probe failure if phy-reset is not handled

[David Abdurachmanov]

On Fri, Feb 5, 2021 at 5:42 AM Palmer Dabbelt  wrote:
>
> On Thu, 04 Feb 2021 02:16:54 PST (-0800), sch...@linux-m68k.org wrote:
> > On Jan 13 2021, Palmer Dabbelt wrote:
> >
> >> On Tue, 10 Nov 2020 07:22:09 PST (-0800), sagar.ka...@sifive.com wrote:
> >>> HiFive Unleashed is having VSC8541-01 ethernet phy device and requires a
> >>> specific reset sequence of 0-1-0-1 in order to use it in unmanaged mode.
> >>> This series addresses a corner case where phy reset is not handled by boot
> >>> stages prior to linux.
> >>> Somewhat similar unreliable phy probe failure was reported and discussed
> >>> here [1].
> >>> The macb driver fails to detect the ethernet phy device if the bootloader
> >>> doesn't provide a proper reset sequence to the phy device or the phy 
> >>> itself
> >>> is in some invalid state. Currently, the FSBL or u-boot-spl is resetting
> >>> the phy device, and so there is no issue observed in the linux network
> >>> setup.
> >>>
> >>> The series is based on linux-5.10-rc5.
> >>> Patch 1: Add the OUI to the phy dt node to fix issue of missing mdio 
> >>> device
> >>> Patch 2 and 3:
> >>> Resetting phy needs GPIO support so add to dt and defconfig.
> >>>
> >>> [1] https://lkml.org/lkml/2018/11/29/154
> >>>
> >>> To reproduce the issue:
> >>> Using FSBL:
> >>> 1. Comment out VSC8541 reset sequence in fsbl/main.c
> >>>from within the freedom-u540-c000-bootloader.
> >>> 2. Build and flash fsbl.bin to micro sdcard.
> >>>
> >>> Using u-boot:
> >>> 1. Comment out VSC8541 reset sequence in board/sifive/fu540/spl.c
> >>>from mainline u-boot source code.
> >>> 2. Build and flash u-boot binaries to micro sdcard.
> >>>
> >>> Boot the board and bootlog will show network setup failure messages as:
> >>>
> >>> [  1.069474] libphy: MACB_mii_bus: probed
> >>> [  1.073092] mdio_bus 1009.ethernet-: MDIO device at address 0
> >>>is missing
> >>> .
> >>> [  1.979252] macb 1009.ethernet eth0: Could not attach PHY (-19)
> >>>
> >>> 3. Now apply the series build, and boot kernel.
> >>> 4. MACB and VSC8541 driver get successfully probed and the network is set
> >>>without any failure.
> >>>
> >>>
> >>> So irrespective of whether the prior stages handle the phy reset sequence,
> >>> the probing is successful in both the cases of cold boot and warm boot.
> >>>
> >>> Change History:
> >>> ===
> >>> V2:
> >>> -Rebased v1 on linux kernel v5.10-rc3.
> >>>
> >>> V1:
> >>> -Ignore 4th patch as suggested and so removed it from the series.
> >>> -Verified this series on 5.7-rc5.
> >>>
> >>> V0: Base RFC patch. Verified on 5.7-rc2
> >>>
> >>> Sagar Shrikant Kadam (3):
> >>>   dts: phy: fix missing mdio device and probe failure of vsc8541-01
> >>> device
> >>>   dts: phy: add GPIO number and active state used for phy reset
> >>>   riscv: defconfig: enable gpio support for HiFive Unleashed
> >>>
> >>>  arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 2 ++
> >>>  arch/riscv/configs/defconfig| 2 ++
> >>>  2 files changed, 4 insertions(+)
> >>
> >> David pointed out I missed these, they're on fixes.  Thanks!
> >
> > This is now on 5.10.12, and breaks ethernet on the Hifive Unleashed:
> >
> > [   12.777976] macb 1009.ethernet: Registered clk switch 
> > 'sifive-gemgxl-mgmt'
> > [   12.784559] macb 1009.ethernet: GEM doesn't support hardware ptp.
> > [   12.791629] libphy: MACB_mii_bus: probed
> > [   12.919728] MACsec IEEE 802.1AE
> > [   12.984676] macb 1009.ethernet eth0: Cadence GEM rev 0x10070109 at 
> > 0x1009 irq 16 (70:b3:d5:92:f1:07)
> > [   14.030319] Microsemi VSC8541 SyncE 1009.ethernet-:00: 
> > phy_poll_reset failed: -110
> > [   14.038986] macb 1009.ethernet eth0: Could not attach PHY (-110)
>
> Sorry about that.  Looks like we forgot to add the special reset sequence to
> the VSC8541, which the driver doesn't yet support (there's a thread about it,
> but I guess I forgot to clean up the patch).  IIUC this should manifest on
> master as well, so my guess is that nobody is testing the HiFive Unleashed any
> more (probably a bad sign).

BayLibre has Unleashed connected to KernelCI. I did notice:

[..]
08:24:37.572482  <3>[2.022855] Microsemi VSC8541 SyncE
1009.ethernet-:00: phy_poll_reset failed: -110
08:24:37.574273  <3>[2.031882] macb 1009.ethernet eth0: Could
not attach PHY (-110)
08:24:37.575304  <3>[2.037772] IP-Config: Failed to open eth0
08:24:37.576087  <3>[2.042087] IP-Config: No network devices available
08:24:37.576863  <6>[2.053662] Freeing unused kernel memory: 2144K
08:24:37.577412  <6>[2.057794] Run /init as init process
[..]

in KCIDB.

I don't use KernelCI extensively, but today at FOSDEM I was told that
KernelCI also incl. "including maintainer ones".

I guess the idea would be to check and ensure that all relevant trees
are tested in KernelCI.


>
> I'll send out a revert.  I looked at the GPIO driver and can't tell if it's

Re: [PATCH 0/3] Dynamic CPU frequency switching for the HiFive

[David Abdurachmanov]

On Wed, Jul 1, 2020 at 1:41 PM Andreas Schwab  wrote:
>
> On Jun 16 2020, Yash Shah wrote:
>
> > The patch series adds the support for dynamic CPU frequency switching
> > for FU540-C000 SoC on the HiFive Unleashed board. All the patches are
> > based on Paul Walmsley's work.
> >
> > This series is based on Linux v5.7 and tested on HiFive unleashed board.
>
> I'm using that patch with 5.7.5.
>
> It appears to interfer with serial output when using the ondemand
> governor.

I do recall that userspace governor is the only one supported but this
might have changed before this patch was posted.

Yash, do you have more details?

>
> I also see soft lockups when using the performance governor:
>
> [  101.587527] rcu: INFO: rcu_sched self-detected stall on CPU
> [  101.592322] rcu: 0-...!: (932 ticks this GP) 
> idle=11a/1/0x4004 softirq=4301/4301 fqs=4
> [  101.601432]  (t=6001 jiffies g=4017 q=859)
> [  101.605514] rcu: rcu_sched kthread starved for 5984 jiffies! g4017 f0x0 
> RCU_GP_WAIT_FQS(5) ->state=0x0 ->cpu=2
> [  101.615494] rcu: RCU grace-period kthread stack dump:
> [  101.620530] rcu_sched   R  running task010  2 
> 0x
> [  101.627560] Call Trace:
> [  101.630004] [] __schedule+0x25c/0x616
> [  101.635205] [] schedule+0x42/0xb2
> [  101.640070] [] schedule_timeout+0x56/0xb8
> [  101.645626] [] rcu_gp_fqs_loop+0x208/0x248
> [  101.651266] [] rcu_gp_kthread+0xc2/0xcc
> [  101.656651] [] kthread+0xda/0xec
> [  101.661426] [] ret_from_exception+0x0/0xc
> [  101.666977] Task dump for CPU 0:
> [  101.670187] loop0   R  running task0   655  2 
> 0x0008
> [  101.677218] Call Trace:
> [  101.679657] [] walk_stackframe+0x0/0xaa
> [  101.685036] [] show_stack+0x2a/0x34
> [  101.690074] [] sched_show_task.part.0+0xc2/0xd2
> [  101.696154] [] sched_show_task+0x64/0x66
> [  101.701618] [] dump_cpu_task+0x3e/0x48
> [  101.706916] [] rcu_dump_cpu_stacks+0x94/0xce
> [  101.712731] [] print_cpu_stall+0x116/0x18a
> [  101.718375] [] check_cpu_stall+0xcc/0x1a2
> [  101.723929] [] rcu_pending.constprop.0+0x36/0xaa
> [  101.730094] [] rcu_sched_clock_irq+0xa6/0xea
> [  101.735913] [] update_process_times+0x1e/0x42
> [  101.741821] [] tick_sched_handle+0x26/0x52
> [  101.747456] [] tick_sched_timer+0x6a/0xd0
> [  101.753015] [] __run_hrtimer.constprop.0+0x50/0xe8
> [  101.759353] [] __hrtimer_run_queues+0x48/0x6c
> [  101.765254] [] hrtimer_interrupt+0xca/0x1d4
> [  101.770985] [] riscv_timer_interrupt+0x32/0x3a
> [  101.776976] [] do_IRQ+0xa4/0xb8
> [  101.781663] [] ret_from_exception+0x0/0xc
>
> Andreas.
>
> --
> Andreas Schwab, SUSE Labs, sch...@suse.de
> GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE  1748 E4D4 88E3 0EEA B9D7
> "And now for something completely different."
>
> ___
> linux-riscv mailing list
> linux-ri...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH v5 0/2] cacheinfo support to read no. of L2 cache ways enabled

[David Abdurachmanov]

Ping.

I think this one got lost in time. I don't see it in v5.6 or v5.7.

david

On Fri, Mar 13, 2020 at 8:03 AM Yash Shah  wrote:
>
> Any comments or updates on this series?
>
> - Yash
>
> > -Original Message-
> > From: Yash Shah 
> > Sent: 20 February 2020 10:45
> > To: pal...@dabbelt.com; Paul Walmsley ( Sifive)
> > 
> > Cc: a...@eecs.berkeley.edu; a...@brainfault.org;
> > gre...@linuxfoundation.org; alexios.zav...@intel.com; t...@linutronix.de;
> > b...@suse.de; linux-ri...@lists.infradead.org; linux-kernel@vger.kernel.org;
> > Sachin Ghadi ; Yash Shah
> > 
> > Subject: [PATCH v5 0/2] cacheinfo support to read no. of L2 cache ways
> > enabled
> >
> > The patchset includes 2 patches. Patch 1 implements cache_get_priv_group
> > which make use of a generic ops structure to return a private attribute 
> > group
> > for custom cacheinfo. Patch 2 implements a private attribute named
> > "number_of_ways_enabled" in the cacheinfo framework. Reading this
> > attribute returns the number of L2 cache ways enabled at runtime,
> >
> > This patchset is based on Linux v5.6-rc2 and tested on HiFive Unleashed
> > board.
> >
> > v5:
> > - Since WayEnable is 8bits, mask out and return only the last 8 bit in
> >   l2_largest_wayenabled()
> > - Rebased on Linux v5.6-rc2
> >
> > v4:
> > - Rename "sifive_l2_largest_wayenabled" to "l2_largest_wayenabled" and
> >   make it a static function
> >
> > v3:
> > - As per Anup Patel's suggestion[0], implement a new approach which uses
> >   generic ops structure. Hence addition of patch 1 to this series and
> >   corresponding changes to patch 2.
> > - Dropped "riscv: dts: Add DT support for SiFive L2 cache controller"
> >   patch since it is already merged
> > - Rebased on Linux v5.5-rc6
> >
> > Changes in v2:
> > - Rebase the series on v5.5-rc3
> > - Remove the reserved-memory node from DT
> >
> > [0]: https://lore.kernel.org/linux-
> > riscv/CAAhSdy0CXde5s_ya=4YvmA4UQ5f5gLU-
> > z_faor8lpni+s_6...@mail.gmail.com/
> >
> > Yash Shah (2):
> >   riscv: cacheinfo: Implement cache_get_priv_group with a generic ops
> > structure
> >   riscv: Add support to determine no. of L2 cache way enabled
> >
> >  arch/riscv/include/asm/cacheinfo.h   | 15 ++
> >  arch/riscv/kernel/cacheinfo.c| 17 
> >  drivers/soc/sifive/sifive_l2_cache.c | 38
> > 
> >  3 files changed, 70 insertions(+)
> >  create mode 100644 arch/riscv/include/asm/cacheinfo.h
> >
> > --
> > 2.7.4
>
>

[PATCH] riscv: fix fs/proc/kcore.c compilation with sparsemem enabled

[David Abdurachmanov]

Failed to compile Fedora/RISCV kernel (5.4-rc3+) with sparsemem enabled:

fs/proc/kcore.c: In function 'read_kcore':
fs/proc/kcore.c:510:8: error: implicit declaration of function 
'kern_addr_valid'; did you mean 'virt_addr_valid'? 
[-Werror=implicit-function-declaration]
  510 |if (kern_addr_valid(start)) {
  |^~~
  |virt_addr_valid

Looking at other architectures I don't see kern_addr_valid being guarded by
CONFIG_FLATMEM.

Fixes: d95f1a542c3d ("RISC-V: Implement sparsemem")
Signed-off-by: David Abdurachmanov 
Tested-by: David Abdurachmanov 
---
 arch/riscv/include/asm/pgtable.h | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
index 42292d99cc74..7110879358b8 100644
--- a/arch/riscv/include/asm/pgtable.h
+++ b/arch/riscv/include/asm/pgtable.h
@@ -428,9 +428,7 @@ static inline int ptep_clear_flush_young(struct 
vm_area_struct *vma,
 #define __pte_to_swp_entry(pte)((swp_entry_t) { pte_val(pte) })
 #define __swp_entry_to_pte(x)  ((pte_t) { (x).val })
 
-#ifdef CONFIG_FLATMEM
 #define kern_addr_valid(addr)   (1) /* FIXME */
-#endif
 
 extern void *dtb_early_va;
 extern void setup_bootmem(void);
-- 
2.21.0

Re: [PATCH] irqchip/sifive-plic: add irq_mask and irq_unmask

[David Abdurachmanov]

On Tue, Sep 17, 2019 at 3:26 PM Paul Walmsley  wrote:
>
>
> Just tested this on the SiFive HiFive Unleashed.  Seems to work OK;
> however I did not stress-test it.
>
> Tested-by: Paul Walmsley  # HiFive Unleashed
>
>
> - Paul
>
>
> # !cat
> cat /proc/interrupts
>CPU0   CPU1   CPU2   CPU3
>   1:  0  0  0  0  SiFive PLIC   5  
> 10011000.serial
>   3:  0  0  0  0  SiFive PLIC  51  
> 1004.spi
>   4:   6266  0  0  0  SiFive PLIC   4  
> 1001.serial
>   5:102  0  0  0  SiFive PLIC   6  
> 1005.spi
>   6: 37  0  0  0  SiFive PLIC  53  eth0
> IPI0:  1134  21128   9024 220261  Rescheduling interrupts
> IPI1:10143 18  7  Function call interrupts
> IPI2: 0  0  0  0  CPU stop interrupts
> #

I have applied the patch on top of 5.2.9 kernel and tried to stress it
with stress-ng interrupt stressors for 2:30+ hours.

# cat /proc/interrupts
   CPU0   CPU1   CPU2   CPU3
  1:  0  0  0  0  SiFive PLIC   5
10011000.serial
  3:  0  0  0  0  SiFive PLIC  51  1004.spi
  4:  34240  0  0  0  SiFive PLIC   4
1001.serial
  5:102  0  0  0  SiFive PLIC   6  1005.spi
  6:  0  0  0  0  SiFive PLIC  53  eth0
  7:  0  0  0  0  SiFive PLIC  32
microsemi-pcie
IPI0:  32013933   28068736   29345256   23346339  Rescheduling interrupts
IPI1: 78514  78586  63144 100317  Function call interrupts
IPI2: 0  0  0  0  CPU stop interrupts

Re: [PATCH v2] riscv: add support for SECCOMP and SECCOMP_FILTER

[David Abdurachmanov]

On Wed, Aug 28, 2019 at 10:36 AM Kees Cook  wrote:
>
> On Fri, Aug 23, 2019 at 05:30:53PM -0700, Paul Walmsley wrote:
> > On Thu, 22 Aug 2019, David Abdurachmanov wrote:
> >
> > > There is one failing kernel selftest: global.user_notification_signal
> >
> > Is this the only failing test?  Or are the rest of the selftests skipped
> > when this test fails, and no further tests are run, as seems to be shown
> > here:
> >
> >   
> > https://lore.kernel.org/linux-riscv/cadnnuqcmdmre1f+3jg8spr6jrrnbsy8vvd70vbkem0nqyeo...@mail.gmail.com/
> >
> > For example, looking at the source, I'd naively expect to see the
> > user_notification_closed_listener test result -- which follows right
> > after the failing test in the selftest source.  But there aren't any
> > results?
> >
> > Also - could you follow up with the author of this failing test to see if
> > we can get some more clarity about what might be going wrong here?  It
> > appears that the failing test was added in commit 6a21cc50f0c7f ("seccomp:
> > add a return code to trap to userspace") by Tycho Andersen
> > .
>
> So, the original email says the riscv series is tested on top of 5.2-rc7,
> but just for fun, can you confirm that you're building a tree that includes
> 9dd3fcb0ab73 ("selftests/seccomp: Handle namespace failures gracefully")? I
> assume it does, but I suspect something similar is happening, where the
> environment is slightly different than expected and the test stalls.
>
> Does it behave the same way under emulation (i.e. can I hope to
> reproduce this myself?)

This was tested in 5.2-rc7 and later in 5.3-rc with the same behavior.
Also VM or physical HW doesn't matter, same result.

>
> --
> Kees Cook

Re: [PATCH v2] riscv: add support for SECCOMP and SECCOMP_FILTER

[David Abdurachmanov]

On Wed, Aug 28, 2019 at 10:36 AM Kees Cook  wrote:
>
> On Thu, Aug 22, 2019 at 01:55:22PM -0700, David Abdurachmanov wrote:
> > This patch was extensively tested on Fedora/RISCV (applied by default on
> > top of 5.2-rc7 kernel for <2 months). The patch was also tested with 5.3-rc
> > on QEMU and SiFive Unleashed board.
>
> Oops, I see the mention of QEMU here. Where's the best place to find
> instructions on creating a qemu riscv image/environment?

Examples from what I personally use:
https://github.com/riscv/meta-riscv
https://fedoraproject.org/wiki/Architectures/RISC-V/Installing#Boot_with_libvirt
(might be outdated)

If you are running machine with a properly working libvirt/QEMU setup:

VIRTBUILDER_IMAGE=fedora-rawhide-developer-20190703n0
FIRMWARE=fw_payload-uboot-qemu-virt-smode.elf
wget 
https://dl.fedoraproject.org/pub/alt/risc-v/disk-images/fedora/rawhide/20190703.n.0/Developer/$FIRMWARE
echo riscv > /tmp/rootpw
virt-builder \
--verbose \
--source 
https://dl.fedoraproject.org/pub/alt/risc-v/repo/virt-builder-images/images/index
\
--no-check-signature \
--arch riscv64 \
--size 10G \
--format raw \
--hostname fedora-riscv \
-o disk \
--root-password file:/tmp/rootpw \
${VIRTBUILDER_IMAGE}

sudo virt-install \
--name fedora-riscv \
--arch riscv64 \
--vcpus 4 \
--memory 3048 \
--import \
--disk path=$PWD/disk \
--boot kernel=$PWD/${FIRMWARE} \
--network network=default \
--graphics none \
--serial log.file=/tmp/fedora-riscv.serial.log \
--noautoconsole

The following does incl. SECCOMP v2 patch on top of 5.2-rc7 kernel.

>
> > There is one failing kernel selftest: global.user_notification_signal
>
> This test has been fragile (and is not arch-specific), so as long as
> everything else is passing, I would call this patch ready to go. :)
>
> Reviewed-by: Kees Cook 
>
> --
> Kees Cook

Re: [PATCH v2] riscv: add support for SECCOMP and SECCOMP_FILTER

[David Abdurachmanov]

On Mon, Aug 26, 2019 at 7:57 AM Tycho Andersen  wrote:
>
> Hi,
>
> On Fri, Aug 23, 2019 at 05:30:53PM -0700, Paul Walmsley wrote:
> > On Thu, 22 Aug 2019, David Abdurachmanov wrote:
> >
> > > There is one failing kernel selftest: global.user_notification_signal
> >
> > Also - could you follow up with the author of this failing test to see if
> > we can get some more clarity about what might be going wrong here?  It
> > appears that the failing test was added in commit 6a21cc50f0c7f ("seccomp:
> > add a return code to trap to userspace") by Tycho Andersen
> > .
>
> Can you post an strace and a cat of /proc/$pid/stack for both tasks
> where it gets stuck? I don't have any riscv hardware, and it "works
> for me" on x86 and arm64 with 100 tries.

I don't have the a build with SECCOMP for the board right now, so it
will have to wait. I just finished a new kernel (almost rc6) for Fedora,
but it will take time to assemble new repositories and a disk image.

There is older disk image available (5.2.0-rc7 kernel with v2 SECCOMP)
for QEMU or libvirt/QEMU:

https://dl.fedoraproject.org/pub/alt/risc-v/disk-images/fedora/rawhide/20190703.n.0/Developer/
https://fedoraproject.org/wiki/Architectures/RISC-V/Installing#Boot_with_libvirt

(If you are interesting trying it locally.)

IIRC I attempted to connected with strace, but it quickly returns and fails
properly. Simply put strace unblocks whatever is stuck.

david

Re: [PATCH v2] riscv: add support for SECCOMP and SECCOMP_FILTER

[David Abdurachmanov]

On Fri, Aug 23, 2019 at 6:04 PM David Abdurachmanov
 wrote:
>
> On Fri, Aug 23, 2019 at 5:30 PM Paul Walmsley  
> wrote:
> >
> > On Thu, 22 Aug 2019, David Abdurachmanov wrote:
> >
> > > There is one failing kernel selftest: global.user_notification_signal
> >
> > Is this the only failing test?  Or are the rest of the selftests skipped
> > when this test fails, and no further tests are run, as seems to be shown
> > here:
> >
> >   
> > https://lore.kernel.org/linux-riscv/cadnnuqcmdmre1f+3jg8spr6jrrnbsy8vvd70vbkem0nqyeo...@mail.gmail.com/
>
> Yes, it's a single test failing. After removing 
> global.user_notification_signal
> test everything else pass and you get the results printed.
>
> >
> > For example, looking at the source, I'd naively expect to see the
> > user_notification_closed_listener test result -- which follows right
> > after the failing test in the selftest source.  But there aren't any
> > results?
>
> Yes, it hangs at this point. You have to manually terminate it.
>
> >
> > Also - could you follow up with the author of this failing test to see if
> > we can get some more clarity about what might be going wrong here?  It
> > appears that the failing test was added in commit 6a21cc50f0c7f ("seccomp:
> > add a return code to trap to userspace") by Tycho Andersen
> > .
>
> Well the code states ".. and hope that it doesn't break when there
> is actually a signal :)". Maybe we are just unlucky. I don't have results
> from other architectures to compare.
>
> I found that Linaro is running selftests, but SECCOMP is disabled
> and thus it's failing. Is there another CI which tracks selftests?
>
> https://qa-reports.linaro.org/lkft/linux-next-oe/tests/kselftest/seccomp_seccomp_bpf?top=next-20190823

Actually it seems that seccomp is enabled in kernel, but not in
systemd, and somehow seccomp_bpf is missing on all arches thus
causing automatic failure.

> >
> >
> > - Paul

Re: [PATCH v2] riscv: add support for SECCOMP and SECCOMP_FILTER

[David Abdurachmanov]

On Fri, Aug 23, 2019 at 5:30 PM Paul Walmsley  wrote:
>
> On Thu, 22 Aug 2019, David Abdurachmanov wrote:
>
> > There is one failing kernel selftest: global.user_notification_signal
>
> Is this the only failing test?  Or are the rest of the selftests skipped
> when this test fails, and no further tests are run, as seems to be shown
> here:
>
>   
> https://lore.kernel.org/linux-riscv/cadnnuqcmdmre1f+3jg8spr6jrrnbsy8vvd70vbkem0nqyeo...@mail.gmail.com/

Yes, it's a single test failing. After removing global.user_notification_signal
test everything else pass and you get the results printed.

>
> For example, looking at the source, I'd naively expect to see the
> user_notification_closed_listener test result -- which follows right
> after the failing test in the selftest source.  But there aren't any
> results?

Yes, it hangs at this point. You have to manually terminate it.

>
> Also - could you follow up with the author of this failing test to see if
> we can get some more clarity about what might be going wrong here?  It
> appears that the failing test was added in commit 6a21cc50f0c7f ("seccomp:
> add a return code to trap to userspace") by Tycho Andersen
> .

Well the code states ".. and hope that it doesn't break when there
is actually a signal :)". Maybe we are just unlucky. I don't have results
from other architectures to compare.

I found that Linaro is running selftests, but SECCOMP is disabled
and thus it's failing. Is there another CI which tracks selftests?

https://qa-reports.linaro.org/lkft/linux-next-oe/tests/kselftest/seccomp_seccomp_bpf?top=next-20190823

>
>
> - Paul

[PATCH v2] riscv: add support for SECCOMP and SECCOMP_FILTER

[David Abdurachmanov]

This patch was extensively tested on Fedora/RISCV (applied by default on
top of 5.2-rc7 kernel for <2 months). The patch was also tested with 5.3-rc
on QEMU and SiFive Unleashed board.

libseccomp (userspace) was rebased:
https://github.com/seccomp/libseccomp/pull/134

Fully passes libseccomp regression testing (simulation and live).

There is one failing kernel selftest: global.user_notification_signal

v1 -> v2:
  - return immediatly if secure_computing(NULL) returns -1
  - fixed whitespace issues
  - add missing seccomp.h
  - remove patch #2 (solved now)
  - add riscv to seccomp kernel selftest

Cc: keesc...@chromium.org
Cc: m...@carlosedp.com

Signed-off-by: David Abdurachmanov 
---
 arch/riscv/Kconfig| 14 ++
 arch/riscv/include/asm/seccomp.h  | 10 +++
 arch/riscv/include/asm/thread_info.h  |  5 +++-
 arch/riscv/kernel/entry.S | 27 +--
 arch/riscv/kernel/ptrace.c| 10 +++
 tools/testing/selftests/seccomp/seccomp_bpf.c |  8 +-
 6 files changed, 70 insertions(+), 4 deletions(-)
 create mode 100644 arch/riscv/include/asm/seccomp.h

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 59a4727ecd6c..441e63ff5adc 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -31,6 +31,7 @@ config RISCV
select GENERIC_SMP_IDLE_THREAD
select GENERIC_ATOMIC64 if !64BIT
select HAVE_ARCH_AUDITSYSCALL
+   select HAVE_ARCH_SECCOMP_FILTER
select HAVE_MEMBLOCK_NODE_MAP
select HAVE_DMA_CONTIGUOUS
select HAVE_FUTEX_CMPXCHG if FUTEX
@@ -235,6 +236,19 @@ menu "Kernel features"
 
 source "kernel/Kconfig.hz"
 
+config SECCOMP
+   bool "Enable seccomp to safely compute untrusted bytecode"
+   help
+ This kernel feature is useful for number crunching applications
+ that may need to compute untrusted bytecode during their
+ execution. By using pipes or other transports made available to
+ the process as file descriptors supporting the read/write
+ syscalls, it's possible to isolate those applications in
+ their own address space using seccomp. Once seccomp is
+ enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
+ and the task is only allowed to execute a few safe syscalls
+ defined by each seccomp mode.
+
 endmenu
 
 menu "Boot options"
diff --git a/arch/riscv/include/asm/seccomp.h b/arch/riscv/include/asm/seccomp.h
new file mode 100644
index ..bf7744ee3b3d
--- /dev/null
+++ b/arch/riscv/include/asm/seccomp.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef _ASM_SECCOMP_H
+#define _ASM_SECCOMP_H
+
+#include 
+
+#include 
+
+#endif /* _ASM_SECCOMP_H */
diff --git a/arch/riscv/include/asm/thread_info.h 
b/arch/riscv/include/asm/thread_info.h
index 905372d7eeb8..a0b2a29a0da1 100644
--- a/arch/riscv/include/asm/thread_info.h
+++ b/arch/riscv/include/asm/thread_info.h
@@ -75,6 +75,7 @@ struct thread_info {
 #define TIF_MEMDIE 5   /* is terminating due to OOM killer */
 #define TIF_SYSCALL_TRACEPOINT  6   /* syscall tracepoint instrumentation 
*/
 #define TIF_SYSCALL_AUDIT  7   /* syscall auditing */
+#define TIF_SECCOMP8   /* syscall secure computing */
 
 #define _TIF_SYSCALL_TRACE (1 << TIF_SYSCALL_TRACE)
 #define _TIF_NOTIFY_RESUME (1 << TIF_NOTIFY_RESUME)
@@ -82,11 +83,13 @@ struct thread_info {
 #define _TIF_NEED_RESCHED  (1 << TIF_NEED_RESCHED)
 #define _TIF_SYSCALL_TRACEPOINT(1 << TIF_SYSCALL_TRACEPOINT)
 #define _TIF_SYSCALL_AUDIT (1 << TIF_SYSCALL_AUDIT)
+#define _TIF_SECCOMP   (1 << TIF_SECCOMP)
 
 #define _TIF_WORK_MASK \
(_TIF_NOTIFY_RESUME | _TIF_SIGPENDING | _TIF_NEED_RESCHED)
 
 #define _TIF_SYSCALL_WORK \
-   (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_TRACEPOINT | _TIF_SYSCALL_AUDIT)
+   (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_TRACEPOINT | _TIF_SYSCALL_AUDIT | \
+_TIF_SECCOMP )
 
 #endif /* _ASM_RISCV_THREAD_INFO_H */
diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
index bc7a56e1ca6f..0bbedfa3e47d 100644
--- a/arch/riscv/kernel/entry.S
+++ b/arch/riscv/kernel/entry.S
@@ -203,8 +203,25 @@ check_syscall_nr:
/* Check to make sure we don't jump to a bogus syscall number. */
li t0, __NR_syscalls
la s0, sys_ni_syscall
-   /* Syscall number held in a7 */
-   bgeu a7, t0, 1f
+   /*
+* The tracer can change syscall number to valid/invalid value.
+* We use syscall_set_nr helper in syscall_trace_enter thus we
+* cannot trust the current value in a7 and have to reload from
+* the current task pt_regs.
+*/
+   REG_L a7, PT_A7(sp)
+   /*
+* Syscall number held in a7.
+* If syscall number is above allowed value, redirect to ni_syscall.
+*/
+

Re: [PATCH v5 2/2] RISC-V: Setup initial page tables in two stages

[David Abdurachmanov]

On Thu, Aug 15, 2019 at 11:57 AM Alistair Francis
 wrote:
>
> On Wed, 2019-07-10 at 17:05 -0700, Paul Walmsley wrote:
> > On Fri, 7 Jun 2019, Anup Patel wrote:
> >
> > > Currently, the setup_vm() does initial page table setup in one-shot
> > > very early before enabling MMU. Due to this, the setup_vm() has to
> > > map
> > > all possible kernel virtual addresses since it does not know size
> > > and
> > > location of RAM. This means we have kernel mappings for non-
> > > existent
> > > RAM and any buggy driver (or kernel) code doing out-of-bound access
> > > to RAM will not fault and cause underterministic behaviour.
> > >
> > > Further, the setup_vm() creates PMD mappings (i.e. 2M mappings) for
> > > RV64 systems. This means for PAGE_OFFSET=0xffe0 (i.e.
> > > MAXPHYSMEM_128GB=y), the setup_vm() will require 129 pages (i.e.
> > > 516 KB) of memory for initial page tables which is never freed. The
> > > memory required for initial page tables will further increase if
> > > we chose a lower value of PAGE_OFFSET (e.g. 0xff00)
> > >
> > > This patch implements two-staged initial page table setup, as
> > > follows:
> > > 1. Early (i.e. setup_vm()): This stage maps kernel image and DTB in
> > > a early page table (i.e. early_pg_dir). The early_pg_dir will be
> > > used
> > > only by boot HART so it can be freed as-part of init memory free-
> > > up.
> > > 2. Final (i.e. setup_vm_final()): This stage maps all possible RAM
> > > banks in the final page table (i.e. swapper_pg_dir). The boot HART
> > > will start using swapper_pg_dir at the end of setup_vm_final(). All
> > > non-boot HARTs directly use the swapper_pg_dir created by boot
> > > HART.
> > >
> > > We have following advantages with this new approach:
> > > 1. Kernel mappings for non-existent RAM don't exists anymore.
> > > 2. Memory consumed by initial page tables is now indpendent of the
> > > chosen PAGE_OFFSET.
> > > 3. Memory consumed by initial page tables on RV64 system is 2 pages
> > > (i.e. 8 KB) which has significantly reduced and these pages will be
> > > freed as-part of the init memory free-up.
> > >
> > > The patch also provides a foundation for implementing strict kernel
> > > mappings where we protect kernel text and rodata using PTE
> > > permissions.
> > >
> > > Suggested-by: Mike Rapoport 
> > > Signed-off-by: Anup Patel 
> >
> > Thanks, updated to apply and to fix a checkpatch warning, and
> > queued.
> >
> > This may not make it in for v5.3-rc1; if not, we'll submit it later.
>
> I'm seeing this failure on RV32 which I bisected to this patch:
>
> [1.820461] systemd[1]: systemd 242-19-gdb2e367+ running in system
> mode. (-PAM -AUDIT -SELINUX +IMA -APPARMOR +SMACK +SYSVINIT +UTMP
> -LIBCRYPTSETUP -GCRYPT -GNUTLS +ACL +XZ -LZ4 -SECCOMP +BLKID -ELFUTILS
> +KMOD -IDN2 -IDN -PCRE2 default-hierarchy=hybrid)
> [1.824320] Unable to handle kernel paging request at virtual
> address 9ff00c15
> [1.824973] Oops [#1]
> [1.825162] Modules linked in:
> [1.825536] CPU: 0 PID: 1 Comm: systemd Not tainted 5.2.0-rc7 #1
> [1.826039] sepc: c05c3c78 ra : c04b5a74 sp : df047ce0
> [1.826514]  gp : c07a1038 tp : df04c000 t0 : 00fc
> [1.826919]  t1 : 0002 t2 : 03ef s0 : df047cf0
> [1.827322]  s1 : df7090f8 a0 : 9ff00c15 a1 : c072166c
> [1.827723]  a2 :  a3 : 0001 a4 : 0001
> [1.828104]  a5 : df6f8138 a6 : 002f a7 : de62a000
> [1.828534]  s2 : c072166c s3 :  s4 : 
> [1.828931]  s5 : c07a2000 s6 : 00400cc0 s7 : 0400
> [1.829319]  s8 : de491018 s9 :  s10: f000
> [1.829702]  s11: de491030 t3 : de62b000 t4 : 
> [1.830090]  t5 :  t6 : 0080
> [1.830392] sstatus: 0100 sbadaddr: 9ff00c15 scause: 000d
> [1.831616] ---[ end trace 49a926a1a5300c00 ]---
> [1.835776] Kernel panic - not syncing: Attempted to kill init!
> exitcode=0x000b
> [1.836575] ---[ end Kernel panic - not syncing: Attempted to kill
> init! exitcode=0x000b ]---
>
> Does anyone else see this?
>
> A simple revert of this patch on 5.3-rc4 fixes the issue for me.

Yes, I do see those in Fedora/RISCV build farm every morning, but with
riscv64 and 5.2.0-rc7 kernel.

You also seem to run 5.2.0-rc7 kernel.

fedora-riscv-4 login: [178876.406122] Unable to handle kernel paging
request at virtual address 00012a28
fedora-riscv-7 login: [17983.074847] Unable to handle kernel paging
request at virtual address 0fdff5e14700

david

[PATCH v2] Add COMPILE_TEST to CONFIG_ARM_TIMER_SP804

[David Abdurachmanov]

This is only used on arm and arm64 platforms. Add COMPILE_TEST option.

Tested with 5.1-rc3+ on Fedora/RISCV. CONFIG_ARM_TIMER_SP804 no more shows
up in riscv config.

Signed-off-by: David Abdurachmanov 
---
 drivers/clocksource/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 171502a356aa..ede5d20299b9 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -379,7 +379,7 @@ config ARM_GLOBAL_TIMER
  This options enables support for the ARM global timer unit
 
 config ARM_TIMER_SP804
-   bool "Support for Dual Timer SP804 module"
+   bool "Support for Dual Timer SP804 module" if COMPILE_TEST
depends on GENERIC_SCHED_CLOCK && CLKDEV_LOOKUP
select CLKSRC_MMIO
select TIMER_OF if OF
-- 
2.20.1

Re: [PATCH] riscv: fix syscall_get_arguments() and syscall_set_arguments()

[David Abdurachmanov]

On Fri, Mar 29, 2019 at 6:15 PM Steven Rostedt  wrote:
>
> On Fri, 29 Mar 2019 20:12:21 +0300
> "Dmitry V. Levin"  wrote:
>
> > RISC-V syscall arguments are located in orig_a0,a1..a5 fields
> > of struct pt_regs.
> >
> > Due to an off-by-one bug and a bug in pointer arithmetic
> > syscall_get_arguments() was reading s3..s7 fields instead of a1..a5.
> > Likewise, syscall_set_arguments() was writing s3..s7 fields
> > instead of a1..a5.
>
> Should I add this to my series? And then rebase on top of it?

I have alternative version posted in December part of SECCOMP
patchset which is based on arm64 implementation.

http://lists.infradead.org/pipermail/linux-riscv/2018-December/002450.html

I noticed that SECCOMP wasn't working properly if filters were
checking syscall arguments, because populated arguments were wrong.

Btw, I plan to send v2 of SECCOMP patchset soonish.

david

>
> -- Steve
>
> >
> > Fixes: e2c0cdfba7f69 ("RISC-V: User-facing API")
> > Cc: Steven Rostedt 
> > Cc: Ingo Molnar 
> > Cc: Kees Cook 
> > Cc: Andy Lutomirski 
> > Cc: Will Drewry 
> > Cc: linux-ri...@lists.infradead.org
> > Cc: sta...@vger.kernel.org # v4.15+
> > Signed-off-by: Dmitry V. Levin 
> > ---
> >  arch/riscv/include/asm/syscall.h | 12 +++-
> >  1 file changed, 7 insertions(+), 5 deletions(-)
> >
> > diff --git a/arch/riscv/include/asm/syscall.h 
> > b/arch/riscv/include/asm/syscall.h
> > index bba3da6ef157..6ea9e1804233 100644
> > --- a/arch/riscv/include/asm/syscall.h
> > +++ b/arch/riscv/include/asm/syscall.h
> > @@ -79,10 +79,11 @@ static inline void syscall_get_arguments(struct 
> > task_struct *task,
> >   if (i == 0) {
> >   args[0] = regs->orig_a0;
> >   args++;
> > - i++;
> >   n--;
> > + } else {
> > + i--;
> >   }
> > - memcpy(args, >a1 + i * sizeof(regs->a1), n * sizeof(args[0]));
> > + memcpy(args, >a1 + i, n * sizeof(args[0]));
> >  }
> >
> >  static inline void syscall_set_arguments(struct task_struct *task,
> > @@ -94,10 +95,11 @@ static inline void syscall_set_arguments(struct 
> > task_struct *task,
> >  if (i == 0) {
> >  regs->orig_a0 = args[0];
> >  args++;
> > -i++;
> >  n--;
> > -}
> > - memcpy(>a1 + i * sizeof(regs->a1), args, n * sizeof(regs->a0));
> > + } else {
> > + i--;
> > + }
> > + memcpy(>a1 + i, args, n * sizeof(regs->a1));
> >  }
> >
> >  static inline int syscall_get_arch(void)
>
>
> ___
> linux-riscv mailing list
> linux-ri...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH][RESEND] Make ARM_TIMER_SP804 depend on (ARM || ARM64)

[David Abdurachmanov]

On Thu, Feb 21, 2019 at 9:48 PM Daniel Lezcano
 wrote:
>
> On 21/02/2019 17:06, David Abdurachmanov wrote:
> > Resending to incl. a proper mailing list and maintainers (not suggested
> > by scripts/get_maintainer.pl)
> >
> > This is only used on arm and arm64 platforms. Other timers also seem
> > to depend on (ARM || ARM64).
> >
> > After I moved Fedora/RISCV kernel to 5.0.0-0.rc2 it keeps asking me to
> > add CONFIG_ARM_TIMER_SP804=n to my config. This patch resolved the issue.
> >
> > Signed-off-by: David Abdurachmanov 
> > ---
> >  drivers/clocksource/Kconfig | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
> > index a9e26f6a81a1..7593d80e1c88 100644
> > --- a/drivers/clocksource/Kconfig
> > +++ b/drivers/clocksource/Kconfig
> > @@ -369,7 +369,7 @@ config ARM_GLOBAL_TIMER
> >
> >  config ARM_TIMER_SP804
> >   bool "Support for Dual Timer SP804 module"
> > - depends on GENERIC_SCHED_CLOCK && CLKDEV_LOOKUP
> > + depends on (ARM || ARM64) && GENERIC_SCHED_CLOCK && CLKDEV_LOOKUP
>
> What about adding the COMPILE_TEST option:
>
> bool "Support for Dual Timer SP804 module" if COMPILE_TEST
>
> but not add the ARM || ARM64 dependency ?
>

That would work, but is that consistent with other timers?

Looks like a number of them have depends on + COMPILE_TEST.

Some examples:

config ROCKCHIP_TIMER
bool "Rockchip timer driver" if COMPILE_TEST
depends on ARM || ARM64

config ARMADA_370_XP_TIMER
bool "Armada 370 and XP timer driver" if COMPILE_TEST
depends on ARM

config ORION_TIMER
bool "Orion timer driver" if COMPILE_TEST
depends on ARM

config ARM_GLOBAL_TIMER
bool "Support for the ARM global timer" if COMPILE_TEST
select TIMER_OF if OF
depends on ARM

config CLKSRC_EXYNOS_MCT
bool "Exynos multi core timer driver" if COMPILE_TEST
depends on ARM || ARM64

david

> >   select CLKSRC_MMIO
> >   select TIMER_OF if OF
> >
> >
>
>
> --
>  <http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
>
> Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
> <http://twitter.com/#!/linaroorg> Twitter |
> <http://www.linaro.org/linaro-blog/> Blog
>

[PATCH][RESEND] Make ARM_TIMER_SP804 depend on (ARM || ARM64)

[David Abdurachmanov]

Resending to incl. a proper mailing list and maintainers (not suggested
by scripts/get_maintainer.pl)

This is only used on arm and arm64 platforms. Other timers also seem
to depend on (ARM || ARM64).

After I moved Fedora/RISCV kernel to 5.0.0-0.rc2 it keeps asking me to
add CONFIG_ARM_TIMER_SP804=n to my config. This patch resolved the issue.

Signed-off-by: David Abdurachmanov 
---
 drivers/clocksource/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index a9e26f6a81a1..7593d80e1c88 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -369,7 +369,7 @@ config ARM_GLOBAL_TIMER
 
 config ARM_TIMER_SP804
bool "Support for Dual Timer SP804 module"
-   depends on GENERIC_SCHED_CLOCK && CLKDEV_LOOKUP
+   depends on (ARM || ARM64) && GENERIC_SCHED_CLOCK && CLKDEV_LOOKUP
select CLKSRC_MMIO
select TIMER_OF if OF
 
-- 
2.20.1

Re: [v3 PATCH 8/8] RISC-V: Assign hwcap only according to boot cpu.

[David Abdurachmanov]

On Sat, Feb 9, 2019 at 12:03 AM Atish Patra  wrote:
>
> On 2/8/19 1:11 AM, Christoph Hellwig wrote:
> >> + * We don't support running Linux on hertergenous ISA systems.
> >> + * But first "okay" processor might not be the boot cpu.
> >> + * Check the ISA of boot cpu.
> >
> > Please use up your available 80 characters per line in comments.
> >
> I will fix it.
>
> >> +/*
> >> + * All "okay" hart should have same isa. We don't know how to
> >> + * handle if they don't. Throw a warning for now.
> >> + */
> >> +if (elf_hwcap && temp_hwcap != elf_hwcap)
> >> +pr_warn("isa mismatch: 0x%lx != 0x%lx\n",
> >> +elf_hwcap, temp_hwcap);
> >> +
> >> +if (hartid == boot_cpu_hartid)
> >> +boot_hwcap = temp_hwcap;
> >> +elf_hwcap = temp_hwcap;
> >
> > So we always set elf_hwcap to the capabilities of the previous cpu.
> >
> >> +temp_hwcap = 0;
> >
> > I think tmp_hwcap should be declared and initialized inside the outer loop
> > instead having to manually reset it like this.
> >
> >> +}
> >>
> >> +elf_hwcap = boot_hwcap;
> >
> > And then reset it here to the boot cpu.
> >
> > Shoudn't we only report the features supported by all cores?  Otherwise
> > we'll still have problems if the boot cpu supports a feature, but not
> > others.
> >
>
> Hmm. The other side of the argument is boot cpu does have a feature that
> is not supported by other hart that didn't even boot.
> The user space may execute something based on boot cpu capability but
> that won't be enabled.
>
> At least, in this way we know that we are compatible completely with
> boot cpu capabilities. Thoughts ?

There is one example on the market, e.g., Samsung Exynos 9810.

Mongoose 3 (big cores) only support ARMv8.0, while Cortex-A55
(little ones) support ARMv8.2 (and that brings atomics support).
I think, it's the only ARM SOC that supports different ISA extensions
between cores on the same package.

Kernel scheduler doesn't know that big cores are missing atomics
support or that applications needs it and moves the thread
resulting in illegal instruction.

E.g., see Golang issue: https://github.com/golang/go/issues/28431

I also recall Jon Masters (Computer Architect at Red Hat) advocating
against having cores with mismatched capabilities on the server market.

It just causes more problems down the line.

david

Re: [PATCH] riscv: Partially revert "Remove stat64 family from default syscall set"

[David Abdurachmanov]

On Thu, Feb 7, 2019 at 11:56 PM Alistair Francis
 wrote:
>
> To fix systemd/sysVinit crashes enable __ARCH_WANT_STAT64.
>
> systemd failed to start with this error for 32-bit RISC-V:
> [2.833864] Run /sbin/init as init process
> /sbin/init: error while loading shared libraries: libsystemd-shared-239.so: 
> cannot stat shared object: Error 38
> [2.933593] Kernel panic - not syncing: Attempted to kill init! 
> exitcode=0x7f00
> [2.934120] CPU: 0 PID: 1 Comm: init Not tainted 
> 5.0.0-rc4-yoctodev-standard #1
> [2.934589] Call Trace:
> [2.934919] [] walk_stackframe+0x0/0xa0
> [2.935243] [] show_stack+0x28/0x32
> [2.935518] [] dump_stack+0x68/0x88
> [2.935788] [] panic+0xf0/0x252
> [2.936041] [] do_exit+0x7de/0x7fc
> [2.936387] [] do_group_exit+0x2a/0x82
> [2.936674] [] __wake_up_parent+0x0/0x22
> [2.936982] [] ret_from_syscall+0x0/0xe
> [2.937673] ---[ end Kernel panic - not syncing: Attempted to kill init! 
> exitcode=0x7f00 ]---
>
> sysVinit had a similar problem as well. By enabling __ARCH_WANT_STAT64
> for 32-bit RISC-V the problem disapears and 32-bit RISC-V is able to
> boot.

Hi,

This is expected change for riscv32. More details here:
http://lists.infradead.org/pipermail/linux-riscv/2018-November/002062.html

david

>
> Signed-off-by: Alistair Francis 
> ---
> This was tested with this fork of glibc to enable 32-bit RISC-V support:
> https://github.com/riscv/riscv-glibc/tree/riscv-glibc-2.29
> commit: 04fdd476160a55792a75375ba2bf56c761f811c2
>
> I'm not sure if this is a glibc problem or a kernel problem, but this
> commit caused the breakage between the 4.19 and 4.20 kernel so I'm
> sending out a patch. Let me know your thoughts
>
> arch/riscv/include/uapi/asm/unistd.h | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/arch/riscv/include/uapi/asm/unistd.h 
> b/arch/riscv/include/uapi/asm/unistd.h
> index 1f3bd3ebbb0d..031b7d78e11c 100644
> --- a/arch/riscv/include/uapi/asm/unistd.h
> +++ b/arch/riscv/include/uapi/asm/unistd.h
> @@ -20,6 +20,9 @@
>  #endif /* __LP64__ */
>
>  #include 
> +#if __BITS_PER_LONG == 32
> +#define __ARCH_WANT_STAT64
> +#endif
>
>  /*
>   * Allows the instruction cache to be flushed from userspace.  Despite RISC-V
> --
> 2.20.1
>
>
> ___
> linux-riscv mailing list
> linux-ri...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

[PATCH] riscv: restore asm/syscalls.h UAPI header

[David Abdurachmanov]

UAPI header asm/syscalls.h was merged into UAPI asm/unistd.h header,
which did resolve issue with missing syscalls macros resulting in
glibc (2.28) build failure. It also broke glibc in a different way:
asm/syscalls.h is being used by glibc. I noticed this while doing
Fedora 30/Rawhide mass rebuild.

The patch returns asm/syscalls.h header and incl. it into asm/unistd.h.
I plan to send a patch to glibc to use asm/unistd.h instead of
asm/syscalls.h

Signed-off-by: David Abdurachmanov 
Fixes: 27f8899d6002 ("riscv: add asm/unistd.h UAPI header")
---
 arch/riscv/include/uapi/asm/syscalls.h | 29 ++
 arch/riscv/include/uapi/asm/unistd.h   | 20 +-
 2 files changed, 30 insertions(+), 19 deletions(-)
 create mode 100644 arch/riscv/include/uapi/asm/syscalls.h

diff --git a/arch/riscv/include/uapi/asm/syscalls.h 
b/arch/riscv/include/uapi/asm/syscalls.h
new file mode 100644
index ..206dc4b0f6ea
--- /dev/null
+++ b/arch/riscv/include/uapi/asm/syscalls.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2017-2018 SiFive
+ */
+
+/*
+ * There is explicitly no include guard here because this file is expected to
+ * be included multiple times in order to define the syscall macros via
+ * __SYSCALL.
+ */
+
+/*
+ * Allows the instruction cache to be flushed from userspace.  Despite RISC-V
+ * having a direct 'fence.i' instruction available to userspace (which we
+ * can't trap!), that's not actually viable when running on Linux because the
+ * kernel might schedule a process on another hart.  There is no way for
+ * userspace to handle this without invoking the kernel (as it doesn't know the
+ * thread->hart mappings), so we've defined a RISC-V specific system call to
+ * flush the instruction cache.
+ *
+ * __NR_riscv_flush_icache is defined to flush the instruction cache over an
+ * address range, with the flush applying to either all threads or just the
+ * caller.  We don't currently do anything with the address range, that's just
+ * in there for forwards compatibility.
+ */
+#ifndef __NR_riscv_flush_icache
+#define __NR_riscv_flush_icache (__NR_arch_specific_syscall + 15)
+#endif
+__SYSCALL(__NR_riscv_flush_icache, sys_riscv_flush_icache)
diff --git a/arch/riscv/include/uapi/asm/unistd.h 
b/arch/riscv/include/uapi/asm/unistd.h
index 1f3bd3ebbb0d..06103139db50 100644
--- a/arch/riscv/include/uapi/asm/unistd.h
+++ b/arch/riscv/include/uapi/asm/unistd.h
@@ -20,22 +20,4 @@
 #endif /* __LP64__ */
 
 #include 
-
-/*
- * Allows the instruction cache to be flushed from userspace.  Despite RISC-V
- * having a direct 'fence.i' instruction available to userspace (which we
- * can't trap!), that's not actually viable when running on Linux because the
- * kernel might schedule a process on another hart.  There is no way for
- * userspace to handle this without invoking the kernel (as it doesn't know the
- * thread->hart mappings), so we've defined a RISC-V specific system call to
- * flush the instruction cache.
- *
- * __NR_riscv_flush_icache is defined to flush the instruction cache over an
- * address range, with the flush applying to either all threads or just the
- * caller.  We don't currently do anything with the address range, that's just
- * in there for forwards compatibility.
- */
-#ifndef __NR_riscv_flush_icache
-#define __NR_riscv_flush_icache (__NR_arch_specific_syscall + 15)
-#endif
-__SYSCALL(__NR_riscv_flush_icache, sys_riscv_flush_icache)
+#include 
-- 
2.19.2

Re: [PATCH 0/2] riscv: enable syscalls tracepoints

[David Abdurachmanov]

On Fri, Dec 7, 2018 at 9:32 PM Palmer Dabbelt  wrote:
>
> On Thu, 06 Dec 2018 07:26:33 PST (-0800), david.abdurachma...@gmail.com wrote:
> > Depends on audit patch:
> > http://lists.infradead.org/pipermail/linux-riscv/2018-October/001931.html
> >
> > audit patch is already merged into linux-next.
> >
> > This simply fixes compilation error in do_syscall_trace_exit() and
> > enables syscalls tracepoints.
> >
> > David Abdurachmanov (2):
> >   riscv: fix trace_sys_exit hook
> >   riscv: add HAVE_SYSCALL_TRACEPOINTS to Kconfig
> >
> >  arch/riscv/Kconfig | 1 +
> >  arch/riscv/kernel/ptrace.c | 2 +-
> >  2 files changed, 2 insertions(+), 1 deletion(-)
>
> I've attempted to add this on top of next-audit, which I've merged into
> for-next.  Let me know if something went wrong.

Two things:
- The order of commits are wrong. Right now the commits are in
  reverse order, i.e. audit patches are on top.
- Intel kbuild test bot found compilation errors with riscv-allmodconfig
  config. I fixed those and posted two patches:
  http://lists.infradead.org/pipermail/linux-riscv/2018-December/002508.html

[PATCH 2/2] riscv: define CREATE_TRACE_POINTS in ptrace.c

[David Abdurachmanov]

Define CREATE_TRACE_POINTS in order to create functions and structures
for the trace events. This is needed if HAVE_SYSCALL_TRACEPOINTS and
CONFIG_FTRACE_SYSCALLS are enabled, otherwise we get linking errors:

[..]
  MODPOST vmlinux.o
kernel/trace/trace_syscalls.o: In function `.L0 ':
trace_syscalls.c:(.text+0x1152): undefined reference to `__tracepoint_sys_enter'
trace_syscalls.c:(.text+0x126c): undefined reference to `__tracepoint_sys_enter'
trace_syscalls.c:(.text+0x1328): undefined reference to `__tracepoint_sys_enter'
trace_syscalls.c:(.text+0x14aa): undefined reference to `__tracepoint_sys_enter'
trace_syscalls.c:(.text+0x1684): undefined reference to `__tracepoint_sys_exit'
trace_syscalls.c:(.text+0x17a0): undefined reference to `__tracepoint_sys_exit'
trace_syscalls.c:(.text+0x185c): undefined reference to `__tracepoint_sys_exit'
trace_syscalls.c:(.text+0x19de): undefined reference to `__tracepoint_sys_exit'
arch/riscv/kernel/ptrace.o: In function `.L0 ':
ptrace.c:(.text+0x4dc): undefined reference to `__tracepoint_sys_enter'
ptrace.c:(.text+0x632): undefined reference to `__tracepoint_sys_exit'
make: *** [Makefile:1036: vmlinux] Error 1

Signed-off-by: David Abdurachmanov 
Fixes: b78002b395b4 ("riscv: add HAVE_SYSCALL_TRACEPOINTS to Kconfig")
---
 arch/riscv/kernel/ptrace.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/riscv/kernel/ptrace.c b/arch/riscv/kernel/ptrace.c
index 60f1e02eed36..32a374a1b31a 100644
--- a/arch/riscv/kernel/ptrace.c
+++ b/arch/riscv/kernel/ptrace.c
@@ -24,6 +24,8 @@
 #include 
 #include 
 #include 
+
+#define CREATE_TRACE_POINTS
 #include 
 
 enum riscv_regset {
-- 
2.19.2

[PATCH 0/2] Fix next-audit branch

[David Abdurachmanov]

Intel kbuild test robot reported on Dec 8th, 2018 that next-audit is
broken. This was with riscv-allmodconfig config.

There were two issues found:
- We don't generate functions needed for trace events;
- We are missing NR_syscalls macro used by kernel/trace.

David Abdurachmanov (2):
  riscv: define NR_syscalls in unistd.h
  riscv: define CREATE_TRACE_POINTS in ptrace.c

 arch/riscv/include/asm/unistd.h | 2 ++
 arch/riscv/kernel/ptrace.c  | 2 ++
 2 files changed, 4 insertions(+)

-- 
2.19.2

[PATCH 1/2] riscv: define NR_syscalls in unistd.h

[David Abdurachmanov]

This macro is used by kernel/trace/{trace.h,trace_syscalls.c} if we
have CONFIG_FTRACE_SYSCALLS enabled.

Signed-off-by: David Abdurachmanov 
Fixes: b78002b395b4 ("riscv: add HAVE_SYSCALL_TRACEPOINTS to Kconfig")
---
 arch/riscv/include/asm/unistd.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/riscv/include/asm/unistd.h b/arch/riscv/include/asm/unistd.h
index fef96f117b4d..073ee80fdf74 100644
--- a/arch/riscv/include/asm/unistd.h
+++ b/arch/riscv/include/asm/unistd.h
@@ -19,3 +19,5 @@
 #define __ARCH_WANT_SYS_CLONE
 
 #include 
+
+#define NR_syscalls (__NR_syscalls)
-- 
2.19.2

Re: [PATCH 1/2] riscv: add support for SECCOMP incl. filters

[David Abdurachmanov]

On Thu, Dec 6, 2018 at 5:52 PM Kees Cook  wrote:
>
> On Thu, Dec 6, 2018 at 7:02 AM David Abdurachmanov
>  wrote:
> > The patch adds support for SECCOMP and SECCOMP_FILTER (BPF).
>
> Can you add support to tools/testing/selftests/seccomp/seccomp_bpf.c
> as well? That selftest finds a lot of weird corner-cases...

I hate it locally and will include in v2.

The results see fine (tested in QEMU).

TAP version 13
selftests: seccomp: seccomp_bpf

[==] Running 64 tests from 1 test cases.
[ RUN  ] global.mode_strict_support
[   OK ] global.mode_strict_support
[ RUN  ] global.mode_strict_cannot_call_prctl
[   OK ] global.mode_strict_cannot_call_prctl
[ RUN  ] global.no_new_privs_support
[   OK ] global.no_new_privs_support
[ RUN  ] global.mode_filter_support
[   OK ] global.mode_filter_support
[ RUN  ] global.mode_filter_without_nnp
[   OK ] global.mode_filter_without_nnp
[ RUN  ] global.filter_size_limits
[   OK ] global.filter_size_limits
[ RUN  ] global.filter_chain_limits
[   OK ] global.filter_chain_limits
[ RUN  ] global.mode_filter_cannot_move_to_strict
[   OK ] global.mode_filter_cannot_move_to_strict
[ RUN  ] global.mode_filter_get_seccomp
[   OK ] global.mode_filter_get_seccomp
[ RUN  ] global.ALLOW_all
[   OK ] global.ALLOW_all
[ RUN  ] global.empty_prog
[   OK ] global.empty_prog
[ RUN  ] global.log_all
[   OK ] global.log_all
[ RUN  ] global.unknown_ret_is_kill_inside
[   OK ] global.unknown_ret_is_kill_inside
[ RUN  ] global.unknown_ret_is_kill_above_allow
[   OK ] global.unknown_ret_is_kill_above_allow
[ RUN  ] global.KILL_all
[   OK ] global.KILL_all
[ RUN  ] global.KILL_one
[   OK ] global.KILL_one
[ RUN  ] global.KILL_one_arg_one
[   OK ] global.KILL_one_arg_one
[ RUN  ] global.KILL_one_arg_six
[   OK ] global.KILL_one_arg_six
[ RUN  ] global.KILL_thread
[   OK ] global.KILL_thread
[ RUN  ] global.KILL_process
[   OK ] global.KILL_process
[ RUN  ] global.arg_out_of_range
[   OK ] global.arg_out_of_range
[ RUN  ] global.ERRNO_valid
[   OK ] global.ERRNO_valid
[ RUN  ] global.ERRNO_zero
[   OK ] global.ERRNO_zero
[ RUN  ] global.ERRNO_capped
[   OK ] global.ERRNO_capped
[ RUN  ] global.ERRNO_order
[   OK ] global.ERRNO_order
[ RUN  ] TRAP.dfl
[   OK ] TRAP.dfl
[ RUN  ] TRAP.ign
[   OK ] TRAP.ign
[ RUN  ] TRAP.handler
[   OK ] TRAP.handler
[ RUN  ] precedence.allow_ok
[   OK ] precedence.allow_ok
[ RUN  ] precedence.kill_is_highest
[   OK ] precedence.kill_is_highest
[ RUN  ] precedence.kill_is_highest_in_any_order
[   OK ] precedence.kill_is_highest_in_any_order
[ RUN  ] precedence.trap_is_second
[   OK ] precedence.trap_is_second
[ RUN  ] precedence.trap_is_second_in_any_order
[   OK ] precedence.trap_is_second_in_any_order
[ RUN  ] precedence.errno_is_third
[   OK ] precedence.errno_is_third
[ RUN  ] precedence.errno_is_third_in_any_order
[   OK ] precedence.errno_is_third_in_any_order
[ RUN  ] precedence.trace_is_fourth
[   OK ] precedence.trace_is_fourth
[ RUN  ] precedence.trace_is_fourth_in_any_order
[   OK ] precedence.trace_is_fourth_in_any_order
[ RUN  ] precedence.log_is_fifth
[   OK ] precedence.log_is_fifth
[ RUN  ] precedence.log_is_fifth_in_any_order
[   OK ] precedence.log_is_fifth_in_any_order
[ RUN  ] TRACE_poke.read_has_side_effects
[   OK ] TRACE_poke.read_has_side_effects
[ RUN  ] TRACE_poke.getpid_runs_normally
[   OK ] TRACE_poke.getpid_runs_normally
[ RUN  ] TRACE_syscall.ptrace_syscall_redirected
[   OK ] TRACE_syscall.ptrace_syscall_redirected
[ RUN  ] TRACE_syscall.ptrace_syscall_dropped
[   OK ] TRACE_syscall.ptrace_syscall_dropped
[ RUN  ] TRACE_syscall.syscall_allowed
[   OK ] TRACE_syscall.syscall_allowed
[ RUN  ] TRACE_syscall.syscall_redirected
[   OK ] TRACE_syscall.syscall_redirected
[ RUN  ] TRACE_syscall.syscall_dropped
[   OK ] TRACE_syscall.syscall_dropped
[ RUN  ] TRACE_syscall.skip_after_RET_TRACE
[   OK ] TRACE_syscall.skip_after_RET_TRACE
[ RUN  ] TRACE_syscall.kill_after_RET_TRACE
[   OK ] TRACE_syscall.kill_after_RET_TRACE
[ RUN  ] TRACE_syscall.skip_after_ptrace
[   OK ] TRACE_syscall.skip_after_ptrace
[ RUN  ] TRACE_syscall.kill_after_ptrace
[   OK ] TRACE_syscall.kill_after_ptrace
[ RUN  ] global.seccomp_syscall
[   OK ] global.seccomp_syscall
[ RUN  ] global.seccomp_syscall_mode_lock
[   OK ] global.seccomp_syscall_mode_lock
[ RUN  ] global.detect_seccomp_filter_flags
[   OK ] global.detect_seccomp_filter_flags
[ RUN  ] global.TSYNC_first
[   OK ] global.TSYNC_first
[ RUN  ] TSYNC.siblings_fail_prctl
[   OK ] TSYNC.s

Re: [PATCH 1/2] riscv: add support for SECCOMP incl. filters

[David Abdurachmanov]

On Thu, Dec 6, 2018 at 5:52 PM Kees Cook  wrote:
>
> On Thu, Dec 6, 2018 at 7:02 AM David Abdurachmanov
>  wrote:
> > The patch adds support for SECCOMP and SECCOMP_FILTER (BPF).
>
> Can you add support to tools/testing/selftests/seccomp/seccomp_bpf.c
> as well? That selftest finds a lot of weird corner-cases...

I hate it locally and will include in v2.

The results see fine (tested in QEMU).

TAP version 13
selftests: seccomp: seccomp_bpf

[==] Running 64 tests from 1 test cases.
[ RUN  ] global.mode_strict_support
[   OK ] global.mode_strict_support
[ RUN  ] global.mode_strict_cannot_call_prctl
[   OK ] global.mode_strict_cannot_call_prctl
[ RUN  ] global.no_new_privs_support
[   OK ] global.no_new_privs_support
[ RUN  ] global.mode_filter_support
[   OK ] global.mode_filter_support
[ RUN  ] global.mode_filter_without_nnp
[   OK ] global.mode_filter_without_nnp
[ RUN  ] global.filter_size_limits
[   OK ] global.filter_size_limits
[ RUN  ] global.filter_chain_limits
[   OK ] global.filter_chain_limits
[ RUN  ] global.mode_filter_cannot_move_to_strict
[   OK ] global.mode_filter_cannot_move_to_strict
[ RUN  ] global.mode_filter_get_seccomp
[   OK ] global.mode_filter_get_seccomp
[ RUN  ] global.ALLOW_all
[   OK ] global.ALLOW_all
[ RUN  ] global.empty_prog
[   OK ] global.empty_prog
[ RUN  ] global.log_all
[   OK ] global.log_all
[ RUN  ] global.unknown_ret_is_kill_inside
[   OK ] global.unknown_ret_is_kill_inside
[ RUN  ] global.unknown_ret_is_kill_above_allow
[   OK ] global.unknown_ret_is_kill_above_allow
[ RUN  ] global.KILL_all
[   OK ] global.KILL_all
[ RUN  ] global.KILL_one
[   OK ] global.KILL_one
[ RUN  ] global.KILL_one_arg_one
[   OK ] global.KILL_one_arg_one
[ RUN  ] global.KILL_one_arg_six
[   OK ] global.KILL_one_arg_six
[ RUN  ] global.KILL_thread
[   OK ] global.KILL_thread
[ RUN  ] global.KILL_process
[   OK ] global.KILL_process
[ RUN  ] global.arg_out_of_range
[   OK ] global.arg_out_of_range
[ RUN  ] global.ERRNO_valid
[   OK ] global.ERRNO_valid
[ RUN  ] global.ERRNO_zero
[   OK ] global.ERRNO_zero
[ RUN  ] global.ERRNO_capped
[   OK ] global.ERRNO_capped
[ RUN  ] global.ERRNO_order
[   OK ] global.ERRNO_order
[ RUN  ] TRAP.dfl
[   OK ] TRAP.dfl
[ RUN  ] TRAP.ign
[   OK ] TRAP.ign
[ RUN  ] TRAP.handler
[   OK ] TRAP.handler
[ RUN  ] precedence.allow_ok
[   OK ] precedence.allow_ok
[ RUN  ] precedence.kill_is_highest
[   OK ] precedence.kill_is_highest
[ RUN  ] precedence.kill_is_highest_in_any_order
[   OK ] precedence.kill_is_highest_in_any_order
[ RUN  ] precedence.trap_is_second
[   OK ] precedence.trap_is_second
[ RUN  ] precedence.trap_is_second_in_any_order
[   OK ] precedence.trap_is_second_in_any_order
[ RUN  ] precedence.errno_is_third
[   OK ] precedence.errno_is_third
[ RUN  ] precedence.errno_is_third_in_any_order
[   OK ] precedence.errno_is_third_in_any_order
[ RUN  ] precedence.trace_is_fourth
[   OK ] precedence.trace_is_fourth
[ RUN  ] precedence.trace_is_fourth_in_any_order
[   OK ] precedence.trace_is_fourth_in_any_order
[ RUN  ] precedence.log_is_fifth
[   OK ] precedence.log_is_fifth
[ RUN  ] precedence.log_is_fifth_in_any_order
[   OK ] precedence.log_is_fifth_in_any_order
[ RUN  ] TRACE_poke.read_has_side_effects
[   OK ] TRACE_poke.read_has_side_effects
[ RUN  ] TRACE_poke.getpid_runs_normally
[   OK ] TRACE_poke.getpid_runs_normally
[ RUN  ] TRACE_syscall.ptrace_syscall_redirected
[   OK ] TRACE_syscall.ptrace_syscall_redirected
[ RUN  ] TRACE_syscall.ptrace_syscall_dropped
[   OK ] TRACE_syscall.ptrace_syscall_dropped
[ RUN  ] TRACE_syscall.syscall_allowed
[   OK ] TRACE_syscall.syscall_allowed
[ RUN  ] TRACE_syscall.syscall_redirected
[   OK ] TRACE_syscall.syscall_redirected
[ RUN  ] TRACE_syscall.syscall_dropped
[   OK ] TRACE_syscall.syscall_dropped
[ RUN  ] TRACE_syscall.skip_after_RET_TRACE
[   OK ] TRACE_syscall.skip_after_RET_TRACE
[ RUN  ] TRACE_syscall.kill_after_RET_TRACE
[   OK ] TRACE_syscall.kill_after_RET_TRACE
[ RUN  ] TRACE_syscall.skip_after_ptrace
[   OK ] TRACE_syscall.skip_after_ptrace
[ RUN  ] TRACE_syscall.kill_after_ptrace
[   OK ] TRACE_syscall.kill_after_ptrace
[ RUN  ] global.seccomp_syscall
[   OK ] global.seccomp_syscall
[ RUN  ] global.seccomp_syscall_mode_lock
[   OK ] global.seccomp_syscall_mode_lock
[ RUN  ] global.detect_seccomp_filter_flags
[   OK ] global.detect_seccomp_filter_flags
[ RUN  ] global.TSYNC_first
[   OK ] global.TSYNC_first
[ RUN  ] TSYNC.siblings_fail_prctl
[   OK ] TSYNC.s

Re: [PATCH 1/2] riscv: add support for SECCOMP incl. filters

[David Abdurachmanov]

On Thu, Dec 6, 2018 at 6:07 PM Kees Cook  wrote:
>
> On Thu, Dec 6, 2018 at 7:02 AM David Abdurachmanov
>  wrote:
> > The patch adds support for SECCOMP and SECCOMP_FILTER (BPF).
>
> I built this against linux-next but it's missing seccomp.h. Was that
> accidentally left out of the commit?
>
>
>   CC  arch/riscv/kernel/asm-offsets.s
> In file included from ./include/linux/sched.h:21:0,
>  from arch/riscv/kernel/asm-offsets.c:18:
> ./include/linux/seccomp.h:14:10: fatal error: asm/seccomp.h: No such
> file or directory
>  #include 
>   ^~~
>

I forgot to add it...
Will fix it.

david

Re: [PATCH 1/2] riscv: add support for SECCOMP incl. filters

[David Abdurachmanov]

On Thu, Dec 6, 2018 at 6:07 PM Kees Cook  wrote:
>
> On Thu, Dec 6, 2018 at 7:02 AM David Abdurachmanov
>  wrote:
> > The patch adds support for SECCOMP and SECCOMP_FILTER (BPF).
>
> I built this against linux-next but it's missing seccomp.h. Was that
> accidentally left out of the commit?
>
>
>   CC  arch/riscv/kernel/asm-offsets.s
> In file included from ./include/linux/sched.h:21:0,
>  from arch/riscv/kernel/asm-offsets.c:18:
> ./include/linux/seccomp.h:14:10: fatal error: asm/seccomp.h: No such
> file or directory
>  #include 
>   ^~~
>

I forgot to add it...
Will fix it.

david

Re: [PATCH 2/2] riscv: fix syscall_{get,set}_arguments

[David Abdurachmanov]

On Thu, Dec 6, 2018 at 5:49 PM Kees Cook  wrote:
>
> On Thu, Dec 6, 2018 at 7:02 AM David Abdurachmanov
>  wrote:
> >
> > Testing with libseccomp master branch revealed that testcases with
> > filters on syscall arguments were failing due to wrong values. Seccomp
> > uses syscall_get_argumentsi() to copy syscall arguments, and there is a
> > bug in pointer arithmetics in memcpy() call.
> >
> > Two alternative implementation were tested: the one in this patch and
> > another one based on while-break loop. Both delivered the same results.
> >
> > This implementation is also used in arm, arm64 and nds32 arches.
>
> Minor nit: can you make this the first patch? That way seccomp works
> correctly from the point of introduction. :)

Ok. I will do it.

david

>
> -Kees
>
> >
> > Signed-off-by: David Abdurachmanov 
> > ---
> >  arch/riscv/include/asm/syscall.h | 42 
> >  1 file changed, 32 insertions(+), 10 deletions(-)
> >
> > diff --git a/arch/riscv/include/asm/syscall.h 
> > b/arch/riscv/include/asm/syscall.h
> > index bba3da6ef157..26ceb434a433 100644
> > --- a/arch/riscv/include/asm/syscall.h
> > +++ b/arch/riscv/include/asm/syscall.h
> > @@ -70,19 +70,32 @@ static inline void syscall_set_return_value(struct 
> > task_struct *task,
> > regs->a0 = (long) error ?: val;
> >  }
> >
> > +#define SYSCALL_MAX_ARGS 6
> > +
> >  static inline void syscall_get_arguments(struct task_struct *task,
> >  struct pt_regs *regs,
> >  unsigned int i, unsigned int n,
> >  unsigned long *args)
> >  {
> > -   BUG_ON(i + n > 6);
> > +   if (n == 0)
> > +   return;
> > +
> > +   if (i + n > SYSCALL_MAX_ARGS) {
> > +   unsigned long *args_bad = args + SYSCALL_MAX_ARGS - i;
> > +   unsigned int n_bad = n + i - SYSCALL_MAX_ARGS;
> > +   pr_warning("%s called with max args %d, handling only %d\n",
> > +   __func__, i + n, SYSCALL_MAX_ARGS);
> > +   memset(args_bad, 0, n_bad * sizeof(args[0]));
> > +   }
> > +
> > if (i == 0) {
> > args[0] = regs->orig_a0;
> > args++;
> > i++;
> > n--;
> > }
> > -   memcpy(args, >a1 + i * sizeof(regs->a1), n * sizeof(args[0]));
> > +
> > +   memcpy(args, >a0 + i, n * sizeof(args[0]));
> >  }
> >
> >  static inline void syscall_set_arguments(struct task_struct *task,
> > @@ -90,14 +103,23 @@ static inline void syscall_set_arguments(struct 
> > task_struct *task,
> >  unsigned int i, unsigned int n,
> >  const unsigned long *args)
> >  {
> > -   BUG_ON(i + n > 6);
> > -if (i == 0) {
> > -regs->orig_a0 = args[0];
> > -args++;
> > -i++;
> > -n--;
> > -}
> > -   memcpy(>a1 + i * sizeof(regs->a1), args, n * 
> > sizeof(regs->a0));
> > +   if (n == 0)
> > +   return;
> > +
> > +   if (i + n > SYSCALL_MAX_ARGS) {
> > +   pr_warning("%s called with max args %d, handling only %d\n",
> > +   __func__, i + n, SYSCALL_MAX_ARGS);
> > +   n = SYSCALL_MAX_ARGS - i;
> > +   }
> > +
> > +   if (i == 0) {
> > +   regs->orig_a0 = args[0];
> > +   args++;
> > +   i++;
> > +   n--;
> > +   }
> > +
> > +   memcpy(>a0 + i, args, n * sizeof(args[0]));
> >  }
> >
> >  static inline int syscall_get_arch(void)
> > --
> > 2.19.2
> >
>
>
> --
> Kees Cook

Re: [PATCH 2/2] riscv: fix syscall_{get,set}_arguments

[David Abdurachmanov]

On Thu, Dec 6, 2018 at 5:49 PM Kees Cook  wrote:
>
> On Thu, Dec 6, 2018 at 7:02 AM David Abdurachmanov
>  wrote:
> >
> > Testing with libseccomp master branch revealed that testcases with
> > filters on syscall arguments were failing due to wrong values. Seccomp
> > uses syscall_get_argumentsi() to copy syscall arguments, and there is a
> > bug in pointer arithmetics in memcpy() call.
> >
> > Two alternative implementation were tested: the one in this patch and
> > another one based on while-break loop. Both delivered the same results.
> >
> > This implementation is also used in arm, arm64 and nds32 arches.
>
> Minor nit: can you make this the first patch? That way seccomp works
> correctly from the point of introduction. :)

Ok. I will do it.

david

>
> -Kees
>
> >
> > Signed-off-by: David Abdurachmanov 
> > ---
> >  arch/riscv/include/asm/syscall.h | 42 
> >  1 file changed, 32 insertions(+), 10 deletions(-)
> >
> > diff --git a/arch/riscv/include/asm/syscall.h 
> > b/arch/riscv/include/asm/syscall.h
> > index bba3da6ef157..26ceb434a433 100644
> > --- a/arch/riscv/include/asm/syscall.h
> > +++ b/arch/riscv/include/asm/syscall.h
> > @@ -70,19 +70,32 @@ static inline void syscall_set_return_value(struct 
> > task_struct *task,
> > regs->a0 = (long) error ?: val;
> >  }
> >
> > +#define SYSCALL_MAX_ARGS 6
> > +
> >  static inline void syscall_get_arguments(struct task_struct *task,
> >  struct pt_regs *regs,
> >  unsigned int i, unsigned int n,
> >  unsigned long *args)
> >  {
> > -   BUG_ON(i + n > 6);
> > +   if (n == 0)
> > +   return;
> > +
> > +   if (i + n > SYSCALL_MAX_ARGS) {
> > +   unsigned long *args_bad = args + SYSCALL_MAX_ARGS - i;
> > +   unsigned int n_bad = n + i - SYSCALL_MAX_ARGS;
> > +   pr_warning("%s called with max args %d, handling only %d\n",
> > +   __func__, i + n, SYSCALL_MAX_ARGS);
> > +   memset(args_bad, 0, n_bad * sizeof(args[0]));
> > +   }
> > +
> > if (i == 0) {
> > args[0] = regs->orig_a0;
> > args++;
> > i++;
> > n--;
> > }
> > -   memcpy(args, >a1 + i * sizeof(regs->a1), n * sizeof(args[0]));
> > +
> > +   memcpy(args, >a0 + i, n * sizeof(args[0]));
> >  }
> >
> >  static inline void syscall_set_arguments(struct task_struct *task,
> > @@ -90,14 +103,23 @@ static inline void syscall_set_arguments(struct 
> > task_struct *task,
> >  unsigned int i, unsigned int n,
> >  const unsigned long *args)
> >  {
> > -   BUG_ON(i + n > 6);
> > -if (i == 0) {
> > -regs->orig_a0 = args[0];
> > -args++;
> > -i++;
> > -n--;
> > -}
> > -   memcpy(>a1 + i * sizeof(regs->a1), args, n * 
> > sizeof(regs->a0));
> > +   if (n == 0)
> > +   return;
> > +
> > +   if (i + n > SYSCALL_MAX_ARGS) {
> > +   pr_warning("%s called with max args %d, handling only %d\n",
> > +   __func__, i + n, SYSCALL_MAX_ARGS);
> > +   n = SYSCALL_MAX_ARGS - i;
> > +   }
> > +
> > +   if (i == 0) {
> > +   regs->orig_a0 = args[0];
> > +   args++;
> > +   i++;
> > +   n--;
> > +   }
> > +
> > +   memcpy(>a0 + i, args, n * sizeof(args[0]));
> >  }
> >
> >  static inline int syscall_get_arch(void)
> > --
> > 2.19.2
> >
>
>
> --
> Kees Cook

Re: [PATCH 1/2] riscv: add support for SECCOMP incl. filters

[David Abdurachmanov]

On Thu, Dec 6, 2018 at 5:52 PM Kees Cook  wrote:
>
> On Thu, Dec 6, 2018 at 7:02 AM David Abdurachmanov
>  wrote:
> > The patch adds support for SECCOMP and SECCOMP_FILTER (BPF).
>
> Can you add support to tools/testing/selftests/seccomp/seccomp_bpf.c
> as well? That selftest finds a lot of weird corner-cases...
>
> > diff --git a/arch/riscv/include/asm/thread_info.h 
> > b/arch/riscv/include/asm/thread_info.h
> > index 1c9cc8389928..1fd6e4130cab 100644
> > --- a/arch/riscv/include/asm/thread_info.h
> > +++ b/arch/riscv/include/asm/thread_info.h
> > @@ -81,6 +81,7 @@ struct thread_info {
> >  #define TIF_MEMDIE 5   /* is terminating due to OOM killer 
> > */
> >  #define TIF_SYSCALL_TRACEPOINT  6   /* syscall tracepoint 
> > instrumentation */
> >  #define TIF_SYSCALL_AUDIT  7   /* syscall auditing */
> > +#define TIF_SECCOMP8   /* syscall secure computing 
> > */
>
> Nit: extra tab needs to be removed.

Will fix it.
I need to cleanup my vim configuration for tab with.

david

Re: [PATCH 1/2] riscv: add support for SECCOMP incl. filters

[David Abdurachmanov]

On Thu, Dec 6, 2018 at 5:52 PM Kees Cook  wrote:
>
> On Thu, Dec 6, 2018 at 7:02 AM David Abdurachmanov
>  wrote:
> > The patch adds support for SECCOMP and SECCOMP_FILTER (BPF).
>
> Can you add support to tools/testing/selftests/seccomp/seccomp_bpf.c
> as well? That selftest finds a lot of weird corner-cases...
>
> > diff --git a/arch/riscv/include/asm/thread_info.h 
> > b/arch/riscv/include/asm/thread_info.h
> > index 1c9cc8389928..1fd6e4130cab 100644
> > --- a/arch/riscv/include/asm/thread_info.h
> > +++ b/arch/riscv/include/asm/thread_info.h
> > @@ -81,6 +81,7 @@ struct thread_info {
> >  #define TIF_MEMDIE 5   /* is terminating due to OOM killer 
> > */
> >  #define TIF_SYSCALL_TRACEPOINT  6   /* syscall tracepoint 
> > instrumentation */
> >  #define TIF_SYSCALL_AUDIT  7   /* syscall auditing */
> > +#define TIF_SECCOMP8   /* syscall secure computing 
> > */
>
> Nit: extra tab needs to be removed.

Will fix it.
I need to cleanup my vim configuration for tab with.

david

Re: [PATCH 1/2] riscv: add support for SECCOMP incl. filters

[David Abdurachmanov]

On Thu, Dec 6, 2018 at 5:47 PM Kees Cook  wrote:
>
> On Thu, Dec 6, 2018 at 7:02 AM David Abdurachmanov
>  wrote:
> >
> > The patch adds support for SECCOMP and SECCOMP_FILTER (BPF).
> >
> > Signed-off-by: David Abdurachmanov 
> > ---
> >  arch/riscv/Kconfig   | 14 ++
> >  arch/riscv/include/asm/thread_info.h |  5 -
> >  arch/riscv/kernel/entry.S| 27 +--
> >  arch/riscv/kernel/ptrace.c   |  8 
> >  4 files changed, 51 insertions(+), 3 deletions(-)
> >
> > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> > index a4f48f757204..49cd8e251547 100644
> > --- a/arch/riscv/Kconfig
> > +++ b/arch/riscv/Kconfig
> > @@ -29,6 +29,7 @@ config RISCV
> > select GENERIC_SMP_IDLE_THREAD
> > select GENERIC_ATOMIC64 if !64BIT || !RISCV_ISA_A
> > select HAVE_ARCH_AUDITSYSCALL
> > +   select HAVE_ARCH_SECCOMP_FILTER
> > select HAVE_MEMBLOCK_NODE_MAP
> > select HAVE_DMA_CONTIGUOUS
> > select HAVE_FUTEX_CMPXCHG if FUTEX
> > @@ -228,6 +229,19 @@ menu "Kernel features"
> >
> >  source "kernel/Kconfig.hz"
> >
> > +config SECCOMP
> > +   bool "Enable seccomp to safely compute untrusted bytecode"
> > +   help
> > + This kernel feature is useful for number crunching applications
> > + that may need to compute untrusted bytecode during their
> > + execution. By using pipes or other transports made available to
> > + the process as file descriptors supporting the read/write
> > + syscalls, it's possible to isolate those applications in
> > + their own address space using seccomp. Once seccomp is
> > + enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
> > + and the task is only allowed to execute a few safe syscalls
> > + defined by each seccomp mode.
> > +
> >  endmenu
> >
> >  menu "Boot options"
> > diff --git a/arch/riscv/include/asm/thread_info.h 
> > b/arch/riscv/include/asm/thread_info.h
> > index 1c9cc8389928..1fd6e4130cab 100644
> > --- a/arch/riscv/include/asm/thread_info.h
> > +++ b/arch/riscv/include/asm/thread_info.h
> > @@ -81,6 +81,7 @@ struct thread_info {
> >  #define TIF_MEMDIE 5   /* is terminating due to OOM killer 
> > */
> >  #define TIF_SYSCALL_TRACEPOINT  6   /* syscall tracepoint 
> > instrumentation */
> >  #define TIF_SYSCALL_AUDIT  7   /* syscall auditing */
> > +#define TIF_SECCOMP8   /* syscall secure computing 
> > */
> >
> >  #define _TIF_SYSCALL_TRACE (1 << TIF_SYSCALL_TRACE)
> >  #define _TIF_NOTIFY_RESUME (1 << TIF_NOTIFY_RESUME)
> > @@ -88,11 +89,13 @@ struct thread_info {
> >  #define _TIF_NEED_RESCHED  (1 << TIF_NEED_RESCHED)
> >  #define _TIF_SYSCALL_TRACEPOINT(1 << TIF_SYSCALL_TRACEPOINT)
> >  #define _TIF_SYSCALL_AUDIT (1 << TIF_SYSCALL_AUDIT)
> > +#define _TIF_SECCOMP   (1 << TIF_SECCOMP)
> >
> >  #define _TIF_WORK_MASK \
> > (_TIF_NOTIFY_RESUME | _TIF_SIGPENDING | _TIF_NEED_RESCHED)
> >
> >  #define _TIF_SYSCALL_WORK \
> > -   (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_TRACEPOINT | _TIF_SYSCALL_AUDIT)
> > +   (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_TRACEPOINT | _TIF_SYSCALL_AUDIT \
> > +_TIF_SECCOMP )
> >
> >  #endif /* _ASM_RISCV_THREAD_INFO_H */
> > diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
> > index 355166f57205..e88ccbfa61ee 100644
> > --- a/arch/riscv/kernel/entry.S
> > +++ b/arch/riscv/kernel/entry.S
> > @@ -207,8 +207,25 @@ check_syscall_nr:
> > /* Check to make sure we don't jump to a bogus syscall number. */
> > li t0, __NR_syscalls
> > la s0, sys_ni_syscall
> > -   /* Syscall number held in a7 */
> > -   bgeu a7, t0, 1f
> > +   /*
> > +* The tracer can change syscall number to valid/invalid value.
> > +* We use syscall_set_nr helper in syscall_trace_enter thus we
> > +* cannot trust the current value in a7 and have to reload from
> > +* the current task pt_regs.
> > +*/
> > +   REG_L a7, PT_A7(sp)
> > +   /*
> > +* Syscall number held in a7.
> > +* If syscall number is above allowed value, redirect to ni_syscall.
> > +*/
> > +   bge a7, t0, 1f
> > +   /*
> > +

Re: [PATCH 1/2] riscv: add support for SECCOMP incl. filters

[David Abdurachmanov]

On Thu, Dec 6, 2018 at 5:47 PM Kees Cook  wrote:
>
> On Thu, Dec 6, 2018 at 7:02 AM David Abdurachmanov
>  wrote:
> >
> > The patch adds support for SECCOMP and SECCOMP_FILTER (BPF).
> >
> > Signed-off-by: David Abdurachmanov 
> > ---
> >  arch/riscv/Kconfig   | 14 ++
> >  arch/riscv/include/asm/thread_info.h |  5 -
> >  arch/riscv/kernel/entry.S| 27 +--
> >  arch/riscv/kernel/ptrace.c   |  8 
> >  4 files changed, 51 insertions(+), 3 deletions(-)
> >
> > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> > index a4f48f757204..49cd8e251547 100644
> > --- a/arch/riscv/Kconfig
> > +++ b/arch/riscv/Kconfig
> > @@ -29,6 +29,7 @@ config RISCV
> > select GENERIC_SMP_IDLE_THREAD
> > select GENERIC_ATOMIC64 if !64BIT || !RISCV_ISA_A
> > select HAVE_ARCH_AUDITSYSCALL
> > +   select HAVE_ARCH_SECCOMP_FILTER
> > select HAVE_MEMBLOCK_NODE_MAP
> > select HAVE_DMA_CONTIGUOUS
> > select HAVE_FUTEX_CMPXCHG if FUTEX
> > @@ -228,6 +229,19 @@ menu "Kernel features"
> >
> >  source "kernel/Kconfig.hz"
> >
> > +config SECCOMP
> > +   bool "Enable seccomp to safely compute untrusted bytecode"
> > +   help
> > + This kernel feature is useful for number crunching applications
> > + that may need to compute untrusted bytecode during their
> > + execution. By using pipes or other transports made available to
> > + the process as file descriptors supporting the read/write
> > + syscalls, it's possible to isolate those applications in
> > + their own address space using seccomp. Once seccomp is
> > + enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
> > + and the task is only allowed to execute a few safe syscalls
> > + defined by each seccomp mode.
> > +
> >  endmenu
> >
> >  menu "Boot options"
> > diff --git a/arch/riscv/include/asm/thread_info.h 
> > b/arch/riscv/include/asm/thread_info.h
> > index 1c9cc8389928..1fd6e4130cab 100644
> > --- a/arch/riscv/include/asm/thread_info.h
> > +++ b/arch/riscv/include/asm/thread_info.h
> > @@ -81,6 +81,7 @@ struct thread_info {
> >  #define TIF_MEMDIE 5   /* is terminating due to OOM killer 
> > */
> >  #define TIF_SYSCALL_TRACEPOINT  6   /* syscall tracepoint 
> > instrumentation */
> >  #define TIF_SYSCALL_AUDIT  7   /* syscall auditing */
> > +#define TIF_SECCOMP8   /* syscall secure computing 
> > */
> >
> >  #define _TIF_SYSCALL_TRACE (1 << TIF_SYSCALL_TRACE)
> >  #define _TIF_NOTIFY_RESUME (1 << TIF_NOTIFY_RESUME)
> > @@ -88,11 +89,13 @@ struct thread_info {
> >  #define _TIF_NEED_RESCHED  (1 << TIF_NEED_RESCHED)
> >  #define _TIF_SYSCALL_TRACEPOINT(1 << TIF_SYSCALL_TRACEPOINT)
> >  #define _TIF_SYSCALL_AUDIT (1 << TIF_SYSCALL_AUDIT)
> > +#define _TIF_SECCOMP   (1 << TIF_SECCOMP)
> >
> >  #define _TIF_WORK_MASK \
> > (_TIF_NOTIFY_RESUME | _TIF_SIGPENDING | _TIF_NEED_RESCHED)
> >
> >  #define _TIF_SYSCALL_WORK \
> > -   (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_TRACEPOINT | _TIF_SYSCALL_AUDIT)
> > +   (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_TRACEPOINT | _TIF_SYSCALL_AUDIT \
> > +_TIF_SECCOMP )
> >
> >  #endif /* _ASM_RISCV_THREAD_INFO_H */
> > diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
> > index 355166f57205..e88ccbfa61ee 100644
> > --- a/arch/riscv/kernel/entry.S
> > +++ b/arch/riscv/kernel/entry.S
> > @@ -207,8 +207,25 @@ check_syscall_nr:
> > /* Check to make sure we don't jump to a bogus syscall number. */
> > li t0, __NR_syscalls
> > la s0, sys_ni_syscall
> > -   /* Syscall number held in a7 */
> > -   bgeu a7, t0, 1f
> > +   /*
> > +* The tracer can change syscall number to valid/invalid value.
> > +* We use syscall_set_nr helper in syscall_trace_enter thus we
> > +* cannot trust the current value in a7 and have to reload from
> > +* the current task pt_regs.
> > +*/
> > +   REG_L a7, PT_A7(sp)
> > +   /*
> > +* Syscall number held in a7.
> > +* If syscall number is above allowed value, redirect to ni_syscall.
> > +*/
> > +   bge a7, t0, 1f
> > +   /*
> > +

[PATCH 1/2] riscv: fix trace_sys_exit hook

[David Abdurachmanov]

Fix compilation error.

Signed-off-by: David Abdurachmanov 
---
 arch/riscv/kernel/ptrace.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/kernel/ptrace.c b/arch/riscv/kernel/ptrace.c
index c1b51539c3e2..2fd9ec48106b 100644
--- a/arch/riscv/kernel/ptrace.c
+++ b/arch/riscv/kernel/ptrace.c
@@ -177,6 +177,6 @@ void do_syscall_trace_exit(struct pt_regs *regs)
 
 #ifdef CONFIG_HAVE_SYSCALL_TRACEPOINTS
if (test_thread_flag(TIF_SYSCALL_TRACEPOINT))
-   trace_sys_exit(regs, regs->regs[0]);
+   trace_sys_exit(regs, regs_return_value(regs));
 #endif
 }
-- 
2.19.2

[PATCH 0/2] riscv: enable syscalls tracepoints

[David Abdurachmanov]

Depends on audit patch:
http://lists.infradead.org/pipermail/linux-riscv/2018-October/001931.html

audit patch is already merged into linux-next.

This simply fixes compilation error in do_syscall_trace_exit() and
enables syscalls tracepoints.

David Abdurachmanov (2):
  riscv: fix trace_sys_exit hook
  riscv: add HAVE_SYSCALL_TRACEPOINTS to Kconfig

 arch/riscv/Kconfig | 1 +
 arch/riscv/kernel/ptrace.c | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

-- 
2.19.2

[PATCH 1/2] riscv: fix trace_sys_exit hook

[David Abdurachmanov]

Fix compilation error.

Signed-off-by: David Abdurachmanov 
---
 arch/riscv/kernel/ptrace.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/kernel/ptrace.c b/arch/riscv/kernel/ptrace.c
index c1b51539c3e2..2fd9ec48106b 100644
--- a/arch/riscv/kernel/ptrace.c
+++ b/arch/riscv/kernel/ptrace.c
@@ -177,6 +177,6 @@ void do_syscall_trace_exit(struct pt_regs *regs)
 
 #ifdef CONFIG_HAVE_SYSCALL_TRACEPOINTS
if (test_thread_flag(TIF_SYSCALL_TRACEPOINT))
-   trace_sys_exit(regs, regs->regs[0]);
+   trace_sys_exit(regs, regs_return_value(regs));
 #endif
 }
-- 
2.19.2

[PATCH 0/2] riscv: enable syscalls tracepoints

[David Abdurachmanov]

Depends on audit patch:
http://lists.infradead.org/pipermail/linux-riscv/2018-October/001931.html

audit patch is already merged into linux-next.

This simply fixes compilation error in do_syscall_trace_exit() and
enables syscalls tracepoints.

David Abdurachmanov (2):
  riscv: fix trace_sys_exit hook
  riscv: add HAVE_SYSCALL_TRACEPOINTS to Kconfig

 arch/riscv/Kconfig | 1 +
 arch/riscv/kernel/ptrace.c | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

-- 
2.19.2

[PATCH 2/2] riscv: add HAVE_SYSCALL_TRACEPOINTS to Kconfig

[David Abdurachmanov]

I looked into Documentation/trace/ftrace-design.rst and, I think,
we check all the boxes needed for HAVE_SYSCALL_TRACEPOINTS.

Signed-off-by: David Abdurachmanov 
---
 arch/riscv/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index a4f48f757204..6749c22ee656 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -34,6 +34,7 @@ config RISCV
select HAVE_FUTEX_CMPXCHG if FUTEX
select HAVE_GENERIC_DMA_COHERENT
select HAVE_PERF_EVENTS
+   select HAVE_SYSCALL_TRACEPOINTS
select IRQ_DOMAIN
select RISCV_ISA_A if SMP
select SPARSE_IRQ
-- 
2.19.2

[PATCH 2/2] riscv: add HAVE_SYSCALL_TRACEPOINTS to Kconfig

[David Abdurachmanov]

I looked into Documentation/trace/ftrace-design.rst and, I think,
we check all the boxes needed for HAVE_SYSCALL_TRACEPOINTS.

Signed-off-by: David Abdurachmanov 
---
 arch/riscv/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index a4f48f757204..6749c22ee656 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -34,6 +34,7 @@ config RISCV
select HAVE_FUTEX_CMPXCHG if FUTEX
select HAVE_GENERIC_DMA_COHERENT
select HAVE_PERF_EVENTS
+   select HAVE_SYSCALL_TRACEPOINTS
select IRQ_DOMAIN
select RISCV_ISA_A if SMP
select SPARSE_IRQ
-- 
2.19.2

[PATCH 1/2] riscv: add support for SECCOMP incl. filters

[David Abdurachmanov]

The patch adds support for SECCOMP and SECCOMP_FILTER (BPF).

Signed-off-by: David Abdurachmanov 
---
 arch/riscv/Kconfig   | 14 ++
 arch/riscv/include/asm/thread_info.h |  5 -
 arch/riscv/kernel/entry.S| 27 +--
 arch/riscv/kernel/ptrace.c   |  8 
 4 files changed, 51 insertions(+), 3 deletions(-)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index a4f48f757204..49cd8e251547 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -29,6 +29,7 @@ config RISCV
select GENERIC_SMP_IDLE_THREAD
select GENERIC_ATOMIC64 if !64BIT || !RISCV_ISA_A
select HAVE_ARCH_AUDITSYSCALL
+   select HAVE_ARCH_SECCOMP_FILTER
select HAVE_MEMBLOCK_NODE_MAP
select HAVE_DMA_CONTIGUOUS
select HAVE_FUTEX_CMPXCHG if FUTEX
@@ -228,6 +229,19 @@ menu "Kernel features"
 
 source "kernel/Kconfig.hz"
 
+config SECCOMP
+   bool "Enable seccomp to safely compute untrusted bytecode"
+   help
+ This kernel feature is useful for number crunching applications
+ that may need to compute untrusted bytecode during their
+ execution. By using pipes or other transports made available to
+ the process as file descriptors supporting the read/write
+ syscalls, it's possible to isolate those applications in
+ their own address space using seccomp. Once seccomp is
+ enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
+ and the task is only allowed to execute a few safe syscalls
+ defined by each seccomp mode.
+
 endmenu
 
 menu "Boot options"
diff --git a/arch/riscv/include/asm/thread_info.h 
b/arch/riscv/include/asm/thread_info.h
index 1c9cc8389928..1fd6e4130cab 100644
--- a/arch/riscv/include/asm/thread_info.h
+++ b/arch/riscv/include/asm/thread_info.h
@@ -81,6 +81,7 @@ struct thread_info {
 #define TIF_MEMDIE 5   /* is terminating due to OOM killer */
 #define TIF_SYSCALL_TRACEPOINT  6   /* syscall tracepoint instrumentation 
*/
 #define TIF_SYSCALL_AUDIT  7   /* syscall auditing */
+#define TIF_SECCOMP8   /* syscall secure computing */
 
 #define _TIF_SYSCALL_TRACE (1 << TIF_SYSCALL_TRACE)
 #define _TIF_NOTIFY_RESUME (1 << TIF_NOTIFY_RESUME)
@@ -88,11 +89,13 @@ struct thread_info {
 #define _TIF_NEED_RESCHED  (1 << TIF_NEED_RESCHED)
 #define _TIF_SYSCALL_TRACEPOINT(1 << TIF_SYSCALL_TRACEPOINT)
 #define _TIF_SYSCALL_AUDIT (1 << TIF_SYSCALL_AUDIT)
+#define _TIF_SECCOMP   (1 << TIF_SECCOMP)
 
 #define _TIF_WORK_MASK \
(_TIF_NOTIFY_RESUME | _TIF_SIGPENDING | _TIF_NEED_RESCHED)
 
 #define _TIF_SYSCALL_WORK \
-   (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_TRACEPOINT | _TIF_SYSCALL_AUDIT)
+   (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_TRACEPOINT | _TIF_SYSCALL_AUDIT \
+_TIF_SECCOMP )
 
 #endif /* _ASM_RISCV_THREAD_INFO_H */
diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
index 355166f57205..e88ccbfa61ee 100644
--- a/arch/riscv/kernel/entry.S
+++ b/arch/riscv/kernel/entry.S
@@ -207,8 +207,25 @@ check_syscall_nr:
/* Check to make sure we don't jump to a bogus syscall number. */
li t0, __NR_syscalls
la s0, sys_ni_syscall
-   /* Syscall number held in a7 */
-   bgeu a7, t0, 1f
+   /*
+* The tracer can change syscall number to valid/invalid value.
+* We use syscall_set_nr helper in syscall_trace_enter thus we
+* cannot trust the current value in a7 and have to reload from
+* the current task pt_regs.
+*/
+   REG_L a7, PT_A7(sp)
+   /*
+* Syscall number held in a7.
+* If syscall number is above allowed value, redirect to ni_syscall.
+*/
+   bge a7, t0, 1f
+   /*
+* Check if syscall is rejected by tracer or seccomp, i.e., a7 == -1.
+* If yes, we pretend it was executed.
+*/
+   li t1, -1
+   beq a7, t1, ret_from_syscall_rejected
+   /* Call syscall */
la s0, sys_call_table
slli t0, a7, RISCV_LGPTR
add s0, s0, t0
@@ -219,6 +236,12 @@ check_syscall_nr:
 ret_from_syscall:
/* Set user a0 to kernel a0 */
REG_S a0, PT_A0(sp)
+   /*
+* We didn't execute the actual syscall.
+* Seccomp already set return value for the current task pt_regs.
+* (If it was configured with SECCOMP_RET_ERRNO/TRACE)
+*/
+ret_from_syscall_rejected:
/* Trace syscalls, but only if requested by the user. */
REG_L t0, TASK_TI_FLAGS(tp)
andi t0, t0, _TIF_SYSCALL_WORK
diff --git a/arch/riscv/kernel/ptrace.c b/arch/riscv/kernel/ptrace.c
index c1b51539c3e2..598e48b8ca2b 100644
--- a/arch/riscv/kernel/ptrace.c
+++ b/arch/riscv/kernel/ptrace.c
@@ -160,6 +160,14 @@ void do_syscall_trace_enter(struct pt_regs *regs)
if (tracehook_repo

[PATCH 1/2] riscv: add support for SECCOMP incl. filters

[David Abdurachmanov]

The patch adds support for SECCOMP and SECCOMP_FILTER (BPF).

Signed-off-by: David Abdurachmanov 
---
 arch/riscv/Kconfig   | 14 ++
 arch/riscv/include/asm/thread_info.h |  5 -
 arch/riscv/kernel/entry.S| 27 +--
 arch/riscv/kernel/ptrace.c   |  8 
 4 files changed, 51 insertions(+), 3 deletions(-)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index a4f48f757204..49cd8e251547 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -29,6 +29,7 @@ config RISCV
select GENERIC_SMP_IDLE_THREAD
select GENERIC_ATOMIC64 if !64BIT || !RISCV_ISA_A
select HAVE_ARCH_AUDITSYSCALL
+   select HAVE_ARCH_SECCOMP_FILTER
select HAVE_MEMBLOCK_NODE_MAP
select HAVE_DMA_CONTIGUOUS
select HAVE_FUTEX_CMPXCHG if FUTEX
@@ -228,6 +229,19 @@ menu "Kernel features"
 
 source "kernel/Kconfig.hz"
 
+config SECCOMP
+   bool "Enable seccomp to safely compute untrusted bytecode"
+   help
+ This kernel feature is useful for number crunching applications
+ that may need to compute untrusted bytecode during their
+ execution. By using pipes or other transports made available to
+ the process as file descriptors supporting the read/write
+ syscalls, it's possible to isolate those applications in
+ their own address space using seccomp. Once seccomp is
+ enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
+ and the task is only allowed to execute a few safe syscalls
+ defined by each seccomp mode.
+
 endmenu
 
 menu "Boot options"
diff --git a/arch/riscv/include/asm/thread_info.h 
b/arch/riscv/include/asm/thread_info.h
index 1c9cc8389928..1fd6e4130cab 100644
--- a/arch/riscv/include/asm/thread_info.h
+++ b/arch/riscv/include/asm/thread_info.h
@@ -81,6 +81,7 @@ struct thread_info {
 #define TIF_MEMDIE 5   /* is terminating due to OOM killer */
 #define TIF_SYSCALL_TRACEPOINT  6   /* syscall tracepoint instrumentation 
*/
 #define TIF_SYSCALL_AUDIT  7   /* syscall auditing */
+#define TIF_SECCOMP8   /* syscall secure computing */
 
 #define _TIF_SYSCALL_TRACE (1 << TIF_SYSCALL_TRACE)
 #define _TIF_NOTIFY_RESUME (1 << TIF_NOTIFY_RESUME)
@@ -88,11 +89,13 @@ struct thread_info {
 #define _TIF_NEED_RESCHED  (1 << TIF_NEED_RESCHED)
 #define _TIF_SYSCALL_TRACEPOINT(1 << TIF_SYSCALL_TRACEPOINT)
 #define _TIF_SYSCALL_AUDIT (1 << TIF_SYSCALL_AUDIT)
+#define _TIF_SECCOMP   (1 << TIF_SECCOMP)
 
 #define _TIF_WORK_MASK \
(_TIF_NOTIFY_RESUME | _TIF_SIGPENDING | _TIF_NEED_RESCHED)
 
 #define _TIF_SYSCALL_WORK \
-   (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_TRACEPOINT | _TIF_SYSCALL_AUDIT)
+   (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_TRACEPOINT | _TIF_SYSCALL_AUDIT \
+_TIF_SECCOMP )
 
 #endif /* _ASM_RISCV_THREAD_INFO_H */
diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
index 355166f57205..e88ccbfa61ee 100644
--- a/arch/riscv/kernel/entry.S
+++ b/arch/riscv/kernel/entry.S
@@ -207,8 +207,25 @@ check_syscall_nr:
/* Check to make sure we don't jump to a bogus syscall number. */
li t0, __NR_syscalls
la s0, sys_ni_syscall
-   /* Syscall number held in a7 */
-   bgeu a7, t0, 1f
+   /*
+* The tracer can change syscall number to valid/invalid value.
+* We use syscall_set_nr helper in syscall_trace_enter thus we
+* cannot trust the current value in a7 and have to reload from
+* the current task pt_regs.
+*/
+   REG_L a7, PT_A7(sp)
+   /*
+* Syscall number held in a7.
+* If syscall number is above allowed value, redirect to ni_syscall.
+*/
+   bge a7, t0, 1f
+   /*
+* Check if syscall is rejected by tracer or seccomp, i.e., a7 == -1.
+* If yes, we pretend it was executed.
+*/
+   li t1, -1
+   beq a7, t1, ret_from_syscall_rejected
+   /* Call syscall */
la s0, sys_call_table
slli t0, a7, RISCV_LGPTR
add s0, s0, t0
@@ -219,6 +236,12 @@ check_syscall_nr:
 ret_from_syscall:
/* Set user a0 to kernel a0 */
REG_S a0, PT_A0(sp)
+   /*
+* We didn't execute the actual syscall.
+* Seccomp already set return value for the current task pt_regs.
+* (If it was configured with SECCOMP_RET_ERRNO/TRACE)
+*/
+ret_from_syscall_rejected:
/* Trace syscalls, but only if requested by the user. */
REG_L t0, TASK_TI_FLAGS(tp)
andi t0, t0, _TIF_SYSCALL_WORK
diff --git a/arch/riscv/kernel/ptrace.c b/arch/riscv/kernel/ptrace.c
index c1b51539c3e2..598e48b8ca2b 100644
--- a/arch/riscv/kernel/ptrace.c
+++ b/arch/riscv/kernel/ptrace.c
@@ -160,6 +160,14 @@ void do_syscall_trace_enter(struct pt_regs *regs)
if (tracehook_repo

[PATCH 2/2] riscv: fix syscall_{get,set}_arguments

[David Abdurachmanov]

Testing with libseccomp master branch revealed that testcases with
filters on syscall arguments were failing due to wrong values. Seccomp
uses syscall_get_argumentsi() to copy syscall arguments, and there is a
bug in pointer arithmetics in memcpy() call.

Two alternative implementation were tested: the one in this patch and
another one based on while-break loop. Both delivered the same results.

This implementation is also used in arm, arm64 and nds32 arches.

Signed-off-by: David Abdurachmanov 
---
 arch/riscv/include/asm/syscall.h | 42 
 1 file changed, 32 insertions(+), 10 deletions(-)

diff --git a/arch/riscv/include/asm/syscall.h b/arch/riscv/include/asm/syscall.h
index bba3da6ef157..26ceb434a433 100644
--- a/arch/riscv/include/asm/syscall.h
+++ b/arch/riscv/include/asm/syscall.h
@@ -70,19 +70,32 @@ static inline void syscall_set_return_value(struct 
task_struct *task,
regs->a0 = (long) error ?: val;
 }
 
+#define SYSCALL_MAX_ARGS 6
+
 static inline void syscall_get_arguments(struct task_struct *task,
 struct pt_regs *regs,
 unsigned int i, unsigned int n,
 unsigned long *args)
 {
-   BUG_ON(i + n > 6);
+   if (n == 0)
+   return;
+
+   if (i + n > SYSCALL_MAX_ARGS) {
+   unsigned long *args_bad = args + SYSCALL_MAX_ARGS - i;
+   unsigned int n_bad = n + i - SYSCALL_MAX_ARGS;
+   pr_warning("%s called with max args %d, handling only %d\n",
+   __func__, i + n, SYSCALL_MAX_ARGS);
+   memset(args_bad, 0, n_bad * sizeof(args[0]));
+   }
+
if (i == 0) {
args[0] = regs->orig_a0;
args++;
i++;
n--;
}
-   memcpy(args, >a1 + i * sizeof(regs->a1), n * sizeof(args[0]));
+
+   memcpy(args, >a0 + i, n * sizeof(args[0]));
 }
 
 static inline void syscall_set_arguments(struct task_struct *task,
@@ -90,14 +103,23 @@ static inline void syscall_set_arguments(struct 
task_struct *task,
 unsigned int i, unsigned int n,
 const unsigned long *args)
 {
-   BUG_ON(i + n > 6);
-if (i == 0) {
-regs->orig_a0 = args[0];
-args++;
-i++;
-n--;
-}
-   memcpy(>a1 + i * sizeof(regs->a1), args, n * sizeof(regs->a0));
+   if (n == 0)
+   return;
+
+   if (i + n > SYSCALL_MAX_ARGS) {
+   pr_warning("%s called with max args %d, handling only %d\n",
+   __func__, i + n, SYSCALL_MAX_ARGS);
+   n = SYSCALL_MAX_ARGS - i;
+   }
+
+   if (i == 0) {
+   regs->orig_a0 = args[0];
+   args++;
+   i++;
+   n--;
+   }
+
+   memcpy(>a0 + i, args, n * sizeof(args[0]));
 }
 
 static inline int syscall_get_arch(void)
-- 
2.19.2

[PATCH 2/2] riscv: fix syscall_{get,set}_arguments

[David Abdurachmanov]

Testing with libseccomp master branch revealed that testcases with
filters on syscall arguments were failing due to wrong values. Seccomp
uses syscall_get_argumentsi() to copy syscall arguments, and there is a
bug in pointer arithmetics in memcpy() call.

Two alternative implementation were tested: the one in this patch and
another one based on while-break loop. Both delivered the same results.

This implementation is also used in arm, arm64 and nds32 arches.

Signed-off-by: David Abdurachmanov 
---
 arch/riscv/include/asm/syscall.h | 42 
 1 file changed, 32 insertions(+), 10 deletions(-)

diff --git a/arch/riscv/include/asm/syscall.h b/arch/riscv/include/asm/syscall.h
index bba3da6ef157..26ceb434a433 100644
--- a/arch/riscv/include/asm/syscall.h
+++ b/arch/riscv/include/asm/syscall.h
@@ -70,19 +70,32 @@ static inline void syscall_set_return_value(struct 
task_struct *task,
regs->a0 = (long) error ?: val;
 }
 
+#define SYSCALL_MAX_ARGS 6
+
 static inline void syscall_get_arguments(struct task_struct *task,
 struct pt_regs *regs,
 unsigned int i, unsigned int n,
 unsigned long *args)
 {
-   BUG_ON(i + n > 6);
+   if (n == 0)
+   return;
+
+   if (i + n > SYSCALL_MAX_ARGS) {
+   unsigned long *args_bad = args + SYSCALL_MAX_ARGS - i;
+   unsigned int n_bad = n + i - SYSCALL_MAX_ARGS;
+   pr_warning("%s called with max args %d, handling only %d\n",
+   __func__, i + n, SYSCALL_MAX_ARGS);
+   memset(args_bad, 0, n_bad * sizeof(args[0]));
+   }
+
if (i == 0) {
args[0] = regs->orig_a0;
args++;
i++;
n--;
}
-   memcpy(args, >a1 + i * sizeof(regs->a1), n * sizeof(args[0]));
+
+   memcpy(args, >a0 + i, n * sizeof(args[0]));
 }
 
 static inline void syscall_set_arguments(struct task_struct *task,
@@ -90,14 +103,23 @@ static inline void syscall_set_arguments(struct 
task_struct *task,
 unsigned int i, unsigned int n,
 const unsigned long *args)
 {
-   BUG_ON(i + n > 6);
-if (i == 0) {
-regs->orig_a0 = args[0];
-args++;
-i++;
-n--;
-}
-   memcpy(>a1 + i * sizeof(regs->a1), args, n * sizeof(regs->a0));
+   if (n == 0)
+   return;
+
+   if (i + n > SYSCALL_MAX_ARGS) {
+   pr_warning("%s called with max args %d, handling only %d\n",
+   __func__, i + n, SYSCALL_MAX_ARGS);
+   n = SYSCALL_MAX_ARGS - i;
+   }
+
+   if (i == 0) {
+   regs->orig_a0 = args[0];
+   args++;
+   i++;
+   n--;
+   }
+
+   memcpy(>a0 + i, args, n * sizeof(args[0]));
 }
 
 static inline int syscall_get_arch(void)
-- 
2.19.2

[PATCH 0/2] riscv: add support for SECCOMP and SECCOMP_FILTER

[David Abdurachmanov]

This was originally tested on 4.19 kernel with Fedora 29/RISCV. 
Depends on audit patches (already in linux-next).

The patches are on top of linux-next next-20181206 tag.

Validation was done using libseccomp (at 
1e64feb5f1a9ea02687228e3073e8b784a04ce46, which is master at this 
date). See PR: https://github.com/seccomp/libseccomp/pull/134

Test results:

# ./regression -T live

Regression Test Summary
tests run: 8
tests skipped: 0
tests passed: 8
tests failed: 0
tests errored: 0

# ./regression

Regression Test Summary
tests run: 5129
tests skipped: 104
tests passed: 5129
tests failed: 0
tests errored: 0

David Abdurachmanov (2):
  riscv: add support for SECCOMP incl. filters
  riscv: fix syscall_{get,set}_arguments

 arch/riscv/Kconfig   | 14 ++
 arch/riscv/include/asm/syscall.h | 42 +---
 arch/riscv/include/asm/thread_info.h |  5 +++-
 arch/riscv/kernel/entry.S| 27 --
 arch/riscv/kernel/ptrace.c   |  8 ++
 5 files changed, 83 insertions(+), 13 deletions(-)

-- 
2.19.2

[PATCH 0/2] riscv: add support for SECCOMP and SECCOMP_FILTER

[David Abdurachmanov]

This was originally tested on 4.19 kernel with Fedora 29/RISCV. 
Depends on audit patches (already in linux-next).

The patches are on top of linux-next next-20181206 tag.

Validation was done using libseccomp (at 
1e64feb5f1a9ea02687228e3073e8b784a04ce46, which is master at this 
date). See PR: https://github.com/seccomp/libseccomp/pull/134

Test results:

# ./regression -T live

Regression Test Summary
tests run: 8
tests skipped: 0
tests passed: 8
tests failed: 0
tests errored: 0

# ./regression

Regression Test Summary
tests run: 5129
tests skipped: 104
tests passed: 5129
tests failed: 0
tests errored: 0

David Abdurachmanov (2):
  riscv: add support for SECCOMP incl. filters
  riscv: fix syscall_{get,set}_arguments

 arch/riscv/Kconfig   | 14 ++
 arch/riscv/include/asm/syscall.h | 42 +---
 arch/riscv/include/asm/thread_info.h |  5 +++-
 arch/riscv/kernel/entry.S| 27 --
 arch/riscv/kernel/ptrace.c   |  8 ++
 5 files changed, 83 insertions(+), 13 deletions(-)

-- 
2.19.2

[PATCH] riscv: remove unused variable in ftrace

[David Abdurachmanov]

Noticed while building kernel-4.20.0-0.rc5.git2.1.fc30 for
Fedora 30/RISCV.

[..]
BUILDSTDERR: arch/riscv/kernel/ftrace.c: In function 'prepare_ftrace_return':
BUILDSTDERR: arch/riscv/kernel/ftrace.c:135:6: warning: unused variable 'err' 
[-Wunused-variable]
BUILDSTDERR:   int err;
BUILDSTDERR:   ^~~
[..]

Signed-off-by: David Abdurachmanov 
---
 arch/riscv/kernel/ftrace.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/riscv/kernel/ftrace.c b/arch/riscv/kernel/ftrace.c
index c433f6d3dd64..a840b7d074f7 100644
--- a/arch/riscv/kernel/ftrace.c
+++ b/arch/riscv/kernel/ftrace.c
@@ -132,7 +132,6 @@ void prepare_ftrace_return(unsigned long *parent, unsigned 
long self_addr,
 {
unsigned long return_hooker = (unsigned long)_to_handler;
unsigned long old;
-   int err;
 
if (unlikely(atomic_read(>tracing_graph_pause)))
return;
-- 
2.19.2

[PATCH] riscv: remove unused variable in ftrace

[David Abdurachmanov]

Noticed while building kernel-4.20.0-0.rc5.git2.1.fc30 for
Fedora 30/RISCV.

[..]
BUILDSTDERR: arch/riscv/kernel/ftrace.c: In function 'prepare_ftrace_return':
BUILDSTDERR: arch/riscv/kernel/ftrace.c:135:6: warning: unused variable 'err' 
[-Wunused-variable]
BUILDSTDERR:   int err;
BUILDSTDERR:   ^~~
[..]

Signed-off-by: David Abdurachmanov 
---
 arch/riscv/kernel/ftrace.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/riscv/kernel/ftrace.c b/arch/riscv/kernel/ftrace.c
index c433f6d3dd64..a840b7d074f7 100644
--- a/arch/riscv/kernel/ftrace.c
+++ b/arch/riscv/kernel/ftrace.c
@@ -132,7 +132,6 @@ void prepare_ftrace_return(unsigned long *parent, unsigned 
long self_addr,
 {
unsigned long return_hooker = (unsigned long)_to_handler;
unsigned long old;
-   int err;
 
if (unlikely(atomic_read(>tracing_graph_pause)))
return;
-- 
2.19.2

Re: [PATCH] riscv: add S and U modes to ISA string

[David Abdurachmanov]

On Sun, Nov 11, 2018 at 11:14 PM Palmer Dabbelt  wrote:
>
> On Sat, 10 Nov 2018 00:35:15 PST (-0800), m...@packi.ch wrote:
> > On 10.11.18 07:45, David Abdurachmanov wrote:
> >>
> >> The patch adds the missing S and U modes.
> >
> > This is the same patch I submitted earlier (see v2 here [1], based on
> > Palmer's feedback). Palmer stated that the "S" extension should not be
> > exposed to usermode.
> >
> > Since two people arrived at the same solution, I wonder if the
> > supervisor mode should really be hidden from userspace, as it's about
> > the CPU information, not about the environment the calling code is
> > running as.
> >
> > [1] https://lkml.org/lkml/2018/11/10/96
>
> I still think S should be hidden from applications.  This patch was fairly
> mechanical, so it probably just wasn't though about twice -- that's the 
> problem
> with user ABI stuff, lots of times the obvious answer isn't the correct one 
> :).
>
True. It was mechanical based on warnings I noticed while booting Fedora
with latest kernel and BBL.

Also true, that /proc/cpuinfo doesn't need to reveal all things to user space
(especially if you don't want various programs to depend on it as some
tend to parse /proc/cpuinfo).

Note, that on server systems which probably would implement SMBIOS
(based on the current proposal for RISC-V) the administrator could
check for S mode.

Re: [PATCH] riscv: add S and U modes to ISA string

[David Abdurachmanov]

On Sun, Nov 11, 2018 at 11:14 PM Palmer Dabbelt  wrote:
>
> On Sat, 10 Nov 2018 00:35:15 PST (-0800), m...@packi.ch wrote:
> > On 10.11.18 07:45, David Abdurachmanov wrote:
> >>
> >> The patch adds the missing S and U modes.
> >
> > This is the same patch I submitted earlier (see v2 here [1], based on
> > Palmer's feedback). Palmer stated that the "S" extension should not be
> > exposed to usermode.
> >
> > Since two people arrived at the same solution, I wonder if the
> > supervisor mode should really be hidden from userspace, as it's about
> > the CPU information, not about the environment the calling code is
> > running as.
> >
> > [1] https://lkml.org/lkml/2018/11/10/96
>
> I still think S should be hidden from applications.  This patch was fairly
> mechanical, so it probably just wasn't though about twice -- that's the 
> problem
> with user ABI stuff, lots of times the obvious answer isn't the correct one 
> :).
>
True. It was mechanical based on warnings I noticed while booting Fedora
with latest kernel and BBL.

Also true, that /proc/cpuinfo doesn't need to reveal all things to user space
(especially if you don't want various programs to depend on it as some
tend to parse /proc/cpuinfo).

Note, that on server systems which probably would implement SMBIOS
(based on the current proposal for RISC-V) the administrator could
check for S mode.

Re: [PATCH 1/2] RISC-V: Request stat64 on RV32

[David Abdurachmanov]

On Mon, Nov 12, 2018 at 5:10 AM Zong Li  wrote:
>
> The stat64 family that is used on 32-bit architectures to replace
> newstat.
>
> Since commit 67314ec7b0250290cc85eaa7a2f88a8ddb9e8547 ("RISC-V: Request
> newstat syscalls"), the RV32 build fail with undeclared 'sys_fstatat64'
>
> Signed-off-by: Zong Li 
> ---
>  arch/riscv/include/asm/unistd.h | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/arch/riscv/include/asm/unistd.h b/arch/riscv/include/asm/unistd.h
> index eff7aa9..a4aade9 100644
> --- a/arch/riscv/include/asm/unistd.h
> +++ b/arch/riscv/include/asm/unistd.h
> @@ -18,5 +18,6 @@
>
>  #define __ARCH_WANT_NEW_STAT
>  #define __ARCH_WANT_SYS_CLONE
> +#define __ARCH_WANT_STAT64
>  #include 
>  #include 
> --

See: http://lists.infradead.org/pipermail/linux-riscv/2018-November/002087.html

The plan is not to have old stat syscalls and support statx on
riscv32, which is y2038 safe.

The issue you see is a bug in include/uapi/asm-generic/unistd.h.
Marcin (CC) already sent a patch to Arnd (CC) IIRC. Basically without
__ARCH_WANT_NEW_STAT or __ARCH_WANT_STAT64 two macros are not defined:
__NR3264_fstatat and __NR3264_fstat. Which is later used (without any
guards):

763 #define __NR_newfstatat __NR3264_fstatat
764 #define __NR_fstat __NR3264_fstat

Re: [PATCH 1/2] RISC-V: Request stat64 on RV32

[David Abdurachmanov]

On Mon, Nov 12, 2018 at 5:10 AM Zong Li  wrote:
>
> The stat64 family that is used on 32-bit architectures to replace
> newstat.
>
> Since commit 67314ec7b0250290cc85eaa7a2f88a8ddb9e8547 ("RISC-V: Request
> newstat syscalls"), the RV32 build fail with undeclared 'sys_fstatat64'
>
> Signed-off-by: Zong Li 
> ---
>  arch/riscv/include/asm/unistd.h | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/arch/riscv/include/asm/unistd.h b/arch/riscv/include/asm/unistd.h
> index eff7aa9..a4aade9 100644
> --- a/arch/riscv/include/asm/unistd.h
> +++ b/arch/riscv/include/asm/unistd.h
> @@ -18,5 +18,6 @@
>
>  #define __ARCH_WANT_NEW_STAT
>  #define __ARCH_WANT_SYS_CLONE
> +#define __ARCH_WANT_STAT64
>  #include 
>  #include 
> --

See: http://lists.infradead.org/pipermail/linux-riscv/2018-November/002087.html

The plan is not to have old stat syscalls and support statx on
riscv32, which is y2038 safe.

The issue you see is a bug in include/uapi/asm-generic/unistd.h.
Marcin (CC) already sent a patch to Arnd (CC) IIRC. Basically without
__ARCH_WANT_NEW_STAT or __ARCH_WANT_STAT64 two macros are not defined:
__NR3264_fstatat and __NR3264_fstat. Which is later used (without any
guards):

763 #define __NR_newfstatat __NR3264_fstatat
764 #define __NR_fstat __NR3264_fstat

[PATCH] riscv: add S and U modes to ISA string

[David Abdurachmanov]

Booting kernel (4.20-rc1) with riscv-pk @
6ebd0f2a46255d0c76dad3c05b16c1d154795d26 (master/HEAD) on Fedora 29 one gets:

[..]
[   55.075000] unsupported ISA "rv64imafdcsu" in device tree
[   55.075000] unsupported ISA "rv64imafdcsu" in device tree
[   55.076000] unsupported ISA "rv64imafdcsu" in device tree
[   55.076000] unsupported ISA "rv64imafdcsu" in device tree
[   55.077000] systemd[1]: Detected architecture riscv64.
[..]

The patch adds the missing S and U modes.

Signed-off-by: David Abdurachmanov 
---
 arch/riscv/kernel/cpu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
index 3a5a2ee31547..4029c7e6872b 100644
--- a/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
@@ -64,7 +64,7 @@ int riscv_of_processor_hartid(struct device_node *node)
 
 static void print_isa(struct seq_file *f, const char *orig_isa)
 {
-   static const char *ext = "mafdc";
+   static const char *ext = "mafdcsu";
const char *isa = orig_isa;
const char *e;
 
-- 
2.19.1

[PATCH] riscv: add S and U modes to ISA string

[David Abdurachmanov]

Booting kernel (4.20-rc1) with riscv-pk @
6ebd0f2a46255d0c76dad3c05b16c1d154795d26 (master/HEAD) on Fedora 29 one gets:

[..]
[   55.075000] unsupported ISA "rv64imafdcsu" in device tree
[   55.075000] unsupported ISA "rv64imafdcsu" in device tree
[   55.076000] unsupported ISA "rv64imafdcsu" in device tree
[   55.076000] unsupported ISA "rv64imafdcsu" in device tree
[   55.077000] systemd[1]: Detected architecture riscv64.
[..]

The patch adds the missing S and U modes.

Signed-off-by: David Abdurachmanov 
---
 arch/riscv/kernel/cpu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
index 3a5a2ee31547..4029c7e6872b 100644
--- a/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
@@ -64,7 +64,7 @@ int riscv_of_processor_hartid(struct device_node *node)
 
 static void print_isa(struct seq_file *f, const char *orig_isa)
 {
-   static const char *ext = "mafdc";
+   static const char *ext = "mafdcsu";
const char *isa = orig_isa;
const char *e;
 
-- 
2.19.1

[PATCH] riscv: fix warning in arch/riscv/include/asm/module.h

[David Abdurachmanov]

Fixes warning: 'struct module' declared inside parameter list will not be
visible outside of this definition or declaration

Signed-off-by: David Abdurachmanov 
---
 arch/riscv/include/asm/module.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/include/asm/module.h b/arch/riscv/include/asm/module.h
index 349df33808c4..cd2af4b013e3 100644
--- a/arch/riscv/include/asm/module.h
+++ b/arch/riscv/include/asm/module.h
@@ -8,6 +8,7 @@
 
 #define MODULE_ARCH_VERMAGIC"riscv"
 
+struct module;
 u64 module_emit_got_entry(struct module *mod, u64 val);
 u64 module_emit_plt_entry(struct module *mod, u64 val);
 
-- 
2.19.1

[PATCH] riscv: fix warning in arch/riscv/include/asm/module.h

[David Abdurachmanov]

Fixes warning: 'struct module' declared inside parameter list will not be
visible outside of this definition or declaration

Signed-off-by: David Abdurachmanov 
---
 arch/riscv/include/asm/module.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/include/asm/module.h b/arch/riscv/include/asm/module.h
index 349df33808c4..cd2af4b013e3 100644
--- a/arch/riscv/include/asm/module.h
+++ b/arch/riscv/include/asm/module.h
@@ -8,6 +8,7 @@
 
 #define MODULE_ARCH_VERMAGIC"riscv"
 
+struct module;
 u64 module_emit_got_entry(struct module *mod, u64 val);
 u64 module_emit_plt_entry(struct module *mod, u64 val);
 
-- 
2.19.1

[PATCH v2] riscv: add asm/unistd.h UAPI header

[David Abdurachmanov]

Marcin Juszkiewicz reported issues while generating syscall table for riscv
using 4.20-rc1. The patch refactors our unistd.h files to match some other
architectures.

- Add asm/unistd.h UAPI header, which has __ARCH_WANT_NEW_STAT only for 64-bit
- Remove asm/syscalls.h UAPI header and merge to asm/unistd.h
- Adjust kernel asm/unistd.h

So now asm/unistd.h UAPI header should show all syscalls for riscv.

Before this, Makefile simply put `#include ` into
generated asm/unistd.h UAPI header thus user didn't see:

- __NR_riscv_flush_icache
- __NR_newfstatat
- __NR_fstat

which are supported by riscv kernel.

Signed-off-by: David Abdurachmanov 
Cc: Arnd Bergmann 
Cc: Marcin Juszkiewicz 
Cc: Guenter Roeck 
Fixes: 67314ec7b025 ("RISC-V: Request newstat syscalls")
Signed-off-by: David Abdurachmanov 
---
 arch/riscv/include/asm/unistd.h|  5 ++--
 arch/riscv/include/uapi/asm/syscalls.h | 29 --
 arch/riscv/include/uapi/asm/unistd.h   | 41 ++
 3 files changed, 43 insertions(+), 32 deletions(-)
 delete mode 100644 arch/riscv/include/uapi/asm/syscalls.h
 create mode 100644 arch/riscv/include/uapi/asm/unistd.h

diff --git a/arch/riscv/include/asm/unistd.h b/arch/riscv/include/asm/unistd.h
index eff7aa9aa163..fef96f117b4d 100644
--- a/arch/riscv/include/asm/unistd.h
+++ b/arch/riscv/include/asm/unistd.h
@@ -13,10 +13,9 @@
 
 /*
  * There is explicitly no include guard here because this file is expected to
- * be included multiple times.  See uapi/asm/syscalls.h for more info.
+ * be included multiple times.
  */
 
-#define __ARCH_WANT_NEW_STAT
 #define __ARCH_WANT_SYS_CLONE
+
 #include 
-#include 
diff --git a/arch/riscv/include/uapi/asm/syscalls.h 
b/arch/riscv/include/uapi/asm/syscalls.h
deleted file mode 100644
index 206dc4b0f6ea..
--- a/arch/riscv/include/uapi/asm/syscalls.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2017-2018 SiFive
- */
-
-/*
- * There is explicitly no include guard here because this file is expected to
- * be included multiple times in order to define the syscall macros via
- * __SYSCALL.
- */
-
-/*
- * Allows the instruction cache to be flushed from userspace.  Despite RISC-V
- * having a direct 'fence.i' instruction available to userspace (which we
- * can't trap!), that's not actually viable when running on Linux because the
- * kernel might schedule a process on another hart.  There is no way for
- * userspace to handle this without invoking the kernel (as it doesn't know the
- * thread->hart mappings), so we've defined a RISC-V specific system call to
- * flush the instruction cache.
- *
- * __NR_riscv_flush_icache is defined to flush the instruction cache over an
- * address range, with the flush applying to either all threads or just the
- * caller.  We don't currently do anything with the address range, that's just
- * in there for forwards compatibility.
- */
-#ifndef __NR_riscv_flush_icache
-#define __NR_riscv_flush_icache (__NR_arch_specific_syscall + 15)
-#endif
-__SYSCALL(__NR_riscv_flush_icache, sys_riscv_flush_icache)
diff --git a/arch/riscv/include/uapi/asm/unistd.h 
b/arch/riscv/include/uapi/asm/unistd.h
new file mode 100644
index ..1f3bd3ebbb0d
--- /dev/null
+++ b/arch/riscv/include/uapi/asm/unistd.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/*
+ * Copyright (C) 2018 David Abdurachmanov 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifdef __LP64__
+#define __ARCH_WANT_NEW_STAT
+#endif /* __LP64__ */
+
+#include 
+
+/*
+ * Allows the instruction cache to be flushed from userspace.  Despite RISC-V
+ * having a direct 'fence.i' instruction available to userspace (which we
+ * can't trap!), that's not actually viable when running on Linux because the
+ * kernel might schedule a process on another hart.  There is no way for
+ * userspace to handle this without invoking the kernel (as it doesn't know the
+ * thread->hart mappings), so we've defined a RISC-V specific system call to
+ * flush the instruction cache.
+ *
+ * __NR_riscv_flush_icache is defined to flush the instruction cache over an
+ * address range, with the flush applying to either all threads or just the
+ * caller.  We don't currently do anything with the address range, that's just
+ * in there for forwards compatibility.
+ */
+#ifndef __NR_riscv_flush_icache
+#define _

[PATCH v2] riscv: add asm/unistd.h UAPI header

[David Abdurachmanov]

Marcin Juszkiewicz reported issues while generating syscall table for riscv
using 4.20-rc1. The patch refactors our unistd.h files to match some other
architectures.

- Add asm/unistd.h UAPI header, which has __ARCH_WANT_NEW_STAT only for 64-bit
- Remove asm/syscalls.h UAPI header and merge to asm/unistd.h
- Adjust kernel asm/unistd.h

So now asm/unistd.h UAPI header should show all syscalls for riscv.

Before this, Makefile simply put `#include ` into
generated asm/unistd.h UAPI header thus user didn't see:

- __NR_riscv_flush_icache
- __NR_newfstatat
- __NR_fstat

which are supported by riscv kernel.

Signed-off-by: David Abdurachmanov 
Cc: Arnd Bergmann 
Cc: Marcin Juszkiewicz 
Cc: Guenter Roeck 
Fixes: 67314ec7b025 ("RISC-V: Request newstat syscalls")
Signed-off-by: David Abdurachmanov 
---
 arch/riscv/include/asm/unistd.h|  5 ++--
 arch/riscv/include/uapi/asm/syscalls.h | 29 --
 arch/riscv/include/uapi/asm/unistd.h   | 41 ++
 3 files changed, 43 insertions(+), 32 deletions(-)
 delete mode 100644 arch/riscv/include/uapi/asm/syscalls.h
 create mode 100644 arch/riscv/include/uapi/asm/unistd.h

diff --git a/arch/riscv/include/asm/unistd.h b/arch/riscv/include/asm/unistd.h
index eff7aa9aa163..fef96f117b4d 100644
--- a/arch/riscv/include/asm/unistd.h
+++ b/arch/riscv/include/asm/unistd.h
@@ -13,10 +13,9 @@
 
 /*
  * There is explicitly no include guard here because this file is expected to
- * be included multiple times.  See uapi/asm/syscalls.h for more info.
+ * be included multiple times.
  */
 
-#define __ARCH_WANT_NEW_STAT
 #define __ARCH_WANT_SYS_CLONE
+
 #include 
-#include 
diff --git a/arch/riscv/include/uapi/asm/syscalls.h 
b/arch/riscv/include/uapi/asm/syscalls.h
deleted file mode 100644
index 206dc4b0f6ea..
--- a/arch/riscv/include/uapi/asm/syscalls.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2017-2018 SiFive
- */
-
-/*
- * There is explicitly no include guard here because this file is expected to
- * be included multiple times in order to define the syscall macros via
- * __SYSCALL.
- */
-
-/*
- * Allows the instruction cache to be flushed from userspace.  Despite RISC-V
- * having a direct 'fence.i' instruction available to userspace (which we
- * can't trap!), that's not actually viable when running on Linux because the
- * kernel might schedule a process on another hart.  There is no way for
- * userspace to handle this without invoking the kernel (as it doesn't know the
- * thread->hart mappings), so we've defined a RISC-V specific system call to
- * flush the instruction cache.
- *
- * __NR_riscv_flush_icache is defined to flush the instruction cache over an
- * address range, with the flush applying to either all threads or just the
- * caller.  We don't currently do anything with the address range, that's just
- * in there for forwards compatibility.
- */
-#ifndef __NR_riscv_flush_icache
-#define __NR_riscv_flush_icache (__NR_arch_specific_syscall + 15)
-#endif
-__SYSCALL(__NR_riscv_flush_icache, sys_riscv_flush_icache)
diff --git a/arch/riscv/include/uapi/asm/unistd.h 
b/arch/riscv/include/uapi/asm/unistd.h
new file mode 100644
index ..1f3bd3ebbb0d
--- /dev/null
+++ b/arch/riscv/include/uapi/asm/unistd.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/*
+ * Copyright (C) 2018 David Abdurachmanov 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifdef __LP64__
+#define __ARCH_WANT_NEW_STAT
+#endif /* __LP64__ */
+
+#include 
+
+/*
+ * Allows the instruction cache to be flushed from userspace.  Despite RISC-V
+ * having a direct 'fence.i' instruction available to userspace (which we
+ * can't trap!), that's not actually viable when running on Linux because the
+ * kernel might schedule a process on another hart.  There is no way for
+ * userspace to handle this without invoking the kernel (as it doesn't know the
+ * thread->hart mappings), so we've defined a RISC-V specific system call to
+ * flush the instruction cache.
+ *
+ * __NR_riscv_flush_icache is defined to flush the instruction cache over an
+ * address range, with the flush applying to either all threads or just the
+ * caller.  We don't currently do anything with the address range, that's just
+ * in there for forwards compatibility.
+ */
+#ifndef __NR_riscv_flush_icache
+#define _

Re: [PATCH] riscv: add asm/unistd.h UAPI header

[David Abdurachmanov]

On Thu, Nov 8, 2018 at 3:10 AM Palmer Dabbelt  wrote:
>
> On Wed, 07 Nov 2018 13:09:39 PST (-0800), Arnd Bergmann wrote:
> > On Wed, Nov 7, 2018 at 7:30 PM David Abdurachmanov
> >  wrote:
> >> On Wed, Nov 7, 2018 at 1:08 AM Palmer Dabbelt  wrote:
> >> > On Mon, 05 Nov 2018 12:56:15 PST (-0800), Arnd Bergmann wrote:
> >
> >> > The target is still the next glibc release (Feb 1st) for a stable RV32I 
> >> > ABI.
> >> > That's progressing well, with one last blocking issue related to some of 
> >> > our
> >> > floating-point emulation routines before we can submit the port.  This 
> >> > should
> >> > give us ample time to line up the ABIs correctly so everything works.
> >> >
> >> > So I think the correct answer here is to drop __ARCH_WANT_STAT64 from 
> >> > RISC-V.
> >> >
> >>
> >> Then if you agree I could do and send v2:
> >>
> >> +#ifdef __LP64__
> >> +#define __ARCH_WANT_NEW_STAT
> >> +#endif /* __LP64__ */
> >
> > Looks good to me.
>
> This is a bit pedantic, but I'm not sure what the right answer is here:
> "-march=rv64gc -mabi=ilp32d" will not define __LP64__, but will define
> "__riscv_xlen == 64".  I actually don't know enough about how an rv64gc/ilp32d
> ABI would work to answer this: would we have "long long" all over our 
> syscalls?
>
> Probably not worth worrying about for now, as we'll have to go audit all of
> these if we ever end up with an ilp32 ABI.  So just go for it and we'll throw
> this on the pile to deal with later :)

GCC will not allow "-march=rv64gc -mabi=ilp32d":

cc1: error: ABI requires -march=rv32

I see that arch/riscv/include/uapi/asm/elf.h already use __riscv_xlen so to be
consistent I will use it too (but I like __LP64__ more as it is well
known macro).

Looking at other UAPI headers I see that include/uapi/linux/rseq.h is using
__LP64__ macro. This header is installed on riscv.

Re: [PATCH] riscv: add asm/unistd.h UAPI header

[David Abdurachmanov]

On Thu, Nov 8, 2018 at 3:10 AM Palmer Dabbelt  wrote:
>
> On Wed, 07 Nov 2018 13:09:39 PST (-0800), Arnd Bergmann wrote:
> > On Wed, Nov 7, 2018 at 7:30 PM David Abdurachmanov
> >  wrote:
> >> On Wed, Nov 7, 2018 at 1:08 AM Palmer Dabbelt  wrote:
> >> > On Mon, 05 Nov 2018 12:56:15 PST (-0800), Arnd Bergmann wrote:
> >
> >> > The target is still the next glibc release (Feb 1st) for a stable RV32I 
> >> > ABI.
> >> > That's progressing well, with one last blocking issue related to some of 
> >> > our
> >> > floating-point emulation routines before we can submit the port.  This 
> >> > should
> >> > give us ample time to line up the ABIs correctly so everything works.
> >> >
> >> > So I think the correct answer here is to drop __ARCH_WANT_STAT64 from 
> >> > RISC-V.
> >> >
> >>
> >> Then if you agree I could do and send v2:
> >>
> >> +#ifdef __LP64__
> >> +#define __ARCH_WANT_NEW_STAT
> >> +#endif /* __LP64__ */
> >
> > Looks good to me.
>
> This is a bit pedantic, but I'm not sure what the right answer is here:
> "-march=rv64gc -mabi=ilp32d" will not define __LP64__, but will define
> "__riscv_xlen == 64".  I actually don't know enough about how an rv64gc/ilp32d
> ABI would work to answer this: would we have "long long" all over our 
> syscalls?
>
> Probably not worth worrying about for now, as we'll have to go audit all of
> these if we ever end up with an ilp32 ABI.  So just go for it and we'll throw
> this on the pile to deal with later :)

GCC will not allow "-march=rv64gc -mabi=ilp32d":

cc1: error: ABI requires -march=rv32

I see that arch/riscv/include/uapi/asm/elf.h already use __riscv_xlen so to be
consistent I will use it too (but I like __LP64__ more as it is well
known macro).

Looking at other UAPI headers I see that include/uapi/linux/rseq.h is using
__LP64__ macro. This header is installed on riscv.

Re: [PATCH] riscv: add asm/unistd.h UAPI header

[David Abdurachmanov]

On Wed, Nov 7, 2018 at 1:08 AM Palmer Dabbelt  wrote:
>
> On Mon, 05 Nov 2018 12:56:15 PST (-0800), Arnd Bergmann wrote:
> > On 11/5/18, David Abdurachmanov  wrote:
> >> Marcin Juszkiewicz reported issues while generating syscall table for riscv
> >> using 4.20-rc1. The patch refactors our unistd.h files to match some other
> >> architectures.
> >>
> >> - Add asm/unistd.h UAPI header, which has __ARCH_WANT_NEW_STAT
> >> - Remove asm/syscalls.h UAPI header and merge to asm/unistd.h
> >> - Adjust kernel asm/unistd.h
> >>
> >> So now asm/unistd.h UAPI header should show all syscalls for riscv.
> >>
> >> Before this, Makefile simply put `#include ` into
> >> generated asm/unistd.h UAPI header thus user didn't see:
> >>
> >> - __NR_riscv_flush_icache
> >> - __NR_newfstatat
> >> - __NR_fstat
> >>
> >> which are supported by riscv kernel.
> >>
> >> Signed-off-by: David Abdurachmanov 
> >> Cc: Arnd Bergmann 
> >> Cc: Marcin Juszkiewicz 
> >> Cc: Guenter Roeck 
> >
> > Thanks for addressing this, your patch correctly fixes riscv64, and
> > I should have noticed the mistake when I originally merged the
> > broken patch.
> >
> > However, looking closer I found another problem with the original
> > patch that your fix does not address:
> >
> > __ARCH_WANT_NEW_STAT should only be set on 64-bit
> > architectures.
> >
> > For a 32-bit architecture, we only want __ARCH_WANT_STAT64 if
> > any. For 64-bit architectures with compat mode, we still need to
> > set __ARCH_WANT_STAT64 from the non-uapi file so we get
> > the syscall implementation.
> >
> > If we don't care about the riscv32 ABI changing yet, we can
> > decide to leave out __ARCH_WANT_STAT64 here, and require
> > glibc to implement it using statx() like any new architecture.
> > stat64 is not y2038 safe, and statx replaces it because of that.
>
> Thanks for pointing this out.   A while ago we decided the rv32 ABI was
> "slushy": it can change if it has a good reason to.  Right now the only 
> planned
> changes are the y2038 changes, which I consider this a part of.  For some
> reason I thought we'd already done this, but since we haven't then I think it
> should go in sooner rather than later -- that will help the glibc guys get
> everything lined up.
>
> The target is still the next glibc release (Feb 1st) for a stable RV32I ABI.
> That's progressing well, with one last blocking issue related to some of our
> floating-point emulation routines before we can submit the port.  This should
> give us ample time to line up the ABIs correctly so everything works.
>
> So I think the correct answer here is to drop __ARCH_WANT_STAT64 from RISC-V.
>

Then if you agree I could do and send v2:

+#ifdef __LP64__
+#define __ARCH_WANT_NEW_STAT
+#endif /* __LP64__ */

Cannot use CONFIG_64BIT as in user space nothing defines it.
Alternatively I could
check for __riscv_xlen == 64.

I found _LP64 and __LP64__ being used in kernel, incl. include/uapi/linux/rseq.h

david

Re: [PATCH] riscv: add asm/unistd.h UAPI header

[David Abdurachmanov]

On Wed, Nov 7, 2018 at 1:08 AM Palmer Dabbelt  wrote:
>
> On Mon, 05 Nov 2018 12:56:15 PST (-0800), Arnd Bergmann wrote:
> > On 11/5/18, David Abdurachmanov  wrote:
> >> Marcin Juszkiewicz reported issues while generating syscall table for riscv
> >> using 4.20-rc1. The patch refactors our unistd.h files to match some other
> >> architectures.
> >>
> >> - Add asm/unistd.h UAPI header, which has __ARCH_WANT_NEW_STAT
> >> - Remove asm/syscalls.h UAPI header and merge to asm/unistd.h
> >> - Adjust kernel asm/unistd.h
> >>
> >> So now asm/unistd.h UAPI header should show all syscalls for riscv.
> >>
> >> Before this, Makefile simply put `#include ` into
> >> generated asm/unistd.h UAPI header thus user didn't see:
> >>
> >> - __NR_riscv_flush_icache
> >> - __NR_newfstatat
> >> - __NR_fstat
> >>
> >> which are supported by riscv kernel.
> >>
> >> Signed-off-by: David Abdurachmanov 
> >> Cc: Arnd Bergmann 
> >> Cc: Marcin Juszkiewicz 
> >> Cc: Guenter Roeck 
> >
> > Thanks for addressing this, your patch correctly fixes riscv64, and
> > I should have noticed the mistake when I originally merged the
> > broken patch.
> >
> > However, looking closer I found another problem with the original
> > patch that your fix does not address:
> >
> > __ARCH_WANT_NEW_STAT should only be set on 64-bit
> > architectures.
> >
> > For a 32-bit architecture, we only want __ARCH_WANT_STAT64 if
> > any. For 64-bit architectures with compat mode, we still need to
> > set __ARCH_WANT_STAT64 from the non-uapi file so we get
> > the syscall implementation.
> >
> > If we don't care about the riscv32 ABI changing yet, we can
> > decide to leave out __ARCH_WANT_STAT64 here, and require
> > glibc to implement it using statx() like any new architecture.
> > stat64 is not y2038 safe, and statx replaces it because of that.
>
> Thanks for pointing this out.   A while ago we decided the rv32 ABI was
> "slushy": it can change if it has a good reason to.  Right now the only 
> planned
> changes are the y2038 changes, which I consider this a part of.  For some
> reason I thought we'd already done this, but since we haven't then I think it
> should go in sooner rather than later -- that will help the glibc guys get
> everything lined up.
>
> The target is still the next glibc release (Feb 1st) for a stable RV32I ABI.
> That's progressing well, with one last blocking issue related to some of our
> floating-point emulation routines before we can submit the port.  This should
> give us ample time to line up the ABIs correctly so everything works.
>
> So I think the correct answer here is to drop __ARCH_WANT_STAT64 from RISC-V.
>

Then if you agree I could do and send v2:

+#ifdef __LP64__
+#define __ARCH_WANT_NEW_STAT
+#endif /* __LP64__ */

Cannot use CONFIG_64BIT as in user space nothing defines it.
Alternatively I could
check for __riscv_xlen == 64.

I found _LP64 and __LP64__ being used in kernel, incl. include/uapi/linux/rseq.h

david

Re: [PATCH] riscv: add asm/unistd.h UAPI header

[David Abdurachmanov]

On Mon, Nov 5, 2018 at 3:26 PM David Abdurachmanov
 wrote:

[..]
> diff --git a/arch/riscv/include/uapi/asm/syscalls.h 
> b/arch/riscv/include/uapi/asm/unistd.h
> similarity index 54%
> rename from arch/riscv/include/uapi/asm/syscalls.h
> rename to arch/riscv/include/uapi/asm/unistd.h
> index 206dc4b0f6ea..5545f498071d 100644
[..]

I forgot to pass --no-renames to git format-patch.
If you want I can resend it with --no-renames to make it
a bit more readable.

david

Re: [PATCH] riscv: add asm/unistd.h UAPI header

[David Abdurachmanov]

On Mon, Nov 5, 2018 at 3:26 PM David Abdurachmanov
 wrote:

[..]
> diff --git a/arch/riscv/include/uapi/asm/syscalls.h 
> b/arch/riscv/include/uapi/asm/unistd.h
> similarity index 54%
> rename from arch/riscv/include/uapi/asm/syscalls.h
> rename to arch/riscv/include/uapi/asm/unistd.h
> index 206dc4b0f6ea..5545f498071d 100644
[..]

I forgot to pass --no-renames to git format-patch.
If you want I can resend it with --no-renames to make it
a bit more readable.

david

[PATCH] riscv: fix spacing in struct pt_regs

[David Abdurachmanov]

Replace 8 spaces with tab to match styling.

Signed-off-by: David Abdurachmanov 
---
 arch/riscv/include/asm/ptrace.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/include/asm/ptrace.h b/arch/riscv/include/asm/ptrace.h
index 2c5df945d43c..bbe1862e8f80 100644
--- a/arch/riscv/include/asm/ptrace.h
+++ b/arch/riscv/include/asm/ptrace.h
@@ -56,8 +56,8 @@ struct pt_regs {
unsigned long sstatus;
unsigned long sbadaddr;
unsigned long scause;
-/* a0 value before the syscall */
-unsigned long orig_a0;
+   /* a0 value before the syscall */
+   unsigned long orig_a0;
 };
 
 #ifdef CONFIG_64BIT
-- 
2.19.1

[PATCH] riscv: fix spacing in struct pt_regs

[David Abdurachmanov]

Replace 8 spaces with tab to match styling.

Signed-off-by: David Abdurachmanov 
---
 arch/riscv/include/asm/ptrace.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/include/asm/ptrace.h b/arch/riscv/include/asm/ptrace.h
index 2c5df945d43c..bbe1862e8f80 100644
--- a/arch/riscv/include/asm/ptrace.h
+++ b/arch/riscv/include/asm/ptrace.h
@@ -56,8 +56,8 @@ struct pt_regs {
unsigned long sstatus;
unsigned long sbadaddr;
unsigned long scause;
-/* a0 value before the syscall */
-unsigned long orig_a0;
+   /* a0 value before the syscall */
+   unsigned long orig_a0;
 };
 
 #ifdef CONFIG_64BIT
-- 
2.19.1

[PATCH] riscv: add missing vdso_install target

[David Abdurachmanov]

Building kernel 4.20 for Fedora as RPM fails, because riscv is missing
vdso_install target in arch/riscv/Makefile.

Signed-off-by: David Abdurachmanov 
---
 arch/riscv/Makefile | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index d10146197533..4af153a182b0 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -77,4 +77,8 @@ core-y += arch/riscv/kernel/ arch/riscv/mm/
 
 libs-y += arch/riscv/lib/
 
+PHONY += vdso_install
+vdso_install:
+   $(Q)$(MAKE) $(build)=arch/riscv/kernel/vdso $@
+
 all: vmlinux
-- 
2.19.1

[PATCH] riscv: add missing vdso_install target

[David Abdurachmanov]

Building kernel 4.20 for Fedora as RPM fails, because riscv is missing
vdso_install target in arch/riscv/Makefile.

Signed-off-by: David Abdurachmanov 
---
 arch/riscv/Makefile | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index d10146197533..4af153a182b0 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -77,4 +77,8 @@ core-y += arch/riscv/kernel/ arch/riscv/mm/
 
 libs-y += arch/riscv/lib/
 
+PHONY += vdso_install
+vdso_install:
+   $(Q)$(MAKE) $(build)=arch/riscv/kernel/vdso $@
+
 all: vmlinux
-- 
2.19.1

[PATCH] riscv: add asm/unistd.h UAPI header

[David Abdurachmanov]

Marcin Juszkiewicz reported issues while generating syscall table for riscv
using 4.20-rc1. The patch refactors our unistd.h files to match some other
architectures.

- Add asm/unistd.h UAPI header, which has __ARCH_WANT_NEW_STAT
- Remove asm/syscalls.h UAPI header and merge to asm/unistd.h
- Adjust kernel asm/unistd.h

So now asm/unistd.h UAPI header should show all syscalls for riscv.

Before this, Makefile simply put `#include ` into
generated asm/unistd.h UAPI header thus user didn't see:

- __NR_riscv_flush_icache
- __NR_newfstatat
- __NR_fstat

which are supported by riscv kernel.

Signed-off-by: David Abdurachmanov 
Cc: Arnd Bergmann 
Cc: Marcin Juszkiewicz 
Cc: Guenter Roeck 
Fixes: 67314ec7b025
---
 arch/riscv/include/asm/unistd.h   |  5 ++--
 .../include/uapi/asm/{syscalls.h => unistd.h} | 24 +--
 2 files changed, 19 insertions(+), 10 deletions(-)
 rename arch/riscv/include/uapi/asm/{syscalls.h => unistd.h} (54%)

diff --git a/arch/riscv/include/asm/unistd.h b/arch/riscv/include/asm/unistd.h
index eff7aa9aa163..fef96f117b4d 100644
--- a/arch/riscv/include/asm/unistd.h
+++ b/arch/riscv/include/asm/unistd.h
@@ -13,10 +13,9 @@
 
 /*
  * There is explicitly no include guard here because this file is expected to
- * be included multiple times.  See uapi/asm/syscalls.h for more info.
+ * be included multiple times.
  */
 
-#define __ARCH_WANT_NEW_STAT
 #define __ARCH_WANT_SYS_CLONE
+
 #include 
-#include 
diff --git a/arch/riscv/include/uapi/asm/syscalls.h 
b/arch/riscv/include/uapi/asm/unistd.h
similarity index 54%
rename from arch/riscv/include/uapi/asm/syscalls.h
rename to arch/riscv/include/uapi/asm/unistd.h
index 206dc4b0f6ea..5545f498071d 100644
--- a/arch/riscv/include/uapi/asm/syscalls.h
+++ b/arch/riscv/include/uapi/asm/unistd.h
@@ -1,13 +1,23 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
 /*
- * Copyright (C) 2017-2018 SiFive
+ * Copyright (C) 2018 David Abdurachmanov 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-/*
- * There is explicitly no include guard here because this file is expected to
- * be included multiple times in order to define the syscall macros via
- * __SYSCALL.
- */
+#define __ARCH_WANT_NEW_STAT
+
+#include 
 
 /*
  * Allows the instruction cache to be flushed from userspace.  Despite RISC-V
-- 
2.19.1

[PATCH] riscv: add asm/unistd.h UAPI header

[David Abdurachmanov]

Marcin Juszkiewicz reported issues while generating syscall table for riscv
using 4.20-rc1. The patch refactors our unistd.h files to match some other
architectures.

- Add asm/unistd.h UAPI header, which has __ARCH_WANT_NEW_STAT
- Remove asm/syscalls.h UAPI header and merge to asm/unistd.h
- Adjust kernel asm/unistd.h

So now asm/unistd.h UAPI header should show all syscalls for riscv.

Before this, Makefile simply put `#include ` into
generated asm/unistd.h UAPI header thus user didn't see:

- __NR_riscv_flush_icache
- __NR_newfstatat
- __NR_fstat

which are supported by riscv kernel.

Signed-off-by: David Abdurachmanov 
Cc: Arnd Bergmann 
Cc: Marcin Juszkiewicz 
Cc: Guenter Roeck 
Fixes: 67314ec7b025
---
 arch/riscv/include/asm/unistd.h   |  5 ++--
 .../include/uapi/asm/{syscalls.h => unistd.h} | 24 +--
 2 files changed, 19 insertions(+), 10 deletions(-)
 rename arch/riscv/include/uapi/asm/{syscalls.h => unistd.h} (54%)

diff --git a/arch/riscv/include/asm/unistd.h b/arch/riscv/include/asm/unistd.h
index eff7aa9aa163..fef96f117b4d 100644
--- a/arch/riscv/include/asm/unistd.h
+++ b/arch/riscv/include/asm/unistd.h
@@ -13,10 +13,9 @@
 
 /*
  * There is explicitly no include guard here because this file is expected to
- * be included multiple times.  See uapi/asm/syscalls.h for more info.
+ * be included multiple times.
  */
 
-#define __ARCH_WANT_NEW_STAT
 #define __ARCH_WANT_SYS_CLONE
+
 #include 
-#include 
diff --git a/arch/riscv/include/uapi/asm/syscalls.h 
b/arch/riscv/include/uapi/asm/unistd.h
similarity index 54%
rename from arch/riscv/include/uapi/asm/syscalls.h
rename to arch/riscv/include/uapi/asm/unistd.h
index 206dc4b0f6ea..5545f498071d 100644
--- a/arch/riscv/include/uapi/asm/syscalls.h
+++ b/arch/riscv/include/uapi/asm/unistd.h
@@ -1,13 +1,23 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
 /*
- * Copyright (C) 2017-2018 SiFive
+ * Copyright (C) 2018 David Abdurachmanov 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-/*
- * There is explicitly no include guard here because this file is expected to
- * be included multiple times in order to define the syscall macros via
- * __SYSCALL.
- */
+#define __ARCH_WANT_NEW_STAT
+
+#include 
 
 /*
  * Allows the instruction cache to be flushed from userspace.  Despite RISC-V
-- 
2.19.1

[PATCH 0/2] riscv: add ARCH_HAS_SG_CHAIN to Kconfig

[David Abdurachmanov]

This should improve virtio-gpu support for riscv.

David Abdurachmanov (2):
  riscv: add ARCH_HAS_SG_CHAIN
  doc: re-run features-refresh.sh

 Documentation/features/io/sg-chain/arch-support.txt   | 4 ++--
 .../features/locking/queued-spinlocks/arch-support.txt| 2 +-
 Documentation/features/perf/kprobes-event/arch-support.txt| 2 +-
 Documentation/features/vm/pte_special/arch-support.txt| 2 +-
 arch/riscv/Kconfig| 1 +
 5 files changed, 6 insertions(+), 5 deletions(-)

-- 
2.17.2

[PATCH 0/2] riscv: add ARCH_HAS_SG_CHAIN to Kconfig

[David Abdurachmanov]

This should improve virtio-gpu support for riscv.

David Abdurachmanov (2):
  riscv: add ARCH_HAS_SG_CHAIN
  doc: re-run features-refresh.sh

 Documentation/features/io/sg-chain/arch-support.txt   | 4 ++--
 .../features/locking/queued-spinlocks/arch-support.txt| 2 +-
 Documentation/features/perf/kprobes-event/arch-support.txt| 2 +-
 Documentation/features/vm/pte_special/arch-support.txt| 2 +-
 arch/riscv/Kconfig| 1 +
 5 files changed, 6 insertions(+), 5 deletions(-)

-- 
2.17.2

[PATCH 1/2] riscv: add ARCH_HAS_SG_CHAIN

[David Abdurachmanov]

This seems to be needed for virtio-gpu.

Signed-off-by: David Abdurachmanov 
Reported-by: Michael Forney 
---
 arch/riscv/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index a344980287a5..b54f2ade769b 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -44,6 +44,7 @@ config RISCV
select RISCV_TIMER
select GENERIC_IRQ_MULTI_HANDLER
select ARCH_HAS_PTE_SPECIAL
+   select ARCH_HAS_SG_CHAIN
 
 config MMU
def_bool y
-- 
2.17.2

[PATCH 2/2] doc: re-run features-refresh.sh

[David Abdurachmanov]

Some arch-support.txt are out-of-date.
This also incl. riscv in sg-chain and pte_special tables.

Signed-off-by: David Abdurachmanov 
---
 Documentation/features/io/sg-chain/arch-support.txt   | 4 ++--
 .../features/locking/queued-spinlocks/arch-support.txt| 2 +-
 Documentation/features/perf/kprobes-event/arch-support.txt| 2 +-
 Documentation/features/vm/pte_special/arch-support.txt| 2 +-
 4 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/Documentation/features/io/sg-chain/arch-support.txt 
b/Documentation/features/io/sg-chain/arch-support.txt
index 6554f0372c3f..41ea6f738b38 100644
--- a/Documentation/features/io/sg-chain/arch-support.txt
+++ b/Documentation/features/io/sg-chain/arch-support.txt
@@ -22,12 +22,12 @@
 |openrisc: | TODO |
 |  parisc: | TODO |
 | powerpc: |  ok  |
-|   riscv: | TODO |
+|   riscv: |  ok  |
 |s390: |  ok  |
 |  sh: | TODO |
 |   sparc: |  ok  |
 |  um: | TODO |
 |   unicore32: | TODO |
 | x86: |  ok  |
-|  xtensa: | TODO |
+|  xtensa: |  ok  |
 ---
diff --git a/Documentation/features/locking/queued-spinlocks/arch-support.txt 
b/Documentation/features/locking/queued-spinlocks/arch-support.txt
index 478e9101322c..beb013a72a90 100644
--- a/Documentation/features/locking/queued-spinlocks/arch-support.txt
+++ b/Documentation/features/locking/queued-spinlocks/arch-support.txt
@@ -9,7 +9,7 @@
 |   alpha: | TODO |
 | arc: | TODO |
 | arm: | TODO |
-|   arm64: | TODO |
+|   arm64: |  ok  |
 | c6x: | TODO |
 |   h8300: | TODO |
 | hexagon: | TODO |
diff --git a/Documentation/features/perf/kprobes-event/arch-support.txt 
b/Documentation/features/perf/kprobes-event/arch-support.txt
index 7331402d1887..bfe41d68b7af 100644
--- a/Documentation/features/perf/kprobes-event/arch-support.txt
+++ b/Documentation/features/perf/kprobes-event/arch-support.txt
@@ -20,7 +20,7 @@
 |   nds32: |  ok  |
 |   nios2: | TODO |
 |openrisc: | TODO |
-|  parisc: | TODO |
+|  parisc: |  ok  |
 | powerpc: |  ok  |
 |   riscv: | TODO |
 |s390: |  ok  |
diff --git a/Documentation/features/vm/pte_special/arch-support.txt 
b/Documentation/features/vm/pte_special/arch-support.txt
index a8378424bc98..5bca00664a4f 100644
--- a/Documentation/features/vm/pte_special/arch-support.txt
+++ b/Documentation/features/vm/pte_special/arch-support.txt
@@ -22,7 +22,7 @@
 |openrisc: | TODO |
 |  parisc: | TODO |
 | powerpc: |  ok  |
-|   riscv: | TODO |
+|   riscv: |  ok  |
 |s390: |  ok  |
 |  sh: |  ok  |
 |   sparc: |  ok  |
-- 
2.17.2

[PATCH 1/2] riscv: add ARCH_HAS_SG_CHAIN

[David Abdurachmanov]

This seems to be needed for virtio-gpu.

Signed-off-by: David Abdurachmanov 
Reported-by: Michael Forney 
---
 arch/riscv/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index a344980287a5..b54f2ade769b 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -44,6 +44,7 @@ config RISCV
select RISCV_TIMER
select GENERIC_IRQ_MULTI_HANDLER
select ARCH_HAS_PTE_SPECIAL
+   select ARCH_HAS_SG_CHAIN
 
 config MMU
def_bool y
-- 
2.17.2

[PATCH 2/2] doc: re-run features-refresh.sh

[David Abdurachmanov]

Some arch-support.txt are out-of-date.
This also incl. riscv in sg-chain and pte_special tables.

Signed-off-by: David Abdurachmanov 
---
 Documentation/features/io/sg-chain/arch-support.txt   | 4 ++--
 .../features/locking/queued-spinlocks/arch-support.txt| 2 +-
 Documentation/features/perf/kprobes-event/arch-support.txt| 2 +-
 Documentation/features/vm/pte_special/arch-support.txt| 2 +-
 4 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/Documentation/features/io/sg-chain/arch-support.txt 
b/Documentation/features/io/sg-chain/arch-support.txt
index 6554f0372c3f..41ea6f738b38 100644
--- a/Documentation/features/io/sg-chain/arch-support.txt
+++ b/Documentation/features/io/sg-chain/arch-support.txt
@@ -22,12 +22,12 @@
 |openrisc: | TODO |
 |  parisc: | TODO |
 | powerpc: |  ok  |
-|   riscv: | TODO |
+|   riscv: |  ok  |
 |s390: |  ok  |
 |  sh: | TODO |
 |   sparc: |  ok  |
 |  um: | TODO |
 |   unicore32: | TODO |
 | x86: |  ok  |
-|  xtensa: | TODO |
+|  xtensa: |  ok  |
 ---
diff --git a/Documentation/features/locking/queued-spinlocks/arch-support.txt 
b/Documentation/features/locking/queued-spinlocks/arch-support.txt
index 478e9101322c..beb013a72a90 100644
--- a/Documentation/features/locking/queued-spinlocks/arch-support.txt
+++ b/Documentation/features/locking/queued-spinlocks/arch-support.txt
@@ -9,7 +9,7 @@
 |   alpha: | TODO |
 | arc: | TODO |
 | arm: | TODO |
-|   arm64: | TODO |
+|   arm64: |  ok  |
 | c6x: | TODO |
 |   h8300: | TODO |
 | hexagon: | TODO |
diff --git a/Documentation/features/perf/kprobes-event/arch-support.txt 
b/Documentation/features/perf/kprobes-event/arch-support.txt
index 7331402d1887..bfe41d68b7af 100644
--- a/Documentation/features/perf/kprobes-event/arch-support.txt
+++ b/Documentation/features/perf/kprobes-event/arch-support.txt
@@ -20,7 +20,7 @@
 |   nds32: |  ok  |
 |   nios2: | TODO |
 |openrisc: | TODO |
-|  parisc: | TODO |
+|  parisc: |  ok  |
 | powerpc: |  ok  |
 |   riscv: | TODO |
 |s390: |  ok  |
diff --git a/Documentation/features/vm/pte_special/arch-support.txt 
b/Documentation/features/vm/pte_special/arch-support.txt
index a8378424bc98..5bca00664a4f 100644
--- a/Documentation/features/vm/pte_special/arch-support.txt
+++ b/Documentation/features/vm/pte_special/arch-support.txt
@@ -22,7 +22,7 @@
 |openrisc: | TODO |
 |  parisc: | TODO |
 | powerpc: |  ok  |
-|   riscv: | TODO |
+|   riscv: |  ok  |
 |s390: |  ok  |
 |  sh: |  ok  |
 |   sparc: |  ok  |
-- 
2.17.2

Re: [PATCH] riscv: fix trace_sys_exit hook

[David Abdurachmanov]

On Mon, Oct 29, 2018 at 1:15 PM David Abdurachmanov
 wrote:
>
> Depends on:
> http://lists.infradead.org/pipermail/linux-riscv/2018-October/001931.html
>
> Why we don't have HAVE_SYSCALL_TRACEPOINTS in arch/riscv/Kconfig?
>

I looked this morning into Documentation/trace/ftrace-design.rst again.

Of all the things the document describes we are only missing
HAVE_SYSCALL_TRACEPOINTS in Kconfig, yet we already have it
implemented in ptrace.c (+ this minor fix). Reading document, I think,
we check all the boxes needed for HAVE_SYSCALL_TRACEPOINTS.

I assume it was just missed (?) and will do v2 later on.

david

Re: [PATCH] riscv: fix trace_sys_exit hook

[David Abdurachmanov]

On Mon, Oct 29, 2018 at 1:15 PM David Abdurachmanov
 wrote:
>
> Depends on:
> http://lists.infradead.org/pipermail/linux-riscv/2018-October/001931.html
>
> Why we don't have HAVE_SYSCALL_TRACEPOINTS in arch/riscv/Kconfig?
>

I looked this morning into Documentation/trace/ftrace-design.rst again.

Of all the things the document describes we are only missing
HAVE_SYSCALL_TRACEPOINTS in Kconfig, yet we already have it
implemented in ptrace.c (+ this minor fix). Reading document, I think,
we check all the boxes needed for HAVE_SYSCALL_TRACEPOINTS.

I assume it was just missed (?) and will do v2 later on.

david

[PATCH] riscv: fix trace_sys_exit hook

[David Abdurachmanov]

Depends on:
http://lists.infradead.org/pipermail/linux-riscv/2018-October/001931.html

Why we don't have HAVE_SYSCALL_TRACEPOINTS in arch/riscv/Kconfig?

Signed-off-by: David Abdurachmanov 
---
 arch/riscv/kernel/ptrace.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/kernel/ptrace.c b/arch/riscv/kernel/ptrace.c
index 9f82a7e34c64..9db7d0076375 100644
--- a/arch/riscv/kernel/ptrace.c
+++ b/arch/riscv/kernel/ptrace.c
@@ -120,6 +120,6 @@ void do_syscall_trace_exit(struct pt_regs *regs)
 
 #ifdef CONFIG_HAVE_SYSCALL_TRACEPOINTS
if (test_thread_flag(TIF_SYSCALL_TRACEPOINT))
-   trace_sys_exit(regs, regs->regs[0]);
+   trace_sys_exit(regs, regs_return_value(regs));
 #endif
 }
-- 
2.17.2

[PATCH] riscv: fix trace_sys_exit hook

[David Abdurachmanov]

Depends on:
http://lists.infradead.org/pipermail/linux-riscv/2018-October/001931.html

Why we don't have HAVE_SYSCALL_TRACEPOINTS in arch/riscv/Kconfig?

Signed-off-by: David Abdurachmanov 
---
 arch/riscv/kernel/ptrace.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/kernel/ptrace.c b/arch/riscv/kernel/ptrace.c
index 9f82a7e34c64..9db7d0076375 100644
--- a/arch/riscv/kernel/ptrace.c
+++ b/arch/riscv/kernel/ptrace.c
@@ -120,6 +120,6 @@ void do_syscall_trace_exit(struct pt_regs *regs)
 
 #ifdef CONFIG_HAVE_SYSCALL_TRACEPOINTS
if (test_thread_flag(TIF_SYSCALL_TRACEPOINT))
-   trace_sys_exit(regs, regs->regs[0]);
+   trace_sys_exit(regs, regs_return_value(regs));
 #endif
 }
-- 
2.17.2