[PATCH 1/2] net: hix5hd2_gmac: fix compatible strings name
The SoC hix5hd2 compatible string has the suffix "-gmac" and
we should not change its compatible string.
So we should name all the compatible string with the suffix "-gmac".
Creating a new name suffix "-gemac" is unnecessary.
We also add another SoC compatible string in dt binding documentation
and describe which generic version the SoC belongs to.
Fixes: d0fb6ba75dc0 ("net: hix5hd2_gmac: add generic compatible string")
Signed-off-by: Dongpo Li
---
.../devicetree/bindings/net/hisilicon-hix5hd2-gmac.txt | 13 -
drivers/net/ethernet/hisilicon/hix5hd2_gmac.c | 13 +++--
2 files changed, 15 insertions(+), 11 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/hisilicon-hix5hd2-gmac.txt
b/Documentation/devicetree/bindings/net/hisilicon-hix5hd2-gmac.txt
index 063c02d..eea73ad 100644
--- a/Documentation/devicetree/bindings/net/hisilicon-hix5hd2-gmac.txt
+++ b/Documentation/devicetree/bindings/net/hisilicon-hix5hd2-gmac.txt
@@ -2,11 +2,14 @@ Hisilicon hix5hd2 gmac controller
Required properties:
- compatible: should contain one of the following SoC strings:
- * "hisilicon,hix5hd2-gemac"
- * "hisilicon,hi3798cv200-gemac"
+ * "hisilicon,hix5hd2-gmac"
+ * "hisilicon,hi3798cv200-gmac"
+ * "hisilicon,hi3516a-gmac"
and one of the following version string:
- * "hisilicon,hisi-gemac-v1"
- * "hisilicon,hisi-gemac-v2"
+ * "hisilicon,hisi-gmac-v1"
+ * "hisilicon,hisi-gmac-v2"
+ The version v1 includes SoCs hix5hd2.
+ The version v2 includes SoCs hi3798cv200, hi3516a.
- reg: specifies base physical address(s) and size of the device registers.
The first region is the MAC register base and size.
The second region is external interface control register.
@@ -35,7 +38,7 @@ Required properties:
Example:
gmac0: ethernet@f984 {
- compatible = "hisilicon,hi3798cv200-gemac",
"hisilicon,hisi-gemac-v2";
+ compatible = "hisilicon,hi3798cv200-gmac",
"hisilicon,hisi-gmac-v2";
reg = <0xf984 0x1000>,<0xf984300c 0x4>;
interrupts = <0 71 4>;
#address-cells = <1>;
diff --git a/drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
b/drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
index ee7e9ce..418ca1f3 100644
--- a/drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
+++ b/drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
@@ -1316,10 +1316,11 @@ static int hix5hd2_dev_remove(struct platform_device
*pdev)
}
static const struct of_device_id hix5hd2_of_match[] = {
- { .compatible = "hisilicon,hisi-gemac-v1", .data = (void *)GEMAC_V1 },
- { .compatible = "hisilicon,hisi-gemac-v2", .data = (void *)GEMAC_V2 },
- { .compatible = "hisilicon,hix5hd2-gemac", .data = (void *)GEMAC_V1 },
- { .compatible = "hisilicon,hi3798cv200-gemac", .data = (void *)GEMAC_V2
},
+ { .compatible = "hisilicon,hisi-gmac-v1", .data = (void *)GEMAC_V1 },
+ { .compatible = "hisilicon,hisi-gmac-v2", .data = (void *)GEMAC_V2 },
+ { .compatible = "hisilicon,hix5hd2-gmac", .data = (void *)GEMAC_V1 },
+ { .compatible = "hisilicon,hi3798cv200-gmac", .data = (void *)GEMAC_V2
},
+ { .compatible = "hisilicon,hi3516a-gmac", .data = (void *)GEMAC_V2 },
{},
};
@@ -1327,7 +1328,7 @@ MODULE_DEVICE_TABLE(of, hix5hd2_of_match);
static struct platform_driver hix5hd2_dev_driver = {
.driver = {
- .name = "hisi-gemac",
+ .name = "hisi-gmac",
.of_match_table = hix5hd2_of_match,
},
.probe = hix5hd2_dev_probe,
@@ -1338,4 +1339,4 @@ module_platform_driver(hix5hd2_dev_driver);
MODULE_DESCRIPTION("HISILICON Gigabit Ethernet MAC driver");
MODULE_LICENSE("GPL v2");
-MODULE_ALIAS("platform:hisi-gemac");
+MODULE_ALIAS("platform:hisi-gmac");
--
2.8.2
[PATCH 2/2] ARM: dts: hix5hd2: don't change the existing compatible string
The SoC hix5hd2 compatible string has the suffix "-gmac" and
we should not change it.
We should only add the generic compatible string "hisi-gmac-v1".
Fixes: 0855950ba580 ("ARM: dts: hix5hd2: add gmac generic compatible and clock
names")
Signed-off-by: Dongpo Li
---
arch/arm/boot/dts/hisi-x5hd2.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi
b/arch/arm/boot/dts/hisi-x5hd2.dtsi
index 0da76c5..2d06f4c 100644
--- a/arch/arm/boot/dts/hisi-x5hd2.dtsi
+++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi
@@ -436,7 +436,7 @@
};
gmac0: ethernet@184 {
- compatible = "hisilicon,hix5hd2-gemac",
"hisilicon,hisi-gemac-v1";
+ compatible = "hisilicon,hix5hd2-gmac",
"hisilicon,hisi-gmac-v1";
reg = <0x184 0x1000>,<0x184300c 0x4>;
interrupts = <0 71 4>;
clocks = <&clock HIX5HD2_MAC0_CLK>;
@@ -445,7 +445,7 @@
};
gmac1: ethernet@1841000 {
- compatible = "hisilicon,hix5hd2-gemac",
"hisilicon,hisi-gemac-v1";
+ compatible = "hisilicon,hix5hd2-gmac",
"hisilicon,hisi-gmac-v1";
reg = <0x1841000 0x1000>,<0x1843010 0x4>;
interrupts = <0 72 4>;
clocks = <&clock HIX5HD2_MAC1_CLK>;
--
2.8.2
[PATCH 0/2] net: hix5hd2_gmac: keep the compatible string not changed
This patch series fix the patch:
d0fb6ba75dc0 ("net: hix5hd2_gmac: add generic compatible string")
The SoC hix5hd2 compatible string has the suffix "-gmac" and
we should not change its compatible string.
So we should name all the compatible string with the suffix "-gmac".
Creating a new name suffix "-gemac" is unnecessary.
Dongpo Li (2):
net: hix5hd2_gmac: fix compatible strings name
ARM: dts: hix5hd2: don't change the existing compatible string
.../devicetree/bindings/net/hisilicon-hix5hd2-gmac.txt | 13 -
arch/arm/boot/dts/hisi-x5hd2.dtsi | 4 ++--
drivers/net/ethernet/hisilicon/hix5hd2_gmac.c | 13 +++--
3 files changed, 17 insertions(+), 13 deletions(-)
--
2.8.2
Re: [PATCH v2 1/4] net: hix5hd2_gmac: add generic compatible string
On 2016/12/20 0:04, Rob Herring wrote:
> On Mon, Dec 19, 2016 at 2:14 AM, Dongpo Li wrote:
>> Hi Rob and David,
>>
>> On 2016/12/12 22:21, Rob Herring wrote:
>>> On Mon, Dec 12, 2016 at 5:16 AM, Dongpo Li wrote:
>>>> Hi Rob,
>>>>
>>>> On 2016/12/10 6:35, Rob Herring wrote:
>>>>> On Mon, Dec 05, 2016 at 09:27:58PM +0800, Dongpo Li wrote:
>
> [...]
>
>>>>>> @@ -20,7 +25,7 @@ Required properties:
>>>>>>
>>>>>> Example:
>>>>>> gmac0: ethernet@f984 {
>>>>>> -compatible = "hisilicon,hix5hd2-gmac";
>>>>>> +compatible = "hisilicon,hix5hd2-gemac",
>>>>>> "hisilicon,hisi-gemac-v1";
>>>>>
>>>>> You can't just change compatible strings.
>>>>>
>>>> Okay, maybe I should name all the compatible string with the suffix
>>>> "-gmac" instead of
>>>> "-gemac". This can keep the compatible strings with the same suffix. Is
>>>> this okay?
>>>> Can I just add the generic compatible string without changing the SoCs
>>>> compatible string?
>>>> Like following:
>>>> gmac0: ethernet@f984 {
>>>> - compatible = "hisilicon,hix5hd2-gmac";
>>>> + compatible = "hisilicon,hix5hd2-gmac",
>>>> "hisilicon,hisi-gmac-v1";
>>>
>>> Yes, this is fine.
>>
>> As the patch series have been applied to net-next branch,
>> in which way should I commit this compatible fix?
>> Should I send a new patch fixing this compatible string error with "Fixes:
>> xxx"?
>> Looking forward to your reply!
>
> Yes to both.
Okay, thanks for your reply!
I will send the fix patch series as soon as possible.
Regards,
Dongpo
.
Re: [PATCH v2 1/4] net: hix5hd2_gmac: add generic compatible string
Hi Rob and David,
On 2016/12/12 22:21, Rob Herring wrote:
> On Mon, Dec 12, 2016 at 5:16 AM, Dongpo Li wrote:
>> Hi Rob,
>>
>> On 2016/12/10 6:35, Rob Herring wrote:
>>> On Mon, Dec 05, 2016 at 09:27:58PM +0800, Dongpo Li wrote:
>>>> The "hix5hd2" is SoC name, add the generic ethernet driver name.
>>>> The "hisi-gemac-v1" is the basic version and "hisi-gemac-v2" adds
>>>> the SG/TXCSUM/TSO/UFO features.
>>>>
>>>> Signed-off-by: Dongpo Li
>>>> ---
>>>> .../devicetree/bindings/net/hisilicon-hix5hd2-gmac.txt| 9 +++--
>>>> drivers/net/ethernet/hisilicon/hix5hd2_gmac.c | 15
>>>> +++
>>>> 2 files changed, 18 insertions(+), 6 deletions(-)
>>>>
>>>> diff --git
>>>> a/Documentation/devicetree/bindings/net/hisilicon-hix5hd2-gmac.txt
>>>> b/Documentation/devicetree/bindings/net/hisilicon-hix5hd2-gmac.txt
>>>> index 75d398b..75920f0 100644
>>>> --- a/Documentation/devicetree/bindings/net/hisilicon-hix5hd2-gmac.txt
>>>> +++ b/Documentation/devicetree/bindings/net/hisilicon-hix5hd2-gmac.txt
>>>> @@ -1,7 +1,12 @@
>>>> Hisilicon hix5hd2 gmac controller
>>>>
>>>> Required properties:
>>>> -- compatible: should be "hisilicon,hix5hd2-gmac".
>>>> +- compatible: should contain one of the following SoC strings:
>>>> +* "hisilicon,hix5hd2-gemac"
>>>> +* "hisilicon,hi3798cv200-gemac"
>>>> +and one of the following version string:
>>>> +* "hisilicon,hisi-gemac-v1"
>>>> +* "hisilicon,hisi-gemac-v2"
>>>
>>> What combinations are valid? I assume both chips don't have both v1 and
>>> v2. 2 SoCs and 2 versions so far, I don't think there is much point to
>>> have the v1 and v2 compatible strings.
>>>
>> The v1 and v2 are generic MAC compatible strings, many HiSilicon SoCs may
>> use the same MAC version. For example,
>> hix5hd2, hi3716cv200 SoCs use the v1 MAC version,
>> hi3798cv200, hi3516a SoCs use the v2 MAC version,
>> and there may be more SoCs added in future.
>> So I think the generic compatible strings are okay here.
>> Should I add the hi3716cv200, hi3516a SoCs compatible here?
>
> Yes.
>
>> Do you have any good advice?
>>
>>>> - reg: specifies base physical address(s) and size of the device
>>>> registers.
>>>>The first region is the MAC register base and size.
>>>>The second region is external interface control register.
>>>> @@ -20,7 +25,7 @@ Required properties:
>>>>
>>>> Example:
>>>> gmac0: ethernet@f984 {
>>>> -compatible = "hisilicon,hix5hd2-gmac";
>>>> +compatible = "hisilicon,hix5hd2-gemac",
>>>> "hisilicon,hisi-gemac-v1";
>>>
>>> You can't just change compatible strings.
>>>
>> Okay, maybe I should name all the compatible string with the suffix "-gmac"
>> instead of
>> "-gemac". This can keep the compatible strings with the same suffix. Is this
>> okay?
>> Can I just add the generic compatible string without changing the SoCs
>> compatible string?
>> Like following:
>> gmac0: ethernet@f984 {
>> - compatible = "hisilicon,hix5hd2-gmac";
>> + compatible = "hisilicon,hix5hd2-gmac",
>> "hisilicon,hisi-gmac-v1";
>
> Yes, this is fine.
As the patch series have been applied to net-next branch,
in which way should I commit this compatible fix?
Should I send a new patch fixing this compatible string error with "Fixes: xxx"?
Looking forward to your reply!
Regards,
Dongpo
.
Re: [PATCH v2 1/4] net: hix5hd2_gmac: add generic compatible string
On 2016/12/12 22:21, Rob Herring wrote:
> On Mon, Dec 12, 2016 at 5:16 AM, Dongpo Li wrote:
>> Hi Rob,
>>
>> On 2016/12/10 6:35, Rob Herring wrote:
>>> On Mon, Dec 05, 2016 at 09:27:58PM +0800, Dongpo Li wrote:
>>>> The "hix5hd2" is SoC name, add the generic ethernet driver name.
>>>> The "hisi-gemac-v1" is the basic version and "hisi-gemac-v2" adds
>>>> the SG/TXCSUM/TSO/UFO features.
>>>>
>>>> Signed-off-by: Dongpo Li
>>>> ---
>>>> .../devicetree/bindings/net/hisilicon-hix5hd2-gmac.txt| 9 +++--
>>>> drivers/net/ethernet/hisilicon/hix5hd2_gmac.c | 15
>>>> +++
>>>> 2 files changed, 18 insertions(+), 6 deletions(-)
>>>>
>>>> diff --git
>>>> a/Documentation/devicetree/bindings/net/hisilicon-hix5hd2-gmac.txt
>>>> b/Documentation/devicetree/bindings/net/hisilicon-hix5hd2-gmac.txt
>>>> index 75d398b..75920f0 100644
>>>> --- a/Documentation/devicetree/bindings/net/hisilicon-hix5hd2-gmac.txt
>>>> +++ b/Documentation/devicetree/bindings/net/hisilicon-hix5hd2-gmac.txt
>>>> @@ -1,7 +1,12 @@
>>>> Hisilicon hix5hd2 gmac controller
>>>>
>>>> Required properties:
>>>> -- compatible: should be "hisilicon,hix5hd2-gmac".
>>>> +- compatible: should contain one of the following SoC strings:
>>>> +* "hisilicon,hix5hd2-gemac"
>>>> +* "hisilicon,hi3798cv200-gemac"
>>>> +and one of the following version string:
>>>> +* "hisilicon,hisi-gemac-v1"
>>>> +* "hisilicon,hisi-gemac-v2"
>>>
>>> What combinations are valid? I assume both chips don't have both v1 and
>>> v2. 2 SoCs and 2 versions so far, I don't think there is much point to
>>> have the v1 and v2 compatible strings.
>>>
>> The v1 and v2 are generic MAC compatible strings, many HiSilicon SoCs may
>> use the same MAC version. For example,
>> hix5hd2, hi3716cv200 SoCs use the v1 MAC version,
>> hi3798cv200, hi3516a SoCs use the v2 MAC version,
>> and there may be more SoCs added in future.
>> So I think the generic compatible strings are okay here.
>> Should I add the hi3716cv200, hi3516a SoCs compatible here?
>
> Yes.
>
>> Do you have any good advice?
>>
>>>> - reg: specifies base physical address(s) and size of the device
>>>> registers.
>>>>The first region is the MAC register base and size.
>>>>The second region is external interface control register.
>>>> @@ -20,7 +25,7 @@ Required properties:
>>>>
>>>> Example:
>>>> gmac0: ethernet@f984 {
>>>> -compatible = "hisilicon,hix5hd2-gmac";
>>>> +compatible = "hisilicon,hix5hd2-gemac",
>>>> "hisilicon,hisi-gemac-v1";
>>>
>>> You can't just change compatible strings.
>>>
>> Okay, maybe I should name all the compatible string with the suffix "-gmac"
>> instead of
>> "-gemac". This can keep the compatible strings with the same suffix. Is this
>> okay?
>> Can I just add the generic compatible string without changing the SoCs
>> compatible string?
>> Like following:
>> gmac0: ethernet@f984 {
>> - compatible = "hisilicon,hix5hd2-gmac";
>> + compatible = "hisilicon,hix5hd2-gmac",
>> "hisilicon,hisi-gmac-v1";
>
> Yes, this is fine.
>
Many thanks for your advice.
As the patch series have been applied to net-next branch,
in which way should I commit this compatible fix?
Should I send a new patch with "Fixes: "?
Regards,
Dongpo
.
[PATCH 2/2] net: ethernet: hip04: Call SET_NETDEV_DEV()
The hip04 driver calls into PHYLIB which now checks for
net_device->dev.parent, so make sure we do set it before calling into
any MDIO/PHYLIB related function.
Fixes: ec988ad78ed6 ("phy: Don't increment MDIO bus refcount unless it's a
different owner")
Signed-off-by: Dongpo Li
---
drivers/net/ethernet/hisilicon/hip04_eth.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/hisilicon/hip04_eth.c
b/drivers/net/ethernet/hisilicon/hip04_eth.c
index 854befd..97b1847 100644
--- a/drivers/net/ethernet/hisilicon/hip04_eth.c
+++ b/drivers/net/ethernet/hisilicon/hip04_eth.c
@@ -828,6 +828,7 @@ static int hip04_mac_probe(struct platform_device *pdev)
priv = netdev_priv(ndev);
priv->ndev = ndev;
platform_set_drvdata(pdev, ndev);
+ SET_NETDEV_DEV(ndev, &pdev->dev);
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
priv->base = devm_ioremap_resource(d, res);
@@ -903,7 +904,6 @@ static int hip04_mac_probe(struct platform_device *pdev)
ndev->priv_flags |= IFF_UNICAST_FLT;
ndev->irq = irq;
netif_napi_add(ndev, &priv->napi, hip04_rx_poll, NAPI_POLL_WEIGHT);
- SET_NETDEV_DEV(ndev, &pdev->dev);
hip04_reset_ppe(priv);
if (priv->phy_mode == PHY_INTERFACE_MODE_MII)
--
2.8.2
[PATCH 0/2] net: ethernet: hisilicon: set dev->dev.parent before PHY connect
This patch series builds atop:
ec988ad78ed6d184a7f4ca6b8e962b0e8f1de461 ("phy: Don't increment MDIO bus
refcount unless it's a different owner")
I have checked all the hisilicon ethernet driver and found only two drivers
need to be fixed to make sure set dev->dev.parent before PHY connect.
Dongpo Li (2):
net: ethernet: hisi_femac: Call SET_NETDEV_DEV()
net: ethernet: hip04: Call SET_NETDEV_DEV()
drivers/net/ethernet/hisilicon/hip04_eth.c | 2 +-
drivers/net/ethernet/hisilicon/hisi_femac.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
--
2.8.2
[PATCH 1/2] net: ethernet: hisi_femac: Call SET_NETDEV_DEV()
The hisi_femac driver calls into PHYLIB which now checks for
net_device->dev.parent, so make sure we do set it before calling into
any MDIO/PHYLIB related function.
Fixes: ec988ad78ed6 ("phy: Don't increment MDIO bus refcount unless it's a
different owner")
Signed-off-by: Dongpo Li
---
drivers/net/ethernet/hisilicon/hisi_femac.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/hisilicon/hisi_femac.c
b/drivers/net/ethernet/hisilicon/hisi_femac.c
index 4986306..979852d 100644
--- a/drivers/net/ethernet/hisilicon/hisi_femac.c
+++ b/drivers/net/ethernet/hisilicon/hisi_femac.c
@@ -805,6 +805,7 @@ static int hisi_femac_drv_probe(struct platform_device
*pdev)
return -ENOMEM;
platform_set_drvdata(pdev, ndev);
+ SET_NETDEV_DEV(ndev, &pdev->dev);
priv = netdev_priv(ndev);
priv->dev = dev;
@@ -882,7 +883,6 @@ static int hisi_femac_drv_probe(struct platform_device
*pdev)
ndev->netdev_ops = &hisi_femac_netdev_ops;
ndev->ethtool_ops = &hisi_femac_ethtools_ops;
netif_napi_add(ndev, &priv->napi, hisi_femac_poll, FEMAC_POLL_WEIGHT);
- SET_NETDEV_DEV(ndev, &pdev->dev);
hisi_femac_port_init(priv);
--
2.8.2
Re: [PATCH v2 1/4] net: hix5hd2_gmac: add generic compatible string
Hi Rob,
On 2016/12/10 6:35, Rob Herring wrote:
> On Mon, Dec 05, 2016 at 09:27:58PM +0800, Dongpo Li wrote:
>> The "hix5hd2" is SoC name, add the generic ethernet driver name.
>> The "hisi-gemac-v1" is the basic version and "hisi-gemac-v2" adds
>> the SG/TXCSUM/TSO/UFO features.
>>
>> Signed-off-by: Dongpo Li
>> ---
>> .../devicetree/bindings/net/hisilicon-hix5hd2-gmac.txt| 9 +++--
>> drivers/net/ethernet/hisilicon/hix5hd2_gmac.c | 15
>> +++
>> 2 files changed, 18 insertions(+), 6 deletions(-)
>>
>> diff --git
>> a/Documentation/devicetree/bindings/net/hisilicon-hix5hd2-gmac.txt
>> b/Documentation/devicetree/bindings/net/hisilicon-hix5hd2-gmac.txt
>> index 75d398b..75920f0 100644
>> --- a/Documentation/devicetree/bindings/net/hisilicon-hix5hd2-gmac.txt
>> +++ b/Documentation/devicetree/bindings/net/hisilicon-hix5hd2-gmac.txt
>> @@ -1,7 +1,12 @@
>> Hisilicon hix5hd2 gmac controller
>>
>> Required properties:
>> -- compatible: should be "hisilicon,hix5hd2-gmac".
>> +- compatible: should contain one of the following SoC strings:
>> +* "hisilicon,hix5hd2-gemac"
>> +* "hisilicon,hi3798cv200-gemac"
>> +and one of the following version string:
>> +* "hisilicon,hisi-gemac-v1"
>> +* "hisilicon,hisi-gemac-v2"
>
> What combinations are valid? I assume both chips don't have both v1 and
> v2. 2 SoCs and 2 versions so far, I don't think there is much point to
> have the v1 and v2 compatible strings.
>
The v1 and v2 are generic MAC compatible strings, many HiSilicon SoCs may
use the same MAC version. For example,
hix5hd2, hi3716cv200 SoCs use the v1 MAC version,
hi3798cv200, hi3516a SoCs use the v2 MAC version,
and there may be more SoCs added in future.
So I think the generic compatible strings are okay here.
Should I add the hi3716cv200, hi3516a SoCs compatible here?
Do you have any good advice?
>> - reg: specifies base physical address(s) and size of the device registers.
>>The first region is the MAC register base and size.
>>The second region is external interface control register.
>> @@ -20,7 +25,7 @@ Required properties:
>>
>> Example:
>> gmac0: ethernet@f984 {
>> -compatible = "hisilicon,hix5hd2-gmac";
>> +compatible = "hisilicon,hix5hd2-gemac",
>> "hisilicon,hisi-gemac-v1";
>
> You can't just change compatible strings.
>
Okay, maybe I should name all the compatible string with the suffix "-gmac"
instead of
"-gemac". This can keep the compatible strings with the same suffix. Is this
okay?
Can I just add the generic compatible string without changing the SoCs
compatible string?
Like following:
gmac0: ethernet@f984 {
- compatible = "hisilicon,hix5hd2-gmac";
+ compatible = "hisilicon,hix5hd2-gmac", "hisilicon,hisi-gmac-v1";
>> reg = <0xf984 0x1000>,<0xf984300c 0x4>;
>> interrupts = <0 71 4>;
>> #address-cells = <1>;
>
> .
>
Regards,
Dongpo
.
[PATCH v2 4/4] ARM: dts: hix5hd2: add gmac generic compatible and clock names
Add gmac generic compatible and clock names.
Signed-off-by: Dongpo Li
---
arch/arm/boot/dts/hisi-x5hd2.dtsi | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi
b/arch/arm/boot/dts/hisi-x5hd2.dtsi
index fdcc23d..0da76c5 100644
--- a/arch/arm/boot/dts/hisi-x5hd2.dtsi
+++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi
@@ -436,18 +436,20 @@
};
gmac0: ethernet@184 {
- compatible = "hisilicon,hix5hd2-gmac";
+ compatible = "hisilicon,hix5hd2-gemac",
"hisilicon,hisi-gemac-v1";
reg = <0x184 0x1000>,<0x184300c 0x4>;
interrupts = <0 71 4>;
clocks = <&clock HIX5HD2_MAC0_CLK>;
+ clock-names = "mac_core";
status = "disabled";
};
gmac1: ethernet@1841000 {
- compatible = "hisilicon,hix5hd2-gmac";
+ compatible = "hisilicon,hix5hd2-gemac",
"hisilicon,hisi-gemac-v1";
reg = <0x1841000 0x1000>,<0x1843010 0x4>;
interrupts = <0 72 4>;
clocks = <&clock HIX5HD2_MAC1_CLK>;
+ clock-names = "mac_core";
status = "disabled";
};
--
2.8.2
[PATCH v2 3/4] net: hix5hd2_gmac: add reset control and clock signals
Add three reset control signals, "mac_core_rst", "mac_ifc_rst" and
"phy_rst".
The following diagram explained how the reset signals work.
SoC
|-
| --|
| | cpu | |
| --|
| | |
| AMBA bus |
| GMAC | |
|-- |
| - mac_core_rst | -- | |
| |clock and |-->| mac core | | |
| |reset | | -- | |
| |generator | | | | |
| - || | |
| |-->| mac interface | | |
| | mac_ifc_rst | | |
| | | | | |
| | | -- | |
| |phy_rst | | RGMII interface | | |
| | | -- | |
| | -- |
|--|--|
| |
| --
|- |PHY chip |
--
The "mac_core_rst" represents "mac core reset signal", it resets
the mac core including packet processing unit, descriptor processing unit,
tx engine, rx engine, control unit.
The "mac_ifc_rst" represents "mac interface reset signal", it resets
the mac interface. The mac interface unit connects mac core and
data interface like MII/RMII/RGMII. After we set a new value of
interface mode, we must reset mac interface to reload the new mode value.
The "mac_core_rst" and "mac_ifc_rst" are both optional to be
backward compatible with the hix5hd2 SoC.
The "phy_rst" represents "phy reset signal", it does a hardware reset
on the PHY chip. This reset signal is optional if the PHY can work well
without the hardware reset.
Add one more clock signal, the existing is MAC core clock,
and the new one is MAC interface clock.
The MAC interface clock is optional to be backward compatible with
the hix5hd2 SoC.
Signed-off-by: Dongpo Li
---
.../bindings/net/hisilicon-hix5hd2-gmac.txt| 20 ++-
drivers/net/ethernet/hisilicon/hix5hd2_gmac.c | 139 +++--
2 files changed, 144 insertions(+), 15 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/hisilicon-hix5hd2-gmac.txt
b/Documentation/devicetree/bindings/net/hisilicon-hix5hd2-gmac.txt
index 75920f0..063c02d 100644
--- a/Documentation/devicetree/bindings/net/hisilicon-hix5hd2-gmac.txt
+++ b/Documentation/devicetree/bindings/net/hisilicon-hix5hd2-gmac.txt
@@ -17,6 +17,16 @@ Required properties:
- phy-handle: see ethernet.txt [1].
- mac-address: see ethernet.txt [1].
- clocks: clock phandle and specifier pair.
+- clock-names: contain the clock name "mac_core"(required) and
"mac_ifc"(optional).
+- resets: should contain the phandle to the MAC core reset signal(optional),
+ the MAC interface reset signal(optional)
+ and the PHY reset signal(optional).
+- reset-names: contain the reset signal name "mac_core"(optional),
+ "mac_ifc"(optional) and "phy"(optional).
+- hisilicon,phy-reset-delays-us: triplet of delays if PHY reset signal given.
+ The 1st cell is reset pre-delay in micro seconds.
+ The 2nd cell is reset pulse in micro seconds.
+ The 3rd cell is reset post-delay in micro seconds.
- PHY subnode: inherits from phy binding [2]
@@ -25,15 +35,19 @@ Required properties:
Example:
gmac0: ethernet@f984 {
- compatible = "hisilicon,hix5hd2-gemac",
"hisilicon,hisi-gemac-v1";
+ compatible = "hisilicon,hi3798cv200-gemac",
"hisilicon,hisi-gemac-v2";
reg = <0xf984 0x1000>,<0xf984300c 0x4>;
interrupts = <0 71 4>;
#address-cells = <1>;
#size-cells = <0>;
- phy-mode = "mii";
+ phy-mode = "rgmii";
phy-handle = <&phy2>;
mac-address = [00 00 00 00 00 00];
- clocks = <&clock HIX5HD2_MAC0_CLK>;
+ clocks = <&crg HISTB_ETH0_MAC_CLK>, <&crg HISTB_ETH0_MACIF_CLK>;
+ clock-names = "mac_core", "mac_ifc";
+ resets = <&crg 0xcc 8>, <&crg 0xcc 10>, <&crg 0xcc 12&g
[PATCH v2 1/4] net: hix5hd2_gmac: add generic compatible string
The "hix5hd2" is SoC name, add the generic ethernet driver name.
The "hisi-gemac-v1" is the basic version and "hisi-gemac-v2" adds
the SG/TXCSUM/TSO/UFO features.
Signed-off-by: Dongpo Li
---
.../devicetree/bindings/net/hisilicon-hix5hd2-gmac.txt| 9 +++--
drivers/net/ethernet/hisilicon/hix5hd2_gmac.c | 15 +++
2 files changed, 18 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/hisilicon-hix5hd2-gmac.txt
b/Documentation/devicetree/bindings/net/hisilicon-hix5hd2-gmac.txt
index 75d398b..75920f0 100644
--- a/Documentation/devicetree/bindings/net/hisilicon-hix5hd2-gmac.txt
+++ b/Documentation/devicetree/bindings/net/hisilicon-hix5hd2-gmac.txt
@@ -1,7 +1,12 @@
Hisilicon hix5hd2 gmac controller
Required properties:
-- compatible: should be "hisilicon,hix5hd2-gmac".
+- compatible: should contain one of the following SoC strings:
+ * "hisilicon,hix5hd2-gemac"
+ * "hisilicon,hi3798cv200-gemac"
+ and one of the following version string:
+ * "hisilicon,hisi-gemac-v1"
+ * "hisilicon,hisi-gemac-v2"
- reg: specifies base physical address(s) and size of the device registers.
The first region is the MAC register base and size.
The second region is external interface control register.
@@ -20,7 +25,7 @@ Required properties:
Example:
gmac0: ethernet@f984 {
- compatible = "hisilicon,hix5hd2-gmac";
+ compatible = "hisilicon,hix5hd2-gemac",
"hisilicon,hisi-gemac-v1";
reg = <0xf984 0x1000>,<0xf984300c 0x4>;
interrupts = <0 71 4>;
#address-cells = <1>;
diff --git a/drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
b/drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
index e69a6be..27cb2e6 100644
--- a/drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
+++ b/drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
@@ -189,6 +189,10 @@
#define dma_cnt(n) ((n) >> 5)
#define dma_byte(n)((n) << 5)
+#define HW_CAP_TSO BIT(0)
+#define GEMAC_V1 0
+#define GEMAC_V2 (GEMAC_V1 | HW_CAP_TSO)
+
struct hix5hd2_desc {
__le32 buff_addr;
__le32 cmd;
@@ -1021,7 +1025,10 @@ static int hix5hd2_dev_remove(struct platform_device
*pdev)
}
static const struct of_device_id hix5hd2_of_match[] = {
- {.compatible = "hisilicon,hix5hd2-gmac",},
+ { .compatible = "hisilicon,hisi-gemac-v1", .data = (void *)GEMAC_V1 },
+ { .compatible = "hisilicon,hisi-gemac-v2", .data = (void *)GEMAC_V2 },
+ { .compatible = "hisilicon,hix5hd2-gemac", .data = (void *)GEMAC_V1 },
+ { .compatible = "hisilicon,hi3798cv200-gemac", .data = (void *)GEMAC_V2
},
{},
};
@@ -1029,7 +1036,7 @@ MODULE_DEVICE_TABLE(of, hix5hd2_of_match);
static struct platform_driver hix5hd2_dev_driver = {
.driver = {
- .name = "hix5hd2-gmac",
+ .name = "hisi-gemac",
.of_match_table = hix5hd2_of_match,
},
.probe = hix5hd2_dev_probe,
@@ -1038,6 +1045,6 @@ static struct platform_driver hix5hd2_dev_driver = {
module_platform_driver(hix5hd2_dev_driver);
-MODULE_DESCRIPTION("HISILICON HIX5HD2 Ethernet driver");
+MODULE_DESCRIPTION("HISILICON Gigabit Ethernet MAC driver");
MODULE_LICENSE("GPL v2");
-MODULE_ALIAS("platform:hix5hd2-gmac");
+MODULE_ALIAS("platform:hisi-gemac");
--
2.8.2
[PATCH v2 0/4] net: hix5hd2_gmac: add tx sg feature and reset/clock control signals
The "hix5hd2" is SoC name, add the generic ethernet driver compatible string. The "hisi-gemac-v1" is the basic version and "hisi-gemac-v2" adds the SG/TXCSUM/TSO/UFO features. This patch set only adds the SG(scatter-gather) driver for transmitting, the drivers of other features will be submitted later. Add the MAC reset control signals and clock signals. We make these signals optional to be backward compatible with the hix5hd2 SoC. Changes in v2: - Make the compatible string changes be a separate patch and the most specific string come first than the generic string as advised by Rob. - Make the MAC reset control signals and clock signals optional to be backward compatible with the hix5hd2 SoC. - Change the compatible string and give the clock a specific name in hix5hd2 dts file. Dongpo Li (4): net: hix5hd2_gmac: add generic compatible string net: hix5hd2_gmac: add tx scatter-gather feature net: hix5hd2_gmac: add reset control and clock signals ARM: dts: hix5hd2: add gmac generic compatible and clock names .../bindings/net/hisilicon-hix5hd2-gmac.txt| 27 +- arch/arm/boot/dts/hisi-x5hd2.dtsi | 6 +- drivers/net/ethernet/hisilicon/hix5hd2_gmac.c | 352 +++-- 3 files changed, 352 insertions(+), 33 deletions(-) -- 2.8.2
[PATCH v2 2/4] net: hix5hd2_gmac: add tx scatter-gather feature
"hisi-gemac-v2" adds the SG/TXCSUM/TSO/UFO features.
This patch only adds the SG(scatter-gather) driver for transmitting,
the drivers of other features will be submitted later.
Signed-off-by: Dongpo Li
---
drivers/net/ethernet/hisilicon/hix5hd2_gmac.c | 198 --
1 file changed, 187 insertions(+), 11 deletions(-)
diff --git a/drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
b/drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
index 27cb2e6..18af55b 100644
--- a/drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
+++ b/drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -183,6 +184,8 @@
#define DESC_DATA_LEN_OFF 16
#define DESC_BUFF_LEN_OFF 0
#define DESC_DATA_MASK 0x7ff
+#define DESC_SGBIT(30)
+#define DESC_FRAGS_NUM_OFF 11
/* DMA descriptor ring helpers */
#define dma_ring_incr(n, s)(((n) + 1) & ((s) - 1))
@@ -192,6 +195,7 @@
#define HW_CAP_TSO BIT(0)
#define GEMAC_V1 0
#define GEMAC_V2 (GEMAC_V1 | HW_CAP_TSO)
+#define HAS_CAP_TSO(hw_cap)((hw_cap) & HW_CAP_TSO)
struct hix5hd2_desc {
__le32 buff_addr;
@@ -205,6 +209,27 @@ struct hix5hd2_desc_sw {
unsigned intsize;
};
+struct hix5hd2_sg_desc_ring {
+ struct sg_desc *desc;
+ dma_addr_t phys_addr;
+};
+
+struct frags_info {
+ __le32 addr;
+ __le32 size;
+};
+
+/* hardware supported max skb frags num */
+#define SG_MAX_SKB_FRAGS 17
+struct sg_desc {
+ __le32 total_len;
+ __le32 resvd0;
+ __le32 linear_addr;
+ __le32 linear_len;
+ /* reserve one more frags for memory alignment */
+ struct frags_info frags[SG_MAX_SKB_FRAGS + 1];
+};
+
#define QUEUE_NUMS 4
struct hix5hd2_priv {
struct hix5hd2_desc_sw pool[QUEUE_NUMS];
@@ -212,6 +237,7 @@ struct hix5hd2_priv {
#define rx_bq pool[1]
#define tx_bq pool[2]
#define tx_rq pool[3]
+ struct hix5hd2_sg_desc_ring tx_ring;
void __iomem *base;
void __iomem *ctrl_base;
@@ -225,6 +251,7 @@ struct hix5hd2_priv {
struct device_node *phy_node;
phy_interface_t phy_mode;
+ unsigned long hw_cap;
unsigned int speed;
unsigned int duplex;
@@ -515,6 +542,27 @@ static int hix5hd2_rx(struct net_device *dev, int limit)
return num;
}
+static void hix5hd2_clean_sg_desc(struct hix5hd2_priv *priv,
+ struct sk_buff *skb, u32 pos)
+{
+ struct sg_desc *desc;
+ dma_addr_t addr;
+ u32 len;
+ int i;
+
+ desc = priv->tx_ring.desc + pos;
+
+ addr = le32_to_cpu(desc->linear_addr);
+ len = le32_to_cpu(desc->linear_len);
+ dma_unmap_single(priv->dev, addr, len, DMA_TO_DEVICE);
+
+ for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
+ addr = le32_to_cpu(desc->frags[i].addr);
+ len = le32_to_cpu(desc->frags[i].size);
+ dma_unmap_page(priv->dev, addr, len, DMA_TO_DEVICE);
+ }
+}
+
static void hix5hd2_xmit_reclaim(struct net_device *dev)
{
struct sk_buff *skb;
@@ -542,8 +590,15 @@ static void hix5hd2_xmit_reclaim(struct net_device *dev)
pkts_compl++;
bytes_compl += skb->len;
desc = priv->tx_rq.desc + pos;
- addr = le32_to_cpu(desc->buff_addr);
- dma_unmap_single(priv->dev, addr, skb->len, DMA_TO_DEVICE);
+
+ if (skb_shinfo(skb)->nr_frags) {
+ hix5hd2_clean_sg_desc(priv, skb, pos);
+ } else {
+ addr = le32_to_cpu(desc->buff_addr);
+ dma_unmap_single(priv->dev, addr, skb->len,
+DMA_TO_DEVICE);
+ }
+
priv->tx_skb[pos] = NULL;
dev_consume_skb_any(skb);
pos = dma_ring_incr(pos, TX_DESC_NUM);
@@ -604,12 +659,66 @@ static irqreturn_t hix5hd2_interrupt(int irq, void
*dev_id)
return IRQ_HANDLED;
}
+static u32 hix5hd2_get_desc_cmd(struct sk_buff *skb, unsigned long hw_cap)
+{
+ u32 cmd = 0;
+
+ if (HAS_CAP_TSO(hw_cap)) {
+ if (skb_shinfo(skb)->nr_frags)
+ cmd |= DESC_SG;
+ cmd |= skb_shinfo(skb)->nr_frags << DESC_FRAGS_NUM_OFF;
+ } else {
+ cmd |= DESC_FL_FULL |
+ ((skb->len & DESC_DATA_MASK) << DESC_BUFF_LEN_OFF);
+ }
+
+ cmd |= (skb->len & DESC_DATA_MASK) << DESC_DATA_LEN_OFF;
+ cmd |= DESC_VLD_BUSY;
+
+ return cmd;
+}
+
+static int hix5hd2_fill_sg_desc(struct hix5hd2_priv *priv,
+ struc
Re: [PATCH 1/4] net: hix5hd2_gmac: add tx scatter-gather feature
On 2016/8/16 0:18, Rob Herring wrote: > On Mon, Aug 15, 2016 at 1:50 AM, Dongpo Li wrote: >> Hi Rob, >> Many thanks for your review. >> >> On 2016/8/13 2:43, Rob Herring wrote: >>> On Thu, Aug 11, 2016 at 05:01:52PM +0800, Dongpo Li wrote: >>>> From: Li Dongpo >>>> >>>> The "hix5hd2" is SoC name, add the generic ethernet driver name. >>>> The "hisi-gemac-v1" is the basic version and "hisi-gemac-v2" adds >>>> the SG/TXCSUM/TSO/UFO features. >>>> This patch only adds the SG(scatter-gather) driver for transmitting, >>>> the drivers of other features will be submitted later. >>> >>> The compatible string changes should probably be a separate patch. >>> >> ok, I will split this patch into two patches, one for compatible string >> changes, >> and one for driver feature implementation. >> >>>> Signed-off-by: Dongpo Li >>>> --- >>>> .../bindings/net/hisilicon-hix5hd2-gmac.txt| 9 +- >>>> drivers/net/ethernet/hisilicon/hix5hd2_gmac.c | 213 >>>> +++-- >>>> 2 files changed, 205 insertions(+), 17 deletions(-) >>>> >>>> diff --git >>>> a/Documentation/devicetree/bindings/net/hisilicon-hix5hd2-gmac.txt >>>> b/Documentation/devicetree/bindings/net/hisilicon-hix5hd2-gmac.txt >>>> index 75d398b..3c02fac 100644 >>>> --- a/Documentation/devicetree/bindings/net/hisilicon-hix5hd2-gmac.txt >>>> +++ b/Documentation/devicetree/bindings/net/hisilicon-hix5hd2-gmac.txt >>>> @@ -1,7 +1,12 @@ >>>> Hisilicon hix5hd2 gmac controller >>>> >>>> Required properties: >>>> -- compatible: should be "hisilicon,hix5hd2-gmac". >>>> +- compatible: should contain one of the following version strings: >>>> +* "hisilicon,hisi-gemac-v1" >>>> +* "hisilicon,hisi-gemac-v2" >>>> +and one of the following SoC string: >>>> +* "hisilicon,hix5hd2-gemac" >>>> +* "hisilicon,hi3798cv200-gemac" >>> >>> Make it clear what the order should be. >>> >> ok, I will put the SoC strings in alphabetical order. > > No, I mean the most specific string comes first. > ok, I will fix it in next patch version. Thank you. > Rob > > . > Regards, Dongpo .
Re: [PATCH 3/4] clk: hix5hd2: change ethernet clock type
Hi all, On 2016/8/11 20:09, kbuild test robot wrote: > Hi Dongpo, > > [auto build test ERROR on robh/for-next] > [also build test ERROR on v4.8-rc1 next-20160811] > [if your patch is applied to the wrong git tree, please drop us a note to > help improve the system] > > url: > https://github.com/0day-ci/linux/commits/Dongpo-Li/net-hix5hd2_gmac-add-tx-sg-feature-and-reset-clock-control-signals/20160811-170826 > base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git > for-next > config: arm-multi_v7_defconfig (attached as .config) > compiler: arm-linux-gnueabi-gcc (Debian 5.4.0-6) 5.4.0 20160609 > reproduce: > wget > https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross > -O ~/bin/make.cross > chmod +x ~/bin/make.cross > # save the attached .config to linux build tree > make.cross ARCH=arm > > All errors (new ones prefixed by >>): > >drivers/clk/hisilicon/clk-hix5hd2.c: In function 'hix5hd2_clk_init': >>> drivers/clk/hisilicon/clk-hix5hd2.c:260:25: error: passing argument 1 of >>> 'hisi_reset_init' from incompatible pointer type >>> [-Werror=incompatible-pointer-types] > rstc = hisi_reset_init(np); > ^ >In file included from drivers/clk/hisilicon/clk-hix5hd2.c:15:0: >drivers/clk/hisilicon/reset.h:25:31: note: expected 'struct > platform_device *' but argument is of type 'struct device_node *' > struct hisi_reset_controller *hisi_reset_init(struct platform_device > *pdev); > ^ Sorry for my mistake, the interface changes in newer patch. I will fix my problem in the next patch version. Regards, Dongpo .
Re: [PATCH 2/4] net: hix5hd2_gmac: add reset control and clock signals
Hi Rob,
On 2016/8/13 2:48, Rob Herring wrote:
> On Thu, Aug 11, 2016 at 05:01:53PM +0800, Dongpo Li wrote:
>> From: Li Dongpo
>>
>> Add three reset control signals, "mac_core_rst", "mac_ifc_rst" and
>> "phy_rst".
>> The following diagram explained how the reset signals work.
>>
>> SoC
>> |-
>> | --|
>> | | cpu | |
>> | --|
>> | | |
>> | AMBA bus |
>> | GMAC | |
>> |-- |
>> | - mac_core_rst | -- | |
>> | |clock and |-->| mac core | | |
>> | |reset | | -- | |
>> | |generator | | | | |
>> | - || | |
>> | |-->| mac interface | | |
>> | | mac_ifc_rst | | |
>> | | | | | |
>> | | | -- | |
>> | |phy_rst | | RGMII interface | | |
>> | | | -- | |
>> | | -- |
>> |--|--|
>>| |
>>| --
>>|- |PHY chip |
>> --
>>
>> The "mac_core_rst" represents "mac core reset signal", it resets
>> the mac core including packet processing unit, descriptor processing unit,
>> tx engine, rx engine, control unit.
>> The "mac_ifc_rst" represents "mac interface reset signal", it resets
>> the mac interface. The mac interface unit connects mac core and
>> data interface like MII/RMII/RGMII. After we set a new value of
>> interface mode, we must reset mac interface to reload the new mode value.
>> The "phy_rst" represents "phy reset signal", it does a hardware reset
>> on the PHY chip. This reset signal is optinal if the PHY can work well
>> without the hardware reset.
>>
>> Add one more clock signal, the existing is MAC core clock,
>> and the new one is MAC interface clock.
>>
>> Signed-off-by: Dongpo Li
>> ---
>> .../bindings/net/hisilicon-hix5hd2-gmac.txt| 16 ++-
>> drivers/net/ethernet/hisilicon/hix5hd2_gmac.c | 140
>> +++--
>> 2 files changed, 143 insertions(+), 13 deletions(-)
>
>
>>
>> @@ -807,16 +829,26 @@ static int hix5hd2_net_open(struct net_device *dev)
>> struct phy_device *phy;
>> int ret;
>>
>> -ret = clk_prepare_enable(priv->clk);
>> +ret = clk_prepare_enable(priv->mac_core_clk);
>> +if (ret < 0) {
>> +netdev_err(dev, "failed to enable mac core clk %d\n", ret);
>> +return ret;
>> +}
>> +
>> +ret = clk_prepare_enable(priv->mac_ifc_clk);
>> if (ret < 0) {
>> -netdev_err(dev, "failed to enable clk %d\n", ret);
>> +clk_disable_unprepare(priv->mac_core_clk);
>> +netdev_err(dev, "failed to enable mac ifc clk %d\n", ret);
>
> This change will break with existing DTs. The mac_ifc_clk should be
> optional.
>
The mac_ifc_clk has existed in the existing hix5hd2. It's not implemented in
the MAC driver
because the CLOCK driver implements a "complex" ethernet clock type.
So [PATCH 3/4] and [PATCH 4/4] are following this patch to change the CLOCK
driver and existing DTs
at the same time.
> Rob
>
>> return ret;
>> }
>
> .
>
Regards,
Dongpo
.
Re: [PATCH 1/4] net: hix5hd2_gmac: add tx scatter-gather feature
Hi Rob,
Many thanks for your review.
On 2016/8/13 2:43, Rob Herring wrote:
> On Thu, Aug 11, 2016 at 05:01:52PM +0800, Dongpo Li wrote:
>> From: Li Dongpo
>>
>> The "hix5hd2" is SoC name, add the generic ethernet driver name.
>> The "hisi-gemac-v1" is the basic version and "hisi-gemac-v2" adds
>> the SG/TXCSUM/TSO/UFO features.
>> This patch only adds the SG(scatter-gather) driver for transmitting,
>> the drivers of other features will be submitted later.
>
> The compatible string changes should probably be a separate patch.
>
ok, I will split this patch into two patches, one for compatible string changes,
and one for driver feature implementation.
>> Signed-off-by: Dongpo Li
>> ---
>> .../bindings/net/hisilicon-hix5hd2-gmac.txt| 9 +-
>> drivers/net/ethernet/hisilicon/hix5hd2_gmac.c | 213
>> +++--
>> 2 files changed, 205 insertions(+), 17 deletions(-)
>>
>> diff --git
>> a/Documentation/devicetree/bindings/net/hisilicon-hix5hd2-gmac.txt
>> b/Documentation/devicetree/bindings/net/hisilicon-hix5hd2-gmac.txt
>> index 75d398b..3c02fac 100644
>> --- a/Documentation/devicetree/bindings/net/hisilicon-hix5hd2-gmac.txt
>> +++ b/Documentation/devicetree/bindings/net/hisilicon-hix5hd2-gmac.txt
>> @@ -1,7 +1,12 @@
>> Hisilicon hix5hd2 gmac controller
>>
>> Required properties:
>> -- compatible: should be "hisilicon,hix5hd2-gmac".
>> +- compatible: should contain one of the following version strings:
>> +* "hisilicon,hisi-gemac-v1"
>> +* "hisilicon,hisi-gemac-v2"
>> +and one of the following SoC string:
>> +* "hisilicon,hix5hd2-gemac"
>> +* "hisilicon,hi3798cv200-gemac"
>
> Make it clear what the order should be.
>
ok, I will put the SoC strings in alphabetical order.
> 2 SOC versions so far and 2 generic versions. I'm not really convinced
> that the generic string is needed.
>
Actually, there are more SoC versions not listed here. We aim to support
hi3798cv200
this time, but may support more SoCs in future.
>> - reg: specifies base physical address(s) and size of the device registers.
>>The first region is the MAC register base and size.
>>The second region is external interface control register.
>> @@ -20,7 +25,7 @@ Required properties:
>>
>> Example:
>> gmac0: ethernet@f984 {
>> -compatible = "hisilicon,hix5hd2-gmac";
>> +compatible = "hisilicon,hix5hd2-gemac",
>> "hisilicon,hisi-gemac-v1";
>> reg = <0xf984 0x1000>,<0xf984300c 0x4>;
>> interrupts = <0 71 4>;
>> #address-cells = <1>;
>
> .
>
Regards,
Dongpo
.
[PATCH 1/4] net: hix5hd2_gmac: add tx scatter-gather feature
From: Li Dongpo
The "hix5hd2" is SoC name, add the generic ethernet driver name.
The "hisi-gemac-v1" is the basic version and "hisi-gemac-v2" adds
the SG/TXCSUM/TSO/UFO features.
This patch only adds the SG(scatter-gather) driver for transmitting,
the drivers of other features will be submitted later.
Signed-off-by: Dongpo Li
---
.../bindings/net/hisilicon-hix5hd2-gmac.txt| 9 +-
drivers/net/ethernet/hisilicon/hix5hd2_gmac.c | 213 +++--
2 files changed, 205 insertions(+), 17 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/hisilicon-hix5hd2-gmac.txt
b/Documentation/devicetree/bindings/net/hisilicon-hix5hd2-gmac.txt
index 75d398b..3c02fac 100644
--- a/Documentation/devicetree/bindings/net/hisilicon-hix5hd2-gmac.txt
+++ b/Documentation/devicetree/bindings/net/hisilicon-hix5hd2-gmac.txt
@@ -1,7 +1,12 @@
Hisilicon hix5hd2 gmac controller
Required properties:
-- compatible: should be "hisilicon,hix5hd2-gmac".
+- compatible: should contain one of the following version strings:
+ * "hisilicon,hisi-gemac-v1"
+ * "hisilicon,hisi-gemac-v2"
+ and one of the following SoC string:
+ * "hisilicon,hix5hd2-gemac"
+ * "hisilicon,hi3798cv200-gemac"
- reg: specifies base physical address(s) and size of the device registers.
The first region is the MAC register base and size.
The second region is external interface control register.
@@ -20,7 +25,7 @@ Required properties:
Example:
gmac0: ethernet@f984 {
- compatible = "hisilicon,hix5hd2-gmac";
+ compatible = "hisilicon,hix5hd2-gemac",
"hisilicon,hisi-gemac-v1";
reg = <0xf984 0x1000>,<0xf984300c 0x4>;
interrupts = <0 71 4>;
#address-cells = <1>;
diff --git a/drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
b/drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
index 275618b..679a5e5 100644
--- a/drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
+++ b/drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -183,12 +184,19 @@
#define DESC_DATA_LEN_OFF 16
#define DESC_BUFF_LEN_OFF 0
#define DESC_DATA_MASK 0x7ff
+#define DESC_SGBIT(30)
+#define DESC_FRAGS_NUM_OFF 11
/* DMA descriptor ring helpers */
#define dma_ring_incr(n, s)(((n) + 1) & ((s) - 1))
#define dma_cnt(n) ((n) >> 5)
#define dma_byte(n)((n) << 5)
+#define HW_CAP_TSO BIT(0)
+#define GEMAC_V1 0
+#define GEMAC_V2 (GEMAC_V1 | HW_CAP_TSO)
+#define HAS_CAP_TSO(hw_cap)((hw_cap) & HW_CAP_TSO)
+
struct hix5hd2_desc {
__le32 buff_addr;
__le32 cmd;
@@ -201,6 +209,27 @@ struct hix5hd2_desc_sw {
unsigned intsize;
};
+struct hix5hd2_sg_desc_ring {
+ struct sg_desc *desc;
+ dma_addr_t phys_addr;
+};
+
+struct frags_info {
+ __le32 addr;
+ __le32 size;
+};
+
+/* hardware supported max skb frags num */
+#define SG_MAX_SKB_FRAGS 17
+struct sg_desc {
+ __le32 total_len;
+ __le32 resvd0;
+ __le32 linear_addr;
+ __le32 linear_len;
+ /* reserve one more frags for memory alignment */
+ struct frags_info frags[SG_MAX_SKB_FRAGS + 1];
+};
+
#define QUEUE_NUMS 4
struct hix5hd2_priv {
struct hix5hd2_desc_sw pool[QUEUE_NUMS];
@@ -208,6 +237,7 @@ struct hix5hd2_priv {
#define rx_bq pool[1]
#define tx_bq pool[2]
#define tx_rq pool[3]
+ struct hix5hd2_sg_desc_ring tx_ring;
void __iomem *base;
void __iomem *ctrl_base;
@@ -221,6 +251,7 @@ struct hix5hd2_priv {
struct device_node *phy_node;
phy_interface_t phy_mode;
+ unsigned long hw_cap;
unsigned int speed;
unsigned int duplex;
@@ -511,6 +542,27 @@ next:
return num;
}
+static void hix5hd2_clean_sg_desc(struct hix5hd2_priv *priv,
+ struct sk_buff *skb, u32 pos)
+{
+ struct sg_desc *desc;
+ dma_addr_t addr;
+ u32 len;
+ int i;
+
+ desc = priv->tx_ring.desc + pos;
+
+ addr = le32_to_cpu(desc->linear_addr);
+ len = le32_to_cpu(desc->linear_len);
+ dma_unmap_single(priv->dev, addr, len, DMA_TO_DEVICE);
+
+ for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
+ addr = le32_to_cpu(desc->frags[i].addr);
+ len = le32_to_cpu(desc->frags[i].size);
+ dma_unmap_page(priv->dev, addr, len, DMA_TO_DEVICE);
+ }
+}
+
static void hix5hd2_xmit_reclaim(struct net_device *dev)
{
struct sk_buff *skb;
@@ -538
[PATCH 4/4] ARM: dts: hix5hd2: add gmac clock and reset property
Add clock and reset property for gmac node.
Signed-off-by: Dongpo Li
---
arch/arm/boot/dts/hisi-x5hd2-dkb.dts | 2 ++
arch/arm/boot/dts/hisi-x5hd2.dtsi| 15 +++
2 files changed, 13 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/hisi-x5hd2-dkb.dts
b/arch/arm/boot/dts/hisi-x5hd2-dkb.dts
index d13af84..9da9283 100644
--- a/arch/arm/boot/dts/hisi-x5hd2-dkb.dts
+++ b/arch/arm/boot/dts/hisi-x5hd2-dkb.dts
@@ -57,6 +57,7 @@
#size-cells = <0>;
phy-handle = <&phy2>;
phy-mode = "mii";
+ hisilicon,phy-reset-delays-us = <1000 1000 2>;
/* Placeholder, overwritten by bootloader */
mac-address = [00 00 00 00 00 00];
status = "okay";
@@ -71,6 +72,7 @@
#size-cells = <0>;
phy-handle = <&phy1>;
phy-mode = "rgmii";
+ hisilicon,phy-reset-delays-us = <1 1 3>;
/* Placeholder, overwritten by bootloader */
mac-address = [00 00 00 00 00 00];
status = "okay";
diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi
b/arch/arm/boot/dts/hisi-x5hd2.dtsi
index fdcc23d..c391ce6 100644
--- a/arch/arm/boot/dts/hisi-x5hd2.dtsi
+++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi
@@ -413,6 +413,7 @@
compatible = "hisilicon,hix5hd2-clock";
reg = <0 0x2000>;
#clock-cells = <1>;
+ #reset-cells = <2>;
};
};
@@ -436,18 +437,24 @@
};
gmac0: ethernet@184 {
- compatible = "hisilicon,hix5hd2-gmac";
+ compatible = "hisilicon,hix5hd2-gemac",
"hisilicon,hisi-gemac-v1";
reg = <0x184 0x1000>,<0x184300c 0x4>;
interrupts = <0 71 4>;
- clocks = <&clock HIX5HD2_MAC0_CLK>;
+ clocks = <&clock HIX5HD2_MAC0_CLK>, <&clock
HIX5HD2_MAC_IFC0_CLK>;
+ clock-names = "mac_core", "mac_ifc";
+ resets = <&clock 0xcc 8>, <&clock 0xcc 10>, <&clock
0x120 4>;
+ reset-names = "mac_core", "mac_ifc", "phy";
status = "disabled";
};
gmac1: ethernet@1841000 {
- compatible = "hisilicon,hix5hd2-gmac";
+ compatible = "hisilicon,hix5hd2-gemac",
"hisilicon,hisi-gemac-v1";
reg = <0x1841000 0x1000>,<0x1843010 0x4>;
interrupts = <0 72 4>;
- clocks = <&clock HIX5HD2_MAC1_CLK>;
+ clocks = <&clock HIX5HD2_MAC1_CLK>, <&clock
HIX5HD2_MAC_IFC1_CLK>;
+ clock-names = "mac_core", "mac_ifc";
+ resets = <&clock 0xcc 9>, <&clock 0xcc 11>, <&clock
0x168 2>;
+ reset-names = "mac_core", "mac_ifc", "phy";
status = "disabled";
};
--
2.8.2
[PATCH 2/4] net: hix5hd2_gmac: add reset control and clock signals
From: Li Dongpo
Add three reset control signals, "mac_core_rst", "mac_ifc_rst" and
"phy_rst".
The following diagram explained how the reset signals work.
SoC
|-
| --|
| | cpu | |
| --|
| | |
| AMBA bus |
| GMAC | |
|-- |
| - mac_core_rst | -- | |
| |clock and |-->| mac core | | |
| |reset | | -- | |
| |generator | | | | |
| - || | |
| |-->| mac interface | | |
| | mac_ifc_rst | | |
| | | | | |
| | | -- | |
| |phy_rst | | RGMII interface | | |
| | | -- | |
| | -- |
|--|--|
| |
| --
|- |PHY chip |
--
The "mac_core_rst" represents "mac core reset signal", it resets
the mac core including packet processing unit, descriptor processing unit,
tx engine, rx engine, control unit.
The "mac_ifc_rst" represents "mac interface reset signal", it resets
the mac interface. The mac interface unit connects mac core and
data interface like MII/RMII/RGMII. After we set a new value of
interface mode, we must reset mac interface to reload the new mode value.
The "phy_rst" represents "phy reset signal", it does a hardware reset
on the PHY chip. This reset signal is optinal if the PHY can work well
without the hardware reset.
Add one more clock signal, the existing is MAC core clock,
and the new one is MAC interface clock.
Signed-off-by: Dongpo Li
---
.../bindings/net/hisilicon-hix5hd2-gmac.txt| 16 ++-
drivers/net/ethernet/hisilicon/hix5hd2_gmac.c | 140 +++--
2 files changed, 143 insertions(+), 13 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/hisilicon-hix5hd2-gmac.txt
b/Documentation/devicetree/bindings/net/hisilicon-hix5hd2-gmac.txt
index 3c02fac..a0bf2ca 100644
--- a/Documentation/devicetree/bindings/net/hisilicon-hix5hd2-gmac.txt
+++ b/Documentation/devicetree/bindings/net/hisilicon-hix5hd2-gmac.txt
@@ -17,6 +17,16 @@ Required properties:
- phy-handle: see ethernet.txt [1].
- mac-address: see ethernet.txt [1].
- clocks: clock phandle and specifier pair.
+- clock-names: contain the clock name "mac_core" and "mac_ifc".
+- resets: should contain the phandle to the MAC core reset signal(required),
+ the MAC interface reset signal(required)
+ and the PHY reset signal(optional).
+- reset-names: contain the reset signal name "mac_core"(required),
+ "mac_ifc"(required) and "phy"(optional).
+- hisilicon,phy-reset-delays-us: triplet of delays if PHY reset signal given.
+ The 1st cell is reset pre-delay in micro seconds.
+ The 2nd cell is reset pulse in micro seconds.
+ The 3rd cell is reset post-delay in micro seconds.
- PHY subnode: inherits from phy binding [2]
@@ -33,7 +43,11 @@ Example:
phy-mode = "mii";
phy-handle = <&phy2>;
mac-address = [00 00 00 00 00 00];
- clocks = <&clock HIX5HD2_MAC0_CLK>;
+ clocks = <&clock HIX5HD2_MAC0_CLK>, <&clock
HIX5HD2_MAC_IFC0_CLK>;
+ clock-names = "mac_core", "mac_ifc";
+ resets = <&clock 0xcc 8>, <&clock 0xcc 10>, <&clock 0x120 4>;
+ reset-names = "mac_core", "mac_ifc", "phy";
+ hisilicon,phy-reset-delays-us = <1 1 3>;
phy2: ethernet-phy@2 {
reg = <2>;
diff --git a/drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
b/drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
index 679a5e5..11e70bb 100644
--- a/drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
+++ b/drivers/net/ethernet/hisilicon/hix5hd2_gmac.c
@@ -14,6 +14,7 @@
#include
#include
#include
+#include
#include
#include
@@ -197,6 +198,15 @@
#define GEMAC_V2 (GEMAC_V1 | HW_CAP_TSO)
#define HAS_CAP_TSO(hw_cap)((hw_cap) &
[PATCH 3/4] clk: hix5hd2: change ethernet clock type
Because the clock and reset signals share the same register,
we initialize reset controller when initializing clock controller.
So the ethernet driver will control the reset signal instead of
the clock driver.
All the ethernet clock is changed from complex clock to gate clock.
The original ethernet clock is really a "complex" clock because
it's obscure and hard to understand.
Signed-off-by: Dongpo Li
---
drivers/clk/hisilicon/clk-hix5hd2.c | 72 +++
include/dt-bindings/clock/hix5hd2-clock.h | 6 ++-
2 files changed, 20 insertions(+), 58 deletions(-)
diff --git a/drivers/clk/hisilicon/clk-hix5hd2.c
b/drivers/clk/hisilicon/clk-hix5hd2.c
index 14b05ef..f9689e3 100644
--- a/drivers/clk/hisilicon/clk-hix5hd2.c
+++ b/drivers/clk/hisilicon/clk-hix5hd2.c
@@ -12,6 +12,7 @@
#include
#include
#include "clk.h"
+#include "reset.h"
static struct hisi_fixed_rate_clock hix5hd2_fixed_rate_clks[] __initdata = {
{ HIX5HD2_FIXED_1200M, "1200m", NULL, 0, 12, },
@@ -93,8 +94,12 @@ static struct hisi_gate_clock hix5hd2_gate_clks[] __initdata
= {
/* gsf */
{ HIX5HD2_FWD_BUS_CLK, "clk_fwd_bus", NULL, 0, 0xcc, 0, 0, },
{ HIX5HD2_FWD_SYS_CLK, "clk_fwd_sys", "clk_fwd_bus", 0, 0xcc, 5, 0, },
- { HIX5HD2_MAC0_PHY_CLK, "clk_fephy", "clk_fwd_sys",
-CLK_SET_RATE_PARENT, 0x120, 0, 0, },
+ { HIX5HD2_MAC0_CLK, "clk_mac0", "clk_fwd_sys", 0, 0xcc, 1, 0, },
+ { HIX5HD2_MAC_IFC0_CLK, "clk_mac_ifc0", "clk_fwd_sys", 0, 0xcc, 3, 0, },
+ { HIX5HD2_MAC1_CLK, "clk_mac1", "clk_fwd_sys", 0, 0xcc, 2, 0, },
+ { HIX5HD2_MAC_IFC1_CLK, "clk_mac_ifc1", "clk_fwd_sys", 0, 0xcc, 4, 0, },
+ { HIX5HD2_MAC0_PHY_CLK, "clk_fephy", NULL,
+CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x120, 0, 0, },
/* wdg0 */
{ HIX5HD2_WDG0_CLK, "clk_wdg0", "24m",
CLK_SET_RATE_PARENT, 0x178, 0, 0, },
@@ -129,7 +134,6 @@ static struct hisi_gate_clock hix5hd2_gate_clks[]
__initdata = {
enum hix5hd2_clk_type {
TYPE_COMPLEX,
- TYPE_ETHER,
};
struct hix5hd2_complex_clock {
@@ -157,10 +161,6 @@ struct hix5hd2_clk_complex {
};
static struct hix5hd2_complex_clock hix5hd2_complex_clks[] __initdata = {
- {"clk_mac0", "clk_fephy", HIX5HD2_MAC0_CLK,
- 0xcc, 0xa, 0x500, 0x120, 0, 0x10, TYPE_ETHER},
- {"clk_mac1", "clk_fwd_sys", HIX5HD2_MAC1_CLK,
- 0xcc, 0x14, 0xa00, 0x168, 0x2, 0, TYPE_ETHER},
{"clk_sata", NULL, HIX5HD2_SATA_CLK,
0xa8, 0x1f, 0x300, 0xac, 0x1, 0x0, TYPE_COMPLEX},
{"clk_usb", NULL, HIX5HD2_USB_CLK,
@@ -169,50 +169,6 @@ static struct hix5hd2_complex_clock hix5hd2_complex_clks[]
__initdata = {
#define to_complex_clk(_hw) container_of(_hw, struct hix5hd2_clk_complex, hw)
-static int clk_ether_prepare(struct clk_hw *hw)
-{
- struct hix5hd2_clk_complex *clk = to_complex_clk(hw);
- u32 val;
-
- val = readl_relaxed(clk->ctrl_reg);
- val |= clk->ctrl_clk_mask | clk->ctrl_rst_mask;
- writel_relaxed(val, clk->ctrl_reg);
- val &= ~(clk->ctrl_rst_mask);
- writel_relaxed(val, clk->ctrl_reg);
-
- val = readl_relaxed(clk->phy_reg);
- val |= clk->phy_clk_mask;
- val &= ~(clk->phy_rst_mask);
- writel_relaxed(val, clk->phy_reg);
- mdelay(10);
-
- val &= ~(clk->phy_clk_mask);
- val |= clk->phy_rst_mask;
- writel_relaxed(val, clk->phy_reg);
- mdelay(10);
-
- val |= clk->phy_clk_mask;
- val &= ~(clk->phy_rst_mask);
- writel_relaxed(val, clk->phy_reg);
- mdelay(30);
- return 0;
-}
-
-static void clk_ether_unprepare(struct clk_hw *hw)
-{
- struct hix5hd2_clk_complex *clk = to_complex_clk(hw);
- u32 val;
-
- val = readl_relaxed(clk->ctrl_reg);
- val &= ~(clk->ctrl_clk_mask);
- writel_relaxed(val, clk->ctrl_reg);
-}
-
-static struct clk_ops clk_ether_ops = {
- .prepare = clk_ether_prepare,
- .unprepare = clk_ether_unprepare,
-};
-
static int clk_complex_enable(struct clk_hw *hw)
{
struct hix5hd2_clk_complex *clk = to_complex_clk(hw);
@@ -269,10 +225,7 @@ hix5hd2_clk_register_complex(struct hix5hd2_complex_clock
*clks, int nums,
return;
init.name = clks[i].name;
- if (clks[i].type == TYPE_ETHER)
- init.ops = &clk_ether_ops;
- else
- init.ops = &clk_complex_ops;
+ init.ops = &clk_complex_ops;
init.flags = CLK_IS_BASIC;
init.parent_n
[PATCH 0/4] net: hix5hd2_gmac: add tx sg feature and reset/clock control signals
The "hix5hd2" is SoC name, add the generic ethernet driver name. The "hisi-gemac-v1" is the basic version and "hisi-gemac-v2" adds the SG/TXCSUM/TSO/UFO features. This patch set only adds the SG(scatter-gather) driver for transmitting, the drivers of other features will be submitted later. Add the MAC reset control signals and clock signals. As a result, the hix5hd2 ethernet clock can be abstracted as gate clock instead of self defined complex clock. Dongpo Li (2): clk: hix5hd2: change ethernet clock type ARM: dts: hix5hd2: add gmac clock and reset property Li Dongpo (2): net: hix5hd2_gmac: add tx scatter-gather feature net: hix5hd2_gmac: add reset control and clock signals .../bindings/net/hisilicon-hix5hd2-gmac.txt| 25 +- arch/arm/boot/dts/hisi-x5hd2-dkb.dts | 2 + arch/arm/boot/dts/hisi-x5hd2.dtsi | 15 +- drivers/clk/hisilicon/clk-hix5hd2.c| 72 + drivers/net/ethernet/hisilicon/hix5hd2_gmac.c | 353 +++-- include/dt-bindings/clock/hix5hd2-clock.h | 6 +- 6 files changed, 381 insertions(+), 92 deletions(-) -- 2.8.2
Re: [PATCH v1 0/3] Add Hisilicon MDIO bus driver and FEMAC driver
Hi Arnd,
On 2016/7/15 16:41, Arnd Bergmann wrote:
> On Friday, July 15, 2016 4:26:32 PM CEST Dongpo Li wrote:
>> This patch set adds a Hisilicon MDIO bus driver and
>> a Fast Ethernet MAC(FEMAC) driver.
>> We also abstract a general interface "of_phy_get_and_connect"
>> for PHY connect. User will have no bother with getting
>> "phy-mode" and "phy-handle" any more.
>>
>> Changes in v1:
>> - Pass private data structure instead of struct mii_bus
>> in MDIO read and write operation.
>> - Return the error which devm_clk_get() gives when MDIO probe.
>> - Leave the clock unprepared and disabled on error when MDIO probe.
>> - Abstract a general interface "of_phy_get_and_connect" for PHY connect.
>> - Remove the "_reset" suffixes in "reset-names" property.
>> - Enable tx per-packet interrupt when tx fifo full.
>> - Remove pointless compatible and add SoC specific compatible.
>> - Declare only one clock in MAC dts documentation.
>> - Add standard unit suffixes for "phy-reset-delays".
>> - Use a smaller NAPI poll weight 16 for our Fast Ethernet MAC.
>> - Use phy_ethtool_{get|set}_link_ksettings for ethtool ops.
>> - Use phydev from struct net_device in MAC driver.
>>
>
> Looks all good to me now,
>
> Reviewed-by: Arnd Bergmann
>
> One comment on the submission format: we normally count the initial
> submission as "v1", so after [PATCH 0/3], the following version is
> [PATCH v2 0/3], not [PATCH v1 0/3].
>
> No need to re-send for this now, and if you end up having to make
> other changes, just continue with "v2" for this driver, just follow
> the normal scheme if you send another driver.
>
Okay, many thanks for your friendly reminder. :)
> Arnd
>
> .
>
Regards,
Dongpo
.
[PATCH v1 0/3] Add Hisilicon MDIO bus driver and FEMAC driver
This patch set adds a Hisilicon MDIO bus driver and
a Fast Ethernet MAC(FEMAC) driver.
We also abstract a general interface "of_phy_get_and_connect"
for PHY connect. User will have no bother with getting
"phy-mode" and "phy-handle" any more.
Changes in v1:
- Pass private data structure instead of struct mii_bus
in MDIO read and write operation.
- Return the error which devm_clk_get() gives when MDIO probe.
- Leave the clock unprepared and disabled on error when MDIO probe.
- Abstract a general interface "of_phy_get_and_connect" for PHY connect.
- Remove the "_reset" suffixes in "reset-names" property.
- Enable tx per-packet interrupt when tx fifo full.
- Remove pointless compatible and add SoC specific compatible.
- Declare only one clock in MAC dts documentation.
- Add standard unit suffixes for "phy-reset-delays".
- Use a smaller NAPI poll weight 16 for our Fast Ethernet MAC.
- Use phy_ethtool_{get|set}_link_ksettings for ethtool ops.
- Use phydev from struct net_device in MAC driver.
Dongpo Li (3):
net: Add MDIO bus driver for the Hisilicon FEMAC
of_mdio: Abstract a general interface for phy connect
net: hisilicon: Add Fast Ethernet MAC driver
.../bindings/net/hisilicon-femac-mdio.txt | 22 +
.../devicetree/bindings/net/hisilicon-femac.txt| 39 +
drivers/net/ethernet/hisilicon/Kconfig | 12 +
drivers/net/ethernet/hisilicon/Makefile|1 +
drivers/net/ethernet/hisilicon/hisi_femac.c| 1007
drivers/net/phy/Kconfig|7 +
drivers/net/phy/Makefile |1 +
drivers/net/phy/mdio-hisi-femac.c | 166
drivers/of/of_mdio.c | 36 +
include/linux/of_mdio.h| 10 +
10 files changed, 1301 insertions(+)
create mode 100644
Documentation/devicetree/bindings/net/hisilicon-femac-mdio.txt
create mode 100644 Documentation/devicetree/bindings/net/hisilicon-femac.txt
create mode 100644 drivers/net/ethernet/hisilicon/hisi_femac.c
create mode 100644 drivers/net/phy/mdio-hisi-femac.c
--
2.8.2
[PATCH v1 3/3] net: hisilicon: Add Fast Ethernet MAC driver
This patch adds the Hisilicon Fast Ethernet MAC(FEMAC) driver.
The FEMAC supports max speed 100Mbps and has been used in many
Hisilicon SoC.
Signed-off-by: Dongpo Li
Reviewed-by: Jiancheng Xue
---
.../devicetree/bindings/net/hisilicon-femac.txt| 39 +
drivers/net/ethernet/hisilicon/Kconfig | 12 +
drivers/net/ethernet/hisilicon/Makefile|1 +
drivers/net/ethernet/hisilicon/hisi_femac.c| 1007
4 files changed, 1059 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/hisilicon-femac.txt
create mode 100644 drivers/net/ethernet/hisilicon/hisi_femac.c
diff --git a/Documentation/devicetree/bindings/net/hisilicon-femac.txt
b/Documentation/devicetree/bindings/net/hisilicon-femac.txt
new file mode 100644
index 000..d11af5e
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/hisilicon-femac.txt
@@ -0,0 +1,39 @@
+Hisilicon Fast Ethernet MAC controller
+
+Required properties:
+- compatible: should contain one of the following version strings:
+ * "hisilicon,hisi-femac-v1"
+ * "hisilicon,hisi-femac-v2"
+ and the soc string "hisilicon,hi3516cv300-femac".
+- reg: specifies base physical address(s) and size of the device registers.
+ The first region is the MAC core register base and size.
+ The second region is the global MAC control register.
+- interrupts: should contain the MAC interrupt.
+- clocks: A phandle to the MAC main clock.
+- resets: should contain the phandle to the MAC reset signal(required) and
+ the PHY reset signal(optional).
+- reset-names: should contain the reset signal name "mac"(required)
+ and "phy"(optional).
+- mac-address: see ethernet.txt [1].
+- phy-mode: see ethernet.txt [1].
+- phy-handle: see ethernet.txt [1].
+- hisilicon,phy-reset-delays-us: triplet of delays if PHY reset signal given.
+ The 1st cell is reset pre-delay in micro seconds.
+ The 2nd cell is reset pulse in micro seconds.
+ The 3rd cell is reset post-delay in micro seconds.
+
+[1] Documentation/devicetree/bindings/net/ethernet.txt
+
+Example:
+ hisi_femac: ethernet@1009 {
+ compatible =
"hisilicon,hi3516cv300-femac","hisilicon,hisi-femac-v2";
+ reg = <0x1009 0x1000>,<0x10091300 0x200>;
+ interrupts = <12>;
+ clocks = <&crg HI3518EV200_ETH_CLK>;
+ resets = <&crg 0xec 0>,<&crg 0xec 3>;
+ reset-names = "mac","phy";
+ mac-address = [00 00 00 00 00 00];
+ phy-mode = "mii";
+ phy-handle = <&phy0>;
+ hisilicon,phy-reset-delays-us = <1 2 2>;
+ };
diff --git a/drivers/net/ethernet/hisilicon/Kconfig
b/drivers/net/ethernet/hisilicon/Kconfig
index 4ccc032..85c43b6 100644
--- a/drivers/net/ethernet/hisilicon/Kconfig
+++ b/drivers/net/ethernet/hisilicon/Kconfig
@@ -23,6 +23,18 @@ config HIX5HD2_GMAC
help
This selects the hix5hd2 mac family network device.
+config HISI_FEMAC
+ tristate "Hisilicon Fast Ethernet MAC device support"
+ depends on HAS_IOMEM
+ select PHYLIB
+ select RESET_CONTROLLER
+ help
+ This selects the Hisilicon Fast Ethernet MAC device(FEMAC).
+ The FEMAC receives and transmits data over Ethernet
+ ports at 10/100 Mbps in full-duplex or half-duplex mode.
+ The FEMAC exchanges data with the CPU, and supports
+ the energy efficient Ethernet (EEE).
+
config HIP04_ETH
tristate "HISILICON P04 Ethernet support"
depends on HAS_IOMEM# For MFD_SYSCON
diff --git a/drivers/net/ethernet/hisilicon/Makefile
b/drivers/net/ethernet/hisilicon/Makefile
index 390b71f..8661695 100644
--- a/drivers/net/ethernet/hisilicon/Makefile
+++ b/drivers/net/ethernet/hisilicon/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_HIX5HD2_GMAC) += hix5hd2_gmac.o
obj-$(CONFIG_HIP04_ETH) += hip04_eth.o
obj-$(CONFIG_HNS_MDIO) += hns_mdio.o
obj-$(CONFIG_HNS) += hns/
+obj-$(CONFIG_HISI_FEMAC) += hisi_femac.o
diff --git a/drivers/net/ethernet/hisilicon/hisi_femac.c
b/drivers/net/ethernet/hisilicon/hisi_femac.c
new file mode 100644
index 000..b5d7ad0
--- /dev/null
+++ b/drivers/net/ethernet/hisilicon/hisi_femac.c
@@ -0,0 +1,1007 @@
+/*
+ * Hisilicon Fast Ethernet MAC Driver
+ *
+ * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A
[PATCH v1 1/3] net: Add MDIO bus driver for the Hisilicon FEMAC
This patch adds a separate driver for the MDIO interface of the
Hisilicon Fast Ethernet MAC.
Signed-off-by: Dongpo Li
Reviewed-by: Jiancheng Xue
Acked-by: Rob Herring
---
.../bindings/net/hisilicon-femac-mdio.txt | 22 +++
drivers/net/phy/Kconfig| 7 +
drivers/net/phy/Makefile | 1 +
drivers/net/phy/mdio-hisi-femac.c | 166 +
4 files changed, 196 insertions(+)
create mode 100644
Documentation/devicetree/bindings/net/hisilicon-femac-mdio.txt
create mode 100644 drivers/net/phy/mdio-hisi-femac.c
diff --git a/Documentation/devicetree/bindings/net/hisilicon-femac-mdio.txt
b/Documentation/devicetree/bindings/net/hisilicon-femac-mdio.txt
new file mode 100644
index 000..6f46337
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/hisilicon-femac-mdio.txt
@@ -0,0 +1,22 @@
+Hisilicon Fast Ethernet MDIO Controller interface
+
+Required properties:
+- compatible: should be "hisilicon,hisi-femac-mdio".
+- reg: address and length of the register set for the device.
+- clocks: A phandle to the reference clock for this device.
+
+- PHY subnode: inherits from phy binding [1]
+[1] Documentation/devicetree/bindings/net/phy.txt
+
+Example:
+mdio: mdio@10091100 {
+ compatible = "hisilicon,hisi-femac-mdio";
+ reg = <0x10091100 0x10>;
+ clocks = <&crg HI3516CV300_MDIO_CLK>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy0: phy@1 {
+ reg = <1>;
+ };
+};
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 6dad9a9..3353bde 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -271,6 +271,13 @@ config MDIO_BCM_IPROC
This module provides a driver for the MDIO busses found in the
Broadcom iProc SoC's.
+config MDIO_HISI_FEMAC
+ tristate "Hisilicon FEMAC MDIO bus controller"
+ depends on HAS_IOMEM && OF_MDIO
+ help
+ This module provides a driver for the MDIO busses found in the
+ Hisilicon SoC that have an Fast Ethernet MAC.
+
endif # PHYLIB
config MICREL_KS8995MA
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index fcdbb92..039c4be 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -44,3 +44,4 @@ obj-$(CONFIG_MDIO_MOXART) += mdio-moxart.o
obj-$(CONFIG_MDIO_BCM_UNIMAC) += mdio-bcm-unimac.o
obj-$(CONFIG_MICROCHIP_PHY)+= microchip.o
obj-$(CONFIG_MDIO_BCM_IPROC) += mdio-bcm-iproc.o
+obj-$(CONFIG_MDIO_HISI_FEMAC) += mdio-hisi-femac.o
diff --git a/drivers/net/phy/mdio-hisi-femac.c
b/drivers/net/phy/mdio-hisi-femac.c
new file mode 100644
index 000..b03fedd
--- /dev/null
+++ b/drivers/net/phy/mdio-hisi-femac.c
@@ -0,0 +1,166 @@
+/*
+ * Hisilicon Fast Ethernet MDIO Bus Driver
+ *
+ * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define MDIO_RWCTRL0x00
+#define MDIO_RO_DATA 0x04
+#define MDIO_WRITE BIT(13)
+#define MDIO_RW_FINISH BIT(15)
+#define BIT_PHY_ADDR_OFFSET8
+#define BIT_WR_DATA_OFFSET 16
+
+struct hisi_femac_mdio_data {
+ struct clk *clk;
+ void __iomem *membase;
+};
+
+static int hisi_femac_mdio_wait_ready(struct hisi_femac_mdio_data *data)
+{
+ u32 val;
+
+ return readl_poll_timeout(data->membase + MDIO_RWCTRL,
+ val, val & MDIO_RW_FINISH, 20, 1);
+}
+
+static int hisi_femac_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
+{
+ struct hisi_femac_mdio_data *data = bus->priv;
+ int ret;
+
+ ret = hisi_femac_mdio_wait_ready(data);
+ if (ret)
+ return ret;
+
+ writel((mii_id << BIT_PHY_ADDR_OFFSET) | regnum,
+ data->membase + MDIO_RWCTRL);
+
+ ret = hisi_femac_mdio_wait_ready(data);
+ if (ret)
+ return ret;
+
+ return readl(data->membase + MDIO_RO_DATA) & 0x;
+}
+
+static int hisi_femac_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
+u16 value)
+{
+ struct hisi_femac_mdio_data *data = bus->priv
[PATCH v1 2/3] of_mdio: Abstract a general interface for phy connect
Abstract a general interface "of_phy_get_and_connect"
for PHY connect. User will have no bother with getting
"phy-mode" and "phy-handle" any more.
Suggested-by: Arnd Bergmann
Signed-off-by: Dongpo Li
Reviewed-by: Jiancheng Xue
---
drivers/of/of_mdio.c| 36
include/linux/of_mdio.h | 10 ++
2 files changed, 46 insertions(+)
diff --git a/drivers/of/of_mdio.c b/drivers/of/of_mdio.c
index e051e1b..1e93f0a 100644
--- a/drivers/of/of_mdio.c
+++ b/drivers/of/of_mdio.c
@@ -19,6 +19,7 @@
#include
#include
#include
+#include
#include
MODULE_AUTHOR("Grant Likely ");
@@ -332,6 +333,41 @@ struct phy_device *of_phy_connect(struct net_device *dev,
EXPORT_SYMBOL(of_phy_connect);
/**
+ * of_phy_get_and_connect
+ * - Get phy node and connect to the phy described in the device tree
+ * @dev: pointer to net_device claiming the phy
+ * @np: Pointer to device tree node for the net_device claiming the phy
+ * @hndlr: Link state callback for the network device
+ *
+ * If successful, returns a pointer to the phy_device with the embedded
+ * struct device refcount incremented by one, or NULL on failure. The
+ * refcount must be dropped by calling phy_disconnect() or phy_detach().
+ */
+struct phy_device *of_phy_get_and_connect(struct net_device *dev,
+ struct device_node *np,
+ void (*hndlr)(struct net_device *))
+{
+ phy_interface_t iface;
+ struct device_node *phy_np;
+ struct phy_device *phy;
+
+ iface = of_get_phy_mode(np);
+ if (iface < 0)
+ return NULL;
+
+ phy_np = of_parse_phandle(np, "phy-handle", 0);
+ if (!phy_np)
+ return NULL;
+
+ phy = of_phy_connect(dev, phy_np, hndlr, 0, iface);
+
+ of_node_put(phy_np);
+
+ return phy;
+}
+EXPORT_SYMBOL(of_phy_get_and_connect);
+
+/**
* of_phy_attach - Attach to a PHY without starting the state machine
* @dev: pointer to net_device claiming the phy
* @phy_np: Node pointer for the PHY
diff --git a/include/linux/of_mdio.h b/include/linux/of_mdio.h
index 8f2237e..6c4d7a6 100644
--- a/include/linux/of_mdio.h
+++ b/include/linux/of_mdio.h
@@ -19,6 +19,9 @@ extern struct phy_device *of_phy_connect(struct net_device
*dev,
struct device_node *phy_np,
void (*hndlr)(struct net_device *),
u32 flags, phy_interface_t iface);
+extern struct phy_device *
+of_phy_get_and_connect(struct net_device *dev, struct device_node *np,
+ void (*hndlr)(struct net_device *));
struct phy_device *of_phy_attach(struct net_device *dev,
struct device_node *phy_np, u32 flags,
phy_interface_t iface);
@@ -50,6 +53,13 @@ static inline struct phy_device *of_phy_connect(struct
net_device *dev,
return NULL;
}
+static inline struct phy_device *
+of_phy_get_and_connect(struct net_device *dev, struct device_node *np,
+ void (*hndlr)(struct net_device *))
+{
+ return NULL;
+}
+
static inline struct phy_device *of_phy_attach(struct net_device *dev,
struct device_node *phy_np,
u32 flags, phy_interface_t iface)
--
2.8.2
Re: [PATCH 3/3] net: hisilicon: Add Fast Ethernet MAC driver
On 2016/7/11 16:16, Arnd Bergmann wrote:
> On Monday, July 11, 2016 11:44:23 AM CEST Dongpo Li wrote:
>> Hi Arnd,
>>
>> On 2016/6/28 17:34, Arnd Bergmann wrote:
>>> On Tuesday, June 28, 2016 5:21:19 PM CEST Dongpo Li wrote:
>>>> On 2016/6/15 5:20, Arnd Bergmann wrote:
>>>>> On Tuesday, June 14, 2016 9:17:44 PM CEST Li Dongpo wrote:
>>>>>> On 2016/6/13 17:06, Arnd Bergmann wrote:
>>>>>>> On Monday, June 13, 2016 2:07:56 PM CEST Dongpo Li wrote:
>>>>>>> You tx function uses BQL to optimize the queue length, and that
>>>>>>> is great. You also check xmit reclaim for rx interrupts, so
>>>>>>> as long as you have both rx and tx traffic, this should work
>>>>>>> great.
>>>>>>>
>>>>>>> However, I notice that you only have a 'tx fifo empty'
>>>>>>> interrupt triggering the napi poll, so I guess on a tx-only
>>>>>>> workload you will always end up pushing packets into the
>>>>>>> queue until BQL throttles tx, and then get the interrupt
>>>>>>> after all packets have been sent, which will cause BQL to
>>>>>>> make the queue longer up to the maximum queue size, and that
>>>>>>> negates the effect of BQL.
>>>>>>>
>>>>>>> Is there any way you can get a tx interrupt earlier than
>>>>>>> this in order to get a more balanced queue, or is it ok
>>>>>>> to just rely on rx packets to come in occasionally, and
>>>>>>> just use the tx fifo empty interrupt as a fallback?
>>>>>>>
>>>>>> In tx direction, there are only two kinds of interrupts, 'tx fifo empty'
>>>>>> and 'tx one packet finish'. I didn't use 'tx one packet finish' because
>>>>>> it would lead to high hardware interrupts rate. This has been verified in
>>>>>> our chips. It's ok to just use tx fifo empty interrupt.
>>>>>
>>>>> I'm not convinced by the explanation, I don't think that has anything
>>>>> to do with the hardware design, but instead is about the correctness
>>>>> of the BQL logic with your driver.
>>>>>
>>>>> Maybe your xmit function can do something like
>>>>>
>>>>> if (dql_avail(netdev_get_tx_queue(dev, 0)->dql) < 0)
>>>>> enable per-packet interrupt
>>>>> else
>>>>> use only fifo-empty interrupt
>>>>>
>>>>> That way, you don't get a lot of interrupts when the system is
>>>>> in a state of packets being received and sent continuously,
>>>>> but if you get to the point where your tx queue fills up
>>>>> and no rx interrupts arrive, you don't have to wait for it
>>>>> to become completely empty before adding new packets, and
>>>>> BQL won't keep growing the queue.
>>>>>
>>>> Hi, Arnd
>>>> I tried enable per-packet interrupt when tx queue full in xmit function
>>>> and disable it in NAPI poll. But the number of interrupts are a little
>>>> bigger than only using fifo-empty interrupt.
>>>
>>> Right, I'd expect that to be the case, it basically means that the
>>> algorithm works as expected.
>>>
>>> Just to be sure you didn't have extra interrupts: you only enable the
>>> per-packet interrupts if interrupts are currently enabled, not in
>>> NAPI polling mode, right?
>>>
>> Sorry so long to reply to you. I use the per-packet interrupt like this:
>> In my xmit function,
>> if (hardware tx fifo is full) {
>> enable tx per-packet interrupt;
>> netif_stop_queue(dev);
>> return NETDEV_TX_BUSY;
>> }
>>
>> In interrupt handle function,
>> if (interrupt is tx per-packet or tx fifo-empty or rx) {
>> disable tx per-packet interrupt;
>> napi_schedule(&priv->napi);
>> }
>> We disable tx per-packet interrupt anyway because the NAPI poll will reclaim
>> the tx fifo.
>> When the NAPI poll completed, it will only enable the tx fifo-empty interrupt
>> and rx interrupt except the tx per-packet interrupt.
>>
>> Is this solution okay?
>
> Yes, this looks good to me.
>
Okay, many thanks for your review.
> Arnd
>
> .
>
Regards,
Dongpo
.
Re: [PATCH 3/3] net: hisilicon: Add Fast Ethernet MAC driver
Hi Arnd,
On 2016/6/28 17:34, Arnd Bergmann wrote:
> On Tuesday, June 28, 2016 5:21:19 PM CEST Dongpo Li wrote:
>> On 2016/6/15 5:20, Arnd Bergmann wrote:
>>> On Tuesday, June 14, 2016 9:17:44 PM CEST Li Dongpo wrote:
>>>> On 2016/6/13 17:06, Arnd Bergmann wrote:
>>>>> On Monday, June 13, 2016 2:07:56 PM CEST Dongpo Li wrote:
>>>>> You tx function uses BQL to optimize the queue length, and that
>>>>> is great. You also check xmit reclaim for rx interrupts, so
>>>>> as long as you have both rx and tx traffic, this should work
>>>>> great.
>>>>>
>>>>> However, I notice that you only have a 'tx fifo empty'
>>>>> interrupt triggering the napi poll, so I guess on a tx-only
>>>>> workload you will always end up pushing packets into the
>>>>> queue until BQL throttles tx, and then get the interrupt
>>>>> after all packets have been sent, which will cause BQL to
>>>>> make the queue longer up to the maximum queue size, and that
>>>>> negates the effect of BQL.
>>>>>
>>>>> Is there any way you can get a tx interrupt earlier than
>>>>> this in order to get a more balanced queue, or is it ok
>>>>> to just rely on rx packets to come in occasionally, and
>>>>> just use the tx fifo empty interrupt as a fallback?
>>>>>
>>>> In tx direction, there are only two kinds of interrupts, 'tx fifo empty'
>>>> and 'tx one packet finish'. I didn't use 'tx one packet finish' because
>>>> it would lead to high hardware interrupts rate. This has been verified in
>>>> our chips. It's ok to just use tx fifo empty interrupt.
>>>
>>> I'm not convinced by the explanation, I don't think that has anything
>>> to do with the hardware design, but instead is about the correctness
>>> of the BQL logic with your driver.
>>>
>>> Maybe your xmit function can do something like
>>>
>>> if (dql_avail(netdev_get_tx_queue(dev, 0)->dql) < 0)
>>> enable per-packet interrupt
>>> else
>>> use only fifo-empty interrupt
>>>
>>> That way, you don't get a lot of interrupts when the system is
>>> in a state of packets being received and sent continuously,
>>> but if you get to the point where your tx queue fills up
>>> and no rx interrupts arrive, you don't have to wait for it
>>> to become completely empty before adding new packets, and
>>> BQL won't keep growing the queue.
>>>
>> Hi, Arnd
>> I tried enable per-packet interrupt when tx queue full in xmit function
>> and disable it in NAPI poll. But the number of interrupts are a little
>> bigger than only using fifo-empty interrupt.
>
> Right, I'd expect that to be the case, it basically means that the
> algorithm works as expected.
>
> Just to be sure you didn't have extra interrupts: you only enable the
> per-packet interrupts if interrupts are currently enabled, not in
> NAPI polling mode, right?
>
Sorry so long to reply to you. I use the per-packet interrupt like this:
In my xmit function,
if (hardware tx fifo is full) {
enable tx per-packet interrupt;
netif_stop_queue(dev);
return NETDEV_TX_BUSY;
}
In interrupt handle function,
if (interrupt is tx per-packet or tx fifo-empty or rx) {
disable tx per-packet interrupt;
napi_schedule(&priv->napi);
}
We disable tx per-packet interrupt anyway because the NAPI poll will reclaim
the tx fifo.
When the NAPI poll completed, it will only enable the tx fifo-empty interrupt
and rx interrupt except the tx per-packet interrupt.
Is this solution okay?
>> The other hand, this is a fast ethernet MAC. Its maximum speed is 100Mbps.
>> This speed is very easily achived and the efficiency of the BQL is not
>> so important. What we focus on is the lower cpu utilization.
>> So I think it is okay to just use the tx fifo empty interrupt.
>
> BQL is not about efficiency, it's about keeping the latency down, which
> is at least as important for low-throughput devices as it is for faster
> ones. I don't think that disabling BQL here would be the right answer,
> you'd just end up with the maximum TX queue length all the time.
>
> Your queue length is 12 packets of 1500 bytes, meaning that you have 1.4ms
> of latency at 100mbit/s rate, or 14ms for 10mbit/s. This is much less
> than most, but it's probably still worth using BQL on it.
>
I spent some time reading some articles and the goal of BQL is more clear to me.
BQL is designed to get the minimum buffer size that will not make hardware
under starvation.
The goal is to reduce latency without the side effect of throughput.
Thanks for your explanation.
> Arnd
>
> .
>
Regards,
Dongpo
.
Re: [PATCH 3/3] net: hisilicon: Add Fast Ethernet MAC driver
On 2016/6/15 5:20, Arnd Bergmann wrote:
> On Tuesday, June 14, 2016 9:17:44 PM CEST Li Dongpo wrote:
>> On 2016/6/13 17:06, Arnd Bergmann wrote:
>>> On Monday, June 13, 2016 2:07:56 PM CEST Dongpo Li wrote:
>>> You tx function uses BQL to optimize the queue length, and that
>>> is great. You also check xmit reclaim for rx interrupts, so
>>> as long as you have both rx and tx traffic, this should work
>>> great.
>>>
>>> However, I notice that you only have a 'tx fifo empty'
>>> interrupt triggering the napi poll, so I guess on a tx-only
>>> workload you will always end up pushing packets into the
>>> queue until BQL throttles tx, and then get the interrupt
>>> after all packets have been sent, which will cause BQL to
>>> make the queue longer up to the maximum queue size, and that
>>> negates the effect of BQL.
>>>
>>> Is there any way you can get a tx interrupt earlier than
>>> this in order to get a more balanced queue, or is it ok
>>> to just rely on rx packets to come in occasionally, and
>>> just use the tx fifo empty interrupt as a fallback?
>>>
>> In tx direction, there are only two kinds of interrupts, 'tx fifo empty'
>> and 'tx one packet finish'. I didn't use 'tx one packet finish' because
>> it would lead to high hardware interrupts rate. This has been verified in
>> our chips. It's ok to just use tx fifo empty interrupt.
>
> I'm not convinced by the explanation, I don't think that has anything
> to do with the hardware design, but instead is about the correctness
> of the BQL logic with your driver.
>
> Maybe your xmit function can do something like
>
> if (dql_avail(netdev_get_tx_queue(dev, 0)->dql) < 0)
> enable per-packet interrupt
> else
> use only fifo-empty interrupt
>
> That way, you don't get a lot of interrupts when the system is
> in a state of packets being received and sent continuously,
> but if you get to the point where your tx queue fills up
> and no rx interrupts arrive, you don't have to wait for it
> to become completely empty before adding new packets, and
> BQL won't keep growing the queue.
>
Hi, Arnd
I tried enable per-packet interrupt when tx queue full in xmit function
and disable it in NAPI poll. But the number of interrupts are a little
bigger than only using fifo-empty interrupt.
The other hand, this is a fast ethernet MAC. Its maximum speed is 100Mbps.
This speed is very easily achived and the efficiency of the BQL is not
so important. What we focus on is the lower cpu utilization.
So I think it is okay to just use the tx fifo empty interrupt.
>>>> +priv->phy_mode = of_get_phy_mode(node);
>>>> +if (priv->phy_mode < 0) {
>>>> +dev_err(dev, "not find phy-mode\n");
>>>> +ret = -EINVAL;
>>>> +goto out_disable_clk;
>>>> +}
>>>> +
>>>> +priv->phy_node = of_parse_phandle(node, "phy-handle", 0);
>>>> +if (!priv->phy_node) {
>>>> +dev_err(dev, "not find phy-handle\n");
>>>> +ret = -EINVAL;
>>>> +goto out_disable_clk;
>>>> +}
>>>> +
>>>> +priv->phy = of_phy_connect(ndev, priv->phy_node,
>>>> + hisi_femac_adjust_link, 0, priv->phy_mode);
>>>> +if (!(priv->phy) || IS_ERR(priv->phy)) {
>>>> +dev_err(dev, "connect to PHY failed!\n");
>>>> +ret = -ENODEV;
>>>> +goto out_phy_node;
>>>> +}
>>>
>>> I wonder if we could generalize this set of three calls, I
>>> get the impression that we duplicate this across several
>>> drivers that shouldn't need to bother with the specific
>>> phy-handle and phy-mode properties.
>>>
>> Some drivers only call 'of_phy_connect' when ndo_open called,
>> some call when driver probed. But 'phy_mode' and 'phy_node' are
>> usually initialized when driver probed.
>> So I think it's not suitable to combine 'of_phy_connect' with
>> 'of_get_phy_mode' and 'of_parse_phandle'.
>> Do you have any more suggestions ?
>
> My idea was to add another interface that drivers could optionally
> call if they use the logic that you have here, but other drivers
> could keep using the plain of_phy_connect.
>
> Anyway, this was just an idea, it's not important.
>
> Arnd
>
> .
>
Regards,
Dongpo
.
Re: [PATCH 3/3] net: hisilicon: Add Fast Ethernet MAC driver
On 2016/6/15 6:31, Rob Herring wrote:
> On Mon, Jun 13, 2016 at 02:07:56PM +0800, Dongpo Li wrote:
>> This patch adds the Hisilicon Fast Ethernet MAC(FEMAC) driver.
>> The FEMAC supports max speed 100Mbps and has been used in many
>> Hisilicon SoC.
>>
>> Reviewed-by: Jiancheng Xue
>> Signed-off-by: Dongpo Li
>> ---
>> .../devicetree/bindings/net/hisilicon-femac.txt| 40 +
>> drivers/net/ethernet/hisilicon/Kconfig | 12 +
>> drivers/net/ethernet/hisilicon/Makefile|1 +
>> drivers/net/ethernet/hisilicon/hisi_femac.c| 1015
>>
>> 4 files changed, 1068 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/net/hisilicon-femac.txt
>> create mode 100644 drivers/net/ethernet/hisilicon/hisi_femac.c
>>
>> diff --git a/Documentation/devicetree/bindings/net/hisilicon-femac.txt
>> b/Documentation/devicetree/bindings/net/hisilicon-femac.txt
>> new file mode 100644
>> index 000..b953a56
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/net/hisilicon-femac.txt
>> @@ -0,0 +1,40 @@
>> +Hisilicon Fast Ethernet MAC controller
>> +
>> +Required properties:
>> +- compatible: should be "hisilicon,hisi-femac" and one of the following:
>
> This compatible seems a bit pointless. The following 2 are generic
> enough.
>
ok, I will remove this compatible.
>> +* "hisilicon,hisi-femac-v1"
>> +* "hisilicon,hisi-femac-v2"
>
> SoC specific compatible strings in addition to these please.
>
ok.
>> +- reg: specifies base physical address(s) and size of the device registers.
>> + The first region is the MAC core register base and size.
>> + The second region is the global MAC control register.
>> +- interrupts: should contain the MAC interrupt.
>> +- clocks: clock phandle and specifier pair.
>
> How many clocks?
>
Only one clock, the following description is ok?
- clocks: phandle reference to the MAC main clock
>> +- resets: should contain the phandle to the MAC reset signal(required) and
>> +the PHY reset signal(optional).
>> +- reset-names: should contain the reset signal name "mac_reset"(required)
>> +and "phy_reset"(optional).
>> +- mac-address: see ethernet.txt [1].
>> +- phy-mode: see ethernet.txt [1].
>> +- phy-handle: see ethernet.txt [1].
>> +- hisilicon,phy-reset-delays: triplet of delays if PHY reset signal given.
>> +The 1st cell is reset pre-delay in micro seconds.
>> +The 2nd cell is reset pulse in micro seconds.
>> +The 3rd cell is reset post-delay in micro seconds.
>
> Add standard unit suffixes.
>
ok.
>> +
>> +[1] Documentation/devicetree/bindings/net/ethernet.txt
>> +
>> +Example:
>> +hisi_femac: ethernet@1009 {
>> +compatible = "hisilicon,hisi-femac-v2", "hisilicon,hisi-femac";
>> +reg = <0x1009 0x1000>,<0x10091300 0x200>;
>> +interrupts = <12>;
>> +clocks = <&crg HI3518EV200_ETH_CLK>;
>> +resets = <&crg 0xec 0>,
>> +<&crg 0xec 3>;
>> +reset-names = "mac_reset",
>> +"phy_reset";
>> +mac-address = [00 00 00 00 00 00];
>> +phy-mode = "mii";
>> +phy-handle = <&phy0>;
>> +hisilicon,phy-reset-delays = <1 2 2>;
>> +};
>
> .
>
Regards,
Dongpo
.
Re: [PATCH 3/3] net: hisilicon: Add Fast Ethernet MAC driver
On 2016/6/15 5:20, Arnd Bergmann wrote:
> On Tuesday, June 14, 2016 9:17:44 PM CEST Li Dongpo wrote:
>> On 2016/6/13 17:06, Arnd Bergmann wrote:
>>> On Monday, June 13, 2016 2:07:56 PM CEST Dongpo Li wrote:
>>> You tx function uses BQL to optimize the queue length, and that
>>> is great. You also check xmit reclaim for rx interrupts, so
>>> as long as you have both rx and tx traffic, this should work
>>> great.
>>>
>>> However, I notice that you only have a 'tx fifo empty'
>>> interrupt triggering the napi poll, so I guess on a tx-only
>>> workload you will always end up pushing packets into the
>>> queue until BQL throttles tx, and then get the interrupt
>>> after all packets have been sent, which will cause BQL to
>>> make the queue longer up to the maximum queue size, and that
>>> negates the effect of BQL.
>>>
>>> Is there any way you can get a tx interrupt earlier than
>>> this in order to get a more balanced queue, or is it ok
>>> to just rely on rx packets to come in occasionally, and
>>> just use the tx fifo empty interrupt as a fallback?
>>>
>> In tx direction, there are only two kinds of interrupts, 'tx fifo empty'
>> and 'tx one packet finish'. I didn't use 'tx one packet finish' because
>> it would lead to high hardware interrupts rate. This has been verified in
>> our chips. It's ok to just use tx fifo empty interrupt.
>
> I'm not convinced by the explanation, I don't think that has anything
> to do with the hardware design, but instead is about the correctness
> of the BQL logic with your driver.
>
> Maybe your xmit function can do something like
>
> if (dql_avail(netdev_get_tx_queue(dev, 0)->dql) < 0)
> enable per-packet interrupt
> else
> use only fifo-empty interrupt
>
> That way, you don't get a lot of interrupts when the system is
> in a state of packets being received and sent continuously,
> but if you get to the point where your tx queue fills up
> and no rx interrupts arrive, you don't have to wait for it
> to become completely empty before adding new packets, and
> BQL won't keep growing the queue.
>
Hi Arnd,
Thanks for your advice. It's a good advice and I will try to fix it and
test on our chip.
>>>> +priv->phy_mode = of_get_phy_mode(node);
>>>> +if (priv->phy_mode < 0) {
>>>> +dev_err(dev, "not find phy-mode\n");
>>>> +ret = -EINVAL;
>>>> +goto out_disable_clk;
>>>> +}
>>>> +
>>>> +priv->phy_node = of_parse_phandle(node, "phy-handle", 0);
>>>> +if (!priv->phy_node) {
>>>> +dev_err(dev, "not find phy-handle\n");
>>>> +ret = -EINVAL;
>>>> +goto out_disable_clk;
>>>> +}
>>>> +
>>>> +priv->phy = of_phy_connect(ndev, priv->phy_node,
>>>> + hisi_femac_adjust_link, 0, priv->phy_mode);
>>>> +if (!(priv->phy) || IS_ERR(priv->phy)) {
>>>> +dev_err(dev, "connect to PHY failed!\n");
>>>> +ret = -ENODEV;
>>>> +goto out_phy_node;
>>>> +}
>>>
>>> I wonder if we could generalize this set of three calls, I
>>> get the impression that we duplicate this across several
>>> drivers that shouldn't need to bother with the specific
>>> phy-handle and phy-mode properties.
>>>
>> Some drivers only call 'of_phy_connect' when ndo_open called,
>> some call when driver probed. But 'phy_mode' and 'phy_node' are
>> usually initialized when driver probed.
>> So I think it's not suitable to combine 'of_phy_connect' with
>> 'of_get_phy_mode' and 'of_parse_phandle'.
>> Do you have any more suggestions ?
>
> My idea was to add another interface that drivers could optionally
> call if they use the logic that you have here, but other drivers
> could keep using the plain of_phy_connect.
>
> Anyway, this was just an idea, it's not important.
>
ok, I get your point. I will try to figure out the general interface.
If there is a solution, I'd like to get more review.
> Arnd
>
> .
>
Regards,
Dongpo
.
[PATCH 2/3] ethtool: Add common functions for get and set settings
Currently, most drivers only support get and set PHY settings
by PHY ethtool API. For those drivers, it's better to
supply common functions for get_settings and set_settings.
This patch adds common functions implementation.
Reviewed-by: Jiancheng Xue
Signed-off-by: Dongpo Li
---
include/linux/ethtool.h | 2 ++
net/core/ethtool.c | 21 +
2 files changed, 23 insertions(+)
diff --git a/include/linux/ethtool.h b/include/linux/ethtool.h
index 9ded8c6..e114db9 100644
--- a/include/linux/ethtool.h
+++ b/include/linux/ethtool.h
@@ -82,6 +82,8 @@ struct net_device;
/* Some generic methods drivers may use in their ethtool_ops */
u32 ethtool_op_get_link(struct net_device *dev);
int ethtool_op_get_ts_info(struct net_device *dev, struct ethtool_ts_info
*eti);
+int ethtool_op_get_settings(struct net_device *dev, struct ethtool_cmd *cmd);
+int ethtool_op_set_settings(struct net_device *dev, struct ethtool_cmd *cmd);
/**
* ethtool_rxfh_indir_default - get default value for RX flow hash indirection
diff --git a/net/core/ethtool.c b/net/core/ethtool.c
index f403481..270b6d1 100644
--- a/net/core/ethtool.c
+++ b/net/core/ethtool.c
@@ -50,6 +50,27 @@ int ethtool_op_get_ts_info(struct net_device *dev, struct
ethtool_ts_info *info)
}
EXPORT_SYMBOL(ethtool_op_get_ts_info);
+int ethtool_op_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
+{
+ if (!dev->phydev)
+ return -ENODEV;
+
+ return phy_ethtool_gset(dev->phydev, cmd);
+}
+EXPORT_SYMBOL(ethtool_op_get_settings);
+
+int ethtool_op_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
+{
+ if (!capable(CAP_NET_ADMIN))
+ return -EPERM;
+
+ if (!dev->phydev)
+ return -ENODEV;
+
+ return phy_ethtool_sset(dev->phydev, cmd);
+}
+EXPORT_SYMBOL(ethtool_op_set_settings);
+
/* Handlers for each ethtool command */
#define ETHTOOL_DEV_FEATURE_WORDS ((NETDEV_FEATURE_COUNT + 31) / 32)
--
2.8.2
[PATCH 1/3] net: Add MDIO bus driver for the Hisilicon FEMAC
This patch adds a separate driver for the MDIO interface of the
Hisilicon Fast Ethernet MAC.
Reviewed-by: Jiancheng Xue
Signed-off-by: Dongpo Li
---
.../bindings/net/hisilicon-femac-mdio.txt | 22 +++
drivers/net/phy/Kconfig| 8 +
drivers/net/phy/Makefile | 1 +
drivers/net/phy/mdio-hisi-femac.c | 165 +
4 files changed, 196 insertions(+)
create mode 100644
Documentation/devicetree/bindings/net/hisilicon-femac-mdio.txt
create mode 100644 drivers/net/phy/mdio-hisi-femac.c
diff --git a/Documentation/devicetree/bindings/net/hisilicon-femac-mdio.txt
b/Documentation/devicetree/bindings/net/hisilicon-femac-mdio.txt
new file mode 100644
index 000..6f46337
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/hisilicon-femac-mdio.txt
@@ -0,0 +1,22 @@
+Hisilicon Fast Ethernet MDIO Controller interface
+
+Required properties:
+- compatible: should be "hisilicon,hisi-femac-mdio".
+- reg: address and length of the register set for the device.
+- clocks: A phandle to the reference clock for this device.
+
+- PHY subnode: inherits from phy binding [1]
+[1] Documentation/devicetree/bindings/net/phy.txt
+
+Example:
+mdio: mdio@10091100 {
+ compatible = "hisilicon,hisi-femac-mdio";
+ reg = <0x10091100 0x10>;
+ clocks = <&crg HI3518EV200_MDIO_CLK>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy0: phy@1 {
+ reg = <1>;
+ };
+};
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 6dad9a9..e257322 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -271,6 +271,14 @@ config MDIO_BCM_IPROC
This module provides a driver for the MDIO busses found in the
Broadcom iProc SoC's.
+config MDIO_HISI_FEMAC
+ tristate "Hisilicon FEMAC MDIO bus controller"
+ depends on ARCH_HISI
+ depends on HAS_IOMEM && OF_MDIO
+ help
+ This module provides a driver for the MDIO busses found in the
+ Hisilicon SoC that have an Fast Ethernet MAC.
+
endif # PHYLIB
config MICREL_KS8995MA
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index fcdbb92..039c4be 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -44,3 +44,4 @@ obj-$(CONFIG_MDIO_MOXART) += mdio-moxart.o
obj-$(CONFIG_MDIO_BCM_UNIMAC) += mdio-bcm-unimac.o
obj-$(CONFIG_MICROCHIP_PHY)+= microchip.o
obj-$(CONFIG_MDIO_BCM_IPROC) += mdio-bcm-iproc.o
+obj-$(CONFIG_MDIO_HISI_FEMAC) += mdio-hisi-femac.o
diff --git a/drivers/net/phy/mdio-hisi-femac.c
b/drivers/net/phy/mdio-hisi-femac.c
new file mode 100644
index 000..a9eea61
--- /dev/null
+++ b/drivers/net/phy/mdio-hisi-femac.c
@@ -0,0 +1,165 @@
+/*
+ * Hisilicon Fast Ethernet MDIO Bus Driver
+ *
+ * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define MDIO_RWCTRL0x00
+#define MDIO_RO_DATA 0x04
+#define MDIO_WRITE BIT(13)
+#define MDIO_RW_FINISH BIT(15)
+#define BIT_PHY_ADDR_OFFSET8
+#define BIT_WR_DATA_OFFSET 16
+
+struct hisi_femac_mdio_data {
+ struct clk *clk;
+ void __iomem *membase;
+};
+
+static int hisi_femac_mdio_wait_ready(struct mii_bus *bus)
+{
+ struct hisi_femac_mdio_data *data = bus->priv;
+ u32 val;
+
+ return readl_poll_timeout(data->membase + MDIO_RWCTRL,
+ val, val & MDIO_RW_FINISH, 20, 1);
+}
+
+static int hisi_femac_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
+{
+ struct hisi_femac_mdio_data *data = bus->priv;
+ int ret;
+
+ ret = hisi_femac_mdio_wait_ready(bus);
+ if (ret)
+ return ret;
+
+ writel((mii_id << BIT_PHY_ADDR_OFFSET) | regnum,
+ data->membase + MDIO_RWCTRL);
+
+ ret = hisi_femac_mdio_wait_ready(bus);
+ if (ret)
+ return ret;
+
+ return readl(data->membase + MDIO_RO_DATA) & 0x;
+}
+
+static int hisi_femac_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
+u16 value)
+{
+
[PATCH 3/3] net: hisilicon: Add Fast Ethernet MAC driver
This patch adds the Hisilicon Fast Ethernet MAC(FEMAC) driver.
The FEMAC supports max speed 100Mbps and has been used in many
Hisilicon SoC.
Reviewed-by: Jiancheng Xue
Signed-off-by: Dongpo Li
---
.../devicetree/bindings/net/hisilicon-femac.txt| 40 +
drivers/net/ethernet/hisilicon/Kconfig | 12 +
drivers/net/ethernet/hisilicon/Makefile|1 +
drivers/net/ethernet/hisilicon/hisi_femac.c| 1015
4 files changed, 1068 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/hisilicon-femac.txt
create mode 100644 drivers/net/ethernet/hisilicon/hisi_femac.c
diff --git a/Documentation/devicetree/bindings/net/hisilicon-femac.txt
b/Documentation/devicetree/bindings/net/hisilicon-femac.txt
new file mode 100644
index 000..b953a56
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/hisilicon-femac.txt
@@ -0,0 +1,40 @@
+Hisilicon Fast Ethernet MAC controller
+
+Required properties:
+- compatible: should be "hisilicon,hisi-femac" and one of the following:
+ * "hisilicon,hisi-femac-v1"
+ * "hisilicon,hisi-femac-v2"
+- reg: specifies base physical address(s) and size of the device registers.
+ The first region is the MAC core register base and size.
+ The second region is the global MAC control register.
+- interrupts: should contain the MAC interrupt.
+- clocks: clock phandle and specifier pair.
+- resets: should contain the phandle to the MAC reset signal(required) and
+ the PHY reset signal(optional).
+- reset-names: should contain the reset signal name "mac_reset"(required)
+ and "phy_reset"(optional).
+- mac-address: see ethernet.txt [1].
+- phy-mode: see ethernet.txt [1].
+- phy-handle: see ethernet.txt [1].
+- hisilicon,phy-reset-delays: triplet of delays if PHY reset signal given.
+ The 1st cell is reset pre-delay in micro seconds.
+ The 2nd cell is reset pulse in micro seconds.
+ The 3rd cell is reset post-delay in micro seconds.
+
+[1] Documentation/devicetree/bindings/net/ethernet.txt
+
+Example:
+ hisi_femac: ethernet@1009 {
+ compatible = "hisilicon,hisi-femac-v2", "hisilicon,hisi-femac";
+ reg = <0x1009 0x1000>,<0x10091300 0x200>;
+ interrupts = <12>;
+ clocks = <&crg HI3518EV200_ETH_CLK>;
+ resets = <&crg 0xec 0>,
+ <&crg 0xec 3>;
+ reset-names = "mac_reset",
+ "phy_reset";
+ mac-address = [00 00 00 00 00 00];
+ phy-mode = "mii";
+ phy-handle = <&phy0>;
+ hisilicon,phy-reset-delays = <1 2 2>;
+ };
diff --git a/drivers/net/ethernet/hisilicon/Kconfig
b/drivers/net/ethernet/hisilicon/Kconfig
index 4ccc032..49ab550 100644
--- a/drivers/net/ethernet/hisilicon/Kconfig
+++ b/drivers/net/ethernet/hisilicon/Kconfig
@@ -23,6 +23,18 @@ config HIX5HD2_GMAC
help
This selects the hix5hd2 mac family network device.
+config HISI_FEMAC
+ tristate "Hisilicon Fast Ethernet MAC device support"
+ select PHYLIB
+ select RESET_CONTROLLER
+ select MDIO_HISI_FEMAC
+ help
+ This selects the Hisilicon Fast Ethernet MAC device(FEMAC).
+ The FEMAC receives and transmits data over Ethernet
+ ports at 10/100 Mbps in full-duplex or half-duplex mode.
+ The FEMAC exchanges data with the CPU, and supports
+ the energy efficient Ethernet (EEE).
+
config HIP04_ETH
tristate "HISILICON P04 Ethernet support"
depends on HAS_IOMEM# For MFD_SYSCON
diff --git a/drivers/net/ethernet/hisilicon/Makefile
b/drivers/net/ethernet/hisilicon/Makefile
index 390b71f..8661695 100644
--- a/drivers/net/ethernet/hisilicon/Makefile
+++ b/drivers/net/ethernet/hisilicon/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_HIX5HD2_GMAC) += hix5hd2_gmac.o
obj-$(CONFIG_HIP04_ETH) += hip04_eth.o
obj-$(CONFIG_HNS_MDIO) += hns_mdio.o
obj-$(CONFIG_HNS) += hns/
+obj-$(CONFIG_HISI_FEMAC) += hisi_femac.o
diff --git a/drivers/net/ethernet/hisilicon/hisi_femac.c
b/drivers/net/ethernet/hisilicon/hisi_femac.c
new file mode 100644
index 000..0c85ac7
--- /dev/null
+++ b/drivers/net/ethernet/hisilicon/hisi_femac.c
@@ -0,0 +1,1015 @@
+/*
+ * Hisilicon Fast Ethernet MAC Driver
+ *
+ * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *
[PATCH 0/3] Add Hisilicon MDIO bus driver and FEMAC driver
This patch set adds a Hisilicon MDIO bus driver and a Fast Ethernet MAC(FEMAC) driver. We found that most ethernet mac drivers use the same ethtool get_settings and set_settings, so this patch set also adds common functions for get and set settings. Dongpo Li (3): net: Add MDIO bus driver for the Hisilicon FEMAC ethtool: Add common functions for get and set settings net: hisilicon: Add Fast Ethernet MAC driver .../bindings/net/hisilicon-femac-mdio.txt | 22 + .../devicetree/bindings/net/hisilicon-femac.txt| 40 + drivers/net/ethernet/hisilicon/Kconfig | 12 + drivers/net/ethernet/hisilicon/Makefile|1 + drivers/net/ethernet/hisilicon/hisi_femac.c| 1015 drivers/net/phy/Kconfig|8 + drivers/net/phy/Makefile |1 + drivers/net/phy/mdio-hisi-femac.c | 165 include/linux/ethtool.h|2 + net/core/ethtool.c | 21 + 10 files changed, 1287 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/hisilicon-femac-mdio.txt create mode 100644 Documentation/devicetree/bindings/net/hisilicon-femac.txt create mode 100644 drivers/net/ethernet/hisilicon/hisi_femac.c create mode 100644 drivers/net/phy/mdio-hisi-femac.c -- 2.8.2
