>
> Signed-off-by: Alexandre Torgue
Hi Alexandre,
Reviewed-by: Fabrice Gasnier
Thanks,
Fabrice
>
> diff --git a/arch/arm/boot/dts/stm32f429.dtsi
> b/arch/arm/boot/dts/stm32f429.dtsi
> index 41e0087bdbf9..8748d5850298 100644
> --- a/arch/arm/boot/dts/stm32f429.d
xandre,
Not sure if this matters: patches 3 and 4 could be swapped in the
series. Apart from that:
Reviewed-by: Fabrice Gasnier
Thanks,
Fabrice
> @@ -119,8 +119,6 @@ patternProperties:
>- compatible
>
> required:
> - - "#address-cells"
> - - "#size-cells"
>- compatible
>- reg
>- clocks
>
/write function is called.
>
> Cc: Syed Nayyar Waris
> Cc: Patrick Havelange
> Cc: Kamel Bouhara
> Cc: Fabrice Gasnier
> Cc: Maxime Coquelin
> Cc: Alexandre Torgue
> Cc: Dan Carpenter
> Reviewed-by: David Lechner
> Tested-by: David Lechner
> Signed-o
; phrase
> to make the intent of this code clearer.
>
> Cc: Syed Nayyar Waris
> Cc: Patrick Havelange
> Cc: Oleksij Rempel
> Cc: Kamel Bouhara
> Cc: Fabrice Gasnier
> Cc: Maxime Coquelin
> Cc: Alexandre Torgue
> Cc: David Lechner
> Signed-off-by: William Breathi
On 3/19/21 12:00 PM, William Breathitt Gray wrote:
> ERANGE is a semantically better error code to return when an argument
> value falls outside the supported limit range of a device.
>
> Cc: Syed Nayyar Waris
> Cc: Oleksij Rempel
> Cc: Fabrice Gasnier
> Cc: Maxime Coqu
od to define a default switch cases for the sake of making the
> intent of the code clear.
>
> Cc: Syed Nayyar Waris
> Cc: Kamel Bouhara
> Cc: Fabrice Gasnier
> Cc: Maxime Coquelin
> Cc: Alexandre Torgue
> Cc: David Lechner
> Signed-off-by: William Breathitt Gray
On 3/19/21 12:00 PM, William Breathitt Gray wrote:
> The struct counter_synapse actions_list member expects a const enum
> counter_synapse_action array. This patch adds the const qualifier to the
> stm32_synapse_actions to match actions_list.
>
> Cc: Fabrice Gasnier
> Cc:
On 3/19/21 12:00 PM, William Breathitt Gray wrote:
> The struct counter_synapse actions_list member expects a const enum
> counter_synapse_action array. This patch adds the const qualifier to the
> stm32_lptim_cnt_synapse_actions to match actions_list.
>
> Cc: Fabrice Gasnie
On 3/19/21 12:00 PM, William Breathitt Gray wrote:
> The struct counter_count functions_list member expects a const enum
> counter_count_function array. This patch adds the const qualifier to the
> stm32_count_functions to match functions_list.
>
> Cc: Fabrice Gasnier
> Cc:
On 3/19/21 12:00 PM, William Breathitt Gray wrote:
> The struct counter_count functions_list member expects a const enum
> counter_count_function array. This patch adds the const qualifier to the
> stm32_lptim_cnt_functions to match functions_list.
>
> Cc: Fabrice Gasnie
On 3/3/21 6:51 PM, Fabrice Gasnier wrote:
> The ARR register is cleared unconditionally upon probing, after the maximum
> value has been read. This initial condition is rather not intuitive, when
> considering the counter child driver. It rather expects the maximum value
>
On 3/18/21 10:21 AM, Fabrice Gasnier wrote:
> On 3/14/21 10:08 AM, William Breathitt Gray wrote:
>> On Sun, Mar 14, 2021 at 04:56:44PM +0900, William Breathitt Gray wrote:
>>> On Fri, Mar 12, 2021 at 04:02:42PM +0100, Fabrice Gasnier wrote:
>>>> On 3/9/21 2:19 PM
On 3/14/21 10:08 AM, William Breathitt Gray wrote:
> On Sun, Mar 14, 2021 at 04:56:44PM +0900, William Breathitt Gray wrote:
>> On Fri, Mar 12, 2021 at 04:02:42PM +0100, Fabrice Gasnier wrote:
>>> On 3/9/21 2:19 PM, William Breathitt Gray wrote:
>>>> +static ssize_t
.
Fixes: d0f949e220fd ("mfd: Add STM32 Timers driver")
Signed-off-by: Fabrice Gasnier
---
drivers/mfd/stm32-timers.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/mfd/stm32-timers.c b/drivers/mfd/stm32-timers.c
index add6033..44ed2fc 100644
--- a/drivers
as priv->ceiling isn't used in
performance critical path.
There's also no point in writing ARR while setting function (sms), so
it can be safely removed.
Fixes: ad29937e206f ("counter: Add STM32 Timer quadrature encoder")
Suggested-by: William Breathitt Gray
Signed-off-by: Fabrice Ga
eletions(-)
>
Hi Martin,
I'm only wondering on moving the allOf and the st,hw-flow-ctrl prop. But
others may comment on this.
Feel free to add my:
Acked-by: Fabrice Gasnier
Thanks!
Fabrice
> diff --git a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml
> b/Documentation/d
On 3/3/21 12:42 AM, William Breathitt Gray wrote:
> On Tue, Mar 02, 2021 at 06:03:25PM +0100, Fabrice Gasnier wrote:
>> On 3/2/21 3:56 PM, William Breathitt Gray wrote:
>>> Side question: if priv->ceiling is tracking the current ceiling
>>> configuration,
usart.h | 4
> 2 files changed, 14 insertions(+), 1 deletion(-)
Hi Martin,
You can add my:
Acked-by: Fabrice Gasnier
Thanks for your patch,
Best Regards,
Fabrice
>
> diff --git a/drivers/tty/serial/stm32-usart.c
> b/drivers/tty/serial/stm32-usart.c
> index b3675cf25a69..d39
.cfg = {
> .uart_enable_bit = 13,
> .has_7bits_data = false,
> + .has_swap = false,
Hi Martin,
Only one minor comment from me here. No need to add a false (zero)
initialization in this struct. I'm not sure why this is the case for the
has_7bit
On 3/2/21 3:56 PM, William Breathitt Gray wrote:
> On Tue, Mar 02, 2021 at 03:43:55PM +0100, Fabrice Gasnier wrote:
>> The ceiling value isn't checked before writing it into registers. The user
>> could write a value higher than the counter resolution (e.g. 16 or 32 bits
>>
.
Fixes: ad29937e206f ("counter: Add STM32 Timer quadrature encoder")
[1] https://lkml.org/lkml/2021/2/12/358
Signed-off-by: Fabrice Gasnier
---
drivers/counter/stm32-timer-cnt.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/counter/stm32-timer-cnt.c
b/drivers/counter/s
On 3/1/21 11:40 PM, Martin DEVERA wrote:
> On 3/1/21 11:28 AM, Fabrice Gasnier wrote:
>> On 2/27/21 5:41 PM, Martin Devera wrote:
>>> STM32 F7/H7 usarts supports RX & TX pin swapping.
>>> Add option to turn it on.
>>> Tested on STM32MP1
On 2/27/21 5:41 PM, Martin Devera wrote:
> Add new rx-tx-swap property to allow for RX & TX pin swapping.
>
> Signed-off-by: Martin Devera
> ---
> Documentation/devicetree/bindings/serial/st,stm32-uart.yaml | 4
> 1 file changed, 4 insertions(+)
>
> diff --git
On 2/27/21 5:41 PM, Martin Devera wrote:
> STM32 F7/H7 usarts supports RX & TX pin swapping.
> Add option to turn it on.
> Tested on STM32MP157.
>
> Signed-off-by: Martin Devera
> ---
> drivers/tty/serial/stm32-usart.c | 3 ++-
> drivers/tty/serial/stm32-usart.h | 1 +
> 2 files changed, 3
perly handle this behavior.
>
> Fixes: ad29937e206f ("counter: Add STM32 Timer quadrature encoder")
> Cc: Fabrice Gasnier
> Cc: Maxime Coquelin
> Cc: Alexandre Torgue
> Signed-off-by: William Breathitt Gray
> ---
> Changes in v2:
> - Support an explicit 0 case for fu
iam,
Thanks for the patch, that's something I also noticed earlier.
Please find few comment below.
>
> Fixes: ad29937e206f ("counter: Add STM32 Timer quadrature encoder")
> Cc: Fabrice Gasnier
> Cc: Maxime Coquelin
> Cc: Alexandre Torgue
> Signed-off-by: William Breath
On 1/22/21 1:18 PM, Ahmad Fatoum wrote:
> Hello Fabrice,
>
> On 19.01.21 18:56, Fabrice Gasnier wrote:
>> On 1/18/21 12:42 PM, Ahmad Fatoum wrote:
>>> Hello Jonathan,
>>>
>>> On 16.01.21 18:53, Jonathan Cameron wrote:
>>>> On Tu
./Documentation/ABI/testing/sysfs-bus-iio-lptimer-stm32:0
[1] https://lkml.org/lkml/2021/1/19/347
Signed-off-by: Fabrice Gasnier
---
.../ABI/testing/sysfs-bus-iio-lptimer-stm32| 62 -
drivers/counter/stm32-lptimer-cnt.c| 297 +++--
2 files changed, 36
dma_chan)
> + if (!adc->dma_chan) {
> handler = _adc_trigger_handler;
Hi Ahmad,
Just suggesting: maybe add a quick comment to indicate that timestamping
is supported in PIO mode (only), as DMA doesn't fill it into the buffer
(well described in the commit message).
> +
On 1/19/21 11:41 AM, Jonathan Cameron wrote:
> On Tue, 19 Jan 2021 18:17:05 +0900
> William Breathitt Gray wrote:
>
>> On Sun, Jan 17, 2021 at 03:42:18PM +, Jonathan Cameron wrote:
>>> On Fri, 15 Jan 2021 13:47:20 +
>>> Jonathan Cameron wrote:
>>>
On Fri, 15 Jan 2021 10:49:47
On 1/18/21 12:42 PM, Ahmad Fatoum wrote:
> Hello Jonathan,
>
> On 16.01.21 18:53, Jonathan Cameron wrote:
>> On Tue, 12 Jan 2021 16:24:42 +0100
>> Ahmad Fatoum wrote:
>>
>>> 1c6c69525b40 ("genirq: Reject bogus threaded irq requests") makes sure
>>> that threaded IRQs either
>>> - have
stm32-adc-core.c | 29 +++--
> drivers/iio/adc/stm32-adc.c | 14 +-
> 2 files changed, 16 insertions(+), 27 deletions(-)
Hi Xu,
Acked-by: Fabrice Gasnier
Thanks for your patch,
Best Regards,
Fabrice
>
> diff --git a/drivers/iio/adc/stm32-adc-core.c
> b/driv
The stm32 timers example name should match the pattern timer@. Also,
the example is based on stm32mp1 timer 2, so the identifier should be
'1' instead of '0' (e.g. timer 1).
Fixes: bfbcbf88f9db ("dt-bindings: timer: Convert stm32 timer bindings to
json-schema")
Signed-off-by: Fabri
On 11/8/20 4:18 PM, Jonathan Cameron wrote:
> On Fri, 6 Nov 2020 17:57:26 +0100
> Fabrice Gasnier wrote:
>
>> For proper operation, STM32 ADC should be used with a clock duty cycle
>> of 50%, in the range of 49% to 51%. Depending on the clock tree, divider
>> can be us
t;&1|grep iio
Fixes: 3442841d ("docs: ABI: testing: make the files compatible with ReST
output")
Signed-off-by: Fabrice Gasnier
---
.../ABI/testing/sysfs-bus-iio-timer-stm32 | 24 --
1 file changed, 24 deletions(-)
diff --git a/Documentation/ABI/
make the probe fail).
Signed-off-by: Fabrice Gasnier
---
drivers/iio/adc/stm32-adc-core.c | 21 -
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/drivers/iio/adc/stm32-adc-core.c b/drivers/iio/adc/stm32-adc-core.c
index cd870c0..d64a9e8 100644
--- a/drivers/iio
On 11/5/20 3:29 PM, Olivier Moysan wrote:
> - Remove processing related to DMA in irq handler as this
> data transfer is managed directly in DMA callback.
> - Update comment in stm32_adc_set_watermark() function.
>
> Signed-off-by: Olivier Moysan
Hi Olivier,
Reviewed-by:
On 10/30/20 11:09 AM, Mauro Carvalho Chehab wrote:
> Em Fri, 30 Oct 2020 10:19:12 +0100
> Fabrice Gasnier escreveu:
>
>> Hi Mauro,
>>
>> [...]
>>
>>>
>>> +What:
>>> /sys/bus/iio/devices/iio:deviceX/in_count_quadrat
The following commit has been merged into the irq/urgent branch of tip:
Commit-ID: a00e85b581fd5ee47e770b6b8d2038dbebbe81f9
Gitweb:
https://git.kernel.org/tip/a00e85b581fd5ee47e770b6b8d2038dbebbe81f9
Author:Fabrice Gasnier
AuthorDate:Fri, 16 Oct 2020 16:40:17 +02:00
input serves as the count input and A as
> + the UP/DOWN direction control input.
> +
> + quadrature:
> + Encoder A and B inputs are mixed to get direction
> + and count with a scale of 0.25.
> +
I just noticed th
On 10/29/20 8:49 AM, Coiby Xu wrote:
> SET_SYSTEM_SLEEP_PM_OPS has already took good care of CONFIG_PM_CONFIG.
>
> Signed-off-by: Coiby Xu
> ---
> drivers/iio/adc/stm32-adc.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/drivers/iio/adc/stm32-adc.c b/drivers/iio/adc/stm32-adc.c
>
On 10/29/20 8:46 AM, Coiby Xu wrote:
> SET_SYSTEM_SLEEP_PM_OPS has already took good care of CONFIG_PM_CONFIG.
>
> Signed-off-by: Coiby Xu
> ---
> drivers/i2c/busses/i2c-stm32f7.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/drivers/i2c/busses/i2c-stm32f7.c
>
LP timer can be used to wakeup from stop mode on stm32mp151.
Add wakeup-source properties to all LP timer instances.
Signed-off-by: Fabrice Gasnier
---
arch/arm/boot/dts/stm32mp151.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/stm32mp151.dtsi
b/arch/arm/boot
Add all remaining LP timer exti direct events, e.g. for LP Timer 2 to 5.
LP timer 1 is already listed (e.g. exti 47).
Signed-off-by: Fabrice Gasnier
---
drivers/irqchip/irq-stm32-exti.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip
STM32 LP timer that's available on STM32MP15x can wakeup the platform
using EXTI interrupts.
This series add:
- LP timer EXTI - GIC interrupt events to EXTI driver and device-tree
- LP timer wakeup-source to device-tree
Fabrice Gasnier (3):
irqchip/stm32-exti: Add all LP timer exti direct
Add all LP timer irqs on stm32mp151.
Signed-off-by: Fabrice Gasnier
---
arch/arm/boot/dts/stm32mp151.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/stm32mp151.dtsi
b/arch/arm/boot/dts/stm32mp151.dtsi
index bfe2902..10d5e2b 100644
--- a/arch/arm/boot/dts
This enables the counter subsystem and drivers for the stm32 timer and LP
timer.
Signed-off-by: Fabrice Gasnier
---
arch/arm/configs/multi_v7_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/configs/multi_v7_defconfig
b/arch/arm/configs/multi_v7_defconfig
index e9e76e3
On 7/1/20 4:55 PM, Fabrice Gasnier wrote:
> When the ADC is runtime suspended and starting a conversion, the stm32-adc
> driver calls pm_runtime_get_sync() that gets cascaded to the parent
> (e.g. runtime resume of stm32-adc-core driver). This also kicks the
> autosuspend de
u Ardelean
> ---
> drivers/iio/dac/stm32-dac.c | 13 +
> 1 file changed, 9 insertions(+), 4 deletions(-)
Hi Alexandru,
Many thanks for this updated patch,
Reviewed-by: Fabrice Gasnier
Best regards,
Fabrice
>
> diff --git a/drivers/iio/dac/stm32-dac.c b/drivers/iio/
On 8/27/20 10:55 AM, Alexandru Ardelean wrote:
> On Wed, Aug 26, 2020 at 3:03 PM Alexandru Ardelean
> wrote:
>> From: Sergiu Cuciurean
>>
>> As part of the general cleanup of indio_dev->mlock, this change replaces
>> it with a local lock. The lock protects against potential races when
>> reading
On 8/26/20 8:38 AM, Alexandru Ardelean wrote:
> From: Sergiu Cuciurean
>
> As part of the general cleanup of indio_dev->mlock, this change replaces
> it with a local lock on the device's state structure.
>
> The patch also does a minor whitespace change to align the 'lock' with the
> 'common'
refbuf_of_match[] = {
> | ^~
>
> Signed-off-by: Jisheng Zhang
Hi Jisheng,
Acked-by: Fabrice Gasnier
Thanks for the patch,
Fabrice
> ---
> drivers/regulator/stm32-vrefbuf.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
&g
ooster_of_match[] = {
> | ^~
>
> Signed-off-by: Jisheng Zhang
Hi Jisheng,
Acked-by: Fabrice Gasnier
Thanks for the patch,
Fabrice
> ---
> drivers/regulator/stm32-booster.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
&g
On 8/20/20 9:46 AM, Jisheng Zhang wrote:
> Fix below warning when CONFIG_OF=n:
>
> drivers/regulator/stm32-vrefbuf.c:287:34: warning: ‘stm32_vrefbuf_of_match’
> defined but not used [-Wunused-const-variable=]
> 287 | static const struct of_device_id stm32_vrefbuf_of_match[] = {
> |
this.
Fixes: 9bdbb1139ca1 ("iio: adc: stm32-adc: add power management support")
Signed-off-by: Fabrice Gasnier
---
Changes in v2:
- Use runtime_idle callback in stm32-adc-core driver, instead of refreshing
last_busy from the child (for the parent) at many place. Initial patch v1
l
On 5/3/20 1:48 PM, Jonathan Cameron wrote:
> On Wed, 29 Apr 2020 14:29:08 +0200
> Fabrice Gasnier wrote:
>
>> When the ADC is runtime suspended and starting a conversion, the stm32-adc
>> driver calls pm_runtime_get_sync() that gets cascaded to the parent
>> (e.g.
32-adc.c | 118 +++-
> 1 file changed, 63 insertions(+), 55 deletions(-)
Hi Alexandru,
Acked-by: Fabrice Gasnier
Thanks,
Fabrice
>
> diff --git a/drivers/iio/adc/stm32-adc.c b/drivers/iio/adc/stm32-adc.c
> index ae622ee6d08c..1dd97ec5571c 100644
> -
nce
> * Note: Must be called once ADC is out of power down.
> */
> -static int stm32h7_adc_selfcalib(struct stm32_adc *adc)
> +static int stm32h7_adc_selfcalib(struct iio_dev *indio_dev)
Same here
> {
> - struct iio_dev *indio_dev = iio_priv_to_dev(adc);
> + struc
On 5/16/20 5:35 PM, Jonathan Cameron wrote:
> On Thu, 14 May 2020 11:50:12 +0300
> Sergiu Cuciurean wrote:
>
>> As part of the general cleanup of indio_dev->mlock, this change replaces
>> it with a local lock on the device's state structure.
>>
>> Signed-off-by: Sergiu Cuciurean
>> ---
>>
rt for STM32MP1")
Signed-off-by: Fabrice Gasnier
---
drivers/iio/adc/stm32-adc-core.c | 34 ++
1 file changed, 14 insertions(+), 20 deletions(-)
diff --git a/drivers/iio/adc/stm32-adc-core.c b/drivers/iio/adc/stm32-adc-core.c
index ebe5dbc..3586369 100644
--- a/drive
3ea0585c99 ("iio: adc: stm32: add optional dma support")
Signed-off-by: Fabrice Gasnier
---
drivers/iio/adc/stm32-adc.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/iio/adc/stm32-adc.c b/drivers/iio/adc/stm32-adc.c
index ae622ee..dfc3a30 100644
-
a949800d2d ("IIO: ADC: add stm32 DFSDM support for PDM microphone")
Signed-off-by: Fabrice Gasnier
---
drivers/iio/adc/stm32-dfsdm-adc.c | 21 +++--
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/iio/adc/stm32-dfsdm-adc.c
b/drivers/iio/adc/stm
this.
Fixes: 9bdbb1139ca1 ("iio: adc: stm32-adc: add power management support")
Signed-off-by: Fabrice Gasnier
---
Changes in v2:
- Use runtime_idle callback in stm32-adc-core driver, instead of refreshing
last_busy from the child (for the parent) at many place. Initial patch v1
l
On 10/16/19 9:06 AM, Thierry Reding wrote:
> On Fri, Oct 04, 2019 at 02:53:53PM +0200, Fabrice Gasnier wrote:
>> Add suspend/resume PM sleep ops. When going to low power, enforce the PWM
>> channel isn't active. Let the PWM consumers disable it during their own
>> suspend
On 10/1/19 10:51 AM, Fabrice Gasnier wrote:
> When in slave mode, an arbitration loss (ARLO) may be detected before the
> slave had a chance to detect the stop condition (STOPF in ISR).
> This is seen when two master + slave adapters switch their roles. It
> provokes the i2c bus to be
On 9/30/19 5:28 PM, Fabrice Gasnier wrote:
> The slave-interface documentation [1] states "the bus driver should
> transmit the first byte" upon I2C_SLAVE_READ_REQUESTED slave event:
> - 'val': backend returns first byte to be sent
> The driver currently ignores the 1st byte
This series adds support for digital-to-analog converter on
stm32mp157c-ed1 board:
- define pins that can be used for DAC
- configure DAC channels to use these
Fabrice Gasnier (2):
ARM: dts: stm32: Add DAC pins used on stm32mp157c-ed1
ARM: dts: stm32: Add DAC support to stm32mp157c-ed1
arch
.
Signed-off-by: Fabrice Gasnier
---
arch/arm/boot/dts/stm32mp157c-ed1.dts | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts
b/arch/arm/boot/dts/stm32mp157c-ed1.dts
index 1d426ea..2b40ad9 100644
--- a/arch/arm/boot/dts/stm32mp157c-ed1.dts
Define pins that can be used by digital-to-analog converter on
stm32mp157c eval daughter board:
- PA4 and PA5 pins are available respectively on JP11 and JP10
Signed-off-by: Fabrice Gasnier
---
arch/arm/boot/dts/stm32mp157-pinctrl.dtsi | 12
1 file changed, 12 insertions(+)
diff
Add support for runtime PM & sleep.
Provide pclk to regmap as registers access doesn't need full power
(e.g. regulator). Always restore HFSEL when resuming. It may get lost
depending on low power level that has been achieved.
Signed-off-by: Fabrice Gasnier
---
drivers/iio/dac/stm32-dac-co
On 10/8/19 4:45 PM, Uwe Kleine-König wrote:
> On Tue, Oct 08, 2019 at 01:41:27PM +0200, Fabrice Gasnier wrote:
>> Add a comment to better describe the purpose of breakinput feature that
>> can be found on some STM32 timer instances. Briefly comment on the
>> characteristics
Add a comment to better describe the purpose of breakinput feature that
can be found on some STM32 timer instances. Briefly comment on the
characteristics of this input for PWM, and pinmuxing as suggested in [1].
[1] https://lkml.org/lkml/2019/10/1/207
Signed-off-by: Fabrice Gasnier
On 10/5/19 7:30 PM, William Breathitt Gray wrote:
> On Wed, Sep 25, 2019 at 10:51:26AM +0100, Colin King wrote:
>> From: Colin Ian King
>>
>> There is an if statement that is indented one level too deeply,
>> remove the extraneous tabs.
>>
>> Signed-off-by: Colin Ian King
>> ---
>>
a comment to mention registers content may be lost in low power mode
Fabrice Gasnier (3):
dt-bindings: pwm-stm32: document pinctrl sleep state
pwm: stm32: split breakinput apply routine to ease PM support
pwm: stm32: add power management support
.../devicetree/bindings/pwm/pwm-stm32.txt
be lost when going to low power mode.
[1] https://lkml.org/lkml/2019/2/5/770
Signed-off-by: Fabrice Gasnier
---
Changes in v2:
Follow Uwe suggestions/remarks:
- Add a precursor patch to ease reviewing
- Use registers read instead of pwm_get_state
- Add a comment to mention registers content may
stm32_pwm_apply_breakinputs()
This is a precursor patch to ease PM support. Registers content may get
lost during low power. So, break input settings applied upon probe need
to be restored upon resume (e.g. by calling stm32_pwm_apply_breakinputs()).
Signed-off-by: Fabrice Gasnier
---
drivers/pwm/pwm-stm32.c | 48
Add documentation for pinctrl sleep state that can be used by
STM32 timers PWM.
Signed-off-by: Fabrice Gasnier
---
Documentation/devicetree/bindings/pwm/pwm-stm32.txt | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/pwm/pwm-stm32.txt
On 10/1/19 11:51 AM, Uwe Kleine-König wrote:
> Hello Fabrice,
>
> On Tue, Oct 01, 2019 at 10:18:31AM +0200, Fabrice Gasnier wrote:
>> On 10/1/19 9:04 AM, Uwe Kleine-König wrote:
>>> On Mon, Sep 30, 2019 at 05:39:11PM +0200, Fabrice Gasnier wrote:
>>>> Add sus
being detected by the slave isr handler,
to properly handle this stop condition. E.g. don't mask IRQs in error
handler, when the slave is running.
Fixes: 60d609f30de2 ("i2c: i2c-stm32f7: Add slave support")
Signed-off-by: Fabrice Gasnier
---
drivers/i2c/busses/i2c-stm3
On 10/1/19 9:04 AM, Uwe Kleine-König wrote:
> Hello Fabrice,
>
> On Mon, Sep 30, 2019 at 05:39:11PM +0200, Fabrice Gasnier wrote:
>> Add suspend/resume PM sleep ops. When going to low power, enforce the PWM
>> channel isn't active. Let the PWM consumers disable it during
be lost when going to low power mode.
[1] https://lkml.org/lkml/2019/2/5/770
Signed-off-by: Fabrice Gasnier
---
drivers/pwm/pwm-stm32.c | 82 +
1 file changed, 62 insertions(+), 20 deletions(-)
diff --git a/drivers/pwm/pwm-stm32.c b/drivers/pwm
Add documentation for pinctrl sleep state that can be used by
STM32 timers PWM.
Signed-off-by: Fabrice Gasnier
---
Documentation/devicetree/bindings/pwm/pwm-stm32.txt | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/pwm/pwm-stm32.txt
This patch series adds power management support for STM32 Timer PWM:
- Document the pinctrl sleep state for STM32 Timer PWM
- STM32 Timer PWM driver
Fabrice Gasnier (2):
dt-bindings: pwm-stm32: document pinctrl sleep state
pwm: stm32: add power management support
.../devicetree/bindings/pwm
32f7: Add slave support")
[1] https://www.kernel.org/doc/Documentation/i2c/slave-interface
Signed-off-by: Fabrice Gasnier
---
drivers/i2c/busses/i2c-stm32f7.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/i2c/busses/i2c-stm32f7.c b/drivers/i2c/busses/i2c-stm32f7.c
index 266
parameter or member
'writeval' not described in 'stm32_adc_debugfs_reg_access'
drivers/iio/adc/stm32-adc.c:1420: warning: Function parameter or member
'readval' not described in 'stm32_adc_debugfs_reg_access'
Signed-off-by: Fabrice Gasnier
---
Note: this applies on top of "iio: adc: stm32-adc
to be written in ARR register later in
the apply() routine.
This results in badly configured PWM period (and also duty_cycle).
Add a check to report an error is such a case.
Signed-off-by: Fabrice Gasnier
---
Changes in v2:
- remarks from Uwe: update the comment, use dev_dbg() and print period that
cannot
Fix the following warnings when documentation is built:
drivers/counter/stm32-lptimer-cnt.c:354: warning: cannot understand
function prototype: 'enum stm32_lptim_cnt_function'
Signed-off-by: Fabrice Gasnier
---
drivers/counter/stm32-lptimer-cnt.c | 2 +-
1 file changed, 1 insertion(+), 1
Fix the following warning when documentation is built:
drivers/counter/stm32-timer-cnt.c:37: warning: cannot understand function
prototype: 'enum stm32_count_function'
Signed-off-by: Fabrice Gasnier
---
drivers/counter/stm32-timer-cnt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion
On 9/18/19 9:52 AM, William Breathitt Gray wrote:
> The count_read and count_write callbacks pass unsigned long now.
>
> Cc: Fabrice Gasnier
> Signed-off-by: William Breathitt Gray
Hi William,
I tested your series for STM32 timer and LPtimer drivers. Maybe you can
squash
to be written in ARR register later in
the apply() routine.
This results in badly configured PWM period (and also duty_cycle).
Add a check to report an error is such a case.
Signed-off-by: Fabrice Gasnier
---
drivers/pwm/pwm-stm32-lp.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/pwm
a precursor patch to follow Jonathan's comment on readability
Fabrice Gasnier (2):
iio: adc: stm32-adc: move registers definitions
iio: adc: stm32-adc: fix a race when using several adcs with dma and
irq
drivers/iio/adc/stm32-adc-core.c | 70 +++-
drivers/iio/adc/stm32-adc
driver.
Fixes: 2763ea0585c9 ("iio: adc: stm32: add optional dma support")
Signed-off-by: Fabrice Gasnier
---
drivers/iio/adc/stm32-adc-core.c | 27
drivers/iio/adc/stm32-adc-core.h | 136 +++
drivers/iio/adc/stm32-adc.c
before invoking the interrupt handler (e.g. call ISR only for
IRQ-enabled ADCs).
Fixes: 2763ea0585c9 ("iio: adc: stm32: add optional dma support")
Signed-off-by: Fabrice Gasnier
---
Changes in v2:
- Keep registers definitions as a whole block to ease readability (add
a precursor patch to
On 9/15/19 12:05 PM, Jonathan Cameron wrote:
> On Fri, 13 Sep 2019 15:21:30 +0200
> Fabrice Gasnier wrote:
>
>> End of conversion may be handled by using IRQ or DMA. There may be a
>> race when two conversions complete at the same time on several ADCs.
>> EOC can b
Enable VREFBUF as ADC/DAC uses it on stm32mp157a-dk1 board.
Signed-off-by: Fabrice Gasnier
---
arch/arm/boot/dts/stm32mp157a-dk1.dts | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/stm32mp157a-dk1.dts
b/arch/arm/boot/dts/stm32mp157a-dk1.dts
index 0615d1c..ebd9f33
This series adds support for ADC on stm32mp157a-dk1 board:
- enable vrefbuf regulator used as reference voltage
- define ADC pins for AIN connector and USB Type-C CC pins
- configure ADC1 and ADC2 to use these
Fabrice Gasnier (3):
ARM: dts: stm32: Enable VREFBUF on stm32mp157a-dk1
ARM: dts
d by default,
so the pins are kept in their initial state to lower power consumption.
This way they can also be used as GPIO.
Add VDD and VDDA supplies to ADC on stm32mp157c-dk1 board. This allows to
get full ADC analog performances in case VDDA is below 2.7V (not the case
by default).
Signed-off-by:
Define pins that can be used for ADC on stm32mp157a-dk1 board:
- AIN connector has ADC input pins
- USB Type-C CC1 & CC2 pins (e.g. in18, in19)
Signed-off-by: Fabrice Gasnier
---
arch/arm/boot/dts/stm32mp157-pinctrl.dtsi | 16
1 file changed, 16 insertions(+)
diff --git a/
before invoking the interrupt handler (e.g. call ISR only for
IRQ-enabled ADCs).
Fixes: 2763ea0585c9 ("iio: adc: stm32: add optional dma support")
Signed-off-by: Fabrice Gasnier
---
drivers/iio/adc/stm32-adc-core.c | 43 +---
drivers/iio/adc/stm32-adc-c
On 7/23/19 3:41 AM, Axel Lin wrote:
> Setting .n_voltages = 1 and .fixed_uV is enough for fixed regulator,
> remove the redundant .min_uV and .list_voltage settings.
>
> Signed-off-by: Axel Lin
Hi Axel,
Acked-by: Fabrice Gasnier
Thanks,
Fabrice
> ---
> drivers/regulator/s
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