On 10/17/2017 6:29 AM, Bjorn Andersson wrote:
On Thu 12 Oct 23:15 PDT 2017, fengl...@codeaurora.org wrote:
From: Fenglin Wu <fengl...@codeaurora.org>
The initial value of is_enabled flag is read out from hardware in
pmic_gpio_populate(), and it will be set in pmic_gpio_config_set() if
p
On 10/17/2017 6:29 AM, Bjorn Andersson wrote:
On Thu 12 Oct 23:15 PDT 2017, fengl...@codeaurora.org wrote:
From: Fenglin Wu
The initial value of is_enabled flag is read out from hardware in
pmic_gpio_populate(), and it will be set in pmic_gpio_config_set() if
pinconf is defined. For any
On 10/9/2017 1:56 PM, Bjorn Andersson wrote:
On Sun 08 Oct 22:34 PDT 2017, Fenglin Wu wrote:
On 10/6/2017 12:27 AM, Bjorn Andersson wrote:
On Mon 11 Sep 17:32 PDT 2017, fengl...@codeaurora.org wrote:
From: Fenglin Wu <fengl...@codeaurora.org>
GPIO is expected to be disabl
On 10/9/2017 1:56 PM, Bjorn Andersson wrote:
On Sun 08 Oct 22:34 PDT 2017, Fenglin Wu wrote:
On 10/6/2017 12:27 AM, Bjorn Andersson wrote:
On Mon 11 Sep 17:32 PDT 2017, fengl...@codeaurora.org wrote:
From: Fenglin Wu
GPIO is expected to be disabled iff PIN_CONFIG_BIAS_HIGH_IMPEDANCE
On 10/6/2017 12:27 AM, Bjorn Andersson wrote:
On Mon 11 Sep 17:32 PDT 2017, fengl...@codeaurora.org wrote:
From: Fenglin Wu <fengl...@codeaurora.org>
GPIO is expected to be disabled iff PIN_CONFIG_BIAS_HIGH_IMPEDANCE is
configured. Update is_enabled flag in config_set() so that it can
r
On 10/6/2017 12:27 AM, Bjorn Andersson wrote:
On Mon 11 Sep 17:32 PDT 2017, fengl...@codeaurora.org wrote:
From: Fenglin Wu
GPIO is expected to be disabled iff PIN_CONFIG_BIAS_HIGH_IMPEDANCE is
configured. Update is_enabled flag in config_set() so that it can
reflect GPIO status correctly
On 8/29/2017 9:51 AM, Shawn Guo wrote:
On Tue, Aug 29, 2017 at 09:03:02AM +0800, Fenglin Wu wrote:
I agree the GPIO's ownership is configurable and it always configured at
the very beginning of the device boot up which is not visible by linux
kernel drivers/image. Normally, this configuration
On 8/29/2017 9:51 AM, Shawn Guo wrote:
On Tue, Aug 29, 2017 at 09:03:02AM +0800, Fenglin Wu wrote:
I agree the GPIO's ownership is configurable and it always configured at
the very beginning of the device boot up which is not visible by linux
kernel drivers/image. Normally, this configuration
On 8/28/2017 10:54 PM, Shawn Guo wrote:
On Wed, Jul 19, 2017 at 03:17:07PM +0800, fengl...@codeaurora.org wrote:
From: Fenglin Wu <fengl...@codeaurora.org>
Add support for qcom,gpios-disallowed property which is used to exclude
PMIC GPIOs not owned by the APSS processor from the pinctrl
On 8/28/2017 10:54 PM, Shawn Guo wrote:
On Wed, Jul 19, 2017 at 03:17:07PM +0800, fengl...@codeaurora.org wrote:
From: Fenglin Wu
Add support for qcom,gpios-disallowed property which is used to exclude
PMIC GPIOs not owned by the APSS processor from the pinctrl device.
If I understand
On 8/22/2017 4:55 PM, Shawn Guo wrote:
On Mon, Aug 21, 2017 at 04:18:58PM -0700, Stephen Boyd wrote:
On 08/18/2017 08:28 AM, Kiran Gunda wrote:
The peripheral ownership check is not necessary on single master
platforms. Hence, enforce the peripheral ownership check optionally.
Signed-off-by:
On 8/22/2017 4:55 PM, Shawn Guo wrote:
On Mon, Aug 21, 2017 at 04:18:58PM -0700, Stephen Boyd wrote:
On 08/18/2017 08:28 AM, Kiran Gunda wrote:
The peripheral ownership check is not necessary on single master
platforms. Hence, enforce the peripheral ownership check optionally.
Signed-off-by:
On 7/25/2017 3:09 AM, Rob Herring wrote:
+ Definition: Array of the GPIO hardware numbers corresponding to GPIOs
+ which the APSS processor is not allowed to configure.
+ The hardware numbers are indexed from 1.
+ The interrupt
On 7/25/2017 3:09 AM, Rob Herring wrote:
+ Definition: Array of the GPIO hardware numbers corresponding to GPIOs
+ which the APSS processor is not allowed to configure.
+ The hardware numbers are indexed from 1.
+ The interrupt
On 7/13/2017 5:33 AM, Bjorn Andersson wrote:
On Mon 12 Jun 23:16 PDT 2017, fengl...@codeaurora.org wrote:
From: Fenglin Wu <fengl...@codeaurora.org>
Power source selection in DIG_VIN_CTL is indexed from 0, in the range
check it shouldn't be equal to the total number of power sources.
On 7/13/2017 5:33 AM, Bjorn Andersson wrote:
On Mon 12 Jun 23:16 PDT 2017, fengl...@codeaurora.org wrote:
From: Fenglin Wu
Power source selection in DIG_VIN_CTL is indexed from 0, in the range
check it shouldn't be equal to the total number of power sources.
Signed-off-by: Fenglin Wu
On 7/13/2017 5:24 AM, Bjorn Andersson wrote:
On Mon 12 Jun 23:16 PDT 2017, fengl...@codeaurora.org wrote:
From: Fenglin Wu <fengl...@codeaurora.org>
Add property "qcom,dtest-buffer" to specify which dtest rail to feed
when the pin is configured as a digital input.
Signed-of
On 7/13/2017 5:24 AM, Bjorn Andersson wrote:
On Mon 12 Jun 23:16 PDT 2017, fengl...@codeaurora.org wrote:
From: Fenglin Wu
Add property "qcom,dtest-buffer" to specify which dtest rail to feed
when the pin is configured as a digital input.
Signed-off-by: Fenglin Wu
---
.../
On 7/13/2017 4:55 AM, Bjorn Andersson wrote:
On Mon 12 Jun 23:16 PDT 2017, fengl...@codeaurora.org wrote:
From: Fenglin Wu <fengl...@codeaurora.org>
GPIO LV (low voltage)/MV (medium voltage) subtypes have different
features and register mappings than 4CH/8CH subtypes. Add support
On 7/13/2017 4:55 AM, Bjorn Andersson wrote:
On Mon 12 Jun 23:16 PDT 2017, fengl...@codeaurora.org wrote:
From: Fenglin Wu
GPIO LV (low voltage)/MV (medium voltage) subtypes have different
features and register mappings than 4CH/8CH subtypes. Add support
for LV and MV subtypes.
Signed-off
englin Wu <fengl...@codeaurora.org>
GPIO LV (low voltage)/MV (medium voltage) subtypes have different
features and register mappings than 4CH/8CH subtypes. Add support
for LV and MV subtypes.
Signed-off-by: Fenglin Wu <fengl...@codeaurora.org>
---
.../devicetree/bindings/pinctrl/qcom,p
Hi Bjorn and Ivan,
Could you help to take some time to look at these spmi-gpio pinctrl
patches?
Thanks.
On 6/20/2017 7:15 PM, Linus Walleij wrote:
Bjrön and/or Ivan: please look at this.
Yours,
Linus Walleij
On Tue, Jun 13, 2017 at 8:16 AM, wrote:
From: Fenglin Wu
GPIO LV (low voltage
On 6/19/2017 9:00 AM, Fenglin Wu wrote:
On 6/18/2017 10:04 PM, Rob Herring wrote:
On Tue, Jun 13, 2017 at 02:16:03PM +0800, fengl...@codeaurora.org wrote:
From: Fenglin Wu <fengl...@codeaurora.org>
GPIO LV (low voltage)/MV (medium voltage) subtypes have different
features and re
On 6/19/2017 9:00 AM, Fenglin Wu wrote:
On 6/18/2017 10:04 PM, Rob Herring wrote:
On Tue, Jun 13, 2017 at 02:16:03PM +0800, fengl...@codeaurora.org wrote:
From: Fenglin Wu
GPIO LV (low voltage)/MV (medium voltage) subtypes have different
features and register mappings than 4CH/8CH subtypes
On 6/18/2017 10:04 PM, Rob Herring wrote:
On Tue, Jun 13, 2017 at 02:16:03PM +0800, fengl...@codeaurora.org wrote:
From: Fenglin Wu <fengl...@codeaurora.org>
GPIO LV (low voltage)/MV (medium voltage) subtypes have different
features and register mappings than 4CH/8CH subtypes. Add s
On 6/18/2017 10:04 PM, Rob Herring wrote:
On Tue, Jun 13, 2017 at 02:16:03PM +0800, fengl...@codeaurora.org wrote:
From: Fenglin Wu
GPIO LV (low voltage)/MV (medium voltage) subtypes have different
features and register mappings than 4CH/8CH subtypes. Add support
for LV and MV subtypes
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