Re: [PATCH 00/31] Introduce devm_pm_opp_* API
HI, On Sun, Jan 3, 2021 at 8:52 PM Dmitry Osipenko wrote: > > 01.01.2021 19:54, Yangtao Li пишет: > > Hi, > > > > This patchset add devm_pm_opp_set_clkname, devm_pm_opp_put_clkname, > > devm_pm_opp_set_regulators, devm_pm_opp_put_regulators, > > devm_pm_opp_set_supported_hw, devm_pm_opp_of_add_table and > > devm_pm_opp_register_notifier. > > > > Yangtao Li (31): > > opp: Add devres wrapper for dev_pm_opp_set_clkname and > > dev_pm_opp_put_clkname > > opp: Add devres wrapper for dev_pm_opp_set_regulators and > > dev_pm_opp_put_regulators > > opp: Add devres wrapper for dev_pm_opp_set_supported_hw > > opp: Add devres wrapper for dev_pm_opp_of_add_table > > opp: Add devres wrapper for dev_pm_opp_register_notifier > > serial: qcom_geni_serial: fix potential mem leak in > > qcom_geni_serial_probe() > > serial: qcom_geni_serial: convert to use devm_pm_opp_* API > > spi: spi-qcom-qspi: fix potential mem leak in spi_geni_probe() > > spi: spi-qcom-qspi: fix potential mem leak in spi_geni_probe() > > qcom-geni-se: remove opp_table > > mmc: sdhci-msm: fix potential mem leak in sdhci_msm_probe() > > mmc: sdhci-msm: convert to use devm_pm_opp_* API > > spi: spi-qcom-qspi: fix potential mem leak in qcom_qspi_probe() > > spi: spi-qcom-qspi: convert to use devm_pm_opp_* API > > drm/msm: fix potential mem leak > > drm/msm: convert to use devm_pm_opp_* API and remove dp_ctrl_put > > drm/lima: convert to use devm_pm_opp_* API > > drm/lima: remove unneeded devm_devfreq_remove_device() > > drm/panfrost: convert to use devm_pm_opp_* API > > media: venus: fix error check in core_get_v4() > > media: venus: convert to use devm_pm_opp_* API > > memory: samsung: exynos5422-dmc: fix return error in > > exynos5_init_freq_table > > memory: samsung: exynos5422-dmc: convert to use devm_pm_opp_* API > > memory: tegra20: convert to use devm_pm_opp_* API > > memory: tegra30: convert to use devm_pm_opp_* API > > PM / devfreq: tegra30: convert to use devm_pm_opp_* API > > PM / devfreq: rk3399_dmc: convert to use devm_pm_opp_* API > > PM / devfreq: imx8m-ddrc: convert to use devm_pm_opp_* API > > PM / devfreq: imx-bus: convert to use devm_pm_opp_* API > > PM / devfreq: exynos: convert to use devm_pm_opp_* API > > PM / devfreq: convert to devm_pm_opp_register_notifier and remove > > unused API > > > > drivers/devfreq/devfreq.c | 66 +-- > > drivers/devfreq/exynos-bus.c | 42 + > > drivers/devfreq/imx-bus.c | 14 +- > > drivers/devfreq/imx8m-ddrc.c | 15 +- > > drivers/devfreq/rk3399_dmc.c | 22 +-- > > drivers/devfreq/tegra30-devfreq.c | 21 +-- > > drivers/gpu/drm/lima/lima_devfreq.c | 45 + > > drivers/gpu/drm/lima/lima_devfreq.h | 2 - > > drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 2 +- > > drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 2 +- > > drivers/gpu/drm/msm/adreno/adreno_gpu.c | 2 +- > > drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 31 ++-- > > drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 2 - > > drivers/gpu/drm/msm/dp/dp_ctrl.c | 29 +-- > > drivers/gpu/drm/msm/dp/dp_ctrl.h | 1 - > > drivers/gpu/drm/msm/dp/dp_display.c | 5 +- > > drivers/gpu/drm/msm/dsi/dsi_host.c| 23 ++- > > drivers/gpu/drm/panfrost/panfrost_devfreq.c | 34 +--- > > drivers/gpu/drm/panfrost/panfrost_devfreq.h | 1 - > > .../media/platform/qcom/venus/pm_helpers.c| 22 +-- > > drivers/memory/samsung/exynos5422-dmc.c | 13 +- > > drivers/memory/tegra/tegra20-emc.c| 29 +-- > > drivers/memory/tegra/tegra30-emc.c| 29 +-- > > drivers/mmc/host/sdhci-msm.c | 27 ++- > > drivers/opp/core.c| 173 ++ > > drivers/opp/of.c | 36 > > drivers/spi/spi-geni-qcom.c | 23 ++- > > drivers/spi/spi-qcom-qspi.c | 25 ++- > > drivers/tty/serial/qcom_geni_serial.c | 31 ++-- > > include/linux/devfreq.h | 23 --- > > include/linux/pm_opp.h| 38 > > include/linux/qcom-geni-se.h | 2 - > > 32 files changed, 402 insertions(+), 428 deletions(-) > > > > Hello, > > Could you please add helper for dev_pm_opp_attach_genpd() and make > cpufreq drivers to use the helpers? Thank you for reminding me. But we shouldn't use this for CPU devices as the CPU device doesn't get bound to a driver, it is rather a fake platform device which gets the cpufreq drivers probed. > > I'd also like to see a devm helper for > dev_pm_opp_register_set_opp_helper(), which should become useful for > Tegra drivers sometime soon. For non-cpu devices? BR / Yangtao
Re: [PATCH 1/2] cpufreq: sun50i: add a100 cpufreq support
HI Maxime, Any comment? BR / Yangtao
Re: [PATCH 2/2] arm64: dts: allwinner: a100: Add CPU Operating Performance Points table
HI shuosheng,
On Fri, Dec 4, 2020 at 3:11 PM Shuosheng Huang
wrote:
>
> Add an Operating Performance Points table for the CPU cores to
> enable Dynamic Voltage & Frequency Scaling on the A100.
>
> Signed-off-by: Shuosheng Huang
> ---
> .../allwinner/sun50i-a100-allwinner-perf1.dts | 5 ++
> .../dts/allwinner/sun50i-a100-cpu-opp.dtsi| 90 +++
> .../arm64/boot/dts/allwinner/sun50i-a100.dtsi | 8 ++
> 3 files changed, 103 insertions(+)
> create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
> b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
> index d34c2bb1079f..7c579923f973 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
> @@ -6,6 +6,7 @@
> /dts-v1/;
>
> #include "sun50i-a100.dtsi"
> +#include "sun50i-a100-cpu-opp.dtsi"
>
> /{
> model = "Allwinner A100 Perf1";
> @@ -20,6 +21,10 @@ chosen {
> };
> };
>
> + {
> + cpu-supply = <_dcdc2>;
> +};
> +
> {
> vcc-pb-supply = <_dcdc1>;
> vcc-pc-supply = <_eldo1>;
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi
> b/arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi
> new file mode 100644
> index ..bc8ceaa38392
> --- /dev/null
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi
> @@ -0,0 +1,90 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +// Copyright (c) 2020 Yangtao Li
> +// Copyright (c) 2020 ShuoSheng Huang
> +
> +/ {
> + cpu_opp_table: cpu-opp-table {
> + compatible = "allwinner,sun50i-h6-operating-points";
> + nvmem-cells = <_speed_grade>;
> + opp-shared;
> +
> + opp@40800 {
> + clock-latency-ns = <244144>; /* 8 32k periods */
> + opp-hz = /bits/ 64 <40800>;
> +
> + opp-microvolt-speed0 = <90 90 120>;
> + opp-microvolt-speed0 = <90 90 120>;
> + opp-microvolt-speed0 = <90 90 120>;
> + };
This should be opp-microvolt-speed0, opp-microvolt-speed1 and
opp-microvolt-speed2.
You may have problems with the replacement when forming the patch.
The following also needs to be modified.
Yangtao
Re: [PATCH 3/3] phy: sun4i-usb: Use power efficient workqueue for debounce and poll
HI, On Wed, Nov 11, 2020 at 11:44 AM Samuel Holland wrote: > > On 11/9/20 6:12 AM, Frank Lee wrote: > > From: Yangtao Li > > > > The debounce and poll time is generally quite long and the work not > > performance critical so allow the scheduler to run the work anywhere > > rather than in the normal per-CPU workqueue. > > > > Signed-off-by: Yangtao Li > > --- > > drivers/phy/allwinner/phy-sun4i-usb.c | 14 +++--- > > 1 file changed, 7 insertions(+), 7 deletions(-) > > > > diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c > > b/drivers/phy/allwinner/phy-sun4i-usb.c > > index 651d5e2a25ce..4787ad13b255 100644 > > --- a/drivers/phy/allwinner/phy-sun4i-usb.c > > +++ b/drivers/phy/allwinner/phy-sun4i-usb.c > > @@ -326,7 +326,7 @@ static int sun4i_usb_phy_init(struct phy *_phy) > > /* Force ISCR and cable state updates */ > > data->id_det = -1; > > data->vbus_det = -1; > > - queue_delayed_work(system_wq, >detect, 0); > > + queue_delayed_work(system_power_efficient_wq, >detect, > > 0); > > } > > > > return 0; > > @@ -444,7 +444,7 @@ static int sun4i_usb_phy_power_on(struct phy *_phy) > > > > /* We must report Vbus high within OTG_TIME_A_WAIT_VRISE msec. */ > > This doesn't sound like "not performance critical" to me. My understanding is > the debouncing has a deadline from the USB spec. Maybe this is more flexible > than the comment makes it sound? According to my understanding, the more meaning of performance here comes from cache locality.
Re: [PATCH 00/19] Second step support for A100
On Tue, Nov 10, 2020 at 4:43 PM Krzysztof Kozlowski wrote: > > On Tue, 10 Nov 2020 at 07:00, Frank Lee wrote: > > > > It seems that sending too many e-mails at one time will cause some > > emails to fail to be sent out. I will try again. > > Hi, > > Instead please reduce the address list to relevant people, as pointed > out by scripts/get_maintainer.pl. Don't Cc irrelevant developers > unless a file is abandoned and you need to get as much audience as > possible... but sunxi is not abandoned. Thank you for the reminder. I resend the version in the afternoon, only CC the relevant people. I'm not sure. Should the cover be copied to everyone? Yangtao
[PATCH] MAINTAINERS: Add myself as arm sunxi soc maintainer
From: Yangtao Li Add myself to sunxi maintainer so the mail can cc me. Signed-off-by: Yangtao Li --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 94ac10a153c7..0ddaf9641546 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1545,6 +1545,7 @@ F:drivers/clk/sunxi/ ARM/Allwinner sunXi SoC support M: Maxime Ripard +M: Yangtao Li M: Chen-Yu Tsai L: linux-arm-ker...@lists.infradead.org (moderated for non-subscribers) S: Maintained -- 2.28.0
[RESEND PATCH 18/19] arm64: allwinner: a100: Add MMC related nodes
From: Yangtao Li
The A100 has 3 MMC controllers, one of them being especially targeted to
eMMC. Let's add nodes on dts.
Signed-off-by: Yangtao Li
---
.../arm64/boot/dts/allwinner/sun50i-a100.dtsi | 71 +++
1 file changed, 71 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
index c731bb9727c2..4adfc7d4854a 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
@@ -169,12 +169,83 @@ pio: pinctrl@300b000 {
interrupt-controller;
#interrupt-cells = <3>;
+ mmc0_pins: mmc0-pins {
+ pins = "PF0", "PF1", "PF2", "PF3",
+ "PF4", "PF5";
+ function = "mmc0";
+ drive-strength = <30>;
+ bias-pull-up;
+ };
+
+ /omit-if-no-ref/
+ mmc1_pins: mmc1-pins {
+ pins = "PG0", "PG1", "PG2", "PG3",
+ "PG4", "PG5";
+ function = "mmc1";
+ drive-strength = <30>;
+ bias-pull-up;
+ };
+
+ mmc2_pins: mmc2-pins {
+ pins = "PC0", "PC1", "PC5", "PC6",
+ "PC8", "PC9", "PC10", "PC11",
+ "PC13", "PC14", "PC15", "PC16";
+ function = "mmc2";
+ drive-strength = <30>;
+ bias-pull-up;
+ };
+
uart0_pb_pins: uart0-pb-pins {
pins = "PB9", "PB10";
function = "uart0";
};
};
+ mmc0: mmc@402 {
+ compatible = "allwinner,sun50i-a100-mmc";
+ reg = <0x0402 0x1000>;
+ clocks = < CLK_BUS_MMC0>, < CLK_MMC0>;
+ clock-names = "ahb", "mmc";
+ resets = < RST_BUS_MMC0>;
+ reset-names = "ahb";
+ interrupts = ;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc1: mmc@4021000 {
+ compatible = "allwinner,sun50i-a100-mmc";
+ reg = <0x04021000 0x1000>;
+ clocks = < CLK_BUS_MMC1>, < CLK_MMC1>;
+ clock-names = "ahb", "mmc";
+ resets = < RST_BUS_MMC1>;
+ reset-names = "ahb";
+ interrupts = ;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc2: mmc@4022000 {
+ compatible = "allwinner,sun50i-a100-emmc";
+ reg = <0x04022000 0x1000>;
+ clocks = < CLK_BUS_MMC2>, < CLK_MMC2>;
+ clock-names = "ahb", "mmc";
+ resets = < RST_BUS_MMC2>;
+ reset-names = "ahb";
+ interrupts = ;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
uart0: serial@500 {
compatible = "snps,dw-apb-uart";
reg = <0x0500 0x400>;
--
2.28.0
[RESEND PATCH 19/19] arm64: dts: allwinner: a100: perf1: Add eMMC and MMC node
From: Yangtao Li
A100 perf1 hava MicroSD slot and on-board eMMC module, add support for them.
Signed-off-by: Yangtao Li
---
.../allwinner/sun50i-a100-allwinner-perf1.dts| 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
index ef205c9b8ff4..d102c50ff7c1 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
@@ -39,6 +39,22 @@ {
status = "okay";
};
+ {
+ vmmc-supply = <_dcdc1>;
+ cd-gpios = < 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ bus-width = <4>;
+ status = "okay";
+};
+
+ {
+ vmmc-supply = <_dcdc1>;
+ vqmmc-supply = <_aldo1>;
+ cap-mmc-hw-reset;
+ non-removable;
+ bus-width = <8>;
+ status = "okay";
+};
+
{
status = "okay";
};
--
2.28.0
[RESEND PATCH 17/19] mmc: sunxi: add support for A100 mmc controller
From: Yangtao Li
This patch adds support for A100 MMC controller, which use word address
for internal dma.
Signed-off-by: Yangtao Li
---
drivers/mmc/host/sunxi-mmc.c | 28 +---
1 file changed, 25 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
index fc62773602ec..1518b64112b7 100644
--- a/drivers/mmc/host/sunxi-mmc.c
+++ b/drivers/mmc/host/sunxi-mmc.c
@@ -244,6 +244,7 @@ struct sunxi_idma_des {
struct sunxi_mmc_cfg {
u32 idma_des_size_bits;
+ u32 idma_des_shift;
const struct sunxi_mmc_clk_delay *clk_delays;
/* does the IP block support autocalibration? */
@@ -343,7 +344,7 @@ static int sunxi_mmc_init_host(struct sunxi_mmc_host *host)
/* Enable CEATA support */
mmc_writel(host, REG_FUNS, SDXC_CEATA_ON);
/* Set DMA descriptor list base address */
- mmc_writel(host, REG_DLBA, host->sg_dma);
+ mmc_writel(host, REG_DLBA, host->sg_dma >> host->cfg->idma_des_shift);
rval = mmc_readl(host, REG_GCTRL);
rval |= SDXC_INTERRUPT_ENABLE_BIT;
@@ -373,8 +374,10 @@ static void sunxi_mmc_init_idma_des(struct sunxi_mmc_host
*host,
next_desc += sizeof(struct sunxi_idma_des);
pdes[i].buf_addr_ptr1 =
- cpu_to_le32(sg_dma_address(>sg[i]));
- pdes[i].buf_addr_ptr2 = cpu_to_le32((u32)next_desc);
+ cpu_to_le32(sg_dma_address(>sg[i]) >>
+ host->cfg->idma_des_shift);
+ pdes[i].buf_addr_ptr2 = cpu_to_le32((u32)next_desc >>
+ host->cfg->idma_des_shift);
}
pdes[0].config |= cpu_to_le32(SDXC_IDMAC_DES0_FD);
@@ -1178,6 +1181,23 @@ static const struct sunxi_mmc_cfg sun50i_a64_emmc_cfg = {
.needs_new_timings = true,
};
+static const struct sunxi_mmc_cfg sun50i_a100_cfg = {
+ .idma_des_size_bits = 16,
+ .idma_des_shift = 2,
+ .clk_delays = NULL,
+ .can_calibrate = true,
+ .mask_data0 = true,
+ .needs_new_timings = true,
+};
+
+static const struct sunxi_mmc_cfg sun50i_a100_emmc_cfg = {
+ .idma_des_size_bits = 13,
+ .idma_des_shift = 2,
+ .clk_delays = NULL,
+ .can_calibrate = true,
+ .needs_new_timings = true,
+};
+
static const struct of_device_id sunxi_mmc_of_match[] = {
{ .compatible = "allwinner,sun4i-a10-mmc", .data = _a10_cfg },
{ .compatible = "allwinner,sun5i-a13-mmc", .data = _a13_cfg },
@@ -1186,6 +1206,8 @@ static const struct of_device_id sunxi_mmc_of_match[] = {
{ .compatible = "allwinner,sun9i-a80-mmc", .data = _a80_cfg },
{ .compatible = "allwinner,sun50i-a64-mmc", .data = _a64_cfg },
{ .compatible = "allwinner,sun50i-a64-emmc", .data =
_a64_emmc_cfg },
+ { .compatible = "allwinner,sun50i-a100-mmc", .data = _a100_cfg },
+ { .compatible = "allwinner,sun50i-a100-emmc", .data =
_a100_emmc_cfg },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, sunxi_mmc_of_match);
--
2.28.0
[RESEND PATCH 16/19] dt-bindings: mmc: sunxi: Add A100 compatibles
From: Yangtao Li Add binding for A100's mmc and emmc controller. Signed-off-by: Yangtao Li --- .../devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml| 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml b/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml index e82c9a07b6fb..41821f14ecaa 100644 --- a/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml +++ b/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml @@ -26,6 +26,8 @@ properties: - const: allwinner,sun9i-a80-mmc - const: allwinner,sun50i-a64-emmc - const: allwinner,sun50i-a64-mmc + - const: allwinner,sun50i-a100-emmc + - const: allwinner,sun50i-a100-mmc - items: - const: allwinner,sun8i-a83t-mmc - const: allwinner,sun7i-a20-mmc -- 2.28.0
[RESEND PATCH 15/19] arm64: allwinner: A100: enable EHCI, OHCI and USB PHY nodes in Perf1
From: Yangtao Li
Add USB support on A100 perf1 board, which include two USB2.0 port.
Signed-off-by: Yangtao Li
---
.../allwinner/sun50i-a100-allwinner-perf1.dts | 38 +++
1 file changed, 38 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
index d34c2bb1079f..ef205c9b8ff4 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
@@ -7,6 +7,8 @@
#include "sun50i-a100.dtsi"
+#include
+
/{
model = "Allwinner A100 Perf1";
compatible = "allwinner,a100-perf1", "allwinner,sun50i-a100";
@@ -18,6 +20,35 @@ aliases {
chosen {
stdout-path = "serial0:115200n8";
};
+
+ reg_usb1_vbus: usb1-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb1-vbus";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ gpio = < 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */
+ enable-active-high;
+ };
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+_otg {
+ status = "okay";
};
{
@@ -178,3 +209,10 @@ {
pinctrl-0 = <_pb_pins>;
status = "okay";
};
+
+ {
+ usb0_id_det-gpios = < 7 8 GPIO_ACTIVE_HIGH>; /* PH8 */
+ usb0_vbus-supply = <_drivevbus>;
+ usb1_vbus-supply = <_usb1_vbus>;
+ status = "okay";
+};
--
2.28.0
[RESEND PATCH 14/19] arm64: dts: allwinner: a100: add usb related nodes
From: Yangtao Li
Allwinner A64 have two HCI USB controllers, a OTG controller and a USB
PHY device, let's add nodes on dts.
Signed-off-by: Yangtao Li
---
.../arm64/boot/dts/allwinner/sun50i-a100.dtsi | 91 +++
1 file changed, 91 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
index 6aa3337ce0e9..c731bb9727c2 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
@@ -290,6 +290,97 @@ ths: thermal-sensor@5070400 {
#thermal-sensor-cells = <1>;
};
+ usbphy: phy@5100400 {
+ #phy-cells = <1>;
+ compatible = "allwinner,sun50i-a100-usb-phy";
+ reg = <0x05100400 0x14>,
+ <0x05101800 0x4>,
+ <0x05200800 0x4>;
+ reg-names = "phy_ctrl",
+ "pmu0",
+ "pmu1";
+ clocks = < CLK_USB_PHY0>,
+< CLK_USB_PHY1>;
+ clock-names = "usb0_phy",
+ "usb1_phy";
+ resets = < RST_USB_PHY0>,
+< RST_USB_PHY1>;
+ reset-names = "usb0_reset",
+ "usb1_reset";
+ status = "disabled";
+ };
+
+ ehci0: usb@5101000 {
+ compatible = "allwinner,sun50i-a100-ehci",
+"generic-ehci";
+ reg = <0x05101000 0x100>;
+ interrupts = ;
+ clocks = < CLK_BUS_OHCI0>,
+< CLK_BUS_EHCI0>,
+< CLK_USB_OHCI0>;
+ resets = < RST_BUS_OHCI0>,
+< RST_BUS_EHCI0>;
+ phys = < 0>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci0: usb@5101400 {
+ compatible = "allwinner,sun50i-a100-ohci",
+"generic-ohci";
+ reg = <0x05101400 0x100>;
+ interrupts = ;
+ clocks = < CLK_BUS_OHCI0>,
+< CLK_USB_OHCI0>;
+ resets = < RST_BUS_OHCI0>;
+ phys = < 0>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ usb_otg: usb@510 {
+ compatible = "allwinner,sun50i-a100-musb",
+"allwinner,sun8i-h3-musb";
+ reg = <0x0510 0x0400>;
+ clocks = < CLK_BUS_OTG>;
+ resets = < RST_BUS_OTG>;
+ interrupts = ;
+ interrupt-names = "mc";
+ phys = < 0>;
+ phy-names = "usb";
+ extcon = < 0>;
+ dr_mode = "otg";
+ status = "disabled";
+ };
+
+ ehci1: usb@520 {
+ compatible = "allwinner,sun50i-a100-ehci",
+"generic-ehci";
+ reg = <0x0520 0x100>;
+ interrupts = ;
+ clocks = < CLK_BUS_OHCI1>,
+< CLK_BUS_EHCI1>,
+< CLK_USB_OHCI1>;
+ resets = < RST_BUS_OHCI1>,
+< RST_BUS_EHCI1>;
+ phys = < 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci1: usb@5200400 {
+ compatible = "allwinner,sun50i-a100-ohci",
+"generic-ohci";
+ reg = <0x05200400 0x100>;
+ interrupts = ;
+ clocks = < CLK_BUS_OHCI1>,
+< CLK_USB_OHCI1>;
+ resets = < RST_BUS_OHCI1>;
+ phys = < 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
r_ccu: clock@701 {
compatible = "allwinner,sun50i-a100-r-ccu";
reg = <0x0701 0x300>;
--
2.28.0
[RESEND PATCH 13/19] phy: sun4i-usb: add support for A100 USB PHY
From: Yangtao Li
Add support for a100's usb phy, which with 2 PHYs.
Signed-off-by: Yangtao Li
---
drivers/phy/allwinner/phy-sun4i-usb.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c
b/drivers/phy/allwinner/phy-sun4i-usb.c
index a6900495baa5..1a0e403131e7 100644
--- a/drivers/phy/allwinner/phy-sun4i-usb.c
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
@@ -107,6 +107,7 @@ enum sun4i_usb_phy_type {
sun8i_r40_phy,
sun8i_v3s_phy,
sun50i_a64_phy,
+ sun50i_a100_phy,
sun50i_h6_phy,
};
@@ -289,7 +290,13 @@ static int sun4i_usb_phy_init(struct phy *_phy)
}
if (data->cfg->type == sun8i_a83t_phy ||
+ data->cfg->type == sun50i_a100_phy ||
data->cfg->type == sun50i_h6_phy) {
+ if (phy->pmu && data->cfg->enable_pmu_unk1) {
+ val = readl(phy->pmu + REG_PMU_UNK1);
+ writel(val & ~BIT(3), phy->pmu + REG_PMU_UNK1);
+ }
+
if (phy->index == 0) {
val = readl(data->base + data->cfg->phyctl_offset);
val |= PHY_CTL_VBUSVLDEXT;
@@ -339,6 +346,7 @@ static int sun4i_usb_phy_exit(struct phy *_phy)
if (phy->index == 0) {
if (data->cfg->type == sun8i_a83t_phy ||
+ data->cfg->type == sun50i_a100_phy ||
data->cfg->type == sun50i_h6_phy) {
void __iomem *phyctl = data->base +
data->cfg->phyctl_offset;
@@ -960,6 +968,16 @@ static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = {
.phy0_dual_route = true,
};
+static const struct sun4i_usb_phy_cfg sun50i_a100_cfg = {
+ .num_phys = 2,
+ .type = sun50i_a100_phy,
+ .disc_thresh = 3,
+ .phyctl_offset = REG_PHYCTL_A33,
+ .dedicated_clocks = true,
+ .enable_pmu_unk1 = true,
+ .phy0_dual_route = true,
+};
+
static const struct sun4i_usb_phy_cfg sun50i_h6_cfg = {
.num_phys = 4,
.type = sun50i_h6_phy,
@@ -983,6 +1001,7 @@ static const struct of_device_id sun4i_usb_phy_of_match[]
= {
{ .compatible = "allwinner,sun8i-v3s-usb-phy", .data = _v3s_cfg },
{ .compatible = "allwinner,sun50i-a64-usb-phy",
.data = _a64_cfg},
+ { .compatible = "allwinner,sun50i-a100-usb-phy", .data =
_a100_cfg },
{ .compatible = "allwinner,sun50i-h6-usb-phy", .data = _h6_cfg },
{ },
};
--
2.28.0
[RESEND PATCH 12/19] dt-bindings: Add bindings for USB phy on Allwinner A100
From: Yangtao Li
Add a device tree binding for the A100's USB PHY.
Signed-off-by: Yangtao Li
---
.../phy/allwinner,sun50i-a100-usb-phy.yaml| 105 ++
1 file changed, 105 insertions(+)
create mode 100644
Documentation/devicetree/bindings/phy/allwinner,sun50i-a100-usb-phy.yaml
diff --git
a/Documentation/devicetree/bindings/phy/allwinner,sun50i-a100-usb-phy.yaml
b/Documentation/devicetree/bindings/phy/allwinner,sun50i-a100-usb-phy.yaml
new file mode 100644
index ..cc9bbebe2bd7
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/allwinner,sun50i-a100-usb-phy.yaml
@@ -0,0 +1,105 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/allwinner,sun50i-a100-usb-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Allwinner A100 USB PHY Device Tree Bindings
+
+maintainers:
+ - Yangtao Li
+
+properties:
+ "#phy-cells":
+const: 1
+
+ compatible:
+const: allwinner,sun50i-a100-usb-phy
+
+ reg:
+items:
+ - description: PHY Control registers
+ - description: PHY PMU0 registers
+ - description: PHY PMU1 registers
+
+ reg-names:
+items:
+ - const: phy_ctrl
+ - const: pmu0
+ - const: pmu1
+
+ clocks:
+items:
+ - description: USB OTG PHY bus clock
+ - description: USB Host 0 PHY bus clock
+
+ clock-names:
+items:
+ - const: usb0_phy
+ - const: usb1_phy
+
+ resets:
+items:
+ - description: USB OTG reset
+ - description: USB Host 1 Controller reset
+
+ reset-names:
+items:
+ - const: usb0_reset
+ - const: usb1_reset
+
+ usb0_id_det-gpios:
+description: GPIO to the USB OTG ID pin
+
+ usb0_vbus_det-gpios:
+description: GPIO to the USB OTG VBUS detect pin
+
+ usb0_vbus_power-supply:
+description: Power supply to detect the USB OTG VBUS
+
+ usb0_vbus-supply:
+description: Regulator controlling USB OTG VBUS
+
+ usb1_vbus-supply:
+description: Regulator controlling USB1 Host controller
+
+required:
+ - "#phy-cells"
+ - compatible
+ - clocks
+ - clock-names
+ - reg
+ - reg-names
+ - resets
+ - reset-names
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+#include
+#include
+
+phy@5100400 {
+#phy-cells = <1>;
+compatible = "allwinner,sun50i-a100-usb-phy";
+reg = <0x05100400 0x14>,
+ <0x05101800 0x4>,
+ <0x05200800 0x4>;
+reg-names = "phy_ctrl",
+"pmu0",
+"pmu1";
+clocks = < CLK_USB_PHY0>,
+ < CLK_USB_PHY1>;
+clock-names = "usb0_phy",
+ "usb1_phy";
+resets = < RST_USB_PHY0>,
+ < RST_USB_PHY1>;
+reset-names = "usb0_reset",
+ "usb1_reset";
+usb0_id_det-gpios = < 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */
+usb0_vbus_power-supply = <_power_supply>;
+usb0_vbus-supply = <_drivevbus>;
+usb1_vbus-supply = <_usb1_vbus>;
+};
--
2.28.0
[RESEND PATCH 11/19] arm64: dts: allwinner: a100: add watchdog node
From: Yangtao Li
Declare A100's watchdog in the device-tree.
Signed-off-by: Yangtao Li
---
arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
index 01ff53b5a7a8..6aa3337ce0e9 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
@@ -144,6 +144,14 @@ ths_calibration: calib@14 {
};
};
+ watchdog@30090a0 {
+ compatible = "allwinner,sun50i-a100-wdt",
+"allwinner,sun6i-a31-wdt";
+ reg = <0x030090a0 0x20>;
+ interrupts = ;
+ clocks = <>;
+ };
+
pio: pinctrl@300b000 {
compatible = "allwinner,sun50i-a100-pinctrl";
reg = <0x0300b000 0x400>;
--
2.28.0
[RESEND PATCH 10/19] dt-bindings: watchdog: sun4i: Add A100 compatible
From: Yangtao Li Add a binding for A100's watchdog controller. Signed-off-by: Yangtao Li --- .../devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml b/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml index e8f226376108..5ac607de8be4 100644 --- a/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml @@ -21,6 +21,9 @@ properties: - items: - const: allwinner,sun50i-a64-wdt - const: allwinner,sun6i-a31-wdt + - items: + - const: allwinner,sun50i-a100-wdt + - const: allwinner,sun6i-a31-wdt - items: - const: allwinner,sun50i-h6-wdt - const: allwinner,sun6i-a31-wdt -- 2.28.0
[RESEND PATCH 09/19] phy: allwinner: Convert to devm_platform_ioremap_* API
From: Yangtao Li
Use the devm_platform_ioremap_resource_byname() and
devm_platform_ioremap_resource helper to simplify the code.
Signed-off-by: Yangtao Li
---
drivers/phy/allwinner/phy-sun4i-usb.c | 9 +++--
drivers/phy/allwinner/phy-sun50i-usb3.c | 4 +---
drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 4 +---
drivers/phy/allwinner/phy-sun9i-usb.c | 4 +---
4 files changed, 6 insertions(+), 15 deletions(-)
diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c
b/drivers/phy/allwinner/phy-sun4i-usb.c
index 0f1888b55dbd..a6900495baa5 100644
--- a/drivers/phy/allwinner/phy-sun4i-usb.c
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
@@ -686,7 +686,6 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
struct device *dev = >dev;
struct device_node *np = dev->of_node;
struct phy_provider *phy_provider;
- struct resource *res;
int i, ret;
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
@@ -700,8 +699,7 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
if (!data->cfg)
return -EINVAL;
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy_ctrl");
- data->base = devm_ioremap_resource(dev, res);
+ data->base = devm_platform_ioremap_resource_byname(pdev, "phy_ctrl");
if (IS_ERR(data->base))
return PTR_ERR(data->base);
@@ -796,9 +794,8 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
if (i || data->cfg->phy0_dual_route) { /* No pmu for musb */
snprintf(name, sizeof(name), "pmu%d", i);
- res = platform_get_resource_byname(pdev,
- IORESOURCE_MEM, name);
- phy->pmu = devm_ioremap_resource(dev, res);
+ phy->pmu = devm_platform_ioremap_resource_byname(pdev,
+name);
if (IS_ERR(phy->pmu))
return PTR_ERR(phy->pmu);
}
diff --git a/drivers/phy/allwinner/phy-sun50i-usb3.c
b/drivers/phy/allwinner/phy-sun50i-usb3.c
index b1c04f71a31d..84055b720016 100644
--- a/drivers/phy/allwinner/phy-sun50i-usb3.c
+++ b/drivers/phy/allwinner/phy-sun50i-usb3.c
@@ -134,7 +134,6 @@ static int sun50i_usb3_phy_probe(struct platform_device
*pdev)
struct sun50i_usb3_phy *phy;
struct device *dev = >dev;
struct phy_provider *phy_provider;
- struct resource *res;
phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
if (!phy)
@@ -153,8 +152,7 @@ static int sun50i_usb3_phy_probe(struct platform_device
*pdev)
return PTR_ERR(phy->reset);
}
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- phy->regs = devm_ioremap_resource(dev, res);
+ phy->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(phy->regs))
return PTR_ERR(phy->regs);
diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
index 1fa761ba6cbb..f0bc87d654d4 100644
--- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
+++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
@@ -253,15 +253,13 @@ static int sun6i_dphy_probe(struct platform_device *pdev)
{
struct phy_provider *phy_provider;
struct sun6i_dphy *dphy;
- struct resource *res;
void __iomem *regs;
dphy = devm_kzalloc(>dev, sizeof(*dphy), GFP_KERNEL);
if (!dphy)
return -ENOMEM;
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- regs = devm_ioremap_resource(>dev, res);
+ regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(regs)) {
dev_err(>dev, "Couldn't map the DPHY encoder
registers\n");
return PTR_ERR(regs);
diff --git a/drivers/phy/allwinner/phy-sun9i-usb.c
b/drivers/phy/allwinner/phy-sun9i-usb.c
index fc6784dd7fa0..2f9e60c188b8 100644
--- a/drivers/phy/allwinner/phy-sun9i-usb.c
+++ b/drivers/phy/allwinner/phy-sun9i-usb.c
@@ -117,7 +117,6 @@ static int sun9i_usb_phy_probe(struct platform_device *pdev)
struct device *dev = >dev;
struct device_node *np = dev->of_node;
struct phy_provider *phy_provider;
- struct resource *res;
phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
if (!phy)
@@ -156,8 +155,7 @@ static int sun9i_usb_phy_probe(struct platform_device *pdev)
}
}
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- phy->pmu = devm_ioremap_resource(dev, res);
+ phy->pmu = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(phy->pmu))
return PTR_ERR(phy->pmu);
--
2.28.0
[RESEND PATCH 08/19] phy: sun4i-usb: remove enable_pmu_unk1 from sun50i_h6_cfg
From: Yangtao Li
For the current code, enable_pmu_unk1 only works in non-a83t and non-h6
types. So let's delete it from the sun50i_h6_cfg.
Signed-off-by: Yangtao Li
---
drivers/phy/allwinner/phy-sun4i-usb.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c
b/drivers/phy/allwinner/phy-sun4i-usb.c
index 651d5e2a25ce..0f1888b55dbd 100644
--- a/drivers/phy/allwinner/phy-sun4i-usb.c
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
@@ -969,7 +969,6 @@ static const struct sun4i_usb_phy_cfg sun50i_h6_cfg = {
.disc_thresh = 3,
.phyctl_offset = REG_PHYCTL_A33,
.dedicated_clocks = true,
- .enable_pmu_unk1 = true,
.phy0_dual_route = true,
.missing_phys = BIT(1) | BIT(2),
};
--
2.28.0
[RESEND PATCH 07/19] arm64: dts: allwinner: A100: Add PMU mode
From: Yangtao Li
Add the Performance Monitoring Unit (PMU) device tree node to the A100
.dtsi, which tells DT users which interrupts are triggered by PMU overflow
events on each core.
Signed-off-by: Yangtao Li
---
arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
index c34ed8045363..01ff53b5a7a8 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
@@ -25,21 +25,21 @@ cpu0: cpu@0 {
enable-method = "psci";
};
- cpu@1 {
+ cpu1: cpu@1 {
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0x1>;
enable-method = "psci";
};
- cpu@2 {
+ cpu2: cpu@2 {
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0x2>;
enable-method = "psci";
};
- cpu@3 {
+ cpu3: cpu@3 {
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0x3>;
@@ -47,6 +47,15 @@ cpu@3 {
};
};
+ pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = ,
+,
+,
+;
+ interrupt-affinity = <>, <>, <>, <>;
+ };
+
psci {
compatible = "arm,psci-1.0";
method = "smc";
--
2.28.0
[RESEND PATCH 06/19] arm64: allwinner: a100: Add device node for DMA controller
From: Yangtao Li
The A100 SoC has a DMA controller that supports 8 DMA channels
to and from various peripherals.
Add a device node for it.
Signed-off-by: Yangtao Li
---
arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
index cc321c04f121..c34ed8045363 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
@@ -101,6 +101,18 @@ ccu: clock@3001000 {
#reset-cells = <1>;
};
+ dma: dma-controller@3002000 {
+ compatible = "allwinner,sun50i-a100-dma";
+ reg = <0x03002000 0x1000>;
+ interrupts = ;
+ clocks = < CLK_BUS_DMA>, < CLK_MBUS_DMA>;
+ clock-names = "bus", "mbus";
+ dma-channels = <8>;
+ dma-requests = <51>;
+ resets = < RST_BUS_DMA>;
+ #dma-cells = <1>;
+ };
+
gic: interrupt-controller@3021000 {
compatible = "arm,gic-400";
reg = <0x03021000 0x1000>, <0x03022000 0x2000>,
--
2.28.0
[RESEND PATCH 05/19] dmaengine: sun6i: Add support for A100 DMA
From: Yangtao Li
The dma of a100 is similar to h6, with some minor changes to
support greater addressing capabilities.
Add support for it.
Signed-off-by: Yangtao Li
---
drivers/dma/sun6i-dma.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c
index f5f9c86c50bc..5cadd4d2b824 100644
--- a/drivers/dma/sun6i-dma.c
+++ b/drivers/dma/sun6i-dma.c
@@ -1173,6 +1173,30 @@ static struct sun6i_dma_config sun50i_a64_dma_cfg = {
BIT(DMA_SLAVE_BUSWIDTH_8_BYTES),
};
+/*
+ * TODO: Add support for more than 4g physical addressing.
+ *
+ * The A100 binding uses the number of dma channels from the
+ * device tree node.
+ */
+static struct sun6i_dma_config sun50i_a100_dma_cfg = {
+ .clock_autogate_enable = sun6i_enable_clock_autogate_h3,
+ .set_burst_length = sun6i_set_burst_length_h3,
+ .set_drq = sun6i_set_drq_h6,
+ .set_mode = sun6i_set_mode_h6,
+ .src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
+ .dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
+ .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
+BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
+BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
+BIT(DMA_SLAVE_BUSWIDTH_8_BYTES),
+ .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
+BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
+BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
+BIT(DMA_SLAVE_BUSWIDTH_8_BYTES),
+ .has_mbus_clk = true,
+};
+
/*
* The H6 binding uses the number of dma channels from the
* device tree node.
@@ -1225,6 +1249,7 @@ static const struct of_device_id sun6i_dma_match[] = {
{ .compatible = "allwinner,sun8i-h3-dma", .data = _h3_dma_cfg },
{ .compatible = "allwinner,sun8i-v3s-dma", .data = _v3s_dma_cfg },
{ .compatible = "allwinner,sun50i-a64-dma", .data = _a64_dma_cfg
},
+ { .compatible = "allwinner,sun50i-a100-dma", .data =
_a100_dma_cfg },
{ .compatible = "allwinner,sun50i-h6-dma", .data = _h6_dma_cfg },
{ /* sentinel */ }
};
--
2.28.0
[RESEND PATCH 04/19] dt-bindings: dma: allwinner,sun50i-a64-dma: Add A100 compatible
From: Yangtao Li Add a binding for A100's dma controller. Signed-off-by: Yangtao Li --- .../devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml| 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml b/Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml index 372679dbd216..b6e1ebfaf366 100644 --- a/Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml +++ b/Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml @@ -21,6 +21,7 @@ properties: compatible: oneOf: - const: allwinner,sun50i-a64-dma + - const: allwinner,sun50i-a100-dma - const: allwinner,sun50i-h6-dma - items: - const: allwinner,sun8i-r40-dma @@ -56,7 +57,9 @@ required: if: properties: compatible: - const: allwinner,sun50i-h6-dma + enum: +- allwinner,sun50i-a100-dma +- allwinner,sun50i-h6-dma then: properties: -- 2.28.0
[RESEND PATCH 03/19] pinctrl: sunxi: Always call chained_irq_{enter, exit} in sunxi_pinctrl_irq_handler
From: Yangtao Li
It is found on many allwinner soc that there is a low probability that
the interrupt status cannot be read in sunxi_pinctrl_irq_handler. This
will cause the interrupt status of a gpio bank to always be active on
gic, preventing gic from responding to other spi interrupts correctly.
So we should call the chained_irq_* each time enter sunxi_pinctrl_irq_handler().
Cc: sta...@vger.kernel.org
Signed-off-by: Yangtao Li
---
drivers/pinctrl/sunxi/pinctrl-sunxi.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index 9d8b59dafa4b..dc8d39ae045b 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -1141,20 +1141,22 @@ static void sunxi_pinctrl_irq_handler(struct irq_desc
*desc)
WARN_ON(bank == pctl->desc->irq_banks);
+ chained_irq_enter(chip, desc);
+
reg = sunxi_irq_status_reg_from_bank(pctl->desc, bank);
val = readl(pctl->membase + reg);
if (val) {
int irqoffset;
- chained_irq_enter(chip, desc);
for_each_set_bit(irqoffset, , IRQ_PER_BANK) {
int pin_irq = irq_find_mapping(pctl->domain,
bank * IRQ_PER_BANK +
irqoffset);
generic_handle_irq(pin_irq);
}
- chained_irq_exit(chip, desc);
}
+
+ chained_irq_exit(chip, desc);
}
static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl,
--
2.28.0
[RESEND PATCH 02/19] pinctrl: sunxi: Mark the irq bank not found in sunxi_pinctrl_irq_handler() with WARN_ON
From: Yangtao Li The interrupt descriptor cannot be found in the interrupt processing function, and this situation cannot happen when the system is running normally. It doesn't seem right to return directly to the status of not handling gic. In this case, it must be a bug, let's mark it with WARN_ON. Signed-off-by: Yangtao Li --- drivers/pinctrl/sunxi/pinctrl-sunxi.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index 8e792f8e2dc9..9d8b59dafa4b 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -1139,8 +1139,7 @@ static void sunxi_pinctrl_irq_handler(struct irq_desc *desc) if (irq == pctl->irq[bank]) break; - if (bank == pctl->desc->irq_banks) - return; + WARN_ON(bank == pctl->desc->irq_banks); reg = sunxi_irq_status_reg_from_bank(pctl->desc, bank); val = readl(pctl->membase + reg); -- 2.28.0
[RESEND PATCH 01/19] pinctrl: sunxi: fix irq bank map for the Allwinner A100 pin controller
From: Yangtao Li
A100's pin starts with PB, so it should start with 1.
Fixes: 473436e7647d6 ("pinctrl: sunxi: add support for the Allwinner A100 pin
controller")
Signed-off-by: Yangtao Li
---
drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
index 19cfd1e76ee2..e69f6da40dc0 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
@@ -677,7 +677,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 19)),
};
-static const unsigned int a100_irq_bank_map[] = { 0, 1, 2, 3, 4, 5, 6};
+static const unsigned int a100_irq_bank_map[] = { 1, 2, 3, 4, 5, 6, 7};
static const struct sunxi_pinctrl_desc a100_pinctrl_data = {
.pins = a100_pins,
--
2.28.0
[RESEND PATCH 00/19] Second step support for A100
Let's add watchdog, arm-pmu, dma, usb, mmc. support for allwinner
a100 soc.
Yangtao Li (19):
pinctrl: sunxi: fix irq bank map for the Allwinner A100 pin controller
pinctrl: sunxi: Mark the irq bank not found in
sunxi_pinctrl_irq_handler() with WARN_ON
pinctrl: sunxi: Always call chained_irq_{enter, exit} in
sunxi_pinctrl_irq_handler
dt-bindings: dma: allwinner,sun50i-a64-dma: Add A100 compatible
dmaengine: sun6i: Add support for A100 DMA
arm64: allwinner: a100: Add device node for DMA controller
arm64: dts: allwinner: A100: Add PMU mode
phy: sun4i-usb: remove enable_pmu_unk1 from sun50i_h6_cfg
phy: allwinner: Convert to devm_platform_ioremap_* API
dt-bindings: watchdog: sun4i: Add A100 compatible
arm64: dts: allwinner: a100: add watchdog node
dt-bindings: Add bindings for USB phy on Allwinner A100
phy: sun4i-usb: add support for A100 USB PHY
arm64: dts: allwinner: a100: add usb related nodes
arm64: allwinner: A100: enable EHCI, OHCI and USB PHY nodes in Perf1
dt-bindings: mmc: sunxi: Add A100 compatibles
mmc: sunxi: add support for A100 mmc controller
arm64: allwinner: a100: Add MMC related nodes
arm64: dts: allwinner: a100: perf1: Add eMMC and MMC node
.../dma/allwinner,sun50i-a64-dma.yaml | 5 +-
.../bindings/mmc/allwinner,sun4i-a10-mmc.yaml | 2 +
.../phy/allwinner,sun50i-a100-usb-phy.yaml| 105 ++
.../watchdog/allwinner,sun4i-a10-wdt.yaml | 3 +
.../allwinner/sun50i-a100-allwinner-perf1.dts | 54 +
.../arm64/boot/dts/allwinner/sun50i-a100.dtsi | 197 +-
drivers/dma/sun6i-dma.c | 25 +++
drivers/mmc/host/sunxi-mmc.c | 28 ++-
drivers/phy/allwinner/phy-sun4i-usb.c | 29 ++-
drivers/phy/allwinner/phy-sun50i-usb3.c | 4 +-
drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 4 +-
drivers/phy/allwinner/phy-sun9i-usb.c | 4 +-
drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c | 2 +-
drivers/pinctrl/sunxi/pinctrl-sunxi.c | 9 +-
14 files changed, 443 insertions(+), 28 deletions(-)
create mode 100644
Documentation/devicetree/bindings/phy/allwinner,sun50i-a100-usb-phy.yaml
--
2.28.0
Re: [PATCH 00/19] Second step support for A100
It seems that sending too many e-mails at one time will cause some emails to fail to be sent out. I will try again. BR / Yangtao
[PATCH 04/19] dt-bindings: dma: allwinner,sun50i-a64-dma: Add A100 compatible
From: Yangtao Li Add a binding for A100's dma controller. Signed-off-by: Yangtao Li --- .../devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml| 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml b/Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml index 372679dbd216..b6e1ebfaf366 100644 --- a/Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml +++ b/Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml @@ -21,6 +21,7 @@ properties: compatible: oneOf: - const: allwinner,sun50i-a64-dma + - const: allwinner,sun50i-a100-dma - const: allwinner,sun50i-h6-dma - items: - const: allwinner,sun8i-r40-dma @@ -56,7 +57,9 @@ required: if: properties: compatible: - const: allwinner,sun50i-h6-dma + enum: +- allwinner,sun50i-a100-dma +- allwinner,sun50i-h6-dma then: properties: -- 2.28.0
[PATCH 06/19] arm64: allwinner: a100: Add device node for DMA controller
From: Yangtao Li
The A100 SoC has a DMA controller that supports 8 DMA channels
to and from various peripherals.
Add a device node for it.
Signed-off-by: Yangtao Li
---
arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
index cc321c04f121..c34ed8045363 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
@@ -101,6 +101,18 @@ ccu: clock@3001000 {
#reset-cells = <1>;
};
+ dma: dma-controller@3002000 {
+ compatible = "allwinner,sun50i-a100-dma";
+ reg = <0x03002000 0x1000>;
+ interrupts = ;
+ clocks = < CLK_BUS_DMA>, < CLK_MBUS_DMA>;
+ clock-names = "bus", "mbus";
+ dma-channels = <8>;
+ dma-requests = <51>;
+ resets = < RST_BUS_DMA>;
+ #dma-cells = <1>;
+ };
+
gic: interrupt-controller@3021000 {
compatible = "arm,gic-400";
reg = <0x03021000 0x1000>, <0x03022000 0x2000>,
--
2.28.0
[PATCH 08/19] phy: sun4i-usb: remove enable_pmu_unk1 from sun50i_h6_cfg
From: Yangtao Li
For the current code, enable_pmu_unk1 only works in non-a83t and non-h6
types. So let's delete it from the sun50i_h6_cfg.
Signed-off-by: Yangtao Li
---
drivers/phy/allwinner/phy-sun4i-usb.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c
b/drivers/phy/allwinner/phy-sun4i-usb.c
index 651d5e2a25ce..0f1888b55dbd 100644
--- a/drivers/phy/allwinner/phy-sun4i-usb.c
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
@@ -969,7 +969,6 @@ static const struct sun4i_usb_phy_cfg sun50i_h6_cfg = {
.disc_thresh = 3,
.phyctl_offset = REG_PHYCTL_A33,
.dedicated_clocks = true,
- .enable_pmu_unk1 = true,
.phy0_dual_route = true,
.missing_phys = BIT(1) | BIT(2),
};
--
2.28.0
[PATCH 07/19] arm64: dts: allwinner: A100: Add PMU mode
From: Yangtao Li
Add the Performance Monitoring Unit (PMU) device tree node to the A100
.dtsi, which tells DT users which interrupts are triggered by PMU overflow
events on each core.
Signed-off-by: Yangtao Li
---
arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
index c34ed8045363..01ff53b5a7a8 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
@@ -25,21 +25,21 @@ cpu0: cpu@0 {
enable-method = "psci";
};
- cpu@1 {
+ cpu1: cpu@1 {
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0x1>;
enable-method = "psci";
};
- cpu@2 {
+ cpu2: cpu@2 {
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0x2>;
enable-method = "psci";
};
- cpu@3 {
+ cpu3: cpu@3 {
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0x3>;
@@ -47,6 +47,15 @@ cpu@3 {
};
};
+ pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = ,
+,
+,
+;
+ interrupt-affinity = <>, <>, <>, <>;
+ };
+
psci {
compatible = "arm,psci-1.0";
method = "smc";
--
2.28.0
[PATCH 09/19] phy: allwinner: Convert to devm_platform_ioremap_* API
From: Yangtao Li
Use the devm_platform_ioremap_resource_byname() and
devm_platform_ioremap_resource helper to simplify the code.
Signed-off-by: Yangtao Li
---
drivers/phy/allwinner/phy-sun4i-usb.c | 9 +++--
drivers/phy/allwinner/phy-sun50i-usb3.c | 4 +---
drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 4 +---
drivers/phy/allwinner/phy-sun9i-usb.c | 4 +---
4 files changed, 6 insertions(+), 15 deletions(-)
diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c
b/drivers/phy/allwinner/phy-sun4i-usb.c
index 0f1888b55dbd..a6900495baa5 100644
--- a/drivers/phy/allwinner/phy-sun4i-usb.c
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
@@ -686,7 +686,6 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
struct device *dev = >dev;
struct device_node *np = dev->of_node;
struct phy_provider *phy_provider;
- struct resource *res;
int i, ret;
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
@@ -700,8 +699,7 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
if (!data->cfg)
return -EINVAL;
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy_ctrl");
- data->base = devm_ioremap_resource(dev, res);
+ data->base = devm_platform_ioremap_resource_byname(pdev, "phy_ctrl");
if (IS_ERR(data->base))
return PTR_ERR(data->base);
@@ -796,9 +794,8 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
if (i || data->cfg->phy0_dual_route) { /* No pmu for musb */
snprintf(name, sizeof(name), "pmu%d", i);
- res = platform_get_resource_byname(pdev,
- IORESOURCE_MEM, name);
- phy->pmu = devm_ioremap_resource(dev, res);
+ phy->pmu = devm_platform_ioremap_resource_byname(pdev,
+name);
if (IS_ERR(phy->pmu))
return PTR_ERR(phy->pmu);
}
diff --git a/drivers/phy/allwinner/phy-sun50i-usb3.c
b/drivers/phy/allwinner/phy-sun50i-usb3.c
index b1c04f71a31d..84055b720016 100644
--- a/drivers/phy/allwinner/phy-sun50i-usb3.c
+++ b/drivers/phy/allwinner/phy-sun50i-usb3.c
@@ -134,7 +134,6 @@ static int sun50i_usb3_phy_probe(struct platform_device
*pdev)
struct sun50i_usb3_phy *phy;
struct device *dev = >dev;
struct phy_provider *phy_provider;
- struct resource *res;
phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
if (!phy)
@@ -153,8 +152,7 @@ static int sun50i_usb3_phy_probe(struct platform_device
*pdev)
return PTR_ERR(phy->reset);
}
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- phy->regs = devm_ioremap_resource(dev, res);
+ phy->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(phy->regs))
return PTR_ERR(phy->regs);
diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
index 1fa761ba6cbb..f0bc87d654d4 100644
--- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
+++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
@@ -253,15 +253,13 @@ static int sun6i_dphy_probe(struct platform_device *pdev)
{
struct phy_provider *phy_provider;
struct sun6i_dphy *dphy;
- struct resource *res;
void __iomem *regs;
dphy = devm_kzalloc(>dev, sizeof(*dphy), GFP_KERNEL);
if (!dphy)
return -ENOMEM;
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- regs = devm_ioremap_resource(>dev, res);
+ regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(regs)) {
dev_err(>dev, "Couldn't map the DPHY encoder
registers\n");
return PTR_ERR(regs);
diff --git a/drivers/phy/allwinner/phy-sun9i-usb.c
b/drivers/phy/allwinner/phy-sun9i-usb.c
index fc6784dd7fa0..2f9e60c188b8 100644
--- a/drivers/phy/allwinner/phy-sun9i-usb.c
+++ b/drivers/phy/allwinner/phy-sun9i-usb.c
@@ -117,7 +117,6 @@ static int sun9i_usb_phy_probe(struct platform_device *pdev)
struct device *dev = >dev;
struct device_node *np = dev->of_node;
struct phy_provider *phy_provider;
- struct resource *res;
phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
if (!phy)
@@ -156,8 +155,7 @@ static int sun9i_usb_phy_probe(struct platform_device *pdev)
}
}
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- phy->pmu = devm_ioremap_resource(dev, res);
+ phy->pmu = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(phy->pmu))
return PTR_ERR(phy->pmu);
--
2.28.0
[PATCH 05/19] dmaengine: sun6i: Add support for A100 DMA
From: Yangtao Li
The dma of a100 is similar to h6, with some minor changes to
support greater addressing capabilities.
Add support for it.
Signed-off-by: Yangtao Li
---
drivers/dma/sun6i-dma.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c
index f5f9c86c50bc..5cadd4d2b824 100644
--- a/drivers/dma/sun6i-dma.c
+++ b/drivers/dma/sun6i-dma.c
@@ -1173,6 +1173,30 @@ static struct sun6i_dma_config sun50i_a64_dma_cfg = {
BIT(DMA_SLAVE_BUSWIDTH_8_BYTES),
};
+/*
+ * TODO: Add support for more than 4g physical addressing.
+ *
+ * The A100 binding uses the number of dma channels from the
+ * device tree node.
+ */
+static struct sun6i_dma_config sun50i_a100_dma_cfg = {
+ .clock_autogate_enable = sun6i_enable_clock_autogate_h3,
+ .set_burst_length = sun6i_set_burst_length_h3,
+ .set_drq = sun6i_set_drq_h6,
+ .set_mode = sun6i_set_mode_h6,
+ .src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
+ .dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
+ .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
+BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
+BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
+BIT(DMA_SLAVE_BUSWIDTH_8_BYTES),
+ .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
+BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
+BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
+BIT(DMA_SLAVE_BUSWIDTH_8_BYTES),
+ .has_mbus_clk = true,
+};
+
/*
* The H6 binding uses the number of dma channels from the
* device tree node.
@@ -1225,6 +1249,7 @@ static const struct of_device_id sun6i_dma_match[] = {
{ .compatible = "allwinner,sun8i-h3-dma", .data = _h3_dma_cfg },
{ .compatible = "allwinner,sun8i-v3s-dma", .data = _v3s_dma_cfg },
{ .compatible = "allwinner,sun50i-a64-dma", .data = _a64_dma_cfg
},
+ { .compatible = "allwinner,sun50i-a100-dma", .data =
_a100_dma_cfg },
{ .compatible = "allwinner,sun50i-h6-dma", .data = _h6_dma_cfg },
{ /* sentinel */ }
};
--
2.28.0
[PATCH 03/19] pinctrl: sunxi: Always call chained_irq_{enter, exit} in sunxi_pinctrl_irq_handler
From: Yangtao Li
It is found on many allwinner soc that there is a low probability that
the interrupt status cannot be read in sunxi_pinctrl_irq_handler. This
will cause the interrupt status of a gpio bank to always be active on
gic, preventing gic from responding to other spi interrupts correctly.
So we should call the chained_irq_* each time enter sunxi_pinctrl_irq_handler().
Cc: sta...@vger.kernel.org
Signed-off-by: Yangtao Li
---
drivers/pinctrl/sunxi/pinctrl-sunxi.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index 9d8b59dafa4b..dc8d39ae045b 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -1141,20 +1141,22 @@ static void sunxi_pinctrl_irq_handler(struct irq_desc
*desc)
WARN_ON(bank == pctl->desc->irq_banks);
+ chained_irq_enter(chip, desc);
+
reg = sunxi_irq_status_reg_from_bank(pctl->desc, bank);
val = readl(pctl->membase + reg);
if (val) {
int irqoffset;
- chained_irq_enter(chip, desc);
for_each_set_bit(irqoffset, , IRQ_PER_BANK) {
int pin_irq = irq_find_mapping(pctl->domain,
bank * IRQ_PER_BANK +
irqoffset);
generic_handle_irq(pin_irq);
}
- chained_irq_exit(chip, desc);
}
+
+ chained_irq_exit(chip, desc);
}
static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl,
--
2.28.0
[PATCH 02/19] pinctrl: sunxi: Mark the irq bank not found in sunxi_pinctrl_irq_handler() with WARN_ON
From: Yangtao Li The interrupt descriptor cannot be found in the interrupt processing function, and this situation cannot happen when the system is running normally. It doesn't seem right to return directly to the status of not handling gic. In this case, it must be a bug, let's mark it with BUG_ON. Signed-off-by: Yangtao Li --- drivers/pinctrl/sunxi/pinctrl-sunxi.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index 8e792f8e2dc9..9d8b59dafa4b 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -1139,8 +1139,7 @@ static void sunxi_pinctrl_irq_handler(struct irq_desc *desc) if (irq == pctl->irq[bank]) break; - if (bank == pctl->desc->irq_banks) - return; + WARN_ON(bank == pctl->desc->irq_banks); reg = sunxi_irq_status_reg_from_bank(pctl->desc, bank); val = readl(pctl->membase + reg); -- 2.28.0
[PATCH 00/19] Second step support for A100
Hi,
Let's add watchdog, arm-pmu, dma, usb, mmc. support for allwinner
a100 soc.
Yangtao Li (19):
pinctrl: sunxi: fix irq bank map for the Allwinner A100 pin controller
pinctrl: sunxi: Mark the irq bank not found in
sunxi_pinctrl_irq_handler() with WARN_ON
pinctrl: sunxi: Always call chained_irq_{enter, exit} in
sunxi_pinctrl_irq_handler
dt-bindings: dma: allwinner,sun50i-a64-dma: Add A100 compatible
dmaengine: sun6i: Add support for A100 DMA
arm64: allwinner: a100: Add device node for DMA controller
arm64: dts: allwinner: A100: Add PMU mode
phy: sun4i-usb: remove enable_pmu_unk1 from sun50i_h6_cfg
phy: allwinner: Convert to devm_platform_ioremap_* API
dt-bindings: watchdog: sun4i: Add A100 compatible
arm64: dts: allwinner: a100: add watchdog node
dt-bindings: Add bindings for USB phy on Allwinner A100
phy: sun4i-usb: add support for A100 USB PHY
arm64: dts: allwinner: a100: add usb related nodes
arm64: allwinner: A100: enable EHCI, OHCI and USB PHY nodes in Perf1
dt-bindings: mmc: sunxi: Add A100 compatibles
mmc: sunxi: add support for A100 mmc controller
arm64: allwinner: a100: Add MMC related nodes
arm64: dts: allwinner: a100: perf1: Add eMMC and MMC node
.../dma/allwinner,sun50i-a64-dma.yaml | 5 +-
.../bindings/mmc/allwinner,sun4i-a10-mmc.yaml | 2 +
.../phy/allwinner,sun50i-a100-usb-phy.yaml| 105 ++
.../watchdog/allwinner,sun4i-a10-wdt.yaml | 3 +
.../allwinner/sun50i-a100-allwinner-perf1.dts | 54 +
.../arm64/boot/dts/allwinner/sun50i-a100.dtsi | 197 +-
drivers/dma/sun6i-dma.c | 25 +++
drivers/mmc/host/sunxi-mmc.c | 28 ++-
drivers/phy/allwinner/phy-sun4i-usb.c | 29 ++-
drivers/phy/allwinner/phy-sun50i-usb3.c | 4 +-
drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 4 +-
drivers/phy/allwinner/phy-sun9i-usb.c | 4 +-
drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c | 2 +-
drivers/pinctrl/sunxi/pinctrl-sunxi.c | 9 +-
14 files changed, 443 insertions(+), 28 deletions(-)
create mode 100644
Documentation/devicetree/bindings/phy/allwinner,sun50i-a100-usb-phy.yaml
--
2.28.0
[PATCH 01/19] pinctrl: sunxi: fix irq bank map for the Allwinner A100 pin controller
From: Yangtao Li
A100's pin starts with PB, so it should start with 1.
Fixes: 473436e7647d6 ("pinctrl: sunxi: add support for the Allwinner A100 pin
controller")
Signed-off-by: Yangtao Li
---
drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
index 19cfd1e76ee2..e69f6da40dc0 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
@@ -677,7 +677,7 @@ static const struct sunxi_desc_pin a100_pins[] = {
SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 19)),
};
-static const unsigned int a100_irq_bank_map[] = { 0, 1, 2, 3, 4, 5, 6};
+static const unsigned int a100_irq_bank_map[] = { 1, 2, 3, 4, 5, 6, 7};
static const struct sunxi_pinctrl_desc a100_pinctrl_data = {
.pins = a100_pins,
--
2.28.0
Re: [PATCH 6/9] cpufreq: sun50i: Add missing MODULE_DEVICE_TABLE
On Tue, Nov 3, 2020 at 11:14 PM Pali Rohár wrote:
>
> This patch adds missing MODULE_DEVICE_TABLE definition which generates
> correct modalias for automatic loading of this cpufreq driver when it is
> compiled as an external module.
>
> Signed-off-by: Pali Rohár
> Fixes: f328584f7bff8 ("cpufreq: Add sun50i nvmem based CPU scaling driver")
> ---
> drivers/cpufreq/sun50i-cpufreq-nvmem.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/cpufreq/sun50i-cpufreq-nvmem.c
> b/drivers/cpufreq/sun50i-cpufreq-nvmem.c
> index 9907a165135b..2deed8d8773f 100644
> --- a/drivers/cpufreq/sun50i-cpufreq-nvmem.c
> +++ b/drivers/cpufreq/sun50i-cpufreq-nvmem.c
> @@ -167,6 +167,7 @@ static const struct of_device_id
> sun50i_cpufreq_match_list[] = {
> { .compatible = "allwinner,sun50i-h6" },
> {}
> };
> +MODULE_DEVICE_TABLE(of, sun50i_cpufreq_match_list);
Reviewed-by: Yangtao Li
Thx!
Re: [PATCH 1/3] dt-bindings: gpio: sunxi：create a DT header for Allwinner pin controller
HI Maxime, Maybe let's convert to use something like SUN4I_PA? Yangtao
[PATCH] arm64: dts: allwinner: a64: fix sid node name
From: Yangtao Li
Sid should be an efuse type device accurately. And no one
needs sid label, so delete it.
Signed-off-by: Yangtao Li
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index dc238814013c..96543df5d890 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -520,7 +520,7 @@ mmc2: mmc@1c11000 {
#size-cells = <0>;
};
- sid: eeprom@1c14000 {
+ efuse@1c14000 {
compatible = "allwinner,sun50i-a64-sid";
reg = <0x1c14000 0x400>;
#address-cells = <1>;
--
2.28.0
[PATCH 3/3] phy: sun4i-usb: Use power efficient workqueue for debounce and poll
From: Yangtao Li The debounce and poll time is generally quite long and the work not performance critical so allow the scheduler to run the work anywhere rather than in the normal per-CPU workqueue. Signed-off-by: Yangtao Li --- drivers/phy/allwinner/phy-sun4i-usb.c | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c index 651d5e2a25ce..4787ad13b255 100644 --- a/drivers/phy/allwinner/phy-sun4i-usb.c +++ b/drivers/phy/allwinner/phy-sun4i-usb.c @@ -326,7 +326,7 @@ static int sun4i_usb_phy_init(struct phy *_phy) /* Force ISCR and cable state updates */ data->id_det = -1; data->vbus_det = -1; - queue_delayed_work(system_wq, >detect, 0); + queue_delayed_work(system_power_efficient_wq, >detect, 0); } return 0; @@ -444,7 +444,7 @@ static int sun4i_usb_phy_power_on(struct phy *_phy) /* We must report Vbus high within OTG_TIME_A_WAIT_VRISE msec. */ if (phy->index == 0 && sun4i_usb_phy0_poll(data)) - mod_delayed_work(system_wq, >detect, DEBOUNCE_TIME); + mod_delayed_work(system_power_efficient_wq, >detect, DEBOUNCE_TIME); return 0; } @@ -465,7 +465,7 @@ static int sun4i_usb_phy_power_off(struct phy *_phy) * Vbus gpio to not trigger an edge irq on Vbus off, so force a rescan. */ if (phy->index == 0 && !sun4i_usb_phy0_poll(data)) - mod_delayed_work(system_wq, >detect, POLL_TIME); + mod_delayed_work(system_power_efficient_wq, >detect, POLL_TIME); return 0; } @@ -504,7 +504,7 @@ static int sun4i_usb_phy_set_mode(struct phy *_phy, data->id_det = -1; /* Force reprocessing of id */ data->force_session_end = true; - queue_delayed_work(system_wq, >detect, 0); + queue_delayed_work(system_power_efficient_wq, >detect, 0); return 0; } @@ -616,7 +616,7 @@ static void sun4i_usb_phy0_id_vbus_det_scan(struct work_struct *work) extcon_set_state_sync(data->extcon, EXTCON_USB, vbus_det); if (sun4i_usb_phy0_poll(data)) - queue_delayed_work(system_wq, >detect, POLL_TIME); + queue_delayed_work(system_power_efficient_wq, >detect, POLL_TIME); } static irqreturn_t sun4i_usb_phy0_id_vbus_det_irq(int irq, void *dev_id) @@ -624,7 +624,7 @@ static irqreturn_t sun4i_usb_phy0_id_vbus_det_irq(int irq, void *dev_id) struct sun4i_usb_phy_data *data = dev_id; /* vbus or id changed, let the pins settle and then scan them */ - mod_delayed_work(system_wq, >detect, DEBOUNCE_TIME); + mod_delayed_work(system_power_efficient_wq, >detect, DEBOUNCE_TIME); return IRQ_HANDLED; } @@ -638,7 +638,7 @@ static int sun4i_usb_phy0_vbus_notify(struct notifier_block *nb, /* Properties on the vbus_power_supply changed, scan vbus_det */ if (val == PSY_EVENT_PROP_CHANGED && psy == data->vbus_power_supply) - mod_delayed_work(system_wq, >detect, DEBOUNCE_TIME); + mod_delayed_work(system_power_efficient_wq, >detect, DEBOUNCE_TIME); return NOTIFY_OK; } -- 2.28.0
[PATCH 2/3] power: supply: axp20x_usb_power: Use power efficient workqueue for debounce
From: Yangtao Li The debounce timeout is generally quite long and the work not performance critical so allow the scheduler to run the work anywhere rather than in the normal per-CPU workqueue. Signed-off-by: Yangtao Li --- drivers/power/supply/axp20x_usb_power.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/power/supply/axp20x_usb_power.c b/drivers/power/supply/axp20x_usb_power.c index 3b4fd710347d..70b28b699a80 100644 --- a/drivers/power/supply/axp20x_usb_power.c +++ b/drivers/power/supply/axp20x_usb_power.c @@ -92,7 +92,7 @@ static irqreturn_t axp20x_usb_power_irq(int irq, void *devid) power_supply_changed(power->supply); - mod_delayed_work(system_wq, >vbus_detect, DEBOUNCE_TIME); + mod_delayed_work(system_power_efficient_wq, >vbus_detect, DEBOUNCE_TIME); return IRQ_HANDLED; } @@ -117,7 +117,7 @@ static void axp20x_usb_power_poll_vbus(struct work_struct *work) out: if (axp20x_usb_vbus_needs_polling(power)) - mod_delayed_work(system_wq, >vbus_detect, DEBOUNCE_TIME); + mod_delayed_work(system_power_efficient_wq, >vbus_detect, DEBOUNCE_TIME); } static int axp20x_get_current_max(struct axp20x_usb_power *power, int *val) @@ -525,7 +525,7 @@ static int axp20x_usb_power_resume(struct device *dev) while (i < power->num_irqs) enable_irq(power->irqs[i++]); - mod_delayed_work(system_wq, >vbus_detect, DEBOUNCE_TIME); + mod_delayed_work(system_power_efficient_wq, >vbus_detect, DEBOUNCE_TIME); return 0; } @@ -647,7 +647,7 @@ static int axp20x_usb_power_probe(struct platform_device *pdev) INIT_DELAYED_WORK(>vbus_detect, axp20x_usb_power_poll_vbus); if (axp20x_usb_vbus_needs_polling(power)) - queue_delayed_work(system_wq, >vbus_detect, 0); + queue_delayed_work(system_power_efficient_wq, >vbus_detect, 0); return 0; } -- 2.28.0
[PATCH 1/3] power: supply: axp20x_usb_power: fix typo
From: Yangtao Li s/on on/on Signed-off-by: Yangtao Li --- drivers/power/supply/axp20x_usb_power.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/power/supply/axp20x_usb_power.c b/drivers/power/supply/axp20x_usb_power.c index 0eaa86c52874..3b4fd710347d 100644 --- a/drivers/power/supply/axp20x_usb_power.c +++ b/drivers/power/supply/axp20x_usb_power.c @@ -397,7 +397,7 @@ static int axp20x_usb_power_prop_writeable(struct power_supply *psy, struct axp20x_usb_power *power = power_supply_get_drvdata(psy); /* -* The VBUS path select flag works differently on on AXP288 and newer: +* The VBUS path select flag works differently on AXP288 and newer: * - On AXP20x and AXP22x, the flag enables VBUS (ignoring N_VBUSEN). * - On AXP288 and AXP8xx, the flag disables VBUS (ignoring N_VBUSEN). * We only expose the control on variants where it can be used to force -- 2.28.0
[PATCH v2] thermal: sun8i: Use bitmap API instead of open code
From: Yangtao Li
The bitmap_* API is the standard way to access data in the bitfield.
So convert irq_ack to return an unsigned long, and make things to use
bitmap API.
Signed-off-by: Yangtao Li
---
v2:
Make irq_ack to return an unsigned long
---
drivers/thermal/sun8i_thermal.c | 33 +
1 file changed, 17 insertions(+), 16 deletions(-)
diff --git a/drivers/thermal/sun8i_thermal.c b/drivers/thermal/sun8i_thermal.c
index f8b13071a6f4..8c80bd06dd9f 100644
--- a/drivers/thermal/sun8i_thermal.c
+++ b/drivers/thermal/sun8i_thermal.c
@@ -8,6 +8,7 @@
* Based on the work of Josef Gajdusek
*/
+#include
#include
#include
#include
@@ -74,7 +75,7 @@ struct ths_thermal_chip {
int (*calibrate)(struct ths_device *tmdev,
u16 *caldata, int callen);
int (*init)(struct ths_device *tmdev);
- int (*irq_ack)(struct ths_device *tmdev);
+ unsigned long (*irq_ack)(struct ths_device *tmdev);
int (*calc_temp)(struct ths_device *tmdev,
int id, int reg);
};
@@ -146,9 +147,10 @@ static const struct regmap_config config = {
.max_register = 0xfc,
};
-static int sun8i_h3_irq_ack(struct ths_device *tmdev)
+static unsigned long sun8i_h3_irq_ack(struct ths_device *tmdev)
{
- int i, state, ret = 0;
+ unsigned long irq_bitmap = 0;
+ int i, state;
regmap_read(tmdev->regmap, SUN8I_THS_IS, );
@@ -156,16 +158,17 @@ static int sun8i_h3_irq_ack(struct ths_device *tmdev)
if (state & SUN8I_THS_DATA_IRQ_STS(i)) {
regmap_write(tmdev->regmap, SUN8I_THS_IS,
SUN8I_THS_DATA_IRQ_STS(i));
- ret |= BIT(i);
+ bitmap_set(_bitmap, i, 1);
}
}
- return ret;
+ return irq_bitmap;
}
-static int sun50i_h6_irq_ack(struct ths_device *tmdev)
+static unsigned long sun50i_h6_irq_ack(struct ths_device *tmdev)
{
- int i, state, ret = 0;
+ unsigned long irq_bitmap = 0;
+ int i, state;
regmap_read(tmdev->regmap, SUN50I_H6_THS_DIS, );
@@ -173,24 +176,22 @@ static int sun50i_h6_irq_ack(struct ths_device *tmdev)
if (state & SUN50I_H6_THS_DATA_IRQ_STS(i)) {
regmap_write(tmdev->regmap, SUN50I_H6_THS_DIS,
SUN50I_H6_THS_DATA_IRQ_STS(i));
- ret |= BIT(i);
+ bitmap_set(_bitmap, i, 1);
}
}
- return ret;
+ return irq_bitmap;
}
static irqreturn_t sun8i_irq_thread(int irq, void *data)
{
struct ths_device *tmdev = data;
- int i, state;
-
- state = tmdev->chip->irq_ack(tmdev);
+ unsigned long irq_bitmap = tmdev->chip->irq_ack(tmdev);
+ int i;
- for (i = 0; i < tmdev->chip->sensor_num; i++) {
- if (state & BIT(i))
- thermal_zone_device_update(tmdev->sensor[i].tzd,
- THERMAL_EVENT_UNSPECIFIED);
+ for_each_set_bit(i, _bitmap, tmdev->chip->sensor_num) {
+ thermal_zone_device_update(tmdev->sensor[i].tzd,
+ THERMAL_EVENT_UNSPECIFIED);
}
return IRQ_HANDLED;
--
2.28.0
Re: [PATCH] thermal: sun8i: Use bitmap API instead of open code
I forgot to add "V2", I will resend. Yangtao
[PATCH] thermal: sun8i: Use bitmap API instead of open code
From: Yangtao Li
The bitmap_* API is the standard way to access data in the bitfield.
So convert irq_ack to return an unsigned long, and make things to use
bitmap API.
Signed-off-by: Yangtao Li
---
v2:
Make irq_ack to return an unsigned long
---
drivers/thermal/sun8i_thermal.c | 33 +
1 file changed, 17 insertions(+), 16 deletions(-)
diff --git a/drivers/thermal/sun8i_thermal.c b/drivers/thermal/sun8i_thermal.c
index f8b13071a6f4..8c80bd06dd9f 100644
--- a/drivers/thermal/sun8i_thermal.c
+++ b/drivers/thermal/sun8i_thermal.c
@@ -8,6 +8,7 @@
* Based on the work of Josef Gajdusek
*/
+#include
#include
#include
#include
@@ -74,7 +75,7 @@ struct ths_thermal_chip {
int (*calibrate)(struct ths_device *tmdev,
u16 *caldata, int callen);
int (*init)(struct ths_device *tmdev);
- int (*irq_ack)(struct ths_device *tmdev);
+ unsigned long (*irq_ack)(struct ths_device *tmdev);
int (*calc_temp)(struct ths_device *tmdev,
int id, int reg);
};
@@ -146,9 +147,10 @@ static const struct regmap_config config = {
.max_register = 0xfc,
};
-static int sun8i_h3_irq_ack(struct ths_device *tmdev)
+static unsigned long sun8i_h3_irq_ack(struct ths_device *tmdev)
{
- int i, state, ret = 0;
+ unsigned long irq_bitmap = 0;
+ int i, state;
regmap_read(tmdev->regmap, SUN8I_THS_IS, );
@@ -156,16 +158,17 @@ static int sun8i_h3_irq_ack(struct ths_device *tmdev)
if (state & SUN8I_THS_DATA_IRQ_STS(i)) {
regmap_write(tmdev->regmap, SUN8I_THS_IS,
SUN8I_THS_DATA_IRQ_STS(i));
- ret |= BIT(i);
+ bitmap_set(_bitmap, i, 1);
}
}
- return ret;
+ return irq_bitmap;
}
-static int sun50i_h6_irq_ack(struct ths_device *tmdev)
+static unsigned long sun50i_h6_irq_ack(struct ths_device *tmdev)
{
- int i, state, ret = 0;
+ unsigned long irq_bitmap = 0;
+ int i, state;
regmap_read(tmdev->regmap, SUN50I_H6_THS_DIS, );
@@ -173,24 +176,22 @@ static int sun50i_h6_irq_ack(struct ths_device *tmdev)
if (state & SUN50I_H6_THS_DATA_IRQ_STS(i)) {
regmap_write(tmdev->regmap, SUN50I_H6_THS_DIS,
SUN50I_H6_THS_DATA_IRQ_STS(i));
- ret |= BIT(i);
+ bitmap_set(_bitmap, i, 1);
}
}
- return ret;
+ return irq_bitmap;
}
static irqreturn_t sun8i_irq_thread(int irq, void *data)
{
struct ths_device *tmdev = data;
- int i, state;
-
- state = tmdev->chip->irq_ack(tmdev);
+ unsigned long irq_bitmap = tmdev->chip->irq_ack(tmdev);
+ int i;
- for (i = 0; i < tmdev->chip->sensor_num; i++) {
- if (state & BIT(i))
- thermal_zone_device_update(tmdev->sensor[i].tzd,
- THERMAL_EVENT_UNSPECIFIED);
+ for_each_set_bit(i, _bitmap, tmdev->chip->sensor_num) {
+ thermal_zone_device_update(tmdev->sensor[i].tzd,
+ THERMAL_EVENT_UNSPECIFIED);
}
return IRQ_HANDLED;
--
2.28.0
Re: [PATCH v1 17/30] mmc: sdhci-tegra: Support OPP and core voltage scaling
On Mon, Nov 9, 2020 at 1:53 PM Viresh Kumar wrote: > > On 09-11-20, 08:44, Dmitry Osipenko wrote: > > 09.11.2020 08:35, Viresh Kumar пишет: > > > On 09-11-20, 08:19, Dmitry Osipenko wrote: > > >> Thanks, I made it in a different way by simply adding helpers to the > > >> pm_opp.h which use devm_add_action_or_reset(). This doesn't require to > > >> add new kernel symbols. > > > > > > I will prefer to add it in core.c itself, and yes > > > devm_add_action_or_reset() looks better. But I am still not sure for > > > which helpers do we need the devm_*() variants, as this is only useful > > > for non-CPU devices. But if we have users that we can add right now, > > > why not. > > > > All current non-CPU drivers (devfreq, mmc, memory, etc) can benefit from it. > > > > For Tegra drivers we need these variants: > > > > devm_pm_opp_set_supported_hw() > > devm_pm_opp_set_regulators() [if we won't use GENPD] > > devm_pm_opp_set_clkname() > > devm_pm_opp_of_add_table() > > I tried to look earlier for the stuff already merged in and didn't > find a lot of stuff where the devm_* could be used, maybe I missed > some of it. > > Frank, would you like to refresh your series based on suggestions from > Dmitry and make other drivers adapt to the new APIs ? I am glad to do this.：） Yangtao
Re: [PATCH v1 17/30] mmc: sdhci-tegra: Support OPP and core voltage scaling
On Fri, Nov 6, 2020 at 9:18 PM Dmitry Osipenko wrote: > > 06.11.2020 09:15, Viresh Kumar пишет: > > Setting regulators for count as 0 doesn't sound good to me. > > > > But, I understand that you don't want to have that if (have_regulator) > > check, and it is a fair request. What I will instead do is, allow all > > dev_pm_opp_put*() API to start accepting a NULL pointer for the OPP > > table and fail silently. And so you won't be required to have this > > unwanted check. But you will be required to save the pointer returned > > back by dev_pm_opp_set_regulators(), which is the right thing to do > > anyways. > > Perhaps even a better variant could be to add a devm versions of the OPP > API functions, then drivers won't need to care about storing the > opp_table pointer if it's unused by drivers. I think so. The consumer may not be so concerned about the status of these OPP tables. If the driver needs to manage the release, it needs to add a pointer to their driver global structure. Maybe it's worth having these devm interfaces for opp. Yangtao
Re: [PATCH 2/3] opp: Add devres wrapper for dev_pm_opp_set_prop_name
On Wed, Oct 28, 2020 at 10:46 PM Viresh Kumar wrote: > > On 28-10-20, 19:02, Frank Lee wrote: > > On Wed, Oct 28, 2020 at 6:29 PM Viresh Kumar > > wrote: > > > > > > On 12-10-20, 21:55, Frank Lee wrote: > > > > From: Yangtao Li > > > > > > > > Add devres wrapper for dev_pm_opp_set_prop_name() to simplify driver > > > > code. > > > > > > > > Signed-off-by: Yangtao Li > > > > Signed-off-by: Yangtao Li > > > > --- > > > > drivers/opp/core.c | 39 +++ > > > > include/linux/pm_opp.h | 6 ++ > > > > 2 files changed, 45 insertions(+) > > > > > > On a second thought I am looking at dropping this one as you haven't > > > added any users yet and I am afraid it will stay unused. > > > > Now it looks like that dev_pm_opp_set_prop_name() is used relatively less. > > Maybe we can wait until a caller, and then pick up the patch. > > I am even wondering if we should be adding any of the devm_* helpers > for now to be honest. Even for the other one we have only one user. > Them major user of the OPP core is the CPU subsystem and it is never > going to use these devm_* helpers as the CPU device doesn't get bound > to a driver, it is rather a fake platform device which gets the > cpufreq drivers probed. So the only users of these devm_* helpers is > going to be non-CPU devices. Considering that we have only one user > right now, it may be better to just fix it instead of adding any of > the devm_* helpers. GPU is also a relatively large number of opp consumers. Most of the time, the dev_pm_opp_set_* functions will only be set once. If don't need the driver to dynamically manage and release the opp, it may be OK？ Yangtao
Re: [PATCH 1/3] dt-bindings: gpio: sunxi：create a DT header for Allwinner pin controller
On Wed, Jul 29, 2020 at 9:06 PM Maxime Ripard wrote: > > Hi, > > On Sat, Jul 25, 2020 at 02:18:39PM -0500, Samuel Holland wrote: > > On 7/17/20 11:07 AM, Maxime Ripard wrote: > > > Hi! > > > > > > On Wed, Jul 15, 2020 at 07:54:12PM +0800, Frank Lee wrote: > > >> From: Yangtao Li > > >> > > >> The sunxi gpio binding defines a few custom cells for its gpio specifier. > > >> Provide bank name for those. > > >> > > >> Signed-off-by: Yangtao Li > > > > > > Thanks for working on this, I wanted to do it at some point but it kept > > > getting pushed further into my todo list. > > > > > >> --- > > >> include/dt-bindings/gpio/sunxi-gpio.h | 29 +++ > > >> 1 file changed, 29 insertions(+) > > >> create mode 100644 include/dt-bindings/gpio/sunxi-gpio.h > > >> > > >> diff --git a/include/dt-bindings/gpio/sunxi-gpio.h > > >> b/include/dt-bindings/gpio/sunxi-gpio.h > > >> new file mode 100644 > > >> index ..c692b4360da6 > > >> --- /dev/null > > >> +++ b/include/dt-bindings/gpio/sunxi-gpio.h > > > > > > So generally we've been using the compatible name as the file name. You > > > should follow that convention too, and since it was added with the A10, > > > using the A10 compatible. > > > > > >> @@ -0,0 +1,29 @@ > > >> +/* SPDX-License-Identifier: GPL-2.0 */ > > >> +/* > > >> + * GPIO definitions for Allwinner SoCs > > >> + * > > >> + * Copyright (C) 2020 Yangtao Li > > >> + */ > > >> + > > >> +#ifndef _DT_BINDINGS_SUNXI_GPIO_H > > >> +#define _DT_BINDINGS_SUNXI_GPIO_H > > >> + > > >> +#include > > >> + > > >> +/* pio */ > > >> +#define PA0 > > >> +#define PB1 > > >> +#define PC2 > > >> +#define PD3 > > >> +#define PE4 > > >> +#define PF5 > > >> +#define PG6 > > >> +#define PH7 > > >> +#define PI8 > > >> + > > >> +/* r-pio */ > > >> +#define PL0 > > >> +#define PM1 > > >> +#define PN2 > > >> + > > >> +#endif /* _DT_BINDINGS_SUNXI_GPIO_H */ > > > > > > Maybe we can go one step further and use a macro to have something like > > > PIN(A, 12) ? > > > > Since we have separate cells for the bank and pin, I don't think it would be > > appropriate to have a single macro generating both. > > Yeah, but it's "just" an encoding issue though, it's not a major concern > if it makes our life easier. > > > And I'm not sure what the benefit of the macro would be, if all it > > does is forward its arguments. Are you concerned that P[A-M] could > > conflict with something else in the device tree? > > There's indeed a bunch of names that are fairly generic and could be > conflicting with others (PD for power domain is the first one that comes > to my mind). Using a prefix would make the GPIO descriptors pretty long, > so it wasn't ideal either. A macro makes it readable without increasing > too much the risks of conflicts I tried to use macros, but failed. I have a look at some other GPIO macros, which have a prefix in front of them. Maybe we can do the same? It's all numbers. It's not intuitive. Yangtao
Re: [PATCH 2/3] opp: Add devres wrapper for dev_pm_opp_set_prop_name
On Wed, Oct 28, 2020 at 6:29 PM Viresh Kumar wrote: > > On 12-10-20, 21:55, Frank Lee wrote: > > From: Yangtao Li > > > > Add devres wrapper for dev_pm_opp_set_prop_name() to simplify driver > > code. > > > > Signed-off-by: Yangtao Li > > Signed-off-by: Yangtao Li > > --- > > drivers/opp/core.c | 39 +++ > > include/linux/pm_opp.h | 6 ++ > > 2 files changed, 45 insertions(+) > > On a second thought I am looking at dropping this one as you haven't > added any users yet and I am afraid it will stay unused. Now it looks like that dev_pm_opp_set_prop_name() is used relatively less. Maybe we can wait until a caller, and then pick up the patch. MBR, Yangtao
[PATCH] thermal: sun8i: Use bitmap API instead of open code
From: Yangtao Li
Thw bitmap_* API is the standard way to access data in the bitfield.
Signed-off-by: Yangtao Li
---
drivers/thermal/sun8i_thermal.c | 35 +
1 file changed, 18 insertions(+), 17 deletions(-)
diff --git a/drivers/thermal/sun8i_thermal.c b/drivers/thermal/sun8i_thermal.c
index f8b13071a6f4..f2e4a4f18101 100644
--- a/drivers/thermal/sun8i_thermal.c
+++ b/drivers/thermal/sun8i_thermal.c
@@ -8,6 +8,7 @@
* Based on the work of Josef Gajdusek
*/
+#include
#include
#include
#include
@@ -74,7 +75,7 @@ struct ths_thermal_chip {
int (*calibrate)(struct ths_device *tmdev,
u16 *caldata, int callen);
int (*init)(struct ths_device *tmdev);
- int (*irq_ack)(struct ths_device *tmdev);
+ void(*irq_ack)(struct ths_device *tmdev);
int (*calc_temp)(struct ths_device *tmdev,
int id, int reg);
};
@@ -82,6 +83,7 @@ struct ths_thermal_chip {
struct ths_device {
const struct ths_thermal_chip *chip;
struct device *dev;
+ DECLARE_BITMAP(irq_bitmap, MAX_SENSOR_NUM);
struct regmap *regmap;
struct reset_control*reset;
struct clk *bus_clk;
@@ -146,9 +148,11 @@ static const struct regmap_config config = {
.max_register = 0xfc,
};
-static int sun8i_h3_irq_ack(struct ths_device *tmdev)
+static void sun8i_h3_irq_ack(struct ths_device *tmdev)
{
- int i, state, ret = 0;
+ int i, state;
+
+ bitmap_zero(tmdev->irq_bitmap, tmdev->chip->sensor_num);
regmap_read(tmdev->regmap, SUN8I_THS_IS, );
@@ -156,16 +160,16 @@ static int sun8i_h3_irq_ack(struct ths_device *tmdev)
if (state & SUN8I_THS_DATA_IRQ_STS(i)) {
regmap_write(tmdev->regmap, SUN8I_THS_IS,
SUN8I_THS_DATA_IRQ_STS(i));
- ret |= BIT(i);
+ bitmap_set(tmdev->irq_bitmap, i, 1);
}
}
-
- return ret;
}
-static int sun50i_h6_irq_ack(struct ths_device *tmdev)
+static void sun50i_h6_irq_ack(struct ths_device *tmdev)
{
- int i, state, ret = 0;
+ int i, state;
+
+ bitmap_zero(tmdev->irq_bitmap, tmdev->chip->sensor_num);
regmap_read(tmdev->regmap, SUN50I_H6_THS_DIS, );
@@ -173,24 +177,21 @@ static int sun50i_h6_irq_ack(struct ths_device *tmdev)
if (state & SUN50I_H6_THS_DATA_IRQ_STS(i)) {
regmap_write(tmdev->regmap, SUN50I_H6_THS_DIS,
SUN50I_H6_THS_DATA_IRQ_STS(i));
- ret |= BIT(i);
+ bitmap_set(tmdev->irq_bitmap, i, 1);
}
}
-
- return ret;
}
static irqreturn_t sun8i_irq_thread(int irq, void *data)
{
struct ths_device *tmdev = data;
- int i, state;
+ int i;
- state = tmdev->chip->irq_ack(tmdev);
+ tmdev->chip->irq_ack(tmdev);
- for (i = 0; i < tmdev->chip->sensor_num; i++) {
- if (state & BIT(i))
- thermal_zone_device_update(tmdev->sensor[i].tzd,
- THERMAL_EVENT_UNSPECIFIED);
+ for_each_set_bit(i, tmdev->irq_bitmap, tmdev->chip->sensor_num) {
+ thermal_zone_device_update(tmdev->sensor[i].tzd,
+ THERMAL_EVENT_UNSPECIFIED);
}
return IRQ_HANDLED;
--
2.28.0
[PATCH] cpufreq: sti-cpufreq: fix mem leak in sti_cpufreq_set_opp_info()
From: Yangtao Li
Use dev_pm_opp_put_prop_name() to avoid mem leak, which free opp_table.
Signed-off-by: Yangtao Li
Signed-off-by: Yangtao Li
---
drivers/cpufreq/sti-cpufreq.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/cpufreq/sti-cpufreq.c b/drivers/cpufreq/sti-cpufreq.c
index a5ad96d29adc..9668a48dad33 100644
--- a/drivers/cpufreq/sti-cpufreq.c
+++ b/drivers/cpufreq/sti-cpufreq.c
@@ -222,7 +222,8 @@ static int sti_cpufreq_set_opp_info(void)
opp_table = dev_pm_opp_set_supported_hw(dev, version, VERSION_ELEMENTS);
if (IS_ERR(opp_table)) {
dev_err(dev, "Failed to set supported hardware\n");
- return PTR_ERR(opp_table);
+ ret = PTR_ERR(opp_table);
+ goto err_put_prop_name;
}
dev_dbg(dev, "pcode: %d major: %d minor: %d substrate: %d\n",
@@ -231,6 +232,10 @@ static int sti_cpufreq_set_opp_info(void)
version[0], version[1], version[2]);
return 0;
+
+err_put_prop_name:
+ dev_pm_opp_put_prop_name(opp_table);
+ return ret;
}
static int sti_cpufreq_fetch_syscon_registers(void)
--
2.28.0
[PATCH 3/3] drm/msm: Convert to devm_pm_opp_set_supported_hw
From: Yangtao Li Use the devm_pm_opp_set_supported_hw() to avoid memory leaks in some cases. Signed-off-by: Yangtao Li Signed-off-by: Yangtao Li --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index 91726da82ed6..8d88f119a59f 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -1487,7 +1487,7 @@ static void check_speed_bin(struct device *dev) nvmem_cell_put(cell); } - dev_pm_opp_set_supported_hw(dev, , 1); + devm_pm_opp_set_supported_hw(dev, , 1); } struct msm_gpu *a5xx_gpu_init(struct drm_device *dev) -- 2.28.0
[PATCH 1/3] opp: Add devres wrapper for dev_pm_opp_set_supported_hw
From: Yangtao Li
Add devres wrapper for dev_pm_opp_set_supported_hw() to simplify driver
code.
Signed-off-by: Yangtao Li
Signed-off-by: Yangtao Li
---
drivers/opp/core.c | 41 +
include/linux/pm_opp.h | 8
2 files changed, 49 insertions(+)
diff --git a/drivers/opp/core.c b/drivers/opp/core.c
index 3ca7543142bf..b38852dde578 100644
--- a/drivers/opp/core.c
+++ b/drivers/opp/core.c
@@ -1625,6 +1625,47 @@ void dev_pm_opp_put_supported_hw(struct opp_table
*opp_table)
}
EXPORT_SYMBOL_GPL(dev_pm_opp_put_supported_hw);
+static void devm_pm_opp_put_supported_hw(struct device *dev, void *res)
+{
+ dev_pm_opp_put_supported_hw(*(struct opp_table **)res);
+}
+
+/**
+ * devm_pm_opp_set_supported_hw() - Set supported platforms
+ * @dev: Device for which supported-hw has to be set.
+ * @versions: Array of hierarchy of versions to match.
+ * @count: Number of elements in the array.
+ *
+ * This is required only for the V2 bindings, and it enables a platform to
+ * specify the hierarchy of versions it supports. OPP layer will then enable
+ * OPPs, which are available for those versions, based on its
'opp-supported-hw'
+ * property.
+ *
+ * The opp_table structure will be freed after the device is destroyed.
+ */
+struct opp_table *devm_pm_opp_set_supported_hw(struct device *dev,
+ const u32 *versions,
+ unsigned int count)
+{
+ struct opp_table **ptr, *opp_table;
+
+ ptr = devres_alloc(devm_pm_opp_put_supported_hw,
+ sizeof(*ptr), GFP_KERNEL);
+ if (!ptr)
+ return ERR_PTR(-ENOMEM);
+
+ opp_table = dev_pm_opp_set_supported_hw(dev, versions, count);
+ if (!IS_ERR(opp_table)) {
+ *ptr = opp_table;
+ devres_add(dev, ptr);
+ } else {
+ devres_free(ptr);
+ }
+
+ return opp_table;
+}
+EXPORT_SYMBOL(devm_pm_opp_set_supported_hw);
+
/**
* dev_pm_opp_set_prop_name() - Set prop-extn name
* @dev: Device for which the prop-name has to be set.
diff --git a/include/linux/pm_opp.h b/include/linux/pm_opp.h
index dbb484524f82..901920e29c54 100644
--- a/include/linux/pm_opp.h
+++ b/include/linux/pm_opp.h
@@ -140,6 +140,7 @@ int dev_pm_opp_unregister_notifier(struct device *dev,
struct notifier_block *nb
struct opp_table *dev_pm_opp_set_supported_hw(struct device *dev, const u32
*versions, unsigned int count);
void dev_pm_opp_put_supported_hw(struct opp_table *opp_table);
+struct opp_table *devm_pm_opp_set_supported_hw(struct device *dev, const u32
*versions, unsigned int count);
struct opp_table *dev_pm_opp_set_prop_name(struct device *dev, const char
*name);
void dev_pm_opp_put_prop_name(struct opp_table *opp_table);
struct opp_table *dev_pm_opp_set_regulators(struct device *dev, const char *
const names[], unsigned int count);
@@ -298,6 +299,13 @@ static inline struct opp_table
*dev_pm_opp_set_supported_hw(struct device *dev,
static inline void dev_pm_opp_put_supported_hw(struct opp_table *opp_table) {}
+static inline struct opp_table *devm_pm_opp_set_supported_hw(struct device
*dev,
+const u32
*versions,
+unsigned int count)
+{
+ return ERR_PTR(-ENOTSUPP);
+}
+
static inline struct opp_table *dev_pm_opp_register_set_opp_helper(struct
device *dev,
int (*set_opp)(struct dev_pm_set_opp_data *data))
{
--
2.28.0
[PATCH 0/3] Introduce devm_pm_opp_set_* API
Hi, this patchset introduce devm_pm_opp_set_prop_name() and devm_pm_opp_set_supported_hw(). Yangtao Li (3): opp: Add devres wrapper for dev_pm_opp_set_supported_hw opp: Add devres wrapper for dev_pm_opp_set_prop_name drm/msm: Convert to devm_pm_opp_set_supported_hw drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 2 +- drivers/opp/core.c| 80 +++ include/linux/pm_opp.h| 14 + 3 files changed, 95 insertions(+), 1 deletion(-) -- 2.28.0
[PATCH 2/3] opp: Add devres wrapper for dev_pm_opp_set_prop_name
From: Yangtao Li
Add devres wrapper for dev_pm_opp_set_prop_name() to simplify driver
code.
Signed-off-by: Yangtao Li
Signed-off-by: Yangtao Li
---
drivers/opp/core.c | 39 +++
include/linux/pm_opp.h | 6 ++
2 files changed, 45 insertions(+)
diff --git a/drivers/opp/core.c b/drivers/opp/core.c
index b38852dde578..3263fa8302c9 100644
--- a/drivers/opp/core.c
+++ b/drivers/opp/core.c
@@ -1721,6 +1721,45 @@ void dev_pm_opp_put_prop_name(struct opp_table
*opp_table)
}
EXPORT_SYMBOL_GPL(dev_pm_opp_put_prop_name);
+static void devm_pm_opp_put_prop_name(struct device *dev, void *res)
+{
+ dev_pm_opp_put_prop_name(*(struct opp_table **)res);
+}
+
+/**
+ * devm_pm_opp_set_prop_name() - Set prop-extn name
+ * @dev: Device for which the prop-name has to be set.
+ * @name: name to postfix to properties.
+ *
+ * This is required only for the V2 bindings, and it enables a platform to
+ * specify the extn to be used for certain property names. The properties to
+ * which the extension will apply are opp-microvolt and opp-microamp. OPP core
+ * should postfix the property name with - while looking for them.
+ *
+ * The opp_table structure will be freed after the device is destroyed.
+ */
+struct opp_table *devm_pm_opp_set_prop_name(struct device *dev,
+ const char *name)
+{
+ struct opp_table **ptr, *opp_table;
+
+ ptr = devres_alloc(devm_pm_opp_put_prop_name,
+ sizeof(*ptr), GFP_KERNEL);
+ if (!ptr)
+ return ERR_PTR(-ENOMEM);
+
+ opp_table = dev_pm_opp_set_prop_name(dev, name);
+ if (!IS_ERR(opp_table)) {
+ *ptr = opp_table;
+ devres_add(dev, ptr);
+ } else {
+ devres_free(ptr);
+ }
+
+ return opp_table;
+}
+EXPORT_SYMBOL(devm_pm_opp_set_prop_name);
+
static int _allocate_set_opp_data(struct opp_table *opp_table)
{
struct dev_pm_set_opp_data *data;
diff --git a/include/linux/pm_opp.h b/include/linux/pm_opp.h
index 901920e29c54..1708485200dd 100644
--- a/include/linux/pm_opp.h
+++ b/include/linux/pm_opp.h
@@ -143,6 +143,7 @@ void dev_pm_opp_put_supported_hw(struct opp_table
*opp_table);
struct opp_table *devm_pm_opp_set_supported_hw(struct device *dev, const u32
*versions, unsigned int count);
struct opp_table *dev_pm_opp_set_prop_name(struct device *dev, const char
*name);
void dev_pm_opp_put_prop_name(struct opp_table *opp_table);
+struct opp_table *devm_pm_opp_set_prop_name(struct device *dev, const char
*name);
struct opp_table *dev_pm_opp_set_regulators(struct device *dev, const char *
const names[], unsigned int count);
void dev_pm_opp_put_regulators(struct opp_table *opp_table);
struct opp_table *dev_pm_opp_set_clkname(struct device *dev, const char *
name);
@@ -321,6 +322,11 @@ static inline struct opp_table
*dev_pm_opp_set_prop_name(struct device *dev, con
static inline void dev_pm_opp_put_prop_name(struct opp_table *opp_table) {}
+static inline struct opp_table *devm_pm_opp_set_prop_name(struct device *dev,
const char *name)
+{
+ return ERR_PTR(-ENOTSUPP);
+}
+
static inline struct opp_table *dev_pm_opp_set_regulators(struct device *dev,
const char * const names[], unsigned int count)
{
return ERR_PTR(-ENOTSUPP);
--
2.28.0
Re: [PATCH v5 00/16] Allwinner A100 Initial support
HI Linus, On Fri, Aug 28, 2020 at 6:02 PM Linus Walleij wrote: > > On Fri, Jul 24, 2020 at 8:53 AM Frank Lee wrote: > > > This patch set adds initial support for allwinner a100 soc, > > which is a 64-bit tablet chip. > > Shall I commit the pinctrl patches (if Maxime ACKed) separately > or not? Once Maxime is happy, I am usually happy too. Maxime told me he wanted you to commit the pinctrl patches. Thx, Yangtao
[PATCH] sched: idle: Change the cpu_idle_poll() return type to void
From: Yangtao Li
No one cares about the return value of this function, which only
increases the time spent in idle loop. Let's drop it.
Signed-off-by: Yangtao Li
---
kernel/sched/idle.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/kernel/sched/idle.c b/kernel/sched/idle.c
index 6bf34986f45c..5250a7c466e6 100644
--- a/kernel/sched/idle.c
+++ b/kernel/sched/idle.c
@@ -52,7 +52,7 @@ static int __init cpu_idle_nopoll_setup(char *__unused)
__setup("hlt", cpu_idle_nopoll_setup);
#endif
-static noinline int __cpuidle cpu_idle_poll(void)
+static noinline void __cpuidle cpu_idle_poll(void)
{
rcu_idle_enter();
trace_cpu_idle_rcuidle(0, smp_processor_id());
@@ -65,8 +65,6 @@ static noinline int __cpuidle cpu_idle_poll(void)
start_critical_timings();
trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
rcu_idle_exit();
-
- return 1;
}
/* Weak implementations for optional arch specific functions */
--
2.28.0
[PATCH] sched: idle: Change the cpu_idle_poll() return type to void
From: Yangtao Li
No one cares about the return value of this function, which only
increases the time spent in idle loop. Let's drop it.
Signed-off-by: Yangtao Li
---
kernel/sched/idle.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/kernel/sched/idle.c b/kernel/sched/idle.c
index 6bf34986f45c..5250a7c466e6 100644
--- a/kernel/sched/idle.c
+++ b/kernel/sched/idle.c
@@ -52,7 +52,7 @@ static int __init cpu_idle_nopoll_setup(char *__unused)
__setup("hlt", cpu_idle_nopoll_setup);
#endif
-static noinline int __cpuidle cpu_idle_poll(void)
+static noinline void __cpuidle cpu_idle_poll(void)
{
rcu_idle_enter();
trace_cpu_idle_rcuidle(0, smp_processor_id());
@@ -65,8 +65,6 @@ static noinline int __cpuidle cpu_idle_poll(void)
start_critical_timings();
trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
rcu_idle_exit();
-
- return 1;
}
/* Weak implementations for optional arch specific functions */
--
2.28.0
Re: [PATCH v5 00/16] Allwinner A100 Initial support
ping..
Re: [PATCH v5 00/16] Allwinner A100 Initial support
HI Maxime, Any comments on thermal and other patches? I hope these patches can be integrated into the mainline as soon as possible. Thx, Yangtao
[PATCH v5 16/16] arm64: allwinner: A100: add support for Allwinner Perf1 board
From: Yangtao Li
A100 perf1 is an Allwinner A100-based SBC, with the following features:
- 1GiB DDR3 DRAM
- AXP803 PMIC
- 2 USB 2.0 ports
- MicroSD slot and on-board eMMC module
- on-board Nand flash
- ···
Adds initial support for it, including UART and PMU.
Signed-off-by: Yangtao Li
---
arch/arm64/boot/dts/allwinner/Makefile| 1 +
.../allwinner/sun50i-a100-allwinner-perf1.dts | 180 ++
2 files changed, 181 insertions(+)
create mode 100644
arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
diff --git a/arch/arm64/boot/dts/allwinner/Makefile
b/arch/arm64/boot/dts/allwinner/Makefile
index e4d3cd0ac5bb..ab780dbdd17b 100644
--- a/arch/arm64/boot/dts/allwinner/Makefile
+++ b/arch/arm64/boot/dts/allwinner/Makefile
@@ -14,6 +14,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinephone-1.1.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinetab.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-sopine-baseboard.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-teres-i.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a100-allwinner-perf1.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-bananapi-m2-plus.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-bananapi-m2-plus-v1.2.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-emlid-neutis-n5-devboard.dtb
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
new file mode 100644
index ..d34c2bb1079f
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
@@ -0,0 +1,180 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Copyright (c) 2020 Yangtao Li
+ */
+
+/dts-v1/;
+
+#include "sun50i-a100.dtsi"
+
+/{
+ model = "Allwinner A100 Perf1";
+ compatible = "allwinner,a100-perf1", "allwinner,sun50i-a100";
+
+ aliases {
+ serial0 =
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+ {
+ vcc-pb-supply = <_dcdc1>;
+ vcc-pc-supply = <_eldo1>;
+ vcc-pd-supply = <_dcdc1>;
+ vcc-pe-supply = <_dldo2>;
+ vcc-pf-supply = <_dcdc1>;
+ vcc-pg-supply = <_dldo1>;
+ vcc-ph-supply = <_dcdc1>;
+};
+
+_pio {
+ /*
+* FIXME: We can't add that supply for now since it would
+* create a circular dependency between pinctrl, the regulator
+* and the RSB Bus.
+*
+* vcc-pl-supply = <_aldo3>;
+*/
+};
+
+_i2c0 {
+ status = "okay";
+
+ axp803: pmic@34 {
+ compatible = "x-powers,axp803";
+ reg = <0x34>;
+ interrupt-parent = <_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ x-powers,drive-vbus-en; /* set N_VBUSEN as output pin */
+ };
+};
+
+#include "axp803.dtsi"
+
+_power_supply {
+ status = "okay";
+};
+
+_aldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+ regulator-name = "vcc-pll-avcc";
+};
+
+_aldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+ regulator-name = "vcc-dram-1";
+};
+
+_aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ regulator-name = "vcc-usb-pl";
+};
+
+_dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ regulator-name = "vcc-io-usb-pd-emmc-nand-card";
+};
+
+_dcdc2 {
+ regulator-always-on;
+ /*
+* FIXME: update min and max before support dvfs.
+*/
+ regulator-min-microvolt = <50>;
+ regulator-max-microvolt = <130>;
+ regulator-name = "vdd-cpux";
+};
+
+/* DCDC3 is polyphased with DCDC2 */
+
+_dcdc4 {
+ regulator-always-on;
+ regulator-min-microvolt = <95>;
+ regulator-max-microvolt = <95>;
+ regulator-name = "vdd-sys-usb-dram";
+};
+
+_dcdc5 {
+ regulator-always-on;
+ regulator-min-microvolt = <150>;
+ regulator-max-microvolt = <150>;
+ regulator-name = "vcc-dram-2";
+};
+
+_dldo1 {
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ regulator-name = "vcc-pg-dcxo-wifi";
+};
+
+_dldo2 {
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <280>;
+ regulator-name = "vcc-pe-csi";
+};
+
+_dldo3 {
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <330>;
+ regulator-name = "ldo-avdd-csi";
+};
+
+_dldo4 {
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <280>;
+ regulator-name = "avcc-csi";
+};
+
+_eldo1 {
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+ regulator-name = "vcc-pc-lvds-csi-efuse-emmc-nand";
+};
+
+_eldo2 {
+
[PATCH v5 15/16] dt-bindings: arm: sunxi: Add Allwinner A100 Perf1 Board bindings
From: Yangtao Li Document board compatible names for Allwinner A100 Perf1 Board. Signed-off-by: Yangtao Li Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/arm/sunxi.yaml | 5 + 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index 87817ff0cd35..dbec66c1377a 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -16,6 +16,11 @@ properties: compatible: oneOf: + - description: Allwinner A100 Perf1 Board +items: + - const: allwinner,a100-perf1 + - const: allwinner,sun50i-a100 + - description: Allwinner A23 Evaluation Board items: - const: allwinner,sun8i-a23-evb -- 2.24.0
[PATCH v5 14/16] arm64: allwinner: A100: add the basical Allwinner A100 DTSI file
From: Yangtao Li
Allwinner A100 is a new SoC with Cortex-A53 cores, this commit adds
the basical DTSI file of it, including the clock, i2c, pins, sid, ths,
nmi, and UART support.
Signed-off-by: Yangtao Li
---
.../arm64/boot/dts/allwinner/sun50i-a100.dtsi | 364 ++
1 file changed, 364 insertions(+)
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
new file mode 100644
index ..cc321c04f121
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
@@ -0,0 +1,364 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Copyright (c) 2020 Yangtao Li
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+/ {
+ interrupt-parent = <>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <0x0>;
+ enable-method = "psci";
+ };
+
+ cpu@1 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <0x1>;
+ enable-method = "psci";
+ };
+
+ cpu@2 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <0x2>;
+ enable-method = "psci";
+ };
+
+ cpu@3 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <0x3>;
+ enable-method = "psci";
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ dcxo24M: dcxo24M-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <2400>;
+ clock-output-names = "dcxo24M";
+ #clock-cells = <0>;
+ };
+
+ iosc: internal-osc-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <1600>;
+ clock-accuracy = <3>;
+ clock-output-names = "iosc";
+ #clock-cells = <0>;
+ };
+
+ osc32k: osc32k-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "osc32k";
+ #clock-cells = <0>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = ,
+,
+,
+;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0 0x3fff>;
+
+ ccu: clock@3001000 {
+ compatible = "allwinner,sun50i-a100-ccu";
+ reg = <0x03001000 0x1000>;
+ clocks = <>, <>, <>;
+ clock-names = "hosc", "losc", "iosc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ gic: interrupt-controller@3021000 {
+ compatible = "arm,gic-400";
+ reg = <0x03021000 0x1000>, <0x03022000 0x2000>,
+ <0x03024000 0x2000>, <0x03026000 0x2000>;
+ interrupts = ;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
+
+ efuse@3006000 {
+ compatible = "allwinner,sun50i-a100-sid",
+"allwinner,sun50i-a64-sid";
+ reg = <0x03006000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ths_calibration: calib@14 {
+ reg = <0x14 8>;
+ };
+ };
+
+ pio: pinctrl@300b000 {
+ compatible = "allwinner,sun50i-a100-pinctrl";
+ reg = <0x0300b000 0x400>;
+ interrupts = ,
+,
+,
+,
+,
+,
+;
+ clocks = < CLK_APB1>, <>, <>;
+ clock-names = "apb", "hosc", "losc";
+ gpio-controller;
+ #gpio-cells = <3>;
+ interrupt-controller;
+
[PATCH v5 13/16] dt-bindings: i2c: mv64xxx: Add compatible for the A100 i2c node.
From: Yangtao Li Allwinner A100 have a mv64xxx i2c interface available to be used. Signed-off-by: Yangtao Li Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml b/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml index 2ceb05ba2df5..5b5ae402f97a 100644 --- a/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml @@ -26,6 +26,9 @@ properties: - items: - const: allwinner,sun50i-a64-i2c - const: allwinner,sun6i-a31-i2c + - items: + - const: allwinner,sun50i-a100-i2c + - const: allwinner,sun6i-a31-i2c - items: - const: allwinner,sun50i-h6-i2c - const: allwinner,sun6i-a31-i2c -- 2.24.0
[PATCH v5 12/16] dt-bindings: irq: sun7i-nmi: Add binding for A100's NMI controller
From: Yangtao Li Add a binding for A100's nmi controller. Signed-off-by: Yangtao Li Acked-by: Rob Herring --- .../interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml index d8fe2d9a307b..8acca0ae3129 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml @@ -33,6 +33,9 @@ properties: - items: - const: allwinner,sun50i-a64-r-intc - const: allwinner,sun6i-a31-r-intc + - items: + - const: allwinner,sun50i-a100-nmi + - const: allwinner,sun9i-a80-nmi - items: - const: allwinner,sun50i-h6-r-intc - const: allwinner,sun6i-a31-r-intc -- 2.24.0
[PATCH v5 11/16] dt-bindings: irq: sun7i-nmi: fix dt-binding for a80 nmi
From: Yangtao Li There is no one use "allwinner,sun9i-a80-sc-nmi". The A80 uses "allwinner,sun9i-a80-nmi". Let's fix it. Signed-off-by: Yangtao Li Acked-by: Rob Herring --- .../interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml| 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml index 7cd6b8bacfa0..d8fe2d9a307b 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml @@ -29,7 +29,7 @@ properties: - items: - const: allwinner,sun8i-a83t-r-intc - const: allwinner,sun6i-a31-r-intc - - const: allwinner,sun9i-a80-sc-nmi + - const: allwinner,sun9i-a80-nmi - items: - const: allwinner,sun50i-a64-r-intc - const: allwinner,sun6i-a31-r-intc -- 2.24.0
[PATCH v5 10/16] mfd: axp20x: Allow the AXP803 to be probed by I2C
From: Yangtao Li
The AXP803 can be used both using the RSB proprietary bus, or a more
traditional I2C bus.
Let's add that possibility.
Signed-off-by: Yangtao Li
Acked-by: Chen-Yu Tsai
---
drivers/mfd/axp20x-i2c.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mfd/axp20x-i2c.c b/drivers/mfd/axp20x-i2c.c
index 14f9df74f855..446a7d0bbb47 100644
--- a/drivers/mfd/axp20x-i2c.c
+++ b/drivers/mfd/axp20x-i2c.c
@@ -63,6 +63,7 @@ static const struct of_device_id axp20x_i2c_of_match[] = {
{ .compatible = "x-powers,axp209", .data = (void *)AXP209_ID },
{ .compatible = "x-powers,axp221", .data = (void *)AXP221_ID },
{ .compatible = "x-powers,axp223", .data = (void *)AXP223_ID },
+ { .compatible = "x-powers,axp803", .data = (void *)AXP803_ID },
{ .compatible = "x-powers,axp806", .data = (void *)AXP806_ID },
{ },
};
@@ -74,6 +75,7 @@ static const struct i2c_device_id axp20x_i2c_id[] = {
{ "axp209", 0 },
{ "axp221", 0 },
{ "axp223", 0 },
+ { "axp803", 0 },
{ "axp806", 0 },
{ },
};
--
2.24.0
[PATCH v5 08/16] thermal: sun8i: add TEMP_CALIB_MASK for calibration data in sun50i_h6_ths_calibrate
From: Yangtao Li
For sun50i_h6_ths_calibrate(), the data read from nvmem needs a round of
calculation. On the other hand, the newer SOC may store other data in
the space other than 12bit sensor data. Add mask operation to read data
to avoid conversion error.
Signed-off-by: Yangtao Li
---
drivers/thermal/sun8i_thermal.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/thermal/sun8i_thermal.c b/drivers/thermal/sun8i_thermal.c
index 74d73be16496..f423d44b9290 100644
--- a/drivers/thermal/sun8i_thermal.c
+++ b/drivers/thermal/sun8i_thermal.c
@@ -244,7 +244,7 @@ static int sun50i_h6_ths_calibrate(struct ths_device *tmdev,
ft_temp = (caldata[0] & FT_TEMP_MASK) * 100;
for (i = 0; i < tmdev->chip->sensor_num; i++) {
- int sensor_reg = caldata[i + 1];
+ int sensor_reg = caldata[i + 1] & TEMP_CALIB_MASK;
int cdata, offset;
int sensor_temp = tmdev->chip->calc_temp(tmdev, i, sensor_reg);
--
2.24.0
[PATCH v5 09/16] thermal: sun8i: Add A100's THS controller support
From: Yangtao Li
This patch add thermal sensor controller support for A100,
which is similar to the previous ones.
Signed-off-by: Yangtao Li
---
drivers/thermal/sun8i_thermal.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/thermal/sun8i_thermal.c b/drivers/thermal/sun8i_thermal.c
index f423d44b9290..f8b13071a6f4 100644
--- a/drivers/thermal/sun8i_thermal.c
+++ b/drivers/thermal/sun8i_thermal.c
@@ -590,6 +590,19 @@ static const struct ths_thermal_chip sun50i_a64_ths = {
.calc_temp = sun8i_ths_calc_temp,
};
+static const struct ths_thermal_chip sun50i_a100_ths = {
+ .sensor_num = 3,
+ .has_bus_clk_reset = true,
+ .ft_deviation = 8000,
+ .offset = 187744,
+ .scale = 672,
+ .temp_data_base = SUN50I_H6_THS_TEMP_DATA,
+ .calibrate = sun50i_h6_ths_calibrate,
+ .init = sun50i_h6_thermal_init,
+ .irq_ack = sun50i_h6_irq_ack,
+ .calc_temp = sun8i_ths_calc_temp,
+};
+
static const struct ths_thermal_chip sun50i_h5_ths = {
.sensor_num = 2,
.has_mod_clk = true,
@@ -619,6 +632,7 @@ static const struct of_device_id of_ths_match[] = {
{ .compatible = "allwinner,sun8i-h3-ths", .data = _h3_ths },
{ .compatible = "allwinner,sun8i-r40-ths", .data = _r40_ths },
{ .compatible = "allwinner,sun50i-a64-ths", .data = _a64_ths },
+ { .compatible = "allwinner,sun50i-a100-ths", .data = _a100_ths },
{ .compatible = "allwinner,sun50i-h5-ths", .data = _h5_ths },
{ .compatible = "allwinner,sun50i-h6-ths", .data = _h6_ths },
{ /* sentinel */ },
--
2.24.0
[PATCH v5 07/16] dt-bindings: thermal: sun8i: Add binding for A100's THS controller
From: Yangtao Li Add a binding for A100's ths controller. Signed-off-by: Yangtao Li Reviewed-by: Rob Herring --- .../bindings/thermal/allwinner,sun8i-a83t-ths.yaml | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml b/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml index 87369264feb9..9d40fc7ff6fd 100644 --- a/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml +++ b/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml @@ -17,6 +17,7 @@ properties: - allwinner,sun8i-h3-ths - allwinner,sun8i-r40-ths - allwinner,sun50i-a64-ths + - allwinner,sun50i-a100-ths - allwinner,sun50i-h5-ths - allwinner,sun50i-h6-ths @@ -61,7 +62,9 @@ allOf: properties: compatible: contains: -const: allwinner,sun50i-h6-ths +enum: + - allwinner,sun50i-a100-ths + - allwinner,sun50i-h6-ths then: properties: @@ -103,6 +106,7 @@ allOf: - const: allwinner,sun8i-h3-ths - const: allwinner,sun8i-r40-ths - const: allwinner,sun50i-a64-ths + - const: allwinner,sun50i-a100-ths - const: allwinner,sun50i-h5-ths - const: allwinner,sun50i-h6-ths -- 2.24.0
[PATCH v5 06/16] dt-bindings: nvmem: SID: add binding for A100's SID controller
From: Yangtao Li Add a binding for A100's SID controller. Signed-off-by: Yangtao Li Reviewed-by: Rob Herring --- .../nvmem/allwinner,sun4i-a10-sid.yaml| 19 +++ 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/nvmem/allwinner,sun4i-a10-sid.yaml b/Documentation/devicetree/bindings/nvmem/allwinner,sun4i-a10-sid.yaml index daf1321d76ad..6687ab720304 100644 --- a/Documentation/devicetree/bindings/nvmem/allwinner,sun4i-a10-sid.yaml +++ b/Documentation/devicetree/bindings/nvmem/allwinner,sun4i-a10-sid.yaml @@ -15,14 +15,17 @@ allOf: properties: compatible: -enum: - - allwinner,sun4i-a10-sid - - allwinner,sun7i-a20-sid - - allwinner,sun8i-a83t-sid - - allwinner,sun8i-h3-sid - - allwinner,sun50i-a64-sid - - allwinner,sun50i-h5-sid - - allwinner,sun50i-h6-sid +oneOf: + - const: allwinner,sun4i-a10-sid + - const: allwinner,sun7i-a20-sid + - const: allwinner,sun8i-a83t-sid + - const: allwinner,sun8i-h3-sid + - const: allwinner,sun50i-a64-sid + - items: + - const: allwinner,sun50i-a100-sid + - const: allwinner,sun50i-a64-sid + - const: allwinner,sun50i-h5-sid + - const: allwinner,sun50i-h6-sid reg: maxItems: 1 -- 2.24.0
[PATCH v5 05/16] pinctrl: sunxi: add support for the Allwinner A100 pin controller
From: Yangtao Li
This commit introduces support for the pin controller on A100.
Signed-off-by: Yangtao Li
---
drivers/pinctrl/sunxi/Kconfig | 10 +
drivers/pinctrl/sunxi/Makefile| 2 +
drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c | 105 +++
drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c | 708 ++
4 files changed, 825 insertions(+)
create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c
create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index f7aae200ee15..593293584ecc 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -94,6 +94,16 @@ config PINCTRL_SUN50I_A64_R
default ARM64 && ARCH_SUNXI
select PINCTRL_SUNXI
+config PINCTRL_SUN50I_A100
+ bool "Support for the Allwinner A100 PIO"
+ default ARM64 && ARCH_SUNXI
+ select PINCTRL_SUNXI
+
+config PINCTRL_SUN50I_A100_R
+ bool "Support for the Allwinner A100 R-PIO"
+ default ARM64 && ARCH_SUNXI
+ select PINCTRL_SUNXI
+
config PINCTRL_SUN50I_H5
bool "Support for the Allwinner H5 PIO"
default ARM64 && ARCH_SUNXI
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
index fafcdae8134f..8b7ff0dc3bdf 100644
--- a/drivers/pinctrl/sunxi/Makefile
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -13,6 +13,8 @@ obj-$(CONFIG_PINCTRL_SUN8I_A23_R) += pinctrl-sun8i-a23-r.o
obj-$(CONFIG_PINCTRL_SUN8I_A33)+= pinctrl-sun8i-a33.o
obj-$(CONFIG_PINCTRL_SUN50I_A64) += pinctrl-sun50i-a64.o
obj-$(CONFIG_PINCTRL_SUN50I_A64_R) += pinctrl-sun50i-a64-r.o
+obj-$(CONFIG_PINCTRL_SUN50I_A100) += pinctrl-sun50i-a100.o
+obj-$(CONFIG_PINCTRL_SUN50I_A100_R)+= pinctrl-sun50i-a100-r.o
obj-$(CONFIG_PINCTRL_SUN8I_A83T) += pinctrl-sun8i-a83t.o
obj-$(CONFIG_PINCTRL_SUN8I_A83T_R) += pinctrl-sun8i-a83t-r.o
obj-$(CONFIG_PINCTRL_SUN8I_H3) += pinctrl-sun8i-h3.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c
b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c
new file mode 100644
index ..21054fcacd34
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2020 Yangtao Li
+ *
+ * Based on:
+ * huangshuosheng
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include "pinctrl-sunxi.h"
+
+static const struct sunxi_desc_pin a100_r_pins[] = {
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_i2c0"),/* SCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_i2c0"),/* SDA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_uart0"), /* TX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_uart0"), /* RX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_jtag"),/* MS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_jtag"),/* CK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_jtag"),/* DO */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_jtag"),/* DI */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_i2c1"),/* SCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9),
+ SUNXI_FUNCTION(0x0,
[PATCH v5 04/16] dt-bindings: pinctrl: sunxi: Add A100 pinctrl bindings
From: Yangtao Li Add device tree binding Documentation details for A100 pinctrl driver, which has a r pin controller and a pin controller with more irq lines. Signed-off-by: Yangtao Li Reviewed-by: Rob Herring --- .../pinctrl/allwinner,sun4i-a10-pinctrl.yaml | 15 +++ 1 file changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml index 35a26abb02e7..34a17d5c6135 100644 --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml @@ -48,6 +48,8 @@ properties: - allwinner,sun9i-a80-r-pinctrl - allwinner,sun50i-a64-pinctrl - allwinner,sun50i-a64-r-pinctrl + - allwinner,sun50i-a100-pinctrl + - allwinner,sun50i-a100-r-pinctrl - allwinner,sun50i-h5-pinctrl - allwinner,sun50i-h6-pinctrl - allwinner,sun50i-h6-r-pinctrl @@ -143,6 +145,18 @@ allOf: # boards are defining it at the moment so it would generate a lot of # warnings. + - if: + properties: +compatible: + enum: +- allwinner,sun50i-a100-pinctrl + +then: + properties: +interrupts: + minItems: 7 + maxItems: 7 + - if: properties: compatible: @@ -216,6 +230,7 @@ allOf: - allwinner,sun8i-h3-r-pinctrl - allwinner,sun8i-r40-pinctrl - allwinner,sun50i-a64-r-pinctrl +- allwinner,sun50i-a100-r-pinctrl - nextthing,gr8-pinctrl then: -- 2.24.0
[PATCH v5 03/16] dt-bindings: pinctrl: sunxi: Get rid of continual nesting
From: Yangtao Li Rather than a continual nesting of 'else' clauses, just make each 'if' a new entry under 'allOf' and get rid of the else. Signed-off-by: Yangtao Li Reviewed-by: Rob Herring --- .../pinctrl/allwinner,sun4i-a10-pinctrl.yaml | 124 ++ 1 file changed, 68 insertions(+), 56 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml index 7556be6e2754..35a26abb02e7 100644 --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml @@ -155,62 +155,74 @@ allOf: minItems: 5 maxItems: 5 -else: - if: -properties: - compatible: -enum: - - allwinner,sun6i-a31-pinctrl - - allwinner,sun6i-a31s-pinctrl - - allwinner,sun50i-h6-pinctrl - - then: -properties: - interrupts: -minItems: 4 -maxItems: 4 - - else: -if: - properties: -compatible: - enum: -- allwinner,sun8i-a23-pinctrl -- allwinner,sun8i-a83t-pinctrl -- allwinner,sun50i-a64-pinctrl -- allwinner,sun50i-h5-pinctrl -- allwinner,suniv-f1c100s-pinctrl - -then: - properties: -interrupts: - minItems: 3 - maxItems: 3 - -else: - if: -properties: - compatible: -enum: - - allwinner,sun6i-a31-r-pinctrl - - allwinner,sun8i-a33-pinctrl - - allwinner,sun8i-h3-pinctrl - - allwinner,sun8i-v3-pinctrl - - allwinner,sun8i-v3s-pinctrl - - allwinner,sun9i-a80-r-pinctrl - - allwinner,sun50i-h6-r-pinctrl - - then: -properties: - interrupts: -minItems: 2 -maxItems: 2 - - else: -properties: - interrupts: -minItems: 1 -maxItems: 1 + - if: + properties: +compatible: + enum: +- allwinner,sun6i-a31-pinctrl +- allwinner,sun6i-a31s-pinctrl +- allwinner,sun50i-h6-pinctrl + +then: + properties: +interrupts: + minItems: 4 + maxItems: 4 + + - if: + properties: +compatible: + enum: +- allwinner,sun8i-a23-pinctrl +- allwinner,sun8i-a83t-pinctrl +- allwinner,sun50i-a64-pinctrl +- allwinner,sun50i-h5-pinctrl +- allwinner,suniv-f1c100s-pinctrl + +then: + properties: +interrupts: + minItems: 3 + maxItems: 3 + + - if: + properties: +compatible: + enum: +- allwinner,sun6i-a31-r-pinctrl +- allwinner,sun8i-a33-pinctrl +- allwinner,sun8i-h3-pinctrl +- allwinner,sun8i-v3-pinctrl +- allwinner,sun8i-v3s-pinctrl +- allwinner,sun9i-a80-r-pinctrl +- allwinner,sun50i-h6-r-pinctrl + +then: + properties: +interrupts: + minItems: 2 + maxItems: 2 + + - if: + properties: +compatible: + enum: +- allwinner,sun4i-a10-pinctrl +- allwinner,sun5i-a10s-pinctrl +- allwinner,sun5i-a13-pinctrl +- allwinner,sun7i-a20-pinctrl +- allwinner,sun8i-a23-r-pinctrl +- allwinner,sun8i-a83t-r-pinctrl +- allwinner,sun8i-h3-r-pinctrl +- allwinner,sun8i-r40-pinctrl +- allwinner,sun50i-a64-r-pinctrl +- nextthing,gr8-pinctrl + +then: + properties: +interrupts: + minItems: 1 + maxItems: 1 additionalProperties: false -- 2.24.0
[PATCH v5 02/16] clk: sunxi-ng: add support for the Allwinner A100 CCU
From: Yangtao Li
Add support for a100 in the sunxi-ng CCU framework.
Signed-off-by: Yangtao Li
---
drivers/clk/sunxi-ng/Kconfig | 10 +
drivers/clk/sunxi-ng/Makefile |2 +
drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c | 214 +++
drivers/clk/sunxi-ng/ccu-sun50i-a100-r.h | 21 +
drivers/clk/sunxi-ng/ccu-sun50i-a100.c| 1276 +
drivers/clk/sunxi-ng/ccu-sun50i-a100.h| 56 +
include/dt-bindings/clock/sun50i-a100-ccu.h | 116 ++
include/dt-bindings/clock/sun50i-a100-r-ccu.h | 23 +
include/dt-bindings/reset/sun50i-a100-ccu.h | 68 +
include/dt-bindings/reset/sun50i-a100-r-ccu.h | 18 +
10 files changed, 1804 insertions(+)
create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c
create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a100-r.h
create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a100.c
create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a100.h
create mode 100644 include/dt-bindings/clock/sun50i-a100-ccu.h
create mode 100644 include/dt-bindings/clock/sun50i-a100-r-ccu.h
create mode 100644 include/dt-bindings/reset/sun50i-a100-ccu.h
create mode 100644 include/dt-bindings/reset/sun50i-a100-r-ccu.h
diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
index cdf333003c30..ce5f5847d5d3 100644
--- a/drivers/clk/sunxi-ng/Kconfig
+++ b/drivers/clk/sunxi-ng/Kconfig
@@ -17,6 +17,16 @@ config SUN50I_A64_CCU
default ARM64 && ARCH_SUNXI
depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
+config SUN50I_A100_CCU
+ bool "Support for the Allwinner A100 CCU"
+ default ARM64 && ARCH_SUNXI
+ depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
+
+config SUN50I_A100_R_CCU
+ bool "Support for the Allwinner A100 PRCM CCU"
+ default ARM64 && ARCH_SUNXI
+ depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
+
config SUN50I_H6_CCU
bool "Support for the Allwinner H6 CCU"
default ARM64 && ARCH_SUNXI
diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
index 4c7bee883f2f..3eb5cff40eac 100644
--- a/drivers/clk/sunxi-ng/Makefile
+++ b/drivers/clk/sunxi-ng/Makefile
@@ -23,6 +23,8 @@ obj-y += ccu_mp.o
# SoC support
obj-$(CONFIG_SUNIV_F1C100S_CCU)+= ccu-suniv-f1c100s.o
obj-$(CONFIG_SUN50I_A64_CCU) += ccu-sun50i-a64.o
+obj-$(CONFIG_SUN50I_A100_CCU) += ccu-sun50i-a100.o
+obj-$(CONFIG_SUN50I_A100_R_CCU)+= ccu-sun50i-a100-r.o
obj-$(CONFIG_SUN50I_H6_CCU)+= ccu-sun50i-h6.o
obj-$(CONFIG_SUN50I_H6_R_CCU) += ccu-sun50i-h6-r.o
obj-$(CONFIG_SUN4I_A10_CCU)+= ccu-sun4i-a10.o
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c
b/drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c
new file mode 100644
index ..a56142b90993
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c
@@ -0,0 +1,214 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2020 Yangtao Li
+ */
+
+#include
+#include
+#include
+#include
+
+#include "ccu_common.h"
+#include "ccu_reset.h"
+
+#include "ccu_div.h"
+#include "ccu_gate.h"
+#include "ccu_mp.h"
+#include "ccu_nm.h"
+
+#include "ccu-sun50i-a100-r.h"
+
+static const char * const cpus_r_apb2_parents[] = { "dcxo24M", "osc32k",
+"iosc", "pll-periph0" };
+static const struct ccu_mux_var_prediv cpus_r_apb2_predivs[] = {
+ { .index = 3, .shift = 0, .width = 5 },
+};
+
+static struct ccu_div r_cpus_clk = {
+ .div= _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
+
+ .mux= {
+ .shift = 24,
+ .width = 2,
+
+ .var_predivs= cpus_r_apb2_predivs,
+ .n_var_predivs = ARRAY_SIZE(cpus_r_apb2_predivs),
+ },
+
+ .common = {
+ .reg= 0x000,
+ .features = CCU_FEATURE_VARIABLE_PREDIV,
+ .hw.init= CLK_HW_INIT_PARENTS("cpus",
+ cpus_r_apb2_parents,
+ _div_ops,
+ 0),
+ },
+};
+
+static CLK_FIXED_FACTOR_HW(r_ahb_clk, "r-ahb", _cpus_clk.common.hw, 1, 1, 0);
+
+static struct ccu_div r_apb1_clk = {
+ .div= _SUNXI_CCU_DIV(0, 2),
+
+ .common = {
+ .reg= 0x00c,
+ .hw.init= CLK_HW_INIT("r-apb1",
+ "r-ahb",
+ _div_ops,
+ 0),
+ },
+};
+
+static struct ccu_div r_apb2_clk = {
+ .div= _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
+
+ .mux= {
+ .shift = 24,
+ .width = 2,
+
+ .var_predivs= cpus_r_apb2_predivs,
+ .n_var_predivs =
[PATCH v5 01/16] dt-bindings: clk: sunxi-ccu: add compatible string for A100 CCU and R-CCU
From: Yangtao Li This patch adds binding to a100's ccu clock and r-ccu clock. Signed-off-by: Yangtao Li Reviewed-by: Rob Herring --- .../devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml index 4d382128b711..3b45344ed758 100644 --- a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml +++ b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml @@ -36,6 +36,8 @@ properties: - allwinner,sun9i-a80-ccu - allwinner,sun50i-a64-ccu - allwinner,sun50i-a64-r-ccu + - allwinner,sun50i-a100-ccu + - allwinner,sun50i-a100-r-ccu - allwinner,sun50i-h5-ccu - allwinner,sun50i-h6-ccu - allwinner,sun50i-h6-r-ccu @@ -78,6 +80,7 @@ if: - allwinner,sun8i-a83t-r-ccu - allwinner,sun8i-h3-r-ccu - allwinner,sun50i-a64-r-ccu +- allwinner,sun50i-a100-r-ccu - allwinner,sun50i-h6-r-ccu then: @@ -94,7 +97,9 @@ else: if: properties: compatible: -const: allwinner,sun50i-h6-ccu +enum: + - allwinner,sun50i-a100-ccu + - allwinner,sun50i-h6-ccu then: properties: -- 2.24.0
[PATCH v5 00/16] Allwinner A100 Initial support
This patch set adds initial support for allwinner a100 soc, which is a 64-bit tablet chip. v5: -Drop redundant SOB for thermal series patch -Trival a100 dtsi fix v4: -Drop "dt-bindings: pinctrl: sunxi: make gpio banks supplies required" -Fix dcdc1 regulator name -Get rid of underscore in dts node name -Some trivial things in yaml files v3: -Add pmu and nmi support -Add read data mask for calibration -Code style -Some trivial things in yaml files v2: -Some naming consistency -Repair email address -Fix mmc clock -Don't export system clock -Fix checkpatch warning -Drop unneeded pin function, convert to jtag_gpu and i2s_x Yangtao Li (16): dt-bindings: clk: sunxi-ccu: add compatible string for A100 CCU and R-CCU clk: sunxi-ng: add support for the Allwinner A100 CCU dt-bindings: pinctrl: sunxi: Get rid of continual nesting dt-bindings: pinctrl: sunxi: Add A100 pinctrl bindings pinctrl: sunxi: add support for the Allwinner A100 pin controller dt-bindings: nvmem: SID: add binding for A100's SID controller dt-bindings: thermal: sun8i: Add binding for A100's THS controller thermal: sun8i: add TEMP_CALIB_MASK for calibration data in sun50i_h6_ths_calibrate thermal: sun8i: Add A100's THS controller support mfd: axp20x: Allow the AXP803 to be probed by I2C dt-bindings: irq: sun7i-nmi: fix dt-binding for a80 nmi dt-bindings: irq: sun7i-nmi: Add binding for A100's NMI controller dt-bindings: i2c: mv64xxx: Add compatible for the A100 i2c node. arm64: allwinner: A100: add the basical Allwinner A100 DTSI file dt-bindings: arm: sunxi: Add Allwinner A100 Perf1 Board bindings arm64: allwinner: A100: add support for Allwinner Perf1 board .../devicetree/bindings/arm/sunxi.yaml|5 + .../clock/allwinner,sun4i-a10-ccu.yaml|7 +- .../bindings/i2c/marvell,mv64xxx-i2c.yaml |3 + .../allwinner,sun7i-a20-sc-nmi.yaml |5 +- .../nvmem/allwinner,sun4i-a10-sid.yaml| 19 +- .../pinctrl/allwinner,sun4i-a10-pinctrl.yaml | 139 +- .../thermal/allwinner,sun8i-a83t-ths.yaml |6 +- arch/arm64/boot/dts/allwinner/Makefile|1 + .../allwinner/sun50i-a100-allwinner-perf1.dts | 180 +++ .../arm64/boot/dts/allwinner/sun50i-a100.dtsi | 364 + drivers/clk/sunxi-ng/Kconfig | 10 + drivers/clk/sunxi-ng/Makefile |2 + drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c | 214 +++ drivers/clk/sunxi-ng/ccu-sun50i-a100-r.h | 21 + drivers/clk/sunxi-ng/ccu-sun50i-a100.c| 1276 + drivers/clk/sunxi-ng/ccu-sun50i-a100.h| 56 + drivers/mfd/axp20x-i2c.c |2 + drivers/pinctrl/sunxi/Kconfig | 10 + drivers/pinctrl/sunxi/Makefile|2 + drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c | 105 ++ drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c | 708 + drivers/thermal/sun8i_thermal.c | 16 +- include/dt-bindings/clock/sun50i-a100-ccu.h | 116 ++ include/dt-bindings/clock/sun50i-a100-r-ccu.h | 23 + include/dt-bindings/reset/sun50i-a100-ccu.h | 68 + include/dt-bindings/reset/sun50i-a100-r-ccu.h | 18 + 26 files changed, 3308 insertions(+), 68 deletions(-) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a100-r.h create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a100.c create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a100.h create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c create mode 100644 include/dt-bindings/clock/sun50i-a100-ccu.h create mode 100644 include/dt-bindings/clock/sun50i-a100-r-ccu.h create mode 100644 include/dt-bindings/reset/sun50i-a100-ccu.h create mode 100644 include/dt-bindings/reset/sun50i-a100-r-ccu.h -- 2.24.0
Re: [PATCH v4 14/16] arm64: allwinner: A100: add the basical Allwinner A100 DTSI file
HI,
On Fri, Jul 24, 2020 at 12:54 AM Maxime Ripard wrote:
>
> Hi,
>
> On Tue, Jul 14, 2020 at 03:20:29PM +0800, Frank Lee wrote:
> > From: Yangtao Li
> >
> > Allwinner A100 is a new SoC with Cortex-A53 cores, this commit adds
> > the basical DTSI file of it, including the clock, i2c, pins, sid, ths,
> > nmi, and UART support.
> >
> > Signed-off-by: Yangtao Li
> > ---
> > .../arm64/boot/dts/allwinner/sun50i-a100.dtsi | 364 ++
> > 1 file changed, 364 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
> >
> > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
> > b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
> > new file mode 100644
> > index ..3fb2443f2121
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
> > @@ -0,0 +1,364 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> > +/*
> > + * Copyright (c) 2020 Yangtao Li
> > + */
> > +
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +
> > +/ {
> > + interrupt-parent = <>;
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + cpu0: cpu@0 {
> > + compatible = "arm,armv8";
>
> You should use the arm,cortex-a53 compatible here, arm,armv8 is for
> software models.
>
> > + sid@3006000 {
>
> The node name is supposed to be the class of the device, and the DT spec
> defines a list of them already. eeprom would be better suited here.
EFuse is more accurate?
Thx,
Yangtao
Re: [PATCH v4 08/16] thermal: sun8i: add TEMP_CALIB_MASK for calibration data in sun50i_h6_ths_calibrate
HI, On Fri, Jul 17, 2020 at 3:56 PM Daniel Lezcano wrote: > > On 17/07/2020 09:35, Frank Lee wrote: > > On Fri, Jul 17, 2020 at 12:26 PM Daniel Lezcano > > wrote: > >> > >> On 14/07/2020 09:13, Frank Lee wrote: > >>> From: Yangtao Li > >>> > >>> For sun50i_h6_ths_calibrate(), the data read from nvmem needs a round of > >>> calculation. On the other hand, the newer SOC may store other data in > >>> the space other than 12bit sensor data. Add mask operation to read data > >>> to avoid conversion error. > >>> > >>> Signed-off-by: Yangtao Li > >>> Reviewed-by: Yangtao Li > >> > >> Can you clarify these SoB ? > > > > Previously I used 'Signed-off-by: Yangtao Li ', > > maybe this should be removed directly? > > > >> > >> Frank Lee==Yangtao Li==fr...@allwinnertech.com==tiny.win...@gmail.com ? > >> > > > > Yeah. > > You are not supposed to add reviewed-by yourself. Please remove it. Should I resend the entire series or just the thermal patch? What about those that have been applied. Thx, Yangtao
Re: [PATCH v4 00/16] Allwinner A100 Initial support
On Fri, Jul 17, 2020 at 12:28 PM Daniel Lezcano wrote: > > On 14/07/2020 08:55, Frank Lee wrote: > > From: Yangtao Li > > Do you expect me to pick patches 7,8,9 or ack them ? > Please pick it. Thx, Yangtao
Re: [PATCH v4 08/16] thermal: sun8i: add TEMP_CALIB_MASK for calibration data in sun50i_h6_ths_calibrate
On Fri, Jul 17, 2020 at 12:26 PM Daniel Lezcano wrote: > > On 14/07/2020 09:13, Frank Lee wrote: > > From: Yangtao Li > > > > For sun50i_h6_ths_calibrate(), the data read from nvmem needs a round of > > calculation. On the other hand, the newer SOC may store other data in > > the space other than 12bit sensor data. Add mask operation to read data > > to avoid conversion error. > > > > Signed-off-by: Yangtao Li > > Reviewed-by: Yangtao Li > > Can you clarify these SoB ? Previously I used 'Signed-off-by: Yangtao Li ', maybe this should be removed directly? > > Frank Lee==Yangtao Li==fr...@allwinnertech.com==tiny.win...@gmail.com ? > Yeah. Yangtao
[PATCH 3/3] arm64: dts: allwinner: Use GPIO bank name macro to describe GPIO
From: Yangtao Li
Convert gpio.h to sunxi-gpio.h, and convert to use gpio bank name macro.
This is done using the following command.
sed -i 's/r_pio 0/r_pio PL/g' arch/arm64/boot/dts/allwinner/*
sed -i 's/r_pio 1/r_pio PM/g' arch/arm64/boot/dts/allwinner/*
sed -i 's/\ 0/\ PA/g' arch/arm64/boot/dts/allwinner/*
sed -i 's/\ 2/\ PC/g' arch/arm64/boot/dts/allwinner/*
sed -i 's/\ 3/\ PD/g' arch/arm64/boot/dts/allwinner/*
sed -i 's/\ 4/\ PE/g' arch/arm64/boot/dts/allwinner/*
sed -i 's/\ 5/\ PF/g' arch/arm64/boot/dts/allwinner/*
sed -i 's/\ 6/\ PG/g' arch/arm64/boot/dts/allwinner/*
sed -i 's/\ 7/\ PH/g' arch/arm64/boot/dts/allwinner/*
sed -i 's/dt-bindings\/gpio\/gpio.h/dt-bindings\/gpio\/sunxi-gpio.h/g' \
arch/arm64/boot/dts/allwinner/*
Signed-off-by: Yangtao Li
---
.../allwinner/sun50i-a64-amarula-relic.dts| 18 ++--
.../dts/allwinner/sun50i-a64-bananapi-m64.dts | 20 ++---
.../dts/allwinner/sun50i-a64-nanopi-a64.dts | 8 +++---
.../sun50i-a64-oceanic-5205-5inmfd.dts| 4 +--
.../dts/allwinner/sun50i-a64-olinuxino.dts| 12
.../dts/allwinner/sun50i-a64-orangepi-win.dts | 20 ++---
.../boot/dts/allwinner/sun50i-a64-pine64.dts | 4 +--
.../dts/allwinner/sun50i-a64-pinebook.dts | 16 +--
.../dts/allwinner/sun50i-a64-pinephone.dtsi | 14 +-
.../boot/dts/allwinner/sun50i-a64-pinetab.dts | 28 +--
.../boot/dts/allwinner/sun50i-a64-sopine.dtsi | 4 +--
.../boot/dts/allwinner/sun50i-a64-teres-i.dts | 20 ++---
.../sun50i-h5-emlid-neutis-n5-devboard.dts| 2 +-
.../sun50i-h5-libretech-all-h5-cc.dts | 2 +-
.../allwinner/sun50i-h5-nanopi-neo-plus2.dts | 14 +-
.../dts/allwinner/sun50i-h5-nanopi-neo2.dts | 14 +-
.../dts/allwinner/sun50i-h5-orangepi-pc2.dts | 16 +--
.../allwinner/sun50i-h5-orangepi-prime.dts| 18 ++--
.../sun50i-h5-orangepi-zero-plus.dts | 13 +
.../sun50i-h5-orangepi-zero-plus2.dts | 6 ++--
.../dts/allwinner/sun50i-h6-beelink-gs1.dts | 8 +++---
.../dts/allwinner/sun50i-h6-orangepi-3.dts| 20 ++---
.../allwinner/sun50i-h6-orangepi-lite2.dts| 8 +++---
.../allwinner/sun50i-h6-orangepi-one-plus.dts | 2 +-
.../dts/allwinner/sun50i-h6-orangepi.dtsi | 12
.../boot/dts/allwinner/sun50i-h6-pine-h64.dts | 16 +--
.../dts/allwinner/sun50i-h6-tanix-tx6.dts | 6 ++--
27 files changed, 163 insertions(+), 162 deletions(-)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts
b/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts
index c7bd73f35ed8..92f8caecf939 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts
@@ -7,7 +7,7 @@
#include "sun50i-a64.dtsi"
#include "sun50i-a64-cpu-opp.dtsi"
-#include
+#include
/ {
model = "Amarula A64-Relic";
@@ -23,8 +23,8 @@ chosen {
i2c {
compatible = "i2c-gpio";
- sda-gpios = < 4 13 GPIO_ACTIVE_HIGH>;
- scl-gpios = < 4 12 GPIO_ACTIVE_HIGH>;
+ sda-gpios = < PE 13 GPIO_ACTIVE_HIGH>;
+ scl-gpios = < PE 12 GPIO_ACTIVE_HIGH>;
i2c-gpio,delay-us = <5>;
#address-cells = <1>;
#size-cells = <0>;
@@ -40,8 +40,8 @@ ov5640: camera@3c {
AVDD-supply = <_aldo1>;
DOVDD-supply = <_dldo3>;
DVDD-supply = <_eldo3>;
- reset-gpios = < 4 14 GPIO_ACTIVE_LOW>; /*
CSI-RST-R: PE14 */
- powerdown-gpios = < 4 15 GPIO_ACTIVE_HIGH>; /*
CSI-STBY-R: PE15 */
+ reset-gpios = < PE 14 GPIO_ACTIVE_LOW>; /*
CSI-RST-R: PE14 */
+ powerdown-gpios = < PE 15 GPIO_ACTIVE_HIGH>; /*
CSI-STBY-R: PE15 */
port {
ov5640_ep: endpoint {
@@ -60,7 +60,7 @@ wifi_pwrseq: wifi-pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = < 1>;
clock-names = "ext_clock";
- reset-gpios = <_pio 0 2 GPIO_ACTIVE_LOW>; /* WL-PMU-EN: PL2 */
+ reset-gpios = <_pio PL 2 GPIO_ACTIVE_LOW>; /* WL-PMU-EN: PL2
*/
};
};
@@ -121,8 +121,8 @@ touchscreen@5d {
AVDD28-supply = <_ldo_io0>; /* VCC-CTP:
GPIO0-LDO */
interrupt-parent = <>;
interrupts = <7 4 IRQ_TYPE_EDGE_FALLING>;
- irq-gpios = < 7 4 GPIO_ACTIVE_HIGH>;/* CTP-INT: PH4
*/
- reset-gpios = < 7 8 GPIO_ACTIVE_HIGH>; /* CTP-RST: PH8
*/
+ irq-gpios = < PH 4 GPIO_ACTIVE_HIGH>; /* CTP-INT: PH4
*/
+ reset-gpios = < PH 8 GPIO_ACTIVE_HIGH>; /* CTP-RST: PH8
*/
touchscreen-inverted-x;
touchscreen-inverted-y;
};
@@ -314,7 +314,7 @@ _otg {
[PATCH 2/3] ARM: dts: allwinner: convert gpio.h to sunxi-gpio.h
From: Yangtao Li
Use names instead of numbers to describe GPIO. We clean arm64 first.
Since H5 uses the DTS file in arm directory, we need to modify the
header file in advance.
Signed-off-by: Yangtao Li
---
arch/arm/boot/dts/sunxi-h3-h5-emlid-neutis.dtsi | 2 +-
arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/sunxi-h3-h5-emlid-neutis.dtsi
b/arch/arm/boot/dts/sunxi-h3-h5-emlid-neutis.dtsi
index fc67e30fe212..93f9653b43f4 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5-emlid-neutis.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5-emlid-neutis.dtsi
@@ -7,7 +7,7 @@
#include "sunxi-common-regulators.dtsi"
-#include
+#include
/ {
aliases {
diff --git a/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi
b/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi
index 19b3b23cfaa8..f6f14b5175e3 100644
--- a/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi
+++ b/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi
@@ -3,7 +3,7 @@
* Copyright (C) 2017 Chen-Yu Tsai
*/
-#include
+#include
#include
/ {
--
2.24.0
[PATCH 1/3] dt-bindings: gpio: sunxi：create a DT header for Allwinner pin controller
From: Yangtao Li The sunxi gpio binding defines a few custom cells for its gpio specifier. Provide bank name for those. Signed-off-by: Yangtao Li --- include/dt-bindings/gpio/sunxi-gpio.h | 29 +++ 1 file changed, 29 insertions(+) create mode 100644 include/dt-bindings/gpio/sunxi-gpio.h diff --git a/include/dt-bindings/gpio/sunxi-gpio.h b/include/dt-bindings/gpio/sunxi-gpio.h new file mode 100644 index ..c692b4360da6 --- /dev/null +++ b/include/dt-bindings/gpio/sunxi-gpio.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * GPIO definitions for Allwinner SoCs + * + * Copyright (C) 2020 Yangtao Li + */ + +#ifndef _DT_BINDINGS_SUNXI_GPIO_H +#define _DT_BINDINGS_SUNXI_GPIO_H + +#include + +/* pio */ +#define PA 0 +#define PB 1 +#define PC 2 +#define PD 3 +#define PE 4 +#define PF 5 +#define PG 6 +#define PH 7 +#define PI 8 + +/* r-pio */ +#define PL 0 +#define PM 1 +#define PN 2 + +#endif /* _DT_BINDINGS_SUNXI_GPIO_H */ -- 2.24.0
[PATCH v4 16/16] arm64: allwinner: A100: add support for Allwinner Perf1 board
From: Yangtao Li
A100 perf1 is an Allwinner A100-based SBC, with the following features:
- 1GiB DDR3 DRAM
- AXP803 PMIC
- 2 USB 2.0 ports
- MicroSD slot and on-board eMMC module
- on-board Nand flash
- ···
Adds initial support for it, including UART and PMU.
Signed-off-by: Yangtao Li
---
arch/arm64/boot/dts/allwinner/Makefile| 1 +
.../allwinner/sun50i-a100-allwinner-perf1.dts | 180 ++
2 files changed, 181 insertions(+)
create mode 100644
arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
diff --git a/arch/arm64/boot/dts/allwinner/Makefile
b/arch/arm64/boot/dts/allwinner/Makefile
index e4d3cd0ac5bb..ab780dbdd17b 100644
--- a/arch/arm64/boot/dts/allwinner/Makefile
+++ b/arch/arm64/boot/dts/allwinner/Makefile
@@ -14,6 +14,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinephone-1.1.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinetab.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-sopine-baseboard.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-teres-i.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a100-allwinner-perf1.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-bananapi-m2-plus.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-bananapi-m2-plus-v1.2.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-emlid-neutis-n5-devboard.dtb
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
new file mode 100644
index ..d34c2bb1079f
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
@@ -0,0 +1,180 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Copyright (c) 2020 Yangtao Li
+ */
+
+/dts-v1/;
+
+#include "sun50i-a100.dtsi"
+
+/{
+ model = "Allwinner A100 Perf1";
+ compatible = "allwinner,a100-perf1", "allwinner,sun50i-a100";
+
+ aliases {
+ serial0 =
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+ {
+ vcc-pb-supply = <_dcdc1>;
+ vcc-pc-supply = <_eldo1>;
+ vcc-pd-supply = <_dcdc1>;
+ vcc-pe-supply = <_dldo2>;
+ vcc-pf-supply = <_dcdc1>;
+ vcc-pg-supply = <_dldo1>;
+ vcc-ph-supply = <_dcdc1>;
+};
+
+_pio {
+ /*
+* FIXME: We can't add that supply for now since it would
+* create a circular dependency between pinctrl, the regulator
+* and the RSB Bus.
+*
+* vcc-pl-supply = <_aldo3>;
+*/
+};
+
+_i2c0 {
+ status = "okay";
+
+ axp803: pmic@34 {
+ compatible = "x-powers,axp803";
+ reg = <0x34>;
+ interrupt-parent = <_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ x-powers,drive-vbus-en; /* set N_VBUSEN as output pin */
+ };
+};
+
+#include "axp803.dtsi"
+
+_power_supply {
+ status = "okay";
+};
+
+_aldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+ regulator-name = "vcc-pll-avcc";
+};
+
+_aldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+ regulator-name = "vcc-dram-1";
+};
+
+_aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ regulator-name = "vcc-usb-pl";
+};
+
+_dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ regulator-name = "vcc-io-usb-pd-emmc-nand-card";
+};
+
+_dcdc2 {
+ regulator-always-on;
+ /*
+* FIXME: update min and max before support dvfs.
+*/
+ regulator-min-microvolt = <50>;
+ regulator-max-microvolt = <130>;
+ regulator-name = "vdd-cpux";
+};
+
+/* DCDC3 is polyphased with DCDC2 */
+
+_dcdc4 {
+ regulator-always-on;
+ regulator-min-microvolt = <95>;
+ regulator-max-microvolt = <95>;
+ regulator-name = "vdd-sys-usb-dram";
+};
+
+_dcdc5 {
+ regulator-always-on;
+ regulator-min-microvolt = <150>;
+ regulator-max-microvolt = <150>;
+ regulator-name = "vcc-dram-2";
+};
+
+_dldo1 {
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ regulator-name = "vcc-pg-dcxo-wifi";
+};
+
+_dldo2 {
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <280>;
+ regulator-name = "vcc-pe-csi";
+};
+
+_dldo3 {
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <330>;
+ regulator-name = "ldo-avdd-csi";
+};
+
+_dldo4 {
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <280>;
+ regulator-name = "avcc-csi";
+};
+
+_eldo1 {
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+ regulator-name = "vcc-pc-lvds-csi-efuse-emmc-nand";
+};
+
+_eldo2 {
+
[PATCH v4 15/16] dt-bindings: arm: sunxi: Add Allwinner A100 Perf1 Board bindings
From: Yangtao Li Document board compatible names for Allwinner A100 Perf1 Board. Signed-off-by: Yangtao Li Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/arm/sunxi.yaml | 5 + 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index 87817ff0cd35..dbec66c1377a 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -16,6 +16,11 @@ properties: compatible: oneOf: + - description: Allwinner A100 Perf1 Board +items: + - const: allwinner,a100-perf1 + - const: allwinner,sun50i-a100 + - description: Allwinner A23 Evaluation Board items: - const: allwinner,sun8i-a23-evb -- 2.24.0
[PATCH v4 14/16] arm64: allwinner: A100: add the basical Allwinner A100 DTSI file
From: Yangtao Li
Allwinner A100 is a new SoC with Cortex-A53 cores, this commit adds
the basical DTSI file of it, including the clock, i2c, pins, sid, ths,
nmi, and UART support.
Signed-off-by: Yangtao Li
---
.../arm64/boot/dts/allwinner/sun50i-a100.dtsi | 364 ++
1 file changed, 364 insertions(+)
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
new file mode 100644
index ..3fb2443f2121
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
@@ -0,0 +1,364 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Copyright (c) 2020 Yangtao Li
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+/ {
+ interrupt-parent = <>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0>;
+ enable-method = "psci";
+ };
+
+ cpu@1 {
+ compatible = "arm,armv8";
+ device_type = "cpu";
+ reg = <0x1>;
+ enable-method = "psci";
+ };
+
+ cpu@2 {
+ compatible = "arm,armv8";
+ device_type = "cpu";
+ reg = <0x2>;
+ enable-method = "psci";
+ };
+
+ cpu@3 {
+ compatible = "arm,armv8";
+ device_type = "cpu";
+ reg = <0x3>;
+ enable-method = "psci";
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ dcxo24M: dcxo24M-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <2400>;
+ clock-output-names = "dcxo24M";
+ #clock-cells = <0>;
+ };
+
+ iosc: internal-osc-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <1600>;
+ clock-accuracy = <3>;
+ clock-output-names = "iosc";
+ #clock-cells = <0>;
+ };
+
+ osc32k: osc32k-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "osc32k";
+ #clock-cells = <0>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = ,
+,
+,
+;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0 0x3fff>;
+
+ ccu: clock@3001000 {
+ compatible = "allwinner,sun50i-a100-ccu";
+ reg = <0x03001000 0x1000>;
+ clocks = <>, <>, <>;
+ clock-names = "hosc", "losc", "iosc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ gic: interrupt-controller@3021000 {
+ compatible = "arm,gic-400";
+ reg = <0x03021000 0x1000>, <0x03022000 0x2000>,
+ <0x03024000 0x2000>, <0x03026000 0x2000>;
+ interrupts = ;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
+
+ sid@3006000 {
+ compatible = "allwinner,sun50i-a100-sid",
+"allwinner,sun50i-a64-sid";
+ reg = <0x03006000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ths_calibration: calib@14 {
+ reg = <0x14 8>;
+ };
+ };
+
+ pio: pinctrl@300b000 {
+ compatible = "allwinner,sun50i-a100-pinctrl";
+ reg = <0x0300b000 0x400>;
+ interrupts = ,
+,
+,
+,
+,
+,
+;
+ clocks = < CLK_APB1>, <>, <>;
+ clock-names = "apb", "hosc", "losc";
+ gpio-controller;
+ #gpio-cells = <3>;
+ interrupt-controller;
+
[PATCH v4 13/16] dt-bindings: i2c: mv64xxx: Add compatible for the A100 i2c node.
From: Yangtao Li Allwinner A100 have a mv64xxx i2c interface available to be used. Signed-off-by: Yangtao Li Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml b/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml index 2ceb05ba2df5..5b5ae402f97a 100644 --- a/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml @@ -26,6 +26,9 @@ properties: - items: - const: allwinner,sun50i-a64-i2c - const: allwinner,sun6i-a31-i2c + - items: + - const: allwinner,sun50i-a100-i2c + - const: allwinner,sun6i-a31-i2c - items: - const: allwinner,sun50i-h6-i2c - const: allwinner,sun6i-a31-i2c -- 2.24.0
[PATCH v4 12/16] dt-bindings: irq: sun7i-nmi: Add binding for A100's NMI controller
From: Yangtao Li Add a binding for A100's nmi controller. Signed-off-by: Yangtao Li Acked-by: Rob Herring --- .../interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml index d8fe2d9a307b..8acca0ae3129 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml @@ -33,6 +33,9 @@ properties: - items: - const: allwinner,sun50i-a64-r-intc - const: allwinner,sun6i-a31-r-intc + - items: + - const: allwinner,sun50i-a100-nmi + - const: allwinner,sun9i-a80-nmi - items: - const: allwinner,sun50i-h6-r-intc - const: allwinner,sun6i-a31-r-intc -- 2.24.0
[PATCH v4 11/16] dt-bindings: irq: sun7i-nmi: fix dt-binding for a80 nmi
From: Yangtao Li There is no one use "allwinner,sun9i-a80-sc-nmi". The A80 uses "allwinner,sun9i-a80-nmi". Let's fix it. Signed-off-by: Yangtao Li Acked-by: Rob Herring --- .../interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml| 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml index 7cd6b8bacfa0..d8fe2d9a307b 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml @@ -29,7 +29,7 @@ properties: - items: - const: allwinner,sun8i-a83t-r-intc - const: allwinner,sun6i-a31-r-intc - - const: allwinner,sun9i-a80-sc-nmi + - const: allwinner,sun9i-a80-nmi - items: - const: allwinner,sun50i-a64-r-intc - const: allwinner,sun6i-a31-r-intc -- 2.24.0
[PATCH v4 10/16] mfd: axp20x: Allow the AXP803 to be probed by I2C
From: Yangtao Li
The AXP803 can be used both using the RSB proprietary bus, or a more
traditional I2C bus.
Let's add that possibility.
Signed-off-by: Yangtao Li
---
drivers/mfd/axp20x-i2c.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mfd/axp20x-i2c.c b/drivers/mfd/axp20x-i2c.c
index 14f9df74f855..446a7d0bbb47 100644
--- a/drivers/mfd/axp20x-i2c.c
+++ b/drivers/mfd/axp20x-i2c.c
@@ -63,6 +63,7 @@ static const struct of_device_id axp20x_i2c_of_match[] = {
{ .compatible = "x-powers,axp209", .data = (void *)AXP209_ID },
{ .compatible = "x-powers,axp221", .data = (void *)AXP221_ID },
{ .compatible = "x-powers,axp223", .data = (void *)AXP223_ID },
+ { .compatible = "x-powers,axp803", .data = (void *)AXP803_ID },
{ .compatible = "x-powers,axp806", .data = (void *)AXP806_ID },
{ },
};
@@ -74,6 +75,7 @@ static const struct i2c_device_id axp20x_i2c_id[] = {
{ "axp209", 0 },
{ "axp221", 0 },
{ "axp223", 0 },
+ { "axp803", 0 },
{ "axp806", 0 },
{ },
};
--
2.24.0
[PATCH v4 09/16] thermal: sun8i: Add A100's THS controller support
From: Yangtao Li
This patch add thermal sensor controller support for A100,
which is similar to the previous ones.
Signed-off-by: Yangtao Li
Reviewed-by: Yangtao Li
---
drivers/thermal/sun8i_thermal.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/thermal/sun8i_thermal.c b/drivers/thermal/sun8i_thermal.c
index f423d44b9290..f8b13071a6f4 100644
--- a/drivers/thermal/sun8i_thermal.c
+++ b/drivers/thermal/sun8i_thermal.c
@@ -590,6 +590,19 @@ static const struct ths_thermal_chip sun50i_a64_ths = {
.calc_temp = sun8i_ths_calc_temp,
};
+static const struct ths_thermal_chip sun50i_a100_ths = {
+ .sensor_num = 3,
+ .has_bus_clk_reset = true,
+ .ft_deviation = 8000,
+ .offset = 187744,
+ .scale = 672,
+ .temp_data_base = SUN50I_H6_THS_TEMP_DATA,
+ .calibrate = sun50i_h6_ths_calibrate,
+ .init = sun50i_h6_thermal_init,
+ .irq_ack = sun50i_h6_irq_ack,
+ .calc_temp = sun8i_ths_calc_temp,
+};
+
static const struct ths_thermal_chip sun50i_h5_ths = {
.sensor_num = 2,
.has_mod_clk = true,
@@ -619,6 +632,7 @@ static const struct of_device_id of_ths_match[] = {
{ .compatible = "allwinner,sun8i-h3-ths", .data = _h3_ths },
{ .compatible = "allwinner,sun8i-r40-ths", .data = _r40_ths },
{ .compatible = "allwinner,sun50i-a64-ths", .data = _a64_ths },
+ { .compatible = "allwinner,sun50i-a100-ths", .data = _a100_ths },
{ .compatible = "allwinner,sun50i-h5-ths", .data = _h5_ths },
{ .compatible = "allwinner,sun50i-h6-ths", .data = _h6_ths },
{ /* sentinel */ },
--
2.24.0
[PATCH v4 08/16] thermal: sun8i: add TEMP_CALIB_MASK for calibration data in sun50i_h6_ths_calibrate
From: Yangtao Li
For sun50i_h6_ths_calibrate(), the data read from nvmem needs a round of
calculation. On the other hand, the newer SOC may store other data in
the space other than 12bit sensor data. Add mask operation to read data
to avoid conversion error.
Signed-off-by: Yangtao Li
Reviewed-by: Yangtao Li
---
drivers/thermal/sun8i_thermal.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/thermal/sun8i_thermal.c b/drivers/thermal/sun8i_thermal.c
index 74d73be16496..f423d44b9290 100644
--- a/drivers/thermal/sun8i_thermal.c
+++ b/drivers/thermal/sun8i_thermal.c
@@ -244,7 +244,7 @@ static int sun50i_h6_ths_calibrate(struct ths_device *tmdev,
ft_temp = (caldata[0] & FT_TEMP_MASK) * 100;
for (i = 0; i < tmdev->chip->sensor_num; i++) {
- int sensor_reg = caldata[i + 1];
+ int sensor_reg = caldata[i + 1] & TEMP_CALIB_MASK;
int cdata, offset;
int sensor_temp = tmdev->chip->calc_temp(tmdev, i, sensor_reg);
--
2.24.0
[PATCH v4 07/16] dt-bindings: thermal: sun8i: Add binding for A100's THS controller
From: Yangtao Li Add a binding for A100's ths controller. Signed-off-by: Yangtao Li Reviewed-by: Yangtao Li Reviewed-by: Rob Herring --- .../bindings/thermal/allwinner,sun8i-a83t-ths.yaml | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml b/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml index 87369264feb9..9d40fc7ff6fd 100644 --- a/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml +++ b/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml @@ -17,6 +17,7 @@ properties: - allwinner,sun8i-h3-ths - allwinner,sun8i-r40-ths - allwinner,sun50i-a64-ths + - allwinner,sun50i-a100-ths - allwinner,sun50i-h5-ths - allwinner,sun50i-h6-ths @@ -61,7 +62,9 @@ allOf: properties: compatible: contains: -const: allwinner,sun50i-h6-ths +enum: + - allwinner,sun50i-a100-ths + - allwinner,sun50i-h6-ths then: properties: @@ -103,6 +106,7 @@ allOf: - const: allwinner,sun8i-h3-ths - const: allwinner,sun8i-r40-ths - const: allwinner,sun50i-a64-ths + - const: allwinner,sun50i-a100-ths - const: allwinner,sun50i-h5-ths - const: allwinner,sun50i-h6-ths -- 2.24.0
[PATCH v4 06/16] dt-bindings: nvmem: SID: add binding for A100's SID controller
From: Yangtao Li Add a binding for A100's SID controller. Signed-off-by: Yangtao Li --- .../nvmem/allwinner,sun4i-a10-sid.yaml| 19 +++ 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/nvmem/allwinner,sun4i-a10-sid.yaml b/Documentation/devicetree/bindings/nvmem/allwinner,sun4i-a10-sid.yaml index daf1321d76ad..6687ab720304 100644 --- a/Documentation/devicetree/bindings/nvmem/allwinner,sun4i-a10-sid.yaml +++ b/Documentation/devicetree/bindings/nvmem/allwinner,sun4i-a10-sid.yaml @@ -15,14 +15,17 @@ allOf: properties: compatible: -enum: - - allwinner,sun4i-a10-sid - - allwinner,sun7i-a20-sid - - allwinner,sun8i-a83t-sid - - allwinner,sun8i-h3-sid - - allwinner,sun50i-a64-sid - - allwinner,sun50i-h5-sid - - allwinner,sun50i-h6-sid +oneOf: + - const: allwinner,sun4i-a10-sid + - const: allwinner,sun7i-a20-sid + - const: allwinner,sun8i-a83t-sid + - const: allwinner,sun8i-h3-sid + - const: allwinner,sun50i-a64-sid + - items: + - const: allwinner,sun50i-a100-sid + - const: allwinner,sun50i-a64-sid + - const: allwinner,sun50i-h5-sid + - const: allwinner,sun50i-h6-sid reg: maxItems: 1 -- 2.24.0
[PATCH v4 05/16] pinctrl: sunxi: add support for the Allwinner A100 pin controller
From: Yangtao Li
This commit introduces support for the pin controller on A100.
Signed-off-by: Yangtao Li
---
drivers/pinctrl/sunxi/Kconfig | 10 +
drivers/pinctrl/sunxi/Makefile| 2 +
drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c | 105 +++
drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c | 708 ++
4 files changed, 825 insertions(+)
create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c
create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index f7aae200ee15..593293584ecc 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -94,6 +94,16 @@ config PINCTRL_SUN50I_A64_R
default ARM64 && ARCH_SUNXI
select PINCTRL_SUNXI
+config PINCTRL_SUN50I_A100
+ bool "Support for the Allwinner A100 PIO"
+ default ARM64 && ARCH_SUNXI
+ select PINCTRL_SUNXI
+
+config PINCTRL_SUN50I_A100_R
+ bool "Support for the Allwinner A100 R-PIO"
+ default ARM64 && ARCH_SUNXI
+ select PINCTRL_SUNXI
+
config PINCTRL_SUN50I_H5
bool "Support for the Allwinner H5 PIO"
default ARM64 && ARCH_SUNXI
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
index fafcdae8134f..8b7ff0dc3bdf 100644
--- a/drivers/pinctrl/sunxi/Makefile
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -13,6 +13,8 @@ obj-$(CONFIG_PINCTRL_SUN8I_A23_R) += pinctrl-sun8i-a23-r.o
obj-$(CONFIG_PINCTRL_SUN8I_A33)+= pinctrl-sun8i-a33.o
obj-$(CONFIG_PINCTRL_SUN50I_A64) += pinctrl-sun50i-a64.o
obj-$(CONFIG_PINCTRL_SUN50I_A64_R) += pinctrl-sun50i-a64-r.o
+obj-$(CONFIG_PINCTRL_SUN50I_A100) += pinctrl-sun50i-a100.o
+obj-$(CONFIG_PINCTRL_SUN50I_A100_R)+= pinctrl-sun50i-a100-r.o
obj-$(CONFIG_PINCTRL_SUN8I_A83T) += pinctrl-sun8i-a83t.o
obj-$(CONFIG_PINCTRL_SUN8I_A83T_R) += pinctrl-sun8i-a83t-r.o
obj-$(CONFIG_PINCTRL_SUN8I_H3) += pinctrl-sun8i-h3.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c
b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c
new file mode 100644
index ..21054fcacd34
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2020 Yangtao Li
+ *
+ * Based on:
+ * huangshuosheng
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include "pinctrl-sunxi.h"
+
+static const struct sunxi_desc_pin a100_r_pins[] = {
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_i2c0"),/* SCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_i2c0"),/* SDA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_uart0"), /* TX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_uart0"), /* RX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_jtag"),/* MS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_jtag"),/* CK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_jtag"),/* DO */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_jtag"),/* DI */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_i2c1"),/* SCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9),
+ SUNXI_FUNCTION(0x0,
[PATCH v4 04/16] dt-bindings: pinctrl: sunxi: Add A100 pinctrl bindings
From: Yangtao Li Add device tree binding Documentation details for A100 pinctrl driver, which has a r pin controller and a pin controller with more irq lines. Signed-off-by: Yangtao Li --- .../pinctrl/allwinner,sun4i-a10-pinctrl.yaml | 15 +++ 1 file changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml index 35a26abb02e7..34a17d5c6135 100644 --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml @@ -48,6 +48,8 @@ properties: - allwinner,sun9i-a80-r-pinctrl - allwinner,sun50i-a64-pinctrl - allwinner,sun50i-a64-r-pinctrl + - allwinner,sun50i-a100-pinctrl + - allwinner,sun50i-a100-r-pinctrl - allwinner,sun50i-h5-pinctrl - allwinner,sun50i-h6-pinctrl - allwinner,sun50i-h6-r-pinctrl @@ -143,6 +145,18 @@ allOf: # boards are defining it at the moment so it would generate a lot of # warnings. + - if: + properties: +compatible: + enum: +- allwinner,sun50i-a100-pinctrl + +then: + properties: +interrupts: + minItems: 7 + maxItems: 7 + - if: properties: compatible: @@ -216,6 +230,7 @@ allOf: - allwinner,sun8i-h3-r-pinctrl - allwinner,sun8i-r40-pinctrl - allwinner,sun50i-a64-r-pinctrl +- allwinner,sun50i-a100-r-pinctrl - nextthing,gr8-pinctrl then: -- 2.24.0
[PATCH v4 03/16] dt-bindings: pinctrl: sunxi: Get rid of continual nesting
From: Yangtao Li Rather than a continual nesting of 'else' clauses, just make each 'if' a new entry under 'allOf' and get rid of the else. Signed-off-by: Yangtao Li --- .../pinctrl/allwinner,sun4i-a10-pinctrl.yaml | 124 ++ 1 file changed, 68 insertions(+), 56 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml index 7556be6e2754..35a26abb02e7 100644 --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml @@ -155,62 +155,74 @@ allOf: minItems: 5 maxItems: 5 -else: - if: -properties: - compatible: -enum: - - allwinner,sun6i-a31-pinctrl - - allwinner,sun6i-a31s-pinctrl - - allwinner,sun50i-h6-pinctrl - - then: -properties: - interrupts: -minItems: 4 -maxItems: 4 - - else: -if: - properties: -compatible: - enum: -- allwinner,sun8i-a23-pinctrl -- allwinner,sun8i-a83t-pinctrl -- allwinner,sun50i-a64-pinctrl -- allwinner,sun50i-h5-pinctrl -- allwinner,suniv-f1c100s-pinctrl - -then: - properties: -interrupts: - minItems: 3 - maxItems: 3 - -else: - if: -properties: - compatible: -enum: - - allwinner,sun6i-a31-r-pinctrl - - allwinner,sun8i-a33-pinctrl - - allwinner,sun8i-h3-pinctrl - - allwinner,sun8i-v3-pinctrl - - allwinner,sun8i-v3s-pinctrl - - allwinner,sun9i-a80-r-pinctrl - - allwinner,sun50i-h6-r-pinctrl - - then: -properties: - interrupts: -minItems: 2 -maxItems: 2 - - else: -properties: - interrupts: -minItems: 1 -maxItems: 1 + - if: + properties: +compatible: + enum: +- allwinner,sun6i-a31-pinctrl +- allwinner,sun6i-a31s-pinctrl +- allwinner,sun50i-h6-pinctrl + +then: + properties: +interrupts: + minItems: 4 + maxItems: 4 + + - if: + properties: +compatible: + enum: +- allwinner,sun8i-a23-pinctrl +- allwinner,sun8i-a83t-pinctrl +- allwinner,sun50i-a64-pinctrl +- allwinner,sun50i-h5-pinctrl +- allwinner,suniv-f1c100s-pinctrl + +then: + properties: +interrupts: + minItems: 3 + maxItems: 3 + + - if: + properties: +compatible: + enum: +- allwinner,sun6i-a31-r-pinctrl +- allwinner,sun8i-a33-pinctrl +- allwinner,sun8i-h3-pinctrl +- allwinner,sun8i-v3-pinctrl +- allwinner,sun8i-v3s-pinctrl +- allwinner,sun9i-a80-r-pinctrl +- allwinner,sun50i-h6-r-pinctrl + +then: + properties: +interrupts: + minItems: 2 + maxItems: 2 + + - if: + properties: +compatible: + enum: +- allwinner,sun4i-a10-pinctrl +- allwinner,sun5i-a10s-pinctrl +- allwinner,sun5i-a13-pinctrl +- allwinner,sun7i-a20-pinctrl +- allwinner,sun8i-a23-r-pinctrl +- allwinner,sun8i-a83t-r-pinctrl +- allwinner,sun8i-h3-r-pinctrl +- allwinner,sun8i-r40-pinctrl +- allwinner,sun50i-a64-r-pinctrl +- nextthing,gr8-pinctrl + +then: + properties: +interrupts: + minItems: 1 + maxItems: 1 additionalProperties: false -- 2.24.0
