[tip: x86/urgent] x86/cpu: Add another Alder Lake CPU to the Intel family

The following commit has been merged into the x86/urgent branch of tip: Commit-ID: 6e1239c13953f3c2a76e70031f74ddca9ae57cd3 Gitweb: https://git.kernel.org/tip/6e1239c13953f3c2a76e70031f74ddca9ae57cd3 Author:Gayatri Kammela AuthorDate:Thu, 21 Jan 2021 13:50:04 -08:00

[PATCH v1 0/5] Add Tiger Lake/Elkhart Lake support to pmc_core driver

the PCH IPs and names of IPs will be available in *future* Intel's Platform Controller Hub (PCH) External Design Specification (EDS) document. Gayatri Kammela (5): x86/intel_pmc_core: Clean up: Remove comma after the termination line x86/intel_pmc_core: Create platform dependent pmc bitmap structs

[PATCH v1 5/5] platform/x86: Add Atom based Elkhart Lake(EHL) platform support to intel_pmc_core driver

: Srinivas Pandruvada Cc: Andy Shevchenko Cc: Kan Liang Cc: David E. Box Cc: Rajneesh Bhardwaj Cc: Tony Luck Reviewed-by: Tony Luck Signed-off-by: Gayatri Kammela --- drivers/platform/x86/intel_pmc_core.c | 13 ++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git

[PATCH v1 4/5] platform/x86: Add Tiger Lake(TGL) platform support to intel_pmc_core driver

Zijlstra Cc: Srinivas Pandruvada Cc: Andy Shevchenko Cc: Kan Liang Cc: David E. Box Cc: Rajneesh Bhardwaj Cc: Tony Luck Reviewed-by: Tony Luck Signed-off-by: Gayatri Kammela --- drivers/platform/x86/intel_pmc_core.c | 40 +-- 1 file changed, 38 insertions(+), 2 deletions

[PATCH v1 3/5] x86/intel_pmc_core: Make debugfs entry for pch_ip_power_gating_status conditional

Check if the platform supports and only then add a debugfs entry for PCH IP power gating status. Cc: Peter Zijlstra Cc: Srinivas Pandruvada Cc: Andy Shevchenko Cc: Kan Liang Cc: David E. Box Cc: Rajneesh Bhardwaj Cc: Tony Luck Reviewed-by: Tony Luck Signed-off-by: Gayatri Kammela

[PATCH v1 1/5] x86/intel_pmc_core: Clean up: Remove comma after the termination line

-by: Gayatri Kammela --- drivers/platform/x86/intel_pmc_core.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c index 94a008efb09b..6ad829915689 100644 --- a/drivers/platform/x86/intel_pmc_core.c

[PATCH v1 2/5] x86/intel_pmc_core: Create platform dependent pmc bitmap structs

Luck Reviewed-by: Tony Luck Signed-off-by: Gayatri Kammela --- drivers/platform/x86/intel_pmc_core.c | 46 --- drivers/platform/x86/intel_pmc_core.h | 2 +- 2 files changed, 35 insertions(+), 13 deletions(-) diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers

[tip: x86/cpu] x86/cpu: Add Tiger Lake to Intel family

The following commit has been merged into the x86/cpu branch of tip: Commit-ID: 6e1c32c5dbb4b90eea8f964c2869d0bde050dbe0 Gitweb: https://git.kernel.org/tip/6e1c32c5dbb4b90eea8f964c2869d0bde050dbe0 Author:Gayatri Kammela AuthorDate:Thu, 05 Sep 2019 12:30:17 -07:00

[tip: x86/cpu] x86/cpu: Add Elkhart Lake to Intel family

The following commit has been merged into the x86/cpu branch of tip: Commit-ID: 0f65605a8d744b3a205d0a2cd8f20707e31fc023 Gitweb: https://git.kernel.org/tip/0f65605a8d744b3a205d0a2cd8f20707e31fc023 Author:Gayatri Kammela AuthorDate:Thu, 05 Sep 2019 12:30:18 -07:00

[tip:x86/cpu] x86/cpufeatures: Enable a new AVX512 CPU feature

Commit-ID: 018ebca8bd704f18d56f8fff38e2c3d76d7d39fb Gitweb: https://git.kernel.org/tip/018ebca8bd704f18d56f8fff38e2c3d76d7d39fb Author: Gayatri Kammela AuthorDate: Wed, 17 Jul 2019 16:46:32 -0700 Committer: Thomas Gleixner CommitDate: Mon, 22 Jul 2019 10:38:25 +0200 x86/cpufeatures

[tip:x86/cpu] cpu/cpuid-deps: Add a tab to cpuid dependent features

Commit-ID: 1e0c08e3034de0659367393bfa825188462f22e6 Gitweb: https://git.kernel.org/tip/1e0c08e3034de0659367393bfa825188462f22e6 Author: Gayatri Kammela AuthorDate: Wed, 17 Jul 2019 16:46:31 -0700 Committer: Thomas Gleixner CommitDate: Mon, 22 Jul 2019 10:38:24 +0200 cpu/cpuid-deps

[tip:perf/core] perf/x86/intel/uncore: Add new IMC PCI IDs for KabyLake, AmberLake and WhiskeyLake CPUs

Commit-ID: 6e86d3db5f8fb69eea76cc496c3c3da19c855aa9 Gitweb: https://git.kernel.org/tip/6e86d3db5f8fb69eea76cc496c3c3da19c855aa9 Author: Gayatri Kammela AuthorDate: Fri, 10 May 2019 17:03:11 -0700 Committer: Ingo Molnar CommitDate: Mon, 3 Jun 2019 11:58:20 +0200 perf/x86/intel/uncore

[tip:perf/core] perf/x86/intel/uncore: Add tabs to Uncore IMC PCI IDs

Commit-ID: 76a16b217a7f086c1c7c2d5f52efddb0c855b278 Gitweb: https://git.kernel.org/tip/76a16b217a7f086c1c7c2d5f52efddb0c855b278 Author: Gayatri Kammela AuthorDate: Fri, 10 May 2019 17:03:10 -0700 Committer: Ingo Molnar CommitDate: Mon, 3 Jun 2019 11:58:19 +0200 perf/x86/intel/uncore

[tip:x86/fpu] x86/cpufeatures: Enable new SSE/AVX/AVX512 CPU features

Commit-ID: c128dbfa0f879f8ce7b79054037889b0b2240728 Gitweb: https://git.kernel.org/tip/c128dbfa0f879f8ce7b79054037889b0b2240728 Author: Gayatri Kammela <gayatri.kamm...@intel.com> AuthorDate: Mon, 30 Oct 2017 18:20:29 -0700 Committer: Ingo Molnar <mi...@kernel.org> CommitD

[tip:x86/fpu] x86/cpufeatures: Enable new SSE/AVX/AVX512 CPU features

Commit-ID: c128dbfa0f879f8ce7b79054037889b0b2240728 Gitweb: https://git.kernel.org/tip/c128dbfa0f879f8ce7b79054037889b0b2240728 Author: Gayatri Kammela AuthorDate: Mon, 30 Oct 2017 18:20:29 -0700 Committer: Ingo Molnar CommitDate: Tue, 31 Oct 2017 11:02:26 +0100 x86/cpufeatures

[PATCH v2] x86/cpufeatures: Enable new SSE/AVX/AVX512 cpu features

com> Cc: Ricardo Neri <ricardo.n...@intel.com> Cc: Yang Zhong <yang.zh...@intel.com> Signed-off-by: Gayatri Kammela <gayatri.kamm...@intel.com> --- Changes since v1: 1) Rebased against the tip tree and so removed all the setup_clear flags arch/x86/include/asm/cpufeatures.h | 6

[PATCH v2] x86/cpufeatures: Enable new SSE/AVX/AVX512 cpu features

1-1. and Table 1-2.). A copy of this document is available at https://bugzilla.kernel.org/show_bug.cgi?id=197239 Cc: Thomas Gleixner Cc: Andi Kleen Cc: Ravi Shankar Cc: Fenghua Yu Cc: Ricardo Neri Cc: Yang Zhong Signed-off-by: Gayatri Kammela --- Changes since v1: 1) Rebased against the tip

[PATCH] x86/cpufeatures: Enable new AVX512 cpu features

gt; Cc: Yang Zhong <yang.zh...@intel.com> Signed-off-by: Gayatri Kammela <gayatri.kamm...@intel.com> --- arch/x86/include/asm/cpufeatures.h | 6 ++ arch/x86/kernel/fpu/xstate.c | 6 ++ 2 files changed, 12 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch

[PATCH] x86/cpufeatures: Enable new AVX512 cpu features

Programming Interface document (refer to Table 1-1. and Table 1-2.). A copy of this document is available at https://bugzilla.kernel.org/show_bug.cgi?id=197239 Cc: Ravi Shankar Cc: Fenghua Yu Cc: Ricardo Neri Cc: Yang Zhong Signed-off-by: Gayatri Kammela --- arch/x86/include/asm/cpufeatures.h

[tip:x86/cpufeature] x86/cpufeatures: Enable new AVX512 cpu features

Commit-ID: a8d9df5a509a232a959e4ef2e281f7ecd77810d6 Gitweb: http://git.kernel.org/tip/a8d9df5a509a232a959e4ef2e281f7ecd77810d6 Author: Gayatri Kammela <gayatri.kamm...@intel.com> AuthorDate: Wed, 16 Nov 2016 12:11:00 -0800 Committer: Thomas Gleixner <t...@linutronix.de> Com

[tip:x86/cpufeature] x86/cpufeatures: Enable new AVX512 cpu features

Commit-ID: a8d9df5a509a232a959e4ef2e281f7ecd77810d6 Gitweb: http://git.kernel.org/tip/a8d9df5a509a232a959e4ef2e281f7ecd77810d6 Author: Gayatri Kammela AuthorDate: Wed, 16 Nov 2016 12:11:00 -0800 Committer: Thomas Gleixner CommitDate: Thu, 17 Nov 2016 01:09:40 +0100 x86/cpufeatures

[PATCH v2] x86/cpufeatures: Enable new AVX512 cpu features

for the features can be found at https://bugzilla.kernel.org/show_bug.cgi?id=187891 Cc: Borislav Petkov <b...@alien8.de> Cc: H. Peter Anvin <h...@linux.intel.com> Cc: Ravi Shankar <ravi.v.shan...@intel.com> Cc: Fenghua Yu <fenghua...@intel.com> Signed-off-by: Gayatri Kammela <gayatri

[PATCH v2] x86/cpufeatures: Enable new AVX512 cpu features

for the features can be found at https://bugzilla.kernel.org/show_bug.cgi?id=187891 Cc: Borislav Petkov Cc: H. Peter Anvin Cc: Ravi Shankar Cc: Fenghua Yu Signed-off-by: Gayatri Kammela --- v1: Change commit message to add stable reference source. arch/x86/include/asm/cpufeatures.h | 2 ++ arch/x86

[PATCH] x86/cpufeatures: Enable new AVX512 cpu features

Detailed information of cpuid bits for the features can be found in Intel Architecture Instruction Set Extensions Programming Reference. Cc: H. Peter Anvin <h...@linux.intel.com> Cc: Ravi Shankar <ravi.v.shan...@intel.com> Cc: Fenghua Yu <fenghua...@intel.com> Signed-off-b

[PATCH] x86/cpufeatures: Enable new AVX512 cpu features

Detailed information of cpuid bits for the features can be found in Intel Architecture Instruction Set Extensions Programming Reference. Cc: H. Peter Anvin Cc: Ravi Shankar Cc: Fenghua Yu Signed-off-by: Gayatri Kammela --- arch/x86/include/asm/cpufeatures.h | 2 ++ arch/x86/kernel/fpu/xstate.c

[PATCH] x86/cpufeatures: Enable new AVX512 cpu features

Detailed information of cpuid bits for the features can be found in Intel Architecture Instruction Set Extensions Programming Reference. Cc: Ravi Shankar <ravi.v.shan...@intel.com> Cc: Fenghua Yu <fenghua...@intel.com> Signed-off-by: Gayatri Kammela <gayatri.kamm...@intel.com> ---

[PATCH] x86/cpufeatures: Enable new AVX512 cpu features

Detailed information of cpuid bits for the features can be found in Intel Architecture Instruction Set Extensions Programming Reference. Cc: Ravi Shankar Cc: Fenghua Yu Signed-off-by: Gayatri Kammela --- arch/x86/include/asm/cpufeatures.h | 2 ++ arch/x86/kernel/fpu/xstate.c | 2 ++ 2

[PATCH] lib/raid6: Add AVX2 optimized xor_syndrome functions

Implement the AVX2 optimization of RAID6 xor_syndrome functions which is simply based on sse2.c written by hpa. Cc: H. Peter Anvin <h...@linux.intel.com> Cc: Yuanhan Liu <yuanhan@intel.com> Cc: Fenghua Yu <fenghua...@intel.com> Signed-off-by: Gayatri Kammela <gaya

[PATCH] lib/raid6: Add AVX2 optimized xor_syndrome functions

Implement the AVX2 optimization of RAID6 xor_syndrome functions which is simply based on sse2.c written by hpa. Cc: H. Peter Anvin Cc: Yuanhan Liu Cc: Fenghua Yu Signed-off-by: Gayatri Kammela --- lib/raid6/avx2.c | 232 ++- 1 file changed

[PATCH v2] raid6/test/test.c: bug fix: Specify aligned(alignment) attributes to the char arrays

. The RAID stripes will be page aligned anyway, so we want to test what the kernel actually will execute. Cc: H. Peter Anvin <h...@zytor.com> Cc: Yu-cheng Yu <yu-cheng...@intel.com> Signed-off-by: Gayatri Kammela <gayatri.kamm...@intel.com> Reviewed-by: H. Peter Anvin <

[PATCH v2] raid6/test/test.c: bug fix: Specify aligned(alignment) attributes to the char arrays

. The RAID stripes will be page aligned anyway, so we want to test what the kernel actually will execute. Cc: H. Peter Anvin Cc: Yu-cheng Yu Signed-off-by: Gayatri Kammela Reviewed-by: H. Peter Anvin --- lib/raid6/test/test.c | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff

[PATCH] raid6/test/test.c: bug fix: Specify aligned(alignment) attributes to the char arrays

t;h...@zytor.com> Cc: Yu-cheng Yu <yu-cheng...@intel.com> Signed-off-by: Gayatri Kammela <gayatri.kamm...@intel.com> Reviewed-by: H. Peter Anvin <h...@linux.intel.com> --- lib/raid6/test/test.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/lib/raid6/test

[PATCH] raid6/test/test.c: bug fix: Specify aligned(alignment) attributes to the char arrays

-cheng Yu Signed-off-by: Gayatri Kammela Reviewed-by: H. Peter Anvin --- lib/raid6/test/test.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/lib/raid6/test/test.c b/lib/raid6/test/test.c index 3bebbabdb510..32a00f11ac50 100644 --- a/lib/raid6/test/test.c +++ b/lib/raid6

[PATCH v2] raid6/test/test.c: bug fix: Specify aligned(alignment) attributes to the char arrays

t;h...@zytor.com> Cc: Yu-cheng Yu <yu-cheng...@intel.com> Signed-off-by: Gayatri Kammela <gayatri.kamm...@intel.com> --- lib/raid6/test/test.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/lib/raid6/test/test.c b/lib/raid6/test/test.c index 3bebbabdb510..3

[PATCH v2] raid6/test/test.c: bug fix: Specify aligned(alignment) attributes to the char arrays

-cheng Yu Signed-off-by: Gayatri Kammela --- lib/raid6/test/test.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/lib/raid6/test/test.c b/lib/raid6/test/test.c index 3bebbabdb510..32a00f11ac50 100644 --- a/lib/raid6/test/test.c +++ b/lib/raid6/test/test.c @@ -21,12 +21,13

[PATCH v2 4/6] lib/raid6: Add AVX512 optimized xor_syndrome functions

flags to support such instructions Cc: H. Peter Anvin <h...@zytor.com> Cc: Jim Kukunas <james.t.kuku...@linux.intel.com> Cc: Fenghua Yu <fenghua...@intel.com> Cc: Megha Dey <megha@linux.intel.com> Signed-off-by: Gayatri Kammela <gayatri.kamm...@intel.com> Re

[PATCH v2 2/6] lib/raid6: Add AVX512 optimized recovery functions

AVX512 flags to support such instructions Cc: Jim Kukunas <james.t.kuku...@linux.intel.com> Cc: H. Peter Anvin <h...@zytor.com> Cc: Fenghua Yu <fenghua...@intel.com> Signed-off-by: Megha Dey <megha@linux.intel.com> Signed-off-by: Gayatri Kammela <gayatri.kamm...@intel.c

[PATCH v2 4/6] lib/raid6: Add AVX512 optimized xor_syndrome functions

flags to support such instructions Cc: H. Peter Anvin Cc: Jim Kukunas Cc: Fenghua Yu Cc: Megha Dey Signed-off-by: Gayatri Kammela Reviewed-by: Fenghua Yu --- lib/raid6/avx512.c | 281 - 1 file changed, 278 insertions(+), 3 deletions(-) diff

[PATCH v2 2/6] lib/raid6: Add AVX512 optimized recovery functions

AVX512 flags to support such instructions Cc: Jim Kukunas Cc: H. Peter Anvin Cc: Fenghua Yu Signed-off-by: Megha Dey Signed-off-by: Gayatri Kammela Reviewed-by: Fenghua Yu --- include/linux/raid/pq.h | 1 + lib/raid6/Makefile | 2 +- lib/raid6/algos.c| 3 + lib/raid6

[PATCH v2 1/6] lib/raid6: Add AVX512 optimized gen_syndrome functions

on a hardware that has AVX512 flags to support such instructions Cc: H. Peter Anvin <h...@zytor.com> Cc: Jim Kukunas <james.t.kuku...@linux.intel.com> Cc: Fenghua Yu <fenghua...@intel.com> Signed-off-by: Megha Dey <megha@linux.intel.com> Signed-off-by: Gayatri Kammela &l

[PATCH v2 1/6] lib/raid6: Add AVX512 optimized gen_syndrome functions

on a hardware that has AVX512 flags to support such instructions Cc: H. Peter Anvin Cc: Jim Kukunas Cc: Fenghua Yu Signed-off-by: Megha Dey Signed-off-by: Gayatri Kammela Reviewed-by: Fenghua Yu --- arch/x86/Makefile | 5 +- include/linux/raid/pq.h | 3 + lib/raid6/Makefile

[PATCH v2 0/6] Add AVX512 optimized gen_syndrome, xor_syndrome and recovery functions

xor_syndrome functions to avx512 optimized raid6. Gayatri Kammela (6): lib/raid6: Add AVX512 optimized gen_syndrome functions lib/raid6: Add AVX512 optimized recovery functions lib/raid6/test/Makefile: Add avx512 gen_syndrome and recovery functions lib/raid6: Add AVX512 optimized

[PATCH v2 5/6] (DO NOT APPLY) lib/raid6: Add unroll by 8 to AVX512 optimized gen_syndrome functions

a@linux.intel.com> Signed-off-by: Gayatri Kammela <gayatri.kamm...@intel.com> Reviewed-by: Fenghua Yu <fenghua...@intel.com> --- include/linux/raid/pq.h | 1 + lib/raid6/algos.c | 1 + lib/raid6/avx512.c | 172 3 files ch

[PATCH v2 3/6] lib/raid6/test/Makefile: Add avx512 gen_syndrome and recovery functions

l.com> Cc: Fenghua Yu <fenghua...@intel.com> Signed-off-by: Megha Dey <megha@linux.intel.com> Signed-off-by: Gayatri Kammela <gayatri.kamm...@intel.com> Reviewed-by: Fenghua Yu <fenghua...@intel.com> --- lib/raid6/test/Makefile | 5 - 1 file changed, 4 insertions(+), 1

[PATCH v2 6/6] (DO NOT APPLY) lib/raid6: Add unroll by 8 to AVX512 optimized xor_syndrome functions.

when tested in userspace. This is posted for reference only, to allow others to make their own experiments. Cc: H. Peter Anvin <h...@zytor.com> Cc: Jim Kukunas <james.t.kuku...@linux.intel.com> Cc: Fenghua Yu <fenghua...@intel.com> Cc: Megha Dey <megha@linux.intel.com>

[PATCH v2 0/6] Add AVX512 optimized gen_syndrome, xor_syndrome and recovery functions

xor_syndrome functions to avx512 optimized raid6. Gayatri Kammela (6): lib/raid6: Add AVX512 optimized gen_syndrome functions lib/raid6: Add AVX512 optimized recovery functions lib/raid6/test/Makefile: Add avx512 gen_syndrome and recovery functions lib/raid6: Add AVX512 optimized

[PATCH v2 5/6] (DO NOT APPLY) lib/raid6: Add unroll by 8 to AVX512 optimized gen_syndrome functions

when tested in user as well as kernel space. This is posted for reference only, to allow others to make their own experiments. Cc: H. Peter Anvin Cc: Jim Kukunas Cc: Fenghua Yu Cc: Megha Dey Signed-off-by: Gayatri Kammela Reviewed-by: Fenghua Yu --- include/linux/raid/pq.h | 1 + lib

[PATCH v2 3/6] lib/raid6/test/Makefile: Add avx512 gen_syndrome and recovery functions

-by: Gayatri Kammela Reviewed-by: Fenghua Yu --- lib/raid6/test/Makefile | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/lib/raid6/test/Makefile b/lib/raid6/test/Makefile index 29090f3db677..2c7b60edea04 100644 --- a/lib/raid6/test/Makefile +++ b/lib/raid6/test/Makefile @@ -32,10

[PATCH v2 6/6] (DO NOT APPLY) lib/raid6: Add unroll by 8 to AVX512 optimized xor_syndrome functions.

when tested in userspace. This is posted for reference only, to allow others to make their own experiments. Cc: H. Peter Anvin Cc: Jim Kukunas Cc: Fenghua Yu Cc: Megha Dey Signed-off-by: Gayatri Kammela Reviewed-by: Fenghua Yu --- lib/raid6/avx512.c | 235

[PATCH 4/4] (DO NOT APPLY) lib/raid6: Add unroll by 8 to AVX512 optimized gen_syndrome functions

when tested in user as well as kernel space. This is posted for reference only, to allow others to make their own experiments. Cc: H. Peter Anvin <h...@zytor.com> Cc: Jim Kukunas <james.t.kuku...@linux.intel.com> Cc: Fenghua Yu <fenghua...@intel.com> Signed-off-by: Gayatri Kam

[PATCH 4/4] (DO NOT APPLY) lib/raid6: Add unroll by 8 to AVX512 optimized gen_syndrome functions

when tested in user as well as kernel space. This is posted for reference only, to allow others to make their own experiments. Cc: H. Peter Anvin Cc: Jim Kukunas Cc: Fenghua Yu Signed-off-by: Gayatri Kammela --- include/linux/raid/pq.h | 1 + lib/raid6/algos.c | 1 + lib/raid6

[PATCH 3/4] lib/raid6/test/Makefile: Add avx512 gen_syndrome and recovery functions

l.com> Cc: Fenghua Yu <fenghua...@intel.com> Signed-off-by: Megha Dey <megha@linux.intel.com> Signed-off-by: Gayatri Kammela <gayatri.kamm...@intel.com> --- lib/raid6/test/Makefile | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/lib/raid6/test/Makefile b

[PATCH 2/4] lib/raid6: Add AVX512 optimized recovery functions

AVX512 flags to support such instructions Cc: Jim Kukunas <james.t.kuku...@linux.intel.com> Cc: H. Peter Anvin <h...@zytor.com> Cc: Fenghua Yu <fenghua...@intel.com> Signed-off-by: Megha Dey <megha@linux.intel.com> Signed-off-by: Gayatri Kammela <gayatri.kamm...@intel.c

[PATCH 3/4] lib/raid6/test/Makefile: Add avx512 gen_syndrome and recovery functions

-by: Gayatri Kammela --- lib/raid6/test/Makefile | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/lib/raid6/test/Makefile b/lib/raid6/test/Makefile index 29090f3..2c7b60e 100644 --- a/lib/raid6/test/Makefile +++ b/lib/raid6/test/Makefile @@ -32,10 +32,13 @@ ifeq ($(ARCH),arm64

[PATCH 2/4] lib/raid6: Add AVX512 optimized recovery functions

AVX512 flags to support such instructions Cc: Jim Kukunas Cc: H. Peter Anvin Cc: Fenghua Yu Signed-off-by: Megha Dey Signed-off-by: Gayatri Kammela --- include/linux/raid/pq.h | 1 + lib/raid6/Makefile | 2 +- lib/raid6/algos.c| 3 + lib/raid6/recov_avx512.c | 335

[PATCH 1/4] lib/raid6: Add AVX512 optimized gen_syndrome functions

on a hardware that has AVX512 flags to support such instructions Cc: H. Peter Anvin <h...@zytor.com> Cc: Jim Kukunas <james.t.kuku...@linux.intel.com> Cc: Fenghua Yu <fenghua...@intel.com> Signed-off-by: Megha Dey <megha@linux.intel.com> Signed-off-by: Gayatri Kammela &l

[PATCH 1/4] lib/raid6: Add AVX512 optimized gen_syndrome functions

on a hardware that has AVX512 flags to support such instructions Cc: H. Peter Anvin Cc: Jim Kukunas Cc: Fenghua Yu Signed-off-by: Megha Dey Signed-off-by: Gayatri Kammela --- arch/x86/Makefile | 5 +- include/linux/raid/pq.h | 3 + lib/raid6/Makefile | 2 +- lib/raid6/algos.c

[PATCH 0/4] Add AVX512 optimized gen_syndrome and recovery functions

This is the patch set for adding AVX512 optimized gen_syndrome and recovery functions. Optimization of RAID6 using AVX512 instructions should improve the RAID6 performance.These patches are tested and observed the improvement in performance. Gayatri Kammela (4): lib/raid6: Add AVX512 optimized

[PATCH 0/4] Add AVX512 optimized gen_syndrome and recovery functions

This is the patch set for adding AVX512 optimized gen_syndrome and recovery functions. Optimization of RAID6 using AVX512 instructions should improve the RAID6 performance.These patches are tested and observed the improvement in performance. Gayatri Kammela (4): lib/raid6: Add AVX512 optimized

[PATCH] raid6/algos.c : bug fix : Add the missing definitions to the pq.h file

' ' ' undefined reference to `pr_err' ' Cc: NeilBrown Cc: Anton Blanchard Cc: Fenghua Yu Signed-off-by: Gayatri Kammela --- include/linux/raid/pq.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/linux/raid/pq.h b/include/linux/raid/pq.h index a7a06d1dcf9c..a0118d5929a9 100644

[PATCH] raid6/algos.c : bug fix : Add the missing definitions to the pq.h file

' ' ' undefined reference to `pr_err' ' Cc: NeilBrown <ne...@suse.com> Cc: Anton Blanchard <an...@samba.org> Cc: Fenghua Yu <fenghua...@intel.com> Signed-off-by: Gayatri Kammela <gayatri.kamm...@intel.com> --- include/linux/raid/pq.h | 2 ++ 1 file changed, 2 insertions(+) diff --