Re: Context switch latency in tickless isolated CPU

On Sun, Aug 21, 2016 at 10:53 PM, Paul E. McKenney wrote: > If latency is all you care about, one approach is to map the device > registers into userspace and do the I/O without assistance from the > kernel. In addition to the context switch latency, local interrupts

Re: Context switch latency in tickless isolated CPU

On Sun, Aug 21, 2016 at 10:53 PM, Paul E. McKenney wrote: > If latency is all you care about, one approach is to map the device > registers into userspace and do the I/O without assistance from the > kernel. In addition to the context switch latency, local interrupts are also closed during

Re: Context switch latency in tickless isolated CPU

On Fri, Aug 19, 2016 at 8:34 PM, Peter Zijlstra wrote: > Why are you wanting to use nohz_full if you do syscalls? We hope to reduce the overhead of the tick while the real time applications run, and these applications might do some syscalls to operate the I/O devices like

Re: Context switch latency in tickless isolated CPU

On Fri, Aug 19, 2016 at 8:34 PM, Peter Zijlstra wrote: > Why are you wanting to use nohz_full if you do syscalls? We hope to reduce the overhead of the tick while the real time applications run, and these applications might do some syscalls to operate the I/O devices like EtherCAT.

Re: Context switch latency in tickless isolated CPU

wrote: > On 8/17/2016 2:26 AM, GeHao Kang wrote: >> >> To investigate the cause, I use the kernel event tracer to find out >> the events, user_enter and user_exit, of context_tracking would happen >> on tickless isolated CPU. These two events means that this CPU enters >&g

Re: Context switch latency in tickless isolated CPU

AM, GeHao Kang wrote: >> >> To investigate the cause, I use the kernel event tracer to find out >> the events, user_enter and user_exit, of context_tracking would happen >> on tickless isolated CPU. These two events means that this CPU enters >> and exits the RCU

Context switch latency in tickless isolated CPU

Hi Frederic and Chris, When the lmbench runs on the tickless isolated CPU, the context switch latency on this CPU is higher than the one on other CPU. The test platform is Linux 4.4.12 with NO_HZ_FULL on I.MX6Q sabresd. The following is the lmbench results about context switch: lmbench runs on

Context switch latency in tickless isolated CPU

Hi Frederic and Chris, When the lmbench runs on the tickless isolated CPU, the context switch latency on this CPU is higher than the one on other CPU. The test platform is Linux 4.4.12 with NO_HZ_FULL on I.MX6Q sabresd. The following is the lmbench results about context switch: lmbench runs on