Re: [PATCH] xhci: Add quirk to workaround the errata seen on Cavium Thunder-X2 Soc

2018-10-28 Thread George Cherian
Hi Alan, Thanks for the review. I will update the patch accordingly and send out v2. On 10/28/2018 10:48 PM, Alan Stern wrote: > > On Sat, 27 Oct 2018, Cherian, George wrote: > >> Implement workaround for ThunderX2 Errata-129 (documented in >> CN99XX Known Issues" available at Cavium support

Re: [PATCH 2/2] ipmi_ssif: Fix crash seen while ipmi_unregister_smi

2018-08-26 Thread George Cherian
Hi Corey, On 08/24/2018 06:38 PM, Corey Minyard wrote: On 08/24/2018 06:10 AM, George Cherian wrote: Dont set ssif_info->intf to NULL before ipmi_unresgiter_smi. shutdown_ssif will anyways free ssif_info. This is correct, but it goes a little deeper.  I just sent out a patch yester

[PATCH v2] i2c: xlp9xx: Fix case where SSIF read transaction completes early

2018-08-09 Thread George Cherian
the code to drain the RX fifo after the length update, so that the transaction completes correctly in all cases. Signed-off-by: George Cherian --- drivers/i2c/busses/i2c-xlp9xx.c | 41 - 1 file changed, 28 insertions(+), 13 deletions(-) diff --git a/drivers/i2c

Re: Re: [PATCH] i2c: xlp9xx: Fix case where SSIF read transaction completes early

2018-08-02 Thread George Cherian
Hi Wolfran, Thanks for the review. I will update the patch with a small comment section above len --; so that there is no confusion. On 08/01/2018 02:35 AM, Wolfram Sang wrote: --- a/drivers/i2c/busses/i2c-xlp9xx.c +++ b/drivers/i2c/busses/i2c-xlp9xx.c @@ -191,28 +191,30 @@ static void

[PATCH] i2c: xlp9xx: Fix case where SSIF read transaction completes early

2018-07-22 Thread George Cherian
the code to drain the RX fifo after the length update, so that the transaction completes correctly in all cases. Signed-off-by: George Cherian --- drivers/i2c/busses/i2c-xlp9xx.c | 28 +++- 1 file changed, 15 insertions(+), 13 deletions(-) diff --git a/drivers/i2c/busses/i2c

[PATCH v4] cpufreq / CPPC: Add cpuinfo_cur_freq support for CPPC

2018-07-12 Thread George Cherian
counter). Implement the above and hook this to the cpufreq->get method. Signed-off-by: George Cherian Acked-by: Viresh Kumar --- drivers/cpufreq/cppc_cpufreq.c | 52 ++ 1 file changed, 52 insertions(+) diff --git a/drivers/cpufreq/cppc_cpufreq.c b/driv

Re: [PATCH v3] cpufreq / CPPC: Add cpuinfo_cur_freq support for CPPC

2018-07-10 Thread George Cherian
Hi Prakash, On 07/10/2018 09:19 PM, Prakash, Prashanth wrote: On 7/9/2018 11:42 PM, George Cherian wrote: Hi Prakash, On 07/09/2018 10:12 PM, Prakash, Prashanth wrote: Hi George, On 7/9/2018 4:10 AM, George Cherian wrote: Per Section 8.4.7.1.3 of ACPI 6.2, The platform provides

Re: [PATCH v3] cpufreq / CPPC: Add cpuinfo_cur_freq support for CPPC

2018-07-09 Thread George Cherian
Hi Prakash, On 07/09/2018 10:12 PM, Prakash, Prashanth wrote: Hi George, On 7/9/2018 4:10 AM, George Cherian wrote: Per Section 8.4.7.1.3 of ACPI 6.2, The platform provides performance feedback via set of performance counters. To determine the actual performance level delivered over time

[PATCH v3] cpufreq / CPPC: Add cpuinfo_cur_freq support for CPPC

2018-07-09 Thread George Cherian
counter). Implement the above and hook this to the cpufreq->get method. Signed-off-by: George Cherian Acked-by: Viresh Kumar --- drivers/cpufreq/cppc_cpufreq.c | 44 ++ 1 file changed, 44 insertions(+) diff --git a/drivers/cpufreq/cppc_cpufreq.c b/driv

Re: [v2] cpufreq / CPPC: Add cpuinfo_cur_freq support for CPPC

2018-06-20 Thread George Cherian
Hi JC, Thanks for the review. On 06/20/2018 02:09 AM, Jayachandran C wrote: Hi George, Few comments on your patch: On Fri, Jun 15, 2018 at 03:03:15AM -0700, George Cherian wrote: Per Section 8.4.7.1.3 of ACPI 6.2, The platform provides performance feedback via set of performance counters

Re: [PATCH v2] cpufreq / CPPC: Add cpuinfo_cur_freq support for CPPC

2018-06-20 Thread George Cherian
Hi Prakash, Thanks for the review. On 06/19/2018 01:51 AM, Prakash, Prashanth wrote: External Email Hi George, On 6/15/2018 4:03 AM, George Cherian wrote: Per Section 8.4.7.1.3 of ACPI 6.2, The platform provides performance feedback via set of performance counters. To determine the actual

[PATCH v2] cpufreq / CPPC: Add cpuinfo_cur_freq support for CPPC

2018-06-15 Thread George Cherian
counter). Implement the above and hook this to the cpufreq->get method. Signed-off-by: George Cherian Acked-by: Viresh Kumar --- drivers/cpufreq/cppc_cpufreq.c | 71 ++ 1 file changed, 71 insertions(+) diff --git a/drivers/cpufreq/cppc_cpufreq.c b/driv

Re: [PATCH] cpufreq / CPPC: Add cpuinfo_cur_freq support for CPPC

2018-05-31 Thread George Cherian
Hi Prashanth, On 05/29/2018 09:14 PM, Prakash, Prashanth wrote: On 5/28/2018 1:09 AM, George Cherian wrote: Hi Prashanth, On 05/26/2018 02:30 AM, Prakash, Prashanth wrote: On 5/25/2018 12:27 AM, George Cherian wrote: Hi Prashanth, On 05/25/2018 12:55 AM, Prakash, Prashanth wrote: Hi

Re: [PATCH] cpufreq / CPPC: Add cpuinfo_cur_freq support for CPPC

2018-05-28 Thread George Cherian
Hi Prashanth, On 05/26/2018 02:30 AM, Prakash, Prashanth wrote: On 5/25/2018 12:27 AM, George Cherian wrote: Hi Prashanth, On 05/25/2018 12:55 AM, Prakash, Prashanth wrote: Hi George, On 5/22/2018 5:42 AM, George Cherian wrote: Per Section 8.4.7.1.3 of ACPI 6.2, The platform provides

Re: [PATCH] cpufreq / CPPC: Add cpuinfo_cur_freq support for CPPC

2018-05-25 Thread George Cherian
Hi Prashanth, On 05/25/2018 12:55 AM, Prakash, Prashanth wrote: Hi George, On 5/22/2018 5:42 AM, George Cherian wrote: Per Section 8.4.7.1.3 of ACPI 6.2, The platform provides performance feedback via set of performance counters. To determine the actual performance level delivered over time

[PATCH] cpufreq / CPPC: Add cpuinfo_cur_freq support for CPPC

2018-05-22 Thread George Cherian
counter). Implement the above and hook this to the cpufreq->get method. Signed-off-by: George Cherian <george.cher...@cavium.com> --- drivers/cpufreq/cppc_cpufreq.c | 44 ++ 1 file changed, 44 insertions(+) diff --git a/drivers/cpufreq/cppc_cpufreq.c

[PATCH 1/4] i2c: xlp9xx: Add support for SMBAlert

2018-05-16 Thread George Cherian
Add support for SMBus alert mechanism to i2c-xlp9xx driver. The second interrupt is parsed to use for SMBus alert. The first interrupt is the i2c controller main interrupt. Signed-off-by: Kamlakant Patel <kamlakant.pa...@cavium.com> Signed-off-by: George Cherian <george.cher...@c

[PATCH 3/4] i2c: xlp9xx: Make sure the transfer size is not more than I2C_SMBUS_BLOCK_SIZE

2018-05-16 Thread George Cherian
-off-by: Jayachandran C <jn...@caviumnetworks.com> Signed-off-by: George Cherian <george.cher...@cavium.com> --- drivers/i2c/busses/i2c-xlp9xx.c | 37 - 1 file changed, 24 insertions(+), 13 deletions(-) diff --git a/drivers/i2c/busses/i2c-xlp9xx.c b

[PATCH 4/4] i2c: xlp9xx: Add MAINTAINERS entry

2018-05-16 Thread George Cherian
The i2c XLP9xx driver is maintained by Cavium. Add George Cherian and Jan Glauber as the Maintainers. Signed-off-by: George Cherian <george.cher...@cavium.com> --- MAINTAINERS | 8 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index df6e9bb..68da265

[PATCH 2/4] i2c: xlp9xx: Fix issue seen when updating receive length

2018-05-16 Thread George Cherian
sure that the new length written to hardware is at least few bytes more than the bytes received so far. While at that refactor the length updation to a new function. Signed-off-by: Jayachandran C <jn...@caviumnetworks.com> Signed-off-by: George Cherian <george.cher...@cavium.com> ---

[PATCH 0/4] i2c-xlp9xx Add support for SMBAlert and minor fixes

2018-05-16 Thread George Cherian
the MAINATINERS file to reflect the current maintainers of the driver. George Cherian (4): i2c: xlp9xx: Add support for SMBAlert i2c: xlp9xx: Fix issue seen when updating receive length i2c: xlp9xx: Make sure the transfer size is not more than I2C_SMBUS_BLOCK_SIZE i2c: xlp9xx: Add MAINTAINERS

[PATCH] cpufreq: cppc: Use transition_delay_us depending on the transition_latency

2018-03-23 Thread George Cherian
8fbee0 (cpufreq: Cap the default transition delay value to 10 ms) Signed-off-by: George Cherian <george.cher...@cavium.com> --- drivers/cpufreq/cppc_cpufreq.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/cpufreq/cppc_cpufreq.c b/drivers/cpufreq/cppc_cpufreq.c index a1c3025..dc

Re: [PATCH] PCI: Add quirk for Cavium Thunder-X2 PCIe erratum #173

2018-03-13 Thread George Cherian
Hi Bjorn, On 02/22/2018 08:39 PM, Bjorn Helgaas wrote: On Thu, Feb 22, 2018 at 06:43:34PM +0530, George Cherian wrote: On 02/22/2018 04:50 AM, Bjorn Helgaas wrote: On Wed, Feb 21, 2018 at 04:25:08PM +0530, George Cherian wrote: On 02/21/2018 03:24 PM, Lukas Wunner wrote: On Wed, Feb 21

[PATCH v2] i2c: xlp9xx: Add support for SMBAlert

2018-03-06 Thread George Cherian
Add support for SMBus alert mechanism to i2c-xlp9xx driver. The second interrupt is parsed to use for SMBus alert. The first interrupt is the i2c controller main interrupt. Signed-off-by: Kamlakant Patel <kamlakant.pa...@cavium.com> Signed-off-by: George Cherian <george.cher...@c

Re: [PATCH 3/3] i2c: xlp9xx: Add support for SMBAlert

2018-03-06 Thread George Cherian
On 03/06/2018 02:48 PM, Phil Reid wrote: On 6/03/2018 16:36, Jan Glauber wrote: On Tue, Feb 27, 2018 at 01:26:20PM +, George Cherian wrote: Add support for SMBus alert mechanism to i2c-xlp9xx driver. The second interrupt is parsed to use for SMBus alert. The first interrupt is the i2c

[PATCHv2 1/3] i2c: xlp9xx: Check for Bus state before every transfer

2018-02-27 Thread George Cherian
sure the bus is not busy before every transaction. Signed-off-by: George Cherian <george.cher...@cavium.com> --- drivers/i2c/busses/i2c-xlp9xx.c | 32 1 file changed, 32 insertions(+) diff --git a/drivers/i2c/busses/i2c-xlp9xx.c b/drivers/i2c/busses/i2c-xl

[PATCH 3/3] i2c: xlp9xx: Add support for SMBAlert

2018-02-27 Thread George Cherian
Add support for SMBus alert mechanism to i2c-xlp9xx driver. The second interrupt is parsed to use for SMBus alert. The first interrupt is the i2c controller main interrupt. Signed-off-by: Kamlakant Patel <kamlakant.pa...@cavium.com> Signed-off-by: George Cherian <george.cher...@c

[PATCH 2/3] i2c: xlp9xx: Handle NACK on DATA properly

2018-02-27 Thread George Cherian
for such transactions. Signed-off-by: George Cherian <george.cher...@cavium.com> --- drivers/i2c/busses/i2c-xlp9xx.c | 14 -- 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/i2c/busses/i2c-xlp9xx.c b/drivers/i2c/busses/i2c-xlp9xx.c index 42dd1fa..eb8913e 100644 --- a/d

Re: [PATCH 4/4] i2c: xlp9xx: Check for Bus state after every transfer

2018-02-27 Thread George Cherian
Hi Wolfram, On 02/27/2018 02:35 PM, Wolfram Sang wrote: Since you raised concern on the patch I thought of reworking this patch. But I can see that this patch is already applied for i2c/for-next. Kindly let me know whether I should be sending follow-up patches on top of i2c/for-next ? Oops,

Re: [PATCH 4/4] i2c: xlp9xx: Check for Bus state after every transfer

2018-02-27 Thread George Cherian
Hi Wolfram, On 02/27/2018 02:34 PM, Wolfram Sang wrote: On Tue, Feb 27, 2018 at 10:30:31AM +0530, George Cherian wrote: Hi Wolfram, Thanks for the review. On 02/27/2018 01:52 AM, Wolfram Sang wrote: On Thu, Jan 18, 2018 at 05:39:24AM +, George Cherian wrote: I2C bus enters the STOP

Re: [PATCH 4/4] i2c: xlp9xx: Check for Bus state after every transfer

2018-02-26 Thread George Cherian
Hi Wolfram, On 02/27/2018 10:30 AM, George Cherian wrote: Hi Wolfram, Thanks for the review. On 02/27/2018 01:52 AM, Wolfram Sang wrote: On Thu, Jan 18, 2018 at 05:39:24AM +, George Cherian wrote: I2C bus enters the STOP condition after the DATA_DONE interrupt is raised. Essentially

Re: [PATCH 4/4] i2c: xlp9xx: Check for Bus state after every transfer

2018-02-26 Thread George Cherian
Hi Wolfram, Thanks for the review. On 02/27/2018 01:52 AM, Wolfram Sang wrote: On Thu, Jan 18, 2018 at 05:39:24AM +, George Cherian wrote: I2C bus enters the STOP condition after the DATA_DONE interrupt is raised. Essentially the driver should be checking the bus state before sending

Re: [PATCH] PCI: Add quirk for Cavium Thunder-X2 PCIe erratum #173

2018-02-22 Thread George Cherian
Hi Bjorn, On 02/22/2018 04:50 AM, Bjorn Helgaas wrote: On Wed, Feb 21, 2018 at 04:25:08PM +0530, George Cherian wrote: On 02/21/2018 03:24 PM, Lukas Wunner wrote: On Wed, Feb 21, 2018 at 02:58:13PM +0530, George Cherian wrote: I will explain the setup used To the Cavium ThunderX RC

Re: [PATCH] PCI: Add quirk for Cavium Thunder-X2 PCIe erratum #173

2018-02-21 Thread George Cherian
Hi Lukas, On 02/21/2018 03:24 PM, Lukas Wunner wrote: On Wed, Feb 21, 2018 at 02:58:13PM +0530, George Cherian wrote: I will explain the setup used To the Cavium ThunderX RC the following PLX device is connected. PLX Technology, Inc. PEX 8747 48-Lane, 5-Port PCI Express Gen 3 (8.0 GT/s) Switch

Re: [PATCH] PCI: Add quirk for Cavium Thunder-X2 PCIe erratum #173

2018-02-21 Thread George Cherian
Hi Bjorn, On 02/21/2018 12:30 AM, Bjorn Helgaas wrote: [+cc Huang] On Tue, Feb 20, 2018 at 02:54:33AM +0100, Lukas Wunner wrote: On Mon, Feb 19, 2018 at 12:21:56PM +0100, Rafael J. Wysocki wrote: On Friday, February 16, 2018 9:34:34 PM CET Bjorn Helgaas wrote: On Fri, Feb 16, 2018 at

[PATCH] ACPI / CPPC: Update all pr_(debug/err) messages to log the susbspace id

2018-02-20 Thread George Cherian
CPPC dirver is aware of multiple PCC subspace IDs. Enhance the debug and error messages in the driver to print the subspace id. In case of error it will be helpful to find which particular subspace is failing. Signed-off-by: George Cherian <george.cher...@cavium.com> --- drivers/acpi/cppc_

Re: [PATCH] PCI: Add quirk for Cavium Thunder-X2 PCIe erratum #173

2018-02-14 Thread George Cherian
Hi Bjorn, Thanks for the review. On 02/13/2018 08:39 PM, Bjorn Helgaas wrote: [+cc Lorenzo] On Fri, Feb 02, 2018 at 07:00:46AM +, George Cherian wrote: The PCIe Controller on Cavium ThunderX2 processors does not respond to downstream CFG/ECFG cycles when root port is in power management

[PATCH] PCI: Add quirk for Cavium Thunder-X2 PCIe erratum #173

2018-02-01 Thread George Cherian
a quirk that prevents the root port from entering D3 state. This is seen on both Ax/Bx variants of the processor. Signed-off-by: George Cherian <george.cher...@cavium.com> --- drivers/pci/quirks.c | 12 1 file changed, 12 insertions(+) diff --git a/drivers/pci/quirks.c b/drive

Re: [PATCH 1/4] i2c: xlp9xx: return ENXIO on slave address NACK

2018-01-30 Thread George Cherian
Gentle Ping on this series. On 01/18/2018 11:09 AM, George Cherian wrote: From: Dmitry Bazhenov <dmitry.bazhe...@auriga.com> Fix the driver violation of the common practice to return ENXIO error on a slave address NACK. Signed-off-by: Dmitry Bazhenov <dmitry.bazhe...@auriga.com>

[PATCH 2/4] i2c: xlp9xx: Handle transactions with I2C_M_RECV_LEN properly

2018-01-17 Thread George Cherian
on the received length. Signed-off-by: George Cherian <george.cher...@cavium.com> --- drivers/i2c/busses/i2c-xlp9xx.c | 31 --- 1 file changed, 24 insertions(+), 7 deletions(-) diff --git a/drivers/i2c/busses/i2c-xlp9xx.c b/drivers/i2c/busses/i2c-xlp9xx.c index 6d78cdc..b

[PATCH 3/4] i2c: xlp9xx: report SMBus block read functionality

2018-01-17 Thread George Cherian
From: Dmitry Bazhenov Report SMBus block read functionality which is actually supported. Signed-off-by: Dmitry Bazhenov --- drivers/i2c/busses/i2c-xlp9xx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git

[PATCH 1/4] i2c: xlp9xx: return ENXIO on slave address NACK

2018-01-17 Thread George Cherian
From: Dmitry Bazhenov <dmitry.bazhe...@auriga.com> Fix the driver violation of the common practice to return ENXIO error on a slave address NACK. Signed-off-by: Dmitry Bazhenov <dmitry.bazhe...@auriga.com> Signed-off-by: George Cherian <george.cher...@cavium.com> --- driv

[PATCH 4/4] i2c: xlp9xx: Check for Bus state after every transfer

2018-01-17 Thread George Cherian
the check to make sure the bus is not busy before next transaction. Signed-off-by: George Cherian <george.cher...@cavium.com> --- drivers/i2c/busses/i2c-xlp9xx.c | 20 +++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/i2c/busses/i2c-xlp9xx.c b/drivers/i2c/

Re: [PATCH] ACPI / CPPC: Fix negative array index read in cppc_set_perf

2017-12-15 Thread George Cherian
after the check on pcc_ss_id at line 1182: pcc_ss_data = pcc_data[pcc_ss_id]; Addresses-Coverity-ID: 1426090 ("Negative array index read") Fixes: 1ecbd7170d65 ("ACPI / CPPC: Fix KASAN global out of bounds warning") Reviewed-by: George Cherian <george.cher...@cavium.com>

Re: [PATCH] ptr_ring: add barriers

2017-12-11 Thread George Cherian
assumption being that producers do not need to read the value so we do not need to order these reads. Reported-by: George Cherian <george.cher...@cavium.com> Suggested-by: Jason Wang <jasow...@redhat.com> Signed-off-by: Michael S. Tsirkin <m...@redhat.com> I'm asked for asking fo

[PATCH] ptr_ring: Add barriers to fix NULL-pointer exception

2017-12-06 Thread George Cherian
+0x24/0x28 [35322.773042] Code: d503201f f9400e93 b940e280 91051274 (f9403261) Reported-by: Joseph DeVincentis <joseph.devincen...@cavium.com> Signed-off-by: George Cherian <george.cher...@cavium.com> --- include/linux/ptr_ring.h | 13 + 1 file changed, 13 insertions(+)

Re: [PATCH] ptr_ring: add barriers

2017-12-06 Thread George Cherian
eed to order these reads. It is not the case that producer is reading the value, but the consumer reading stale value. So we need to have a strict rmb in place . Reported-by: George Cherian <george.cher...@cavium.com> Suggested-by: Jason Wang <jasow...@redhat.com> Signed-off-b

[PATCH] skb_array: fix NULL-pointer exception

2017-12-04 Thread George Cherian
+0x24/0x28 [35322.773042] Code: d503201f f9400e93 b940e280 91051274 (f9403261) Reported-by: Joseph DeVincentis <joseph.devincen...@cavium.com> Signed-off-by: George Cherian <george.cher...@cavium.com> Cc: sta...@vger.kernel.org --- include/linux/skb_array.h | 9 + 1 fil

[PATCH] ACPI / CPPC: FIX KASAN global out of bounds warning

2017-12-04 Thread George Cherian
00 [ 15.116983] == Reported-by: Changbin Du <changbin...@intel.com> Signed-off-by: George Cherian <george.cher...@cavium.com> --- drivers/acpi/cppc_acpi.c | 23 +++ 1 file changed, 15 insertions(

Re: [PATCH v4 2/2] ACPI / CPPC: Make cppc acpi driver aware of pcc subspace ids

2017-10-11 Thread George Cherian
Thanks Prakash for the clarifications. I have updated the patch set incorporating your comments and posted v5. Regards -George On 10/07/2017 02:40 AM, Prakash, Prashanth wrote: On 10/3/2017 5:01 AM, George Cherian wrote: Hi Prakash, On 09/29/2017 04:49 AM, Prakash, Prashanth wrote: Hi

[PATCH v5 1/2] mailbox: PCC: Move the MAX_PCC_SUBSPACES definition to header file

2017-10-11 Thread George Cherian
Move the MAX_PCC_SUBSPACES definition to acpi/pcc.h file. In preparation to add subspace id support for cppc_acpi driver. Signed-off-by: George Cherian <george.cher...@cavium.com> --- drivers/mailbox/pcc.c | 1 - include/acpi/pcc.h| 1 + 2 files changed, 1 insertion(+), 1 deletion(-)

[PATCH v5 2/2] ACPI / CPPC: Make cppc acpi driver aware of pcc subspace ids

2017-10-11 Thread George Cherian
subspace ids. Add support of multiple PCC subspace id instead of using a single global pcc_data structure. While at that fix the time_delta check in send_pcc_cmd() so that last_mpar_reset and mpar_count is initialized properly. Signed-off-by: George Cherian <george.cher...@cavium.com> --- d

[PATCH v5 0/2] Make cppc acpi driver aware of pcc subspace ids

2017-10-11 Thread George Cherian
the cppc_pcc_data per unique subspace idx. - Added cleanup in acpi_cppc_processor_exit. Free the mbox channel and free the cppc_pcc_data in case refcount is zero. George Cherian (2): mailbox: PCC: Move the MAX_PCC_SUBSPACES definition to header file ACPI / CPPC: Make cppc acpi driver aware of pcc

Re: [PATCH v4 2/2] ACPI / CPPC: Make cppc acpi driver aware of pcc subspace ids

2017-10-03 Thread George Cherian
Hi Prakash, On 09/29/2017 04:49 AM, Prakash, Prashanth wrote: Hi George, On 9/19/2017 11:24 PM, George Cherian wrote: Based on ACPI 6.2 Section 8.4.7.1.9 If the PCC register space is used, all PCC registers, for all processors in the same performance domain (as defined by _PSD), must

[PATCH v4 2/2] ACPI / CPPC: Make cppc acpi driver aware of pcc subspace ids

2017-09-19 Thread George Cherian
subspace ids. Add support of multiple PCC subspace id instead of using a single global pcc_data structure. While at that fix the time_delta check in send_pcc_cmd() so that last_mpar_reset and mpar_count is initialized properly. Signed-off-by: George Cherian <george.cher...@cavium.com> --- d

[PATCH v4 1/2] mailbox: PCC: Move the MAX_PCC_SUBSPACES definition to header file

2017-09-19 Thread George Cherian
Move the MAX_PCC_SUBSPACES definition to acpi/pcc.h file. In preparation to add subspace id support for cppc_acpi driver. Signed-off-by: George Cherian <george.cher...@cavium.com> --- drivers/mailbox/pcc.c | 1 - include/acpi/pcc.h| 1 + 2 files changed, 1 insertion(+), 1 deletion(-)

[PATCH v4 0/2] Make cppc acpi driver aware of pcc subspace ids

2017-09-19 Thread George Cherian
. - Added cleanup in acpi_cppc_processor_exit. Free the mbox channel and free the cppc_pcc_data in case refcount is zero. George Cherian (2): mailbox: PCC: Move the MAX_PCC_SUBSPACES definition to header file ACPI / CPPC: Make cppc acpi driver aware of pcc subspace ids drivers/acpi

[PATCH v3 2/2] ACPI / CPPC: Make cppc acpi driver aware of pcc subspace ids

2017-09-04 Thread George Cherian
subspace ids. Add support of multiple PCC subspace id instead of using a single global pcc_data structure. While at that fix the time_delta check in send_pcc_cmd() so that last_mpar_reset and mpar_count is initialized properly. Signed-off-by: George Cherian <george.cher...@cavium.com> --- d

[PATCH v3 0/2] Make cppc acpi driver aware of pcc subspace ids

2017-09-04 Thread George Cherian
channel and free the cppc_pcc_data in case refcount is zero. George Cherian (2): mailbox: PCC: Move the MAX_PCC_SUBSPACES definition to header file ACPI / CPPC: Make cppc acpi driver aware of pcc subspace ids drivers/acpi/cppc_acpi.c | 241

[PATCH v3 1/2] mailbox: PCC: Move the MAX_PCC_SUBSPACES definition to header file

2017-09-04 Thread George Cherian
Move the MAX_PCC_SUBSPACES definition to acpi/pcc.h file. In preparation to add subspace id support for cppc_acpi driver. Signed-off-by: George Cherian <george.cher...@cavium.com> --- drivers/mailbox/pcc.c | 1 - include/acpi/pcc.h| 1 + 2 files changed, 1 insertion(+), 1 deletion(-)

[PATCHv2 2/2] ACPI / CPPC: Make cppc acpi driver aware of pcc subspace ids

2017-07-21 Thread George Cherian
subspace ids. Add support of multiple PCC subspace id instead of using a single global pcc_data structure. While at that fix the time_delta check in send_pcc_cmd() so that last_mpar_reset and mpar_count is initialized properly. Signed-off-by: George Cherian <george.cher...@cavium.com> --- d

[PATCHv2 0/2] Make cppc acpi driver aware of pcc subspace ids

2017-07-21 Thread George Cherian
is zero. George Cherian (2): mailbox: PCC: Move the MAX_PCC_SUBSPACES definition to header file ACPI / CPPC: Make cppc acpi driver aware of pcc subspace ids drivers/acpi/cppc_acpi.c | 228 ++- drivers/mailbox/pcc.c| 1 - include/acpi/pcc.h

[PATCHv2 1/2] mailbox: PCC: Move the MAX_PCC_SUBSPACES definition to header file

2017-07-21 Thread George Cherian
Move the MAX_PCC_SUBSPACES definition to acpi/pcc.h file. In preparation to add subspace id support for cppc_acpi driver. Signed-off-by: George Cherian <george.cher...@cavium.com> --- drivers/mailbox/pcc.c | 1 - include/acpi/pcc.h| 1 + 2 files changed, 1 insertion(+), 1 deletion(-)

Re: [PATCH 2/2] ACPI / CPPC: Make cppc acpi driver aware of pcc subspace ids

2017-07-14 Thread George Cherian
Hi Prashanth, Thanks for the review. On 07/14/2017 03:14 AM, Prakash, Prashanth wrote: Hi George, On 6/13/2017 8:17 AM, George Cherian wrote: Based on ACPI 6.2 Section 8.4.7.1.9 If the PCC register space is used, all PCC registers, for all processors in the same performance domain

[PATCH 2/2] ACPI / CPPC: Make cppc acpi driver aware of pcc subspace ids

2017-06-13 Thread George Cherian
subspace ids. Add support of multiple PCC subspace id instead of using a single global pcc_data structure. While at that fix the time_delta check in send_pcc_cmd() so that last_mpar_reset and mpar_count is initialized properly. Signed-off-by: George Cherian <george.cher...@cavium.com> --- d

Re: [PATCH-internal 1/2] mailbox: PCC: Move the MAX_PCC_SUBSPACES definition to header file

2017-06-13 Thread George Cherian
Please ignore this patch the subject had -internal tag Sorry!! Resent the proper one. On 06/13/2017 07:45 PM, George Cherian wrote: Move the MAX_PCC_SUBSPACES definition to acpi/pcc.h file. In preparation to add subspace id support for cppc_acpi driver. Signed-off-by: George Cherian

[PATCH 0/2] Make cppc acpi driver aware of pcc subspace ids

2017-06-13 Thread George Cherian
subspace ids. George Cherian (2): mailbox: PCC: Move the MAX_PCC_SUBSPACES definition to header file ACPI / CPPC: Make cppc acpi driver aware of pcc subspace ids drivers/acpi/cppc_acpi.c | 179 +-- drivers/mailbox/pcc.c| 1 - include/acpi

[PATCH 1/2] mailbox: PCC: Move the MAX_PCC_SUBSPACES definition to header file

2017-06-13 Thread George Cherian
Move the MAX_PCC_SUBSPACES definition to acpi/pcc.h file. In preparation to add subspace id support for cppc_acpi driver. Signed-off-by: George Cherian <george.cher...@cavium.com> --- drivers/mailbox/pcc.c | 1 - include/acpi/pcc.h| 1 + 2 files changed, 1 insertion(+), 1 deletion(-)

Re: [PATCH-internal 0/2] Make cppc acpi driver aware of pcc subspace ids

2017-06-13 Thread George Cherian
Sorry Ignore this series!!! On 06/13/2017 07:45 PM, George Cherian wrote: The current cppc acpi driver works with only one pcc subspace id. It maintains and registers only one pcc channel even if the acpi table has different pcc subspace ids. As per ACPI 6.2 spec all PCC registers, for all

[PATCH-internal 1/2] mailbox: PCC: Move the MAX_PCC_SUBSPACES definition to header file

2017-06-13 Thread George Cherian
Move the MAX_PCC_SUBSPACES definition to acpi/pcc.h file. In preparation to add subspace id support for cppc_acpi driver. Signed-off-by: George Cherian <george.cher...@cavium.com> --- drivers/mailbox/pcc.c | 1 - include/acpi/pcc.h| 1 + 2 files changed, 1 insertion(+), 1 deletion(-)

[PATCH-internal 0/2] Make cppc acpi driver aware of pcc subspace ids

2017-06-13 Thread George Cherian
subspace ids. George Cherian (2): mailbox: PCC: Move the MAX_PCC_SUBSPACES definition to header file ACPI / CPPC: Make cppc acpi driver aware of pcc subspace ids drivers/acpi/cppc_acpi.c | 179 +-- drivers/mailbox/pcc.c| 1 - include/acpi

Re: [PATCH v2 0/3] Add more algorithms and some misc cleanups

2017-06-10 Thread George Cherian
Hi Herbert, Ping on this series Regards, -George Cherian On Thu, May 4, 2017 at 5:04 PM, George Cherian <george.cher...@cavium.com> wrote: > This series adds more algorithm support for CPT. > Add support for > -ecb(aes) > -cfb(aes) > -ecb(des3_e

[PATCH] i2c: xlp9xx: Enable HWMON class probing for xlp9xx

2017-05-25 Thread George Cherian
Set I2C_CLASS_HWMON for xlp9xx to enable automatic probing of BMC devices by the ipmi-ssif driver. Signed-off-by: George Cherian <george.cher...@cavium.com> --- drivers/i2c/busses/i2c-xlp9xx.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/i2c/busses/i2c-xlp9xx.c b/drive

[PATCH v2 3/3] crypto: cavium: Add more algorithms

2017-05-04 Thread George Cherian
Add more algorithm support for the driver. Add support for ecb(aes), cfb(aes) and ecb(des3_ede). Signed-off-by: George Cherian <george.cher...@cavium.com> --- drivers/crypto/cavium/cpt/cptvf_algs.c | 81 ++ 1 file changed, 81 insertions(+) diff --git a/d

[PATCH v2 2/3] crypto: cavium: Remove the individual encrypt/decrypt function for each algorithm

2017-05-04 Thread George Cherian
Remove the individual encrypt/decrypt function for easch algorithm. This is in prepration of adding more crypto algorithms supported by hardware. While at that simplify create_ctx_hdr/create_input_list function interfaces. Signed-off-by: George Cherian <george.cher...@cavium.com> --- d

[PATCH v2 1/3] crypto: cavium: Downgrade the annoying misc interrupt print from dev_err to dev_dbg

2017-05-04 Thread George Cherian
Mailbox interrupt is common and it is not an error interrupt. So downgrade the print from dev_err to dev_dbg. Signed-off-by: George Cherian <george.cher...@cavium.com> --- drivers/crypto/cavium/cpt/cptvf_main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/

[PATCH v2 0/3] Add more algorithms and some misc cleanups

2017-05-04 Thread George Cherian
This series adds more algorithem support for CPT. Add support for -ecb(aes) -cfb(aes) -ecb(des3_ede) Some cleanups too. George Cherian (3): crypto: cavium: Downgrade the annoying misc interrupt print from dev_err to dev_dbg crypto: cavium: Remove the individual

[PATCH 2/3] crypto: cavium: Remove the individual encrypt/decrypt function for each algorithm

2017-04-20 Thread George Cherian
Remove the individual encrypt/decrypt function for easch algorithm. This is in prepration of adding more crypto algorithms supported by hardware. While at that simplify create_ctx_hdr/create_input_list function interfaces. Signed-off-by: George Cherian <george.cher...@cavium.com> --- d

[PATCH 1/3] crypto: cavium: Downgrade the annoying misc interrupt print from dev_err to dev_dbg

2017-04-20 Thread George Cherian
Mailbox interrupt is common and it is not an error interrupt. So downgrade the print from dev_err to dev_dbg. Signed-off-by: George Cherian <george.cher...@cavium.com> --- drivers/crypto/cavium/cpt/cptvf_main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/

[PATCH 0/3] Add more algorithms and some misc cleanups

2017-04-20 Thread George Cherian
This series adds more algorithem support for CPT. Add support for -ecb(aes) -cfb(aes) -ecb(des3_ede) Some cleanups too. George Cherian (3): crypto: cavium: Downgrade the annoying misc interrupt print from dev_err to dev_dbg crypto: cavium: Remove the individual

[PATCH 3/3] crypto: cavium: Add more algorithms

2017-04-20 Thread George Cherian
Add more algorithm support for the driver. Add support for ecb(aes), cfb(aes) and ecb(des3_ede). Signed-off-by: George Cherian <george.cher...@cavium.com> --- drivers/crypto/cavium/cpt/cptvf_algs.c | 63 ++ 1 file changed, 63 insertions(+) diff --git a/d

[PATCH] net: thunderx: Fix set_max_bgx_per_node for 81xx rgx

2017-04-13 Thread George Cherian
num_vfs is always calculated as zero. Signed-off-by: George Cherian <george.cher...@cavium.com> --- drivers/net/ethernet/cavium/thunder/thunder_bgx.c | 1 + drivers/net/ethernet/cavium/thunder/thunder_bgx.h | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/net/ethernet/cavium/t

Re: [PATCH 0/2] Make cppc acpi driver aware of pcc subspace ids

2017-04-04 Thread George Cherian
Hi Hoan/Prashanth, On 04/03/2017 11:20 PM, Hoan Tran wrote: Hi George, On Mon, Apr 3, 2017 at 9:44 AM, Prakash, Prashanth <pprak...@codeaurora.org> wrote: Hi George, On 3/31/2017 12:24 AM, George Cherian wrote: The current cppc acpi driver works with only one pcc subspace id. It mai

Re: [PATCH 2/2] ACPI / CPPC: Make cppc acpi driver aware of pcc subspace ids

2017-04-04 Thread George Cherian
Hi Alexey, On 04/03/2017 11:07 PM, Alexey Klimov wrote: (adding Prashanth to c/c) Hi George, On Fri, Mar 31, 2017 at 06:24:02AM +, George Cherian wrote: Based on Section 14.1 of ACPI specification, it is possible to have a maximum of 256 PCC subspace ids. Add support of multiple PCC

[PATCH 1/2] mailbox: PCC: Move the MAX_PCC_SUBSPACES definition to header file

2017-03-31 Thread George Cherian
Move the MAX_PCC_SUBSPACES definition to acpi/pcc.h file. In preparation to add subspace id support for cppc_acpi driver. Signed-off-by: George Cherian <george.cher...@cavium.com> --- drivers/mailbox/pcc.c | 1 - include/acpi/pcc.h| 1 + 2 files changed, 1 insertion(+), 1 deletion(-)

[PATCH 0/2] Make cppc acpi driver aware of pcc subspace ids

2017-03-31 Thread George Cherian
: In preparation to share the MAX_PCC_SUBSPACE definition with cppc acpi driver Patch 2 : Make the cppc acpi driver aware of multiple pcc subspace ids. George Cherian (2): mailbox: PCC: Move the MAX_PCC_SUBSPACES definition to header file ACPI / CPPC: Make cppc acpi driver aware of pcc

[PATCH 2/2] ACPI / CPPC: Make cppc acpi driver aware of pcc subspace ids

2017-03-31 Thread George Cherian
is initialized properly. Also maintain a global total_mpar_count which is a sum of per subspace id mpar value. Signed-off-by: George Cherian <george.cher...@cavium.com> --- drivers/acpi/cppc_acpi.c | 189 ++- 1 file changed, 105 insertions(+), 84 del

[PATCH] crypto: cavium/cpt: Fix couple of static checker errors

2017-02-15 Thread George Cherian
Fix the following smatch errors cptvf_reqmanager.c:333 do_post_process() warn: variable dereferenced before check 'cptvf' cptvf_main.c:825 cptvf_remove() error: we previously assumed 'cptvf' could be null Reported-by: Dan Carpenter <dan.carpen...@oracle.com> Signed-off-by: George C

Re: crypto/cavium MSI-X fixups

2017-02-15 Thread George Cherian
. Can you please test it and make sure it goes in before the end of the merge window so that no more users of the old API hit mainline? Yes the changes works well. Acked-by: George Cherian <george.cher...@cavium.com> for the series.

[PATCH] drivers: crypto: cpt: cpt_bind_vq_to_grp could return an error code

2017-02-14 Thread George Cherian
ed-off-by: George Cherian <george.cher...@cavium.com> --- drivers/crypto/cavium/cpt/cptpf_mbox.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/crypto/cavium/cpt/cptpf_mbox.c b/drivers/crypto/cavium/cpt/cptpf_mbox.c index 5818b41..20f2c6e 100644 --- a/drivers/c

[PATCH v6 3/3] drivers: crypto: Enable CPT options crypto for build

2017-02-07 Thread George Cherian
Add the CPT options in crypto Kconfig and update the crypto Makefile Update the MAINTAINERS file too. Signed-off-by: George Cherian <george.cher...@cavium.com> Reviewed-by: David Daney <david.da...@cavium.com> --- MAINTAINERS | 7 +++ drivers/crypto/Kconfig |

[PATCH v6 2/3] drivers: crypto: Add the Virtual Function driver for CPT

2017-02-07 Thread George Cherian
Enable the CPT VF driver. CPT is the cryptographic Acceleration Unit in Octeon-tx series of processors. Signed-off-by: George Cherian <george.cher...@cavium.com> Reviewed-by: David Daney <david.da...@cavium.com> --- drivers/crypto/cavium/cpt/Makefile | 3 +- drivers/crypt

[PATCH v6 1/3] drivers: crypto: Add Support for Octeon-tx CPT Engine

2017-02-07 Thread George Cherian
Enable the Physical Function driver for the Cavium Crypto Engine (CPT) found in Octeon-tx series of SoC's. CPT is the Cryptographic Accelaration Unit. CPT includes microcoded GigaCypher symmetric engines (SEs) and asymmetric engines (AEs). Signed-off-by: George Cherian <george.cher...@cavium.

[PATCH v6 0/3] Add Support for Cavium Cryptographic Acceleration Unit

2017-02-07 Thread George Cherian
cro definitions -- Remove the redundant ROUNDUP* macros and use kernel function -- Select proper config option in Kconfig file. -- Removed some of the unwanted header file inclusions -- Miscellaneous Cleanup George Cherian (3): drivers: cryp

Re: [PATCH v5 0/3] Add Support for Cavium Cryptographic Acceleration Unit

2017-02-03 Thread George Cherian
On Friday 03 February 2017 11:02 PM, Sasha Levin wrote: On Mon, Jan 30, 2017 at 7:30 AM, George Cherian <george.cher...@cavium.com> wrote: This series adds the support for Cavium Cryptographic Accelerarion Unit (CPT) CPT is available in Cavium's Octeon-Tx SoC series. The series was

Re: [PATCH v5 2/3] drivers: crypto: Add the Virtual Function driver for CPT

2017-02-03 Thread George Cherian
Hi Sasha, Thanks for the reveiw. On Friday 03 February 2017 12:24 AM, Sasha Levin wrote: On Mon, Jan 30, 2017 at 7:30 AM, George Cherian <george.cher...@cavium.com> wrote: diff --git a/drivers/crypto/cavium/cpt/cptvf_main.c b/drivers/crypto/cavium/cpt/cptvf_main.c new file mode

[PATCH v5 3/3] drivers: crypto: Enable CPT options crypto for build

2017-01-30 Thread George Cherian
Add the CPT options in crypto Kconfig and update the crypto Makefile Signed-off-by: George Cherian <george.cher...@cavium.com> Reviewed-by: David Daney <david.da...@cavium.com> --- drivers/crypto/Kconfig | 1 + drivers/crypto/Makefile | 1 + 2 files changed, 2 insertions(+)

[PATCH v5 2/3] drivers: crypto: Add the Virtual Function driver for CPT

2017-01-30 Thread George Cherian
Enable the CPT VF driver. CPT is the cryptographic Acceleration Unit in Octeon-tx series of processors. Signed-off-by: George Cherian <george.cher...@cavium.com> Reviewed-by: David Daney <david.da...@cavium.com> --- drivers/crypto/cavium/cpt/Makefile | 3 +- drivers/crypt

[PATCH v5 1/3] drivers: crypto: Add Support for Octeon-tx CPT Engine

2017-01-30 Thread George Cherian
Enable the Physical Function driver for the Cavium Crypto Engine (CPT) found in Octeon-tx series of SoC's. CPT is the Cryptographic Accelaration Unit. CPT includes microcoded GigaCypher symmetric engines (SEs) and asymmetric engines (AEs). Signed-off-by: George Cherian <george.cher...@cavium.

[PATCH v5 0/3] Add Support for Cavium Cryptographic Acceleration Unit

2017-01-30 Thread George Cherian
definitions -- Remove the redundant ROUNDUP* macros and use kernel function -- Select proper config option in Kconfig file. -- Removed some of the unwanted header file inclusions -- Miscellaneous Cleanup George Cherian (3

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