>From: Brian Norris
>
>Hi White,
>
>On Thu, Jul 24, 2014 at 01:00:01AM +, bpqw wrote:
>> Do nand reset before write protect check
>> If we want to check the WP# low or high through STATUS READ and check bit 7,
>> we must reset the device, other operation (eg.erase/program a locked block)
>> ca
>From: Brian Norris
>>On Thu, Jul 17, 2014 at 12:54:17AM +, Bean Huo wrote:
>> > I have just fixed up your patch myself, to use max() and to improve some
>> > of the language. Let me know if the below works for you.
>>
>> hi,Brian
>> Thanks once again.I test and it works Ok.It can be accepted
>From: Quadros, Roger
>>On 07/11/2014 10:43 AM, Gupta, Pekon wrote:
>>> From: Quadros, Roger
[...]
>>> @@ -1176,6 +1172,7 @@ static int __maybe_unused
>>> omap_calculate_ecc_bch(struct mtd_info
>*mtd,
>>> {
>>> struct omap_
>From: Quadros, Roger
>>On 07/11/2014 10:27 AM, Gupta, Pekon wrote:
>>> From: Tony Lindgren [mailto:t...@atomide.com]
>>>> * Roger Quadros [140709 05:39]:
>>>> Hi,
>>>>
>>>> The following hardware modules/registers are meant fo
Roger,
>From: Quadros, Roger
>Don't access the ECC/BCH engine registers directly as they belong
>to the GPMC controller's register space. Use the relevant
>GPMC APIs instead.
>
>Signed-off-by: Roger Quadros
>---
> drivers/mtd/nand/omap2.c | 191 +++
> 1
Hi Roger,
>From: Quadros, Roger
>
>Even though the ECC/BCH engine is meant for exclusive use by
>the OMAP NAND controller, the ECC/BCH registers belong
>to the GPMC controller's register space
>
>Add omap_gpmc_ecc_configure_enable() and omap_gpmc_ecc_disable()
>to manage the ECC engine. OMAP NAND
>From: Quadros, Roger
>
>Instead of hardcoding use the pre-calculated chip->ecc.steps for
>configuring number of sectors to process with the BCH algorithm.
>
>This also avoids unnecessary access to the ECC_CONFIG register in
>omap_calculate_ecc_bch().
>
>Signed-off-by: Roger Quadros
>---
> drivers
Hi Roger,
>From: Tony Lindgren [mailto:t...@atomide.com]
>>* Roger Quadros [140709 05:39]:
>> Hi,
>>
>> The following hardware modules/registers are meant for NAND controller driver
>> usage:
>> - NAND I/O control (NAND address, data, command registers)
>> - Prefetch/Write-post engine
>> - ECC/BC
>From: Ezequiel García [mailto:ezequ...@vanguardiasur.com.ar]
>>On 26 Jun 12:02 PM, Guido Martínez wrote:
>> Currently, child nodes of the gpmc node are iterated and probed
>> regardless of their 'status' property. This means adding 'status =
>> "disabled";' has no effect.
>>
>> This patch changes
>From: Tony Lindgren [mailto:t...@atomide.com]
>>* Roger Quadros [140613 00:40]:
>>> On 06/13/2014 10:18 AM, Tony Lindgren wrote:
>> >> * Roger Quadros [140611 01:58]:
>> >> Since the Interrupt Events are used only by the NAND driver,
>> >> there is no point in managing the Interrupt registers
>
>From: Lee Jones
>
>First introduction of the driver. Includes the basic device struct
>(some functionality isn't utilised as of yet) and supplies some of the
>important resources required for basic running of the Controller.
>
>Signed-off-by: Lee Jones
>---
>--- /dev/null
>+++ b/drivers/mtd/nand/
>From: linux-mtd [mailto:linux-mtd-boun...@lists.infradead.org] On Behalf Of
>Lee Jones
>
>This is where we describe the different new and generic options used by
>the ST BCH driver.
>
>Cc: devicet...@vger.kernel.org
>Signed-off-by: Lee Jones
>---
> Documentation/devicetree/bindings/mtd/stm-nand.
>From: Lee Jones [mailto:lee.jo...@linaro.org]
>
>> >> >+of_property_read_u32(np, "st,bch-bitflip-threshold",
>> >> >+ &pdata->bch_bitflip_threshold);
>> >> >+
>> >> mtd->bitflip_threshold is by default set to ecc.strength (unless a driver
>> >> initializes it).
Hi Nikita,
>From: Nikita Yushchenko
>
>Per MPC8572E manual, sec 14.4.3.1.3: "Transfers shorter than a full page,
>however, require software to prepare the appropriate ECC in the spare
>region"
>
>Need to set NAND_NO_SUBPAGE_WRITE flag. If this is not done, then
>generic nand_write_subpage_hwecc()
Hi Lee,
>From: Lee Jones [mailto:lee.jo...@linaro.org]
>> >From: Lee Jones [mailto:lee.jo...@linaro.org]
[...]
>> >+ of_property_read_u32(np, "st,bch-bitflip-threshold",
>> >+&pdata->bch_bitflip_threshold);
>> >+
>> mtd->bitflip_threshold is by default set to ecc.streng
>From: Lee Jones [mailto:lee.jo...@linaro.org]
>>On Wed, 26 Mar 2014, Gupta, Pekon wrote:
[...]
>> >+ /* Reset and disable boot-mode controller */
>> >+ writel(BOOT_CFG_RESET, nandi->base + NANDBCH_BOOTBANK_CFG);
>> >+ udelay(1);
>> >+ write
>From: Jingoo Han [mailto:jg1@samsung.com]
>>On Tuesday, April 15, 2014 7:32 AM, Christian Engelmayer wrote:
>>
>> Commit 2c9f2365 (mtd: nand: omap: ecc.calculate: merge
>> omap3_calculate_ecc_bch4
>> in omap_calculate_ecc_bch) introduced minor compile warning
>> "‘erased_sector_bitflips’ defi
Hi Lee,
>From: Lee Jones [mailto:lee.jo...@linaro.org]
>
>Helper function for bch_mtd_read() and bch_mtd_write() to handle
>multi-page or non-aligned reads and writes respectively.
>
>Signed-off-by: Lee Jones
>---
I think below code is duplicate of nand_do_read_ops() and nand_do_write_ops()
in n
Hi Lee,
>From: Lee Jones [mailto:lee.jo...@linaro.org]
missing commit log :-)
Though $subject is self-explanatory, but you can add more description about
assumption and hardware caveats about the controller, and its use.
>
>Signed-off-by: Lee Jones
>---
> drivers/mtd/nand/stm_nand_bch.c | 56 +++
Hi Lee,
>From: Lee Jones [mailto:lee.jo...@linaro.org]
>
>Use DMA to read and/or write a single page of data.
>
>Signed-off-by: Lee Jones
>---
> drivers/mtd/nand/stm_nand_bch.c | 119
> 1 file changed, 119 insertions(+)
>
>diff --git a/drivers/mtd/nand/stm_
Hi Lee,
>From: Lee Jones [mailto:lee.jo...@linaro.org]
>
>Fetch platform specific data from Device Tree. Any functions which
>are useful to other STM NAND Controllers have been separated into a
>separate file so they can be easily referenced by them as they
>appear.
>
>Signed-off-by: Lee Jones
>-
>From: Lee Jones [mailto:lee.jo...@linaro.org]
>
>Add support for clocks when, and only when, they are supplied. It is
>not yet compulsory to provide the BCH and EMI clocks, as Common Clk isn't
>supported Mainline yet. Until an implementation lands upstream all clocks
>located on STM boards default
Hi Lee,
>From: Lee Jones [mailto:lee.jo...@linaro.org]
>Obtain IRQ number and request IRQ resource via the usual methods. We're
>also registering an IRQ handler to inform us of any completed tasks.
>Notice that we're starting to make use of the device struct that we
>defined before. In keeping wit
Hello Lee,
[...]
>> I can help reviewing those patches, if you can please share your
>> controller specs, and also share if there are any already know
>> hardware limitations.
>
>Thanks for your kind offer. I will send it right away.
>
Is the spec for this controller available in public domain som
Hi,
>From: Lee Jones
>
>Hi Brian,
>
>Firstly I'd like to thank you for supporting the inclusion of ST's SPI
>NOR (FSM) driver. As promised I will convert it over to the new
>framework once it has been applied by your good self.
>
>In the meantime however, I have a NAND driver which I need to
>subm
Hi Boris,
>From: Boris BREZILLON
>
>This patch aims to add per partition ECC config for NAND devices.
>It defines a new field in the mtd struct to store the mtd ECC config and
>thus each mtd partition device can store its config instead of using the
>default NAND chip config.
>
>This feature is ne
Dear Rob, and other DT maintainers,
(apologies, fixed typos in earlier mail)
>>From: Rob Herring
>[...]
>>> +- onfi,nand-timing-mode : mandatory if the chip does not support the ONFI
>>> + standard.
>>
>>Add to generic nand binding.
>>
>>> +- allwinner,rb : shall contain the native Ready/Busy ids
Dear Rob, and other DT maintainers,
>From: Rob Herring
[...]
>> +- onfi,nand-timing-mode : mandatory if the chip does not support the ONFI
>> + standard.
>
>Add to generic nand binding.
>
>> +- allwinner,rb : shall contain the native Ready/Busy ids.
>> + or
>> +- rb-gpios : shall contain the gpio
Hi Shawn,
>From: Shawn Guo [mailto:shawn@linaro.org]
>>On Tue, Dec 17, 2013 at 05:00:53AM +0000, Gupta, Pekon wrote:
>> >From: Huang Shijie [mailto:b32...@freescale.com]
>>> >On Tue, Dec 17, 2013 at 04:08:33AM +, Gupta, Pekon wrote:
[...]
>> >>
> From: Brian Norris [mailto:computersforpe...@gmail.com]
> > On Thu, Oct 31, 2013 at 7:18 PM, Jingoo Han
> >> From: Wei Yongjun
> >>
> >> Fix to return a negative error code from the error handling
> >> case instead of 0, as done elsewhere in this function.
> >
> > Commit message is right? :-(
>
Hi Mark,
>
> Pekon, could you please re-send this version of the patches?
>
As already there are feedbacks on the patches, so re-sending the
Patch series might clutter someone else's mailbox.
Will it be possible for you to fetch the patches from MTD archives?
else I would send you the patches s
>
> Anyway, at this point I think your patch series should be nearly
> complete. I made a few comments on your patches, and I'd imagine you
> only should need one more revision (v7) before I can accept it to the
> l2-mtd.git tree.
>
Yes surely I will send next version (v7), but it might take few
Hi Brian,
>
> Hi Pekon,
>
> On Wed, Sep 25, 2013 at 08:46:19AM -0500, Felipe Balbi wrote:
> > + akpm
> >
> > On Tue, Sep 24, 2013 at 01:04:05PM -0500, Gupta, Pekon wrote:
[snip]
> > >
> > > Dear Olof and other DT Maintainers,
> > >
>
Hi Olof,
>
> fb1585bc13b (mtd: nand: omap2: clean-up BCHx_HW and BCHx_SW ECC
> configurations in device_probe) introduced a warning when the new option
> is disabled, i.e. with omap2plus_defconfig:
>
> drivers/mtd/nand/omap2.c:1075:13: warning: 'omap3_enable_hwecc_bch'
> defined but not used [-W
>
> On Mon, Jul 1, 2013 at 10:44 PM, Gupta, Pekon wrote:
> >>
> >> Hi all,
> >>
> >> Today's linux-next merge of the arm-soc tree got a conflict in
> >> Documentation/devicetree/bindings/mtd/gpmc-nand.txt between
> commits
> >&
>
> Hi all,
>
> Today's linux-next merge of the arm-soc tree got a conflict in
> Documentation/devicetree/bindings/mtd/gpmc-nand.txt between commits
> 6c88058ef927 ("ARM: OMAP2+: cleaned-up DT support of various ECC
> schemes") and 212012138deb ("mtd: nand: omap2: updated support for
> BCH4
> ECC
> Hi all,
>
> Today's linux-next merge of the arm-soc tree got a conflict in
> arch/arm/boot/dts/am33xx.dtsi between commit a82279dd6d3e ("arm:
> am33xx:
> add TSC/ADC mfd device support") from the mfd tree and commit
> 15e8246bd61b ("ARM: dts: AM33XX: Add ELM node") from the arm-soc tree.
>
> I
> > Sorry, I missed that series.
> >
> > I'm applying it right now.
> >
> No issues.. Please pick newer v4 versions of this series.
> Following are rebased, updated and tested on linux-3.10-rc3
>
> [PATCH v4,0/3] http://www.spinics.net/lists/linux-omap/msg91165.html
>
> [PATCH v4,1/3] http://www.
> Sorry, I missed that series.
>
> I'm applying it right now.
>
No issues.. Please pick newer v4 versions of this series.
Following are rebased, updated and tested on linux-3.10-rc3
[PATCH v4,0/3] http://www.spinics.net/lists/linux-omap/msg91165.html
[PATCH v4,1/3] http://www.spinics.net/list
> > "Lars" == Lars Poeschel writes:
>
> Lars> From: Lars Poeschel
> Lars> The gpmc driver is actually looking for "gpmc,num-cs" and
> Lars> "gpmc,num-waitpins" properties in DT. The binding doc also states
> Lars> this.
> Lars> Correct the properties in the dts to provide the right valu
> > > >
> > > > am33xx_pinmux: pinmux@44e10800 {
> > > > pinctrl-names = "default";
> > > > - pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0>;
> > > > + pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0
> > > > + &nandflash_pi
> > >
> > > am33xx_pinmux: pinmux@44e10800 {
> > > pinctrl-names = "default";
> > > - pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0>;
> > > + pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0
> > > + &nandflash_pins_s0>;
> >
> > Why add this to the board le
From: Philip Avinash
NAND flash connected in am335x-evm on GPMC controller. This patch adds
device tree node in am3355-evm with GPMC contoller timing for NAND flash
interface, NAND partition table, ECC scheme, elm handle id.
Signed-off-by: Philip Avinash
Signed-off-by: Gupta, Pekon
From: avinash philip
NAND flash connected in am335x-evm on GPMC controller. This patch adds
device tree node in am3355-evm with GPMC contoller timing for NAND flash
interface, NAND partition table, ECC scheme, elm handle id.
Signed-off-by: Philip Avinash
Signed-off-by: Gupta, Pekon
---
arch
> Since the ONFI 2.1, the onfi spec adds the Extended Parameter Page
> to store the ECC info.
>
> The onfi spec tells us that if the nand chip's recommended ECC codeword
> size is not 512 bytes, then the @ecc_bits is 0xff. The host _SHOULD_
> then
> read the Extended ECC information that is part o
> Since the ONFI 2.1, the onfi spec adds the Extended Parameter Page
> to store the ECC info.
>
> The onfi spec tells us that if the nand chip's recommended ECC codeword
> size is not 512 bytes, then the @ecc_bits is 0xff. The host _SHOULD_
> then
> read the Extended ECC information that is part o
> 于 2013年05月02日 13:42, Gupta, Pekon 写道:
> >>>> -*busw = 0;
> >>>> -if (le16_to_cpu(p->features)& 1)
> >>>> -*busw = NAND_BUSWIDTH_16;
> >>>> +
> >> - *busw = 0;
> >> - if (le16_to_cpu(p->features)& 1)
> >> - *busw = NAND_BUSWIDTH_16;
> >> +
> >> + *busw = (onfi_feature(chip)& ONFI_FEATURE_16_BIT_BUS) ?
> >> + NAND_BUSWIDTH_16 : 0;
> > Is this really needed ? you have already checked the 'onfi_version'
> abov
> - *busw = 0;
> - if (le16_to_cpu(p->features) & 1)
> - *busw = NAND_BUSWIDTH_16;
> +
> + *busw = (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS) ?
> + NAND_BUSWIDTH_16 : 0;
Is this really needed ? you have already checked the 'onfi_version' above in
nan
From: avinash philip
NAND flash connected in am335x-evm on GPMC controller. This patch adds
device tree node in am3355-evm with GPMC contoller timing for NAND flash
interface, NAND partition table, ECC scheme, elm handle id.
Signed-off-by: Philip Avinash
Tested-by: Pekon Gupta
---
arch/arm/bo
From: avinash philip
From: "Philip, Avinash"
Add GPMC data node to AM33XX device tree file.
Signed-off-by: Philip Avinash
Acked-by: Peter Korsgaard
Tested-by: Pekon Gupta
---
Changes since v2:
- Change number of chip select to 7
arch/arm/boot/dts/am33xx.dtsi | 12
From: avinash philip
From: "Philip, Avinash"
Add ELM data node to AM33XX device tree file.
Signed-off-by: Philip Avinash
Acked-by: Peter Korsgaard
Tested-by: Pekon Gupta
---
Changes since v2:
- Replace literals to 52
- remove tab
arch/arm/boot/dts/am33xx.dtsi |8
> * Arnd Bergmann [130423 09:37]:
> > The omap2 nand device driver calls into the the elm code, which can
> > be a loadable module, and in that case it cannot be built-in itself.
> > I can see no reason why the omap2 driver cannot also be a module,
> > so let's make the option "tristate" in Kconfi
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