Hi Neil,
Thanks for the review, I will update the subject and commit message in the next
version.
On 2019/10/21 15:57, Neil Armstrong wrote:
> Hi,
>
> Thanks for the fix.
>
> First, you should add "mmc: meson-gx:" in the subject.
>
> On 21/10/2019 07:59, Jia
From: Nan Li
In MMC dma transfer, the region requested by dma_map_sg() may be released
by dma_unmap_sg() before the transfer is completed.
Put the unmap operation in front of mmc_request_done() to avoid this.
Signed-off-by: Nan Li
Signed-off-by: Jianxin Pan
---
drivers/mmc/host/meson-gx
The Amlogic Meson A1/C1 Secure Monitor implements calls to control power
domain.
Signed-off-by: Jianxin Pan
---
drivers/firmware/meson/meson_sm.c | 2 ++
include/linux/firmware/meson/meson_sm.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/drivers/firmware/meson/meson_sm.c
b
Add support for the Amlogic Secure Power controller. In A1/C1 series, power
control registers are in secure domain, and should be accessed by smc.
Signed-off-by: Jianxin Pan
---
drivers/soc/amlogic/Kconfig | 13 ++
drivers/soc/amlogic/Makefile| 1 +
drivers/soc
Add the bindings for the Amlogic Secure power domains, controlling the
secure power domains.
The bindings targets the Amlogic A1 and C1 compatible SoCs, in which the
power domain registers are in secure world.
Signed-off-by: Jianxin Pan
---
.../bindings/power/amlogic,meson-sec-pwrc.yaml
4116-1-git-send-email-jianxin@amlogic.com
[1]
https://lore.kernel.org/linux-amlogic/1570695678-42623-1-git-send-email-jianxin@amlogic.com
Jianxin Pan (4):
dt-bindings: power: add Amlogic secure power domains bindings
firmware: meson_sm: Add secure power domain support
soc: am
Enable power domain controller for Meson A1 SoC.
Signed-off-by: Jianxin Pan
---
arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
index 7210ad0..081bc31
Hi Rob,
On 2019/10/15 1:39, Rob Herring wrote:
> On Thu, Oct 10, 2019 at 04:21:15AM -0400, Jianxin Pan wrote:
>> Add the bindings for the Amlogic Secure power domains, controlling the
>> secure power domains.
>>
>> The bindings targets the Amlogic A1 and C1 compatible
Enable power domain controller for Meson A1 SoC.
Signed-off-by: Jianxin Pan
---
arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
index 7210ad0..5547913
The Amlogic Meson A1/C1 Secure Monitor implements calls to control power
domain.
Signed-off-by: Jianxin Pan
---
drivers/firmware/meson/meson_sm.c | 2 ++
include/linux/firmware/meson/meson_sm.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/drivers/firmware/meson/meson_sm.c
b
Add the bindings for the Amlogic Secure power domains, controlling the
secure power domains.
The bindings targets the Amlogic A1 and C1 compatible SoCs, in which the
power domain registers are in secure world.
Signed-off-by: Jianxin Pan
---
.../bindings/power/amlogic,meson-sec-pwrc.yaml
Add support for the Amlogic Secure Power controller. In A1/C1 series, power
control registers are in secure domain, and should be accessed by smc.
Signed-off-by: Jianxin Pan
---
drivers/soc/amlogic/Kconfig | 13 ++
drivers/soc/amlogic/Makefile| 1 +
drivers/soc
sm driver
- rename pwrc_secure_get_power as Kevin suggested
- add comments for always on domains
- replace arch_initcall_sync with builtin_platform_driver
- fix coding style
[0]
https://lore.kernel.org/linux-amlogic/1568895064-4116-1-git-send-email-jianxin@amlogic.com
Jianxin Pan (4):
dt-bindi
Enable power domain controller for Meson A1 SoC.
Signed-off-by: Jianxin Pan
---
arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
index 7210ad0..5547913
sm driver
- rename pwrc_secure_get_power as Kevin suggested
- add comments for always on domains
- replace arch_initcall_sync with builtin_platform_driver
- fix coding style
[0]
https://lore.kernel.org/linux-amlogic/1568895064-4116-1-git-send-email-jianxin@amlogic.com
Jianxin Pan (4):
dt-bindi
Add the bindings for the Amlogic Secure power domains, controlling the
secure power domains.
The bindings targets the Amlogic A1 and C1 compatible SoCs, in which the
power domain registers are in secure world.
Signed-off-by: Jianxin Pan
---
.../bindings/power/amlogic,meson-sec-pwrc.yaml
Add support for the Amlogic Secure Power controller. In A1/C1 series, power
control registers are in secure domain, and should be accessed by smc.
Signed-off-by: Jianxin Pan
---
drivers/soc/amlogic/Kconfig | 13 ++
drivers/soc/amlogic/Makefile| 1 +
drivers/soc
The Amlogic Meson A1/C1 Secure Monitor implements calls to control power
domain.
Signed-off-by: Jianxin Pan
---
drivers/firmware/meson/meson_sm.c | 2 ++
include/linux/firmware/meson/meson_sm.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/drivers/firmware/meson/meson_sm.c
b
Hi Rob，
Thanks for your review.
I'm sorry to reply so late, for I've been on vacation in the last week.
On 2019/10/2 6:09, Rob Herring wrote:
> On Thu, Sep 19, 2019 at 08:11:02AM -0400, Jianxin Pan wrote:
>> Add the bindings for the Amlogic Secure power domains, controlling the
>&g
Hi Kevin,
Thanks for your review. Please see my comments below.
On 2019/9/26 6:41, Kevin Hilman wrote:
> Hi Jianxin,
>
> Jianxin Pan writes:
>
>> Add support for the Amlogic Secure Power controller. In A1/C1 series, power
>> control registers are in secure domain
Hi Martin,
On 2019/9/20 4:03, Martin Blumenstingl wrote:
> Hi Jianxin,
>
> I added three comments below from a quick glance at this driver (I
> didn't have time for a complete review)
>
> On Thu, Sep 19, 2019 at 2:11 PM Jianxin Pan wrote:
> [...]
>> +
Hi Martin,
On 2019/9/20 4:06, Martin Blumenstingl wrote:
> Hi Jianxin,
>
> On Thu, Sep 19, 2019 at 2:11 PM Jianxin Pan wrote:
>>
>> Add the bindings for the Amlogic Secure power domains, controlling the
>> secure power domains.
>>
>> The bindings target
Enable power domain controller for Meson A1 SoC.
Signed-off-by: Jianxin Pan
Signed-off-by: Zhiqiang Liang
---
arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
b/arch/arm64/boot/dts/amlogic/meson-a1
Add the bindings for the Amlogic Secure power domains, controlling the
secure power domains.
The bindings targets the Amlogic A1 and C1 compatible SoCs, in which the
power domain registers are in secure world.
Signed-off-by: Jianxin Pan
Signed-off-by: Zhiqiang Liang
---
.../bindings/power
Add support for the Amlogic Secure Power controller. In A1/C1 series, power
control registers are in secure domain, and should be accessed by smc.
Signed-off-by: Jianxin Pan
Signed-off-by: Zhiqiang Liang
---
drivers/soc/amlogic/Kconfig | 13 +++
drivers/soc/amlogic/Makefile
t [0].
[0]
https://lore.kernel.org/linux-amlogic/1568276370-54181-1-git-send-email-jianxin@amlogic.com
Jianxin Pan (3):
dt-bindings: power: add Amlogic secure power domains bindings
soc: amlogic: Add support for Secure power domains controller
arm64: dts: meson: a1: add secure power domain
Hi Neil,
On 2019/9/11 23:54, Neil Armstrong wrote:
> On 11/09/2019 17:38, Jianxin Pan wrote:
>> Add basic support for the Amlogic A1 based Amlogic AD401 board:
>> which describe components as follows: Reserve Memory, CPU, GIC, IRQ,
>> Timer, UART. It's capable of booti
Add the compatible for the Amlogic A1 Based AD401 board.
Signed-off-by: Jianxin Pan
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/arm/amlogic.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml
b/Documentation
Add bindings for the new Amlogic A1 SoC family.
A1 is an application processor designed for smart audio and IoT applications,
with dual core Cortex-A35.
Signed-off-by: Jianxin Pan
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/arm/amlogic.yaml | 4
1 file changed, 4
-amlogic/1567667251-33466-1-git-send-email-jianxin@amlogic.com
[2]
https://lore.kernel.org/linux-amlogic/1568216290-84219-1-git-send-email-jianxin@amlogic.com
Jianxin Pan (4):
soc: amlogic: meson-gx-socinfo: Add A1 and A113L IDs
dt-bindings: arm: amlogic: add A1 bindings
dt-bindings: arm
Add the SoC IDs for the A113L Amlogic A1 SoC.
Signed-off-by: Jianxin Pan
Reviewed-by: Neil Armstrong
---
drivers/soc/amlogic/meson-gx-socinfo.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/soc/amlogic/meson-gx-socinfo.c
b/drivers/soc/amlogic/meson-gx-socinfo.c
index 6d0d04f
Add basic support for the Amlogic A1 based Amlogic AD401 board:
which describe components as follows: Reserve Memory, CPU, GIC, IRQ,
Timer, UART. It's capable of booting up into the serial console.
Signed-off-by: Jianxin Pan
Reviewed-by: Jerome Brunet
Reviewed-by: Neil Armstrong
---
arch
Add the compatible for the Amlogic A1 Based AD401 board.
Signed-off-by: Jianxin Pan
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/arm/amlogic.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml
b/Documentation
Add bindings for the new Amlogic A1 SoC family.
A1 is an application processor designed for smart audio and IoT applications,
with dual core Cortex-A35.
Signed-off-by: Jianxin Pan
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/arm/amlogic.yaml | 4
1 file changed, 4
@amlogic.com
Jianxin Pan (4):
soc: amlogic: meson-gx-socinfo: Add A1 and A113L IDs
dt-bindings: arm: amlogic: add A1 bindings
dt-bindings: arm: amlogic: add Amlogic AD401 bindings
arm64: dts: add support for A1 based Amlogic AD401
Documentation/devicetree/bindings/arm/amlogic.yaml
Add the SoC IDs for the A113L Amlogic A1 SoC.
Signed-off-by: Jianxin Pan
Reviewed-by: Neil Armstrong
---
drivers/soc/amlogic/meson-gx-socinfo.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/soc/amlogic/meson-gx-socinfo.c
b/drivers/soc/amlogic/meson-gx-socinfo.c
index 6d0d04f
Add basic support for the Amlogic A1 based Amlogic AD401 board:
which describe components as follows: Reserve Memory, CPU, GIC, IRQ,
Timer, UART. It's capable of booting up into the serial console.
Signed-off-by: Jianxin Pan
Reviewed-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/Makefile
Hi Martin,
On 2019/9/10 1:24, Martin Blumenstingl wrote:
> Hi Jianxin,
>
> On Mon, Sep 9, 2019 at 2:03 PM Jianxin Pan wrote:
>>
>> Hi Martin,
>>
>> On 2019/9/7 23:02, Martin Blumenstingl wrote:
>>> Hi Jianxin,
>>>
>>> On Fri, Sep 6,
Hi Jerome,
On 2019/9/9 19:36, Jerome Brunet wrote:
>
> On Sat 07 Sep 2019 at 17:02, Martin Blumenstingl wrote:
>
>> Hi Jianxin,
>>
>> On Fri, Sep 6, 2019 at 7:58 AM Jianxin Pan wrote:
>> [...]
>>>> also I'm a bit surprised to see no busse
Hi Martin,
On 2019/9/7 23:02, Martin Blumenstingl wrote:
> Hi Jianxin,
>
> On Fri, Sep 6, 2019 at 7:58 AM Jianxin Pan wrote:
> [...]
>>> also I'm a bit surprised to see no busses (like aobus, cbus, periphs, ...)
>>> here
>>> aren't there any buss
Hi Martin,
Thanks for the review, we really appreciate your time.
Please see my comments below.
On 2019/9/6 4:15, Martin Blumenstingl wrote:
> Hi Jianxin,
>
> (it's great to see that you and your team are upstreaming this early)
>
> On Thu, Sep 5, 2019 at 9:08 AM Jia
Add bindings for the new Amlogic A1 SoC family.
A1 is an application processor designed for smart audio and IoT applications,
with dual core Cortex-A35.
Signed-off-by: Jianxin Pan
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/arm/amlogic.yaml | 4
1 file changed, 4
Add the compatible for the Amlogic A1 Based AD401 board.
Signed-off-by: Jianxin Pan
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/arm/amlogic.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml
b/Documentation
Add basic support for the Amlogic A1 based Amlogic AD401 board:
which describe components as follows: Reserve Memory, CPU, GIC, IRQ,
Timer, UART. It's capable of booting up into the serial console.
Signed-off-by: Jianxin Pan
Reviewed-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/Makefile
Add the SoC IDs for the A113L Amlogic A1 SoC.
Signed-off-by: Jianxin Pan
Reviewed-by: Neil Armstrong
---
drivers/soc/amlogic/meson-gx-socinfo.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/soc/amlogic/meson-gx-socinfo.c
b/drivers/soc/amlogic/meson-gx-socinfo.c
index 6d0d04f
-by
[0]
https://lore.kernel.org/linux-amlogic/1567493475-75451-1-git-send-email-jianxin@amlogic.com/
Jianxin Pan (4):
soc: amlogic: meson-gx-socinfo: Add A1 and A113L IDs
dt-bindings: arm: amlogic: add A1 bindings
dt-bindings: arm: amlogic: add Amlogic AD401 bindings
arm64: dts: add
Hi Neil,
Thanks for your time.
Please see my comments below.
On 2019/9/3 15:42, Neil Armstrong wrote:
> Hi,
>
> On 03/09/2019 08:51, Jianxin Pan wrote:
>> Add basic support for the Amlogic A1 based Amlogic AD401 board:
>> which describe components as follows: Reserve
Hi Jerome,
Thanks for your suggestion.
I will fix them in the next version.
On 2019/9/3 15:30, Jerome Brunet wrote:
> On Tue 03 Sep 2019 at 02:51, Jianxin Pan wrote:
>
>> Add basic support for the Amlogic A1 based Amlogic AD401 board:
>> which describe components as follo
Add bindings for the new Amlogic A1 SoC family.
A1 is an application processor designed for smart audio and IoT applications,
with dual core Cortex-A35.
Signed-off-by: Jianxin Pan
---
Documentation/devicetree/bindings/arm/amlogic.yaml | 4
1 file changed, 4 insertions(+)
diff --git
Add basic support for the Amlogic A1 based Amlogic AD401 board:
which describe components as follows: Reserve Memory, CPU, GIC, IRQ,
Timer, UART. It's capable of booting up into the serial console.
Signed-off-by: Jianxin Pan
---
arch/arm64/boot/dts/amlogic/Makefile | 1 +
arch/arm64
Add the SoC IDs for the A113L Amlogic A1 SoC.
Signed-off-by: Jianxin Pan
---
drivers/soc/amlogic/meson-gx-socinfo.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/soc/amlogic/meson-gx-socinfo.c
b/drivers/soc/amlogic/meson-gx-socinfo.c
index 6d0d04f..3c86d8d 100644
--- a/drivers
Add the compatible for the Amlogic A1 Based AD401 board.
Signed-off-by: Jianxin Pan
---
Documentation/devicetree/bindings/arm/amlogic.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml
b/Documentation/devicetree/bindings/arm
as follows: Reserve Memory, CPU, GIC, IRQ,
Timer, UART. It's capable of booting up into the serial console.
The pclk for uart_AO_B need to be fixed once A1 clock driver is merged.
In this version, it rely on bootloader to enable the pclk gate
Jianxin Pan (4):
soc: amlogic: meson-gx-socinfo: Add A1
Hi Jerome,
On 2019/1/22 17:25, Jerome Brunet wrote:
> On Tue, 2019-01-08 at 21:50 +0800, Jianxin Pan wrote:
>> When CLK_DIVIDER_ONE_BASED flag is set, the sclk divider will be:
>> one based divider (div = val), and zero value gates the clock
>>
>> Signed-off-by: Jian
Hi Miquel,
On 2019/1/20 23:06, Miquel Raynal wrote:
> Hi Jianxin,
>
> Jianxin Pan wrote on Sun, 20 Jan 2019
> 01:02:35 +0800:
>
>> Add entry for Amlogic NAND controller driver and its bindings[0].
>>
>> [0]
>> https://lore.kernel.org/lkml/15
Add entry for Amlogic NAND controller driver and its bindings[0].
[0]
https://lore.kernel.org/lkml/1547566684-57472-1-git-send-email-jianxin@amlogic.com/
Signed-off-by: Liang Yang
Signed-off-by: Jianxin Pan
---
MAINTAINERS | 7 +++
1 file changed, 7 insertions(+)
diff --git
Hi Miquel,
On 2019/1/16 0:52, Miquel Raynal wrote:
> Hi Jianxin,
>
> Jianxin Pan wrote on Tue, 15 Jan 2019
> 23:38:02 +0800:
>
>> These two patches try to add initial NAND driver support for Amlogic Meson
>> SoCs, current it has been tested on GXL(p212) and AXG(s4
Hi Martin and Jerome,
On 2019/1/18 5:20, Martin Blumenstingl wrote:
> On Thu, Jan 17, 2019 at 9:39 PM Jerome Brunet wrote:
>>
>> On Thu, 2019-01-17 at 21:27 +0100, Martin Blumenstingl wrote:
>>> OK, but we had incorrect documentation in the past. did you check this
>>> with someone from
Hi Stephen,
Thank you for your time.
Please see my comments below.
On 2019/1/10 4:48, Stephen Boyd wrote:
> Quoting Jianxin Pan (2018-12-17 08:24:10)
>> diff --git a/drivers/clk/meson/mmc-clkc.c b/drivers/clk/meson/mmc-clkc.c
>> new file mode 100644
>> index 000..258
From: Liang Yang
Add initial support for the Amlogic NAND flash controller which foundi
in the Meson SoCs.
Signed-off-by: Liang Yang
Signed-off-by: Yixun Lan
Signed-off-by: Jianxin Pan
---
drivers/mtd/nand/raw/Kconfig |8 +
drivers/mtd/nand/raw/Makefile |1 +
drivers/mtd
From: Liang Yang
Add Amlogic NAND controller dt-bindings for Meson SoC,
Current this driver support GXBB/GXL/AXG platform.
Signed-off-by: Liang Yang
Signed-off-by: Yixun Lan
Signed-off-by: Jianxin Pan
Reviewed-by: Rob Herring
---
.../devicetree/bindings/mtd/amlogic,meson-nand.txt | 60
These two patches try to add initial NAND driver support for Amlogic Meson
SoCs, current it has been tested on GXL(p212) and AXG(s400) platform.
Changes since V8 at [9]
- fix build failre at object_is_on_stack
- update Kconfig as Martin's suggested
Changes since V7 at [8]
- fix bitflips
Hi Miquel,
On 2019/1/15 16:49, Miquel Raynal wrote:
> Hi Jianxin,
>
> Jianxin Pan wrote on Sun, 16 Dec 2018
> 23:17:41 +0800:
>
>> These two patches try to add initial NAND driver support for Amlogic Meson
>> SoCs, current it has been tested on GXL(p212) and AXG(s4
When CLK_DIVIDER_ONE_BASED flag is set, the sclk divider will be:
one based divider (div = val), and zero value gates the clock
Signed-off-by: Jianxin Pan
---
drivers/clk/meson/Makefile | 3 ++-
drivers/clk/meson/clkc-audio.h | 8 --
drivers/clk/meson/clkc.h | 10
From: Yixun Lan
Export the emmc sub clock phase delay ops which will be used
by the emmc sub clock driver itself.
Signed-off-by: Yixun Lan
Signed-off-by: Jianxin Pan
---
drivers/clk/meson/Makefile | 1 +
drivers/clk/meson/clk-phase-delay.c | 73
From: Yixun Lan
Document the MMC sub clock controller driver, the potential consumer
of this driver is MMC or NAND. Also add four clock bindings IDs which
provided by this driver.
Reviewed-by: Rob Herring
Signed-off-by: Yixun Lan
Signed-off-by: Jianxin Pan
---
.../devicetree/bindings/clock
ot; in AXG platform.
To specify which clock the MMC or NAND driver may consume,
the preprocessor macros in the dt-bindings/clock/amlogic,mmc-clkc.h header
can be used in the device tree sources.
Signed-off-by: Yixun Lan
Signed-off-by: Jianxin Pan
---
drivers/clk/meson/Kconfig| 10 ++
drivers
@amlogic.com
[8]
https://lkml.kernel.org/r/1544457877-51301-1-git-send-email-jianxin@amlogic.com
[9]
https://lkml.kernel.org/r/1545063850-21504-1-git-send-email-jianxin@amlogic.com
Jianxin Pan (1):
clk: meson: add one based divider support for sclk divider
Yixun Lan (3):
clk: meson
These two patches try to add initial NAND driver support for Amlogic Meson
SoCs, current it has been tested on GXL(p212) and AXG(s400) platform.
Changes since V6 at [8]
- fix bitflips checking for blank pages
- trace the latest commit with nand/next branch
- checking the return of
From: Liang Yang
Add Amlogic NAND controller dt-bindings for Meson SoC,
Current this driver support GXBB/GXL/AXG platform.
Signed-off-by: Liang Yang
Signed-off-by: Yixun Lan
Signed-off-by: Jianxin Pan
Reviewed-by: Rob Herring
---
.../devicetree/bindings/mtd/amlogic,meson-nand.txt | 60
From: Liang Yang
Add initial support for the Amlogic NAND flash controller which found
in the Meson-GXBB/GXL/AXG SoCs.
Signed-off-by: Liang Yang
Signed-off-by: Yixun Lan
Signed-off-by: Jianxin Pan
---
drivers/mtd/nand/raw/Kconfig | 10 +
drivers/mtd/nand/raw/Makefile |1
-send-email-jianxin@amlogic.com
Jianxin Pan (1):
clk: meson: add one based divider support for sclk divider
Yixun Lan (3):
clk: meson: add emmc sub clock phase delay driver
clk: meson: add DT documentation for emmc clock controller
clk: meson: add sub MMC clock controller driver
When CLK_DIVIDER_ONE_BASED flag is set, the sclk divider will be:
one based divider (div = val), and zero value gates the clock
Signed-off-by: Jianxin Pan
---
drivers/clk/meson/Makefile | 3 ++-
drivers/clk/meson/clkc-audio.h | 8 --
drivers/clk/meson/clkc.h | 10
ot; in AXG platform.
To specify which clock the MMC or NAND driver may consume,
the preprocessor macros in the dt-bindings/clock/amlogic,mmc-clkc.h header
can be used in the device tree sources.
Signed-off-by: Yixun Lan
Signed-off-by: Jianxin Pan
---
drivers/clk/meson/Kconfig| 9 ++
drivers
From: Yixun Lan
Document the MMC sub clock controller driver, the potential consumer
of this driver is MMC or NAND. Also add four clock bindings IDs which
provided by this driver.
Reviewed-by: Rob Herring
Signed-off-by: Yixun Lan
Signed-off-by: Jianxin Pan
---
.../devicetree/bindings/clock
From: Yixun Lan
Export the emmc sub clock phase delay ops which will be used
by the emmc sub clock driver itself.
Signed-off-by: Yixun Lan
Signed-off-by: Jianxin Pan
---
drivers/clk/meson/Makefile | 1 +
drivers/clk/meson/clk-phase-delay.c | 73
When CLK_DIVIDER_ONE_BASED flag is set, the sclk divider will be:
one based divider (div = val), and zero value gates the clock
Signed-off-by: Jianxin Pan
---
drivers/clk/meson/Makefile | 3 ++-
drivers/clk/meson/clkc-audio.h | 8 --
drivers/clk/meson/clkc.h | 10
-send-email-jianxin@amlogic.com
Jianxin Pan (1):
clk: meson: add one based divider support for sclk divider
Yixun Lan (3):
clk: meson: add emmc sub clock phase delay driver
clk: meson: add DT documentation for emmc clock controller
clk: meson: add sub MMC clock controller driver
ot; in AXG platform.
To specify which clock the MMC or NAND driver may consume,
the preprocessor macros in the dt-bindings/clock/amlogic,mmc-clkc.h header
can be used in the device tree sources.
Signed-off-by: Yixun Lan
Signed-off-by: Jianxin Pan
---
drivers/clk/meson/Kconfig| 9 ++
drivers
From: Yixun Lan
Export the emmc sub clock phase delay ops which will be used
by the emmc sub clock driver itself.
Signed-off-by: Yixun Lan
Signed-off-by: Jianxin Pan
---
drivers/clk/meson/Makefile | 1 +
drivers/clk/meson/clk-phase-delay.c | 70
From: Yixun Lan
Document the MMC sub clock controller driver, the potential consumer
of this driver is MMC or NAND. Also add four clock bindings IDs which
provided by this driver.
Reviewed-by: Rob Herring
Signed-off-by: Yixun Lan
Signed-off-by: Jianxin Pan
---
.../devicetree/bindings/clock
From: Liang Yang
Add initial support for the Amlogic NAND flash controller which found
in the Meson-GXBB/GXL/AXG SoCs.
Signed-off-by: Liang Yang
Signed-off-by: Yixun Lan
Signed-off-by: Jianxin Pan
---
drivers/mtd/nand/raw/Kconfig | 10 +
drivers/mtd/nand/raw/Makefile |1
From: Liang Yang
Add Amlogic NAND controller dt-bindings for Meson SoC,
Current this driver support GXBB/GXL/AXG platform.
Signed-off-by: Liang Yang
Signed-off-by: Yixun Lan
Signed-off-by: Jianxin Pan
Reviewed-by: Rob Herring
---
.../devicetree/bindings/mtd/amlogic,meson-nand.txt | 60
These two patches try to add initial NAND driver support for Amlogic Meson
SoCs, current it has been tested on GXL(p212) and AXG(s400) platform.
Changes since V6 at [8]
- fix bitflips checking for blank pages
- trace the latest commit with nand/next branch
- checking the return of
On 2018/12/13 17:01, Jerome Brunet wrote:
> On Thu, 2018-12-13 at 12:55 +0800, Jianxin Pan wrote:
>> On 2018/12/12 0:59, Jerome Brunet wrote:
>>> On Tue, 2018-12-11 at 00:04 +0800, Jianxin Pan wrote:
>>>> From: Yixun Lan
>>>>
>> [...]
>>&
Hi Jerome,
Thanks for the fully review, we really appreciate your time.
On 2018/12/12 1:16, Jerome Brunet wrote:
> On Tue, 2018-12-11 at 00:04 +0800, Jianxin Pan wrote:
>> When CLK_DIVIDER_ONE_BASED flag is set, the sclk divider will be:
>> one based divider (div = val), and z
On 2018/12/12 0:59, Jerome Brunet wrote:
> On Tue, 2018-12-11 at 00:04 +0800, Jianxin Pan wrote:
>> From: Yixun Lan
>>
[...]
>>
>> +config COMMON_CLK_MMC_MESON
>> +tristate "Meson MMC Sub Clock Controller Driver"
>> +select MFD_SYSCON
HI Jerome,
On 2018/12/12 0:28, Jerome Brunet wrote:
> On Tue, 2018-12-11 at 00:04 +0800, Jianxin Pan wrote:
>> From: Yixun Lan
>>
[...]
>> +
>> +static inline struct meson_clk_phase_delay_data *
>> +meson_clk_get_phase_delay_data(struct clk_regmap *cl
From: Yixun Lan
Document the MMC sub clock controller driver, the potential consumer
of this driver is MMC or NAND. Also add four clock bindings IDs which
provided by this driver.
Reviewed-by: Rob Herring
Signed-off-by: Yixun Lan
Signed-off-by: Jianxin Pan
---
.../devicetree/bindings/clock
When CLK_DIVIDER_ONE_BASED flag is set, the sclk divider will be:
one based divider (div = val), and zero value gates the clock
Signed-off-by: Jianxin Pan
---
drivers/clk/meson/clkc-audio.h | 1 +
drivers/clk/meson/sclk-div.c | 28 ++--
2 files changed, 19 insertions
ot; in AXG platform.
To specify which clock the MMC or NAND driver may consume,
the preprocessor macros in the dt-bindings/clock/amlogic,mmc-clkc.h header
can be used in the device tree sources.
Signed-off-by: Yixun Lan
Signed-off-by: Jianxin Pan
---
drivers/clk/meson/Kconfig| 10 ++
drivers
From: Yixun Lan
Export the emmc sub clock phase delay ops which will be used
by the emmc sub clock driver itself.
Signed-off-by: Yixun Lan
Signed-off-by: Jianxin Pan
---
drivers/clk/meson/Makefile | 2 +-
drivers/clk/meson/clk-phase-delay.c | 64
This driver will add a MMC clock controller driver support.
The original idea about adding a clock controller is during the
discussion in the NAND driver mainline effort[1].
This driver is tested in the S400 board (AXG platform) with NAND driver.
Changes since v6 [7]:
- add one based support
Hi Stephen,
On 2018/12/4 6:45, Stephen Boyd wrote:
> Quoting Jianxin Pan (2018-11-15 04:18:30)
>> diff --git a/include/dt-bindings/clock/amlogic,mmc-clkc.h
>> b/include/dt-bindings/clock/amlogic,mmc-clkc.h
>> new file mode 100644
>> index 000..162b949
>>
Hi Stephen,
On 2018/12/4 6:45, Stephen Boyd wrote:
> Quoting Jianxin Pan (2018-11-15 04:18:30)
>> diff --git a/include/dt-bindings/clock/amlogic,mmc-clkc.h
>> b/include/dt-bindings/clock/amlogic,mmc-clkc.h
>> new file mode 100644
>> index 000..162b949
>>
Hi Jerome,
I made some modifications as you suggested， could you please take a look?
On 2018/11/15 20:18, Jianxin Pan wrote:
> This driver will add a MMC clock controller driver support.
> The original idea about adding a clock controller is during the
> discussion in the NAND driver
Hi Jerome,
I made some modifications as you suggested， could you please take a look?
On 2018/11/15 20:18, Jianxin Pan wrote:
> This driver will add a MMC clock controller driver support.
> The original idea about adding a clock controller is during the
> discussion in the NAND driver
From: Liang Yang
Add initial support for the Amlogic NAND flash controller which found
in the Meson-GXBB/GXL/AXG SoCs.
Signed-off-by: Liang Yang
Signed-off-by: Yixun Lan
Signed-off-by: Jianxin Pan
---
drivers/mtd/nand/raw/Kconfig | 10 +
drivers/mtd/nand/raw/Makefile |1
From: Liang Yang
Add Amlogic NAND controller dt-bindings for Meson SoC,
Current this driver support GXBB/GXL/AXG platform.
Signed-off-by: Liang Yang
Signed-off-by: Yixun Lan
Signed-off-by: Jianxin Pan
Reviewed-by: Rob Herring
---
.../devicetree/bindings/mtd/amlogic,meson-nand.txt | 60
From: Liang Yang
Add initial support for the Amlogic NAND flash controller which found
in the Meson-GXBB/GXL/AXG SoCs.
Signed-off-by: Liang Yang
Signed-off-by: Yixun Lan
Signed-off-by: Jianxin Pan
---
drivers/mtd/nand/raw/Kconfig | 10 +
drivers/mtd/nand/raw/Makefile |1
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