Re: [PATCH for-next] scsi: ufs: Update dwc driver maintainer to Pedro Sousa

Thanks Martin. On 2/5/2019 3:37 AM, Martin K. Petersen wrote: > Joao, > >> Currently I am managing the Synopsys drivers & tools team (full-time) and >> so I am passing the DWC UFS driver maintenance to Pedro Sousa. > Applied to 5.1/scsi-queue, thanks. >

Re: [PATCH for-next] scsi: ufs: Update dwc driver maintainer to Pedro Sousa

Hello Bart, First of all thanks for the feedback. On 1/30/2019 5:54 PM, Bart Van Assche wrote: > On Wed, 2019-01-30 at 18:48 +0100, Joao Pinto wrote: >> Currently I am managing the Synopsys drivers & tools team (full-time) and >> so I am passing the DWC UFS driver mainten

[PATCH for-next] scsi: ufs: Update dwc driver maintainer to Pedro Sousa

Currently I am managing the Synopsys drivers & tools team (full-time) and so I am passing the DWC UFS driver maintenance to Pedro Sousa. Signed-off-by: Joao Pinto Cc: Pedro Sousa Cc: Marc Gonzalez Cc: Alex Lemberg --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

[PATCH] PCI: designware: Change maintainer to Gustavo Pimentel

Currently I am managing the Synopsys drivers & tools team (full-time) and so I am passing the pcie-designware maintenance to Gustavo. Signed-off-by: Joao Pinto CC: Gustavo Pimentel CC: Jingoo Han --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINE

[PATCH] PCI: designware: Change maintainer to Gustavo Pimentel

Currently I am managing the Synopsys drivers & tools team (full-time) and so I am passing the pcie-designware maintenance to Gustavo. Signed-off-by: Joao Pinto CC: Gustavo Pimentel CC: Jingoo Han --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINE

Re: [PATCH 0/4] Add DesignWare EP support

-- > drivers/pci/endpoint/functions/pci-epf-test.c | 7 + > include/linux/pci-epc.h| 8 ++ > 7 files changed, 206 insertions(+), 27 deletions(-) > Thanks for this patch-set. Reviewed-by: Joao Pinto <jpi...@synopsys.com>

Re: [PATCH 0/4] Add DesignWare EP support

-- > drivers/pci/endpoint/functions/pci-epf-test.c | 7 + > include/linux/pci-epc.h| 8 ++ > 7 files changed, 206 insertions(+), 27 deletions(-) > Thanks for this patch-set. Reviewed-by: Joao Pinto

Re: [PATCH v4 6/8] PCI: Rework of_pci_get_host_bridge_resources() to devm_of_pci_get_host_bridge_resources()

uiring everyone to do this explicitly, convert the > existing function to a managed version. > > CC: Jingoo Han <jingooh...@gmail.com> > CC: Joao Pinto <joao.pi...@synopsys.com> > CC: Lorenzo Pieralisi <lorenzo.pieral...@arm.com> > Signed-off-by: Jan Kiszka <jan.

Re: [PATCH v4 6/8] PCI: Rework of_pci_get_host_bridge_resources() to devm_of_pci_get_host_bridge_resources()

icitly, convert the > existing function to a managed version. > > CC: Jingoo Han > CC: Joao Pinto > CC: Lorenzo Pieralisi > Signed-off-by: Jan Kiszka > --- > drivers/pci/dwc/pcie-designware-host.c | 2 +- > drivers/pci/host/pci-aardvark.c| 2 +- > drivers/pci/

Re: [PATCH 2/4] PCI: dwc: Add support for EP mode

++ b/drivers/pci/endpoint/functions/pci-epf-test.c > @@ -435,6 +435,13 @@ static int pci_epf_test_bind(struct pci_epf *epf) > if (WARN_ON_ONCE(!epc)) > return -EINVAL; > > + if (epc->features & EPC_FEATURE_NO_LINKUP_NOTIFIER) > + epf_test->linkup_notifier = false; > + else > + epf_test->linkup_notifier = true; > + > + epf_test->test_reg_bar = EPC_FEATURE_GET_BAR(epc->features); > + > ret = pci_epc_write_header(epc, epf->func_no, header); > if (ret) { > dev_err(dev, "configuration header write failed\n"); > diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h > index af657ca..243eaa5 100644 > --- a/include/linux/pci-epc.h > +++ b/include/linux/pci-epc.h > @@ -90,8 +90,16 @@ struct pci_epc { > struct config_group *group; > /* spinlock to protect against concurrent access of EP controller */ > spinlock_t lock; > + unsigned intfeatures; > }; > > +#define EPC_FEATURE_NO_LINKUP_NOTIFIER BIT(0) > +#define EPC_FEATURE_BAR_MASK (BIT(1) | BIT(2) | BIT(3)) > +#define EPC_FEATURE_SET_BAR(features, bar) \ > + (features |= (EPC_FEATURE_BAR_MASK & (bar << 1))) > +#define EPC_FEATURE_GET_BAR(features)\ > + ((features & EPC_FEATURE_BAR_MASK) >> 1) > + > #define to_pci_epc(device) container_of((device), struct pci_epc, dev) > > #define pci_epc_create(dev, ops)\ > Acked-by: Joao Pinto <jpi...@synopsys.com>

Re: [PATCH 2/4] PCI: dwc: Add support for EP mode

@@ -435,6 +435,13 @@ static int pci_epf_test_bind(struct pci_epf *epf) > if (WARN_ON_ONCE(!epc)) > return -EINVAL; > > + if (epc->features & EPC_FEATURE_NO_LINKUP_NOTIFIER) > + epf_test->linkup_notifier = false; > + else > + epf_test->linkup_notifier = true; > + > + epf_test->test_reg_bar = EPC_FEATURE_GET_BAR(epc->features); > + > ret = pci_epc_write_header(epc, epf->func_no, header); > if (ret) { > dev_err(dev, "configuration header write failed\n"); > diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h > index af657ca..243eaa5 100644 > --- a/include/linux/pci-epc.h > +++ b/include/linux/pci-epc.h > @@ -90,8 +90,16 @@ struct pci_epc { > struct config_group *group; > /* spinlock to protect against concurrent access of EP controller */ > spinlock_t lock; > + unsigned intfeatures; > }; > > +#define EPC_FEATURE_NO_LINKUP_NOTIFIER BIT(0) > +#define EPC_FEATURE_BAR_MASK (BIT(1) | BIT(2) | BIT(3)) > +#define EPC_FEATURE_SET_BAR(features, bar) \ > + (features |= (EPC_FEATURE_BAR_MASK & (bar << 1))) > +#define EPC_FEATURE_GET_BAR(features)\ > + ((features & EPC_FEATURE_BAR_MASK) >> 1) > + > #define to_pci_epc(device) container_of((device), struct pci_epc, dev) > > #define pci_epc_create(dev, ops)\ > Acked-by: Joao Pinto

Re: [PATCH v5 09/10] PCI: dwc: Small computation improvement

gt; - pp->cfg0_size = resource_size(pp->cfg) / 2; > - pp->cfg1_size = resource_size(pp->cfg) / 2; > + pp->cfg0_size = resource_size(pp->cfg) >> 1; > + pp->cfg1_size = resource_size(pp->cfg) >> 1; > pp->cfg0_base = pp->cfg->start; > pp->cfg1_base = pp->cfg->start + pp->cfg0_size; > break; > Thanks Gustavo! Acked-by: Joao Pinto <jpi...@synopsys.com>

Re: [PATCH v5 09/10] PCI: dwc: Small computation improvement

resource_size(pp->cfg) / 2; > - pp->cfg1_size = resource_size(pp->cfg) / 2; > + pp->cfg0_size = resource_size(pp->cfg) >> 1; > + pp->cfg1_size = resource_size(pp->cfg) >> 1; > pp->cfg0_base = pp->cfg->start; > pp->cfg1_base = pp->cfg->start + pp->cfg0_size; > break; > Thanks Gustavo! Acked-by: Joao Pinto

Re: [PATCH v5 08/10] PCI: dwc: Replace lower into upper case characters

not being enabled\n"); > + dev_err(pci->dev, "Inbound iATU is not being enabled\n"); > > return -EBUSY; > } > @@ -284,7 +284,7 @@ int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int > index, int bar, > > usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX); > } > - dev_err(pci->dev, "inbound iATU is not being enabled\n"); > + dev_err(pci->dev, "Inbound iATU is not being enabled\n"); > > return -EBUSY; > } > @@ -313,16 +313,16 @@ int dw_pcie_wait_for_link(struct dw_pcie *pci) > { > int retries; > > - /* check if the link is up or not */ > + /* Check if the link is up or not */ > for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { > if (dw_pcie_link_up(pci)) { > - dev_info(pci->dev, "link up\n"); > + dev_info(pci->dev, "Link up\n"); > return 0; > } > usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); > } > > - dev_err(pci->dev, "phy link never came up\n"); > + dev_err(pci->dev, "Phy link never came up\n"); > > return -ETIMEDOUT; > } > @@ -351,7 +351,7 @@ void dw_pcie_setup(struct dw_pcie *pci) > if (ret) > lanes = 0; > > - /* set the number of lanes */ > + /* Set the number of lanes */ > val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL); > val &= ~PORT_LINK_MODE_MASK; > switch (lanes) { > @@ -373,7 +373,7 @@ void dw_pcie_setup(struct dw_pcie *pci) > } > dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val); > > - /* set link width speed control register */ > + /* Set link width speed control register */ > val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); > val &= ~PORT_LOGIC_LINK_WIDTH_MASK; > switch (lanes) { > Acked-by: Joao Pinto <jpi...@synopsys.com>

Re: [PATCH v5 08/10] PCI: dwc: Replace lower into upper case characters

ot;Inbound iATU is not being enabled\n"); > > return -EBUSY; > } > @@ -284,7 +284,7 @@ int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int > index, int bar, > > usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX); > } > - dev_err(pci->dev, "inbound iATU is not being enabled\n"); > + dev_err(pci->dev, "Inbound iATU is not being enabled\n"); > > return -EBUSY; > } > @@ -313,16 +313,16 @@ int dw_pcie_wait_for_link(struct dw_pcie *pci) > { > int retries; > > - /* check if the link is up or not */ > + /* Check if the link is up or not */ > for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { > if (dw_pcie_link_up(pci)) { > - dev_info(pci->dev, "link up\n"); > + dev_info(pci->dev, "Link up\n"); > return 0; > } > usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); > } > > - dev_err(pci->dev, "phy link never came up\n"); > + dev_err(pci->dev, "Phy link never came up\n"); > > return -ETIMEDOUT; > } > @@ -351,7 +351,7 @@ void dw_pcie_setup(struct dw_pcie *pci) > if (ret) > lanes = 0; > > - /* set the number of lanes */ > + /* Set the number of lanes */ > val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL); > val &= ~PORT_LINK_MODE_MASK; > switch (lanes) { > @@ -373,7 +373,7 @@ void dw_pcie_setup(struct dw_pcie *pci) > } > dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val); > > - /* set link width speed control register */ > + /* Set link width speed control register */ > val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); > val &= ~PORT_LOGIC_LINK_WIDTH_MASK; > switch (lanes) { > Acked-by: Joao Pinto

Re: [PATCH v5 07/10] PCI: dwc: Define maximum number of vectors

ost_ops = { > .host_init = dw_plat_pcie_host_init, > + .set_num_vectors = dw_plat_set_num_vectors, > }; > > static int dw_plat_pcie_establish_link(struct dw_pcie *pci) > Yes, in our reference plat driver we should target all the available IRQs. Thanks! Acked-by: Joao Pinto <jpi...@synopsys.com>

Re: [PATCH v5 07/10] PCI: dwc: Define maximum number of vectors

init, > + .set_num_vectors = dw_plat_set_num_vectors, > }; > > static int dw_plat_pcie_establish_link(struct dw_pcie *pci) > Yes, in our reference plat driver we should target all the available IRQs. Thanks! Acked-by: Joao Pinto

Re: [PATCH v5 02/10] PCI: dwc: Add support for endpoint mode

Hi Gustavo, Às 3:34 PM de 4/17/2018, Gustavo Pimentel escreveu: > The PCIe controller dual mode is capable of operating in host mode as well > as endpoint mode by configuration, therefore this patch aims to add > endpoint mode support to the designware driver. > > Signed-off-by: Gustavo

Re: [PATCH v5 02/10] PCI: dwc: Add support for endpoint mode

Hi Gustavo, Às 3:34 PM de 4/17/2018, Gustavo Pimentel escreveu: > The PCIe controller dual mode is capable of operating in host mode as well > as endpoint mode by configuration, therefore this patch aims to add > endpoint mode support to the designware driver. > > Signed-off-by: Gustavo

Re: [PATCH v2] PCI: dwc: Use {upper,lower}_32_bits() macros for clarity

g the update of the Interrupt API for pcie-designware* already does this modification, so I would suggest that we wait for Gustavo' patch to be stable and get the same modification. Best regards, Joao Pinto

Re: [PATCH v2] PCI: dwc: Use {upper,lower}_32_bits() macros for clarity

ddress_lo = lower_32_bits(msi_target); > + msg.address_hi = upper_32_bits(msi_target); > > if (pp->ops->get_msi_data) > msg.data = pp->ops->get_msi_data(pp, pos); > Thanks for the patch. Gustavo' patch-set targeting the update of the Interrupt API for pcie-designware* already does this modification, so I would suggest that we wait for Gustavo' patch to be stable and get the same modification. Best regards, Joao Pinto

Re: [PATCH v6 00/18] dwc MSI fixes, ARTPEC-6 EP mode support, ARTPEC-7 SoC support

Hi Niklas, Às 11:22 PM de 12/20/2017, Niklas Cassel escreveu: > On Wed, Dec 20, 2017 at 07:47:41PM +0000, Joao Pinto wrote: >> >> Hello to all, >> >> Às 5:34 PM de 12/20/2017, Lorenzo Pieralisi escreveu: >>> On Wed, Dec 20, 2017 at 12:29:21AM +0100, Niklas

Re: [PATCH v6 00/18] dwc MSI fixes, ARTPEC-6 EP mode support, ARTPEC-7 SoC support

Hi Niklas, Às 11:22 PM de 12/20/2017, Niklas Cassel escreveu: > On Wed, Dec 20, 2017 at 07:47:41PM +0000, Joao Pinto wrote: >> >> Hello to all, >> >> Às 5:34 PM de 12/20/2017, Lorenzo Pieralisi escreveu: >>> On Wed, Dec 20, 2017 at 12:29:21AM +0100, Niklas

Re: [PATCH v6 00/18] dwc MSI fixes, ARTPEC-6 EP mode support, ARTPEC-7 SoC support

Hello to all, Às 5:34 PM de 12/20/2017, Lorenzo Pieralisi escreveu: > On Wed, Dec 20, 2017 at 12:29:21AM +0100, Niklas Cassel wrote: >> This is a series that adds: >> - PCI endpoint mode support in the ARTPEC-6 driver. >> - ARTPEC-7 SoC support in the ARTPEC-6 driver (the SoCs are very similar).

Re: [PATCH v6 00/18] dwc MSI fixes, ARTPEC-6 EP mode support, ARTPEC-7 SoC support

Hello to all, Às 5:34 PM de 12/20/2017, Lorenzo Pieralisi escreveu: > On Wed, Dec 20, 2017 at 12:29:21AM +0100, Niklas Cassel wrote: >> This is a series that adds: >> - PCI endpoint mode support in the ARTPEC-6 driver. >> - ARTPEC-7 SoC support in the ARTPEC-6 driver (the SoCs are very similar).

Re: [PATCH v6 06/18] PCI: designware-ep: Add generic function for raising MSI irq

reset_bar(struct dw_pcie *pci, enum pci_barno bar); > #else > static inline void dw_pcie_ep_linkup(struct dw_pcie_ep *ep) > @@ -353,6 +356,12 @@ static inline void dw_pcie_ep_exit(struct dw_pcie_ep *ep) > { > } > > +static inline int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, > +u8 interrupt_num) > +{ > + return 0; > +} > + > static inline void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno > bar) > { > } > Acked-by: Joao Pinto <jpi...@synopsys.com>

Re: [PATCH v6 06/18] PCI: designware-ep: Add generic function for raising MSI irq

bar(struct dw_pcie *pci, enum pci_barno bar); > #else > static inline void dw_pcie_ep_linkup(struct dw_pcie_ep *ep) > @@ -353,6 +356,12 @@ static inline void dw_pcie_ep_exit(struct dw_pcie_ep *ep) > { > } > > +static inline int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, > +u8 interrupt_num) > +{ > + return 0; > +} > + > static inline void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno > bar) > { > } > Acked-by: Joao Pinto

Re: [PATCH v6 04/18] PCI: designware-ep: Pre-allocate memory for MSI in dw_pcie_ep_init

@ -198,6 +198,8 @@ struct dw_pcie_ep { > unsigned long ob_window_map; > u32 num_ib_windows; > u32 num_ob_windows; > + void __iomem*msi_mem; > + phys_addr_t msi_mem_phys; > }; > > struct dw_pcie_ops { > Acked-by: Joao Pinto <jpi...@synopsys.com>

Re: [PATCH v6 04/18] PCI: designware-ep: Pre-allocate memory for MSI in dw_pcie_ep_init

dw_pcie_ep { > unsigned long ob_window_map; > u32 num_ib_windows; > u32 num_ob_windows; > + void __iomem*msi_mem; > + phys_addr_t msi_mem_phys; > }; > > struct dw_pcie_ops { > Acked-by: Joao Pinto

Re: [PATCH v6 03/18] PCI: designware-ep: Read-only registers need DBI_RO_WR_EN to be writable

_epc *epc, u8 > encode_int) > val = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL); > val &= ~MSI_CAP_MMC_MASK; > val |= (encode_int << MSI_CAP_MMC_SHIFT) & MSI_CAP_MMC_MASK; > + dw_pcie_dbi_ro_wr_en(pci); > dw_pcie_writew_dbi(pci, MSI_MESSAGE_CONTROL, val); > + dw_pcie_dbi_ro_wr_dis(pci); > > return 0; > } > Acked-by: Joao Pinto <jpi...@synopsys.com>

Re: [PATCH v6 03/18] PCI: designware-ep: Read-only registers need DBI_RO_WR_EN to be writable

val = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL); > val &= ~MSI_CAP_MMC_MASK; > val |= (encode_int << MSI_CAP_MMC_SHIFT) & MSI_CAP_MMC_MASK; > + dw_pcie_dbi_ro_wr_en(pci); > dw_pcie_writew_dbi(pci, MSI_MESSAGE_CONTROL, val); > + dw_pcie_dbi_ro_wr_dis(pci); > > return 0; > } > Acked-by: Joao Pinto

Re: [PATCH v6 02/18] PCI: designware-ep: dw_pcie_ep_set_msi() should only set MMC bits

(7 << MSI_CAP_MMC_SHIFT) > #define MSI_CAP_MME_SHIFT4 > #define MSI_CAP_MME_MASK (7 << MSI_CAP_MME_SHIFT) > #define MSI_MESSAGE_ADDR_L32 0x54 > Acked-by: Joao Pinto <jpi...@synopsys.com>

Re: [PATCH v6 02/18] PCI: designware-ep: dw_pcie_ep_set_msi() should only set MMC bits

IFT) > #define MSI_CAP_MME_SHIFT 4 > #define MSI_CAP_MME_MASK (7 << MSI_CAP_MME_SHIFT) > #define MSI_MESSAGE_ADDR_L32 0x54 > Acked-by: Joao Pinto

Re: [PATCH v6 01/18] PCI: dwc: Use the DMA-API to get the MSI address

DESIGNWARE_H > > +#include > #include > #include > #include > @@ -168,7 +169,7 @@ struct pcie_port { > const struct dw_pcie_host_ops *ops; > int msi_irq; > struct irq_domain *irq_domain; > - unsigned long msi_data; > + dma_addr_t msi_data; > DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS); > }; > > Makes total sense! Thanks. Acked-by: Joao Pinto <jpi...@synopsys.com>

Re: [PATCH v6 01/18] PCI: dwc: Use the DMA-API to get the MSI address

+#include > #include > #include > #include > @@ -168,7 +169,7 @@ struct pcie_port { > const struct dw_pcie_host_ops *ops; > int msi_irq; > struct irq_domain *irq_domain; > - unsigned long msi_data; > + dma_addr_t msi_data; > DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS); > }; > > Makes total sense! Thanks. Acked-by: Joao Pinto

Re: [PATCH v5 01/18] PCI: dwc: Use the DMA-API to get the MSI address

Hi Niklas, Às 1:59 PM de 12/13/2017, Niklas Cassel escreveu: > On Thu, Nov 30, 2017 at 03:28:43PM +, Lorenzo Pieralisi wrote: >> Jingoo, Joao, >> >> I am expecting your testing on the series and ACKs on the dwc related >> patches please, according to v4 review - I will mark them as needs >>

Re: [PATCH v5 01/18] PCI: dwc: Use the DMA-API to get the MSI address

Hi Niklas, Às 1:59 PM de 12/13/2017, Niklas Cassel escreveu: > On Thu, Nov 30, 2017 at 03:28:43PM +, Lorenzo Pieralisi wrote: >> Jingoo, Joao, >> >> I am expecting your testing on the series and ACKs on the dwc related >> patches please, according to v4 review - I will mark them as needs >>

Re: [PATCH net-next] net: stmmac: fix broken dma_interrupt handling for multi-queues

Hi Niklas, Às 10:56 PM de 12/7/2017, Niklas Cassel escreveu: > There is nothing that says that number of TX queues == number of RX > queues. E.g. the ARTPEC-6 SoC has 2 TX queues and 1 RX queue. > Yes you are totally right. Our Hardware was configured with 4RX queues and 4TX queues and that

Re: [PATCH net-next] net: stmmac: fix broken dma_interrupt handling for multi-queues

Hi Niklas, Às 10:56 PM de 12/7/2017, Niklas Cassel escreveu: > There is nothing that says that number of TX queues == number of RX > queues. E.g. the ARTPEC-6 SoC has 2 TX queues and 1 RX queue. > Yes you are totally right. Our Hardware was configured with 4RX queues and 4TX queues and that

Re: [PATCH v4 01/17] PCI: dwc: Use the DMA-API to get the MSI address

Hello to all, Às 12:56 AM de 11/8/2017, Bjorn Helgaas escreveu: > On Fri, Nov 03, 2017 at 02:47:05PM +0100, Niklas Cassel wrote: >> Use the DMA-API to get the MSI address. This address will be written to >> our PCI config space and to the register which determines which AXI >> address the DWC IP

Re: [PATCH v4 01/17] PCI: dwc: Use the DMA-API to get the MSI address

Hello to all, Às 12:56 AM de 11/8/2017, Bjorn Helgaas escreveu: > On Fri, Nov 03, 2017 at 02:47:05PM +0100, Niklas Cassel wrote: >> Use the DMA-API to get the MSI address. This address will be written to >> our PCI config space and to the register which determines which AXI >> address the DWC IP

Re: [PATCH] pci: dwc: Clear MSI interrupt status after it is handled

dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, > 4, 1 << pos); > - generic_handle_irq(irq); > pos++; > } > } > It makes sense. Acked-By: Joao Pinto <jpi...@synopsys.com>

Re: [PATCH] pci: dwc: Clear MSI interrupt status after it is handled

TR0_STATUS + i * 12, > 4, 1 << pos); > - generic_handle_irq(irq); > pos++; > } > } > It makes sense. Acked-By: Joao Pinto

Re: [PATCH 1/1] scsi: ufs: changing maintainer

Hello Greg and Prabu, Às 10:31 AM de 7/18/2017, Greg Kroah-Hartman (gre...@linuxfoundation.org) escreveu: > On Tue, Jul 18, 2017 at 09:15:58AM +, Prabu Thangamuthu wrote: >> As per internal decision, Joao Pinto will be maintainer for DWC UFS driver. > > That's "

Re: [PATCH 1/1] scsi: ufs: changing maintainer

Hello Greg and Prabu, Às 10:31 AM de 7/18/2017, Greg Kroah-Hartman (gre...@linuxfoundation.org) escreveu: > On Tue, Jul 18, 2017 at 09:15:58AM +, Prabu Thangamuthu wrote: >> As per internal decision, Joao Pinto will be maintainer for DWC UFS driver. > > That's "

Re: [PATCH] PCI: dwc: designware: make dw_pcie_prog_*_atu_unroll() static

el_dbi(pci, offset + reg, val); > } > > -int dw_pcie_prog_inbound_atu_unroll(struct dw_pcie *pci, int index, int bar, > +static int dw_pcie_prog_inbound_atu_unroll(struct dw_pcie *pci, int index, > int bar, > u64 cpu_addr, enum dw_pcie_as

Re: [PATCH] PCI: dwc: designware: make dw_pcie_prog_*_atu_unroll() static

val); > } > > -int dw_pcie_prog_inbound_atu_unroll(struct dw_pcie *pci, int index, int bar, > +static int dw_pcie_prog_inbound_atu_unroll(struct dw_pcie *pci, int index, > int bar, > u64 cpu_addr, enum dw_pcie_as_type as_type) > { > int type; > -- > 2.11.0 > That indeed escaped in the refactoring :) Thanks! Acked-by: Joao Pinto

Re: [PATCH 1/3] PCI: dwc: Handle host_init failures

ct pcie_port *pp) > if (ret) > goto err; > > - return; > + return 0; > err: > qcom_ep_reset_assert(pcie); > phy_power_off(pcie->phy); > err_deinit: > pcie->ops->deinit(pcie); > + > + return ret; > } > >

Re: [PATCH 1/3] PCI: dwc: Handle host_init failures

gt; goto err; > > - return; > + return 0; > err: > qcom_ep_reset_assert(pcie); > phy_power_off(pcie->phy); > err_deinit: > pcie->ops->deinit(pcie); > + > + return ret; > } > > static int qcom_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, > diff --git a/drivers/pci/dwc/pcie-spear13xx.c > b/drivers/pci/dwc/pcie-spear13xx.c > index 80897291e0fb..52000bc34600 100644 > --- a/drivers/pci/dwc/pcie-spear13xx.c > +++ b/drivers/pci/dwc/pcie-spear13xx.c > @@ -177,13 +177,15 @@ static int spear13xx_pcie_link_up(struct dw_pcie *pci) > return 0; > } > > -static void spear13xx_pcie_host_init(struct pcie_port *pp) > +static int spear13xx_pcie_host_init(struct pcie_port *pp) > { > struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pci); > > spear13xx_pcie_establish_link(spear13xx_pcie); > spear13xx_pcie_enable_interrupts(spear13xx_pcie); > + > + return 0; > } > > static const struct dw_pcie_host_ops spear13xx_pcie_host_ops = { > A step in the right direction :). In the future we should add host init validation in the specific SoC drivers, like Layerscape and Qcom have, to assure that any problem is treated properly in the core driver. Acked-by: Joao Pinto

Re: [PATCH] PCI: dwc: designware: test PCIE_ATU_ENABLE bit to check enabled or not

dbi(pci, PCIE_ATU_CR2); > - if (val == PCIE_ATU_ENABLE) > + if (val & PCIE_ATU_ENABLE) > return; > > usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX); > Make sense, turn it more accurate. Thanks! Acked-by: Joao Pinto <jpi...@synopsys.com>

Re: [PATCH] PCI: dwc: designware: test PCIE_ATU_ENABLE bit to check enabled or not

if (val == PCIE_ATU_ENABLE) > + if (val & PCIE_ATU_ENABLE) > return; > > usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX); > Make sense, turn it more accurate. Thanks! Acked-by: Joao Pinto

Re: [PATCH v9 2/3] PCI: Add tango PCIe host bridge support

Hi to all, Às 10:38 AM de 7/4/2017, Ard Biesheuvel escreveu: > On 4 July 2017 at 09:19, Jisheng Zhang wrote: >> On Tue, 4 Jul 2017 09:02:06 +0100 Ard Biesheuvel wrote: >> >>> On 4 July 2017 at 07:58, Jisheng Zhang wrote: On Mon, 3 Jul 2017 08:27:04

Re: [PATCH v9 2/3] PCI: Add tango PCIe host bridge support

Hi to all, Às 10:38 AM de 7/4/2017, Ard Biesheuvel escreveu: > On 4 July 2017 at 09:19, Jisheng Zhang wrote: >> On Tue, 4 Jul 2017 09:02:06 +0100 Ard Biesheuvel wrote: >> >>> On 4 July 2017 at 07:58, Jisheng Zhang wrote: On Mon, 3 Jul 2017 08:27:04 -0500 wrote: > [+cc Jingoo,

Re: [PATCH V4 2/2] scsi: ufshcd-pci: Add Intel CNL support

Hello to all, Às 2:16 PM de 6/7/2017, Christoph Hellwig escreveu: > On Tue, Jun 06, 2017 at 02:35:31PM +0300, Adrian Hunter wrote: >> Add PCI id and variant ops for Intel CNL UFS host controller. > > Looks good: > > Reviewed-by: Christoph Hellwig > > It would be great if we could

Re: [PATCH V4 2/2] scsi: ufshcd-pci: Add Intel CNL support

Hello to all, Às 2:16 PM de 6/7/2017, Christoph Hellwig escreveu: > On Tue, Jun 06, 2017 at 02:35:31PM +0300, Adrian Hunter wrote: >> Add PCI id and variant ops for Intel CNL UFS host controller. > > Looks good: > > Reviewed-by: Christoph Hellwig > > It would be great if we could fold

Re: Regression: 442ec4c04d1: PCI: dwc: all: Split struct pcie_port into host-only and core structures

Às 4:20 PM de 5/8/2017, Kishon Vijay Abraham I escreveu: > Hi Joao, > > On Monday 08 May 2017 08:43 PM, Joao Pinto wrote: >> >> Hi Peter, >> >> Às 4:02 PM de 5/8/2017, Peter Senna Tschudin escreveu: >>> Hello Kishon, >>> >>> Our

Re: Regression: 442ec4c04d1: PCI: dwc: all: Split struct pcie_port into host-only and core structures

Às 4:20 PM de 5/8/2017, Kishon Vijay Abraham I escreveu: > Hi Joao, > > On Monday 08 May 2017 08:43 PM, Joao Pinto wrote: >> >> Hi Peter, >> >> Às 4:02 PM de 5/8/2017, Peter Senna Tschudin escreveu: >>> Hello Kishon, >>> >>> Our

Re: Regression: 442ec4c04d1: PCI: dwc: all: Split struct pcie_port into host-only and core structures

Hi Peter, Às 4:02 PM de 5/8/2017, Peter Senna Tschudin escreveu: > Hello Kishon, > > Our iMX6 hardware (imx6q-b850v3.dts) is not booting with latest > linux-next and I could bisect until: > > commit 442ec4c04d1235f8c664a74004dae54a7a574d18 > Author: Kishon Vijay Abraham I >

Re: Regression: 442ec4c04d1: PCI: dwc: all: Split struct pcie_port into host-only and core structures

Hi Peter, Às 4:02 PM de 5/8/2017, Peter Senna Tschudin escreveu: > Hello Kishon, > > Our iMX6 hardware (imx6q-b850v3.dts) is not booting with latest > linux-next and I could bisect until: > > commit 442ec4c04d1235f8c664a74004dae54a7a574d18 > Author: Kishon Vijay Abraham I > Date: Wed Feb 15

Re: [PATCH v3 net-next 01/11] net: stmmac: prepare dma op mode config for multiple queues

Às 12:56 PM de 5/8/2017, Andy Shevchenko escreveu: > On Mon, May 8, 2017 at 2:40 PM, Joao Pinto <joao.pi...@synopsys.com> wrote: >> Às 12:34 PM de 5/8/2017, Andy Shevchenko escreveu: >>> On Mon, May 8, 2017 at 1:42 PM, Joao Pinto <joao.pi...@synopsys.com> wrote: >

Re: [PATCH v3 net-next 01/11] net: stmmac: prepare dma op mode config for multiple queues

Às 12:56 PM de 5/8/2017, Andy Shevchenko escreveu: > On Mon, May 8, 2017 at 2:40 PM, Joao Pinto wrote: >> Às 12:34 PM de 5/8/2017, Andy Shevchenko escreveu: >>> On Mon, May 8, 2017 at 1:42 PM, Joao Pinto wrote: >>>> Às 11:12 AM de 5/8/2017, Andy Shevchenko escre

Re: [PATCH v3 net-next 01/11] net: stmmac: prepare dma op mode config for multiple queues

Às 12:34 PM de 5/8/2017, Andy Shevchenko escreveu: > On Mon, May 8, 2017 at 1:42 PM, Joao Pinto <joao.pi...@synopsys.com> wrote: >> Às 11:12 AM de 5/8/2017, Andy Shevchenko escreveu: >>> On Mon, May 8, 2017 at 12:54 PM, Joao Pinto <joao.pi...@synopsys.com> wrote: >

Re: [PATCH v3 net-next 01/11] net: stmmac: prepare dma op mode config for multiple queues

Às 12:34 PM de 5/8/2017, Andy Shevchenko escreveu: > On Mon, May 8, 2017 at 1:42 PM, Joao Pinto wrote: >> Às 11:12 AM de 5/8/2017, Andy Shevchenko escreveu: >>> On Mon, May 8, 2017 at 12:54 PM, Joao Pinto wrote: >>>> Às 10:36 AM de 5/8/2017, Andy Shevchenko escreve

Re: [PATCH v3 net-next 01/11] net: stmmac: prepare dma op mode config for multiple queues

Às 11:12 AM de 5/8/2017, Andy Shevchenko escreveu: > On Mon, May 8, 2017 at 12:54 PM, Joao Pinto <joao.pi...@synopsys.com> wrote: >> Hi Andy and Jan, >> >> Às 10:36 AM de 5/8/2017, Andy Shevchenko escreveu: >>> On Mon, May 8, 2017 at 9:56 AM, Jan Kiszka <jan.

Re: [PATCH v3 net-next 01/11] net: stmmac: prepare dma op mode config for multiple queues

Às 11:12 AM de 5/8/2017, Andy Shevchenko escreveu: > On Mon, May 8, 2017 at 12:54 PM, Joao Pinto wrote: >> Hi Andy and Jan, >> >> Às 10:36 AM de 5/8/2017, Andy Shevchenko escreveu: >>> On Mon, May 8, 2017 at 9:56 AM, Jan Kiszka wrote: >>>> On 2017-03-15

Re: [PATCH v3 net-next 01/11] net: stmmac: prepare dma op mode config for multiple queues

Hi Andy and Jan, Às 10:36 AM de 5/8/2017, Andy Shevchenko escreveu: > On Mon, May 8, 2017 at 9:56 AM, Jan Kiszka <jan.kis...@siemens.com> wrote: >> On 2017-03-15 12:04, Joao Pinto wrote: >>> This patch prepares DMA Operation Mode configuration for multiple queues

Re: [PATCH v3 net-next 01/11] net: stmmac: prepare dma op mode config for multiple queues

Hi Andy and Jan, Às 10:36 AM de 5/8/2017, Andy Shevchenko escreveu: > On Mon, May 8, 2017 at 9:56 AM, Jan Kiszka wrote: >> On 2017-03-15 12:04, Joao Pinto wrote: >>> This patch prepares DMA Operation Mode configuration for multiple queues. >>> The work consisted on

Re: [PATCH net-next v3] bindings: net: stmmac: add missing note about LPI interrupt

= <0xe080 0x8000>; > interrupt-parent = <>; > - interrupts = <24 23>; > - interrupt-names = "macirq", "eth_wake_irq"; > + interrupts = <24 23 22>; > + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; > mac-address = []; /* Filled in by U-Boot */ > max-frame-size = <3800>; > phy-mode = "gmii"; > Acked-By: Joao Pinto <jpi...@synopsys.com> Regards!

Re: [PATCH net-next v3] bindings: net: stmmac: add missing note about LPI interrupt

pt-parent = <>; > - interrupts = <24 23>; > - interrupt-names = "macirq", "eth_wake_irq"; > + interrupts = <24 23 22>; > + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; > mac-address = []; /* Filled in by U-Boot */ > max-frame-size = <3800>; > phy-mode = "gmii"; > Acked-By: Joao Pinto Regards!

Re: [PATCH net-next] net: stmmac: set total length of the packet to be transmitted in TDES3

Hi Niklas, Às 7:33 PM de 4/10/2017, Niklas Cassel escreveu: > From: Niklas Cassel > > Field FL/TPL in register TDES3 is not correctly set on GMAC4. > TX appears to be functional on GMAC 4.10a even if this field is not set, > however, to avoid relying on undefined

Re: [PATCH net-next] net: stmmac: set total length of the packet to be transmitted in TDES3

Hi Niklas, Às 7:33 PM de 4/10/2017, Niklas Cassel escreveu: > From: Niklas Cassel > > Field FL/TPL in register TDES3 is not correctly set on GMAC4. > TX appears to be functional on GMAC 4.10a even if this field is not set, > however, to avoid relying on undefined behavior, set the length in

Re: [PATCH] [net-next] stmmac: use netif_set_real_num_{rx,tx}_queues

Hello Peppe, Às 2:07 PM de 4/3/2017, Giuseppe CAVALLARO escreveu: > Hello Joao > > On 3/30/2017 6:42 PM, Joao Pinto wrote: >> Às 5:35 PM de 3/30/2017, Niklas Cassel escreveu: >>> On 03/30/2017 04:34 PM, Thierry Reding wrote: >>>> On Thu, Mar 30, 2017 at 09

Re: [PATCH] [net-next] stmmac: use netif_set_real_num_{rx,tx}_queues

Hello Peppe, Às 2:07 PM de 4/3/2017, Giuseppe CAVALLARO escreveu: > Hello Joao > > On 3/30/2017 6:42 PM, Joao Pinto wrote: >> Às 5:35 PM de 3/30/2017, Niklas Cassel escreveu: >>> On 03/30/2017 04:34 PM, Thierry Reding wrote: >>>> On Thu, Mar 30, 2017 at 09

Re: [PATCH] [net-next] stmmac: use netif_set_real_num_{rx,tx}_queues

Às 5:57 PM de 3/31/2017, David Miller escreveu: > From: Joao Pinto <joao.pi...@synopsys.com> > Date: Fri, 31 Mar 2017 11:43:38 +0100 > >> @David: Could you please create a branch in your git tree for us to work on >> it >> until the multiple buffers get stable f

Re: [PATCH] [net-next] stmmac: use netif_set_real_num_{rx,tx}_queues

Às 5:57 PM de 3/31/2017, David Miller escreveu: > From: Joao Pinto > Date: Fri, 31 Mar 2017 11:43:38 +0100 > >> @David: Could you please create a branch in your git tree for us to work on >> it >> until the multiple buffers get stable for everyone? This way the pat

[PATCH] net: stmmac: fix cbs configuration

The QoS IP does not accept AVB capabilities to default/queue 0, this way we guarantee 75% bandwidth for AVB. This patch assures that only queues >= 1 gets CBS confgured. Additional info was also added to stmmac.txt. Reported-by: Niklas Cassel <niklas.cas...@axis.com> Signed-off-by: J

[PATCH] net: stmmac: fix cbs configuration

The QoS IP does not accept AVB capabilities to default/queue 0, this way we guarantee 75% bandwidth for AVB. This patch assures that only queues >= 1 gets CBS confgured. Additional info was also added to stmmac.txt. Reported-by: Niklas Cassel Signed-off-by: Joao Pinto --- Documentat

Re: [PATCH] [net-next] stmmac: use netif_set_real_num_{rx,tx}_queues

Às 11:14 AM de 3/31/2017, Joao Pinto escreveu: > Às 6:48 PM de 3/30/2017, David Miller escreveu: >> From: Thierry Reding <tred...@nvidia.com> >> Date: Thu, 30 Mar 2017 16:34:36 +0200 >> >>> On Thu, Mar 30, 2017 at 09:45:36AM +0200, Corentin Labbe wrote: >

Re: [PATCH] [net-next] stmmac: use netif_set_real_num_{rx,tx}_queues

Às 11:14 AM de 3/31/2017, Joao Pinto escreveu: > Às 6:48 PM de 3/30/2017, David Miller escreveu: >> From: Thierry Reding >> Date: Thu, 30 Mar 2017 16:34:36 +0200 >> >>> On Thu, Mar 30, 2017 at 09:45:36AM +0200, Corentin Labbe wrote: >>>> On Tue, Mar

Re: [PATCH] [net-next] stmmac: use netif_set_real_num_{rx,tx}_queues

Às 6:48 PM de 3/30/2017, David Miller escreveu: > From: Thierry Reding > Date: Thu, 30 Mar 2017 16:34:36 +0200 > >> On Thu, Mar 30, 2017 at 09:45:36AM +0200, Corentin Labbe wrote: >>> On Tue, Mar 28, 2017 at 06:01:05PM -0700, David Miller wrote: From: Arnd Bergmann

Re: [PATCH] [net-next] stmmac: use netif_set_real_num_{rx,tx}_queues

Às 6:48 PM de 3/30/2017, David Miller escreveu: > From: Thierry Reding > Date: Thu, 30 Mar 2017 16:34:36 +0200 > >> On Thu, Mar 30, 2017 at 09:45:36AM +0200, Corentin Labbe wrote: >>> On Tue, Mar 28, 2017 at 06:01:05PM -0700, David Miller wrote: From: Arnd Bergmann Date: Tue, 28 Mar

Re: [PATCH] [net-next] stmmac: use netif_set_real_num_{rx,tx}_queues

Às 5:35 PM de 3/30/2017, Niklas Cassel escreveu: > On 03/30/2017 04:34 PM, Thierry Reding wrote: >> On Thu, Mar 30, 2017 at 09:45:36AM +0200, Corentin Labbe wrote: >>> On Tue, Mar 28, 2017 at 06:01:05PM -0700, David Miller wrote: From: Arnd Bergmann Date: Tue, 28 Mar 2017

Re: [PATCH] [net-next] stmmac: use netif_set_real_num_{rx,tx}_queues

Às 5:35 PM de 3/30/2017, Niklas Cassel escreveu: > On 03/30/2017 04:34 PM, Thierry Reding wrote: >> On Thu, Mar 30, 2017 at 09:45:36AM +0200, Corentin Labbe wrote: >>> On Tue, Mar 28, 2017 at 06:01:05PM -0700, David Miller wrote: From: Arnd Bergmann Date: Tue, 28 Mar 2017 11:48:21 +0200

Re: [PATCH] PCI: dwc: fix crash seen due to missing ops

Às 7:19 AM de 3/23/2017, Niklas Cassel escreveu: > On 03/22/2017 04:47 PM, Joao Pinto wrote: >> Hi Niklas, >> >> Às 2:43 PM de 3/21/2017, Niklas Cassel escreveu: >>> From: Niklas Cassel <niklas.cas...@axis.com> >>> >>> Fix the following crash

Re: [PATCH] PCI: dwc: fix crash seen due to missing ops

Às 7:19 AM de 3/23/2017, Niklas Cassel escreveu: > On 03/22/2017 04:47 PM, Joao Pinto wrote: >> Hi Niklas, >> >> Às 2:43 PM de 3/21/2017, Niklas Cassel escreveu: >>> From: Niklas Cassel >>> >>> Fix the following crash, seen in dwc/pcie-artpec6

Re: stmmac: Performance regression after commit aff3d9eff843 "net: stmmac: enable multiple buffers"

Às 10:56 AM de 3/23/2017, Joao Pinto escreveu: > Às 10:51 AM de 3/23/2017, Giuseppe CAVALLARO escreveu: >> On 3/23/2017 11:48 AM, Giuseppe CAVALLARO wrote: >>> Hello >>> >>> On 3/23/2017 11:20 AM, Corentin Labbe wrote: >>>>> I have a 4.21 Q

Re: stmmac: Performance regression after commit aff3d9eff843 "net: stmmac: enable multiple buffers"

Às 10:56 AM de 3/23/2017, Joao Pinto escreveu: > Às 10:51 AM de 3/23/2017, Giuseppe CAVALLARO escreveu: >> On 3/23/2017 11:48 AM, Giuseppe CAVALLARO wrote: >>> Hello >>> >>> On 3/23/2017 11:20 AM, Corentin Labbe wrote: >>>>> I have a 4.21 Q

Re: stmmac: Performance regression after commit aff3d9eff843 "net: stmmac: enable multiple buffers"

Às 10:51 AM de 3/23/2017, Giuseppe CAVALLARO escreveu: > On 3/23/2017 11:48 AM, Giuseppe CAVALLARO wrote: >> Hello >> >> On 3/23/2017 11:20 AM, Corentin Labbe wrote: I have a 4.21 QoS Core with 4 RX + 4 TX and detected no regression. >Could you please share the iperf cmds you are using

Re: stmmac: Performance regression after commit aff3d9eff843 "net: stmmac: enable multiple buffers"

Às 10:51 AM de 3/23/2017, Giuseppe CAVALLARO escreveu: > On 3/23/2017 11:48 AM, Giuseppe CAVALLARO wrote: >> Hello >> >> On 3/23/2017 11:20 AM, Corentin Labbe wrote: I have a 4.21 QoS Core with 4 RX + 4 TX and detected no regression. >Could you please share the iperf cmds you are using

Re: stmmac: Performance regression after commit aff3d9eff843 "net: stmmac: enable multiple buffers"

Hi Peppe, Às 10:48 AM de 3/23/2017, Giuseppe CAVALLARO escreveu: > Hello > > On 3/23/2017 11:20 AM, Corentin Labbe wrote: >>> I have a 4.21 QoS Core with 4 RX + 4 TX and detected no regression. >>> >Could you please share the iperf cmds you are using in order for me to >>> reproduce >>> >in my

Re: stmmac: Performance regression after commit aff3d9eff843 "net: stmmac: enable multiple buffers"

Hi Peppe, Às 10:48 AM de 3/23/2017, Giuseppe CAVALLARO escreveu: > Hello > > On 3/23/2017 11:20 AM, Corentin Labbe wrote: >>> I have a 4.21 QoS Core with 4 RX + 4 TX and detected no regression. >>> >Could you please share the iperf cmds you are using in order for me to >>> reproduce >>> >in my

Re: stmmac: Performance regression after commit aff3d9eff843 "net: stmmac: enable multiple buffers"

Às 10:20 AM de 3/23/2017, Corentin Labbe escreveu: > On Thu, Mar 23, 2017 at 10:12:18AM +0000, Joao Pinto wrote: >> >> Hi Corentin, >> >> Às 10:08 AM de 3/23/2017, Corentin Labbe escreveu: >>> Hello >>> >>> Using next-20170323 produce

Re: stmmac: Performance regression after commit aff3d9eff843 "net: stmmac: enable multiple buffers"

Às 10:20 AM de 3/23/2017, Corentin Labbe escreveu: > On Thu, Mar 23, 2017 at 10:12:18AM +0000, Joao Pinto wrote: >> >> Hi Corentin, >> >> Às 10:08 AM de 3/23/2017, Corentin Labbe escreveu: >>> Hello >>> >>> Using next-20170323 produce

Re: stmmac: Performance regression after commit aff3d9eff843 "net: stmmac: enable multiple buffers"

Hi Corentin, Às 10:08 AM de 3/23/2017, Corentin Labbe escreveu: > Hello > > Using next-20170323 produce a huge performance regression on my sunxi boards. > On dwmac-sun8i, iperf goes from 94mbs/s to 37 when sending. > > On cubieboard2(dwmac-sunxi), iperf made the kernel flood with >

Re: stmmac: Performance regression after commit aff3d9eff843 "net: stmmac: enable multiple buffers"

Hi Corentin, Às 10:08 AM de 3/23/2017, Corentin Labbe escreveu: > Hello > > Using next-20170323 produce a huge performance regression on my sunxi boards. > On dwmac-sun8i, iperf goes from 94mbs/s to 37 when sending. > > On cubieboard2(dwmac-sunxi), iperf made the kernel flood with >

Re: [PATCH] PCI: dwc: fix crash seen due to missing ops

Hi Niklas, Às 2:43 PM de 3/21/2017, Niklas Cassel escreveu: > From: Niklas Cassel > > Fix the following crash, seen in dwc/pcie-artpec6. > > Unable to handle kernel NULL pointer dereference at virtual address 0004 > pgd = c0204000 > [0004] *pgd= >

Re: [PATCH] PCI: dwc: fix crash seen due to missing ops

Hi Niklas, Às 2:43 PM de 3/21/2017, Niklas Cassel escreveu: > From: Niklas Cassel > > Fix the following crash, seen in dwc/pcie-artpec6. > > Unable to handle kernel NULL pointer dereference at virtual address 0004 > pgd = c0204000 > [0004] *pgd= > Internal error: Oops:

Re: [PATCH 3/3] net: stmmac: Use AVB mode by default

Às 4:50 PM de 3/21/2017, Joao Pinto escreveu: > Às 4:42 PM de 3/21/2017, Thierry Reding escreveu: >> On Tue, Mar 21, 2017 at 03:23:00PM +0000, Joao Pinto wrote: >>> Às 3:12 PM de 3/21/2017, Thierry Reding escreveu: >>>> From: Thierry Reding <tred...@nvidia.com>

Re: [PATCH 3/3] net: stmmac: Use AVB mode by default

Às 4:50 PM de 3/21/2017, Joao Pinto escreveu: > Às 4:42 PM de 3/21/2017, Thierry Reding escreveu: >> On Tue, Mar 21, 2017 at 03:23:00PM +0000, Joao Pinto wrote: >>> Às 3:12 PM de 3/21/2017, Thierry Reding escreveu: >>>> From: Thierry Reding >>>> &g

Re: [PATCH 3/3] net: stmmac: Use AVB mode by default

Às 4:42 PM de 3/21/2017, Thierry Reding escreveu: > On Tue, Mar 21, 2017 at 03:23:00PM +0000, Joao Pinto wrote: >> Às 3:12 PM de 3/21/2017, Thierry Reding escreveu: >>> From: Thierry Reding <tred...@nvidia.com> >>> >>> Prior to the recent mult

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