Re: [PATCH] MIPS: ralink: define stubs for clk_set_parent to fix compile testing

[John Crispin]

On 16.03.21 18:57, Krzysztof Kozlowski wrote:

The Ralink MIPS platform does not use Common Clock Framework and does
not define certain clock operations leading to compile test failures:

 /usr/bin/mips-linux-gnu-ld: drivers/usb/phy/phy-tegra-usb.o: in function 
`tegra_usb_phy_init':
 phy-tegra-usb.c:(.text+0x1dd4): undefined reference to `clk_get_parent'

Reported-by: kernel test robot 
Signed-off-by: Krzysztof Kozlowski 

Acked-by John Crispin 

---
  arch/mips/ralink/clk.c | 14 ++
  1 file changed, 14 insertions(+)

diff --git a/arch/mips/ralink/clk.c b/arch/mips/ralink/clk.c
index 2f9d5acb38ea..8387177a47ef 100644
--- a/arch/mips/ralink/clk.c
+++ b/arch/mips/ralink/clk.c
@@ -70,6 +70,20 @@ long clk_round_rate(struct clk *clk, unsigned long rate)
  }
  EXPORT_SYMBOL_GPL(clk_round_rate);
  
+int clk_set_parent(struct clk *clk, struct clk *parent)

+{
+   WARN_ON(clk);
+   return -1;
+}
+EXPORT_SYMBOL(clk_set_parent);
+
+struct clk *clk_get_parent(struct clk *clk)
+{
+   WARN_ON(clk);
+   return NULL;
+}
+EXPORT_SYMBOL(clk_get_parent);
+
  void __init plat_time_init(void)
  {
struct clk *clk;

Re: [PATCH v4 2/2] irqchip: Add support for Realtek RTL838x/RTL839x interrupt controller

[John Crispin]

On 22.01.21 21:42, Bert Vermeulen wrote:

This is a standard IRQ driver with only status and mask registers.

The mapping from SoC interrupts (18-31) to MIPS core interrupts is
done via an interrupt-map in device tree.

Signed-off-by: Bert Vermeulen 
Signed-off-by: Birger Koblitz 


Acked-by: John Crispin 

Thanks !


---
  drivers/irqchip/Makefile  |   1 +
  drivers/irqchip/irq-realtek-rtl.c | 180 ++
  2 files changed, 181 insertions(+)
  create mode 100644 drivers/irqchip/irq-realtek-rtl.c

diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 0ac93bfaec61..4fc1086bed7e 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -113,3 +113,4 @@ obj-$(CONFIG_LOONGSON_PCH_PIC)  += 
irq-loongson-pch-pic.o
  obj-$(CONFIG_LOONGSON_PCH_MSI)+= irq-loongson-pch-msi.o
  obj-$(CONFIG_MST_IRQ) += irq-mst-intc.o
  obj-$(CONFIG_SL28CPLD_INTC)   += irq-sl28cpld.o
+obj-$(CONFIG_MACH_REALTEK_RTL) += irq-realtek-rtl.o
diff --git a/drivers/irqchip/irq-realtek-rtl.c 
b/drivers/irqchip/irq-realtek-rtl.c
new file mode 100644
index ..b57c67dfab5b
--- /dev/null
+++ b/drivers/irqchip/irq-realtek-rtl.c
@@ -0,0 +1,180 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2020 Birger Koblitz 
+ * Copyright (C) 2020 Bert Vermeulen 
+ * Copyright (C) 2020 John Crispin 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* Global Interrupt Mask Register */
+#define RTL_ICTL_GIMR  0x00
+/* Global Interrupt Status Register */
+#define RTL_ICTL_GISR  0x04
+/* Interrupt Routing Registers */
+#define RTL_ICTL_IRR0  0x08
+#define RTL_ICTL_IRR1  0x0c
+#define RTL_ICTL_IRR2  0x10
+#define RTL_ICTL_IRR3  0x14
+
+#define REG(x) (realtek_ictl_base + x)
+
+static DEFINE_RAW_SPINLOCK(irq_lock);
+static void __iomem *realtek_ictl_base;
+
+static void realtek_ictl_unmask_irq(struct irq_data *i)
+{
+   unsigned long flags;
+   u32 value;
+
+   raw_spin_lock_irqsave(_lock, flags);
+
+   value = readl(REG(RTL_ICTL_GIMR));
+   value |= BIT(i->hwirq);
+   writel(value, REG(RTL_ICTL_GIMR));
+
+   raw_spin_unlock_irqrestore(_lock, flags);
+}
+
+static void realtek_ictl_mask_irq(struct irq_data *i)
+{
+   unsigned long flags;
+   u32 value;
+
+   raw_spin_lock_irqsave(_lock, flags);
+
+   value = readl(REG(RTL_ICTL_GIMR));
+   value &= ~BIT(i->hwirq);
+   writel(value, REG(RTL_ICTL_GIMR));
+
+   raw_spin_unlock_irqrestore(_lock, flags);
+}
+
+static struct irq_chip realtek_ictl_irq = {
+   .name = "realtek-rtl-intc",
+   .irq_mask = realtek_ictl_mask_irq,
+   .irq_unmask = realtek_ictl_unmask_irq,
+};
+
+static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
+{
+   irq_set_chip_and_handler(hw, _ictl_irq, handle_level_irq);
+
+   return 0;
+}
+
+static const struct irq_domain_ops irq_domain_ops = {
+   .map = intc_map,
+   .xlate = irq_domain_xlate_onecell,
+};
+
+static void realtek_irq_dispatch(struct irq_desc *desc)
+{
+   struct irq_chip *chip = irq_desc_get_chip(desc);
+   struct irq_domain *domain;
+   unsigned int pending;
+
+   chained_irq_enter(chip, desc);
+   pending = readl(REG(RTL_ICTL_GIMR)) & readl(REG(RTL_ICTL_GISR));
+   if (unlikely(!pending)) {
+   spurious_interrupt();
+   goto out;
+   }
+   domain = irq_desc_get_handler_data(desc);
+   generic_handle_irq(irq_find_mapping(domain, __ffs(pending)));
+
+out:
+   chained_irq_exit(chip, desc);
+}
+
+/*
+ * SoC interrupts are cascaded to MIPS CPU interrupts according to the
+ * interrupt-map in the device tree. Each SoC interrupt gets 4 bits for
+ * the CPU interrupt in an Interrupt Routing Register. Max 32 SoC interrupts
+ * thus go into 4 IRRs.
+ */
+static int __init map_interrupts(struct device_node *node, struct irq_domain 
*domain)
+{
+   struct device_node *cpu_ictl;
+   const __be32 *imap;
+   u32 imaplen, soc_int, cpu_int, tmp, regs[4];
+   int ret, i, irr_regs[] = {
+   RTL_ICTL_IRR3,
+   RTL_ICTL_IRR2,
+   RTL_ICTL_IRR1,
+   RTL_ICTL_IRR0,
+   };
+   u8 mips_irqs_set;
+
+   ret = of_property_read_u32(node, "#address-cells", );
+   if (ret || tmp)
+   return -EINVAL;
+
+   imap = of_get_property(node, "interrupt-map", );
+   if (!imap || imaplen % 3)
+   return -EINVAL;
+
+   mips_irqs_set = 0;
+   memset(regs, 0, sizeof(regs));
+   for (i = 0; i < imaplen; i += 3 * sizeof(u32)) {
+   soc_int = be32_to_cpup(imap);
+   if (soc_int > 31)
+   return -EINVAL;
+
+   cpu_ictl = of_find_node_by_phandle(be32_to_cpup(imap + 1));
+   if (!cpu_ictl)
+

Re: [PATCH] MIPS: ralink: manage low reset lines

[John Crispin]

On 03.02.21 10:21, Sander Vanheule wrote:

Reset lines with indices smaller than 8 are currently considered invalid
by the rt2880-reset reset controller.

The MT7621 SoC uses a number of these low reset lines. The DTS defines
reset lines "hsdma", "fe", and "mcm" with respective values 5, 6, and 2.
As a result of the above restriction, these resets cannot be asserted or
de-asserted by the reset controller. In cases where the bootloader does
not de-assert these lines, this results in e.g. the MT7621's internal
switch staying in reset.

Change the reset controller to only ignore the system reset, so all
reset lines with index greater than 0 are considered valid.

Signed-off-by: Sander Vanheule 

Acked-by: John Crispin 

---
This patch was tested on a TP-Link EAP235-Wall, with an MT7621DA SoC.
The bootloader on this device would leave reset line 2 ("mcm") asserted,
which caused the internal switch to be unresponsive on an uninterrupted
boot from flash.

When tftpboot was used in the bootloader to load an initramfs, it did
initialise the internal switch, and cleared the mcm reset line. In this
case the switch could be used from the OS. With this patch applied, the
switch works both in an initramfs, and when (cold) booting from flash.

  arch/mips/ralink/reset.c | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/mips/ralink/reset.c b/arch/mips/ralink/reset.c
index 8126f1260407..274d33078c5e 100644
--- a/arch/mips/ralink/reset.c
+++ b/arch/mips/ralink/reset.c
@@ -27,7 +27,7 @@ static int ralink_assert_device(struct reset_controller_dev 
*rcdev,
  {
u32 val;
  
-	if (id < 8)

+   if (id == 0)
return -1;
  
  	val = rt_sysc_r32(SYSC_REG_RESET_CTRL);

@@ -42,7 +42,7 @@ static int ralink_deassert_device(struct reset_controller_dev 
*rcdev,
  {
u32 val;
  
-	if (id < 8)

+   if (id == 0)
return -1;
  
  	val = rt_sysc_r32(SYSC_REG_RESET_CTRL);

Re: [PATCH v2 2/2] irqchip: Add support for Realtek RTL838x/RTL839x IRQ controller

[John Crispin]

On 04.01.21 14:17, Bert Vermeulen wrote:

This is a standard IRQ driver with only status and mask registers.

The mapping from SoC interrupts (18-31) to MIPS core interrupts is
done via an interrupt-map in device tree.

Signed-off-by: Bert Vermeulen 

Signed-off-by: John Crispin 

---
  drivers/irqchip/Makefile  |   1 +
  drivers/irqchip/irq-realtek-rtl.c | 180 ++
  2 files changed, 181 insertions(+)
  create mode 100644 drivers/irqchip/irq-realtek-rtl.c

diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 0ac93bfaec61..4fc1086bed7e 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -113,3 +113,4 @@ obj-$(CONFIG_LOONGSON_PCH_PIC)  += 
irq-loongson-pch-pic.o
  obj-$(CONFIG_LOONGSON_PCH_MSI)+= irq-loongson-pch-msi.o
  obj-$(CONFIG_MST_IRQ) += irq-mst-intc.o
  obj-$(CONFIG_SL28CPLD_INTC)   += irq-sl28cpld.o
+obj-$(CONFIG_MACH_REALTEK_RTL) += irq-realtek-rtl.o
diff --git a/drivers/irqchip/irq-realtek-rtl.c 
b/drivers/irqchip/irq-realtek-rtl.c
new file mode 100644
index ..bafe9ee4a85a
--- /dev/null
+++ b/drivers/irqchip/irq-realtek-rtl.c
@@ -0,0 +1,180 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2006-2012 Tony Wu 
+ * Copyright (C) 2020 Birger Koblitz 
+ * Copyright (C) 2020 Bert Vermeulen 
+ * Copyright (C) 2020 John Crispin 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* Global Interrupt Mask Register */
+#define RTL_ICTL_GIMR  0x00
+/* Global Interrupt Status Register */
+#define RTL_ICTL_GISR  0x04
+/* Interrupt Routing Registers */
+#define RTL_ICTL_IRR0  0x08
+#define RTL_ICTL_IRR1  0x0c
+#define RTL_ICTL_IRR2  0x10
+#define RTL_ICTL_IRR3  0x14
+
+#define REG(x) (realtek_ictl_base + x)
+
+static DEFINE_RAW_SPINLOCK(irq_lock);
+static void __iomem *realtek_ictl_base;
+
+static void realtek_ictl_unmask_irq(struct irq_data *i)
+{
+   unsigned long flags;
+   u32 value;
+
+   raw_spin_lock_irqsave(_lock, flags);
+
+   value = readl(REG(RTL_ICTL_GIMR));
+   value |= BIT(i->hwirq);
+   writel(value, REG(RTL_ICTL_GIMR));
+
+   raw_spin_unlock_irqrestore(_lock, flags);
+}
+
+static void realtek_ictl_mask_irq(struct irq_data *i)
+{
+   unsigned long flags;
+   u32 value;
+
+   raw_spin_lock_irqsave(_lock, flags);
+
+   value = readl(REG(RTL_ICTL_GIMR));
+   value &= ~BIT(i->hwirq);
+   writel(value, REG(RTL_ICTL_GIMR));
+
+   raw_spin_unlock_irqrestore(_lock, flags);
+}
+
+static struct irq_chip realtek_ictl_irq = {
+   .name = "realtek-rtl-intc",
+   .irq_mask = realtek_ictl_mask_irq,
+   .irq_unmask = realtek_ictl_unmask_irq,
+};
+
+static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
+{
+   irq_set_chip_and_handler(hw, _ictl_irq, handle_level_irq);
+
+   return 0;
+}
+
+static const struct irq_domain_ops irq_domain_ops = {
+   .map = intc_map,
+   .xlate = irq_domain_xlate_onecell,
+};
+
+static void realtek_irq_dispatch(struct irq_desc *desc)
+{
+   struct irq_chip *chip = irq_desc_get_chip(desc);
+   struct irq_domain *domain;
+   unsigned int pending;
+
+   chained_irq_enter(chip, desc);
+   pending = readl(REG(RTL_ICTL_GIMR)) & readl(REG(RTL_ICTL_GISR));
+   if (unlikely(!pending)) {
+   spurious_interrupt();
+   goto out;
+   }
+   domain = irq_desc_get_handler_data(desc);
+   generic_handle_irq(irq_find_mapping(domain, __ffs(pending)));
+
+out:
+   chained_irq_exit(chip, desc);
+}
+
+/*
+ * SoC interrupts are cascaded to MIPS CPU interrupts according to the
+ * interrupt-map in the device tree. Each SoC interrupt gets 4 bits for
+ * the CPU interrupt in an Interrupt Routing Register. Max 32 SoC interrupts
+ * thus go into 4 IRRs.
+ */
+static int __init map_interrupts(struct device_node *node)
+{
+   struct device_node *cpu_ictl;
+   const __be32 *imap;
+   u32 imaplen, soc_int, cpu_int, tmp, regs[4];
+   int ret, i, irr_regs[] = {
+   RTL_ICTL_IRR3,
+   RTL_ICTL_IRR2,
+   RTL_ICTL_IRR1,
+   RTL_ICTL_IRR0,
+   };
+
+   ret = of_property_read_u32(node, "#address-cells", );
+   if (ret || tmp)
+   return -EINVAL;
+
+   imap = of_get_property(node, "interrupt-map", );
+   if (!imap || imaplen % 3)
+   return -EINVAL;
+
+   memset(regs, 0, sizeof(regs));
+   for (i = 0; i < imaplen; i += 3 * sizeof(u32)) {
+   soc_int = be32_to_cpup(imap);
+   if (soc_int > 31)
+   return -EINVAL;
+
+   cpu_ictl = of_find_node_by_phandle(be32_to_cpup(imap + 1));
+   if (!cpu_ictl)
+   return -EINVAL;
+   ret = of_property_read_u32(cpu_ictl, &qu

[PATCH V4 1/4] nl80211: add basic multiple bssid support

[John Crispin]

This patch adds support for passing the multiple bssid config to the
kernel when adding an AP gets started. If the BSS is non-transmitting we
need to pass the ifidx of the transmitting parent. The multiple bssid
elements are passed as an array inside the beacon data. This allows use to
generate multiple bssid beacons aswell as EMA ones.

Signed-off-by: Aloka Dixit 
Signed-off-by: John Crispin 
---
 include/net/cfg80211.h   | 33 +
 include/uapi/linux/nl80211.h | 21 +
 net/wireless/nl80211.c   | 34 ++
 3 files changed, 88 insertions(+)

diff --git a/include/net/cfg80211.h b/include/net/cfg80211.h
index aee47f2b5709..20782e9c5aaa 100644
--- a/include/net/cfg80211.h
+++ b/include/net/cfg80211.h
@@ -496,6 +496,21 @@ struct ieee80211_supported_band {
const struct ieee80211_sband_iftype_data *iftype_data;
 };
 
+/**
+ * struct ieee80211_multiple_bssid - AP settings for multi bssid
+ *
+ * @index: the index of this AP in the multi bssid group.
+ * @count: the total number of multi bssid peer APs.
+ * @parent: non-transmitted BSSs transmitted parents index
+ * @ema: Shall the beacons be sent out in EMA mode.
+ */
+struct ieee80211_multiple_bssid {
+   u8 index;
+   u8 count;
+   u32 parent;
+   bool ema;
+};
+
 /**
  * ieee80211_get_sband_iftype_data - return sband data for a given iftype
  * @sband: the sband to search for the STA on
@@ -1027,6 +1042,19 @@ struct cfg80211_crypto_settings {
u8 sae_pwd_len;
 };
 
+/**
+ * struct cfg80211_multiple_bssid_data - multiple_bssid data
+ * @ies: array of extra information element(s) to add into Beacon frames for 
multiple
+ * bssid or %NULL
+ * @len: array of lengths of multiple_bssid.ies in octets
+ * @cnt: number of entries in multiple_bssid.ies
+ */
+struct cfg80211_multiple_bssid_data {
+   u8 *ies[NL80211_MULTIPLE_BSSID_IES_MAX];
+   size_t len[NL80211_MULTIPLE_BSSID_IES_MAX];
+   int cnt;
+};
+
 /**
  * struct cfg80211_beacon_data - beacon data
  * @head: head portion of beacon (before TIM IE)
@@ -1053,6 +1081,7 @@ struct cfg80211_crypto_settings {
  * Token (measurement type 11)
  * @lci_len: LCI data length
  * @civicloc_len: Civic location data length
+ * @multiple_bssid: multiple_bssid data
  */
 struct cfg80211_beacon_data {
const u8 *head, *tail;
@@ -1071,6 +1100,8 @@ struct cfg80211_beacon_data {
size_t probe_resp_len;
size_t lci_len;
size_t civicloc_len;
+
+   struct cfg80211_multiple_bssid_data multiple_bssid;
 };
 
 struct mac_address {
@@ -1175,6 +1206,7 @@ enum cfg80211_ap_settings_flags {
  * @he_oper: HE operation IE (or %NULL if HE isn't enabled)
  * @fils_discovery: FILS discovery transmission parameters
  * @unsol_bcast_probe_resp: Unsolicited broadcast probe response parameters
+ * @multiple_bssid: AP settings for multiple bssid
  */
 struct cfg80211_ap_settings {
struct cfg80211_chan_def chandef;
@@ -1207,6 +1239,7 @@ struct cfg80211_ap_settings {
struct cfg80211_he_bss_color he_bss_color;
struct cfg80211_fils_discovery fils_discovery;
struct cfg80211_unsol_bcast_probe_resp unsol_bcast_probe_resp;
+   struct ieee80211_multiple_bssid multiple_bssid;
 };
 
 /**
diff --git a/include/uapi/linux/nl80211.h b/include/uapi/linux/nl80211.h
index 47700a2b9af9..91b338b0b9cb 100644
--- a/include/uapi/linux/nl80211.h
+++ b/include/uapi/linux/nl80211.h
@@ -2527,6 +2527,19 @@ enum nl80211_commands {
  * override mask. Used with NL80211_ATTR_S1G_CAPABILITY in
  * NL80211_CMD_ASSOCIATE or NL80211_CMD_CONNECT.
  *
+ * @NL80211_ATTR_MULTIPLE_BSSID_PARENT: If this is a Non-Transmitted BSSID, 
define
+ * the parent (transmitting) interface.
+ *
+ * @NL80211_ATTR_MULTIPLE_BSSID_INDEX: The index of this BSS inside the multi 
bssid
+ * element.
+ *
+ * @NL80211_ATTR_MULTIPLE_BSSID_COUNT: The number of BSSs inside the multi 
bssid element.
+ *
+ * @NL80211_ATTR_MULTIPLE_BSSID_IES: The Elements that describe our multiple 
BSS group.
+ * these get passed separately as the kernel might need to split them up 
for EMA VAP.
+ *
+ * @NL80211_ATTR_MULTIPLE_BSSID_EMA: Shall the multiple BSS beacons be sent 
out in EMA mode.
+ *
  * @NUM_NL80211_ATTR: total number of nl80211_attrs available
  * @NL80211_ATTR_MAX: highest attribute number currently defined
  * @__NL80211_ATTR_AFTER_LAST: internal use
@@ -3016,6 +3029,12 @@ enum nl80211_attrs {
NL80211_ATTR_S1G_CAPABILITY,
NL80211_ATTR_S1G_CAPABILITY_MASK,
 
+   NL80211_ATTR_MULTIPLE_BSSID_PARENT,
+   NL80211_ATTR_MULTIPLE_BSSID_INDEX,
+   NL80211_ATTR_MULTIPLE_BSSID_COUNT,
+   NL80211_ATTR_MULTIPLE_BSSID_IES,
+   NL80211_ATTR_MULTIPLE_BSSID_EMA,
+
/* add attributes here, update the policy in nl80211.c */
 
__NL80211_ATTR_AFTER_LAST,
@@ -3079,6 +3098,8 @@ enum nl80211_attrs {
 
 #define NL80211_CQM_TXE_MAX_INTVL  1800
 
+#define

[PATCH V4 2/4] mac80211: add multiple bssid support to interface handling

[John Crispin]

When bringing up multi bssid APs we need to track the parent-child relation
aswell as figuring out if the BSS is (non-)transmitting. The new helper
function ieee80211_set_multiple_bssid_options() takes care of storing the
config as well as figuring out the runtime flags of the virtual interface.

The patch also makes sure that when a parent is closed, its children are
also closed.

Signed-off-by: Aloka Dixit 
Signed-off-by: John Crispin 
---
 include/net/mac80211.h | 28 +-
 net/mac80211/cfg.c | 53 ++
 net/mac80211/debugfs.c |  1 +
 net/mac80211/iface.c   |  6 +
 4 files changed, 87 insertions(+), 1 deletion(-)

diff --git a/include/net/mac80211.h b/include/net/mac80211.h
index 4747d446179a..fef9c893f757 100644
--- a/include/net/mac80211.h
+++ b/include/net/mac80211.h
@@ -628,6 +628,7 @@ struct ieee80211_fils_discovery {
  * @unsol_bcast_probe_resp_interval: Unsolicited broadcast probe response
  * interval.
  * @s1g: BSS is S1G BSS (affects Association Request format).
+ * @multiple_bssid: the multiple bssid settings of the AP.
  */
 struct ieee80211_bss_conf {
const u8 *bssid;
@@ -698,6 +699,7 @@ struct ieee80211_bss_conf {
struct ieee80211_fils_discovery fils_discovery;
u32 unsol_bcast_probe_resp_interval;
bool s1g;
+   struct ieee80211_multiple_bssid multiple_bssid;
 };
 
 /**
@@ -1650,6 +1652,20 @@ enum ieee80211_offload_flags {
IEEE80211_OFFLOAD_ENCAP_4ADDR   = BIT(1),
 };
 
+/**
+ * enum ieee80211_vif_multiple_bssid_flags - virtual interface multiple bssid 
flags
+ *
+ * @IEEE80211_VIF_MBSS_TRANSMITTING: this BSS is transmitting beacons
+ * @IEEE80211_VIF_MBSS_NON_TRANSMITTING: this BSS is not transmitting beacons
+ * @IEEE80211_VIF_MBSS_EMA_BEACON: beacons should be send out in EMA mode
+ */
+
+enum ieee80211_vif_multiple_bssid_flags {
+   IEEE80211_VIF_MBSS_TRANSMITTING = BIT(1),
+   IEEE80211_VIF_MBSS_NON_TRANSMITTING = BIT(2),
+   IEEE80211_VIF_MBSS_EMA_BEACON   = BIT(3),
+};
+
 /**
  * struct ieee80211_vif - per-interface data
  *
@@ -1696,6 +1712,9 @@ enum ieee80211_offload_flags {
  * protected by fq->lock.
  * @offload_flags: 802.3 -> 802.11 enapsulation offload flags, see
  *  ieee80211_offload_flags.
+ * @multiple_bssid.parent: a non-transmitted bssid has a transmitted parent.
+ * @multiple_bssid.flags: multiple bssid flags, see
+ *  ieee80211_vif_multiple_bssid_flags
  */
 struct ieee80211_vif {
enum nl80211_iftype type;
@@ -1723,6 +1742,10 @@ struct ieee80211_vif {
bool rx_mcast_action_reg;
 
bool txqs_stopped[IEEE80211_NUM_ACS];
+   struct {
+   struct ieee80211_vif *parent;
+   u32 flags;
+   } multiple_bssid;
 
/* must be last */
u8 drv_priv[] __aligned(sizeof(void *));
@@ -2371,7 +2394,7 @@ struct ieee80211_txq {
  * @IEEE80211_HW_TX_STATUS_NO_AMPDU_LEN: Driver does not report accurate A-MPDU
  * length in tx status information
  *
- * @IEEE80211_HW_SUPPORTS_MULTI_BSSID: Hardware supports multi BSSID
+ * @IEEE80211_HW_SUPPORTS_MULTI_BSSID: Hardware supports multi BSSID in STA 
mode
  *
  * @IEEE80211_HW_SUPPORTS_ONLY_HE_MULTI_BSSID: Hardware supports multi BSSID
  * only for HE APs. Applies if @IEEE80211_HW_SUPPORTS_MULTI_BSSID is set.
@@ -2383,6 +2406,8 @@ struct ieee80211_txq {
  * @IEEE80211_HW_SUPPORTS_TX_ENCAP_OFFLOAD: Hardware supports tx encapsulation
  * offload
  *
+ * @IEEE80211_HW_SUPPORTS_MULTI_BSSID_AP: Hardware supports multi BSSID in AP 
mode
+ *
  * @NUM_IEEE80211_HW_FLAGS: number of hardware flags, used for sizing arrays
  */
 enum ieee80211_hw_flags {
@@ -2436,6 +2461,7 @@ enum ieee80211_hw_flags {
IEEE80211_HW_SUPPORTS_ONLY_HE_MULTI_BSSID,
IEEE80211_HW_AMPDU_KEYBORDER_SUPPORT,
IEEE80211_HW_SUPPORTS_TX_ENCAP_OFFLOAD,
+   IEEE80211_HW_SUPPORTS_MULTI_BSSID_AP,
 
/* keep last, obviously */
NUM_IEEE80211_HW_FLAGS
diff --git a/net/mac80211/cfg.c b/net/mac80211/cfg.c
index da70f174d629..3e81241e709f 100644
--- a/net/mac80211/cfg.c
+++ b/net/mac80211/cfg.c
@@ -111,6 +111,39 @@ static int ieee80211_set_mon_options(struct 
ieee80211_sub_if_data *sdata,
return 0;
 }
 
+static void ieee80211_set_multiple_bssid_options(struct ieee80211_sub_if_data 
*sdata,
+struct cfg80211_ap_settings 
*params)
+{
+   struct ieee80211_local *local = sdata->local;
+   struct wiphy *wiphy = local->hw.wiphy;
+   struct net_device *parent;
+   struct ieee80211_sub_if_data *psdata;
+
+   if (!ieee80211_hw_check(>hw, SUPPORTS_MULTI_BSSID_AP))
+   return;
+
+   if (!params->multiple_bssid.count)
+   return;
+
+   if (params->multiple_bssid.parent) {
+   parent = __dev_get_by_index(wiphy_net(wiphy),
+   params-&

[PATCH V4 4/4] mac80211: don't allow CSA on non-transmitting interfaces

[John Crispin]

As a non-transmitting interface does not broadcast a beacon, we do not want
to allow channel switch announcements. They need to be triggered on the
transmitting interface.

Signed-off-by: Aloka Dixit 
Signed-off-by: John Crispin 
---
 net/mac80211/cfg.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/net/mac80211/cfg.c b/net/mac80211/cfg.c
index 11cecb2ed640..7693894c4f84 100644
--- a/net/mac80211/cfg.c
+++ b/net/mac80211/cfg.c
@@ -3504,6 +3504,9 @@ __ieee80211_channel_switch(struct wiphy *wiphy, struct 
net_device *dev,
if (sdata->vif.csa_active)
return -EBUSY;
 
+   if (sdata->vif.multiple_bssid.flags & 
IEEE80211_VIF_MBSS_NON_TRANSMITTING)
+   return -EINVAL;
+
mutex_lock(>chanctx_mtx);
conf = rcu_dereference_protected(sdata->vif.chanctx_conf,
 lockdep_is_held(>chanctx_mtx));
-- 
2.25.1

[PATCH V4 0/4] mac80211: add multiple bssid support

[John Crispin]

Changes in V4
* move multiple bssid config from add_interface to start_ap
* add ema support

John Crispin (4):
  nl80211: add basic multiple bssid support
  mac80211: add multiple bssid support to interface handling
  mac80211: add multiple bssid/EMA support to beacon handling
  mac80211: don't allow CSA on non-transmitting interfaces

 include/net/cfg80211.h   |  33 
 include/net/mac80211.h   | 118 +-
 include/uapi/linux/nl80211.h |  21 +
 net/mac80211/cfg.c   | 113 -
 net/mac80211/debugfs.c   |   1 +
 net/mac80211/ieee80211_i.h   |   2 +
 net/mac80211/iface.c |   6 ++
 net/mac80211/tx.c| 157 +++
 net/wireless/nl80211.c   |  34 
 9 files changed, 464 insertions(+), 21 deletions(-)

-- 
2.25.1

[PATCH V4 3/4] mac80211: add multiple bssid/EMA support to beacon handling

[John Crispin]

With beacon_data now holding the additional information about the multiple
bssid elements, we need to honour these in the various beacon handling
code paths.

Extend ieee80211_beacon_get_template() to allow generation of multiple
bssid/EMA beacons. The API provides support for HW that can offload the
EMA beaconing aswell as HW that will require periodic updates of the
beacon template upon completion events.

In case the HW can do full EMA offload, functions are provided that allow
the driver to get a list of the periodicity number of beacons and their
matching mutable offsets.

Signed-off-by: Aloka Dixit 
Signed-off-by: John Crispin 
---
 include/net/mac80211.h |  90 +
 net/mac80211/cfg.c |  57 +-
 net/mac80211/ieee80211_i.h |   2 +
 net/mac80211/tx.c  | 157 +
 4 files changed, 286 insertions(+), 20 deletions(-)

diff --git a/include/net/mac80211.h b/include/net/mac80211.h
index fef9c893f757..0116d6539109 100644
--- a/include/net/mac80211.h
+++ b/include/net/mac80211.h
@@ -4862,12 +4862,17 @@ void ieee80211_report_low_ack(struct ieee80211_sta 
*sta, u32 num_packets);
  * @cntdwn_counter_offs: array of IEEE80211_MAX_CNTDWN_COUNTERS_NUM offsets
  * to countdown counters.  This array can contain zero values which
  * should be ignored.
+ * @multiple_bssid_offset: position of the multiple bssid element
+ * @multiple_bssid_length: size of the multiple bssid element
  */
 struct ieee80211_mutable_offsets {
u16 tim_offset;
u16 tim_length;
 
u16 cntdwn_counter_offs[IEEE80211_MAX_CNTDWN_COUNTERS_NUM];
+
+   u16 multiple_bssid_offset;
+   u16 multiple_bssid_length;
 };
 
 /**
@@ -4894,6 +4899,91 @@ ieee80211_beacon_get_template(struct ieee80211_hw *hw,
  struct ieee80211_vif *vif,
  struct ieee80211_mutable_offsets *offs);
 
+/**
+ * enum ieee80211_bcn_tmpl_ema - EMA beacon generation type
+ * @IEEE80211_BCN_EMA_NONE: don't generate an EMA beacon.
+ * @IEEE80211_BCN_EMA_NEXT: generate the next periodicity beacon.
+ * @IEEE80211_BCN_EMA_INDEX: generate beacon by periodicity index
+ * if the value is >= this enum value.
+ */
+enum ieee80211_bcn_tmpl_ema {
+   IEEE80211_BCN_EMA_NONE  = -2,
+   IEEE80211_BCN_EMA_NEXT  = -1,
+   IEEE80211_BCN_EMA_INDEX = 0,
+};
+
+/**
+ * ieee80211_beacon_get_template_ema_next - EMA beacon template generation
+ * function for drivers using the sw offload path.
+ * @hw: pointer obtained from ieee80211_alloc_hw().
+ * @vif:  ieee80211_vif pointer from the add_interface callback.
+ * @offs:  ieee80211_mutable_offsets pointer to struct that will
+ * receive the offsets that may be updated by the driver.
+ *
+ * This function differs from ieee80211_beacon_get_template in the sense that
+ * it generates EMA VAP templates. When we use multiple_bssid, the beacons can
+ * get very large costing a lot of airtime. To work around this, we iterate
+ * over the multiple bssid elements and only send one inside the beacon for
+ * 1..n. Calling this function will auto-increment the periodicity counter.
+ *
+ * This function needs to follow the same rules as 
ieee80211_beacon_get_template
+ *
+ * Return: The beacon template. %NULL on error.
+ */
+
+struct sk_buff *
+ieee80211_beacon_get_template_ema_next(struct ieee80211_hw *hw,
+  struct ieee80211_vif *vif,
+  struct ieee80211_mutable_offsets *offs);
+
+/** struct ieee80211_ema_bcn_list - list entry of an EMA beacon
+ * @list: the list pointer.
+ * @skb: the skb containing this specific beacon
+ * @offs:  ieee80211_mutable_offsets pointer to struct that will
+ * receive the offsets that may be updated by the driver.
+ */
+struct ieee80211_ema_bcn_list {
+   struct list_head list;
+   struct sk_buff *skb;
+   struct ieee80211_mutable_offsets offs;
+};
+
+/**
+ * ieee80211_beacon_get_template_ema_list - EMA beacon template generation
+ * function for drivers using the hw offload.
+ * @hw: pointer obtained from ieee80211_alloc_hw().
+ * @vif:  ieee80211_vif pointer from the add_interface callback.
+ * @head: linked list head that will get populated with
+ *  ieee80211_ema_bcn_list pointers.
+ *
+ * This function differs from ieee80211_beacon_get_template in the sense that
+ * it generates EMA VAP templates. When we use multiple_bssid, the beacons can
+ * get very large costing a lot of airtime. To work around this, we iterate
+ * over the multiple bssid elements and only send one inside the beacon for
+ * 1..n. This function will populate a linked list that the driver can pass
+ * to the HW.
+ *
+ * This function needs to follow the same rules as 
ieee80211_beacon_get_template
+ *
+ * Return: The nuber of entries in the list or 0 on error.
+ */
+
+int
+ieee80211_beacon_get_template_ema_list(struct ieee80211_hw 

Re: [PATCH V4 0/4] mac80211: add multiple bssid support

[John Crispin]

oops, CC'ed the wrong ML, sorry ...

On 09.10.20 12:13, John Crispin wrote:

Changes in V4
* move multiple bssid config from add_interface to start_ap
* add ema support

John Crispin (4):
   nl80211: add basic multiple bssid support
   mac80211: add multiple bssid support to interface handling
   mac80211: add multiple bssid/EMA support to beacon handling
   mac80211: don't allow CSA on non-transmitting interfaces

  include/net/cfg80211.h   |  33 
  include/net/mac80211.h   | 118 +-
  include/uapi/linux/nl80211.h |  21 +
  net/mac80211/cfg.c   | 113 -
  net/mac80211/debugfs.c   |   1 +
  net/mac80211/ieee80211_i.h   |   2 +
  net/mac80211/iface.c |   6 ++
  net/mac80211/tx.c| 157 +++
  net/wireless/nl80211.c   |  34 
  9 files changed, 464 insertions(+), 21 deletions(-)

Re: [PATCH 2/2] dt-bindings: net: dsa: qca8k: Add PORT0_PAD_CTRL properties

[John Crispin]

On 17.07.20 22:39, Florian Fainelli wrote:


On 7/17/2020 1:29 PM, Matthew Hagan wrote:


On 16/07/2020 23:09, Jakub Kicinski wrote:

On Mon, 13 Jul 2020 21:50:26 +0100 Matthew Hagan wrote:

Add names and decriptions of additional PORT0_PAD_CTRL properties.

Signed-off-by: Matthew Hagan 
---
  Documentation/devicetree/bindings/net/dsa/qca8k.txt | 8 
  1 file changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/net/dsa/qca8k.txt 
b/Documentation/devicetree/bindings/net/dsa/qca8k.txt
index ccbc6d89325d..3d34c4f2e891 100644
--- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt
+++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt
@@ -13,6 +13,14 @@ Optional properties:
  
  - reset-gpios: GPIO to be used to reset the whole device
  
+Optional MAC configuration properties:

+
+- qca,exchange-mac0-mac6:  If present, internally swaps MAC0 and MAC6.

Perhaps we can say a little more here?


 From John's patch:
"The switch allows us to swap the internal wirering of the two cpu ports.
For the HW offloading to work the ethernet MAC conencting to the LAN
ports must be wired to cpu port 0. There is HW in the wild that does not
fulfill this requirement. On these boards we need to swap the cpu ports."

This option is somewhat linked to instances where both MAC0 and MAC6 are
used as CPU ports. I may omit this for now since support for this hasn't
been added and MAC0 is hard-coded as the CPU port. The initial intention
here was to cover options commonly set by OpenWrt devices, based upon
their ar8327-initvals, to allow migration to qca8k.

If you update the description of the property, I do not see a reason why
this should not be supported as of today, sooner or later you will need
it to convert more devices to qca8k as you say.


correct, there will be patches soonish to make qcom dakota and 
hawkeye/cypress use qca8k as their switch fabric is 95% identical.  we 
already started working on it. it is mmio based rather than mdio based, 
so the patch is quite a large rework right now.


    John

Re: [PATCH 2/2] dt-bindings: net: dsa: qca8k: Add PORT0_PAD_CTRL properties

[John Crispin]

On 17.07.20 22:29, Matthew Hagan wrote:


On 16/07/2020 23:09, Jakub Kicinski wrote:

On Mon, 13 Jul 2020 21:50:26 +0100 Matthew Hagan wrote:

Add names and decriptions of additional PORT0_PAD_CTRL properties.

Signed-off-by: Matthew Hagan 
---
  Documentation/devicetree/bindings/net/dsa/qca8k.txt | 8 
  1 file changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/net/dsa/qca8k.txt 
b/Documentation/devicetree/bindings/net/dsa/qca8k.txt
index ccbc6d89325d..3d34c4f2e891 100644
--- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt
+++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt
@@ -13,6 +13,14 @@ Optional properties:
  
  - reset-gpios: GPIO to be used to reset the whole device
  
+Optional MAC configuration properties:

+
+- qca,exchange-mac0-mac6:  If present, internally swaps MAC0 and MAC6.

Perhaps we can say a little more here?


 From John's patch:
"The switch allows us to swap the internal wirering of the two cpu ports.
For the HW offloading to work the ethernet MAC conencting to the LAN
ports must be wired to cpu port 0. There is HW in the wild that does not
fulfill this requirement. On these boards we need to swap the cpu ports."

This option is somewhat linked to instances where both MAC0 and MAC6 are
used as CPU ports. I may omit this for now since support for this hasn't
been added and MAC0 is hard-coded as the CPU port. The initial intention
here was to cover options commonly set by OpenWrt devices, based upon
their ar8327-initvals, to allow migration to qca8k.


correct, specifically quantenna designs do this, also saw ciscos swap 
mac0/6 for cpu port, that part of the patch is definitely safe to go. I 
stumbled across this while making qca8k work for g-fiber on a quantenna SoC.


in regards to the sgmii clk skew. I never understood the electrics fully 
I am afraid, but without the patch it simply does not work. my eletcric 
foo is unfortunately is not sufficient to understand the "whys" I am afraid.


    John

Re: [PATCH v7 1/3] phy: add driver for Qualcomm IPQ40xx USB PHY

[John Crispin]

On 03.05.20 22:18, Robert Marko wrote:

Add a driver to setup the USB PHY-s on Qualcom m IPQ40xx series SoCs.
The driver sets up HS and SS phys.

Signed-off-by: John Crispin
Signed-off-by: Robert Marko
Cc: Luka Perkov


Thanks for pushing these patches upstream !

Re: [PATCH 2/5] MIPS: lantiq: use a generic "EBU" driver for Falcon and XWAY SoCs

[John Crispin]

On 27/07/2019 19:53, Martin Blumenstingl wrote:

+ *  Copyright (C) 2011-2012 John Crispin


could you change that to j...@phrozen.org please

    John

Re: [PATCH] clk: Remove io.h from clk-provider.h

[John Crispin]

On 14/05/2019 19:09, Stephen Boyd wrote:

Now that we've gotten rid of clk_readl() we can remove io.h from the
clk-provider header and push out the io.h include to any code that isn't
already including the io.h header but using things like readl/writel,
etc.


for arch/mips/ath79/*

Acked-by: John Crispin 

Re: [PATCH] netfilter: fix checking method of conntrack helper

[John Crispin]

On 14/01/2019 10:59, Henry Yen wrote:

This patch uses nfct_help() to detect whether an
established connection needs conntrack helper instead of using
test_bit(IPS_HELPER_BIT, >status).

The reason is that IPS_HELPER_BIT is only set when using explicit
CT target.

However, in the case that a device enables conntrack helper via
command "echo 1 > /proc/sys/net/netfilter/nf_conntrack_helper",
the status of IPS_HELPER_BIT will not present any change, and
consequently it loses the checking ability in the context.

Signed-off-by: Henry Yen 
Reviewed-by: Ryder Lee 

Tested-by: John Crispin 

---
  net/netfilter/nft_flow_offload.c | 5 -
  1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/net/netfilter/nft_flow_offload.c b/net/netfilter/nft_flow_offload.c
index 974525eb92df..de4684cc4633 100644
--- a/net/netfilter/nft_flow_offload.c
+++ b/net/netfilter/nft_flow_offload.c
@@ -12,6 +12,7 @@
  #include 
  #include 
  #include 
+#include 
  
  struct nft_flow_offload {

struct nft_flowtable*flowtable;
@@ -71,6 +72,7 @@ static void nft_flow_offload_eval(const struct nft_expr *expr,
struct flow_offload *flow;
enum ip_conntrack_dir dir;
struct nf_conn *ct;
+   const struct nf_conn_help *help;
int ret;
  
  	if (nft_flow_offload_skip(pkt->skb))

@@ -88,7 +90,8 @@ static void nft_flow_offload_eval(const struct nft_expr *expr,
goto out;
}
  
-	if (test_bit(IPS_HELPER_BIT, >status))

+   help = nfct_help(ct);
+   if (help)
goto out;
  
  	if (ctinfo == IP_CT_NEW ||

Re: [PATCH] pinctrl: xway: fix gpio-hog related boot issues

[John Crispin]

On 17/12/2018 15:32, Linus Walleij wrote:

On Fri, Dec 14, 2018 at 8:48 AM Martin Schiller  wrote:


This patch is based on commit a86caa9ba5d7 ("pinctrl: msm: fix gpio-hog
related boot issues").

It fixes the issue that the gpio ranges needs to be defined before
gpiochip_add().

Therefore, we also have to swap the order of registering the pinctrl
driver and registering the gpio chip.

You also have to add the "gpio-ranges" property to the pinctrl device
node to get it finally working.

Signed-off-by: Martin Schiller 

Patch applied unless John Crispin has objections, it looks
good to me!

Yours,
Linus Walleij



sorry did not see the patch in my inbox

Acked-by: John Crispin 

Re: [resend PATCH 1/3] pwm: mediatek: drop flag 'has_clks'

[John Crispin]

On 14/11/2018 13:47, Thierry Reding wrote:

On Tue, Nov 13, 2018 at 10:08:22AM +0800, Ryder Lee wrote:

The flag 'has_clks' and related checks are superfluous as the CCF
subsystem does this for you.

Both of these mechanisms aren't equivalent. While CCF can deal with
optional clocks, what the has_clks flag actually means is that the
device doesn't need a clock (or doesn't have a clock input) on the
devices where it is cleared.

So I'd actually be in favor of keeping the has_clks property because it
serves as an additional sanity check. For example if you run this driver
on an SoC that "has clocks" but if you don't list them in DT, then after
this patch the driver will happily continue without clocks, even though
it may break completely without those clocks. I've seen SoCs respond to
disabled clocks for a hardware block in different ways, in many cases an
access to any of the registers will completely hang the CPU. In other
cases it may just crash in some other way or give you some sort of
machine exception. None of those are good, and make the tiny bit of
additional code required to support the has_clks flag very attractive.

But that's just my opinion. If you prefer to throw away that safety
barrier, be my guest. But if you do, please move this functionality into
the clock framework first and then make the driver use it.

Thierry


Hi,

sorry for my late response. I added the flag for the legacy MIPS 
silicon. These SoCs only have a single clock register with a few on/off 
bits. there is no complex clocktree or scaling. Hence COMMON_CLK is not 
supported by those SoCs. I fully agree with Thierry, that the flag makes 
this explicit and the intent was indeed to make sure that on silicon 
where clocks are required, that they really are listed in OF. This is 
indeed an extra sanity check and hiding it in an implicit check inside 
CCF does not feel right.


    John

Re: [resend PATCH 1/3] pwm: mediatek: drop flag 'has_clks'

[John Crispin]

On 14/11/2018 13:47, Thierry Reding wrote:

On Tue, Nov 13, 2018 at 10:08:22AM +0800, Ryder Lee wrote:

The flag 'has_clks' and related checks are superfluous as the CCF
subsystem does this for you.

Both of these mechanisms aren't equivalent. While CCF can deal with
optional clocks, what the has_clks flag actually means is that the
device doesn't need a clock (or doesn't have a clock input) on the
devices where it is cleared.

So I'd actually be in favor of keeping the has_clks property because it
serves as an additional sanity check. For example if you run this driver
on an SoC that "has clocks" but if you don't list them in DT, then after
this patch the driver will happily continue without clocks, even though
it may break completely without those clocks. I've seen SoCs respond to
disabled clocks for a hardware block in different ways, in many cases an
access to any of the registers will completely hang the CPU. In other
cases it may just crash in some other way or give you some sort of
machine exception. None of those are good, and make the tiny bit of
additional code required to support the has_clks flag very attractive.

But that's just my opinion. If you prefer to throw away that safety
barrier, be my guest. But if you do, please move this functionality into
the clock framework first and then make the driver use it.

Thierry


Hi,

sorry for my late response. I added the flag for the legacy MIPS 
silicon. These SoCs only have a single clock register with a few on/off 
bits. there is no complex clocktree or scaling. Hence COMMON_CLK is not 
supported by those SoCs. I fully agree with Thierry, that the flag makes 
this explicit and the intent was indeed to make sure that on silicon 
where clocks are required, that they really are listed in OF. This is 
indeed an extra sanity check and hiding it in an implicit check inside 
CCF does not feel right.


    John

Re: [PATCH] MIPS: pci-rt2880: set pci controller of_node

[John Crispin]

On 05/09/18 08:51, Mathias Kresin wrote:

From: Tobias Wolf 

Set the PCI controller of_node such that PCI devices can be
instantiated via device tree.

Signed-off-by: Tobias Wolf 
Signed-off-by: Mathias Kresin 

Acked-by: John Crispin 


---
  arch/mips/pci/pci-rt2880.c | 2 ++
  1 file changed, 2 insertions(+)

diff --git a/arch/mips/pci/pci-rt2880.c b/arch/mips/pci/pci-rt2880.c
index 711cdcc..f376a1d 100644
--- a/arch/mips/pci/pci-rt2880.c
+++ b/arch/mips/pci/pci-rt2880.c
@@ -246,6 +246,8 @@ static int rt288x_pci_probe(struct platform_device *pdev)
rt2880_pci_write_u32(PCI_BASE_ADDRESS_0, 0x0800);
(void) rt2880_pci_read_u32(PCI_BASE_ADDRESS_0);
  
+	rt2880_pci_controller.of_node = pdev->dev.of_node;

+
register_pci_controller(_pci_controller);
return 0;
  }

Re: [PATCH] MIPS: pci-rt2880: set pci controller of_node

[John Crispin]

On 05/09/18 08:51, Mathias Kresin wrote:

From: Tobias Wolf 

Set the PCI controller of_node such that PCI devices can be
instantiated via device tree.

Signed-off-by: Tobias Wolf 
Signed-off-by: Mathias Kresin 

Acked-by: John Crispin 


---
  arch/mips/pci/pci-rt2880.c | 2 ++
  1 file changed, 2 insertions(+)

diff --git a/arch/mips/pci/pci-rt2880.c b/arch/mips/pci/pci-rt2880.c
index 711cdcc..f376a1d 100644
--- a/arch/mips/pci/pci-rt2880.c
+++ b/arch/mips/pci/pci-rt2880.c
@@ -246,6 +246,8 @@ static int rt288x_pci_probe(struct platform_device *pdev)
rt2880_pci_write_u32(PCI_BASE_ADDRESS_0, 0x0800);
(void) rt2880_pci_read_u32(PCI_BASE_ADDRESS_0);
  
+	rt2880_pci_controller.of_node = pdev->dev.of_node;

+
register_pci_controller(_pci_controller);
return 0;
  }

Re: [PATCH] nohz: Fix missing tick reprog while interrupting inline timer softirq

[John Crispin]

> Sry, that disturbing you all, but what are the conclusion here for 4.14.y?
> - take Thomas's patch https://lore.kernel.org/patchwork/patch/969521/#1162900
> - revert commit 2d898915ccf4838c04531c51a598469e921a5eb5

Hi Frederic,

I reported this very issue to tglx last night and he asked me to verify his
proposed patch which i just did. I can confirm the the patch fixes the issue
on 4.14.67 and Greg should add it to the stable queue please.

Tested-by: John Crispin 

Thanks,
John

Re: [PATCH] nohz: Fix missing tick reprog while interrupting inline timer softirq

[John Crispin]

> Sry, that disturbing you all, but what are the conclusion here for 4.14.y?
> - take Thomas's patch https://lore.kernel.org/patchwork/patch/969521/#1162900
> - revert commit 2d898915ccf4838c04531c51a598469e921a5eb5

Hi Frederic,

I reported this very issue to tglx last night and he asked me to verify his
proposed patch which i just did. I can confirm the the patch fixes the issue
on 4.14.67 and Greg should add it to the stable queue please.

Tested-by: John Crispin 

Thanks,
John

[PATCH V2 2/3] phy: qcom-ipq4019-usb: add driver for QCOM/IPQ4019

[John Crispin]

Add a driver to setup the USB phy on Qualcom Dakota SoCs.
The driver sets up HS and SS phys. In case of HS some magic values need to
be written to magic offsets. These were taken from the SDK driver.

Signed-off-by: John Crispin 
---
 drivers/phy/qualcomm/Kconfig|   7 +
 drivers/phy/qualcomm/Makefile   |   1 +
 drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c | 193 
 3 files changed, 201 insertions(+)
 create mode 100644 drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c

diff --git a/drivers/phy/qualcomm/Kconfig b/drivers/phy/qualcomm/Kconfig
index 632a0e73ee10..41894904d708 100644
--- a/drivers/phy/qualcomm/Kconfig
+++ b/drivers/phy/qualcomm/Kconfig
@@ -17,6 +17,13 @@ config PHY_QCOM_APQ8064_SATA
depends on OF
select GENERIC_PHY
 
+config PHY_QCOM_IPQ4019_USB
+   tristate "Qualcomm IPQ4019 USB PHY module"
+   depends on OF && ARCH_QCOM
+   select GENERIC_PHY
+   help
+ Support for the USB PHY on QCOM IPQ4019/Dakota chipsets.
+
 config PHY_QCOM_IPQ806X_SATA
tristate "Qualcomm IPQ806x SATA SerDes/PHY driver"
depends on ARCH_QCOM
diff --git a/drivers/phy/qualcomm/Makefile b/drivers/phy/qualcomm/Makefile
index deb831f453ae..463383483cd4 100644
--- a/drivers/phy/qualcomm/Makefile
+++ b/drivers/phy/qualcomm/Makefile
@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0
 obj-$(CONFIG_PHY_ATH79_USB)+= phy-ath79-usb.o
 obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)+= phy-qcom-apq8064-sata.o
+obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o
 obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)+= phy-qcom-ipq806x-sata.o
 obj-$(CONFIG_PHY_QCOM_QMP) += phy-qcom-qmp.o
 obj-$(CONFIG_PHY_QCOM_QUSB2)   += phy-qcom-qusb2.o
diff --git a/drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c 
b/drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c
new file mode 100644
index ..12f81789c37e
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c
@@ -0,0 +1,193 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 John Crispin 
+ *
+ * Based on code from
+ * Allwinner Technology Co., Ltd. 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/*
+ * Magic registers copied from the SDK driver code
+ */
+#define PHY_CTRL0_ADDR 0x000
+#define PHY_CTRL1_ADDR 0x004
+#define PHY_CTRL2_ADDR 0x008
+#define PHY_CTRL3_ADDR 0x00C
+#define PHY_CTRL4_ADDR 0x010
+#define PHY_MISC_ADDR  0x024
+#define PHY_IPG_ADDR   0x030
+
+#define PHY_CTRL0_VAL  0xA4600015
+#define PHY_CTRL1_VAL  0x0950
+#define PHY_CTRL2_VAL  0x00058180
+#define PHY_CTRL3_VAL  0x6DB6DCD6
+#define PHY_CTRL4_VAL  0x836DB6DB
+#define PHY_MISC_VAL   0x3803FB0C
+#define PHY_IPG_VAL0x47323232
+
+struct ipq4019_usb_phy {
+   struct device   *dev;
+   struct phy  *phy;
+   void __iomem*base;
+   struct reset_control*por_rst;
+   struct reset_control*srif_rst;
+};
+
+static int ipq4019_ss_phy_power_off(struct phy *_phy)
+{
+   struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy);
+
+   reset_control_assert(phy->por_rst);
+   msleep(20);
+
+   return 0;
+}
+
+static int ipq4019_ss_phy_power_on(struct phy *_phy)
+{
+   struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy);
+
+   ipq4019_ss_phy_power_off(_phy);
+
+   reset_control_deassert(phy->por_rst);
+
+   return 0;
+}
+
+static struct phy_ops ipq4019_usb_ss_phy_ops = {
+   .power_on   = ipq4019_ss_phy_power_on,
+   .power_off  = ipq4019_ss_phy_power_off,
+};
+
+static int ipq4019_hs_phy_power_off(struct phy *_phy)
+{
+   struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy);
+
+   reset_control_assert(phy->por_rst);
+   msleep(20);
+
+   reset_control_assert(phy->srif_rst);
+   msleep(20);
+
+   return 0;
+}
+
+static int ipq4019_hs_phy_power_on(struct phy *_phy)
+{
+   struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy);
+
+   ipq4019_hs_phy_power_off(_phy);
+
+   reset_control_deassert(phy->srif_rst);
+   msleep(20);
+
+   writel(PHY_CTRL0_VAL, phy->base + PHY_CTRL0_ADDR);
+   writel(PHY_CTRL1_VAL, phy->base + PHY_CTRL1_ADDR);
+   writel(PHY_CTRL2_VAL, phy->base + PHY_CTRL2_ADDR);
+   writel(PHY_CTRL3_VAL, phy->base + PHY_CTRL3_ADDR);
+   writel(PHY_CTRL4_VAL, phy->base + PHY_CTRL4_ADDR);
+   writel(PHY_MISC_VAL, phy->base + PHY_MIS

[PATCH V2 0/3] phy: qcom-ipq4019-usb: add new driver

[John Crispin]

This series adds a PHY driver for the Qualcomm Dakota SoC

Changes V1->V2
* fix the compat string inside the binding doc
* fix up the reset names inside the binding doc
* reflect the above changes in the driver and dts/i files

John Crispin (3):
  dt-bindings: phy-qcom-ipq4019-usb: add binding document
  phy: qcom-ipq4019-usb: add driver for QCOM/IPQ4019
  qcom: ipq4019: add USB devicetree nodes

 .../bindings/phy/phy-qcom-ipq4019-usb.txt  |  21 +++
 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi  |  20 +++
 arch/arm/boot/dts/qcom-ipq4019.dtsi|  76 
 drivers/phy/qualcomm/Kconfig   |   7 +
 drivers/phy/qualcomm/Makefile  |   1 +
 drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c| 193 +
 6 files changed, 318 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/phy/phy-qcom-ipq4019-usb.txt
 create mode 100644 drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c

-- 
2.11.0

[PATCH V2 1/3] dt-bindings: phy-qcom-ipq4019-usb: add binding document

[John Crispin]

This patch adds the binding documentation for the HS/SS USB PHY found
inside Qualcomm Dakota SoCs.

Cc: Rob Herring 
Cc: devicet...@vger.kernel.org
Signed-off-by: John Crispin 
---
 .../bindings/phy/phy-qcom-ipq4019-usb.txt   | 21 +
 1 file changed, 21 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/phy/phy-qcom-ipq4019-usb.txt

diff --git a/Documentation/devicetree/bindings/phy/phy-qcom-ipq4019-usb.txt 
b/Documentation/devicetree/bindings/phy/phy-qcom-ipq4019-usb.txt
new file mode 100644
index ..320a596c45b4
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-qcom-ipq4019-usb.txt
@@ -0,0 +1,21 @@
+Qualcom Dakota HS/SS USB PHY
+
+Required properties:
+ - compatible: "qcom,ipq4019-usb-ss-phy",
+  "qcom,ipq4019-usb-hs-phy"
+ - reg: offset and length of the registers
+ - #phy-cells: should be 0
+ - resets: the reset controllers as listed below
+ - reset-names: the names of the reset controllers
+   "por" - the POR reset line for SS and HS phys
+   "srif" - the SRIF reset line for HS phys
+Example:
+
+usb-phy@a8000 {
+   compatible = "qcom,ipq4019-usb-hs-phy";
+   phy-cells = <0>;
+   reg = <0xa8000 0x40>;
+   resets = < USB2_HSPHY_POR_ARES>,
+< USB2_HSPHY_S_ARES>;
+   reset-names = "por", "srif";
+};
-- 
2.11.0

[PATCH V2 0/3] phy: qcom-ipq4019-usb: add new driver

[John Crispin]

This series adds a PHY driver for the Qualcomm Dakota SoC

Changes V1->V2
* fix the compat string inside the binding doc
* fix up the reset names inside the binding doc
* reflect the above changes in the driver and dts/i files

John Crispin (3):
  dt-bindings: phy-qcom-ipq4019-usb: add binding document
  phy: qcom-ipq4019-usb: add driver for QCOM/IPQ4019
  qcom: ipq4019: add USB devicetree nodes

 .../bindings/phy/phy-qcom-ipq4019-usb.txt  |  21 +++
 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi  |  20 +++
 arch/arm/boot/dts/qcom-ipq4019.dtsi|  76 
 drivers/phy/qualcomm/Kconfig   |   7 +
 drivers/phy/qualcomm/Makefile  |   1 +
 drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c| 193 +
 6 files changed, 318 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/phy/phy-qcom-ipq4019-usb.txt
 create mode 100644 drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c

-- 
2.11.0

[PATCH V2 1/3] dt-bindings: phy-qcom-ipq4019-usb: add binding document

[John Crispin]

This patch adds the binding documentation for the HS/SS USB PHY found
inside Qualcomm Dakota SoCs.

Cc: Rob Herring 
Cc: devicet...@vger.kernel.org
Signed-off-by: John Crispin 
---
 .../bindings/phy/phy-qcom-ipq4019-usb.txt   | 21 +
 1 file changed, 21 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/phy/phy-qcom-ipq4019-usb.txt

diff --git a/Documentation/devicetree/bindings/phy/phy-qcom-ipq4019-usb.txt 
b/Documentation/devicetree/bindings/phy/phy-qcom-ipq4019-usb.txt
new file mode 100644
index ..320a596c45b4
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-qcom-ipq4019-usb.txt
@@ -0,0 +1,21 @@
+Qualcom Dakota HS/SS USB PHY
+
+Required properties:
+ - compatible: "qcom,ipq4019-usb-ss-phy",
+  "qcom,ipq4019-usb-hs-phy"
+ - reg: offset and length of the registers
+ - #phy-cells: should be 0
+ - resets: the reset controllers as listed below
+ - reset-names: the names of the reset controllers
+   "por" - the POR reset line for SS and HS phys
+   "srif" - the SRIF reset line for HS phys
+Example:
+
+usb-phy@a8000 {
+   compatible = "qcom,ipq4019-usb-hs-phy";
+   phy-cells = <0>;
+   reg = <0xa8000 0x40>;
+   resets = < USB2_HSPHY_POR_ARES>,
+< USB2_HSPHY_S_ARES>;
+   reset-names = "por", "srif";
+};
-- 
2.11.0

[PATCH V2 2/3] phy: qcom-ipq4019-usb: add driver for QCOM/IPQ4019

[John Crispin]

Add a driver to setup the USB phy on Qualcom Dakota SoCs.
The driver sets up HS and SS phys. In case of HS some magic values need to
be written to magic offsets. These were taken from the SDK driver.

Signed-off-by: John Crispin 
---
 drivers/phy/qualcomm/Kconfig|   7 +
 drivers/phy/qualcomm/Makefile   |   1 +
 drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c | 193 
 3 files changed, 201 insertions(+)
 create mode 100644 drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c

diff --git a/drivers/phy/qualcomm/Kconfig b/drivers/phy/qualcomm/Kconfig
index 632a0e73ee10..41894904d708 100644
--- a/drivers/phy/qualcomm/Kconfig
+++ b/drivers/phy/qualcomm/Kconfig
@@ -17,6 +17,13 @@ config PHY_QCOM_APQ8064_SATA
depends on OF
select GENERIC_PHY
 
+config PHY_QCOM_IPQ4019_USB
+   tristate "Qualcomm IPQ4019 USB PHY module"
+   depends on OF && ARCH_QCOM
+   select GENERIC_PHY
+   help
+ Support for the USB PHY on QCOM IPQ4019/Dakota chipsets.
+
 config PHY_QCOM_IPQ806X_SATA
tristate "Qualcomm IPQ806x SATA SerDes/PHY driver"
depends on ARCH_QCOM
diff --git a/drivers/phy/qualcomm/Makefile b/drivers/phy/qualcomm/Makefile
index deb831f453ae..463383483cd4 100644
--- a/drivers/phy/qualcomm/Makefile
+++ b/drivers/phy/qualcomm/Makefile
@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0
 obj-$(CONFIG_PHY_ATH79_USB)+= phy-ath79-usb.o
 obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)+= phy-qcom-apq8064-sata.o
+obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o
 obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)+= phy-qcom-ipq806x-sata.o
 obj-$(CONFIG_PHY_QCOM_QMP) += phy-qcom-qmp.o
 obj-$(CONFIG_PHY_QCOM_QUSB2)   += phy-qcom-qusb2.o
diff --git a/drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c 
b/drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c
new file mode 100644
index ..12f81789c37e
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c
@@ -0,0 +1,193 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 John Crispin 
+ *
+ * Based on code from
+ * Allwinner Technology Co., Ltd. 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/*
+ * Magic registers copied from the SDK driver code
+ */
+#define PHY_CTRL0_ADDR 0x000
+#define PHY_CTRL1_ADDR 0x004
+#define PHY_CTRL2_ADDR 0x008
+#define PHY_CTRL3_ADDR 0x00C
+#define PHY_CTRL4_ADDR 0x010
+#define PHY_MISC_ADDR  0x024
+#define PHY_IPG_ADDR   0x030
+
+#define PHY_CTRL0_VAL  0xA4600015
+#define PHY_CTRL1_VAL  0x0950
+#define PHY_CTRL2_VAL  0x00058180
+#define PHY_CTRL3_VAL  0x6DB6DCD6
+#define PHY_CTRL4_VAL  0x836DB6DB
+#define PHY_MISC_VAL   0x3803FB0C
+#define PHY_IPG_VAL0x47323232
+
+struct ipq4019_usb_phy {
+   struct device   *dev;
+   struct phy  *phy;
+   void __iomem*base;
+   struct reset_control*por_rst;
+   struct reset_control*srif_rst;
+};
+
+static int ipq4019_ss_phy_power_off(struct phy *_phy)
+{
+   struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy);
+
+   reset_control_assert(phy->por_rst);
+   msleep(20);
+
+   return 0;
+}
+
+static int ipq4019_ss_phy_power_on(struct phy *_phy)
+{
+   struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy);
+
+   ipq4019_ss_phy_power_off(_phy);
+
+   reset_control_deassert(phy->por_rst);
+
+   return 0;
+}
+
+static struct phy_ops ipq4019_usb_ss_phy_ops = {
+   .power_on   = ipq4019_ss_phy_power_on,
+   .power_off  = ipq4019_ss_phy_power_off,
+};
+
+static int ipq4019_hs_phy_power_off(struct phy *_phy)
+{
+   struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy);
+
+   reset_control_assert(phy->por_rst);
+   msleep(20);
+
+   reset_control_assert(phy->srif_rst);
+   msleep(20);
+
+   return 0;
+}
+
+static int ipq4019_hs_phy_power_on(struct phy *_phy)
+{
+   struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy);
+
+   ipq4019_hs_phy_power_off(_phy);
+
+   reset_control_deassert(phy->srif_rst);
+   msleep(20);
+
+   writel(PHY_CTRL0_VAL, phy->base + PHY_CTRL0_ADDR);
+   writel(PHY_CTRL1_VAL, phy->base + PHY_CTRL1_ADDR);
+   writel(PHY_CTRL2_VAL, phy->base + PHY_CTRL2_ADDR);
+   writel(PHY_CTRL3_VAL, phy->base + PHY_CTRL3_ADDR);
+   writel(PHY_CTRL4_VAL, phy->base + PHY_CTRL4_ADDR);
+   writel(PHY_MISC_VAL, phy->base + PHY_MIS

[PATCH V2 3/3] qcom: ipq4019: add USB devicetree nodes

[John Crispin]

This patch makes USB work on the Dakota EVB.

Signed-off-by: John Crispin 
---
 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 20 +++
 arch/arm/boot/dts/qcom-ipq4019.dtsi   | 76 +++
 2 files changed, 96 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
index 418f9a022336..0c226de1c672 100644
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
@@ -109,5 +109,25 @@
wifi@a80 {
status = "ok";
};
+
+   usb3_ss_phy: usb-phy@9a000 {
+   status = "ok";
+   };
+
+   usb3_hs_phy: usb-phy@a6000 {
+   status = "ok";
+   };
+
+   usb3: usb3@8af8800 {
+   status = "ok";
+   };
+
+   usb2_hs_phy: usb-phy@a8000 {
+   status = "ok";
+   };
+
+   usb2: usb2@60f8800 {
+   status = "ok";
+   };
};
 };
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 4620beafa84d..2ef20749b446 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -553,5 +553,81 @@
  "legacy";
status = "disabled";
};
+
+   usb3_ss_phy: usb-phy@9a000 {
+   compatible = "qcom,ipq4019-usb-ss-phy";
+   #phy-cells = <0>;
+   reg = <0x9a000 0x800>;
+   reg-names = "phy_base";
+   resets = < USB3_UNIPHY_PHY_ARES>;
+   reset-names = "por";
+   status = "disabled";
+   };
+
+   usb3_hs_phy: usb-phy@a6000 {
+   compatible = "qcom,ipq4019-usb-hs-phy";
+   #phy-cells = <0>;
+   reg = <0xa6000 0x40>;
+   reg-names = "phy_base";
+   resets = < USB3_HSPHY_POR_ARES>,
+< USB3_HSPHY_S_ARES>;
+   reset-names = "por", "srif";
+   status = "disabled";
+   };
+
+   usb3@8af8800 {
+   compatible = "qcom,dwc3";
+   reg = <0x8af8800 0x100>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   clocks = < GCC_USB3_MASTER_CLK>,
+< GCC_USB3_SLEEP_CLK>,
+< GCC_USB3_MOCK_UTMI_CLK>;
+   clock-names = "master", "sleep", "mock_utmi";
+   ranges;
+   status = "disabled";
+
+   dwc3@8a0 {
+   compatible = "snps,dwc3";
+   reg = <0x8a0 0xf8000>;
+   interrupts = <0 132 0>;
+   phys = <_hs_phy>, <_ss_phy>;
+   phy-names = "usb2-phy", "usb3-phy";
+   dr_mode = "host";
+   };
+   };
+
+   usb2_hs_phy: usb-phy@a8000 {
+   compatible = "qcom,ipq4019-usb-hs-phy";
+   #phy-cells = <0>;
+   reg = <0xa8000 0x40>;
+   reg-names = "phy_base";
+   resets = < USB2_HSPHY_POR_ARES>,
+< USB2_HSPHY_S_ARES>;
+   reset-names = "por", "srif";
+   status = "disabled";
+   };
+
+   usb2@60f8800 {
+   compatible = "qcom,dwc3";
+   reg = <0x60f8800 0x100>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   clocks = < GCC_USB2_MASTER_CLK>,
+< GCC_USB2_SLEEP_CLK>,
+< GCC_USB2_MOCK_UTMI_CLK>;
+   clock-names = "master", "sleep", "mock_utmi";
+   ranges;
+   status = "disabled";
+
+   dwc3@600 {
+   compatible = "snps,dwc3";
+   reg = <0x600 0xf8000>;
+   interrupts = <0 136 0>;
+   phys = <_hs_phy>;
+   phy-names = "usb2-phy";
+   dr_mode = "host";
+   };
+   };
};
 };
-- 
2.11.0

[PATCH V2 3/3] qcom: ipq4019: add USB devicetree nodes

[John Crispin]

This patch makes USB work on the Dakota EVB.

Signed-off-by: John Crispin 
---
 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 20 +++
 arch/arm/boot/dts/qcom-ipq4019.dtsi   | 76 +++
 2 files changed, 96 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
index 418f9a022336..0c226de1c672 100644
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
@@ -109,5 +109,25 @@
wifi@a80 {
status = "ok";
};
+
+   usb3_ss_phy: usb-phy@9a000 {
+   status = "ok";
+   };
+
+   usb3_hs_phy: usb-phy@a6000 {
+   status = "ok";
+   };
+
+   usb3: usb3@8af8800 {
+   status = "ok";
+   };
+
+   usb2_hs_phy: usb-phy@a8000 {
+   status = "ok";
+   };
+
+   usb2: usb2@60f8800 {
+   status = "ok";
+   };
};
 };
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 4620beafa84d..2ef20749b446 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -553,5 +553,81 @@
  "legacy";
status = "disabled";
};
+
+   usb3_ss_phy: usb-phy@9a000 {
+   compatible = "qcom,ipq4019-usb-ss-phy";
+   #phy-cells = <0>;
+   reg = <0x9a000 0x800>;
+   reg-names = "phy_base";
+   resets = < USB3_UNIPHY_PHY_ARES>;
+   reset-names = "por";
+   status = "disabled";
+   };
+
+   usb3_hs_phy: usb-phy@a6000 {
+   compatible = "qcom,ipq4019-usb-hs-phy";
+   #phy-cells = <0>;
+   reg = <0xa6000 0x40>;
+   reg-names = "phy_base";
+   resets = < USB3_HSPHY_POR_ARES>,
+< USB3_HSPHY_S_ARES>;
+   reset-names = "por", "srif";
+   status = "disabled";
+   };
+
+   usb3@8af8800 {
+   compatible = "qcom,dwc3";
+   reg = <0x8af8800 0x100>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   clocks = < GCC_USB3_MASTER_CLK>,
+< GCC_USB3_SLEEP_CLK>,
+< GCC_USB3_MOCK_UTMI_CLK>;
+   clock-names = "master", "sleep", "mock_utmi";
+   ranges;
+   status = "disabled";
+
+   dwc3@8a0 {
+   compatible = "snps,dwc3";
+   reg = <0x8a0 0xf8000>;
+   interrupts = <0 132 0>;
+   phys = <_hs_phy>, <_ss_phy>;
+   phy-names = "usb2-phy", "usb3-phy";
+   dr_mode = "host";
+   };
+   };
+
+   usb2_hs_phy: usb-phy@a8000 {
+   compatible = "qcom,ipq4019-usb-hs-phy";
+   #phy-cells = <0>;
+   reg = <0xa8000 0x40>;
+   reg-names = "phy_base";
+   resets = < USB2_HSPHY_POR_ARES>,
+< USB2_HSPHY_S_ARES>;
+   reset-names = "por", "srif";
+   status = "disabled";
+   };
+
+   usb2@60f8800 {
+   compatible = "qcom,dwc3";
+   reg = <0x60f8800 0x100>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   clocks = < GCC_USB2_MASTER_CLK>,
+< GCC_USB2_SLEEP_CLK>,
+< GCC_USB2_MOCK_UTMI_CLK>;
+   clock-names = "master", "sleep", "mock_utmi";
+   ranges;
+   status = "disabled";
+
+   dwc3@600 {
+   compatible = "snps,dwc3";
+   reg = <0x600 0xf8000>;
+   interrupts = <0 136 0>;
+   phys = <_hs_phy>;
+   phy-names = "usb2-phy";
+   dr_mode = "host";
+   };
+   };
};
 };
-- 
2.11.0

[PATCH 1/3] dt-bindings: phy-qcom-ipq4019-usb: add binding document

[John Crispin]

This patch adds the binding documentation for the HS/SS USB PHY found
inside Qualcom Dakota SoCs.

Cc: Rob Herring 
Cc: devicet...@vger.kernel.org
Signed-off-by: John Crispin 
---
 .../bindings/phy/phy-qcom-ipq4019-usb.txt   | 21 +
 1 file changed, 21 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/phy/phy-qcom-ipq4019-usb.txt

diff --git a/Documentation/devicetree/bindings/phy/phy-qcom-ipq4019-usb.txt 
b/Documentation/devicetree/bindings/phy/phy-qcom-ipq4019-usb.txt
new file mode 100644
index ..362877fcafed
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-qcom-ipq4019-usb.txt
@@ -0,0 +1,21 @@
+Qualcom Dakota HS/SS USB PHY
+
+Required properties:
+ - compatible: "qcom,usb-ss-ipq4019-phy",
+  "qcom,usb-hs-ipq4019-phy"
+ - reg: offset and length of the registers
+ - #phy-cells: should be 0
+ - resets: the reset controllers as listed below
+ - reset-names: the names of the reset controllers
+   "por_rst" - the POR reset line for SS and HS phys
+   "srif_rst" - the SRIF reset line for HS phys
+Example:
+
+hsphy@a8000 {
+   compatible = "qcom,usb-hs-ipq4019-phy";
+   phy-cells = <0>;
+   reg = <0xa8000 0x40>;
+   resets = < USB2_HSPHY_POR_ARES>,
+< USB2_HSPHY_S_ARES>;
+   reset-names = "por_rst", "srif_rst";
+};
-- 
2.11.0

[PATCH 1/3] dt-bindings: phy-qcom-ipq4019-usb: add binding document

[John Crispin]

This patch adds the binding documentation for the HS/SS USB PHY found
inside Qualcom Dakota SoCs.

Cc: Rob Herring 
Cc: devicet...@vger.kernel.org
Signed-off-by: John Crispin 
---
 .../bindings/phy/phy-qcom-ipq4019-usb.txt   | 21 +
 1 file changed, 21 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/phy/phy-qcom-ipq4019-usb.txt

diff --git a/Documentation/devicetree/bindings/phy/phy-qcom-ipq4019-usb.txt 
b/Documentation/devicetree/bindings/phy/phy-qcom-ipq4019-usb.txt
new file mode 100644
index ..362877fcafed
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-qcom-ipq4019-usb.txt
@@ -0,0 +1,21 @@
+Qualcom Dakota HS/SS USB PHY
+
+Required properties:
+ - compatible: "qcom,usb-ss-ipq4019-phy",
+  "qcom,usb-hs-ipq4019-phy"
+ - reg: offset and length of the registers
+ - #phy-cells: should be 0
+ - resets: the reset controllers as listed below
+ - reset-names: the names of the reset controllers
+   "por_rst" - the POR reset line for SS and HS phys
+   "srif_rst" - the SRIF reset line for HS phys
+Example:
+
+hsphy@a8000 {
+   compatible = "qcom,usb-hs-ipq4019-phy";
+   phy-cells = <0>;
+   reg = <0xa8000 0x40>;
+   resets = < USB2_HSPHY_POR_ARES>,
+< USB2_HSPHY_S_ARES>;
+   reset-names = "por_rst", "srif_rst";
+};
-- 
2.11.0

[PATCH 3/3] qcom: ipq4019: add USB devicetree nodes

[John Crispin]

This patch makes USB work on the Dakota EVB.

Signed-off-by: John Crispin 
---
 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 20 +++
 arch/arm/boot/dts/qcom-ipq4019.dtsi   | 76 +++
 2 files changed, 96 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
index 418f9a022336..2ee5f05d5a43 100644
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
@@ -109,5 +109,25 @@
wifi@a80 {
status = "ok";
};
+
+   usb3_ss_phy: ssphy@9a000 {
+   status = "ok";
+   };
+
+   usb3_hs_phy: hsphy@a6000 {
+   status = "ok";
+   };
+
+   usb3: usb3@8af8800 {
+   status = "ok";
+   };
+
+   usb2_hs_phy: hsphy@a8000 {
+   status = "ok";
+   };
+
+   usb2: usb2@60f8800 {
+   status = "ok";
+   };
};
 };
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 47b10f4caa04..eb39f59f1843 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -553,5 +553,81 @@
  "legacy";
status = "disabled";
};
+
+   usb3_ss_phy: ssphy@9a000 {
+   compatible = "qcom,usb-ss-ipq4019-phy";
+   #phy-cells = <0>;
+   reg = <0x9a000 0x800>;
+   reg-names = "phy_base";
+   resets = < USB3_UNIPHY_PHY_ARES>;
+   reset-names = "por_rst";
+   status = "disabled";
+   };
+
+   usb3_hs_phy: hsphy@a6000 {
+   compatible = "qcom,usb-hs-ipq4019-phy";
+   #phy-cells = <0>;
+   reg = <0xa6000 0x40>;
+   reg-names = "phy_base";
+   resets = < USB3_HSPHY_POR_ARES>,
+< USB3_HSPHY_S_ARES>;
+   reset-names = "por_rst", "srif_rst";
+   status = "disabled";
+   };
+
+   usb3@8af8800 {
+   compatible = "qcom,dwc3";
+   reg = <0x8af8800 0x100>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   clocks = < GCC_USB3_MASTER_CLK>,
+< GCC_USB3_SLEEP_CLK>,
+< GCC_USB3_MOCK_UTMI_CLK>;
+   clock-names = "master", "sleep", "mock_utmi";
+   ranges;
+   status = "disabled";
+
+   dwc3@8a0 {
+   compatible = "snps,dwc3";
+   reg = <0x8a0 0xf8000>;
+   interrupts = <0 132 0>;
+   phys = <_hs_phy>, <_ss_phy>;
+   phy-names = "usb2-phy", "usb3-phy";
+   dr_mode = "host";
+   };
+   };
+
+   usb2_hs_phy: hsphy@a8000 {
+   compatible = "qcom,usb-hs-ipq4019-phy";
+   #phy-cells = <0>;
+   reg = <0xa8000 0x40>;
+   reg-names = "phy_base";
+   resets = < USB2_HSPHY_POR_ARES>,
+< USB2_HSPHY_S_ARES>;
+   reset-names = "por_rst", "srif_rst";
+   status = "disabled";
+   };
+
+   usb2@60f8800 {
+   compatible = "qcom,dwc3";
+   reg = <0x60f8800 0x100>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   clocks = < GCC_USB2_MASTER_CLK>,
+< GCC_USB2_SLEEP_CLK>,
+< GCC_USB2_MOCK_UTMI_CLK>;
+   clock-names = "master", "sleep", "mock_utmi";
+   ranges;
+   status = "disabled";
+
+   dwc3@600 {
+   compatible = "snps,dwc3";
+   reg = <0x600 0xf8000>;
+   interrupts = <0 136 0>;
+   phys = <_hs_phy>;
+   phy-names = "usb2-phy";
+   dr_mode = "host";
+   };
+   };
};
 };
-- 
2.11.0

[PATCH 3/3] qcom: ipq4019: add USB devicetree nodes

[John Crispin]

This patch makes USB work on the Dakota EVB.

Signed-off-by: John Crispin 
---
 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 20 +++
 arch/arm/boot/dts/qcom-ipq4019.dtsi   | 76 +++
 2 files changed, 96 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
index 418f9a022336..2ee5f05d5a43 100644
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
@@ -109,5 +109,25 @@
wifi@a80 {
status = "ok";
};
+
+   usb3_ss_phy: ssphy@9a000 {
+   status = "ok";
+   };
+
+   usb3_hs_phy: hsphy@a6000 {
+   status = "ok";
+   };
+
+   usb3: usb3@8af8800 {
+   status = "ok";
+   };
+
+   usb2_hs_phy: hsphy@a8000 {
+   status = "ok";
+   };
+
+   usb2: usb2@60f8800 {
+   status = "ok";
+   };
};
 };
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 47b10f4caa04..eb39f59f1843 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -553,5 +553,81 @@
  "legacy";
status = "disabled";
};
+
+   usb3_ss_phy: ssphy@9a000 {
+   compatible = "qcom,usb-ss-ipq4019-phy";
+   #phy-cells = <0>;
+   reg = <0x9a000 0x800>;
+   reg-names = "phy_base";
+   resets = < USB3_UNIPHY_PHY_ARES>;
+   reset-names = "por_rst";
+   status = "disabled";
+   };
+
+   usb3_hs_phy: hsphy@a6000 {
+   compatible = "qcom,usb-hs-ipq4019-phy";
+   #phy-cells = <0>;
+   reg = <0xa6000 0x40>;
+   reg-names = "phy_base";
+   resets = < USB3_HSPHY_POR_ARES>,
+< USB3_HSPHY_S_ARES>;
+   reset-names = "por_rst", "srif_rst";
+   status = "disabled";
+   };
+
+   usb3@8af8800 {
+   compatible = "qcom,dwc3";
+   reg = <0x8af8800 0x100>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   clocks = < GCC_USB3_MASTER_CLK>,
+< GCC_USB3_SLEEP_CLK>,
+< GCC_USB3_MOCK_UTMI_CLK>;
+   clock-names = "master", "sleep", "mock_utmi";
+   ranges;
+   status = "disabled";
+
+   dwc3@8a0 {
+   compatible = "snps,dwc3";
+   reg = <0x8a0 0xf8000>;
+   interrupts = <0 132 0>;
+   phys = <_hs_phy>, <_ss_phy>;
+   phy-names = "usb2-phy", "usb3-phy";
+   dr_mode = "host";
+   };
+   };
+
+   usb2_hs_phy: hsphy@a8000 {
+   compatible = "qcom,usb-hs-ipq4019-phy";
+   #phy-cells = <0>;
+   reg = <0xa8000 0x40>;
+   reg-names = "phy_base";
+   resets = < USB2_HSPHY_POR_ARES>,
+< USB2_HSPHY_S_ARES>;
+   reset-names = "por_rst", "srif_rst";
+   status = "disabled";
+   };
+
+   usb2@60f8800 {
+   compatible = "qcom,dwc3";
+   reg = <0x60f8800 0x100>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   clocks = < GCC_USB2_MASTER_CLK>,
+< GCC_USB2_SLEEP_CLK>,
+< GCC_USB2_MOCK_UTMI_CLK>;
+   clock-names = "master", "sleep", "mock_utmi";
+   ranges;
+   status = "disabled";
+
+   dwc3@600 {
+   compatible = "snps,dwc3";
+   reg = <0x600 0xf8000>;
+   interrupts = <0 136 0>;
+   phys = <_hs_phy>;
+   phy-names = "usb2-phy";
+   dr_mode = "host";
+   };
+   };
};
 };
-- 
2.11.0

[PATCH 2/3] phy: qcom-ipq4019-usb: add driver for QCOM/IPQ4019

[John Crispin]

Add a driver to setup the USB phy on Qualcom Dakota SoCs.
The driver sets up HS and SS phys. In case of HS some magic values need to
be written to magic offsets. These were taken from the SDK driver.

Signed-off-by: John Crispin 
---
 drivers/phy/qualcomm/Kconfig|   7 +
 drivers/phy/qualcomm/Makefile   |   1 +
 drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c | 193 
 3 files changed, 201 insertions(+)
 create mode 100644 drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c

diff --git a/drivers/phy/qualcomm/Kconfig b/drivers/phy/qualcomm/Kconfig
index 632a0e73ee10..41894904d708 100644
--- a/drivers/phy/qualcomm/Kconfig
+++ b/drivers/phy/qualcomm/Kconfig
@@ -17,6 +17,13 @@ config PHY_QCOM_APQ8064_SATA
depends on OF
select GENERIC_PHY
 
+config PHY_QCOM_IPQ4019_USB
+   tristate "Qualcomm IPQ4019 USB PHY module"
+   depends on OF && ARCH_QCOM
+   select GENERIC_PHY
+   help
+ Support for the USB PHY on QCOM IPQ4019/Dakota chipsets.
+
 config PHY_QCOM_IPQ806X_SATA
tristate "Qualcomm IPQ806x SATA SerDes/PHY driver"
depends on ARCH_QCOM
diff --git a/drivers/phy/qualcomm/Makefile b/drivers/phy/qualcomm/Makefile
index deb831f453ae..463383483cd4 100644
--- a/drivers/phy/qualcomm/Makefile
+++ b/drivers/phy/qualcomm/Makefile
@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0
 obj-$(CONFIG_PHY_ATH79_USB)+= phy-ath79-usb.o
 obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)+= phy-qcom-apq8064-sata.o
+obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o
 obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)+= phy-qcom-ipq806x-sata.o
 obj-$(CONFIG_PHY_QCOM_QMP) += phy-qcom-qmp.o
 obj-$(CONFIG_PHY_QCOM_QUSB2)   += phy-qcom-qusb2.o
diff --git a/drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c 
b/drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c
new file mode 100644
index ..89ab02161589
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c
@@ -0,0 +1,193 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 John Crispin 
+ *
+ * Based on code from
+ * Allwinner Technology Co., Ltd. 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/*
+ * Magic registers copied from the SDK driver code
+ */
+#define PHY_CTRL0_ADDR 0x000
+#define PHY_CTRL1_ADDR 0x004
+#define PHY_CTRL2_ADDR 0x008
+#define PHY_CTRL3_ADDR 0x00C
+#define PHY_CTRL4_ADDR 0x010
+#define PHY_MISC_ADDR  0x024
+#define PHY_IPG_ADDR   0x030
+
+#define PHY_CTRL0_VAL  0xA4600015
+#define PHY_CTRL1_VAL  0x0950
+#define PHY_CTRL2_VAL  0x00058180
+#define PHY_CTRL3_VAL  0x6DB6DCD6
+#define PHY_CTRL4_VAL  0x836DB6DB
+#define PHY_MISC_VAL   0x3803FB0C
+#define PHY_IPG_VAL0x47323232
+
+struct ipq4019_usb_phy {
+   struct device   *dev;
+   struct phy  *phy;
+   void __iomem*base;
+   struct reset_control*por_rst;
+   struct reset_control*srif_rst;
+};
+
+static int ipq4019_ss_phy_power_off(struct phy *_phy)
+{
+   struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy);
+
+   reset_control_assert(phy->por_rst);
+   msleep(20);
+
+   return 0;
+}
+
+static int ipq4019_ss_phy_power_on(struct phy *_phy)
+{
+   struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy);
+
+   ipq4019_ss_phy_power_off(_phy);
+
+   reset_control_deassert(phy->por_rst);
+
+   return 0;
+}
+
+static struct phy_ops ipq4019_usb_ss_phy_ops = {
+   .power_on   = ipq4019_ss_phy_power_on,
+   .power_off  = ipq4019_ss_phy_power_off,
+};
+
+static int ipq4019_hs_phy_power_off(struct phy *_phy)
+{
+   struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy);
+
+   reset_control_assert(phy->por_rst);
+   msleep(20);
+
+   reset_control_assert(phy->srif_rst);
+   msleep(20);
+
+   return 0;
+}
+
+static int ipq4019_hs_phy_power_on(struct phy *_phy)
+{
+   struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy);
+
+   ipq4019_hs_phy_power_off(_phy);
+
+   reset_control_deassert(phy->srif_rst);
+   msleep(20);
+
+   writel(PHY_CTRL0_VAL, phy->base + PHY_CTRL0_ADDR);
+   writel(PHY_CTRL1_VAL, phy->base + PHY_CTRL1_ADDR);
+   writel(PHY_CTRL2_VAL, phy->base + PHY_CTRL2_ADDR);
+   writel(PHY_CTRL3_VAL, phy->base + PHY_CTRL3_ADDR);
+   writel(PHY_CTRL4_VAL, phy->base + PHY_CTRL4_ADDR);
+   writel(PHY_MISC_VAL, phy->base + PHY_MIS

[PATCH 2/3] phy: qcom-ipq4019-usb: add driver for QCOM/IPQ4019

[John Crispin]

Add a driver to setup the USB phy on Qualcom Dakota SoCs.
The driver sets up HS and SS phys. In case of HS some magic values need to
be written to magic offsets. These were taken from the SDK driver.

Signed-off-by: John Crispin 
---
 drivers/phy/qualcomm/Kconfig|   7 +
 drivers/phy/qualcomm/Makefile   |   1 +
 drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c | 193 
 3 files changed, 201 insertions(+)
 create mode 100644 drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c

diff --git a/drivers/phy/qualcomm/Kconfig b/drivers/phy/qualcomm/Kconfig
index 632a0e73ee10..41894904d708 100644
--- a/drivers/phy/qualcomm/Kconfig
+++ b/drivers/phy/qualcomm/Kconfig
@@ -17,6 +17,13 @@ config PHY_QCOM_APQ8064_SATA
depends on OF
select GENERIC_PHY
 
+config PHY_QCOM_IPQ4019_USB
+   tristate "Qualcomm IPQ4019 USB PHY module"
+   depends on OF && ARCH_QCOM
+   select GENERIC_PHY
+   help
+ Support for the USB PHY on QCOM IPQ4019/Dakota chipsets.
+
 config PHY_QCOM_IPQ806X_SATA
tristate "Qualcomm IPQ806x SATA SerDes/PHY driver"
depends on ARCH_QCOM
diff --git a/drivers/phy/qualcomm/Makefile b/drivers/phy/qualcomm/Makefile
index deb831f453ae..463383483cd4 100644
--- a/drivers/phy/qualcomm/Makefile
+++ b/drivers/phy/qualcomm/Makefile
@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0
 obj-$(CONFIG_PHY_ATH79_USB)+= phy-ath79-usb.o
 obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)+= phy-qcom-apq8064-sata.o
+obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o
 obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)+= phy-qcom-ipq806x-sata.o
 obj-$(CONFIG_PHY_QCOM_QMP) += phy-qcom-qmp.o
 obj-$(CONFIG_PHY_QCOM_QUSB2)   += phy-qcom-qusb2.o
diff --git a/drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c 
b/drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c
new file mode 100644
index ..89ab02161589
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c
@@ -0,0 +1,193 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 John Crispin 
+ *
+ * Based on code from
+ * Allwinner Technology Co., Ltd. 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/*
+ * Magic registers copied from the SDK driver code
+ */
+#define PHY_CTRL0_ADDR 0x000
+#define PHY_CTRL1_ADDR 0x004
+#define PHY_CTRL2_ADDR 0x008
+#define PHY_CTRL3_ADDR 0x00C
+#define PHY_CTRL4_ADDR 0x010
+#define PHY_MISC_ADDR  0x024
+#define PHY_IPG_ADDR   0x030
+
+#define PHY_CTRL0_VAL  0xA4600015
+#define PHY_CTRL1_VAL  0x0950
+#define PHY_CTRL2_VAL  0x00058180
+#define PHY_CTRL3_VAL  0x6DB6DCD6
+#define PHY_CTRL4_VAL  0x836DB6DB
+#define PHY_MISC_VAL   0x3803FB0C
+#define PHY_IPG_VAL0x47323232
+
+struct ipq4019_usb_phy {
+   struct device   *dev;
+   struct phy  *phy;
+   void __iomem*base;
+   struct reset_control*por_rst;
+   struct reset_control*srif_rst;
+};
+
+static int ipq4019_ss_phy_power_off(struct phy *_phy)
+{
+   struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy);
+
+   reset_control_assert(phy->por_rst);
+   msleep(20);
+
+   return 0;
+}
+
+static int ipq4019_ss_phy_power_on(struct phy *_phy)
+{
+   struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy);
+
+   ipq4019_ss_phy_power_off(_phy);
+
+   reset_control_deassert(phy->por_rst);
+
+   return 0;
+}
+
+static struct phy_ops ipq4019_usb_ss_phy_ops = {
+   .power_on   = ipq4019_ss_phy_power_on,
+   .power_off  = ipq4019_ss_phy_power_off,
+};
+
+static int ipq4019_hs_phy_power_off(struct phy *_phy)
+{
+   struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy);
+
+   reset_control_assert(phy->por_rst);
+   msleep(20);
+
+   reset_control_assert(phy->srif_rst);
+   msleep(20);
+
+   return 0;
+}
+
+static int ipq4019_hs_phy_power_on(struct phy *_phy)
+{
+   struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy);
+
+   ipq4019_hs_phy_power_off(_phy);
+
+   reset_control_deassert(phy->srif_rst);
+   msleep(20);
+
+   writel(PHY_CTRL0_VAL, phy->base + PHY_CTRL0_ADDR);
+   writel(PHY_CTRL1_VAL, phy->base + PHY_CTRL1_ADDR);
+   writel(PHY_CTRL2_VAL, phy->base + PHY_CTRL2_ADDR);
+   writel(PHY_CTRL3_VAL, phy->base + PHY_CTRL3_ADDR);
+   writel(PHY_CTRL4_VAL, phy->base + PHY_CTRL4_ADDR);
+   writel(PHY_MISC_VAL, phy->base + PHY_MIS

Re: [PATCH 2/2] dt-bindings: arm: mediatek: cleanup MT7623N reference boards

[John Crispin]

On 10/07/18 07:09, Ryder Lee wrote:

Cleanup binding document to get rid of unsupported reference boards
for MT7623N.

Cc: John Crispin 
Cc: Sean Wang 
Signed-off-by: Ryder Lee 

Acked-by: John Crispin 

---
  Documentation/devicetree/bindings/arm/mediatek.txt | 3 ---
  1 file changed, 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt 
b/Documentation/devicetree/bindings/arm/mediatek.txt
index 7d21ab3..c07ddf4 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek.txt
@@ -59,9 +59,6 @@ Supported boards:
  - Reference board for MT7623n with eMMC:
  Required root node properties:
- compatible = "mediatek,mt7623n-rfb-emmc", "mediatek,mt7623";
-- Reference  board for MT7623n with NAND:
-Required root node properties:
-  - compatible = "mediatek,mt7623n-rfb-nand", "mediatek,mt7623";
  - Bananapi BPI-R2 board:
- compatible = "bananapi,bpi-r2", "mediatek,mt7623";
  - MTK mt8127 tablet moose EVB:

Re: [PATCH 1/2] arm: dts: mt7623: cleanup MT7623N NAND dts file

[John Crispin]

On 10/07/18 07:09, Ryder Lee wrote:

Normally, we didn't release this kind of baord to user. This specific
board exists only in the early stage of development inside MediaTek -
and that may confuse peoples.

Hence this patch removes related files accordingly.

Cc: John Crispin 
Cc: Sean Wang 
Signed-off-by: Ryder Lee 

Acked-by: John Crispin 

---
  arch/arm/boot/dts/Makefile |  1 -
  arch/arm/boot/dts/mt7623n-rfb-nand.dts | 73 -
  arch/arm/boot/dts/mt7623n-rfb.dtsi | 86 --
  3 files changed, 160 deletions(-)
  delete mode 100644 arch/arm/boot/dts/mt7623n-rfb-nand.dts
  delete mode 100644 arch/arm/boot/dts/mt7623n-rfb.dtsi

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 37a3de7..dde494e 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1168,7 +1168,6 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7623a-rfb-emmc.dtb \
mt7623a-rfb-nand.dtb \
mt7623n-rfb-emmc.dtb \
-   mt7623n-rfb-nand.dtb \
mt7623n-bananapi-bpi-r2.dtb \
mt8127-moose.dtb \
mt8135-evbp1.dtb
diff --git a/arch/arm/boot/dts/mt7623n-rfb-nand.dts 
b/arch/arm/boot/dts/mt7623n-rfb-nand.dts
deleted file mode 100644
index 96ff3c9..000
--- a/arch/arm/boot/dts/mt7623n-rfb-nand.dts
+++ /dev/null
@@ -1,73 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2017 MediaTek Inc.
- * Author: John Crispin 
- *
- */
-
-/dts-v1/;
-#include "mt7623n-rfb.dtsi"
-
-/ {
-   model = "MediaTek MT7623N NAND reference board";
-   compatible = "mediatek,mt7623n-rfb-nand", "mediatek,mt7623";
-};
-
- {
-   status = "okay";
-};
-
- {
-   status = "okay";
-   pinctrl-names = "default";
-   pinctrl-0 = <_pins_default>;
-
-   nand@0 {
-   reg = <0>;
-   spare_per_sector = <64>;
-   nand-ecc-mode = "hw";
-   nand-ecc-strength = <12>;
-   nand-ecc-step-size = <1024>;
-
-   partitions {
-   compatible = "fixed-partitions";
-   #address-cells = <1>;
-   #size-cells = <1>;
-
-   partition@0 {
-   label = "preloader";
-   reg = <0x0 0x4>;
-   };
-
-   partition@4 {
-   label = "uboot";
-   reg = <0x4 0x8>;
-   };
-
-   partition@c {
-   label = "uboot-env";
-   reg = <0xC 0x4>;
-   };
-
-   partition@14 {
-   label = "bootimg";
-   reg = <0x14 0x200>;
-   };
-
-   partition@214 {
-   label = "recovery";
-   reg = <0x214 0x200>;
-   };
-
-   partition@414 {
-   label = "rootfs";
-   reg = <0x414 0x100>;
-   };
-
-   partition@514 {
-   label = "usrdata";
-   reg = <0x514 0x100>;
-   };
-   };
-   };
-};
diff --git a/arch/arm/boot/dts/mt7623n-rfb.dtsi 
b/arch/arm/boot/dts/mt7623n-rfb.dtsi
deleted file mode 100644
index 5c5cc7d..000
--- a/arch/arm/boot/dts/mt7623n-rfb.dtsi
+++ /dev/null
@@ -1,86 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2017 MediaTek Inc.
- * Author: John Crispin 
- *Sean Wang 
- *
- */
-
-/dts-v1/;
-#include "mt7623.dtsi"
-#include "mt6323.dtsi"
-
-/ {
-   aliases {
-   serial0 = 
-   serial1 = 
-   serial2 = 
-   };
-
-   chosen {
-   stdout-path = "serial2:115200n8";
-   };
-
-   cpus {
-   cpu0 {
-   proc-supply = <_vproc_reg>;
-   };
-
-   cpu1 {
-   proc-supply = <_vproc_reg>;
-   };
-
-   cpu2 {
-   proc-supply = <_vproc_reg>;
-   };
-
-   cpu3 {
-   proc-supply = <_vproc_reg>;
-   };
-   };
-
-   memory@8000 {
-   device_type = "memory";
-   reg = <0 0x8000 0 0x4000>;
-   };
-
-   usb_p1_vbus: regulator-5v {
-

Re: [PATCH 2/2] dt-bindings: arm: mediatek: cleanup MT7623N reference boards

[John Crispin]

On 10/07/18 07:09, Ryder Lee wrote:

Cleanup binding document to get rid of unsupported reference boards
for MT7623N.

Cc: John Crispin 
Cc: Sean Wang 
Signed-off-by: Ryder Lee 

Acked-by: John Crispin 

---
  Documentation/devicetree/bindings/arm/mediatek.txt | 3 ---
  1 file changed, 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt 
b/Documentation/devicetree/bindings/arm/mediatek.txt
index 7d21ab3..c07ddf4 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek.txt
@@ -59,9 +59,6 @@ Supported boards:
  - Reference board for MT7623n with eMMC:
  Required root node properties:
- compatible = "mediatek,mt7623n-rfb-emmc", "mediatek,mt7623";
-- Reference  board for MT7623n with NAND:
-Required root node properties:
-  - compatible = "mediatek,mt7623n-rfb-nand", "mediatek,mt7623";
  - Bananapi BPI-R2 board:
- compatible = "bananapi,bpi-r2", "mediatek,mt7623";
  - MTK mt8127 tablet moose EVB:

Re: [PATCH 1/2] arm: dts: mt7623: cleanup MT7623N NAND dts file

[John Crispin]

On 10/07/18 07:09, Ryder Lee wrote:

Normally, we didn't release this kind of baord to user. This specific
board exists only in the early stage of development inside MediaTek -
and that may confuse peoples.

Hence this patch removes related files accordingly.

Cc: John Crispin 
Cc: Sean Wang 
Signed-off-by: Ryder Lee 

Acked-by: John Crispin 

---
  arch/arm/boot/dts/Makefile |  1 -
  arch/arm/boot/dts/mt7623n-rfb-nand.dts | 73 -
  arch/arm/boot/dts/mt7623n-rfb.dtsi | 86 --
  3 files changed, 160 deletions(-)
  delete mode 100644 arch/arm/boot/dts/mt7623n-rfb-nand.dts
  delete mode 100644 arch/arm/boot/dts/mt7623n-rfb.dtsi

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 37a3de7..dde494e 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1168,7 +1168,6 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7623a-rfb-emmc.dtb \
mt7623a-rfb-nand.dtb \
mt7623n-rfb-emmc.dtb \
-   mt7623n-rfb-nand.dtb \
mt7623n-bananapi-bpi-r2.dtb \
mt8127-moose.dtb \
mt8135-evbp1.dtb
diff --git a/arch/arm/boot/dts/mt7623n-rfb-nand.dts 
b/arch/arm/boot/dts/mt7623n-rfb-nand.dts
deleted file mode 100644
index 96ff3c9..000
--- a/arch/arm/boot/dts/mt7623n-rfb-nand.dts
+++ /dev/null
@@ -1,73 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2017 MediaTek Inc.
- * Author: John Crispin 
- *
- */
-
-/dts-v1/;
-#include "mt7623n-rfb.dtsi"
-
-/ {
-   model = "MediaTek MT7623N NAND reference board";
-   compatible = "mediatek,mt7623n-rfb-nand", "mediatek,mt7623";
-};
-
- {
-   status = "okay";
-};
-
- {
-   status = "okay";
-   pinctrl-names = "default";
-   pinctrl-0 = <_pins_default>;
-
-   nand@0 {
-   reg = <0>;
-   spare_per_sector = <64>;
-   nand-ecc-mode = "hw";
-   nand-ecc-strength = <12>;
-   nand-ecc-step-size = <1024>;
-
-   partitions {
-   compatible = "fixed-partitions";
-   #address-cells = <1>;
-   #size-cells = <1>;
-
-   partition@0 {
-   label = "preloader";
-   reg = <0x0 0x4>;
-   };
-
-   partition@4 {
-   label = "uboot";
-   reg = <0x4 0x8>;
-   };
-
-   partition@c {
-   label = "uboot-env";
-   reg = <0xC 0x4>;
-   };
-
-   partition@14 {
-   label = "bootimg";
-   reg = <0x14 0x200>;
-   };
-
-   partition@214 {
-   label = "recovery";
-   reg = <0x214 0x200>;
-   };
-
-   partition@414 {
-   label = "rootfs";
-   reg = <0x414 0x100>;
-   };
-
-   partition@514 {
-   label = "usrdata";
-   reg = <0x514 0x100>;
-   };
-   };
-   };
-};
diff --git a/arch/arm/boot/dts/mt7623n-rfb.dtsi 
b/arch/arm/boot/dts/mt7623n-rfb.dtsi
deleted file mode 100644
index 5c5cc7d..000
--- a/arch/arm/boot/dts/mt7623n-rfb.dtsi
+++ /dev/null
@@ -1,86 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2017 MediaTek Inc.
- * Author: John Crispin 
- *Sean Wang 
- *
- */
-
-/dts-v1/;
-#include "mt7623.dtsi"
-#include "mt6323.dtsi"
-
-/ {
-   aliases {
-   serial0 = 
-   serial1 = 
-   serial2 = 
-   };
-
-   chosen {
-   stdout-path = "serial2:115200n8";
-   };
-
-   cpus {
-   cpu0 {
-   proc-supply = <_vproc_reg>;
-   };
-
-   cpu1 {
-   proc-supply = <_vproc_reg>;
-   };
-
-   cpu2 {
-   proc-supply = <_vproc_reg>;
-   };
-
-   cpu3 {
-   proc-supply = <_vproc_reg>;
-   };
-   };
-
-   memory@8000 {
-   device_type = "memory";
-   reg = <0 0x8000 0 0x4000>;
-   };
-
-   usb_p1_vbus: regulator-5v {
-

[PATCH] irqchip/irq-ath79-intc: add irq cascade driver for QCA9556 SoCs

[John Crispin]

The QCA ATH79 MIPS target is being converted to pure OF. Right now the
platform code will setup the IRQ cascade found on the QCA9556 and newer
SoCs and uses fixed IRQ numbers for the peripherals attached to the
cascade. This patch adds a proper driver based on the code previously
located inside arch/mips/ath79/irq.c.

Signed-off-by: John Crispin <j...@phrozen.org>
---
 drivers/irqchip/Makefile |   1 +
 drivers/irqchip/irq-ath79-intc.c | 108 +++
 2 files changed, 109 insertions(+)
 create mode 100644 drivers/irqchip/irq-ath79-intc.c

diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index d27e3e3619e0..f63c94a92e25 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -3,6 +3,7 @@ obj-$(CONFIG_IRQCHIP)   += irqchip.o
 
 obj-$(CONFIG_ALPINE_MSI)   += irq-alpine-msi.o
 obj-$(CONFIG_ATH79)+= irq-ath79-cpu.o
+obj-$(CONFIG_ATH79)+= irq-ath79-intc.o
 obj-$(CONFIG_ATH79)+= irq-ath79-misc.o
 obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
 obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2836.o
diff --git a/drivers/irqchip/irq-ath79-intc.c b/drivers/irqchip/irq-ath79-intc.c
new file mode 100644
index ..ba15b1ac98b3
--- /dev/null
+++ b/drivers/irqchip/irq-ath79-intc.c
@@ -0,0 +1,108 @@
+/*
+ *  Atheros QCA955X specific interrupt cascade handling
+ *
+ *  Copyright (C) 2018 John Crispin <j...@phrozen.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+#define ATH79_MAX_INTC_CASCADE 3
+
+struct ath79_intc {
+   struct irq_chip chip;
+   u32 irq;
+   u32 pending_mask;
+   u32 irq_mask[ATH79_MAX_INTC_CASCADE];
+};
+
+static void ath79_intc_irq_handler(struct irq_desc *desc)
+{
+   struct irq_domain *domain = irq_desc_get_handler_data(desc);
+   struct ath79_intc *intc = domain->host_data;
+   u32 pending;
+
+   pending = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS);
+   pending &= intc->pending_mask;
+
+   if (pending) {
+   int i;
+
+   for (i = 0; i < domain->hwirq_max; i++)
+   if (pending & intc->irq_mask[i])
+   generic_handle_irq(irq_find_mapping(domain, i));
+   } else {
+   spurious_interrupt();
+   }
+}
+
+static void ath79_intc_irq_unmask(struct irq_data *d)
+{
+}
+
+static void ath79_intc_irq_mask(struct irq_data *d)
+{
+}
+
+static int ath79_intc_map(struct irq_domain *d, unsigned int irq,
+ irq_hw_number_t hw)
+{
+   struct ath79_intc *intc = d->host_data;
+
+   irq_set_chip_and_handler(irq, >chip, handle_level_irq);
+
+   return 0;
+}
+
+static const struct irq_domain_ops ath79_irq_domain_ops = {
+   .xlate = irq_domain_xlate_onecell,
+   .map = ath79_intc_map,
+};
+
+static int __init qca9556_intc_of_init(
+   struct device_node *node, struct device_node *parent)
+{
+   struct irq_domain *domain;
+   struct ath79_intc *intc;
+   int cnt, i;
+
+   cnt = of_property_count_u32_elems(node, "qcom,pending-bits");
+   if (cnt > ATH79_MAX_INTC_CASCADE)
+   panic("Too many INTC pending bits\n");
+
+   intc = kzalloc(sizeof(*intc), GFP_KERNEL);
+   if (!intc)
+   panic("Failed to allocate INTC memory\n");
+   intc->chip.name = "INTC";
+   intc->chip.irq_unmask = ath79_intc_irq_unmask,
+   intc->chip.irq_mask = ath79_intc_irq_mask,
+
+   of_property_read_u32_array(node, "qcom,pending-bits", intc->irq_mask,
+  cnt);
+   for (i = 0; i < cnt; i++)
+   intc->pending_mask |= intc->irq_mask[i];
+
+   intc->irq = irq_of_parse_and_map(node, 0);
+   if (!intc->irq)
+   panic("Failed to get INTC IRQ");
+
+   domain = irq_domain_add_linear(node, cnt, _irq_domain_ops,
+  intc);
+   irq_set_chained_handler_and_data(intc->irq, ath79_intc_irq_handler,
+domain);
+
+   return 0;
+}
+IRQCHIP_DECLARE(qca9556_intc, "qcom,qca9556-intc",
+   qca9556_intc_of_init);
-- 
2.11.0

[PATCH] irqchip/irq-ath79-intc: add irq cascade driver for QCA9556 SoCs

[John Crispin]

The QCA ATH79 MIPS target is being converted to pure OF. Right now the
platform code will setup the IRQ cascade found on the QCA9556 and newer
SoCs and uses fixed IRQ numbers for the peripherals attached to the
cascade. This patch adds a proper driver based on the code previously
located inside arch/mips/ath79/irq.c.

Signed-off-by: John Crispin 
---
 drivers/irqchip/Makefile |   1 +
 drivers/irqchip/irq-ath79-intc.c | 108 +++
 2 files changed, 109 insertions(+)
 create mode 100644 drivers/irqchip/irq-ath79-intc.c

diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index d27e3e3619e0..f63c94a92e25 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -3,6 +3,7 @@ obj-$(CONFIG_IRQCHIP)   += irqchip.o
 
 obj-$(CONFIG_ALPINE_MSI)   += irq-alpine-msi.o
 obj-$(CONFIG_ATH79)+= irq-ath79-cpu.o
+obj-$(CONFIG_ATH79)+= irq-ath79-intc.o
 obj-$(CONFIG_ATH79)+= irq-ath79-misc.o
 obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
 obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2836.o
diff --git a/drivers/irqchip/irq-ath79-intc.c b/drivers/irqchip/irq-ath79-intc.c
new file mode 100644
index ..ba15b1ac98b3
--- /dev/null
+++ b/drivers/irqchip/irq-ath79-intc.c
@@ -0,0 +1,108 @@
+/*
+ *  Atheros QCA955X specific interrupt cascade handling
+ *
+ *  Copyright (C) 2018 John Crispin 
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+#define ATH79_MAX_INTC_CASCADE 3
+
+struct ath79_intc {
+   struct irq_chip chip;
+   u32 irq;
+   u32 pending_mask;
+   u32 irq_mask[ATH79_MAX_INTC_CASCADE];
+};
+
+static void ath79_intc_irq_handler(struct irq_desc *desc)
+{
+   struct irq_domain *domain = irq_desc_get_handler_data(desc);
+   struct ath79_intc *intc = domain->host_data;
+   u32 pending;
+
+   pending = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS);
+   pending &= intc->pending_mask;
+
+   if (pending) {
+   int i;
+
+   for (i = 0; i < domain->hwirq_max; i++)
+   if (pending & intc->irq_mask[i])
+   generic_handle_irq(irq_find_mapping(domain, i));
+   } else {
+   spurious_interrupt();
+   }
+}
+
+static void ath79_intc_irq_unmask(struct irq_data *d)
+{
+}
+
+static void ath79_intc_irq_mask(struct irq_data *d)
+{
+}
+
+static int ath79_intc_map(struct irq_domain *d, unsigned int irq,
+ irq_hw_number_t hw)
+{
+   struct ath79_intc *intc = d->host_data;
+
+   irq_set_chip_and_handler(irq, >chip, handle_level_irq);
+
+   return 0;
+}
+
+static const struct irq_domain_ops ath79_irq_domain_ops = {
+   .xlate = irq_domain_xlate_onecell,
+   .map = ath79_intc_map,
+};
+
+static int __init qca9556_intc_of_init(
+   struct device_node *node, struct device_node *parent)
+{
+   struct irq_domain *domain;
+   struct ath79_intc *intc;
+   int cnt, i;
+
+   cnt = of_property_count_u32_elems(node, "qcom,pending-bits");
+   if (cnt > ATH79_MAX_INTC_CASCADE)
+   panic("Too many INTC pending bits\n");
+
+   intc = kzalloc(sizeof(*intc), GFP_KERNEL);
+   if (!intc)
+   panic("Failed to allocate INTC memory\n");
+   intc->chip.name = "INTC";
+   intc->chip.irq_unmask = ath79_intc_irq_unmask,
+   intc->chip.irq_mask = ath79_intc_irq_mask,
+
+   of_property_read_u32_array(node, "qcom,pending-bits", intc->irq_mask,
+  cnt);
+   for (i = 0; i < cnt; i++)
+   intc->pending_mask |= intc->irq_mask[i];
+
+   intc->irq = irq_of_parse_and_map(node, 0);
+   if (!intc->irq)
+   panic("Failed to get INTC IRQ");
+
+   domain = irq_domain_add_linear(node, cnt, _irq_domain_ops,
+  intc);
+   irq_set_chained_handler_and_data(intc->irq, ath79_intc_irq_handler,
+domain);
+
+   return 0;
+}
+IRQCHIP_DECLARE(qca9556_intc, "qcom,qca9556-intc",
+   qca9556_intc_of_init);
-- 
2.11.0

Re: [PATCH 00/13] staging: add drivers to support Mediatek mt7621 in gnubee-pc1

[John Crispin]

On 15/03/18 21:12, NeilBrown wrote:

On Thu, Mar 15 2018, John Crispin wrote:


On 15/03/18 11:48, Dan Carpenter wrote:

This all seems fine.  Generally the requirements for staging are that it
has a TODO, someone to work on it, and it doesn't break the build.  But
some of the patches don't have commit message and those are required and
some of the commit messages are just the changes you have made not don't
describe the actual code...

John Crispin's email is j...@phrozen.org.

regards,
dan carpenter


Hi All,

looks like i was CC'ed on the openwrt addr, which no longer exists. This
series makes no sense. None of the stuff posted is anywhere near ready
to be upstreamed.

* we dont need a dedicated pinctrl driver, pinctrl-single will work fine
on these SoCs
* the DMA/sdhci driver is a hacked up version of the SDK driver.
* drivers/net/ethernet/mediatek/* works on mt7623 and is easily portable
to mt7621, same goes for the gsw driver.

Hi John,
  I think it makes sense in that, with the patches, the hardware works, and
  without the patches (at least the first) you cannot even build with
  CONFIG_SOC_MT7621=y as pcibios_map_irq() is undefined.  Having
  working code is a great starting point for further development.
  It certainly isn't ready for upstream, which is why it is heading for
  drivers/staging.  This is explicitly for code that isn't yet ready.
  By putting the code there it should be safe from bit-rot, and can be
  worked on by multiple people.  It gets increased visibility so people
  can say how bad it is (as you have done - thanks).  This feed back is a
  valuable part of improving the code and getting it out of staging.

  I'll add notes to various TODO files based on your comments.  If you
  have anything else to add, it would be most welcome.  Thank you for
  making these patches available in the first place, so that my hardware
  can work!

Thanks,
NeilBrown


Hi Neil,

I understand your reasoning, however ...
only the pcie driver is worth merging. all other drivers are already 
inside the kernel for mt7623 and can be easily adapted to work on 
mt7621. having duplicate drivers is a certain no-go.
cleaning up the pci driver is a matter of a few days work. merging a 
shitty pci driver just to postpone doing the 3-5 days work involved to 
polish it seems a rally bad trade-off.
i strongly oppose having any of this code merged into the kernel, even 
if it is only the staging area.


    John

Re: [PATCH 00/13] staging: add drivers to support Mediatek mt7621 in gnubee-pc1

[John Crispin]

On 15/03/18 21:12, NeilBrown wrote:

On Thu, Mar 15 2018, John Crispin wrote:


On 15/03/18 11:48, Dan Carpenter wrote:

This all seems fine.  Generally the requirements for staging are that it
has a TODO, someone to work on it, and it doesn't break the build.  But
some of the patches don't have commit message and those are required and
some of the commit messages are just the changes you have made not don't
describe the actual code...

John Crispin's email is j...@phrozen.org.

regards,
dan carpenter


Hi All,

looks like i was CC'ed on the openwrt addr, which no longer exists. This
series makes no sense. None of the stuff posted is anywhere near ready
to be upstreamed.

* we dont need a dedicated pinctrl driver, pinctrl-single will work fine
on these SoCs
* the DMA/sdhci driver is a hacked up version of the SDK driver.
* drivers/net/ethernet/mediatek/* works on mt7623 and is easily portable
to mt7621, same goes for the gsw driver.

Hi John,
  I think it makes sense in that, with the patches, the hardware works, and
  without the patches (at least the first) you cannot even build with
  CONFIG_SOC_MT7621=y as pcibios_map_irq() is undefined.  Having
  working code is a great starting point for further development.
  It certainly isn't ready for upstream, which is why it is heading for
  drivers/staging.  This is explicitly for code that isn't yet ready.
  By putting the code there it should be safe from bit-rot, and can be
  worked on by multiple people.  It gets increased visibility so people
  can say how bad it is (as you have done - thanks).  This feed back is a
  valuable part of improving the code and getting it out of staging.

  I'll add notes to various TODO files based on your comments.  If you
  have anything else to add, it would be most welcome.  Thank you for
  making these patches available in the first place, so that my hardware
  can work!

Thanks,
NeilBrown


Hi Neil,

I understand your reasoning, however ...
only the pcie driver is worth merging. all other drivers are already 
inside the kernel for mt7623 and can be easily adapted to work on 
mt7621. having duplicate drivers is a certain no-go.
cleaning up the pci driver is a matter of a few days work. merging a 
shitty pci driver just to postpone doing the 3-5 days work involved to 
polish it seems a rally bad trade-off.
i strongly oppose having any of this code merged into the kernel, even 
if it is only the staging area.


    John

Re: [PATCH 00/13] staging: add drivers to support Mediatek mt7621 in gnubee-pc1

[John Crispin]

On 15/03/18 11:48, Dan Carpenter wrote:

This all seems fine.  Generally the requirements for staging are that it
has a TODO, someone to work on it, and it doesn't break the build.  But
some of the patches don't have commit message and those are required and
some of the commit messages are just the changes you have made not don't
describe the actual code...

John Crispin's email is j...@phrozen.org.

regards,
dan carpenter


Hi All,

looks like i was CC'ed on the openwrt addr, which no longer exists. This 
series makes no sense. None of the stuff posted is anywhere near ready 
to be upstreamed.


* we dont need a dedicated pinctrl driver, pinctrl-single will work fine 
on these SoCs

* the DMA/sdhci driver is a hacked up version of the SDK driver.
* drivers/net/ethernet/mediatek/* works on mt7623 and is easily portable 
to mt7621, same goes for the gsw driver.


    John

Re: [PATCH 00/13] staging: add drivers to support Mediatek mt7621 in gnubee-pc1

[John Crispin]

On 15/03/18 11:48, Dan Carpenter wrote:

This all seems fine.  Generally the requirements for staging are that it
has a TODO, someone to work on it, and it doesn't break the build.  But
some of the patches don't have commit message and those are required and
some of the commit messages are just the changes you have made not don't
describe the actual code...

John Crispin's email is j...@phrozen.org.

regards,
dan carpenter


Hi All,

looks like i was CC'ed on the openwrt addr, which no longer exists. This 
series makes no sense. None of the stuff posted is anywhere near ready 
to be upstreamed.


* we dont need a dedicated pinctrl driver, pinctrl-single will work fine 
on these SoCs

* the DMA/sdhci driver is a hacked up version of the SDK driver.
* drivers/net/ethernet/mediatek/* works on mt7623 and is easily portable 
to mt7621, same goes for the gsw driver.


    John

Re: [PATCH] MIPS: mt7620: Rename uartlite to serial

[John Crispin]

Hi,


comments inline


On 01/09/17 16:53, Harvey Hunt wrote:

Previously, mt7620.c defined the clocks for uarts with the names
uartlite, uart1 and uart2. Rename them to serial{0,1,2} and update
the devicetree node names.

Signed-off-by: Harvey Hunt 
Cc: devicet...@vger.kernel.org
Cc: linux-m...@linux-mips.org
Cc: linux-kernel@vger.kernel.org
---
  arch/mips/boot/dts/ralink/mt7620a.dtsi |  2 +-
  arch/mips/boot/dts/ralink/mt7628a.dtsi |  6 +++---
  arch/mips/ralink/mt7620.c  | 14 +++---
  3 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/arch/mips/boot/dts/ralink/mt7620a.dtsi 
b/arch/mips/boot/dts/ralink/mt7620a.dtsi
index 793c0c7..58bd002 100644
--- a/arch/mips/boot/dts/ralink/mt7620a.dtsi
+++ b/arch/mips/boot/dts/ralink/mt7620a.dtsi
@@ -45,7 +45,7 @@
reg = <0x300 0x100>;
};
  
-		uartlite@c00 {

+   serial0@c00 {
the uartlite is indeed not a full uart, having only rx/tx lines and 
missing various other features. i would prefer to keep it as is. you 
cannot connect a modem to the port for example as that would require HW 
handshake for example. Also making these changes will break 
compatibility with existing devicetrees.


John


compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", 
"ns16550a";
reg = <0xc00 0x100>;
  
diff --git a/arch/mips/boot/dts/ralink/mt7628a.dtsi b/arch/mips/boot/dts/ralink/mt7628a.dtsi

index 9ff7e8f..fe3fe9a 100644
--- a/arch/mips/boot/dts/ralink/mt7628a.dtsi
+++ b/arch/mips/boot/dts/ralink/mt7628a.dtsi
@@ -62,7 +62,7 @@
reg = <0x300 0x100>;
};
  
-		uart0: uartlite@c00 {

+   uart0: serial0@c00 {
compatible = "ns16550a";
reg = <0xc00 0x100>;
  
@@ -75,7 +75,7 @@

reg-shift = <2>;
};
  
-		uart1: uart1@d00 {

+   uart1: serial1@d00 {
compatible = "ns16550a";
reg = <0xd00 0x100>;
  
@@ -88,7 +88,7 @@

reg-shift = <2>;
};
  
-		uart2: uart2@e00 {

+   uart2: serial2@e00 {
compatible = "ns16550a";
reg = <0xe00 0x100>;
  
diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c

index 9be8b08..f623ceb 100644
--- a/arch/mips/ralink/mt7620.c
+++ b/arch/mips/ralink/mt7620.c
@@ -54,7 +54,7 @@ static int dram_type;
  
  static struct rt2880_pmx_func i2c_grp[] =  { FUNC("i2c", 0, 1, 2) };

  static struct rt2880_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) };
-static struct rt2880_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) };
+static struct rt2880_pmx_func serial_grp[] = { FUNC("serial", 0, 15, 2) };
  static struct rt2880_pmx_func mdio_grp[] = {
FUNC("mdio", MT7620_GPIO_MODE_MDIO, 22, 2),
FUNC("refclk", MT7620_GPIO_MODE_MDIO_REFCLK, 22, 2),
@@ -92,7 +92,7 @@ static struct rt2880_pmx_group mt7620a_pinmux_data[] = {
GRP("uartf", uartf_grp, MT7620_GPIO_MODE_UART0_MASK,
MT7620_GPIO_MODE_UART0_SHIFT),
GRP("spi", spi_grp, 1, MT7620_GPIO_MODE_SPI),
-   GRP("uartlite", uartlite_grp, 1, MT7620_GPIO_MODE_UART1),
+   GRP("serial", serial_grp, 1, MT7620_GPIO_MODE_UART1),
GRP_G("wdt", wdt_grp, MT7620_GPIO_MODE_WDT_MASK,
MT7620_GPIO_MODE_WDT_GPIO, MT7620_GPIO_MODE_WDT_SHIFT),
GRP_G("mdio", mdio_grp, MT7620_GPIO_MODE_MDIO_MASK,
@@ -530,8 +530,8 @@ void __init ralink_clk_init(void)
periph_rate = MHZ(40);
pcmi2s_rate = MHZ(480);
  
-		ralink_clk_add("1d00.uartlite", periph_rate);

-   ralink_clk_add("1e00.uartlite", periph_rate);
+   ralink_clk_add("1d00.serial0", periph_rate);
+   ralink_clk_add("1e00.serial0", periph_rate);
} else {
cpu_pll_rate = mt7620_get_cpu_pll_rate(xtal_rate);
pll_rate = mt7620_get_pll_rate(xtal_rate, cpu_pll_rate);
@@ -566,9 +566,9 @@ void __init ralink_clk_init(void)
ralink_clk_add("1a00.i2s", pcmi2s_rate);
ralink_clk_add("1b00.spi", sys_rate);
ralink_clk_add("1b40.spi", sys_rate);
-   ralink_clk_add("1c00.uartlite", periph_rate);
-   ralink_clk_add("1d00.uart1", periph_rate);
-   ralink_clk_add("1e00.uart2", periph_rate);
+   ralink_clk_add("1c00.serial0", periph_rate);
+   ralink_clk_add("1d00.serial1", periph_rate);
+   ralink_clk_add("1e00.serial2", periph_rate);
ralink_clk_add("1018.wmac", xtal_rate);
  
  	if (IS_ENABLED(CONFIG_USB) && !is_mt76x8()) {

Re: [PATCH] MIPS: mt7620: Rename uartlite to serial

[John Crispin]

Hi,


comments inline


On 01/09/17 16:53, Harvey Hunt wrote:

Previously, mt7620.c defined the clocks for uarts with the names
uartlite, uart1 and uart2. Rename them to serial{0,1,2} and update
the devicetree node names.

Signed-off-by: Harvey Hunt 
Cc: devicet...@vger.kernel.org
Cc: linux-m...@linux-mips.org
Cc: linux-kernel@vger.kernel.org
---
  arch/mips/boot/dts/ralink/mt7620a.dtsi |  2 +-
  arch/mips/boot/dts/ralink/mt7628a.dtsi |  6 +++---
  arch/mips/ralink/mt7620.c  | 14 +++---
  3 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/arch/mips/boot/dts/ralink/mt7620a.dtsi 
b/arch/mips/boot/dts/ralink/mt7620a.dtsi
index 793c0c7..58bd002 100644
--- a/arch/mips/boot/dts/ralink/mt7620a.dtsi
+++ b/arch/mips/boot/dts/ralink/mt7620a.dtsi
@@ -45,7 +45,7 @@
reg = <0x300 0x100>;
};
  
-		uartlite@c00 {

+   serial0@c00 {
the uartlite is indeed not a full uart, having only rx/tx lines and 
missing various other features. i would prefer to keep it as is. you 
cannot connect a modem to the port for example as that would require HW 
handshake for example. Also making these changes will break 
compatibility with existing devicetrees.


John


compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", 
"ns16550a";
reg = <0xc00 0x100>;
  
diff --git a/arch/mips/boot/dts/ralink/mt7628a.dtsi b/arch/mips/boot/dts/ralink/mt7628a.dtsi

index 9ff7e8f..fe3fe9a 100644
--- a/arch/mips/boot/dts/ralink/mt7628a.dtsi
+++ b/arch/mips/boot/dts/ralink/mt7628a.dtsi
@@ -62,7 +62,7 @@
reg = <0x300 0x100>;
};
  
-		uart0: uartlite@c00 {

+   uart0: serial0@c00 {
compatible = "ns16550a";
reg = <0xc00 0x100>;
  
@@ -75,7 +75,7 @@

reg-shift = <2>;
};
  
-		uart1: uart1@d00 {

+   uart1: serial1@d00 {
compatible = "ns16550a";
reg = <0xd00 0x100>;
  
@@ -88,7 +88,7 @@

reg-shift = <2>;
};
  
-		uart2: uart2@e00 {

+   uart2: serial2@e00 {
compatible = "ns16550a";
reg = <0xe00 0x100>;
  
diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c

index 9be8b08..f623ceb 100644
--- a/arch/mips/ralink/mt7620.c
+++ b/arch/mips/ralink/mt7620.c
@@ -54,7 +54,7 @@ static int dram_type;
  
  static struct rt2880_pmx_func i2c_grp[] =  { FUNC("i2c", 0, 1, 2) };

  static struct rt2880_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) };
-static struct rt2880_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) };
+static struct rt2880_pmx_func serial_grp[] = { FUNC("serial", 0, 15, 2) };
  static struct rt2880_pmx_func mdio_grp[] = {
FUNC("mdio", MT7620_GPIO_MODE_MDIO, 22, 2),
FUNC("refclk", MT7620_GPIO_MODE_MDIO_REFCLK, 22, 2),
@@ -92,7 +92,7 @@ static struct rt2880_pmx_group mt7620a_pinmux_data[] = {
GRP("uartf", uartf_grp, MT7620_GPIO_MODE_UART0_MASK,
MT7620_GPIO_MODE_UART0_SHIFT),
GRP("spi", spi_grp, 1, MT7620_GPIO_MODE_SPI),
-   GRP("uartlite", uartlite_grp, 1, MT7620_GPIO_MODE_UART1),
+   GRP("serial", serial_grp, 1, MT7620_GPIO_MODE_UART1),
GRP_G("wdt", wdt_grp, MT7620_GPIO_MODE_WDT_MASK,
MT7620_GPIO_MODE_WDT_GPIO, MT7620_GPIO_MODE_WDT_SHIFT),
GRP_G("mdio", mdio_grp, MT7620_GPIO_MODE_MDIO_MASK,
@@ -530,8 +530,8 @@ void __init ralink_clk_init(void)
periph_rate = MHZ(40);
pcmi2s_rate = MHZ(480);
  
-		ralink_clk_add("1d00.uartlite", periph_rate);

-   ralink_clk_add("1e00.uartlite", periph_rate);
+   ralink_clk_add("1d00.serial0", periph_rate);
+   ralink_clk_add("1e00.serial0", periph_rate);
} else {
cpu_pll_rate = mt7620_get_cpu_pll_rate(xtal_rate);
pll_rate = mt7620_get_pll_rate(xtal_rate, cpu_pll_rate);
@@ -566,9 +566,9 @@ void __init ralink_clk_init(void)
ralink_clk_add("1a00.i2s", pcmi2s_rate);
ralink_clk_add("1b00.spi", sys_rate);
ralink_clk_add("1b40.spi", sys_rate);
-   ralink_clk_add("1c00.uartlite", periph_rate);
-   ralink_clk_add("1d00.uart1", periph_rate);
-   ralink_clk_add("1e00.uart2", periph_rate);
+   ralink_clk_add("1c00.serial0", periph_rate);
+   ralink_clk_add("1d00.serial1", periph_rate);
+   ralink_clk_add("1e00.serial2", periph_rate);
ralink_clk_add("1018.wmac", xtal_rate);
  
  	if (IS_ENABLED(CONFIG_USB) && !is_mt76x8()) {

Re: [PATCH] phy: ralink: fix 64-bit build warning

[John Crispin]

On 23/08/17 15:39, Arnd Bergmann wrote:

Casting between an 'int' and a pointer causes a warning on
64-bit architectures in compile-testing this driver:

drivers/phy/ralink/phy-ralink-usb.c: In function 'ralink_usb_phy_probe':
drivers/phy/ralink/phy-ralink-usb.c:195:13: error: cast from pointer to integer 
of different size [-Werror=pointer-to-int-cast]

This changes the code to cast to uintptr_t instead. This is
guaranteed to do what we want on all architectures and avoids
the warning.

Fixes: 2411a736ff09 ("phy: ralink-usb: add driver for Mediatek/Ralink")
Signed-off-by: Arnd Bergmann <a...@arndb.de>

Acked-by: John Crispin <j...@phrozen.org>

gregkh: can you fold this into the commit sitting inside usb-next ?




---
  drivers/phy/ralink/phy-ralink-usb.c | 14 +++---
  1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/phy/ralink/phy-ralink-usb.c 
b/drivers/phy/ralink/phy-ralink-usb.c
index d19088c0ce5c..4fea31f8ac1c 100644
--- a/drivers/phy/ralink/phy-ralink-usb.c
+++ b/drivers/phy/ralink/phy-ralink-usb.c
@@ -160,18 +160,18 @@ static struct phy_ops ralink_usb_phy_ops = {
  static const struct of_device_id ralink_usb_phy_of_match[] = {
{
.compatible = "ralink,rt3352-usbphy",
-   .data = (void *) (RT_CLKCFG1_UPHY1_CLK_EN |
- RT_CLKCFG1_UPHY0_CLK_EN)
+   .data = (void *)(uintptr_t)(RT_CLKCFG1_UPHY1_CLK_EN |
+   RT_CLKCFG1_UPHY0_CLK_EN)
},
{
.compatible = "mediatek,mt7620-usbphy",
-   .data = (void *) (MT7620_CLKCFG1_UPHY1_CLK_EN |
- MT7620_CLKCFG1_UPHY0_CLK_EN)
+   .data = (void *)(uintptr_t)(MT7620_CLKCFG1_UPHY1_CLK_EN |
+   MT7620_CLKCFG1_UPHY0_CLK_EN)
},
{
.compatible = "mediatek,mt7628-usbphy",
-   .data = (void *) (MT7620_CLKCFG1_UPHY1_CLK_EN |
- MT7620_CLKCFG1_UPHY0_CLK_EN) },
+   .data = (void *)(uintptr_t)(MT7620_CLKCFG1_UPHY1_CLK_EN |
+   MT7620_CLKCFG1_UPHY0_CLK_EN) },
{ },
  };
  MODULE_DEVICE_TABLE(of, ralink_usb_phy_of_match);
@@ -192,7 +192,7 @@ static int ralink_usb_phy_probe(struct platform_device 
*pdev)
if (!phy)
return -ENOMEM;
  
-	phy->clk = (u32) match->data;

+   phy->clk = (uintptr_t)match->data;
phy->base = NULL;
  
  	phy->sysctl = syscon_regmap_lookup_by_phandle(dev->of_node, "ralink,sysctl");

Re: [PATCH] phy: ralink: fix 64-bit build warning

[John Crispin]

On 23/08/17 15:39, Arnd Bergmann wrote:

Casting between an 'int' and a pointer causes a warning on
64-bit architectures in compile-testing this driver:

drivers/phy/ralink/phy-ralink-usb.c: In function 'ralink_usb_phy_probe':
drivers/phy/ralink/phy-ralink-usb.c:195:13: error: cast from pointer to integer 
of different size [-Werror=pointer-to-int-cast]

This changes the code to cast to uintptr_t instead. This is
guaranteed to do what we want on all architectures and avoids
the warning.

Fixes: 2411a736ff09 ("phy: ralink-usb: add driver for Mediatek/Ralink")
Signed-off-by: Arnd Bergmann 

Acked-by: John Crispin 

gregkh: can you fold this into the commit sitting inside usb-next ?




---
  drivers/phy/ralink/phy-ralink-usb.c | 14 +++---
  1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/phy/ralink/phy-ralink-usb.c 
b/drivers/phy/ralink/phy-ralink-usb.c
index d19088c0ce5c..4fea31f8ac1c 100644
--- a/drivers/phy/ralink/phy-ralink-usb.c
+++ b/drivers/phy/ralink/phy-ralink-usb.c
@@ -160,18 +160,18 @@ static struct phy_ops ralink_usb_phy_ops = {
  static const struct of_device_id ralink_usb_phy_of_match[] = {
{
.compatible = "ralink,rt3352-usbphy",
-   .data = (void *) (RT_CLKCFG1_UPHY1_CLK_EN |
- RT_CLKCFG1_UPHY0_CLK_EN)
+   .data = (void *)(uintptr_t)(RT_CLKCFG1_UPHY1_CLK_EN |
+   RT_CLKCFG1_UPHY0_CLK_EN)
},
{
.compatible = "mediatek,mt7620-usbphy",
-   .data = (void *) (MT7620_CLKCFG1_UPHY1_CLK_EN |
- MT7620_CLKCFG1_UPHY0_CLK_EN)
+   .data = (void *)(uintptr_t)(MT7620_CLKCFG1_UPHY1_CLK_EN |
+   MT7620_CLKCFG1_UPHY0_CLK_EN)
},
{
.compatible = "mediatek,mt7628-usbphy",
-   .data = (void *) (MT7620_CLKCFG1_UPHY1_CLK_EN |
- MT7620_CLKCFG1_UPHY0_CLK_EN) },
+   .data = (void *)(uintptr_t)(MT7620_CLKCFG1_UPHY1_CLK_EN |
+   MT7620_CLKCFG1_UPHY0_CLK_EN) },
{ },
  };
  MODULE_DEVICE_TABLE(of, ralink_usb_phy_of_match);
@@ -192,7 +192,7 @@ static int ralink_usb_phy_probe(struct platform_device 
*pdev)
if (!phy)
return -ENOMEM;
  
-	phy->clk = (u32) match->data;

+   phy->clk = (uintptr_t)match->data;
phy->base = NULL;
  
  	phy->sysctl = syscon_regmap_lookup_by_phandle(dev->of_node, "ralink,sysctl");

Re: [PATCH 0/4] net-next: dsa: fix flow dissection

[John Crispin]

On 10/08/17 08:42, Eric Dumazet wrote:

On Wed, 2017-08-09 at 22:52 -0700, David Miller wrote:

From: John Crispin <j...@phrozen.org>
Date: Wed,  9 Aug 2017 14:41:15 +0200


RPS and probably other kernel features are currently broken on some if not
all DSA devices. The root cause of this is that skb_hash will call the
flow_dissector. At this point the skb still contains the magic switch
header and the skb->protocol field is not set up to the correct 802.3
value yet. By the time the tag specific code is called, removing the header
and properly setting the protocol an invalid hash is already set. In the
case of the mt7530 this will result in all flows always having the same
hash.

Changes since RFC:
* use a callback instead of static values
* add cover letter

Series applied, thanks.

Is this related ?

net/core/flow_dissector.c: In function '__skb_flow_dissect':
net/core/flow_dissector.c:448:18: error: 'struct net_device' has no member 
named 'dsa_ptr'
 ops = skb->dev->dsa_ptr->tag_ops;
   ^
make[3]: *** [net/core/flow_dissector.o] Error 1



Hi Eric,

I have just sent the fix for this compile error

John

Re: [PATCH 0/4] net-next: dsa: fix flow dissection

[John Crispin]

On 10/08/17 08:42, Eric Dumazet wrote:

On Wed, 2017-08-09 at 22:52 -0700, David Miller wrote:

From: John Crispin 
Date: Wed,  9 Aug 2017 14:41:15 +0200


RPS and probably other kernel features are currently broken on some if not
all DSA devices. The root cause of this is that skb_hash will call the
flow_dissector. At this point the skb still contains the magic switch
header and the skb->protocol field is not set up to the correct 802.3
value yet. By the time the tag specific code is called, removing the header
and properly setting the protocol an invalid hash is already set. In the
case of the mt7530 this will result in all flows always having the same
hash.

Changes since RFC:
* use a callback instead of static values
* add cover letter

Series applied, thanks.

Is this related ?

net/core/flow_dissector.c: In function '__skb_flow_dissect':
net/core/flow_dissector.c:448:18: error: 'struct net_device' has no member 
named 'dsa_ptr'
 ops = skb->dev->dsa_ptr->tag_ops;
   ^
make[3]: *** [net/core/flow_dissector.o] Error 1



Hi Eric,

I have just sent the fix for this compile error

John

[PATCH net-next] net: core: fix compile error inside flow_dissector due to new dsa callback

[John Crispin]

The following error was introduced by
commit 43e665287f93 ("net-next: dsa: fix flow dissection")
due to a missing #if guard

net/core/flow_dissector.c: In function '__skb_flow_dissect':
net/core/flow_dissector.c:448:18: error: 'struct net_device' has no member 
named 'dsa_ptr'
ops = skb->dev->dsa_ptr->tag_ops;
^
make[3]: *** [net/core/flow_dissector.o] Error 1

Signed-off-by: John Crispin <j...@phrozen.org>
---
 net/core/flow_dissector.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/net/core/flow_dissector.c b/net/core/flow_dissector.c
index 5b5be9577257..79b9c06c83ad 100644
--- a/net/core/flow_dissector.c
+++ b/net/core/flow_dissector.c
@@ -441,6 +441,7 @@ bool __skb_flow_dissect(const struct sk_buff *skb,
 skb->vlan_proto : skb->protocol;
nhoff = skb_network_offset(skb);
hlen = skb_headlen(skb);
+#if IS_ENABLED(CONFIG_NET_DSA)
if (unlikely(netdev_uses_dsa(skb->dev))) {
const struct dsa_device_ops *ops;
int offset;
@@ -452,6 +453,7 @@ bool __skb_flow_dissect(const struct sk_buff *skb,
nhoff += offset;
}
}
+#endif
}
 
/* It is ensured by skb_flow_dissector_init() that control key will
-- 
2.11.0

[PATCH net-next] net: core: fix compile error inside flow_dissector due to new dsa callback

[John Crispin]

The following error was introduced by
commit 43e665287f93 ("net-next: dsa: fix flow dissection")
due to a missing #if guard

net/core/flow_dissector.c: In function '__skb_flow_dissect':
net/core/flow_dissector.c:448:18: error: 'struct net_device' has no member 
named 'dsa_ptr'
ops = skb->dev->dsa_ptr->tag_ops;
^
make[3]: *** [net/core/flow_dissector.o] Error 1

Signed-off-by: John Crispin 
---
 net/core/flow_dissector.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/net/core/flow_dissector.c b/net/core/flow_dissector.c
index 5b5be9577257..79b9c06c83ad 100644
--- a/net/core/flow_dissector.c
+++ b/net/core/flow_dissector.c
@@ -441,6 +441,7 @@ bool __skb_flow_dissect(const struct sk_buff *skb,
 skb->vlan_proto : skb->protocol;
nhoff = skb_network_offset(skb);
hlen = skb_headlen(skb);
+#if IS_ENABLED(CONFIG_NET_DSA)
if (unlikely(netdev_uses_dsa(skb->dev))) {
const struct dsa_device_ops *ops;
int offset;
@@ -452,6 +453,7 @@ bool __skb_flow_dissect(const struct sk_buff *skb,
nhoff += offset;
}
}
+#endif
}
 
/* It is ensured by skb_flow_dissector_init() that control key will
-- 
2.11.0

Re: [PATCH 0/4] net-next: dsa: fix flow dissection

[John Crispin]

On 10/08/17 08:42, Eric Dumazet wrote:

On Wed, 2017-08-09 at 22:52 -0700, David Miller wrote:

From: John Crispin <j...@phrozen.org>
Date: Wed,  9 Aug 2017 14:41:15 +0200


RPS and probably other kernel features are currently broken on some if not
all DSA devices. The root cause of this is that skb_hash will call the
flow_dissector. At this point the skb still contains the magic switch
header and the skb->protocol field is not set up to the correct 802.3
value yet. By the time the tag specific code is called, removing the header
and properly setting the protocol an invalid hash is already set. In the
case of the mt7530 this will result in all flows always having the same
hash.

Changes since RFC:
* use a callback instead of static values
* add cover letter

Series applied, thanks.

Is this related ?

net/core/flow_dissector.c: In function '__skb_flow_dissect':
net/core/flow_dissector.c:448:18: error: 'struct net_device' has no member 
named 'dsa_ptr'
 ops = skb->dev->dsa_ptr->tag_ops;
   ^
make[3]: *** [net/core/flow_dissector.o] Error 1




looks like it, I did test the patches against net-next from 24 hours 
ago, let me do a test build just now.

John



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Re: [PATCH 0/4] net-next: dsa: fix flow dissection

[John Crispin]

On 10/08/17 08:42, Eric Dumazet wrote:

On Wed, 2017-08-09 at 22:52 -0700, David Miller wrote:

From: John Crispin 
Date: Wed,  9 Aug 2017 14:41:15 +0200


RPS and probably other kernel features are currently broken on some if not
all DSA devices. The root cause of this is that skb_hash will call the
flow_dissector. At this point the skb still contains the magic switch
header and the skb->protocol field is not set up to the correct 802.3
value yet. By the time the tag specific code is called, removing the header
and properly setting the protocol an invalid hash is already set. In the
case of the mt7530 this will result in all flows always having the same
hash.

Changes since RFC:
* use a callback instead of static values
* add cover letter

Series applied, thanks.

Is this related ?

net/core/flow_dissector.c: In function '__skb_flow_dissect':
net/core/flow_dissector.c:448:18: error: 'struct net_device' has no member 
named 'dsa_ptr'
 ops = skb->dev->dsa_ptr->tag_ops;
   ^
make[3]: *** [net/core/flow_dissector.o] Error 1




looks like it, I did test the patches against net-next from 24 hours 
ago, let me do a test build just now.

John



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[PATCH 1/4] net-next: dsa: move struct dsa_device_ops to the global header file

[John Crispin]

We need to access this struct from within the flow_dissector to fix
dissection for packets coming in on DSA devices.

Signed-off-by: Muciri Gatimu <muc...@openmesh.com>
Signed-off-by: Shashidhar Lakkavalli <shashidhar.lakkava...@openmesh.com>
Signed-off-by: John Crispin <j...@phrozen.org>
---
 include/net/dsa.h  | 7 +++
 net/dsa/dsa_priv.h | 7 ---
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/include/net/dsa.h b/include/net/dsa.h
index a4f66dbb4b7c..65d7804c6f69 100644
--- a/include/net/dsa.h
+++ b/include/net/dsa.h
@@ -101,6 +101,13 @@ struct dsa_platform_data {
 
 struct packet_type;
 
+struct dsa_device_ops {
+   struct sk_buff *(*xmit)(struct sk_buff *skb, struct net_device *dev);
+   struct sk_buff *(*rcv)(struct sk_buff *skb, struct net_device *dev,
+  struct packet_type *pt,
+  struct net_device *orig_dev);
+};
+
 struct dsa_switch_tree {
struct list_headlist;
 
diff --git a/net/dsa/dsa_priv.h b/net/dsa/dsa_priv.h
index 68c63d4b989c..9fff7f4c8689 100644
--- a/net/dsa/dsa_priv.h
+++ b/net/dsa/dsa_priv.h
@@ -65,13 +65,6 @@ struct dsa_notifier_vlan_info {
int port;
 };
 
-struct dsa_device_ops {
-   struct sk_buff *(*xmit)(struct sk_buff *skb, struct net_device *dev);
-   struct sk_buff *(*rcv)(struct sk_buff *skb, struct net_device *dev,
-  struct packet_type *pt,
-  struct net_device *orig_dev);
-};
-
 struct dsa_slave_priv {
/* Copy of dp->ds->dst->tag_ops->xmit for faster access in hot path */
struct sk_buff *(*xmit)(struct sk_buff *skb,
-- 
2.11.0

[PATCH 1/4] net-next: dsa: move struct dsa_device_ops to the global header file

[John Crispin]

We need to access this struct from within the flow_dissector to fix
dissection for packets coming in on DSA devices.

Signed-off-by: Muciri Gatimu 
Signed-off-by: Shashidhar Lakkavalli 
Signed-off-by: John Crispin 
---
 include/net/dsa.h  | 7 +++
 net/dsa/dsa_priv.h | 7 ---
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/include/net/dsa.h b/include/net/dsa.h
index a4f66dbb4b7c..65d7804c6f69 100644
--- a/include/net/dsa.h
+++ b/include/net/dsa.h
@@ -101,6 +101,13 @@ struct dsa_platform_data {
 
 struct packet_type;
 
+struct dsa_device_ops {
+   struct sk_buff *(*xmit)(struct sk_buff *skb, struct net_device *dev);
+   struct sk_buff *(*rcv)(struct sk_buff *skb, struct net_device *dev,
+  struct packet_type *pt,
+  struct net_device *orig_dev);
+};
+
 struct dsa_switch_tree {
struct list_headlist;
 
diff --git a/net/dsa/dsa_priv.h b/net/dsa/dsa_priv.h
index 68c63d4b989c..9fff7f4c8689 100644
--- a/net/dsa/dsa_priv.h
+++ b/net/dsa/dsa_priv.h
@@ -65,13 +65,6 @@ struct dsa_notifier_vlan_info {
int port;
 };
 
-struct dsa_device_ops {
-   struct sk_buff *(*xmit)(struct sk_buff *skb, struct net_device *dev);
-   struct sk_buff *(*rcv)(struct sk_buff *skb, struct net_device *dev,
-  struct packet_type *pt,
-  struct net_device *orig_dev);
-};
-
 struct dsa_slave_priv {
/* Copy of dp->ds->dst->tag_ops->xmit for faster access in hot path */
struct sk_buff *(*xmit)(struct sk_buff *skb,
-- 
2.11.0

[PATCH 4/4] net-next: dsa: fix flow dissection

[John Crispin]

RPS and probably other kernel features are currently broken on some if not
all DSA devices. The root cause of this is that skb_hash will call the
flow_dissector. At this point the skb still contains the magic switch
header and the skb->protocol field is not set up to the correct 802.3
value yet. By the time the tag specific code is called, removing the header
and properly setting the protocol an invalid hash is already set. In the
case of the mt7530 this will result in all flows always having the same
hash.

Signed-off-by: Muciri Gatimu <muc...@openmesh.com>
Signed-off-by: Shashidhar Lakkavalli <shashidhar.lakkava...@openmesh.com>
Signed-off-by: John Crispin <j...@phrozen.org>
---
 net/core/flow_dissector.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/net/core/flow_dissector.c b/net/core/flow_dissector.c
index 0cc672aba1f0..5b5be9577257 100644
--- a/net/core/flow_dissector.c
+++ b/net/core/flow_dissector.c
@@ -4,6 +4,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -440,6 +441,17 @@ bool __skb_flow_dissect(const struct sk_buff *skb,
 skb->vlan_proto : skb->protocol;
nhoff = skb_network_offset(skb);
hlen = skb_headlen(skb);
+   if (unlikely(netdev_uses_dsa(skb->dev))) {
+   const struct dsa_device_ops *ops;
+   int offset;
+
+   ops = skb->dev->dsa_ptr->tag_ops;
+   if (ops->flow_dissect &&
+   !ops->flow_dissect(skb, , )) {
+   hlen -= offset;
+   nhoff += offset;
+   }
+   }
}
 
/* It is ensured by skb_flow_dissector_init() that control key will
-- 
2.11.0

[PATCH 4/4] net-next: dsa: fix flow dissection

[John Crispin]

RPS and probably other kernel features are currently broken on some if not
all DSA devices. The root cause of this is that skb_hash will call the
flow_dissector. At this point the skb still contains the magic switch
header and the skb->protocol field is not set up to the correct 802.3
value yet. By the time the tag specific code is called, removing the header
and properly setting the protocol an invalid hash is already set. In the
case of the mt7530 this will result in all flows always having the same
hash.

Signed-off-by: Muciri Gatimu 
Signed-off-by: Shashidhar Lakkavalli 
Signed-off-by: John Crispin 
---
 net/core/flow_dissector.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/net/core/flow_dissector.c b/net/core/flow_dissector.c
index 0cc672aba1f0..5b5be9577257 100644
--- a/net/core/flow_dissector.c
+++ b/net/core/flow_dissector.c
@@ -4,6 +4,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -440,6 +441,17 @@ bool __skb_flow_dissect(const struct sk_buff *skb,
 skb->vlan_proto : skb->protocol;
nhoff = skb_network_offset(skb);
hlen = skb_headlen(skb);
+   if (unlikely(netdev_uses_dsa(skb->dev))) {
+   const struct dsa_device_ops *ops;
+   int offset;
+
+   ops = skb->dev->dsa_ptr->tag_ops;
+   if (ops->flow_dissect &&
+   !ops->flow_dissect(skb, , )) {
+   hlen -= offset;
+   nhoff += offset;
+   }
+   }
}
 
/* It is ensured by skb_flow_dissector_init() that control key will
-- 
2.11.0

[PATCH 0/4] net-next: dsa: fix flow dissection

[John Crispin]

RPS and probably other kernel features are currently broken on some if not
all DSA devices. The root cause of this is that skb_hash will call the
flow_dissector. At this point the skb still contains the magic switch
header and the skb->protocol field is not set up to the correct 802.3
value yet. By the time the tag specific code is called, removing the header
and properly setting the protocol an invalid hash is already set. In the
case of the mt7530 this will result in all flows always having the same
hash.

Changes since RFC:
* use a callback instead of static values
* add cover letter

John Crispin (4):
  net-next: dsa: move struct dsa_device_ops to the global header file
  net-next: dsa: add flow_dissect callback to struct dsa_device_ops
  net-next: tag_mtk: add flow_dissect callback to the ops struct
  net-next: dsa: fix flow dissection

 include/net/dsa.h |  9 +
 net/core/flow_dissector.c | 12 
 net/dsa/dsa_priv.h|  7 ---
 net/dsa/tag_mtk.c | 14 --
 4 files changed, 33 insertions(+), 9 deletions(-)

-- 
2.11.0

[PATCH 0/4] net-next: dsa: fix flow dissection

[John Crispin]

RPS and probably other kernel features are currently broken on some if not
all DSA devices. The root cause of this is that skb_hash will call the
flow_dissector. At this point the skb still contains the magic switch
header and the skb->protocol field is not set up to the correct 802.3
value yet. By the time the tag specific code is called, removing the header
and properly setting the protocol an invalid hash is already set. In the
case of the mt7530 this will result in all flows always having the same
hash.

Changes since RFC:
* use a callback instead of static values
* add cover letter

John Crispin (4):
  net-next: dsa: move struct dsa_device_ops to the global header file
  net-next: dsa: add flow_dissect callback to struct dsa_device_ops
  net-next: tag_mtk: add flow_dissect callback to the ops struct
  net-next: dsa: fix flow dissection

 include/net/dsa.h |  9 +
 net/core/flow_dissector.c | 12 
 net/dsa/dsa_priv.h|  7 ---
 net/dsa/tag_mtk.c | 14 --
 4 files changed, 33 insertions(+), 9 deletions(-)

-- 
2.11.0

[PATCH 3/4] net-next: tag_mtk: add flow_dissect callback to the ops struct

[John Crispin]

The MT7530 inserts the 4 magic header in between the 802.3 address and
protocol field. The patch implements the callback that can be called by
the flow dissector to figure out the real protocol and offset of the
network header. With this patch applied we can properly parse the packet
and thus make hashing function properly.

Signed-off-by: Muciri Gatimu <muc...@openmesh.com>
Signed-off-by: Shashidhar Lakkavalli <shashidhar.lakkava...@openmesh.com>
Signed-off-by: John Crispin <j...@phrozen.org>
---
 net/dsa/tag_mtk.c | 14 --
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/net/dsa/tag_mtk.c b/net/dsa/tag_mtk.c
index 2f32b7ea3365..02163c045a96 100644
--- a/net/dsa/tag_mtk.c
+++ b/net/dsa/tag_mtk.c
@@ -87,7 +87,17 @@ static struct sk_buff *mtk_tag_rcv(struct sk_buff *skb, 
struct net_device *dev,
return skb;
 }
 
+static int mtk_tag_flow_dissect(const struct sk_buff *skb, __be16 *proto,
+   int *offset)
+{
+   *offset = 4;
+   *proto = ((__be16 *)skb->data)[1];
+
+   return 0;
+}
+
 const struct dsa_device_ops mtk_netdev_ops = {
-   .xmit   = mtk_tag_xmit,
-   .rcv= mtk_tag_rcv,
+   .xmit   = mtk_tag_xmit,
+   .rcv= mtk_tag_rcv,
+   .flow_dissect   = mtk_tag_flow_dissect,
 };
-- 
2.11.0

[PATCH 3/4] net-next: tag_mtk: add flow_dissect callback to the ops struct

[John Crispin]

The MT7530 inserts the 4 magic header in between the 802.3 address and
protocol field. The patch implements the callback that can be called by
the flow dissector to figure out the real protocol and offset of the
network header. With this patch applied we can properly parse the packet
and thus make hashing function properly.

Signed-off-by: Muciri Gatimu 
Signed-off-by: Shashidhar Lakkavalli 
Signed-off-by: John Crispin 
---
 net/dsa/tag_mtk.c | 14 --
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/net/dsa/tag_mtk.c b/net/dsa/tag_mtk.c
index 2f32b7ea3365..02163c045a96 100644
--- a/net/dsa/tag_mtk.c
+++ b/net/dsa/tag_mtk.c
@@ -87,7 +87,17 @@ static struct sk_buff *mtk_tag_rcv(struct sk_buff *skb, 
struct net_device *dev,
return skb;
 }
 
+static int mtk_tag_flow_dissect(const struct sk_buff *skb, __be16 *proto,
+   int *offset)
+{
+   *offset = 4;
+   *proto = ((__be16 *)skb->data)[1];
+
+   return 0;
+}
+
 const struct dsa_device_ops mtk_netdev_ops = {
-   .xmit   = mtk_tag_xmit,
-   .rcv= mtk_tag_rcv,
+   .xmit   = mtk_tag_xmit,
+   .rcv= mtk_tag_rcv,
+   .flow_dissect   = mtk_tag_flow_dissect,
 };
-- 
2.11.0

[PATCH 2/4] net-next: dsa: add flow_dissect callback to struct dsa_device_ops

[John Crispin]

When the flow dissector first sees packets coming in on a DSA devices the
802.3 header wont be located where the code expects it to be as the tag
is still present. Adding this new callback allows a DSA device to provide a
new function that the flow_dissector can use to get the correct protocol
and offset of the network header.

Signed-off-by: Muciri Gatimu <muc...@openmesh.com>
Signed-off-by: Shashidhar Lakkavalli <shashidhar.lakkava...@openmesh.com>
Signed-off-by: John Crispin <j...@phrozen.org>
---
 include/net/dsa.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/net/dsa.h b/include/net/dsa.h
index 65d7804c6f69..7f46b521313e 100644
--- a/include/net/dsa.h
+++ b/include/net/dsa.h
@@ -106,6 +106,8 @@ struct dsa_device_ops {
struct sk_buff *(*rcv)(struct sk_buff *skb, struct net_device *dev,
   struct packet_type *pt,
   struct net_device *orig_dev);
+   int (*flow_dissect)(const struct sk_buff *skb, __be16 *proto,
+   int *offset);
 };
 
 struct dsa_switch_tree {
-- 
2.11.0

[PATCH 2/4] net-next: dsa: add flow_dissect callback to struct dsa_device_ops

[John Crispin]

When the flow dissector first sees packets coming in on a DSA devices the
802.3 header wont be located where the code expects it to be as the tag
is still present. Adding this new callback allows a DSA device to provide a
new function that the flow_dissector can use to get the correct protocol
and offset of the network header.

Signed-off-by: Muciri Gatimu 
Signed-off-by: Shashidhar Lakkavalli 
Signed-off-by: John Crispin 
---
 include/net/dsa.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/net/dsa.h b/include/net/dsa.h
index 65d7804c6f69..7f46b521313e 100644
--- a/include/net/dsa.h
+++ b/include/net/dsa.h
@@ -106,6 +106,8 @@ struct dsa_device_ops {
struct sk_buff *(*rcv)(struct sk_buff *skb, struct net_device *dev,
   struct packet_type *pt,
   struct net_device *orig_dev);
+   int (*flow_dissect)(const struct sk_buff *skb, __be16 *proto,
+   int *offset);
 };
 
 struct dsa_switch_tree {
-- 
2.11.0

[PATCH 0/2] net-next: mediatek: bring up QDMA RX ring 0

[John Crispin]

The MT7623 has several DMA rings. Inside the SW path, the core will use
the PDMA when receiving traffic. While bringing up the HW path we noticed
that the PPE requires the QDMA RX to also be brought up as it uses this
ring internally for its flow scheduling.

John Crispin (2):
  net-next: mediatek: fix typos inside the header file
  net-next: mediatek: bring up QDMA RX ring 0

 drivers/net/ethernet/mediatek/mtk_eth_soc.c | 36 +
 drivers/net/ethernet/mediatek/mtk_eth_soc.h |  7 --
 2 files changed, 31 insertions(+), 12 deletions(-)

-- 
2.11.0

[PATCH 0/2] net-next: mediatek: bring up QDMA RX ring 0

[John Crispin]

The MT7623 has several DMA rings. Inside the SW path, the core will use
the PDMA when receiving traffic. While bringing up the HW path we noticed
that the PPE requires the QDMA RX to also be brought up as it uses this
ring internally for its flow scheduling.

John Crispin (2):
  net-next: mediatek: fix typos inside the header file
  net-next: mediatek: bring up QDMA RX ring 0

 drivers/net/ethernet/mediatek/mtk_eth_soc.c | 36 +
 drivers/net/ethernet/mediatek/mtk_eth_soc.h |  7 --
 2 files changed, 31 insertions(+), 12 deletions(-)

-- 
2.11.0

[PATCH 1/2] net-next: mediatek: fix typos inside the header file

[John Crispin]

Trivial patch fixing 2 typos.

Signed-off-by: John Crispin <j...@phrozen.org>
---
 drivers/net/ethernet/mediatek/mtk_eth_soc.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h 
b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index 4594862e5a9b..940517af8039 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -599,8 +599,8 @@ struct mtk_soc_data {
  * @pctl:  The register map pointing at the range used to setup
  * GMAC port drive/slew values
  * @dma_refcnt:track how many netdevs are using the DMA engine
- * @tx_ring:   Pointer to the memore holding info about the TX ring
- * @rx_ring:   Pointer to the memore holding info about the RX ring
+ * @tx_ring:   Pointer to the memory holding info about the TX ring
+ * @rx_ring:   Pointer to the memory holding info about the RX ring
  * @tx_napi:   The TX NAPI struct
  * @rx_napi:   The RX NAPI struct
  * @scratch_ring:  Newer SoCs need memory for a second HW managed TX ring
-- 
2.11.0

[PATCH 2/2] net-next: mediatek: bring up QDMA RX ring 0

[John Crispin]

This patch is in preparation for adding HW flow and QoS offloading. For
those features to work, the driver needs to bring up the first QDMA RX
ring. This ring is used by the PPE offloading HW.

Signed-off-by: John Crisp in 
---
 drivers/net/ethernet/mediatek/mtk_eth_soc.c | 36 +
 drivers/net/ethernet/mediatek/mtk_eth_soc.h |  3 +++
 2 files changed, 29 insertions(+), 10 deletions(-)

diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c 
b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index ff97f2939209..4c85b4713c0d 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -1285,9 +1285,19 @@ static void mtk_tx_clean(struct mtk_eth *eth)
 
 static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag)
 {
-   struct mtk_rx_ring *ring = >rx_ring[ring_no];
+   struct mtk_rx_ring *ring;
int rx_data_len, rx_dma_size;
int i;
+   u32 offset = 0;
+
+   if (rx_flag == MTK_RX_FLAGS_QDMA) {
+   if (ring_no)
+   return -EINVAL;
+   ring = >rx_ring_qdma;
+   offset = 0x1000;
+   } else {
+   ring = >rx_ring[ring_no];
+   }
 
if (rx_flag == MTK_RX_FLAGS_HWLRO) {
rx_data_len = MTK_MAX_LRO_RX_LENGTH;
@@ -1337,17 +1347,16 @@ static int mtk_rx_alloc(struct mtk_eth *eth, int 
ring_no, int rx_flag)
 */
wmb();
 
-   mtk_w32(eth, ring->phys, MTK_PRX_BASE_PTR_CFG(ring_no));
-   mtk_w32(eth, rx_dma_size, MTK_PRX_MAX_CNT_CFG(ring_no));
-   mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
-   mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), MTK_PDMA_RST_IDX);
+   mtk_w32(eth, ring->phys, MTK_PRX_BASE_PTR_CFG(ring_no) + offset);
+   mtk_w32(eth, rx_dma_size, MTK_PRX_MAX_CNT_CFG(ring_no) + offset);
+   mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg + offset);
+   mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), MTK_PDMA_RST_IDX + offset);
 
return 0;
 }
 
-static void mtk_rx_clean(struct mtk_eth *eth, int ring_no)
+static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring)
 {
-   struct mtk_rx_ring *ring = >rx_ring[ring_no];
int i;
 
if (ring->data && ring->dma) {
@@ -1673,6 +1682,10 @@ static int mtk_dma_init(struct mtk_eth *eth)
if (err)
return err;
 
+   err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_QDMA);
+   if (err)
+   return err;
+
err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL);
if (err)
return err;
@@ -1712,12 +1725,13 @@ static void mtk_dma_free(struct mtk_eth *eth)
eth->phy_scratch_ring = 0;
}
mtk_tx_clean(eth);
-   mtk_rx_clean(eth, 0);
+   mtk_rx_clean(eth, >rx_ring[0]);
+   mtk_rx_clean(eth, >rx_ring_qdma);
 
if (eth->hwlro) {
mtk_hwlro_rx_uninit(eth);
for (i = 1; i < MTK_MAX_RX_RING_NUM; i++)
-   mtk_rx_clean(eth, i);
+   mtk_rx_clean(eth, >rx_ring[i]);
}
 
kfree(eth->scratch_head);
@@ -1784,7 +1798,9 @@ static int mtk_start_dma(struct mtk_eth *eth)
 
mtk_w32(eth,
MTK_TX_WB_DDONE | MTK_TX_DMA_EN |
-   MTK_DMA_SIZE_16DWORDS | MTK_NDP_CO_PRO,
+   MTK_DMA_SIZE_16DWORDS | MTK_NDP_CO_PRO |
+   MTK_RX_DMA_EN | MTK_RX_2B_OFFSET |
+   MTK_RX_BT_32DWORDS,
MTK_QDMA_GLO_CFG);
 
mtk_w32(eth,
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h 
b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index 940517af8039..3d3c24a28112 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -532,6 +532,7 @@ struct mtk_tx_ring {
 enum mtk_rx_flags {
MTK_RX_FLAGS_NORMAL = 0,
MTK_RX_FLAGS_HWLRO,
+   MTK_RX_FLAGS_QDMA,
 };
 
 /* struct mtk_rx_ring -This struct holds info describing a RX ring
@@ -601,6 +602,7 @@ struct mtk_soc_data {
  * @dma_refcnt:track how many netdevs are using the DMA engine
  * @tx_ring:   Pointer to the memory holding info about the TX ring
  * @rx_ring:   Pointer to the memory holding info about the RX ring
+ * @rx_ring_qdma:  Pointer to the memory holding info about the QDMA RX 
ring
  * @tx_napi:   The TX NAPI struct
  * @rx_napi:   The RX NAPI struct
  * @scratch_ring:  Newer SoCs need memory for a second HW managed TX ring
@@ -633,6 +635,7 @@ struct mtk_eth {
atomic_tdma_refcnt;
struct mtk_tx_ring  tx_ring;
struct mtk_rx_ring  rx_ring[MTK_MAX_RX_RING_NUM];
+   struct mtk_rx_ring  rx_ring_qdma;
struct napi_struct  tx_napi;
struct napi_struct  rx_napi;
struct mtk_tx_dma   *scratch_ring;
-- 
2.11.0

[PATCH 1/2] net-next: mediatek: fix typos inside the header file

[John Crispin]

Trivial patch fixing 2 typos.

Signed-off-by: John Crispin 
---
 drivers/net/ethernet/mediatek/mtk_eth_soc.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h 
b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index 4594862e5a9b..940517af8039 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -599,8 +599,8 @@ struct mtk_soc_data {
  * @pctl:  The register map pointing at the range used to setup
  * GMAC port drive/slew values
  * @dma_refcnt:track how many netdevs are using the DMA engine
- * @tx_ring:   Pointer to the memore holding info about the TX ring
- * @rx_ring:   Pointer to the memore holding info about the RX ring
+ * @tx_ring:   Pointer to the memory holding info about the TX ring
+ * @rx_ring:   Pointer to the memory holding info about the RX ring
  * @tx_napi:   The TX NAPI struct
  * @rx_napi:   The RX NAPI struct
  * @scratch_ring:  Newer SoCs need memory for a second HW managed TX ring
-- 
2.11.0

[PATCH 2/2] net-next: mediatek: bring up QDMA RX ring 0

[John Crispin]

This patch is in preparation for adding HW flow and QoS offloading. For
those features to work, the driver needs to bring up the first QDMA RX
ring. This ring is used by the PPE offloading HW.

Signed-off-by: John Crisp in 
---
 drivers/net/ethernet/mediatek/mtk_eth_soc.c | 36 +
 drivers/net/ethernet/mediatek/mtk_eth_soc.h |  3 +++
 2 files changed, 29 insertions(+), 10 deletions(-)

diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c 
b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index ff97f2939209..4c85b4713c0d 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -1285,9 +1285,19 @@ static void mtk_tx_clean(struct mtk_eth *eth)
 
 static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag)
 {
-   struct mtk_rx_ring *ring = >rx_ring[ring_no];
+   struct mtk_rx_ring *ring;
int rx_data_len, rx_dma_size;
int i;
+   u32 offset = 0;
+
+   if (rx_flag == MTK_RX_FLAGS_QDMA) {
+   if (ring_no)
+   return -EINVAL;
+   ring = >rx_ring_qdma;
+   offset = 0x1000;
+   } else {
+   ring = >rx_ring[ring_no];
+   }
 
if (rx_flag == MTK_RX_FLAGS_HWLRO) {
rx_data_len = MTK_MAX_LRO_RX_LENGTH;
@@ -1337,17 +1347,16 @@ static int mtk_rx_alloc(struct mtk_eth *eth, int 
ring_no, int rx_flag)
 */
wmb();
 
-   mtk_w32(eth, ring->phys, MTK_PRX_BASE_PTR_CFG(ring_no));
-   mtk_w32(eth, rx_dma_size, MTK_PRX_MAX_CNT_CFG(ring_no));
-   mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
-   mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), MTK_PDMA_RST_IDX);
+   mtk_w32(eth, ring->phys, MTK_PRX_BASE_PTR_CFG(ring_no) + offset);
+   mtk_w32(eth, rx_dma_size, MTK_PRX_MAX_CNT_CFG(ring_no) + offset);
+   mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg + offset);
+   mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), MTK_PDMA_RST_IDX + offset);
 
return 0;
 }
 
-static void mtk_rx_clean(struct mtk_eth *eth, int ring_no)
+static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring)
 {
-   struct mtk_rx_ring *ring = >rx_ring[ring_no];
int i;
 
if (ring->data && ring->dma) {
@@ -1673,6 +1682,10 @@ static int mtk_dma_init(struct mtk_eth *eth)
if (err)
return err;
 
+   err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_QDMA);
+   if (err)
+   return err;
+
err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL);
if (err)
return err;
@@ -1712,12 +1725,13 @@ static void mtk_dma_free(struct mtk_eth *eth)
eth->phy_scratch_ring = 0;
}
mtk_tx_clean(eth);
-   mtk_rx_clean(eth, 0);
+   mtk_rx_clean(eth, >rx_ring[0]);
+   mtk_rx_clean(eth, >rx_ring_qdma);
 
if (eth->hwlro) {
mtk_hwlro_rx_uninit(eth);
for (i = 1; i < MTK_MAX_RX_RING_NUM; i++)
-   mtk_rx_clean(eth, i);
+   mtk_rx_clean(eth, >rx_ring[i]);
}
 
kfree(eth->scratch_head);
@@ -1784,7 +1798,9 @@ static int mtk_start_dma(struct mtk_eth *eth)
 
mtk_w32(eth,
MTK_TX_WB_DDONE | MTK_TX_DMA_EN |
-   MTK_DMA_SIZE_16DWORDS | MTK_NDP_CO_PRO,
+   MTK_DMA_SIZE_16DWORDS | MTK_NDP_CO_PRO |
+   MTK_RX_DMA_EN | MTK_RX_2B_OFFSET |
+   MTK_RX_BT_32DWORDS,
MTK_QDMA_GLO_CFG);
 
mtk_w32(eth,
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h 
b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index 940517af8039..3d3c24a28112 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -532,6 +532,7 @@ struct mtk_tx_ring {
 enum mtk_rx_flags {
MTK_RX_FLAGS_NORMAL = 0,
MTK_RX_FLAGS_HWLRO,
+   MTK_RX_FLAGS_QDMA,
 };
 
 /* struct mtk_rx_ring -This struct holds info describing a RX ring
@@ -601,6 +602,7 @@ struct mtk_soc_data {
  * @dma_refcnt:track how many netdevs are using the DMA engine
  * @tx_ring:   Pointer to the memory holding info about the TX ring
  * @rx_ring:   Pointer to the memory holding info about the RX ring
+ * @rx_ring_qdma:  Pointer to the memory holding info about the QDMA RX 
ring
  * @tx_napi:   The TX NAPI struct
  * @rx_napi:   The RX NAPI struct
  * @scratch_ring:  Newer SoCs need memory for a second HW managed TX ring
@@ -633,6 +635,7 @@ struct mtk_eth {
atomic_tdma_refcnt;
struct mtk_tx_ring  tx_ring;
struct mtk_rx_ring  rx_ring[MTK_MAX_RX_RING_NUM];
+   struct mtk_rx_ring  rx_ring_qdma;
struct napi_struct  tx_napi;
struct napi_struct  rx_napi;
struct mtk_tx_dma   *scratch_ring;
-- 
2.11.0

[PATCH] net: dsa: mediatek: add adjust link support for user ports

[John Crispin]

Manually adjust the port settings of user ports once PHY polling has
completed. This patch extends the adjust_link callback to configure the
per port PMCR register, applying the proper values polled from the PHY.
Without this patch flow control was not always getting setup properly.

Signed-off-by: Shashidhar Lakkavalli <shashidhar.lakkava...@openmesh.com>
Signed-off-by: Muciri Gatimu <muc...@openmesh.com>
Signed-off-by: John Crispin <j...@phrozen.org>
---
 drivers/net/dsa/mt7530.c | 38 ++
 drivers/net/dsa/mt7530.h |  1 +
 2 files changed, 39 insertions(+)

diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c
index 1e46418a3b74..264b281eb86b 100644
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
@@ -625,6 +625,44 @@ static void mt7530_adjust_link(struct dsa_switch *ds, int 
port,
 * all finished.
 */
mt7623_pad_clk_setup(ds);
+   } else {
+   u16 lcl_adv = 0, rmt_adv = 0;
+   u8 flowctrl;
+   u32 mcr = PMCR_USERP_LINK | PMCR_FORCE_MODE;
+
+   switch (phydev->speed) {
+   case SPEED_1000:
+   mcr |= PMCR_FORCE_SPEED_1000;
+   break;
+   case SPEED_100:
+   mcr |= PMCR_FORCE_SPEED_100;
+   break;
+   };
+
+   if (phydev->link)
+   mcr |= PMCR_FORCE_LNK;
+
+   if (phydev->duplex) {
+   mcr |= PMCR_FORCE_FDX;
+
+   if (phydev->pause)
+   rmt_adv = LPA_PAUSE_CAP;
+   if (phydev->asym_pause)
+   rmt_adv |= LPA_PAUSE_ASYM;
+
+   if (phydev->advertising & ADVERTISED_Pause)
+   lcl_adv |= ADVERTISE_PAUSE_CAP;
+   if (phydev->advertising & ADVERTISED_Asym_Pause)
+   lcl_adv |= ADVERTISE_PAUSE_ASYM;
+
+   flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
+
+   if (flowctrl & FLOW_CTRL_TX)
+   mcr |= PMCR_TX_FC_EN;
+   if (flowctrl & FLOW_CTRL_RX)
+   mcr |= PMCR_RX_FC_EN;
+   }
+   mt7530_write(priv, MT7530_PMCR_P(port), mcr);
}
 }
 
diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h
index b83d76b99802..74db9822eb40 100644
--- a/drivers/net/dsa/mt7530.h
+++ b/drivers/net/dsa/mt7530.h
@@ -151,6 +151,7 @@ enum mt7530_stp_state {
 #define  PMCR_TX_FC_EN BIT(5)
 #define  PMCR_RX_FC_EN BIT(4)
 #define  PMCR_FORCE_SPEED_1000 BIT(3)
+#define  PMCR_FORCE_SPEED_100  BIT(2)
 #define  PMCR_FORCE_FDXBIT(1)
 #define  PMCR_FORCE_LNKBIT(0)
 #define  PMCR_COMMON_LINK  (PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | \
-- 
2.11.0

[PATCH] net: dsa: mediatek: add adjust link support for user ports

[John Crispin]

Manually adjust the port settings of user ports once PHY polling has
completed. This patch extends the adjust_link callback to configure the
per port PMCR register, applying the proper values polled from the PHY.
Without this patch flow control was not always getting setup properly.

Signed-off-by: Shashidhar Lakkavalli 
Signed-off-by: Muciri Gatimu 
Signed-off-by: John Crispin 
---
 drivers/net/dsa/mt7530.c | 38 ++
 drivers/net/dsa/mt7530.h |  1 +
 2 files changed, 39 insertions(+)

diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c
index 1e46418a3b74..264b281eb86b 100644
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
@@ -625,6 +625,44 @@ static void mt7530_adjust_link(struct dsa_switch *ds, int 
port,
 * all finished.
 */
mt7623_pad_clk_setup(ds);
+   } else {
+   u16 lcl_adv = 0, rmt_adv = 0;
+   u8 flowctrl;
+   u32 mcr = PMCR_USERP_LINK | PMCR_FORCE_MODE;
+
+   switch (phydev->speed) {
+   case SPEED_1000:
+   mcr |= PMCR_FORCE_SPEED_1000;
+   break;
+   case SPEED_100:
+   mcr |= PMCR_FORCE_SPEED_100;
+   break;
+   };
+
+   if (phydev->link)
+   mcr |= PMCR_FORCE_LNK;
+
+   if (phydev->duplex) {
+   mcr |= PMCR_FORCE_FDX;
+
+   if (phydev->pause)
+   rmt_adv = LPA_PAUSE_CAP;
+   if (phydev->asym_pause)
+   rmt_adv |= LPA_PAUSE_ASYM;
+
+   if (phydev->advertising & ADVERTISED_Pause)
+   lcl_adv |= ADVERTISE_PAUSE_CAP;
+   if (phydev->advertising & ADVERTISED_Asym_Pause)
+   lcl_adv |= ADVERTISE_PAUSE_ASYM;
+
+   flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
+
+   if (flowctrl & FLOW_CTRL_TX)
+   mcr |= PMCR_TX_FC_EN;
+   if (flowctrl & FLOW_CTRL_RX)
+   mcr |= PMCR_RX_FC_EN;
+   }
+   mt7530_write(priv, MT7530_PMCR_P(port), mcr);
}
 }
 
diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h
index b83d76b99802..74db9822eb40 100644
--- a/drivers/net/dsa/mt7530.h
+++ b/drivers/net/dsa/mt7530.h
@@ -151,6 +151,7 @@ enum mt7530_stp_state {
 #define  PMCR_TX_FC_EN BIT(5)
 #define  PMCR_RX_FC_EN BIT(4)
 #define  PMCR_FORCE_SPEED_1000 BIT(3)
+#define  PMCR_FORCE_SPEED_100  BIT(2)
 #define  PMCR_FORCE_FDXBIT(1)
 #define  PMCR_FORCE_LNKBIT(0)
 #define  PMCR_COMMON_LINK  (PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | \
-- 
2.11.0

Re: [V3 1/2] phy: ralink-usb: add driver for Mediatek/Ralink

[John Crispin]

Hi Harvey,

Thanks for picking up my stale patch. small comment inline ...


On 03/08/17 12:32, Harvey Hunt wrote:

From: John Crispin <j...@phrozen.org>

Add a driver to setup the USB phy on Mediatek/Ralink SoCs.
The driver is trivial and only sets up power and host mode.

Signed-off-by: John Crispin <j...@phrozen.org>
Signed-off-by: Harvey Hunt <harvey.h...@imgtec.com>
Cc: linux-kernel@vger.kernel.org
Cc: linux-media...@lists.infradead.org
---
Changes in V3
* Separate DT bindings
* Update Kconfig text
* Modify John's email address
* Rebase onto v4.13-rc3

Changes in V2
* remove refcounting
* drop empty functions
* dont use static globals
* use explicit compatible strings

  drivers/phy/Kconfig  |   8 ++
  drivers/phy/Makefile |   1 +
  drivers/phy/phy-ralink-usb.c | 175 +++
  3 files changed, 184 insertions(+)
  create mode 100644 drivers/phy/phy-ralink-usb.c

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index c1807d4..79f966a 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -41,6 +41,14 @@ config PHY_PISTACHIO_USB
help
  Enable this to support the USB2.0 PHY on the IMG Pistachio SoC.
  
+config PHY_RALINK_USB

+   tristate "Ralink USB PHY driver"
+   select GENERIC_PHY
+   depends on RALINK
+   help
+ This option enables support for the Ralink USB PHY found inside
+ RT3352, MT7620, MT7628 and MT7688.
+
  config PHY_XGENE
tristate "APM X-Gene 15Gbps PHY support"
depends on HAS_IOMEM && OF && (ARM64 || COMPILE_TEST)
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index f252201..60ed30b 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_PHY_LPC18XX_USB_OTG)   += phy-lpc18xx-usb-otg.o
  obj-$(CONFIG_PHY_MT65XX_USB3) += phy-mt65xx-usb3.o
  obj-$(CONFIG_PHY_XGENE)   += phy-xgene.o
  obj-$(CONFIG_PHY_PISTACHIO_USB)   += phy-pistachio-usb.o
+obj-$(CONFIG_PHY_RALINK_USB)   += phy-ralink-usb.o
  
  obj-$(CONFIG_ARCH_SUNXI)		+= allwinner/

  obj-$(CONFIG_ARCH_MESON)  += amlogic/
diff --git a/drivers/phy/phy-ralink-usb.c b/drivers/phy/phy-ralink-usb.c
new file mode 100644
index 000..c693fb1
--- /dev/null
+++ b/drivers/phy/phy-ralink-usb.c
@@ -0,0 +1,175 @@
+/*
+ * Allwinner ralink USB phy driver

We should remove the "Allwinner" from the header

John




+ *
+ * Copyright (C) 2016 John Crispin <j...@phrozen.org>
+ *
+ * Based on code from
+ * Allwinner Technology Co., Ltd. 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#define RT_SYSC_REG_SYSCFG10x014
+#define RT_SYSC_REG_CLKCFG10x030
+#define RT_SYSC_REG_USB_PHY_CFG0x05c
+
+#define RT_RSTCTRL_UDEVBIT(25)
+#define RT_RSTCTRL_UHSTBIT(22)
+#define RT_SYSCFG1_USB0_HOST_MODE  BIT(10)
+
+#define MT7620_CLKCFG1_UPHY0_CLK_ENBIT(25)
+#define MT7620_CLKCFG1_UPHY1_CLK_ENBIT(22)
+#define RT_CLKCFG1_UPHY1_CLK_ENBIT(20)
+#define RT_CLKCFG1_UPHY0_CLK_ENBIT(18)
+
+#define USB_PHY_UTMI_8B60M BIT(1)
+#define UDEV_WAKEUPBIT(0)
+
+struct ralink_usb_phy {
+   struct reset_control*rstdev;
+   struct reset_control*rsthost;
+   u32 clk;
+   struct phy  *phy;
+};
+
+static int ralink_usb_phy_power_on(struct phy *_phy)
+{
+   struct ralink_usb_phy *phy = phy_get_drvdata(_phy);
+   u32 t;
+
+   /* enable the phy */
+   rt_sysc_m32(0, phy->clk, RT_SYSC_REG_CLKCFG1);
+
+   /* setup host mode */
+   rt_sysc_m32(0, RT_SYSCFG1_USB0_HOST_MODE, RT_SYSC_REG_SYSCFG1);
+
+   /* deassert the reset lines */
+   reset_control_deassert(phy->rsthost);
+   reset_control_deassert(phy->rstdev);
+
+   /*
+* The SDK kernel had a delay of 100ms. however on device
+* testing showed that 10ms is enough
+*/
+   mdelay(10);
+
+   /* print some status info */
+   t = rt_sysc_r32(RT_SYSC_REG_USB_PHY_CFG);
+   dev_info(>phy->dev, "remote usb device wakeup %s\n",
+   (t & UDEV_WAKEUP) ? ("enabled") : ("disabled"));
+   if (t & USB_PHY_U

Re: [V3 1/2] phy: ralink-usb: add driver for Mediatek/Ralink

[John Crispin]

Hi Harvey,

Thanks for picking up my stale patch. small comment inline ...


On 03/08/17 12:32, Harvey Hunt wrote:

From: John Crispin 

Add a driver to setup the USB phy on Mediatek/Ralink SoCs.
The driver is trivial and only sets up power and host mode.

Signed-off-by: John Crispin 
Signed-off-by: Harvey Hunt 
Cc: linux-kernel@vger.kernel.org
Cc: linux-media...@lists.infradead.org
---
Changes in V3
* Separate DT bindings
* Update Kconfig text
* Modify John's email address
* Rebase onto v4.13-rc3

Changes in V2
* remove refcounting
* drop empty functions
* dont use static globals
* use explicit compatible strings

  drivers/phy/Kconfig  |   8 ++
  drivers/phy/Makefile |   1 +
  drivers/phy/phy-ralink-usb.c | 175 +++
  3 files changed, 184 insertions(+)
  create mode 100644 drivers/phy/phy-ralink-usb.c

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index c1807d4..79f966a 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -41,6 +41,14 @@ config PHY_PISTACHIO_USB
help
  Enable this to support the USB2.0 PHY on the IMG Pistachio SoC.
  
+config PHY_RALINK_USB

+   tristate "Ralink USB PHY driver"
+   select GENERIC_PHY
+   depends on RALINK
+   help
+ This option enables support for the Ralink USB PHY found inside
+ RT3352, MT7620, MT7628 and MT7688.
+
  config PHY_XGENE
tristate "APM X-Gene 15Gbps PHY support"
depends on HAS_IOMEM && OF && (ARM64 || COMPILE_TEST)
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index f252201..60ed30b 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_PHY_LPC18XX_USB_OTG)   += phy-lpc18xx-usb-otg.o
  obj-$(CONFIG_PHY_MT65XX_USB3) += phy-mt65xx-usb3.o
  obj-$(CONFIG_PHY_XGENE)   += phy-xgene.o
  obj-$(CONFIG_PHY_PISTACHIO_USB)   += phy-pistachio-usb.o
+obj-$(CONFIG_PHY_RALINK_USB)   += phy-ralink-usb.o
  
  obj-$(CONFIG_ARCH_SUNXI)		+= allwinner/

  obj-$(CONFIG_ARCH_MESON)  += amlogic/
diff --git a/drivers/phy/phy-ralink-usb.c b/drivers/phy/phy-ralink-usb.c
new file mode 100644
index 000..c693fb1
--- /dev/null
+++ b/drivers/phy/phy-ralink-usb.c
@@ -0,0 +1,175 @@
+/*
+ * Allwinner ralink USB phy driver

We should remove the "Allwinner" from the header

John




+ *
+ * Copyright (C) 2016 John Crispin 
+ *
+ * Based on code from
+ * Allwinner Technology Co., Ltd. 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#define RT_SYSC_REG_SYSCFG10x014
+#define RT_SYSC_REG_CLKCFG10x030
+#define RT_SYSC_REG_USB_PHY_CFG0x05c
+
+#define RT_RSTCTRL_UDEVBIT(25)
+#define RT_RSTCTRL_UHSTBIT(22)
+#define RT_SYSCFG1_USB0_HOST_MODE  BIT(10)
+
+#define MT7620_CLKCFG1_UPHY0_CLK_ENBIT(25)
+#define MT7620_CLKCFG1_UPHY1_CLK_ENBIT(22)
+#define RT_CLKCFG1_UPHY1_CLK_ENBIT(20)
+#define RT_CLKCFG1_UPHY0_CLK_ENBIT(18)
+
+#define USB_PHY_UTMI_8B60M BIT(1)
+#define UDEV_WAKEUPBIT(0)
+
+struct ralink_usb_phy {
+   struct reset_control*rstdev;
+   struct reset_control*rsthost;
+   u32 clk;
+   struct phy  *phy;
+};
+
+static int ralink_usb_phy_power_on(struct phy *_phy)
+{
+   struct ralink_usb_phy *phy = phy_get_drvdata(_phy);
+   u32 t;
+
+   /* enable the phy */
+   rt_sysc_m32(0, phy->clk, RT_SYSC_REG_CLKCFG1);
+
+   /* setup host mode */
+   rt_sysc_m32(0, RT_SYSCFG1_USB0_HOST_MODE, RT_SYSC_REG_SYSCFG1);
+
+   /* deassert the reset lines */
+   reset_control_deassert(phy->rsthost);
+   reset_control_deassert(phy->rstdev);
+
+   /*
+* The SDK kernel had a delay of 100ms. however on device
+* testing showed that 10ms is enough
+*/
+   mdelay(10);
+
+   /* print some status info */
+   t = rt_sysc_r32(RT_SYSC_REG_USB_PHY_CFG);
+   dev_info(>phy->dev, "remote usb device wakeup %s\n",
+   (t & UDEV_WAKEUP) ? ("enabled") : ("disabled"));
+   if (t & USB_PHY_UTMI_8B60M)
+   dev_info(>phy->dev, "UTMI 8bit 60MHz\n");
+   else
+

Re: [PATCH v3 0/6] mediatek: pwm driver add MT2712/MT7622 support

[John Crispin]

On 02/08/17 09:19, Zhi Mao wrote:

Hi John, Matthais & Thierry,

Just a gentle ping on this issue again.
Do you have any update?

Regards,
Zhi

Hi Zhi,

looks good to me

Acked-by: John Crispin <j...@phrozen.org>

John

Re: [PATCH v3 0/6] mediatek: pwm driver add MT2712/MT7622 support

[John Crispin]

On 02/08/17 09:19, Zhi Mao wrote:

Hi John, Matthais & Thierry,

Just a gentle ping on this issue again.
Do you have any update?

Regards,
Zhi

Hi Zhi,

looks good to me

Acked-by: John Crispin 

John

Re: [PATCH net-next v3 4/4] MAINTAINERS: add Sean/Nelson as MediaTek ethernet maintainers

[John Crispin]

On 31/07/17 12:05, sean.w...@mediatek.com wrote:

From: Sean Wang <sean.w...@mediatek.com>

Sean and Nelson work for MediaTek on maintaining the MediaTek ethernet
driver for the existing SoCs and adding support for the following SoCs.
In the past, Sean has been active at making most of the qualifications
, stress test and submitting a lot of patches for the driver while
Nelson was looking into the aspects more on hardware additions and details
such as introducing PDMA with Hardware LRO to the driver. Also update
John's up-to-date mail address in the patch.

Cc: John Crispin <j...@phrozen.org>
Signed-off-by: Sean Wang <sean.w...@mediatek.com>
Signed-off-by: Nelson Chang <nelson.ch...@mediatek.com>


Acked-by: John Crispin <j...@phrozen.org>


---
  MAINTAINERS | 4 +++-
  1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index bd22d07..22faf704 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8431,7 +8431,9 @@ F:include/uapi/linux/uvcvideo.h
  
  MEDIATEK ETHERNET DRIVER

  M:Felix Fietkau <n...@openwrt.org>
-M: John Crispin <blo...@openwrt.org>
+M: John Crispin <j...@phrozen.org>
+M: Sean Wang <sean.w...@mediatek.com>
+M: Nelson Chang <nelson.ch...@mediatek.com>
  L:net...@vger.kernel.org
  S:Maintained
  F:drivers/net/ethernet/mediatek/

Re: [PATCH net-next v3 4/4] MAINTAINERS: add Sean/Nelson as MediaTek ethernet maintainers

[John Crispin]

On 31/07/17 12:05, sean.w...@mediatek.com wrote:

From: Sean Wang 

Sean and Nelson work for MediaTek on maintaining the MediaTek ethernet
driver for the existing SoCs and adding support for the following SoCs.
In the past, Sean has been active at making most of the qualifications
, stress test and submitting a lot of patches for the driver while
Nelson was looking into the aspects more on hardware additions and details
such as introducing PDMA with Hardware LRO to the driver. Also update
John's up-to-date mail address in the patch.

Cc: John Crispin 
Signed-off-by: Sean Wang 
Signed-off-by: Nelson Chang 


Acked-by: John Crispin 


---
  MAINTAINERS | 4 +++-
  1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index bd22d07..22faf704 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8431,7 +8431,9 @@ F:include/uapi/linux/uvcvideo.h
  
  MEDIATEK ETHERNET DRIVER

  M:Felix Fietkau 
-M: John Crispin 
+M: John Crispin 
+M: Sean Wang 
+M: Nelson Chang 
  L:net...@vger.kernel.org
  S:Maintained
  F:drivers/net/ethernet/mediatek/

Re: [PATCH V2 3/4] net-next: dsa: fix flow dissection

[John Crispin]

On 26/07/17 17:10, Andrew Lunn wrote:

On Fri, Jul 21, 2017 at 10:58:12AM +0200, John Crispin wrote:

RPS and probably other kernel features are currently broken on some if not
all DSA devices. The root cause of this is that skb_hash will call the
flow_dissector. At this point the skb still contains the magic switch header
and the skb->protocol field is not set up to the correct 802.3 value yet.
By the time the tag specific code is called, removing the header and
properly setting the protocol an invalid hash is already set. In the case
of the mt7530 this will result in all flows always having the same hash.

This patch makes the flow dissector honour the nh and protocol offset
defined by the dsa tag driver thus fixing dissection, hashing and RPS.

Signed-off-by: John Crispin <j...@phrozen.org>
---
  net/core/flow_dissector.c | 12 
  1 file changed, 12 insertions(+)

diff --git a/net/core/flow_dissector.c b/net/core/flow_dissector.c
index fc5fc4594c90..1268ae75c3b3 100644
--- a/net/core/flow_dissector.c
+++ b/net/core/flow_dissector.c
@@ -4,6 +4,7 @@
  #include 
  #include 
  #include 
+#include 
  #include 
  #include 
  #include 
@@ -440,6 +441,17 @@ bool __skb_flow_dissect(const struct sk_buff *skb,
 skb->vlan_proto : skb->protocol;
nhoff = skb_network_offset(skb);
hlen = skb_headlen(skb);
+
+   if (unlikely(netdev_uses_dsa(skb->dev))) {
+   const struct dsa_device_ops *ops;
+   u8 *p = (u8 *)data;
+
+   ops = skb->dev->dsa_ptr->tag_ops;
+   if (ops->hash_proto_off)
+   proto = (u16)p[ops->hash_proto_off];

Hi John

Unfortunately, this is not generic enough to work for DSA and EDSA
tagging. With these tagging protocols, the size of the tag depends on
the presence or not of a VLAN header.

To make this work for all tagging protocols, we are going to need to
add an a new op to tag_ops.

 Andrew

Hi Andrew,

thanks for the feedback. should I add 2 callbacks for each of the 2 
parameters ?


John

Re: [PATCH V2 3/4] net-next: dsa: fix flow dissection

[John Crispin]

On 26/07/17 17:10, Andrew Lunn wrote:

On Fri, Jul 21, 2017 at 10:58:12AM +0200, John Crispin wrote:

RPS and probably other kernel features are currently broken on some if not
all DSA devices. The root cause of this is that skb_hash will call the
flow_dissector. At this point the skb still contains the magic switch header
and the skb->protocol field is not set up to the correct 802.3 value yet.
By the time the tag specific code is called, removing the header and
properly setting the protocol an invalid hash is already set. In the case
of the mt7530 this will result in all flows always having the same hash.

This patch makes the flow dissector honour the nh and protocol offset
defined by the dsa tag driver thus fixing dissection, hashing and RPS.

Signed-off-by: John Crispin 
---
  net/core/flow_dissector.c | 12 
  1 file changed, 12 insertions(+)

diff --git a/net/core/flow_dissector.c b/net/core/flow_dissector.c
index fc5fc4594c90..1268ae75c3b3 100644
--- a/net/core/flow_dissector.c
+++ b/net/core/flow_dissector.c
@@ -4,6 +4,7 @@
  #include 
  #include 
  #include 
+#include 
  #include 
  #include 
  #include 
@@ -440,6 +441,17 @@ bool __skb_flow_dissect(const struct sk_buff *skb,
 skb->vlan_proto : skb->protocol;
nhoff = skb_network_offset(skb);
hlen = skb_headlen(skb);
+
+   if (unlikely(netdev_uses_dsa(skb->dev))) {
+   const struct dsa_device_ops *ops;
+   u8 *p = (u8 *)data;
+
+   ops = skb->dev->dsa_ptr->tag_ops;
+   if (ops->hash_proto_off)
+   proto = (u16)p[ops->hash_proto_off];

Hi John

Unfortunately, this is not generic enough to work for DSA and EDSA
tagging. With these tagging protocols, the size of the tag depends on
the presence or not of a VLAN header.

To make this work for all tagging protocols, we are going to need to
add an a new op to tag_ops.

 Andrew

Hi Andrew,

thanks for the feedback. should I add 2 callbacks for each of the 2 
parameters ?


John

Re: [RFC 1/2] net-next: add a dma_desc element to struct skb_shared_info

[John Crispin]

On 21/07/17 17:56, Paolo Abeni wrote:

Hi,

On Fri, 2017-07-21 at 17:20 +0200, John Crispin wrote:

In order to make HW flow offloading work in latest MediaTek silicon we need
to propagate part of the RX DMS descriptor to the upper layers populating
the flow offload engines HW tables. This patch adds an extra element to
struct skb_shared_info allowing the ethernet drivers RX napi code to store
the required information and make it persistent for the lifecycle of the
skb and its clones.

Signed-off-by: John Crispin <j...@phrozen.org>
---
  include/linux/skbuff.h | 1 +
  1 file changed, 1 insertion(+)

diff --git a/include/linux/skbuff.h b/include/linux/skbuff.h
index 4093552be1de..db9576cd946b 100644
--- a/include/linux/skbuff.h
+++ b/include/linux/skbuff.h
@@ -426,6 +426,7 @@ struct skb_shared_info {
unsigned intgso_type;
u32 tskey;
__be32  ip6_frag_id;
+   u32 dma_desc;
  
  	/*

 * Warning : all fields before dataref are cleared in __alloc_skb()

This will increase the skb_shared_info struct size, which is already
quite large, and can have several kind of performance drawback.
AFAIK this is discouraged.

I don't understand the use case; the driver will set this field, but
who is going to consume it?

Thanks,

Paolo

Hi Paolo,

When the flow offloading engine forwards a packet to the DMA it will 
send additional info to the sw path. this includes

* physical switch port
* internal flow hash - this is required to populate the correct flow 
table entry
* ppe state - this indicates what state the PPEs internal table is in 
for the flow
* the reason why the packet was forwarde - these are things like bind, 
unbind, timed out, ...


once the flow table offloading patches are ready and upstream, the 
netfilter layer will see the SKB and pass it o to the flow table 
offloading code, at which point it will finally end up inside the 
offloading driver. this will need to have access to this info sent to 
the sw path inside the rx descriptor to properly work out what state the 
flow is in and which table entry to populate in the HW table for 
offloading to work.


Hope that is a little clearer. current hackish driver is here [1], the 
patch to the ethernet driver is here [2]


John

[1] 
https://git.lede-project.org/?p=lede/blogic/staging.git;a=tree;f=target/linux/mediatek/files/drivers/net/ethernet/mediatek/mtk_hnat;hb=bc0518b9d928b43d965d8a1f8860281f0ae6a31c
[2] 
https://git.lede-project.org/?p=lede/blogic/staging.git;a=blob;f=target/linux/mediatek/patches-4.9/0310-hwnat.patch;h=57bd0c07b39d2169f3ba08e1aa83b92dffcee025;hb=bc0518b9d928b43d965d8a1f8860281f0ae6a31c

Re: [RFC 1/2] net-next: add a dma_desc element to struct skb_shared_info

[John Crispin]

On 21/07/17 17:56, Paolo Abeni wrote:

Hi,

On Fri, 2017-07-21 at 17:20 +0200, John Crispin wrote:

In order to make HW flow offloading work in latest MediaTek silicon we need
to propagate part of the RX DMS descriptor to the upper layers populating
the flow offload engines HW tables. This patch adds an extra element to
struct skb_shared_info allowing the ethernet drivers RX napi code to store
the required information and make it persistent for the lifecycle of the
skb and its clones.

Signed-off-by: John Crispin 
---
  include/linux/skbuff.h | 1 +
  1 file changed, 1 insertion(+)

diff --git a/include/linux/skbuff.h b/include/linux/skbuff.h
index 4093552be1de..db9576cd946b 100644
--- a/include/linux/skbuff.h
+++ b/include/linux/skbuff.h
@@ -426,6 +426,7 @@ struct skb_shared_info {
unsigned intgso_type;
u32 tskey;
__be32  ip6_frag_id;
+   u32 dma_desc;
  
  	/*

 * Warning : all fields before dataref are cleared in __alloc_skb()

This will increase the skb_shared_info struct size, which is already
quite large, and can have several kind of performance drawback.
AFAIK this is discouraged.

I don't understand the use case; the driver will set this field, but
who is going to consume it?

Thanks,

Paolo

Hi Paolo,

When the flow offloading engine forwards a packet to the DMA it will 
send additional info to the sw path. this includes

* physical switch port
* internal flow hash - this is required to populate the correct flow 
table entry
* ppe state - this indicates what state the PPEs internal table is in 
for the flow
* the reason why the packet was forwarde - these are things like bind, 
unbind, timed out, ...


once the flow table offloading patches are ready and upstream, the 
netfilter layer will see the SKB and pass it o to the flow table 
offloading code, at which point it will finally end up inside the 
offloading driver. this will need to have access to this info sent to 
the sw path inside the rx descriptor to properly work out what state the 
flow is in and which table entry to populate in the HW table for 
offloading to work.


Hope that is a little clearer. current hackish driver is here [1], the 
patch to the ethernet driver is here [2]


John

[1] 
https://git.lede-project.org/?p=lede/blogic/staging.git;a=tree;f=target/linux/mediatek/files/drivers/net/ethernet/mediatek/mtk_hnat;hb=bc0518b9d928b43d965d8a1f8860281f0ae6a31c
[2] 
https://git.lede-project.org/?p=lede/blogic/staging.git;a=blob;f=target/linux/mediatek/patches-4.9/0310-hwnat.patch;h=57bd0c07b39d2169f3ba08e1aa83b92dffcee025;hb=bc0518b9d928b43d965d8a1f8860281f0ae6a31c

[RFC 1/2] net-next: add a dma_desc element to struct skb_shared_info

[John Crispin]

In order to make HW flow offloading work in latest MediaTek silicon we need
to propagate part of the RX DMS descriptor to the upper layers populating
the flow offload engines HW tables. This patch adds an extra element to
struct skb_shared_info allowing the ethernet drivers RX napi code to store
the required information and make it persistent for the lifecycle of the
skb and its clones.

Signed-off-by: John Crispin <j...@phrozen.org>
---
 include/linux/skbuff.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/linux/skbuff.h b/include/linux/skbuff.h
index 4093552be1de..db9576cd946b 100644
--- a/include/linux/skbuff.h
+++ b/include/linux/skbuff.h
@@ -426,6 +426,7 @@ struct skb_shared_info {
unsigned intgso_type;
u32 tskey;
__be32  ip6_frag_id;
+   u32 dma_desc;
 
/*
 * Warning : all fields before dataref are cleared in __alloc_skb()
-- 
2.11.0

[RFC 1/2] net-next: add a dma_desc element to struct skb_shared_info

[John Crispin]

In order to make HW flow offloading work in latest MediaTek silicon we need
to propagate part of the RX DMS descriptor to the upper layers populating
the flow offload engines HW tables. This patch adds an extra element to
struct skb_shared_info allowing the ethernet drivers RX napi code to store
the required information and make it persistent for the lifecycle of the
skb and its clones.

Signed-off-by: John Crispin 
---
 include/linux/skbuff.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/linux/skbuff.h b/include/linux/skbuff.h
index 4093552be1de..db9576cd946b 100644
--- a/include/linux/skbuff.h
+++ b/include/linux/skbuff.h
@@ -426,6 +426,7 @@ struct skb_shared_info {
unsigned intgso_type;
u32 tskey;
__be32  ip6_frag_id;
+   u32 dma_desc;
 
/*
 * Warning : all fields before dataref are cleared in __alloc_skb()
-- 
2.11.0

[RFC 0/2] net-next: hw flow offloading

[John Crispin]

Hi,

I managed to bring up the flow offloading on latest MedieTek silicon.

When enabling HW flow offloading, the traffic coming in on either of the
GMACs is first sent to the PPE for processing. Any traffic not offloaded
at this point will then be forwarded to the normal RX DMA ring for SW path
processing. In this case the PPE will send additional data inside RXD4
that is later required by the upper layers to populate the flow offloading
engines HW tables properly.

This series is a RFC as i am not sure how to best propagate the additional
info from the RX DMA descriptor. The driver is still using NF hooks and
I plan to rebase it and send it upstream once the flow table offloading
patches that folks are working on are upstream.

I am right now trying to get rid of the remaning hacks in the code and
wanted to know if this series would be a feasible solution.

John

John Crispin (2):
  net-next: add a dma_desc element to struct skb_shared_info
  net-next: mediatek: populate the shared

 drivers/net/ethernet/mediatek/mtk_eth_soc.c | 4 
 include/linux/skbuff.h  | 1 +
 2 files changed, 5 insertions(+)

-- 
2.11.0

[RFC 0/2] net-next: hw flow offloading

[John Crispin]

Hi,

I managed to bring up the flow offloading on latest MedieTek silicon.

When enabling HW flow offloading, the traffic coming in on either of the
GMACs is first sent to the PPE for processing. Any traffic not offloaded
at this point will then be forwarded to the normal RX DMA ring for SW path
processing. In this case the PPE will send additional data inside RXD4
that is later required by the upper layers to populate the flow offloading
engines HW tables properly.

This series is a RFC as i am not sure how to best propagate the additional
info from the RX DMA descriptor. The driver is still using NF hooks and
I plan to rebase it and send it upstream once the flow table offloading
patches that folks are working on are upstream.

I am right now trying to get rid of the remaning hacks in the code and
wanted to know if this series would be a feasible solution.

John

John Crispin (2):
  net-next: add a dma_desc element to struct skb_shared_info
  net-next: mediatek: populate the shared

 drivers/net/ethernet/mediatek/mtk_eth_soc.c | 4 
 include/linux/skbuff.h  | 1 +
 2 files changed, 5 insertions(+)

-- 
2.11.0

[RFC 2/2] net-next: mediatek: populate the shared

[John Crispin]

When enabling HW flow offloading, the traffic coming in on either of the
GMACs is first sent to the PPE for processing. Any traffic not offloaded
at this point will then be forwarded to the normal RX DMA ring for SW path
processing. In this case the PPE will send additional data inside RXD4
that is later required by the upper layers to populate the flow offloading
engines HW tables properly. This patch sets the skb_shared_info's dma_desc
field so that we can use the value later on.

Signed-off-by: John Crispin <j...@phrozen.org>
---
 drivers/net/ethernet/mediatek/mtk_eth_soc.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c 
b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index a455d1b4f1d8..42d162cd6363 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -918,6 +918,7 @@ static void mtk_update_rx_cpu_idx(struct mtk_eth *eth)
 static int mtk_poll_rx(struct napi_struct *napi, int budget,
   struct mtk_eth *eth)
 {
+   struct skb_shared_info *sh;
struct mtk_rx_ring *ring;
int idx;
struct sk_buff *skb;
@@ -1000,6 +1001,9 @@ static int mtk_poll_rx(struct napi_struct *napi, int 
budget,
else
skb_checksum_none_assert(skb);
skb->protocol = eth_type_trans(skb, netdev);
+   sh = skb_shinfo(skb);
+
+   sh->dma_desc = trxd.rxd4;
 
if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX &&
RX_DMA_VID(trxd.rxd3))
-- 
2.11.0

[RFC 2/2] net-next: mediatek: populate the shared

[John Crispin]

When enabling HW flow offloading, the traffic coming in on either of the
GMACs is first sent to the PPE for processing. Any traffic not offloaded
at this point will then be forwarded to the normal RX DMA ring for SW path
processing. In this case the PPE will send additional data inside RXD4
that is later required by the upper layers to populate the flow offloading
engines HW tables properly. This patch sets the skb_shared_info's dma_desc
field so that we can use the value later on.

Signed-off-by: John Crispin 
---
 drivers/net/ethernet/mediatek/mtk_eth_soc.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c 
b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index a455d1b4f1d8..42d162cd6363 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -918,6 +918,7 @@ static void mtk_update_rx_cpu_idx(struct mtk_eth *eth)
 static int mtk_poll_rx(struct napi_struct *napi, int budget,
   struct mtk_eth *eth)
 {
+   struct skb_shared_info *sh;
struct mtk_rx_ring *ring;
int idx;
struct sk_buff *skb;
@@ -1000,6 +1001,9 @@ static int mtk_poll_rx(struct napi_struct *napi, int 
budget,
else
skb_checksum_none_assert(skb);
skb->protocol = eth_type_trans(skb, netdev);
+   sh = skb_shinfo(skb);
+
+   sh->dma_desc = trxd.rxd4;
 
if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX &&
RX_DMA_VID(trxd.rxd3))
-- 
2.11.0

[PATCH V2 4/4] net-next: tag_mtk: add nh and proto offsets to the ops struct

[John Crispin]

The MT7530 inserts the 4 magic header in between the 802.3 address and
protocol field. The patch defines these header such that the flow_disector
can properly parse the packet and thus allows hashing to function properly.

Signed-off-by: John Crispin <j...@phrozen.org>
---
 net/dsa/tag_mtk.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/net/dsa/tag_mtk.c b/net/dsa/tag_mtk.c
index 2f32b7ea3365..142322988202 100644
--- a/net/dsa/tag_mtk.c
+++ b/net/dsa/tag_mtk.c
@@ -88,6 +88,8 @@ static struct sk_buff *mtk_tag_rcv(struct sk_buff *skb, 
struct net_device *dev,
 }
 
 const struct dsa_device_ops mtk_netdev_ops = {
-   .xmit   = mtk_tag_xmit,
-   .rcv= mtk_tag_rcv,
+   .xmit   = mtk_tag_xmit,
+   .rcv= mtk_tag_rcv,
+   .hash_nh_off= 4,
+   .hash_proto_off = 2,
 };
-- 
2.11.0

[PATCH V2 4/4] net-next: tag_mtk: add nh and proto offsets to the ops struct

[John Crispin]

The MT7530 inserts the 4 magic header in between the 802.3 address and
protocol field. The patch defines these header such that the flow_disector
can properly parse the packet and thus allows hashing to function properly.

Signed-off-by: John Crispin 
---
 net/dsa/tag_mtk.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/net/dsa/tag_mtk.c b/net/dsa/tag_mtk.c
index 2f32b7ea3365..142322988202 100644
--- a/net/dsa/tag_mtk.c
+++ b/net/dsa/tag_mtk.c
@@ -88,6 +88,8 @@ static struct sk_buff *mtk_tag_rcv(struct sk_buff *skb, 
struct net_device *dev,
 }
 
 const struct dsa_device_ops mtk_netdev_ops = {
-   .xmit   = mtk_tag_xmit,
-   .rcv= mtk_tag_rcv,
+   .xmit   = mtk_tag_xmit,
+   .rcv= mtk_tag_rcv,
+   .hash_nh_off= 4,
+   .hash_proto_off = 2,
 };
-- 
2.11.0

[PATCH V2 1/4] net-next: dsa: move struct dsa_device_ops to the global header file

[John Crispin]

We need to access this struct from within the flow_dissector to fix
dissection for packets coming in on DSA devices.

Signed-off-by: John Crispin <j...@phrozen.org>
---
 include/net/dsa.h  | 7 +++
 net/dsa/dsa_priv.h | 7 ---
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/include/net/dsa.h b/include/net/dsa.h
index 88da272d20d0..a4c0d52abc80 100644
--- a/include/net/dsa.h
+++ b/include/net/dsa.h
@@ -101,6 +101,13 @@ struct dsa_platform_data {
 
 struct packet_type;
 
+struct dsa_device_ops {
+   struct sk_buff *(*xmit)(struct sk_buff *skb, struct net_device *dev);
+   struct sk_buff *(*rcv)(struct sk_buff *skb, struct net_device *dev,
+  struct packet_type *pt,
+  struct net_device *orig_dev);
+};
+
 struct dsa_switch_tree {
struct list_headlist;
 
diff --git a/net/dsa/dsa_priv.h b/net/dsa/dsa_priv.h
index 55982cc39b24..62ea3663c2c6 100644
--- a/net/dsa/dsa_priv.h
+++ b/net/dsa/dsa_priv.h
@@ -65,13 +65,6 @@ struct dsa_notifier_vlan_info {
int port;
 };
 
-struct dsa_device_ops {
-   struct sk_buff *(*xmit)(struct sk_buff *skb, struct net_device *dev);
-   struct sk_buff *(*rcv)(struct sk_buff *skb, struct net_device *dev,
-  struct packet_type *pt,
-  struct net_device *orig_dev);
-};
-
 struct dsa_slave_priv {
/* Copy of dp->ds->dst->tag_ops->xmit for faster access in hot path */
struct sk_buff *(*xmit)(struct sk_buff *skb,
-- 
2.11.0

[PATCH V2 1/4] net-next: dsa: move struct dsa_device_ops to the global header file

[John Crispin]

We need to access this struct from within the flow_dissector to fix
dissection for packets coming in on DSA devices.

Signed-off-by: John Crispin 
---
 include/net/dsa.h  | 7 +++
 net/dsa/dsa_priv.h | 7 ---
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/include/net/dsa.h b/include/net/dsa.h
index 88da272d20d0..a4c0d52abc80 100644
--- a/include/net/dsa.h
+++ b/include/net/dsa.h
@@ -101,6 +101,13 @@ struct dsa_platform_data {
 
 struct packet_type;
 
+struct dsa_device_ops {
+   struct sk_buff *(*xmit)(struct sk_buff *skb, struct net_device *dev);
+   struct sk_buff *(*rcv)(struct sk_buff *skb, struct net_device *dev,
+  struct packet_type *pt,
+  struct net_device *orig_dev);
+};
+
 struct dsa_switch_tree {
struct list_headlist;
 
diff --git a/net/dsa/dsa_priv.h b/net/dsa/dsa_priv.h
index 55982cc39b24..62ea3663c2c6 100644
--- a/net/dsa/dsa_priv.h
+++ b/net/dsa/dsa_priv.h
@@ -65,13 +65,6 @@ struct dsa_notifier_vlan_info {
int port;
 };
 
-struct dsa_device_ops {
-   struct sk_buff *(*xmit)(struct sk_buff *skb, struct net_device *dev);
-   struct sk_buff *(*rcv)(struct sk_buff *skb, struct net_device *dev,
-  struct packet_type *pt,
-  struct net_device *orig_dev);
-};
-
 struct dsa_slave_priv {
/* Copy of dp->ds->dst->tag_ops->xmit for faster access in hot path */
struct sk_buff *(*xmit)(struct sk_buff *skb,
-- 
2.11.0

[PATCH V2 3/4] net-next: dsa: fix flow dissection

[John Crispin]

RPS and probably other kernel features are currently broken on some if not
all DSA devices. The root cause of this is that skb_hash will call the
flow_dissector. At this point the skb still contains the magic switch header
and the skb->protocol field is not set up to the correct 802.3 value yet.
By the time the tag specific code is called, removing the header and
properly setting the protocol an invalid hash is already set. In the case
of the mt7530 this will result in all flows always having the same hash.

This patch makes the flow dissector honour the nh and protocol offset
defined by the dsa tag driver thus fixing dissection, hashing and RPS.

Signed-off-by: John Crispin <j...@phrozen.org>
---
 net/core/flow_dissector.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/net/core/flow_dissector.c b/net/core/flow_dissector.c
index fc5fc4594c90..1268ae75c3b3 100644
--- a/net/core/flow_dissector.c
+++ b/net/core/flow_dissector.c
@@ -4,6 +4,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -440,6 +441,17 @@ bool __skb_flow_dissect(const struct sk_buff *skb,
 skb->vlan_proto : skb->protocol;
nhoff = skb_network_offset(skb);
hlen = skb_headlen(skb);
+
+   if (unlikely(netdev_uses_dsa(skb->dev))) {
+   const struct dsa_device_ops *ops;
+   u8 *p = (u8 *)data;
+
+   ops = skb->dev->dsa_ptr->tag_ops;
+   if (ops->hash_proto_off)
+   proto = (u16)p[ops->hash_proto_off];
+   hlen -= ops->hash_nh_off;
+   nhoff += ops->hash_nh_off;
+   }
}
 
/* It is ensured by skb_flow_dissector_init() that control key will
-- 
2.11.0

[PATCH V2 3/4] net-next: dsa: fix flow dissection

[John Crispin]

RPS and probably other kernel features are currently broken on some if not
all DSA devices. The root cause of this is that skb_hash will call the
flow_dissector. At this point the skb still contains the magic switch header
and the skb->protocol field is not set up to the correct 802.3 value yet.
By the time the tag specific code is called, removing the header and
properly setting the protocol an invalid hash is already set. In the case
of the mt7530 this will result in all flows always having the same hash.

This patch makes the flow dissector honour the nh and protocol offset
defined by the dsa tag driver thus fixing dissection, hashing and RPS.

Signed-off-by: John Crispin 
---
 net/core/flow_dissector.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/net/core/flow_dissector.c b/net/core/flow_dissector.c
index fc5fc4594c90..1268ae75c3b3 100644
--- a/net/core/flow_dissector.c
+++ b/net/core/flow_dissector.c
@@ -4,6 +4,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -440,6 +441,17 @@ bool __skb_flow_dissect(const struct sk_buff *skb,
 skb->vlan_proto : skb->protocol;
nhoff = skb_network_offset(skb);
hlen = skb_headlen(skb);
+
+   if (unlikely(netdev_uses_dsa(skb->dev))) {
+   const struct dsa_device_ops *ops;
+   u8 *p = (u8 *)data;
+
+   ops = skb->dev->dsa_ptr->tag_ops;
+   if (ops->hash_proto_off)
+   proto = (u16)p[ops->hash_proto_off];
+   hlen -= ops->hash_nh_off;
+   nhoff += ops->hash_nh_off;
+   }
}
 
/* It is ensured by skb_flow_dissector_init() that control key will
-- 
2.11.0

[PATCH V2 2/4] net-next: dsa: add 802.3 protocol offset to struct dsa_device_ops

[John Crispin]

Adding these 2 new fields allows a DSA device to indicate the offsets of
the 802.3 header caused by the insertion of the switches tag.

Signed-off-by: John Crispin <j...@phrozen.org>
---
 include/net/dsa.h | 5 +
 1 file changed, 5 insertions(+)

diff --git a/include/net/dsa.h b/include/net/dsa.h
index a4c0d52abc80..b98bc3621905 100644
--- a/include/net/dsa.h
+++ b/include/net/dsa.h
@@ -106,6 +106,11 @@ struct dsa_device_ops {
struct sk_buff *(*rcv)(struct sk_buff *skb, struct net_device *dev,
   struct packet_type *pt,
   struct net_device *orig_dev);
+   /*
+* Network header and 802.3 protocol offsets
+*/
+   int hash_nh_off;
+   int hash_proto_off;
 };
 
 struct dsa_switch_tree {
-- 
2.11.0

[PATCH V2 2/4] net-next: dsa: add 802.3 protocol offset to struct dsa_device_ops

[John Crispin]

Adding these 2 new fields allows a DSA device to indicate the offsets of
the 802.3 header caused by the insertion of the switches tag.

Signed-off-by: John Crispin 
---
 include/net/dsa.h | 5 +
 1 file changed, 5 insertions(+)

diff --git a/include/net/dsa.h b/include/net/dsa.h
index a4c0d52abc80..b98bc3621905 100644
--- a/include/net/dsa.h
+++ b/include/net/dsa.h
@@ -106,6 +106,11 @@ struct dsa_device_ops {
struct sk_buff *(*rcv)(struct sk_buff *skb, struct net_device *dev,
   struct packet_type *pt,
   struct net_device *orig_dev);
+   /*
+* Network header and 802.3 protocol offsets
+*/
+   int hash_nh_off;
+   int hash_proto_off;
 };
 
 struct dsa_switch_tree {
-- 
2.11.0

Re: [PATCH net] net: ethernet: mediatek: avoid potential invalid memory access

[John Crispin]

On 20/07/17 08:52, sean.w...@mediatek.com wrote:

From: Sean Wang <sean.w...@mediatek.com>

Potential dangerous invalid memory might be accessed if invalid mac value
reflected from the forward port field in rxd4 caused by possible potential
hardware defects. So added a simple sanity checker to avoid the kind of
situation happening.

Signed-off-by: Sean Wang <sean.w...@mediatek.com>


Thanks, i ran into the same problem last week and was going to send a 
fix shortly.


Acked-by: John Crispin <j...@phrozen.org>


---
  drivers/net/ethernet/mediatek/mtk_eth_soc.c | 6 ++
  1 file changed, 6 insertions(+)

diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c 
b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index c1dc08c..8175433 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -999,6 +999,12 @@ static int mtk_poll_rx(struct napi_struct *napi, int 
budget,
  RX_DMA_FPORT_MASK;
mac--;
  
+		if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT ||

+!eth->netdev[mac])) {
+   netdev->stats.rx_dropped++;
+   goto release_desc;
+   }
+
netdev = eth->netdev[mac];
  
  		if (unlikely(test_bit(MTK_RESETTING, >state)))