On 3/5/21 5:45 PM, Dmitry Baryshkov wrote:
On 15/02/2021 19:27, Jonathan Marek wrote:
Add the required changes to support 7nm pll/phy in CPHY mode.
This adds a "qcom,dsi-phy-cphy-mode" property for the PHY node to enable
the CPHY mode.
Signed-off-by: Jonathan Marek
Other that fe
On 3/5/21 4:48 PM, Rob Herring wrote:
On Mon, Feb 15, 2021 at 11:27:44AM -0500, Jonathan Marek wrote:
Add the required changes to support 7nm pll/phy in CPHY mode.
This adds a "qcom,dsi-phy-cphy-mode" property for the PHY node to enable
the CPHY mode.
Signed-off-by: Jona
D_SOC_NOPM as the register and use an enum in
the shift field instead.
Fixes: 2c4066e5d428 ("ASoC: codecs: lpass-wsa-macro: add dapm widgets and
route")
Signed-off-by: Jonathan Marek
---
sound/soc/codecs/lpass-wsa-macro.c | 20 +++-
1 file changed, 11 insertions(+), 9 deletions(-)
On 3/4/21 7:05 PM, Bjorn Andersson wrote:
On Thu 04 Mar 13:48 CST 2021, Jonathan Marek wrote:
If these fields are not set in dts, the driver will use these variables
uninitialized to set the fields. Not only will it set garbage values for
these fields, but it can overflow into other fields
ld.
Fixes: 908e6b1df26e ("ASoC: codecs: lpass-va-macro: Add support to VA Macro")
Signed-off-by: Jonathan Marek
---
sound/soc/codecs/lpass-va-macro.c | 28 +---
1 file changed, 13 insertions(+), 15 deletions(-)
diff --git a/sound/soc/codecs/lpass-va-macro.c
b/sound
,
and might not work without this change.
Fixes: 6e261d1090d6 ("pinctrl: qcom: Add sm8250 lpass lpi pinctrl driver")
Signed-off-by: Jonathan Marek
---
drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/qcom/pinctrl-lpas
On 2/22/21 7:37 AM, Srinivas Kandagatla wrote:
On 18/02/2021 03:20, Jonathan Marek wrote:
fastrpc_internal_invoke() will call fastrpc_map_create, so there is no
point in having it called here. This does change the behavior somewhat as
fastrpc_internal_invoke() will release the map afterwards
fastrpc_internal_invoke() will call fastrpc_map_create, so there is no
point in having it called here. This does change the behavior somewhat as
fastrpc_internal_invoke() will release the map afterwards, but that's what
we want to happen in this case.
Signed-off-by: Jonathan Marek
---
drivers
ion with fastrpc_map_find() logic.
Signed-off-by: Jonathan Marek
---
drivers/misc/fastrpc.c | 27 +--
1 file changed, 13 insertions(+), 14 deletions(-)
diff --git a/drivers/misc/fastrpc.c b/drivers/misc/fastrpc.c
index 4fabea0c1551..170352b43ab6 100644
--- a/drivers/misc/fastrp
dmabuf arguments are completely broken, these patches make it possible
to actually use dmabuf arguments (in particular, the second patch).
Jonathan Marek (3):
fastrpc: always use fl->lock and remove fl->mutex
fastrpc: move fl->maps list removal into fastrpc_free_map
fastrp
Fix the broken behavior of having a separate mutex for locking at this
place, and use the same spinlock that is used to add/remove from the list.
Signed-off-by: Jonathan Marek
---
drivers/misc/fastrpc.c | 11 +++
1 file changed, 3 insertions(+), 8 deletions(-)
diff --git a/drivers/misc
On 2/17/21 3:18 PM, Rob Clark wrote:
On Wed, Feb 17, 2021 at 11:08 AM Jordan Crouse wrote:
On Wed, Feb 17, 2021 at 07:14:16PM +0530, Akhil P Oommen wrote:
On 2/17/2021 8:36 AM, Rob Clark wrote:
On Tue, Feb 16, 2021 at 12:10 PM Jonathan Marek wrote:
Ignore nvmem_cell_get() EOPNOTSUPP
On 2/16/21 11:53 PM, Viresh Kumar wrote:
On 16-02-21, 15:10, Jonathan Marek wrote:
There is not "nothing to do" when the opp is the same. The frequency can
be different from opp->rate.
I am sorry but I am not sure what are you trying to fix here and what exactly is
broken
Ignore nvmem_cell_get() EOPNOTSUPP error in the same way as a ENOENT error,
to fix the case where the kernel was compiled without CONFIG_NVMEM.
Fixes: fe7952c629da ("drm/msm: Add speed-bin support to a618 gpu")
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx
There is not "nothing to do" when the opp is the same. The frequency can
be different from opp->rate.
Fixes: 81c4d8a3c414 ("opp: Keep track of currently programmed OPP")
Signed-off-by: Jonathan Marek
---
drivers/opp/core.c | 7 +--
drivers/opp/opp.h | 1 +
2 file
On 2/16/21 11:54 AM, Dmitry Baryshkov wrote:
On Mon, 15 Feb 2021 at 19:25, Jonathan Marek wrote:
The driver already has support for sm8150/sm8250, but the compatibles were
never added.
Also inverse the non-mdp4 condition in add_display_components() to avoid
having to check every new
Add the required changes to support 7nm pll/phy in CPHY mode.
This adds a "qcom,dsi-phy-cphy-mode" property for the PHY node to enable
the CPHY mode.
Signed-off-by: Jonathan Marek
---
.../devicetree/bindings/display/msm/dsi.txt | 1 +
drivers/gpu/drm/msm/dsi/dsi.c
On 2/11/21 3:05 PM, Dmitry Baryshkov wrote:
On Thu, 11 Feb 2021 at 21:11, Jonathan Marek wrote:
Apply these fixes to the newly added sm8250 display ndoes
- Use sm8250 compatibles instead of sdm845 compatibles
- Remove "notused" interconnect (which apparently was blindly copied f
documented or used by the driver and fixing the region size.
Fixes: 7c1dffd471b1 ("arm64: dts: qcom: sm8250.dtsi: add display system nodes")
Signed-off-by: Jonathan Marek
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 31 +++-
1 file changed, 8 insertions(+), 23 dele
The driver already has support for sm8150/sm8250, but the compatibles were
never added.
Also inverse the non-mdp4 condition in add_display_components() to avoid
having to check every new compatible in the condition.
Signed-off-by: Jonathan Marek
---
Documentation/devicetree/bindings/display
Add sm8150/sm8250 compatibles to drm/msm and fix the sm8250
display nodes.
v2: do not remove mmcx-supply from dispcc node
v3: remove references to dp_phy (missed this in v2, sorry for the spam)
Jonathan Marek (2):
drm/msm: add compatibles for sm8150/sm8250 display
arm64: dts: qcom: sm8250
documented or used by the driver and fixing the region size.
Fixes: 7c1dffd471b1 ("arm64: dts: qcom: sm8250.dtsi: add display system nodes")
Signed-off-by: Jonathan Marek
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 33
1 file changed, 9 insertions(+), 24 dele
The driver already has support for sm8150/sm8250, but the compatibles were
never added.
Also inverse the non-mdp4 condition in add_display_components() to avoid
having to check every new compatible in the condition.
Signed-off-by: Jonathan Marek
---
Documentation/devicetree/bindings/display
Add sm8150/sm8250 compatibles to drm/msm and fix the sm8250
display nodes.
v2: do not remove mmcx-supply from dispcc node
Jonathan Marek (2):
drm/msm: add compatibles for sm8150/sm8250 display
arm64: dts: qcom: sm8250: fix display nodes
.../devicetree/bindings/display/msm/dpu.txt | 4
The driver already has support for sm8150/sm8250, but the compatibles were
never added.
Also inverse the non-mdp4 condition in add_display_components() to avoid
having to check every new compatible in the condition.
Signed-off-by: Jonathan Marek
---
Documentation/devicetree/bindings/display
Add sm8150/sm8250 compatibles to drm/msm and fix the sm8250
display nodes.
Jonathan Marek (2):
drm/msm: add compatibles for sm8150/sm8250 display
arm64: dts: qcom: sm8250: fix display nodes
.../devicetree/bindings/display/msm/dpu.txt | 4 +--
arch/arm64/boot/dts/qcom/sm8250.dtsi
quot;arm64: dts: qcom: sm8250.dtsi: add display system nodes")
Signed-off-by: Jonathan Marek
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 34
1 file changed, 9 insertions(+), 25 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi
b/arch/arm64/boot/dts/qc
Use the correct name to avoid ldo7 commands being sent to ldo6's address.
Fixes: 06369bcc15a1 ("regulator: qcom-rpmh: Add support for SM8150")
Signed-off-by: Jonathan Marek
---
drivers/regulator/qcom-rpmh-regulator.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
dma_map_sgtable() returns 0 on success, which is the opposite of what this
code was doing.
Fixes: 7cd7edb89437 ("misc: fastrpc: fix common struct sg_table related issues")
Signed-off-by: Jonathan Marek
---
drivers/misc/fastrpc.c | 7 ---
1 file changed, 4 insertions(+), 3 deletion
The cleanup patch broke a6xx_gmu_clear_oob, fix it by adding the missing
bitshift operation.
Fixes: 555c50a4a19b ("drm/msm: Clean up GMU OOB set/clear handling")
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletio
Fix an error introduced resolving conflicts with camnoc_virt node.
Fixes: 0c9dde0d2015 ("arm64: dts: qcom: sm8150: Add secondary USB and PHY
nodes")
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git
Use tabs instead of 6 spaces.
Signed-off-by: Jonathan Marek
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 34 ++--
1 file changed, 17 insertions(+), 17 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi
b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 468ba1d18751
The top-level node doesn't provide any clocks, the subnode provides a
single clock with of_clk_hw_simple_get.
Signed-off-by: Jonathan Marek
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 1 -
arch/arm64/boot/dts/qcom/sdm845.dtsi | 4 ++--
arch/arm64/boot/dts/qcom/sm8150.dtsi | 4 ++--
arch/arm64
The uart2 node has been renamed, apply the change to sm8250-hdk dts too so
that serial output works.
Fixes: 91ed0e90fc49 ("arm64: dts: qcom: add sm8250 hdk dts")
Signed-off-by: Jonathan Marek
---
arch/arm64/boot/dts/qcom/sm8250-hdk.dts | 4 ++--
1 file changed, 2 insertions(+), 2
On 11/16/20 12:50 PM, Rob Clark wrote:
On Mon, Nov 16, 2020 at 9:33 AM Christoph Hellwig wrote:
On Sat, Nov 14, 2020 at 03:07:20PM -0500, Jonathan Marek wrote:
qcom's vulkan driver has nonCoherentAtomSize=1, and it looks like
dma_sync_single_for_cpu() does deal in some way with the partial
On 11/14/20 2:39 PM, Rob Clark wrote:
On Sat, Nov 14, 2020 at 10:58 AM Jonathan Marek wrote:
On 11/14/20 1:46 PM, Rob Clark wrote:
On Sat, Nov 14, 2020 at 8:24 AM Christoph Hellwig wrote:
On Sat, Nov 14, 2020 at 10:17:12AM -0500, Jonathan Marek wrote:
+void msm_gem_sync_cache(struct
On 11/14/20 1:46 PM, Rob Clark wrote:
On Sat, Nov 14, 2020 at 8:24 AM Christoph Hellwig wrote:
On Sat, Nov 14, 2020 at 10:17:12AM -0500, Jonathan Marek wrote:
+void msm_gem_sync_cache(struct drm_gem_object *obj, uint32_t flags,
+ size_t range_start, size_t range_end
This makes it possible to use the non-coherent cached MSM_BO_CACHED mode,
which otherwise doesn't provide any method for cleaning/invalidating the
cache to sync with the device.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/msm_drv.c | 21 +
drivers/gpu/drm/msm
Always use direct dma ops and no swiotlb.
Note: arm-smmu-qcom already avoids creating iommu dma ops, but not
everything uses arm-smmu-qcom and this also sets the dma mask.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/Kconfig | 1 +
drivers/gpu/drm/msm/msm_drv.c | 8 +---
2 files
Add a function to force direct ops and disable swiotlb for a deivce.
Signed-off-by: Jonathan Marek
---
include/linux/dma-direct.h | 9 +
kernel/dma/direct.c| 23 +++
2 files changed, 32 insertions(+)
diff --git a/include/linux/dma-direct.h b/include/linux
Increase the minor version to indicate the presence of new features.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/msm_drv.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 3f17acdf6594
Add a new cache mode for creating coherent host-cached BOs.
Signed-off-by: Jonathan Marek
Reviewed-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 1 +
drivers/gpu/drm/msm/msm_drv.h | 1 +
drivers/gpu/drm/msm/msm_gem.c | 8
include/uapi/drm
.
Jonathan Marek (5):
drm/msm: add MSM_BO_CACHED_COHERENT
dma-direct: add dma_direct_bypass() to force direct ops
drm/msm: call dma_direct_bypass()
drm/msm: add DRM_MSM_GEM_SYNC_CACHE for non-coherent cache maintenance
drm/msm: bump up the uapi version
drivers/gpu/drm/msm/Kconfig
Increase the minor version to indicate the presence of new features.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/msm_drv.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 3f17acdf6594
Add a new cache mode for creating coherent host-cached BOs.
Signed-off-by: Jonathan Marek
Reviewed-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 1 +
drivers/gpu/drm/msm/msm_drv.h | 1 +
drivers/gpu/drm/msm/msm_gem.c | 8
include/uapi/drm
Always use direct dma ops and no swiotlb.
Note: arm-smmu-qcom already avoids creating iommu dma ops, but not
everything uses arm-smmu-qcom and this also sets the dma mask.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/Kconfig | 1 +
drivers/gpu/drm/msm/msm_drv.c | 8 +---
2 files
with for the dma_ops_bypass part,
this is what I came up with reading the emails.
Jonathan Marek (5):
drm/msm: add MSM_BO_CACHED_COHERENT
dma-direct: add dma_direct_bypass() to force direct ops
drm/msm: call dma_direct_bypass()
drm/msm: add DRM_MSM_GEM_SYNC_CACHE for non-coherent cache maintenance
drm
Add a function to force direct ops and disable swiotlb for a deivce.
Signed-off-by: Jonathan Marek
---
include/linux/dma-direct.h | 9 +
kernel/dma/direct.c| 23 +++
2 files changed, 32 insertions(+)
diff --git a/include/linux/dma-direct.h b/include/linux
This makes it possible to use the non-coherent cached MSM_BO_CACHED mode,
which otherwise doesn't provide any method for cleaning/invalidating the
cache to sync with the device.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/msm_drv.c | 21 +
drivers/gpu/drm/msm
On 10/6/20 3:23 AM, Christoph Hellwig wrote:
On Mon, Oct 05, 2020 at 10:35:43AM -0400, Jonathan Marek wrote:
The cache synchronization doesn't have anything to do with IOMMU (for
example: cache synchronization would be useful in cases where drm/msm
doesn't use IOMMU).
It has to do with doing
On 10/5/20 4:29 AM, Christoph Hellwig wrote:
On Fri, Oct 02, 2020 at 08:46:35AM -0400, Jonathan Marek wrote:
+void msm_gem_sync_cache(struct drm_gem_object *obj, uint32_t flags,
+ size_t range_start, size_t range_end)
+{
+ struct msm_gem_object *msm_obj = to_msm_bo(obj
On 10/2/20 3:53 AM, Christoph Hellwig wrote:
@@ -8,6 +8,7 @@
#include
#include
#include
+#include
NAK, dma-noncoherent.h is not for driver use. And will in fact go
away in 5.10.
Not actually used, so can be removed.
#include
@@ -808,6 +809,20 @@ int
This makes it possible to use the non-coherent cached MSM_BO_CACHED mode,
which otherwise doesn't provide any method for cleaning/invalidating the
cache to sync with the device.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/msm_drv.c | 21 +
drivers/gpu/drm/msm
This is to support cached and cached-coherent memory types in vulkan.
I made a corresponding WIP merge request [1] which shows usage of this.
[1] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6949
Jonathan Marek (3):
drm/msm: add MSM_BO_CACHED_COHERENT
drm/msm: add
Add a new cache mode for creating coherent host-cached BOs.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 1 +
drivers/gpu/drm/msm/msm_drv.h | 1 +
drivers/gpu/drm/msm/msm_gem.c | 8
include/uapi/drm/msm_drm.h
Increase the minor version to indicate the presence of new features.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/msm_drv.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 305db1db1064
On 9/24/20 2:16 AM, Stephen Boyd wrote:
Quoting Jonathan Marek (2020-09-23 09:10:04)
On 9/22/20 3:00 PM, Stephen Boyd wrote:
Quoting Jonathan Marek (2020-09-11 08:34:07)
diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c
new file mode 100644
index
Add support for the display clock controller found on SM8150 and SM8250.
Signed-off-by: Jonathan Marek
Tested-by: Dmitry Baryshkov (SM8250)
---
drivers/clk/qcom/Kconfig |9 +
drivers/clk/qcom/Makefile|1 +
drivers/clk/qcom/dispcc-sm8250.c | 1107
ining yaml with sdm845/sc7180 dispcc
- Combined drivers into one (sm8250 driver + patched pll config for sm8150)
- Dropped uses of CLK_GET_RATE_NOCACHE (which was copied from downstream)
- Dropped CLK_SET_RATE_PARENT from some DP clocks (upstream phy design)
Jonathan Marek (2):
dt-bindings: clock: add Q
Add device tree bindings for display clock controller for
Qualcomm Technology Inc's SM8150 and SM8250 SoCs.
Signed-off-by: Jonathan Marek
Tested-by: Dmitry Baryshkov (SM8250)
---
.../bindings/clock/qcom,dispcc-sm8x50.yaml| 93 +++
.../dt-bindings/clock/qcom,dispcc-sm8150.h
On 9/23/20 7:30 PM, Stephen Boyd wrote:
Quoting Jonathan Marek (2020-09-23 09:07:16)
On 9/22/20 2:46 PM, Stephen Boyd wrote:
Quoting Jonathan Marek (2020-09-03 20:09:54)
+ .ops = _branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch
On 9/22/20 3:04 PM, Stephen Boyd wrote:
Quoting Jonathan Marek (2020-09-11 08:34:06)
Add support for the display clock controller found on SM8150
based devices. This would allow display drivers to probe and
control their clocks.
Signed-off-by: Jonathan Marek
---
drivers/clk/qcom/Kconfig
On 9/22/20 3:00 PM, Stephen Boyd wrote:
Quoting Jonathan Marek (2020-09-11 08:34:07)
diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c
new file mode 100644
index ..7c0f384a3a42
--- /dev/null
+++ b/drivers/clk/qcom/dispcc-sm8250.c
@@ -0,0 +1,1100
On 9/22/20 2:46 PM, Stephen Boyd wrote:
Quoting Jonathan Marek (2020-09-03 20:09:54)
Add support for the video clock controller found on SM8250 based devices.
Derived from the downstream driver.
Signed-off-by: Jonathan Marek
---
drivers/clk/qcom/Kconfig | 9 +
drivers/clk/qcom
Add device tree bindings for video clock controller for SM8250 SoCs.
Signed-off-by: Jonathan Marek
Reviewed-by: Rob Herring
---
.../bindings/clock/qcom,videocc.yaml | 4 ++-
.../dt-bindings/clock/qcom,videocc-sm8250.h | 34 +++
2 files changed, 37 insertions(+), 1
Add support for the video clock controller found on SM8150 based devices.
Derived from the downstream driver.
Signed-off-by: Jonathan Marek
---
drivers/clk/qcom/Kconfig | 9 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/videocc-sm8150.c | 276
Add support for the video clock controller found on SM8250 based devices.
Derived from the downstream driver.
Signed-off-by: Jonathan Marek
---
drivers/clk/qcom/Kconfig | 9 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/videocc-sm8250.c | 369
clocks (hardware controlled and always on)
Jonathan Marek (5):
dt-bindings: clock: combine qcom,sdm845-videocc and
qcom,sc7180-videocc
dt-bindings: clock: add SM8150 QCOM video clock bindings
dt-bindings: clock: add SM8250 QCOM video clock bindings
clk: qcom: add video clock controller
Add device tree bindings for video clock controller for SM8150 SoCs.
Signed-off-by: Jonathan Marek
Reviewed-by: Rob Herring
---
.../bindings/clock/qcom,videocc.yaml | 4 ++-
.../dt-bindings/clock/qcom,videocc-sm8150.h | 25 +++
2 files changed, 28 insertions(+), 1
These two bindings are almost identical, so combine them into one. This
will make it easier to add the sm8150 and sm8250 videocc bindings.
Signed-off-by: Jonathan Marek
Reviewed-by: Rob Herring
---
.../bindings/clock/qcom,sc7180-videocc.yaml | 65 ---
...,sdm845-videocc.yaml
ad of time to correctly set the
hw_apriv flag so that it can be used by msm_gpu to properly setup
global buffers.
Fixes: 604234f33658 ("drm/msm: Enable expanded apriv support for a650")
Signed-off-by: Jordan Crouse
Tested-by: Jonathan Marek
---
drivers/gpu/drm/msm/ad
On 9/14/20 7:57 PM, Stephen Boyd wrote:
Quoting Dmitry Baryshkov (2020-09-07 07:25:45)
On 04/09/2020 01:26, Jonathan Marek wrote:
Add display clock drivers required to get DSI and DP displays working on
SM8150 and SM8250 SoCs.
Derived from downstream drivers. Notable changes compared
The clk_pre/clk_post values in shared_timings are used instead, and these
are unused.
Signed-off-by: Jonathan Marek
Tested-by: Dmitry Baryshkov (SM8250)
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
b
Note I haven't tested SM8150 recently, but DSI is almost identical to SM8250.
v2:
- added workaround for 5GHz max_rate overflowing in 32-bit builds
(based on robclark's suggestion)
- Updated Kconfig option to mention SM8250 and not just SM8150
Jonathan Marek (3):
drm/msm/dsi: remove
This adds support for the 7nm ("V4") DSI PHY/PLL for sm8150 and sm8250.
Implementation is based on 10nm driver, but updated based on the downstream
7nm driver.
Signed-off-by: Jonathan Marek
Tested-by: Dmitry Baryshkov (SM8250)
---
.../devicetree/bindings/display/msm/dsi.t
This allows DSI driver to work with sm8150 and sm8250. The sdm845 config
is re-used as the config is the same.
Signed-off-by: Jonathan Marek
Tested-by: Dmitry Baryshkov (SM8250)
---
drivers/gpu/drm/msm/dsi/dsi_cfg.c | 5 -
drivers/gpu/drm/msm/dsi/dsi_cfg.h | 2 ++
2 files changed, 6
This makes it easier to combine dt bindings for sdm845/sc7180 dispcc.
Note: nothing upstream provides these clocks and the sdm845 dispcc driver
hasn't switched to using .fw_name for these clocks (these properties are
ignored), so changing this shouldn't be a problem.
Signed-off-by: Jonathan
This makes it easier to combine dt bindings for sdm845/sc7180 dispcc.
Note: nothing upstream provides these clocks and the sdm845 dispcc driver
hasn't switched to using .fw_name for these clocks (these properties are
ignored), so changing this shouldn't be a problem.
Signed-off-by: Jonathan
Add device tree bindings for display clock controller for
Qualcomm Technology Inc's SM8250 SoCs.
Signed-off-by: Jonathan Marek
---
.../bindings/clock/qcom,dispcc.yaml | 4 +-
.../dt-bindings/clock/qcom,dispcc-sm8250.h| 66 +++
2 files changed, 69 insertions(+), 1
Add device tree bindings for display clock controller for
Qualcomm Technology Inc's SM8150 SoCs.
Signed-off-by: Jonathan Marek
---
.../bindings/clock/qcom,dispcc.yaml | 10 +--
.../dt-bindings/clock/qcom,dispcc-sm8150.h| 69 +++
2 files changed, 75 insertions(+), 4
Add support for the display clock controller found on SM8250
based devices. This would allow display drivers to probe and
control their clocks.
Signed-off-by: Jonathan Marek
Tested-by: Dmitry Baryshkov
---
drivers/clk/qcom/Kconfig |9 +
drivers/clk/qcom/Makefile|1
Add support for the display clock controller found on SM8150
based devices. This would allow display drivers to probe and
control their clocks.
Signed-off-by: Jonathan Marek
---
drivers/clk/qcom/Kconfig |9 +
drivers/clk/qcom/Makefile|1 +
drivers/clk/qcom/dispcc-sm8150
These two bindings are almost identical, so combine them into one. This
will make it easier to add the sm8150 and sm8250 dispcc bindings.
Signed-off-by: Jonathan Marek
---
...om,sdm845-dispcc.yaml => qcom,dispcc.yaml} | 18 ++--
.../bindings/clock/qcom,sc7180-dispcc.yaml|
v2:
- updated dts example to reflect the change (first patch)
- updated config_ctl_hi1_val in sm8250 dispcc to latest downstream
v3:
- combined dt-binding: "gcc_disp_gpll0_clk_src" is needed by sc7180 too
- use the right order in drivers/clk/qcom/Kconfig
Jonathan Marek (7):
dt-bindi
Define SENSORS_PD for the next patch, to void using magic values for these.
Signed-off-by: Jonathan Marek
---
drivers/misc/fastrpc.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/misc/fastrpc.c b/drivers/misc/fastrpc.c
index 7939c55daceb..07b381c042cd
Initializing sensors requires attaching to pd 2. Add an ioctl for that.
This corresponds to FASTRPC_INIT_ATTACH_SENSORS in the downstream driver.
v2:
- define names of PD values in a separate patch
- split out identation fix in a separate patch
Jonathan Marek (3):
misc: fastrpc: fix
Use tabs instead of spaces.
Fixes: 2419e55e532d ("misc: fastrpc: add mmap/unmap support")
Signed-off-by: Jonathan Marek
---
include/uapi/misc/fastrpc.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/uapi/misc/fastrpc.h b/include/uapi/misc/fastr
On 9/8/20 9:56 AM, Pierre-Louis Bossart wrote:
@@ -764,8 +786,11 @@ static int qcom_swrm_probe(struct platform_device
*pdev)
if (!ctrl->regmap)
return -EINVAL;
} else {
- /* Only WCD based SoundWire controller is supported */
- return
Add fastrpc nodes for sDSP, cDSP, and aDSP.
Signed-off-by: Jonathan Marek
---
v2: rebase without audio dts nodes, changed "dsps" to "sdsp"
arch/arm64/boot/dts/qcom/sm8250.dtsi | 115 ++-
1 file changed, 113 insertions(+), 2 deletions(-)
diff --git a
Fix slimbus case being broken thanks to a typo.
Fixes: 5bd773242f75 ("soundwire: qcom: avoid dependency on CONFIG_SLIMBUS")
Signed-off-by: Jonathan Marek
---
This should be squashed into the problematic patch if possible,
but I'm not sure if that's possible since its already in
Initializing sensors requires attaching to pd 2. Add an ioctl for that.
This corresponds to FASTRPC_INIT_ATTACH_SENSORS in the downstream driver.
Signed-off-by: Jonathan Marek
---
drivers/misc/fastrpc.c | 9 ++---
include/uapi/misc/fastrpc.h | 1 +
2 files changed, 7 insertions(+), 3
On 9/7/20 8:33 AM, Greg Kroah-Hartman wrote:
On Mon, Aug 31, 2020 at 08:32:59PM -0400, Jonathan Marek wrote:
Initializing sensors requires attaching to pd 2. Add an ioctl for that.
This corresponds to FASTRPC_INIT_ATTACH_SENSORS in the downstream driver.
Signed-off-by: Jonathan Marek
On 9/7/20 9:58 AM, Srinivas Kandagatla wrote:
On 07/09/2020 14:51, Jonathan Marek wrote:
@@ -1477,7 +1477,10 @@ static long fastrpc_device_ioctl(struct file
*file, unsigned int cmd,
err = fastrpc_invoke(fl, argp);
break;
case FASTRPC_IOCTL_INIT_ATTACH:
- err
On 9/7/20 10:01 AM, Srinivas Kandagatla wrote:
On 07/09/2020 14:47, Jonathan Marek wrote:
On 9/7/20 8:36 AM, Srinivas Kandagatla wrote:
On 01/09/2020 01:32, Jonathan Marek wrote:
-#define FASTRPC_IOCTL_MMAP _IOWR('R', 6, struct
fastrpc_req_mmap)
-#define FASTRPC_IOCTL_MUNMAP
On 9/7/20 8:36 AM, Srinivas Kandagatla wrote:
On 01/09/2020 01:32, Jonathan Marek wrote:
-#define FASTRPC_IOCTL_MMAP _IOWR('R', 6, struct
fastrpc_req_mmap)
-#define FASTRPC_IOCTL_MUNMAP _IOWR('R', 7, struct
fastrpc_req_munmap)
+#define FASTRPC_IOCTL_MMAP _IOWR
The function name qcom_swrm_abh_reg_read should say ahb, fix that.
Signed-off-by: Jonathan Marek
Reviewed-by: Srinivas Kandagatla
---
drivers/soundwire/qcom.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/soundwire/qcom.c b/drivers/soundwire/qcom.c
index
eam driver doesn't define this bit, so I can't implement it.
Soundwire works without it and It shouldn't be difficult to implement later.
Jonathan Marek (4):
soundwire: qcom: fix abh/ahb typo
soundwire: qcom: avoid dependency on CONFIG_SLIMBUS
soundwire: qcom: add support for mmio soundwire mast
Add a compatible string for HW version v1.5.1 on sm8250 SoCs.
Signed-off-by: Jonathan Marek
---
Documentation/devicetree/bindings/soundwire/qcom,sdw.txt | 1 +
drivers/soundwire/qcom.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/Documentation/devicetree
The driver may be used without slimbus, so don't depend on slimbus.
Signed-off-by: Jonathan Marek
---
drivers/soundwire/Kconfig | 2 +-
drivers/soundwire/qcom.c | 4
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/soundwire/Kconfig b/drivers/soundwire/Kconfig
index
Adds support for qcom soundwire devices with memory mapped IO registers.
Signed-off-by: Jonathan Marek
---
drivers/soundwire/qcom.c | 29 +++--
1 file changed, 27 insertions(+), 2 deletions(-)
diff --git a/drivers/soundwire/qcom.c b/drivers/soundwire/qcom.c
index
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