Re: unknown NMI on AMD Rome

On 3/16/21 2:53 PM, Peter Zijlstra wrote: > On Tue, Mar 16, 2021 at 04:45:02PM +0100, Jiri Olsa wrote: >> hi, >> when running 'perf top' on AMD Rome (/proc/cpuinfo below) >> with fedora 33 kernel 5.10.22-200.fc33.x86_64 >> >> we got unknown NMI messages: >> >> [ 226.700160] Uhhuh. NMI received for

[PATCH v2 2/4] powercap/intel_rapl_msr: Convert rapl_msr_priv into pointer

From: Victor Ding This patch changes the static struct rapl_msr_priv to a pointer to allow using a different set of of RAPL MSR interface, preparing for supporting AMD's RAPL MSR interface. No functional changes. Signed-off-by: Victor Ding Acked-by: Kim Phillips Cc: Victor Din

[PATCH v2 0/4] powercap: Enable RAPL for AMD Fam17h and Fam19h

ML Cc: linux...@vger.kernel.org Cc: x...@kernel.org Kim Phillips (1): powercap: Add AMD Fam19h RAPL support Victor Ding (3): x86/msr-index: sort AMD RAPL MSRs by address powercap/intel_rapl_msr: Convert rapl_msr_priv into pointer powercap: Add AMD Fam17h RAPL support arch/x86/include/asm/msr

[PATCH v2 3/4] powercap: Add AMD Fam17h RAPL support

/dev/cpu/[x]/msr: /sys/class/powercap/intel-rapl/intel-rapl:0/energy_uj /sys/class/powercap/intel-rapl/intel-rapl:0/intel-rapl:0:0/energy_uj Signed-off-by: Victor Ding Acked-by: Kim Phillips Cc: Victor Ding Cc: Alexander Shishkin Cc: Borislav Petkov Cc: Daniel Lezcano Cc: "H. Peter

[PATCH v2 4/4] powercap: Add AMD Fam19h RAPL support

AMD Family 19h's RAPL MSRs are identical to Family 17h's. Extend Family 17h's support to Family 19h. Signed-off-by: Kim Phillips Cc: Victor Ding Cc: Alexander Shishkin Cc: Borislav Petkov Cc: Daniel Lezcano Cc: "H. Peter Anvin" Cc: Ingo Molnar Cc: Josh Poimb

[PATCH v2 1/4] x86/msr-index: sort AMD RAPL MSRs by address

From: Victor Ding MSRs in the rest of this file are sorted by their addresses; fixing the two outliers. No functional changes. Signed-off-by: Victor Ding Acked-by: Kim Phillips Cc: Victor Ding Cc: Alexander Shishkin Cc: Borislav Petkov Cc: Daniel Lezcano Cc: "H. Peter Anvin"

Re: [PATCH] perf/x86/intel: Fix n_metric for the canceled group

kernel will probably fail to add new Topdown events. >>> >>> Check if the canceled group has Topdown events. If so, subtract the >>> TopDown events from n_metric accordingly. >>> >>> Fixes: 7b2c05a15d29 ("perf/x86/intel: Generic support for hardware

Re: [PATCH] rcu,ftrace: Fix ftrace recursion

e not being a helpful > comment. > > Reinstate the notrace and add a comment to avoid loosing it again. > > Fixes: ff5c4f5cad33 ("rcu/tree: Mark the idle relevant functions noinstr") > Reported-by: Kim Phillips > Signed-off-by: Peter Zijlstra (Intel) > --- Tested-by: Kim Phillips Thanks, Kim

Re: [tip: core/rcu] rcu/tree: Mark the idle relevant functions noinstr

Hi, On 5/19/20 2:52 PM, tip-bot2 for Thomas Gleixner wrote: > The following commit has been merged into the core/rcu branch of tip: > > Commit-ID: ff5c4f5cad33061b07c3fb9187506783c0f3cb66 > Gitweb: > https://git.kernel.org/tip/ff5c4f5cad33061b07c3fb9187506783c0f3cb66 > Author:

[tip: perf/core] perf/amd/uncore: Inform the user how many counters each uncore PMU has

The following commit has been merged into the perf/core branch of tip: Commit-ID: 9ed9647dc0671486f9e998b7258f75167a9c4697 Gitweb: https://git.kernel.org/tip/9ed9647dc0671486f9e998b7258f75167a9c4697 Author:Kim Phillips AuthorDate:Mon, 21 Sep 2020 09:43:30 -05:00 Committer

[tip: perf/core] perf/amd/uncore: Allow F19h user coreid, threadmask, and sliceid specification

The following commit has been merged into the perf/core branch of tip: Commit-ID: 87a54a1fd525f2af8d82becf583c7e836918cf22 Gitweb: https://git.kernel.org/tip/87a54a1fd525f2af8d82becf583c7e836918cf22 Author:Kim Phillips AuthorDate:Mon, 21 Sep 2020 09:43:29 -05:00 Committer

[tip: perf/core] perf/amd/uncore: Allow F17h user threadmask and slicemask specification

The following commit has been merged into the perf/core branch of tip: Commit-ID: 8170f386f19ca7120393c957d4bfbdc07f964ab6 Gitweb: https://git.kernel.org/tip/8170f386f19ca7120393c957d4bfbdc07f964ab6 Author:Kim Phillips AuthorDate:Mon, 21 Sep 2020 09:43:28 -05:00 Committer

[tip: perf/core] perf/amd/uncore: Prepare to scale for more attributes that vary per family

The following commit has been merged into the perf/core branch of tip: Commit-ID: 06f2c24584f31bc16129643bfb8239a1af82a17f Gitweb: https://git.kernel.org/tip/06f2c24584f31bc16129643bfb8239a1af82a17f Author:Kim Phillips AuthorDate:Mon, 21 Sep 2020 09:43:27 -05:00 Committer

[PATCH 4/4] perf/amd/uncore: Inform the user how many counters each uncore PMU has

_uncore: AMD NB counters detected amd_uncore: AMD LLC counters detected F17h dmesg AFTER: amd_uncore: 4 amd_df counters detected amd_uncore: 6 amd_l3 counters detected Signed-off-by: Kim Phillips Cc: Alexander Shishkin Cc: Arnaldo Carvalho de Melo Cc: Borislav Petkov Cc: "H. Peter Anvin&q

[PATCH 0/4] perf/amd/uncore: Support user core/thread and slice specification

Cc: Borislav Petkov Cc: "H. Peter Anvin" Cc: Ingo Molnar Cc: Jiri Olsa Cc: Mark Rutland Cc: Michael Petlan Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Stephane Eranian Cc: Thomas Gleixner Cc: x...@kernel.org Cc: linux-kernel@vger.kernel.org Kim Phillips (4): perf/amd/unc

[PATCH 3/4] perf/amd/uncore: Allow F19h user coreid, threadmask, and sliceid specification

invocation to measure L3 accesses (event 4, umask 0xff) by the first thread (id 0 -> mask 0x1) of the first core (id 0) on the first slice (id 0): perf stat -a -e instructions,amd_l3/umask=0xff,event=0x4,coreid=0,threadmask=1,sliceid=0,enallcores=0,enallslices=0/ Signed-off-by: Kim Phillips

[PATCH 2/4] perf/amd/uncore: Allow F17h user threadmask and slicemask specification

Continue to fully populate either one of threadmask or slicemask if the user doesn't. Signed-off-by: Kim Phillips Cc: Alexander Shishkin Cc: Arnaldo Carvalho de Melo Cc: Borislav Petkov Cc: "H. Peter Anvin" Cc: Ingo Molnar Cc: Jiri Olsa Cc: Mark Rutland Cc: Michael Petla

[PATCH 1/4] perf/amd/uncore: Prepare to scale for more attributes that vary per family

_df/format/umask:config:8-15 Signed-off-by: Kim Phillips Cc: Alexander Shishkin Cc: Arnaldo Carvalho de Melo Cc: Borislav Petkov Cc: "H. Peter Anvin" Cc: Ingo Molnar Cc: Jiri Olsa Cc: Mark Rutland Cc: Michael Petlan Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Stephane Eranian Cc: Th

Re: [PATCH v2] perf vendor events amd: remove trailing commas

urns > > Acked-by: Namhyung Kim Acked-by: Kim Phillips Thanks, Kim

[tip: perf/core] perf/x86/amd/ibs: Fix raw sample data accumulation

The following commit has been merged into the perf/core branch of tip: Commit-ID: 36e1be8ada994d509538b3b1d0af8b63c351e729 Gitweb: https://git.kernel.org/tip/36e1be8ada994d509538b3b1d0af8b63c351e729 Author:Kim Phillips AuthorDate:Tue, 08 Sep 2020 16:47:38 -05:00 Committer

[tip: perf/core] perf/x86/amd/ibs: Support 27-bit extended Op/cycle counter

The following commit has been merged into the perf/core branch of tip: Commit-ID: 8b0bed7d410f48499d72af2e2bcd890daad94e0d Gitweb: https://git.kernel.org/tip/8b0bed7d410f48499d72af2e2bcd890daad94e0d Author:Kim Phillips AuthorDate:Tue, 08 Sep 2020 16:47:39 -05:00 Committer

[tip: perf/core] perf/x86/rapl: Add AMD Fam19h RAPL support

The following commit has been merged into the perf/core branch of tip: Commit-ID: a77259bdcb62a2c345914df659a1fbc421269a8b Gitweb: https://git.kernel.org/tip/a77259bdcb62a2c345914df659a1fbc421269a8b Author:Kim Phillips AuthorDate:Tue, 08 Sep 2020 16:47:40 -05:00 Committer

[tip: perf/core] perf/x86/amd/ibs: Don't include randomized bits in get_ibs_op_count()

The following commit has been merged into the perf/core branch of tip: Commit-ID: 680d69635005ba0e58fe3f4c52fc162b8fc743b0 Gitweb: https://git.kernel.org/tip/680d69635005ba0e58fe3f4c52fc162b8fc743b0 Author:Kim Phillips AuthorDate:Tue, 08 Sep 2020 16:47:37 -05:00 Committer

[tip: perf/core] arch/x86/amd/ibs: Fix re-arming IBS Fetch

The following commit has been merged into the perf/core branch of tip: Commit-ID: 221bfce5ebbdf72ff08b3bf2510ae81058ee568b Gitweb: https://git.kernel.org/tip/221bfce5ebbdf72ff08b3bf2510ae81058ee568b Author:Kim Phillips AuthorDate:Tue, 08 Sep 2020 16:47:36 -05:00 Committer

[tip: perf/core] perf/x86/amd: Fix sampling Large Increment per Cycle events

The following commit has been merged into the perf/core branch of tip: Commit-ID: 26e52558ead4b39c0e0fe7bf08f82f5a9777a412 Gitweb: https://git.kernel.org/tip/26e52558ead4b39c0e0fe7bf08f82f5a9777a412 Author:Kim Phillips AuthorDate:Tue, 08 Sep 2020 16:47:35 -05:00 Committer

[tip: perf/core] perf/amd/uncore: Set all slices and threads to restore perf stat -a behaviour

The following commit has been merged into the perf/core branch of tip: Commit-ID: c8fe99d0701fec9fb849ec880a86bc5592530496 Gitweb: https://git.kernel.org/tip/c8fe99d0701fec9fb849ec880a86bc5592530496 Author:Kim Phillips AuthorDate:Tue, 08 Sep 2020 16:47:34 -05:00 Committer

Re: [PATCH v2 3/7] arch/x86/amd/ibs: Fix re-arming IBS Fetch

On 9/10/20 3:50 AM, pet...@infradead.org wrote: > On Thu, Sep 10, 2020 at 10:32:23AM +0200, pet...@infradead.org wrote: >>> @@ -363,7 +363,14 @@ perf_ibs_event_update(struct perf_ibs *perf_ibs, >>> struct perf_event *event, >>> static inline void perf_ibs_enable_event(struct perf_ibs *perf_ibs, >

[PATCH v2 7/7] perf/x86/rapl: Add AMD Fam19h RAPL support

Family 19h RAPL support did not change from Family 17h; extend the existing Fam17h support to work on Family 19h too. Signed-off-by: Kim Phillips Cc: Stephane Eranian Cc: Peter Zijlstra Cc: Ingo Molnar Cc: Ingo Molnar Cc: Thomas Gleixner Cc: Borislav Petkov Cc: Alexander Shishkin Cc

[PATCH v2 6/7] perf/x86/amd/ibs: Support 27-bit extended Op/cycle counter

period is over 1,048,560 (0x0), which would previously activate the driver's software counter. That threshold is now 134,217,712 (0x7f0). Signed-off-by: Kim Phillips Cc: Stephane Eranian Cc: Peter Zijlstra Cc: Ingo Molnar Cc: Ingo Molnar Cc: Thomas Gleixner Cc: Borislav Petko

[PATCH v2 5/7] perf/x86/amd/ibs: Fix raw sample data accumulation

don't see any perf driver version information being included in perf.data file headers, but, existing users can detect whether the size of the sample record has reduced by 8 bytes to determine whether the IBS driver has this fix. Reported-by: Stephane Eranian Signed-off-by: Kim Phill

[PATCH v2 4/7] perf/x86/amd/ibs: Don't include randomized bits in get_ibs_op_count()

domized by hardware. Don't include those bits in the driver's event count. Signed-off-by: Kim Phillips Fixes: 8b1e13638d46 ("perf/x86-ibs: Fix usage of IBS op current count") Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 Cc: Stephane Eranian Cc: Peter Zijlstra Cc: In

[PATCH v2 3/7] arch/x86/amd/ibs: Fix re-arming IBS Fetch

al counter to 0 and IBS Fetch starts counting again. A family 15h machine tested does not have this problem, and the extra wrmsr is also not needed on Family 19h, so only do the extra wrmsr on families 16h through 18h. Reported-by: Stephane Eranian Signed-off-by: Kim Phillips Link: https://bugz

[PATCH v2 2/7] perf/x86/amd: Fix sampling Large Increment per Cycle events

it value to the even counter. Reading the even counter of the merged counter pair returns the full 64-bit value." Fixes: 5738891229a2 ("perf/x86/amd: Add support for Large Increment per Cycle Events") Signed-off-by: Kim Phillips Link: https://bugzilla.kernel.org/show_bug.cgi?id=206

[PATCH v2 1/7] perf/amd/uncore: Set all slices and threads to restore perf stat -a behaviour

. CPU36354,891 l3_request_g1.caching_l3_cache_accesses CPU40 1,780,870 l3_request_g1.caching_l3_cache_accesses CPU44315,062 l3_request_g1.caching_l3_cache_accesses ... Signed-off-by: Kim Phillips Fixes: 2f217d58a8a0 ("perf/x86/amd/unco

[PATCH v2 0/7] perf/x86/amd: Miscellaneous updates

o Molnar Cc: Thomas Gleixner Cc: Borislav Petkov Cc: Alexander Shishkin Cc: Arnaldo Carvalho de Melo Cc: "H. Peter Anvin" Cc: Jiri Olsa Cc: Mark Rutland Cc: Michael Petlan Cc: Namhyung Kim Cc: LKML Cc: x86 Kim Phillips (7): perf/amd/uncore: Set all slices and threads to rest

Re: [PATCH 3/4] perf vendor events amd: Add recommended events

On 9/3/20 1:19 AM, Ian Rogers wrote: > On Tue, Sep 1, 2020 at 3:10 PM Kim Phillips wrote: >> The nps1_die_to_dram event may need perf stat's --metric-no-group >> switch if the number of available data fabric counters is less >> than the number it uses (8). >

[PATCH 4/4] perf vendor events amd: Enable Family 19h users by matching Zen2 events

This enables zen3 users by reusing mostly-compatible zen2 events until the official public list of zen3 events is published in a future PPR. Signed-off-by: Kim Phillips Cc: Peter Zijlstra Cc: Ingo Molnar Cc: Arnaldo Carvalho de Melo Cc: Mark Rutland Cc: Alexander Shishkin Cc: Jiri Olsa Cc

[PATCH 3/4] perf vendor events amd: Add recommended events

The nps1_die_to_dram event may need perf stat's --metric-no-group switch if the number of available data fabric counters is less than the number it uses (8). Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 Signed-off-by: Kim Phillips Cc: Peter Zijlstra Cc: Ingo Molnar Cc: Arnaldo C

[PATCH 1/4] perf vendor events amd: Add L2 Prefetch events for zen1

e.g., are included in this 2019 version of the PPR: Processor Programming Reference (PPR) for AMD Family 17h Model 18h, Revision B1 Processors Rev. 3.14 - Sep 26, 2019 Signed-off-by: Kim Phillips Fixes: 98c07a8f74f8 ("perf vendor events amd: perf PMU events for AMD Family 17h") L

[PATCH 2/4] perf vendor events amd: Add ITLB Instruction Fetch Hits event for zen1

pu/event=0x94/u 211,318 cpu/event=0x94,umask=0xff/u Rome/zen2: zen2$ perf stat -e cpu/event=0x94/,cpu/event=0x94,umask=0xff/ sleep 1 Performance counter stats for 'sleep 1': 0 cpu/event=0x94/u 190,744 cpu/event=0x94,umask=0xff/u Signed

[PATCH] perf record/stat: Explicitly call out event modifiers in the documentation

Event modifiers are not mentioned in the perf record or perf stat manpages. Add them to orient new users more effectively by pointing them to the perf list manpage for details. Signed-off-by: Kim Phillips Fixes: 2055fdaf8703 ("perf list: Document precise event sampling for AMD IBS")

[PATCH] tools/power turbostat: Support AMD Family 19h

at the bottom of the page at amd.com->processors->servers->epyc->2nd-gen-epyc, i.e., the EPYC 7H12. Signed-off-by: Kim Phillips Cc: Len Brown Cc: Len Brown Cc: linux...@vger.kernel.org Cc: linux-kernel@vger.kernel.org --- tools/power/x86/turbostat/turb

[PATCH] powercap: Add AMD Fam19h RAPL support

AMD Family 19h's RAPL MSRs are identical to Family 17h's. Extend Family 17h's support to Family 19h. Signed-off-by: Kim Phillips Cc: "Rafael J. Wysocki" Cc: Victor Ding Cc: LKML Cc: linux...@vger.kernel.org Cc: x...@kernel.org --- Depends on Victor Ding's

Re: [PATCH 3/3] powercap: Add AMD Fam17h RAPL support

lues directly read from corresponding MSRs via /dev/cpu/[x]/msr: > /sys/class/powercap/intel-rapl/intel-rapl:0/energy_uj > /sys/class/powercap/intel-rapl/intel-rapl:0/intel-rapl:0:0/energy_uj > > Signed-off-by: Victor Ding > --- For the series: Acked-by: Kim Phillips Thanks, Kim

[PATCH 7/7] perf/x86/rapl: Add AMD Fam19h RAPL support

Family 19h RAPL support did not change from Family 17h; extend the existing Fam17h support to work on Family 19h too. Signed-off-by: Kim Phillips Cc: Stephane Eranian Cc: Peter Zijlstra Cc: Ingo Molnar Cc: Ingo Molnar Cc: Thomas Gleixner Cc: Borislav Petkov Cc: Alexander Shishkin Cc

[PATCH 6/7] perf/x86/amd/ibs: Support 27-bit extended Op/cycle counter

period is over 1,048,560 (0x0), which would previously activate the driver's software counter. That threshold is now 134,217,712 (0x7f0). Signed-off-by: Kim Phillips Cc: Stephane Eranian Cc: Peter Zijlstra Cc: Ingo Molnar Cc: Ingo Molnar Cc: Thomas Gleixner Cc: Borislav Petko

[PATCH 3/7] arch/x86/amd/ibs: Fix re-arming IBS Fetch

al counter to 0 and IBS Fetch starts counting again. It is not clear what versions of IBS hardware need IbsFetchEn explicitly zeroed and which historically may not have, so now make the driver always do it. Reported-by: Stephane Eranian Signed-off-by: Kim Phillips Link: https://bugzilla.kernel.o

[PATCH 2/7] perf/x86/amd: Fix sampling Large Increment per Cycle events

it value to the even counter. Reading the even counter of the merged counter pair returns the full 64-bit value." Fixes: 5738891229a2 ("perf/x86/amd: Add support for Large Increment per Cycle Events") Signed-off-by: Kim Phillips Link: https://bugzilla.kernel.org/show_bug.cgi?id=206

[PATCH 4/7] perf/x86/amd/ibs: Don't include randomized bits in get_ibs_op_count()

domized by hardware. Don't include those bits in the driver's event count. Signed-off-by: Kim Phillips Fixes: 8b1e13638d46 ("perf/x86-ibs: Fix usage of IBS op current count") Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 Cc: Stephane Eranian Cc: Peter Zijlstra Cc: In

[PATCH 5/7] perf/x86/amd/ibs: Fix raw sample data accumulation

#x27;t see any perf driver version information being included in perf.data file headers, but, existing users can detect whether the size of the sample record has reduced by 8 bytes to determine whether the IBS driver has this fix. Reported-by: Stephane Eranian Signed-off-by: Kim Phillips Fixes: 90

[PATCH 1/7 RESEND] perf/amd/uncore: Set all slices and threads to restore perf stat -a behaviour

. CPU36354,891 l3_request_g1.caching_l3_cache_accesses CPU40 1,780,870 l3_request_g1.caching_l3_cache_accesses CPU44315,062 l3_request_g1.caching_l3_cache_accesses ... Reported-by: Stephane Eranian Signed-off-by: Kim Phillips Fixes: 2f21

Re: [PATCH 13/13] cpufreq: amd_freq_sensitivity: Remove unused ID structs

On 7/14/20 4:02 PM, Lee Jones wrote: > On Tue, 14 Jul 2020, Kim Phillips wrote: >> On 7/14/20 9:50 AM, Lee Jones wrote: >>> Can't see them being used anywhere and the compiler doesn't complain >>> that they're missing, so ... >>>

Re: [PATCH 13/13] cpufreq: amd_freq_sensitivity: Remove unused ID structs

On 7/14/20 9:50 AM, Lee Jones wrote: > Can't see them being used anywhere and the compiler doesn't complain > that they're missing, so ... > > Fixes the following W=1 kernel build warning(s): > > drivers/cpufreq/amd_freq_sensitivity.c:147:32: warning: > ‘amd_freq_sensitivity_ids’ defined but no

Re: [PATCH] perf/x86/rapl: fix rapl config variable bug

phane Eranian > > --- Tested-by: Kim Phillips Thanks, Kim

[tip: x86/cpu] x86/cpu/amd: Make erratum #1054 a legacy erratum

The following commit has been merged into the x86/cpu branch of tip: Commit-ID: e2abfc0448a46d8a137505aa180caf14070ec535 Gitweb: https://git.kernel.org/tip/e2abfc0448a46d8a137505aa180caf14070ec535 Author:Kim Phillips AuthorDate:Fri, 17 Apr 2020 09:33:56 -05:00 Committer

[tip: x86/cpu] x86/cpu/amd: Make erratum #1054 a legacy erratum

The following commit has been merged into the x86/cpu branch of tip: Commit-ID: 3e2c1fd2022ccce96b6a05a6ab519d65769ee320 Gitweb: https://git.kernel.org/tip/3e2c1fd2022ccce96b6a05a6ab519d65769ee320 Author:Kim Phillips AuthorDate:Fri, 17 Apr 2020 09:33:56 -05:00 Committer

[PATCH 2/2] perf/x86/amd/ibs: handle erratum #420 only on the affected CPU family (10h)

count mask for IBS Op implementations that have read & writeable current count (CurCnt) fields in addition to the MaxCnt field. These bits were reserved on prior implementations, and therefore shouldn't have negative impact. Signed-off-by: Kim Phillips Fixes: c9574fe0bdb9 ("perf/x86-

[PATCH 1/2] perf/x86/amd/ibs: Fix reading of the IBS OpData register and thus precise RIP validity

memory. Signed-off-by: Kim Phillips Fixes: d47e8238cd76 ("perf/x86-ibs: Take instruction pointer from ibs sample") Cc: sta...@vger.kernel.org Cc: Stephane Eranian Cc: Peter Zijlstra Cc: Ingo Molnar Cc: Arnaldo Carvalho de Melo Cc: Alexander Shishkin Cc: Jiri Olsa Cc: Namhyung Kim

[PATCH 5/5] perf list: specify metrics are to be used with -M

t of 'perf list metrics' after: $ perf list metrics List of pre-defined events (to be used with -e): Metrics (to be used with -M): C2_Pkg_Residency [C2 residency percent per package] ... Signed-off-by: Kim Phillips Cc: Janakarajan Natarajan Cc: Peter Zijlstra Cc: Ingo

[PATCH 2/5] perf vendor events amd: remove redundant '['

Remove the redundant '['. perf list output before: ex_ret_brn [[Retired Branch Instructions] perf list output after: ex_ret_brn [Retired Branch Instructions] Signed-off-by: Kim Phillips Cc: Janakarajan Natarajan Cc: Peter Zijlstra Cc: Ingo Molnar Cc: Arnaldo C

[PATCH 3/5] perf vendor events: minor fixes to the README

Some grammatical fixes, and updates to some path references that have since changed. Signed-off-by: Kim Phillips Cc: Janakarajan Natarajan Cc: Peter Zijlstra Cc: Ingo Molnar Cc: Arnaldo Carvalho de Melo Cc: Alexander Shishkin Cc: Andi Kleen Cc: Jiri Olsa Cc: Namhyung Kim Cc: Borislav

[PATCH 4/5] perf list: allow plurals for metric, metricgroup

ist metrics List of pre-defined events (to be used in -e): Metrics: IPC [Instructions Per Cycle (per logical thread)] UPI [Uops Per Instruction] Signed-off-by: Kim Phillips Cc: Janakarajan Natarajan Cc: Peter Zijlstra Cc: Ingo Molnar Cc: Arnaldo Carvalho de Melo Cc: Al

[PATCH 1/5] perf vendor events amd: add L3 cache events for Family 17h

-l 100 -f default ... 7,006,831 l3_request_g1.caching_l3_cache_accesses 7,006,830 amd_l3/event=0x01,umask=0x80/ 366,530 l3_comb_clstr_state.request_miss 366,568 amd_l3/event=0x06,umask=0x01/ Signed-off-by: Kim Phillips Cc: Janakarajan Nat

[tip: perf/urgent] perf/x86/amd/ibs: Fix sample bias for dispatched micro-ops

The following commit has been merged into the perf/urgent branch of tip: Commit-ID: 0f4cd769c410e2285a4e9873a684d90423f03090 Gitweb: https://git.kernel.org/tip/0f4cd769c410e2285a4e9873a684d90423f03090 Author:Kim Phillips AuthorDate:Mon, 26 Aug 2019 14:57:30 -05:00

[RFC] perf/x86/amd: add support for Large Increment per Cycle Events

u 800,000,000 cpu/event=0x03,umask=0xff/u 0.041359898 seconds time elapsed 0.04120 seconds user 0.0 seconds sys Fixes: e40ed1542dd7 ("perf/x86: Add perf support for AMD family-17h processors") Signed-off-by: Kim Phillips Cc: Janakarajan Nataraja

[PATCH] perf/x86/amd/ibs: Fix sample bias for dispatched micro-ops

operation. It is unknown why commit db98c5faf8cb ("perf/x86: Implement 64-bit counter support for IBS") ignored the lower 4 bits of the IbsOpCurCnt field; the number of preloaded random bits has always been 7, AFAICT. Signed-off-by: Kim Phillips Cc: Stephane Eranian Cc: Peter Zijlstr

[tip:perf/urgent] perf/x86/amd/uncore: Do not set 'ThreadMask' and 'SliceMask' for non-L3 PMCs

Commit-ID: 16f4641166b10e199f0d7b68c2c5f004fef0bda3 Gitweb: https://git.kernel.org/tip/16f4641166b10e199f0d7b68c2c5f004fef0bda3 Author: Kim Phillips AuthorDate: Fri, 28 Jun 2019 21:59:20 + Committer: Ingo Molnar CommitDate: Sat, 13 Jul 2019 11:21:26 +0200 perf/x86/amd/uncore: Do

[tip:perf/urgent] perf/x86/amd/uncore: Set the thread mask for F17h L3 PMCs

Commit-ID: 2f217d58a8a086d3399fecce39fb358848e799c4 Gitweb: https://git.kernel.org/tip/2f217d58a8a086d3399fecce39fb358848e799c4 Author: Kim Phillips AuthorDate: Fri, 28 Jun 2019 21:59:33 + Committer: Ingo Molnar CommitDate: Sat, 13 Jul 2019 11:21:27 +0200 perf/x86/amd/uncore: Set

Re: [PATCH v3 1/6] EDAC/amd64: Add Family 17h Model 30h PCI IDs

Hi Boris, I've tested this patch and it gets rid of a slew of these messages: kernel: EDAC amd64: Error: F0 not found, device 0x1460 (broken BIOS?) kernel: EDAC amd64: Error: Error probing instance: 0 So please add my: Tested-by: Kim Phillips Thank you, Kim On 3/21/19 3:30 PM, Gh

Re: [PATCH] Input: synaptics - add PNP IDs for Dell XPS models to forcepad

On 1/17/19 2:13 AM, Benjamin Tissoires wrote: On Wed, Jan 16, 2019 at 5:59 AM Kim Phillips wrote: On 1/15/19 2:57 AM, Benjamin Tissoires wrote: On Mon, Jan 14, 2019 at 7:40 PM Dmitry Torokhov wrote: On Sat, Jan 12, 2019 at 04:04:36PM -0600, Kim Phillips wrote: On 1/11/19 7:40 PM, Dmitry

Re: [PATCH] Input: synaptics - add PNP IDs for Dell XPS models to forcepad

On 1/15/19 2:57 AM, Benjamin Tissoires wrote: On Mon, Jan 14, 2019 at 7:40 PM Dmitry Torokhov wrote: On Sat, Jan 12, 2019 at 04:04:36PM -0600, Kim Phillips wrote: On 1/11/19 7:40 PM, Dmitry Torokhov wrote: Hi Kim, Hi Dmitry, On Fri, Jan 11, 2019 at 02:54:30PM -0600, Kim Phillips wrote

Re: [PATCH] Input: synaptics - add PNP IDs for Dell XPS models to forcepad

On 1/11/19 7:40 PM, Dmitry Torokhov wrote: > Hi Kim, Hi Dmitry, > On Fri, Jan 11, 2019 at 02:54:30PM -0600, Kim Phillips wrote: >> This patch is the result of seeing this message: >> >> psmouse serio1: synaptics: Your touchpad (PNP: DLL087c PNP0f13) says it can >&g

[PATCH] Input: synaptics - add PNP IDs for Dell XPS models to forcepad

t can support a different bus". E.g, this is one such instance: https://lkml.org/lkml/2018/2/15/52 Cc: Paul Menzel Cc: Dmitry Torokhov Cc: Benjamin Tissoires Cc: linux-in...@vger.kernel.org Signed-off-by: Kim Phillips --- With or without this patch, I'm seeing a problem where when t

[tip:perf/core] perf annotate: Handle arm64 move instructions

Commit-ID: 58094c48f4079cfc784f53a73caaa446db436389 Gitweb: https://git.kernel.org/tip/58094c48f4079cfc784f53a73caaa446db436389 Author: Kim Phillips AuthorDate: Mon, 27 Aug 2018 15:08:07 -0500 Committer: Arnaldo Carvalho de Melo CommitDate: Thu, 30 Aug 2018 15:52:25 -0300 perf

[tip:perf/core] perf annotate: Fix parsing aarch64 branch instructions after objdump update

Commit-ID: 4e67b2a5df5d3f341776d12ee575e00ca3ef92de Gitweb: https://git.kernel.org/tip/4e67b2a5df5d3f341776d12ee575e00ca3ef92de Author: Kim Phillips AuthorDate: Mon, 27 Aug 2018 12:53:40 -0500 Committer: Arnaldo Carvalho de Melo CommitDate: Thu, 30 Aug 2018 15:51:54 -0300 perf

[tip:perf/core] perf arm64: Fix include path for asm-generic/unistd.h

Commit-ID: 5ab1de932e2923f490645ad017a689c5b58dc433 Gitweb: https://git.kernel.org/tip/5ab1de932e2923f490645ad017a689c5b58dc433 Author: Kim Phillips AuthorDate: Mon, 6 Aug 2018 17:28:00 -0500 Committer: Arnaldo Carvalho de Melo CommitDate: Thu, 30 Aug 2018 14:49:24 -0300 perf arm64

Re: [PATCH v4 6/8] perf, tools, script: Make itrace script default to all calls

On Mon, 3 Sep 2018 09:22:47 -0700 Andi Kleen wrote: > Fix ETM build failure > --- > diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c > index 2ae640257fdb..0296405f38b2 100644 > --- a/tools/perf/util/cs-etm.c > +++ b/tools/perf/util/cs-etm.c > @@ -1432,7 +1432,8 @@ int cs_etm__pro

Re: Make perf script easier to use for itrace

On Fri, 31 Aug 2018 15:01:56 -0700 Andi Kleen wrote: > Also available in > git://git.kernel.org/pub/scm/linux/kernel/git/ak/linux-misc.git > pt/easy-script-2 > > v1: Initial post > v2: Address review comments. Minor fixes to descriptions. Now builds > everywhere. OK, I grabbed the pt/easy-scr

Re: [PATCH v2] perf: Support for Arm A32/T32 instruction sets in CoreSight trace

For now, share the new feature in a personal git tree, for those that need it. Meanwhile, the library needs to be fixed with a run-time version compatibility API ASAP. Thanks, Kim > On 29/08/18 17:32, Kim Phillips wrote: > > On Wed, 29 Aug 2018 15:34:16 +0100 > > Robert

Re: [PATCH v2] perf: Support for Arm A32/T32 instruction sets in CoreSight trace

On Wed, 29 Aug 2018 15:34:16 +0100 Robert Walker wrote: > Hi Kim, Hi Robert, > On 29/08/18 14:49, Kim Phillips wrote: > > On Wed, 29 Aug 2018 10:44:23 +0100 > > Robert Walker wrote: > > > >> This patch adds support for generating instruction samples from tra

Re: [PATCH v2] perf: Support for Arm A32/T32 instruction sets in CoreSight trace

On Wed, 29 Aug 2018 10:44:23 +0100 Robert Walker wrote: > This patch adds support for generating instruction samples from trace of > AArch32 programs using the A32 and T32 instruction sets. > > T32 has variable 2 or 4 byte instruction size, so the conversion between > addresses and instruction c

Re: [PATCH v4 0/2]: perf: reduce data loss when profiling highly parallel CPU bound workloads

On Tue, 28 Aug 2018 18:44:57 +0300 Alexey Budankov wrote: > Experiment with profiling matrix multiplication code executing 128 > threads on Intel Xeon Phi (KNM) with 272 cores, like below, > demonstrates data loss metrics value of 98%: So I took these two patches for a quick test-drive on intel

[PATCH] perf annotate: Handle arm64 move instructions

Thomas Richter Cc: Hendrik Brueckner Signed-off-by: Kim Phillips --- tools/perf/arch/arm64/annotate/instructions.c | 59 ++- tools/perf/arch/s390/annotate/instructions.c | 2 - 2 files changed, 58 insertions(+), 3 deletions(-) diff --git a/tools/perf/arch/arm64/annotate/in

[PATCH v2] perf annotate: fix parsing aarch64 branch instructions after objdump update

Molnar Cc: Arnaldo Carvalho de Melo Cc: Alexander Shishkin Cc: Jiri Olsa Cc: Namhyung Kim Fixes: b13bbeee5ee6 ("perf annotate: Fix branch instruction with multiple operands") Signed-off-by: Kim Phillips --- v2: address acme's comments: - consolidate into a validate_comma()

Re: [PATCH] perf annotate: fix parsing aarch64 branch instructions after objdump update

On Fri, 24 Aug 2018 09:59:22 +0200 Thomas-Mich Richter wrote: > On 08/24/2018 02:10 AM, Kim Phillips wrote: > > Tested no difference in output for sample x86_64, power arch perf.data > > files. > > Tested, no difference in output on s390. Just to let you know. Thanks!

[PATCH] perf annotate: fix parsing aarch64 branch instructions after objdump update

Molnar Cc: Arnaldo Carvalho de Melo Cc: Alexander Shishkin Cc: Jiri Olsa Cc: Namhyung Kim Fixes: b13bbeee5ee6 ("perf annotate: Fix branch instruction with multiple operands") Signed-off-by: Kim Phillips --- tools/perf/util/annotate.c | 17 - tools/perf/util/annotate

Re: [PATCH] Properly interpret indirect call in perf annotate.

7;t parse only address. > > Signed-off-by: Martin Liška > --- Tested this doesn't incur any grievances parsing aarch64 code: Tested-by: Kim Phillips Thanks, Kim

Re: [PATCH v3 0/7] perf: Add ioctl for PMU driver configuration

On Tue, 21 Aug 2018 11:16:49 -0600 Mathieu Poirier wrote: > On Mon, 20 Aug 2018 at 08:36, Suzuki K Poulose wrote: > > > > On 08/20/2018 03:22 PM, Kim Phillips wrote: > > > On Mon, 20 Aug 2018 11:03:03 +0100 > > > Suzuki K Poulose wrote: > > > >

Re: [PATCH v3 0/7] perf: Add ioctl for PMU driver configuration

On Tue, 21 Aug 2018 09:39:22 +0100 Suzuki K Poulose wrote: > On 08/20/2018 04:25 PM, Kim Phillips wrote: > > On Mon, 20 Aug 2018 15:36:47 +0100 > > Suzuki K Poulose wrote: > > > >> On 08/20/2018 03:22 PM, Kim Phillips wrote: > >>> On Mon, 20 Aug

Re: [PATCH v3 0/7] perf: Add ioctl for PMU driver configuration

On Mon, 20 Aug 2018 15:36:47 +0100 Suzuki K Poulose wrote: > On 08/20/2018 03:22 PM, Kim Phillips wrote: > > On Mon, 20 Aug 2018 11:03:03 +0100 > > Suzuki K Poulose wrote: > > > >> On 08/16/2018 08:28 PM, Mathieu Poirier wrote: > >>> On Wed,

Re: [PATCH v3 0/7] perf: Add ioctl for PMU driver configuration

On Mon, 20 Aug 2018 11:03:03 +0100 Suzuki K Poulose wrote: > On 08/16/2018 08:28 PM, Mathieu Poirier wrote: > > On Wed, 15 Aug 2018 at 09:28, Kim Phillips wrote: > >> > >> On Wed, 15 Aug 2018 10:39:13 +0100 > >> Will Deacon wrote: > >> > >&

[tip:perf/urgent] perf arm spe: Fix uninitialized record error variable

Commit-ID: 344353366591acf659a0d0dea498611da78d67e2 Gitweb: https://git.kernel.org/tip/344353366591acf659a0d0dea498611da78d67e2 Author: Kim Phillips AuthorDate: Fri, 10 Aug 2018 17:45:12 -0500 Committer: Arnaldo Carvalho de Melo CommitDate: Tue, 14 Aug 2018 15:10:44 -0300 perf arm spe

Re: [PATCH v3 0/7] perf: Add ioctl for PMU driver configuration

On Wed, 15 Aug 2018 10:39:13 +0100 Will Deacon wrote: > On Tue, Aug 14, 2018 at 01:42:27PM -0600, Mathieu Poirier wrote: > > On Tue, 14 Aug 2018 at 11:09, Kim Phillips wrote: > > > The other thing that's going on here is that I'm becoming numb to the > > &

Re: [PATCH v3 0/7] perf: Add ioctl for PMU driver configuration

On Tue, 14 Aug 2018 10:15:56 -0600 Mathieu Poirier wrote: > On Mon, 13 Aug 2018 at 11:46, Kim Phillips wrote: > > It yields success for the --per-thread case..: > > > > $ sudo taskset -c 0 ./perf record -e cs_etm/@2001.etf/ --per-thread > > uname -a >

Re: [PATCH v3 0/7] perf: Add ioctl for PMU driver configuration

On Wed, 18 Jul 2018 15:48:00 -0600 Mathieu Poirier wrote: > This set adds the capability to communiate event specific configuration > to the PMU kernel driver using an ioctl(). The functionatlity is made > generic enough for anyone to use but is targeted at the identification > of CoreSight sink

[PATCH] perf tools: arm-spe: Fix uninitialized record error variable

s-etm does. Signed-off-by: Kim Phillips --- Hi Arnaldo, please apply to perf/urgent / stable series if at all possible. Thank you. tools/perf/arch/arm64/util/arm-spe.c | 1 + 1 file changed, 1 insertion(+) diff --git a/tools/perf/arch/arm64/util/arm-spe.c b/tools/perf/arch/arm64/util/arm-s

Re: [GIT PULL 00/44] perf/core improvements and fixes

On Thu, 9 Aug 2018 11:57:38 -0300 Arnaldo Carvalho de Melo wrote: Hi Arnaldo, > Arch specific: > > arm64: (Sean V Kelley) > > - Enable JSON events for Ampere Computing eMAG processor > Did this one get missed?: https://www.mail-archive.com/linux-kernel@vger.kernel.org/msg1745454.html Than

[PATCH] perf arm64: Fix include path for asm-generic/unistd.h

6 ("perf arm64: Generate system call table from asm/unistd.h") Signed-off-by: Kim Phillips --- Hi, sorry for late response - was on vacation. I was able to reproduce and fix by adding this -I to the $hostcc line. Please test, and let me know if this is an acceptable fix. tools/perf/arch/ar

[tip:perf/core] perf trace arm64: Use generated syscall table

Commit-ID: a7f660d6576a5f4504c8ab4f4956bba03d48bf52 Gitweb: https://git.kernel.org/tip/a7f660d6576a5f4504c8ab4f4956bba03d48bf52 Author: Kim Phillips AuthorDate: Fri, 6 Jul 2018 16:34:54 -0500 Committer: Arnaldo Carvalho de Melo CommitDate: Tue, 24 Jul 2018 14:53:01 -0300 perf trace

[tip:perf/core] tools include: Grab copies of arm64 dependent unistd.h files

Commit-ID: 34b009cfde2b8ce20a69c7bfd6bad4ce0e7cd970 Gitweb: https://git.kernel.org/tip/34b009cfde2b8ce20a69c7bfd6bad4ce0e7cd970 Author: Kim Phillips AuthorDate: Fri, 6 Jul 2018 16:34:34 -0500 Committer: Arnaldo Carvalho de Melo CommitDate: Tue, 24 Jul 2018 14:52:39 -0300 tools include

  1   2   3   4   5   >