Re: omap5 fixing palmas IRQ_TYPE_NONE warning leads to gpadc timeouts

2018-11-20 Thread Laxman Dewangan
On Monday 19 November 2018 10:44 PM, Tony Lindgren wrote: Hi, * Tony Lindgren [181119 16:19]: * Peter Ujfalusi [181119 10:16]: On 2018-11-13 20:06, Tony Lindgren wrote: Looks like the IRQ_TYPE_NONE issue still is there for omap5 and should be fixed with IRQ_TYPE_HIGH. No idea about why

Re: [PATCH] pinctrl: max77620: Use define directive for max77620_pinconf_param values

2018-11-09 Thread Laxman Dewangan
-by: Laxman Dewangan

Re: [PATCH v1] i2c: tegra: Remove suspend-resume

2018-05-30 Thread Laxman Dewangan
ssert from the tegra_i2c_init(). So I'd go for a complete suspend/resume removal for now as it is causes problem. Laxman, are you convinced or do you have still objections? Fine with me. Please add my Ack Acked-by: Laxman Dewangan

Re: [PATCH v1] i2c: tegra: Remove suspend-resume

2018-05-14 Thread Laxman Dewangan
On Monday 14 May 2018 05:29 PM, Thierry Reding wrote: * PGP Signed by an unknown key On Mon, May 14, 2018 at 12:13:47AM +0300, Dmitry Osipenko wrote: Nothing prevents I2C clients to access I2C while Tegra's driver is being suspended, this results in -EBUSY error returned to the clients and

Re: [PATCH 05/10] hwmon: generic-pwm-tachometer: Add generic PWM based tachometer

2018-03-08 Thread Laxman Dewangan
On Thursday 08 March 2018 08:01 PM, Guenter Roeck wrote: On 03/07/2018 10:06 PM, Laxman Dewangan wrote: The RPM is measured speed via PWM signal capture which is output from fan. So should we have the fan[1..n]_output_rpm? No. I hear you clearly that you for some reason dislike fan[1

Re: [PATCH 05/10] hwmon: generic-pwm-tachometer: Add generic PWM based tachometer

2018-03-07 Thread Laxman Dewangan
On Wednesday 07 March 2018 07:50 PM, Guenter Roeck wrote: On 03/07/2018 01:47 AM, Rajkumar Rampelli wrote: While I am not opposed to ABI changes, the merits of those would need to be discussed on the mailing list. But replacing "fan1_input" with "rpm" is not an acceptable ABI change,

Re: [PATCH] spi: tegra20-slink: use true and false for boolean values

2018-03-05 Thread Laxman Dewangan
On Tuesday 06 March 2018 05:23 AM, Gustavo A. R. Silva wrote: Assign true or false to boolean variables instead of an integer value. This issue was detected with the help of Coccinelle. Signed-off-by: Gustavo A. R. Silva <gust...@embeddedor.com> Acked-by: Laxman Dewangan &

Re: [PATCH v3 01/11] regulator: core: add API to get voltage constraints

2018-02-08 Thread Laxman Dewangan
On Wednesday 07 February 2018 09:07 PM, Mark Brown wrote: On Wed, Feb 07, 2018 at 05:20:45PM +0200, Peter De Schrijver wrote: On Wed, Feb 07, 2018 at 03:01:55PM +, Mark Brown wrote: I can't really tell what you're saying here. If the driver needs to know if it can set the a given

Re: [PATCH 1/2] serial: tegra: Delete an error message for a failed memory allocation in tegra_uart_probe()

2017-12-08 Thread Laxman Dewangan
Acked-by: Laxman Dewangan <ldewan...@nvidia.com>

Re: [PATCH 2/2] serial: tegra: Fix a typo in a comment line

2017-12-08 Thread Laxman Dewangan
On Friday 08 December 2017 01:51 AM, SF Markus Elfring wrote: From: Markus Elfring <elfr...@users.sourceforge.net> Date: Thu, 7 Dec 2017 21:06:25 +0100 Delete a duplicate character in a word of this description. Acked-by: Laxman Dewangan <ldewan...@nvidia.com>

Re: [PATCH V2] thermal/drivers/generic-iio-adc: Switch tz request to devm version

2017-09-08 Thread Laxman Dewangan
-devm version of thermal_zone_of_sensor_register(). Now the devm_iio_channel_get() is available, do the corresponding change in this driver and remove gadc_thermal_remove(). Acked-by: Laxman Dewangan <ldewan...@nvidia.com> Thanks, Laxman

Re: [PATCH 1/1] gpio: core: Decouple open drain/source flag with active low/high

2017-07-19 Thread Laxman Dewangan
On Wednesday 19 July 2017 06:55 PM, Johan Hovold wrote: On Fri, Apr 07, 2017 at 12:25:49PM +0200, Linus Walleij wrote: On Thu, Apr 6, 2017 at 3:35 PM, Laxman Dewangan <ldewan...@nvidia.com> wrote: Currently, the GPIO interface is said to Open Drain if it is Single Ended and acti

Re: [PATCH V2] pwm: tegra: Set maximum pwm clock source per SoC tapeout

2017-05-15 Thread Laxman Dewangan
On Tuesday 02 May 2017 11:13 PM, Laxman Dewangan wrote: On Tuesday 02 May 2017 08:53 PM, Jon Hunter wrote: On 02/05/17 15:05, Laxman Dewangan wrote: The PWM hardware IP is taped-out with different maximum frequency on different SoCs. From HW team: Before Tegra186, it is 38.4MHz

Re: [PATCH V2] pwm: tegra: Set maximum pwm clock source per SoC tapeout

2017-05-02 Thread Laxman Dewangan
On Tuesday 02 May 2017 08:53 PM, Jon Hunter wrote: On 02/05/17 15:05, Laxman Dewangan wrote: The PWM hardware IP is taped-out with different maximum frequency on different SoCs. From HW team: Before Tegra186, it is 38.4MHz. In Tegra186, it is 102MHz. Add support to limit

[PATCH V2] pwm: tegra: Set maximum pwm clock source per SoC tapeout

2017-05-02 Thread Laxman Dewangan
SoC chipdata. Signed-off-by: Laxman Dewangan <ldewan...@nvidia.com> --- Changes from V1: - Set the 48MHz maximum frequency for Tegra210 and earlier. - Set the maximum frequency unconditionally as per V1 review comment. --- drivers/pwm/pwm-tegra.c | 18 +- 1 file changed, 17 i

Re: [PATCH v2 1/2] regulator: DT: Add properties for asymmetric settling times

2017-05-02 Thread Laxman Dewangan
org> --- Acked-by: Laxman Dewangan <ldewan...@nvidia.com>

Re: [PATCH v2 2/2] regulator: Allow for asymmetric settling times

2017-05-02 Thread Laxman Dewangan
t;m...@chromium.org> --- Acked-by: Laxman Dewangan <ldewan...@nvidia.com>

Re: [PATCH] regulator: Allow for asymmetric settling times

2017-04-29 Thread Laxman Dewangan
On Saturday 29 April 2017 05:36 AM, Matthias Kaehlcke wrote: Some regulators have different settling times for voltage increases and decreases. To avoid a time penalty on the faster transition extend the settling time property to allow for different settings for upward and downward transitions.

Re: [PATCH] regulator: tps65132: fix platform_no_drv_owner.cocci warnings

2017-04-14 Thread Laxman Dewangan
: Venkat Reddy Talla <vreddyta...@nvidia.com> Signed-off-by: Fengguang Wu <fengguang...@intel.com> --- LGTM, Acked-by: Laxman Dewangan <ldewan...@nvidia.com>

Re: [PATCH 2/2] pwm: tegra: Set maximum pwm clock source per SoC tapeout

2017-04-13 Thread Laxman Dewangan
On Thursday 13 April 2017 08:57 PM, Thierry Reding wrote: * PGP Signed by an unknown key On Thu, Apr 13, 2017 at 07:40:28PM +0530, Laxman Dewangan wrote: The PWM hardware IP is taped-out with different maximum frequency on different SoCs. From HW team: For Tegra210, it is 38.4MHz

[PATCH 2/2] pwm: tegra: Set maximum pwm clock source per SoC tapeout

2017-04-13 Thread Laxman Dewangan
SoC chipdata. Signed-off-by: Laxman Dewangan <ldewan...@nvidia.com> --- drivers/pwm/pwm-tegra.c | 28 1 file changed, 28 insertions(+) diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c index 8c6ed55..7016c08 100644 --- a/drivers/pwm/pwm-tegra.c +++ b/driver

[PATCH 1/2] pwm: tegra: Read PWM clock source rate in driver init

2017-04-13 Thread Laxman Dewangan
in avoiding the clock call for getting clock rate in the pwm_config() each time. Signed-off-by: Laxman Dewangan <ldewan...@nvidia.com> --- drivers/pwm/pwm-tegra.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c index c

Re: [PATCH 1/1] gpio: core: Decouple open drain/source flag with active low/high

2017-04-07 Thread Laxman Dewangan
On Friday 07 April 2017 03:55 PM, Linus Walleij wrote: On Thu, Apr 6, 2017 at 3:35 PM, Laxman Dewangan <ldewan...@nvidia.com> wrote: Currently, the GPIO interface is said to Open Drain if it is Single Ended and active LOW. Similarly, it is said as Open Source if it is Single Ended and

[PATCH V3 4/4] pwm: tegra: Add support to configure pin state in suspends/resume

2017-04-07 Thread Laxman Dewangan
devices require the PWM output to be tristated. Add support to configure the pin state via pinctrl frameworks in suspend and active state of the system. Signed-off-by: Laxman Dewangan <ldewan...@nvidia.com> --- Changes from v1: - Use standard pinctrl names for sleep and active state. - U

[PATCH V3 3/4] pwm: tegra: Add DT binding details to configure pin in suspends/resume

2017-04-07 Thread Laxman Dewangan
devices require the PWM output to be tristated. Add DT binding details to provide the pin configuration state from PWM and pinctrl DT node in suspend and active state of the system. Signed-off-by: Laxman Dewangan <ldewan...@nvidia.com> --- Changes from v1: - Use standard pinctrl names for

[PATCH V3 2/4] pwm: tegra: Increase precision in pwm rate calculation

2017-04-07 Thread Laxman Dewangan
on old formula: hz = 59, rate = 3390 Based on new formula: hz = 5951, rate = 3360 The PWM signal rate of 3360 is more near to requested period than . Signed-off-by: Laxman Dewangan <ldewan...@nvidia.com> --- Changes from v1: - None Change

[PATCH V3 1/4] pwm: tegra: Use DIV_ROUND_CLOSEST_ULL() instead of local implementation

2017-04-07 Thread Laxman Dewangan
Use macro DIV_ROUND_CLOSEST_ULL() for 64bit division to closest one instead of implementing the same locally. This increase readability. Signed-off-by: Laxman Dewangan <ldewan...@nvidia.com> --- Changes from v1: - None Changes from V2: - Fix typo in commit message. --- drivers/pwm/pwm-t

[PATCH V3 0/4] pwm: tegra: Pin configuration in suspend/resume and cleanups

2017-04-07 Thread Laxman Dewangan
pinctrl_pm_select_*() Changes from V2: - Type fixes, rephrases commit message and use pinctrl_pm_state* return value. Laxman Dewangan (4): pwm: tegra: Use DIV_ROUND_CLOSEST_ULL() instead of local implementation pwm: tegra: Increase precision in pwm rate calculation pwm: tegra: Add DT

Re: [PATCH 1/1] gpio: core: Decouple open drain/source flag with active low/high

2017-04-06 Thread Laxman Dewangan
On Thursday 06 April 2017 09:40 PM, Andy Shevchenko wrote: On Thu, Apr 6, 2017 at 4:35 PM, Laxman Dewangan <ldewan...@nvidia.com> wrote: Currently, the GPIO interface is said to Open Drain if it is Single Ended and active LOW. Similarly, it is said as Open Source if it is Single

Re: [PATCH V3 3/4] pwm: tegra: Add DT binding details to configure pin in suspends/resume

2017-04-06 Thread Laxman Dewangan
On Thursday 06 April 2017 08:56 PM, Jon Hunter wrote: On 06/04/17 15:21, Laxman Dewangan wrote: In some of NVIDIA Tegra's platform, PWM controller is used to control the PWM controlled regulators. PWM signal is connected to the VID pin of the regulator where duty cycle of PWM signal decide

Re: [PATCH V4 4/4] pwm: tegra: Add support to configure pin state in suspends/resume

2017-04-06 Thread Laxman Dewangan
Oops, it was actually v2. On Thursday 06 April 2017 08:47 PM, Jon Hunter wrote: On 06/04/17 15:21, Laxman Dewangan wrote: In some of NVIDIA Tegra's platform, PWM controller is used to control the PWM controlled regulators. PWM signal is connected to the VID pin of the regulator where duty

[PATCH V2 0/4] pwm: tegra: Pin configuration in suspend/resume and cleanups

2017-04-06 Thread Laxman Dewangan
pinctrl_pm_select_*() Laxman Dewangan (4): pwm: tegra: Use DIV_ROUND_CLOSEST_ULL() instead of local implementation pwm: tegra: Increase precision in pwm rate calculation pwm: tegra: Add DT binding details to configure pin in suspends/resume pwm: tegra: Add support to configure pin state

[PATCH V2 2/4] pwm: tegra: Increase precision in pwm rate calculation

2017-04-06 Thread Laxman Dewangan
formula: hz = 60, rate = Based on new formula: hz = 5951, rate = 3360 The rate of 3360 is more near to requested period then the . Signed-off-by: Laxman Dewangan <ldewan...@nvidia.com> --- Changes from V1: - None drivers/pwm/pwm-tegra

[PATCH V4 4/4] pwm: tegra: Add support to configure pin state in suspends/resume

2017-04-06 Thread Laxman Dewangan
define one of the state of PWM regulator which needs to be configure in suspend state of system. Add support to configure the pin state via pinctrl frameworks in suspend and active state of the system. Signed-off-by: Laxman Dewangan <ldewan...@nvidia.com> --- Changes from v1: - Use standard p

[PATCH V2 1/4] pwm: tegra: Use DIV_ROUND_CLOSEST_ULL() instead of local implementation

2017-04-06 Thread Laxman Dewangan
Use macro DIV_ROUND_CLOSEST_ULL() for 64bit division to closet one instead of implementing the same locally. This increase readability. Signed-off-by: Laxman Dewangan <ldewan...@nvidia.com> --- Changes from V1: None drivers/pwm/pwm-tegra.c | 3 +-- 1 file changed, 1 insertion(+), 2 del

[PATCH V3 3/4] pwm: tegra: Add DT binding details to configure pin in suspends/resume

2017-04-06 Thread Laxman Dewangan
define one of the state of PWM regulator which needs to be configure in suspend state of system. Add DT binding details to provide the pin configuration state from PWM and pinctrl DT node in suspend and active state of the system. Signed-off-by: Laxman Dewangan <ldewan...@nvidia.com> --- C

[PATCH 1/1] gpio: core: Decouple open drain/source flag with active low/high

2017-04-06 Thread Laxman Dewangan
only when Single ended flag is enabled. Signed-off-by: Laxman Dewangan <ldewan...@nvidia.com> --- drivers/gpio/gpiolib-of.c | 2 +- drivers/gpio/gpiolib.c | 4 +++- include/dt-bindings/gpio/gpio.h | 12 include/linux/of_gpio.h | 1 + 4 files chang

Re: [PATCH 3/4] pwm: tegra: Add DT binding details to configure pin in suspends/resume

2017-04-06 Thread Laxman Dewangan
On Thursday 06 April 2017 06:33 PM, Thierry Reding wrote: * PGP Signed by an unknown key On Thu, Apr 06, 2017 at 09:57:09AM +0100, Jon Hunter wrote: On 05/04/17 15:13, Laxman Dewangan wrote: +state of the system. The configuration of pin is provided via the pinctrl +DT node as detailed

[PATCH 0/4] pwm: tegra: Pin configuration in suspend/resume and cleanups

2017-04-05 Thread Laxman Dewangan
This patch series have following fixes: - Add more precession in PWM period register value calculation for lower pwm frequency. - Add support to configure PWM pins in different state in the suspend/resume. Laxman Dewangan (4): pwm: tegra: Use DIV_ROUND_CLOSEST_ULL() instead of local

[PATCH 1/4] pwm: tegra: Use DIV_ROUND_CLOSEST_ULL() instead of local implementation

2017-04-05 Thread Laxman Dewangan
Use macro DIV_ROUND_CLOSEST_ULL() for 64bit division to closet one instead of implementing the same locally. This increase readability. Signed-off-by: Laxman Dewangan <ldewan...@nvidia.com> --- drivers/pwm/pwm-tegra.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/d

[PATCH 2/4] pwm: tegra: Increase precision in pwm rate calculation

2017-04-05 Thread Laxman Dewangan
formula: hz = 60, rate = Based on new formula: hz = 5951, rate = 3360 The rate of 3360 is more near to requested period then the . Signed-off-by: Laxman Dewangan <ldewan...@nvidia.com> --- drivers/pwm/pwm-tegra.c | 8 ++-- 1 file c

[PATCH 4/4] pwm: tegra: Add support to configure pin state in suspends/resume

2017-04-05 Thread Laxman Dewangan
define one of the state of PWM regulator which needs to be configure in suspend state of system. Add support to configure the pin state via pinctrl frameworks in suspend and active state of the system. Signed-off-by: Laxman Dewangan <ldewan...@nvidia.com> --- drivers/pwm/pwm-tegra.

[PATCH 3/4] pwm: tegra: Add DT binding details to configure pin in suspends/resume

2017-04-05 Thread Laxman Dewangan
define one of the state of PWM regulator which needs to be configure in suspend state of system. Add DT binding details to provide the pin configuration state from PWM and pinctrl DT node in suspend and active state of the system. Signed-off-by: Laxman Dewangan <ldewan...@nvidia.

[PATCH V4 2/2] regulator: Add settling time for non-linear voltage transition

2017-04-04 Thread Laxman Dewangan
settling time. Signed-off-by: Laxman Dewangan <ldewan...@nvidia.com> --- This patch is continuation of discussion on patch regulator: pwm: Fix regulator ramp delay for continuous mode https://patchwork.kernel.org/patch/9216857/ where is it discussed to have separate property for PWM whi

[PATCH V4 1/2] regulator: DT: Add settling time property for non-linear voltage change

2017-04-04 Thread Laxman Dewangan
Some regulators (some PWM regulators) have the voltage transition exponentially. On such cases, the settling time for voltage change is treated as constant time. Add DT property for providing the settling time for any level of voltage change for non-linear voltage change. signed-off-by: Laxman

Re: [PATCH] serial: tegra: Map the iir register to default defines

2017-03-30 Thread Laxman Dewangan
-off-by: Olliver Schinagl <oli...@schinagl.nl> --- Adding Shardar for verifications. Acked-by: Laxman Dewangan <ldewan...@nvidia.com>

Re: [PATCH] power: reset: Add MAX77620 support

2017-01-12 Thread Laxman Dewangan
On Thursday 12 January 2017 11:05 PM, Thierry Reding wrote: * PGP Signed by an unknown key On Thu, Jan 12, 2017 at 10:06:24PM +0530, Laxman Dewangan wrote: On Thursday 12 January 2017 09:45 PM, Thierry Reding wrote: + dev_dbg(>dev, "event recorder: %#x\n

Re: [PATCH] power: reset: Add MAX77620 support

2017-01-12 Thread Laxman Dewangan
On Thursday 12 January 2017 09:45 PM, Thierry Reding wrote: From: Thierry Reding The Maxim MAX77620 PMIC has the ability to power off and restart the system. Add a driver that supports power off (via pm_power_off()) and restart (via arm_pm_restart() on 32-bit and 64-bit

Re: [PATCH 0/4] mfd: max77686: Remove unneeded non-OF code in driver

2017-01-12 Thread Laxman Dewangan
me also review the max77620 on similar cleanups. Acked-by: Laxman Dewangan <ldewan...@nvidia.com>

Re: [PATCH V4 2/2] pinctrl: tegra: Add driver to configure voltage and power of io pads

2016-11-28 Thread Laxman Dewangan
On Monday 28 November 2016 02:56 PM, Jon Hunter wrote: On 25/11/16 17:49, Laxman Dewangan wrote: In the above dpaux driver, you used the pinctrl framework and its core functionality for the device tree interfacing and client interfacing. The same thing I am saying here, we should not avoid

Re: [PATCH V4 2/2] pinctrl: tegra: Add driver to configure voltage and power of io pads

2016-11-25 Thread Laxman Dewangan
On Friday 25 November 2016 10:59 PM, Jon Hunter wrote: On 25/11/16 12:04, Laxman Dewangan wrote: Thanks Thierry for review. On Friday 25 November 2016 03:27 PM, Thierry Reding wrote: * PGP Signed by an unknown key On Thu, Nov 24, 2016 at 02:08:54PM +0530, Laxman Dewangan wrote

Re: [PATCH V4 2/2] pinctrl: tegra: Add driver to configure voltage and power of io pads

2016-11-25 Thread Laxman Dewangan
On Friday 25 November 2016 10:56 PM, Jon Hunter wrote: On 25/11/16 09:57, Thierry Reding wrote: * PGP Signed by an unknown key On Thu, Nov 24, 2016 at 02:08:54PM +0530, Laxman Dewangan wrote: ... diff --git a/drivers/pinctrl/tegra/pinctrl-tegra-io-pad.c b/drivers/pinctrl/tegra/pinctrl

Re: [PATCH] gpio: Add Tegra186 support

2016-11-25 Thread Laxman Dewangan
On Thursday 24 November 2016 08:38 PM, Thierry Reding wrote: * PGP Signed by an unknown key On Thu, Nov 24, 2016 at 08:14:31PM +0530, Laxman Dewangan wrote: This has nothing to do with the device tree binding. What the device tree binding defines is the indices to use to obtain a given GPIO

Re: [PATCH V4 2/2] pinctrl: tegra: Add driver to configure voltage and power of io pads

2016-11-25 Thread Laxman Dewangan
Thanks Thierry for review. On Friday 25 November 2016 03:27 PM, Thierry Reding wrote: * PGP Signed by an unknown key On Thu, Nov 24, 2016 at 02:08:54PM +0530, Laxman Dewangan wrote: + NVIDIA Tegra124/210 SoC has IO pads which supports multi-voltage + level of interfacing

Re: [PATCH V4 1/2] pinctrl: tegra: Add DT binding for io pads control

2016-11-25 Thread Laxman Dewangan
On Friday 25 November 2016 02:43 PM, Thierry Reding wrote: * PGP Signed by an unknown key On Thu, Nov 24, 2016 at 02:08:53PM +0530, Laxman Dewangan wrote: + +The DT property of the IO pads must be under the node of pmc i.e. +pmc@7000e400 for Tegra124 onwards. The PMC is at a different

Re: [PATCH] gpio: Add Tegra186 support

2016-11-24 Thread Laxman Dewangan
On Thursday 24 November 2016 08:14 PM, Thierry Reding wrote: * PGP Signed by an unknown key On Thu, Nov 24, 2016 at 12:23:56PM +0530, Laxman Dewangan wrote: On Tuesday 22 November 2016 11:25 PM, Thierry Reding wrote: +static inline struct tegra_gpio *to_tegra_gpio(struct gpio_chip *chip

Re: [PATCH V3 2/2] pinctrl: tegra: Add driver to configure voltage and power of io pads

2016-11-24 Thread Laxman Dewangan
On Thursday 24 November 2016 07:41 PM, Linus Walleij wrote: On Wed, Nov 23, 2016 at 12:42 PM, Laxman Dewangan <ldewan...@nvidia.com> wrote: Here, we need the regulator handle which can support the other regulator APIs. In some of platforms, we do not use some of the io-pins and on thi

[PATCH V4 2/2] pinctrl: tegra: Add driver to configure voltage and power of io pads

2016-11-24 Thread Laxman Dewangan
can be static and dynamic. Signed-off-by: Laxman Dewangan <ldewan...@nvidia.com> --- Changes from V1: - Dropped the custom properties to set pad voltage and use regulator. - Added support for regulator to get vottage in boot and configure IO pad voltage. - Add support for callback to

[PATCH V4 0/2] pinctrl: tegra: Add support for IO pad control

2016-11-24 Thread Laxman Dewangan
as per review comment from V2. Changes from V3: Use devm_regulator_get() instead of devm_regulator_get_optional(). Laxman Dewangan (2): pinctrl: tegra: Add DT binding for io pads control pinctrl: tegra: Add driver to configure voltage and power of io pads .../bindings/pinctrl/nvidia,tegra

[PATCH V4 1/2] pinctrl: tegra: Add DT binding for io pads control

2016-11-24 Thread Laxman Dewangan
from SoC and hence SW need to configure the PMC register explicitly to set proper voltage in IO pads based on IO rail power source voltage. Add DT binding document for detailing the DT properties for configuring IO pads voltage levels and its power state. Signed-off-by: Laxman Dewangan <lde

Re: [PATCH] gpio: Add Tegra186 support

2016-11-23 Thread Laxman Dewangan
On Tuesday 22 November 2016 11:25 PM, Thierry Reding wrote: +static inline struct tegra_gpio *to_tegra_gpio(struct gpio_chip *chip) +{ + return container_of(chip, struct tegra_gpio, gpio); +} You dont need this as gpiochip_get_data(chip); can provide the required driver specific data.

Re: [PATCH] gpio: tegra186: Add support for T186 GPIO

2016-11-23 Thread Laxman Dewangan
On Thursday 24 November 2016 01:10 AM, Thierry Reding wrote: * PGP Signed by an unknown key On Wed, Nov 23, 2016 at 02:25:51PM +0100, Linus Walleij wrote: This is already possible and several drivers are doing this. Everything, all kernel users and all character device users, end up calling

Re: [PATCH V3 2/2] pinctrl: tegra: Add driver to configure voltage and power of io pads

2016-11-23 Thread Laxman Dewangan
On Tuesday 22 November 2016 06:28 PM, Linus Walleij wrote: On Tue, Nov 22, 2016 at 11:20 AM, Laxman Dewangan <ldewan...@nvidia.com> wrote: + rinfo->regulator = devm_regulator_get_optional(dev, + soc_data->cfg[i].vsupp

[PATCH V3 2/2] regulator: Add settling time for non-linear voltage transition

2016-11-23 Thread Laxman Dewangan
settling time. Signed-off-by: Laxman Dewangan <ldewan...@nvidia.com> CC: Douglas Anderson <diand...@chromium.org> CC: Aleksandr Frid <af...@nvidia.com> --- This patch is continuation of discussion on patch regulator: pwm: Fix regulator ramp delay for continuous mode https://pa

[PATCH V3 1/2] regulator: DT: Add settling time property for non-linear voltage change

2016-11-23 Thread Laxman Dewangan
Some regulators (some PWM regulators) have the voltage transition exponentially. On such cases, the settling time for voltage change is treated as constant time. Add DT property for providing the settling time for any level of voltage change for non-linear voltage change. Signed-off-by: Laxman

Re: [PATCH V2 0/4] soc/tegra: pmc: Add support for IO pad configuration and sub-driver

2016-11-22 Thread Laxman Dewangan
Thierry, On Wednesday 09 November 2016 06:39 PM, Laxman Dewangan wrote: Tegra SoC support the configutaion of IO pads to multi-level voltage and low power state. The conifguration is done via pictrl framework and the io pad driver in pinctrl frameowrk uses the APIs from pmc to access PMC

[PATCH V3 1/2] pinctrl: tegra: Add DT binding for io pads control

2016-11-22 Thread Laxman Dewangan
from SoC and hence SW need to configure the PMC register explicitly to set proper voltage in IO pads based on IO rail power source voltage. Add DT binding document for detailing the DT properties for configuring IO pads voltage levels and its power state. Signed-off-by: Laxman Dewangan <lde

[PATCH V3 2/2] pinctrl: tegra: Add driver to configure voltage and power of io pads

2016-11-22 Thread Laxman Dewangan
can be static and dynamic. Signed-off-by: Laxman Dewangan <ldewan...@nvidia.com> --- Changes from V1: - Dropped the custom properties to set pad voltage and use regulator. - Added support for regulator to get vottage in boot and configure IO pad voltage. - Add support for callback to

[PATCH V3 0/2] pinctrl: tegra: Add support for IO pad control

2016-11-22 Thread Laxman Dewangan
as per review comment from V2. Laxman Dewangan (2): pinctrl: tegra: Add DT binding for io pads control pinctrl: tegra: Add driver to configure voltage and power of io pads .../bindings/pinctrl/nvidia,tegra-io-pad.txt | 126 + drivers/pinctrl/tegra/Kconfig | 12

Re: [PATCH V2 2/2] pinctrl: tegra: Add driver to configure voltage and power of io pads

2016-11-22 Thread Laxman Dewangan
On Tuesday 22 November 2016 03:15 PM, Joe Perches wrote: On Tue, 2016-11-22 at 13:45 +0530, Laxman Dewangan wrote: On Tuesday 22 November 2016 02:31 AM, Jon Hunter wrote: On 09/11/16 13:06, Laxman Dewangan wrote: + _entry_(32, "uart", UART, true, &

Re: [PATCH V2 1/2] regulator: pwm: DT: Add ramp delay for exponential voltage transition

2016-11-22 Thread Laxman Dewangan
On Monday 21 November 2016 09:47 PM, Rob Herring wrote: On Fri, Nov 18, 2016 at 08:05:55PM +0530, Laxman Dewangan wrote: Some PWM regulator has the exponential transition in voltage change as opposite to fixed slew-rate linear transition on other regulators. For such PWM regulators, add

Re: [PATCH V2 2/2] pinctrl: tegra: Add driver to configure voltage and power of io pads

2016-11-22 Thread Laxman Dewangan
On Tuesday 22 November 2016 02:31 AM, Jon Hunter wrote: On 09/11/16 13:06, Laxman Dewangan wrote: + _entry_(32, "uart", UART, true, "vddio-uart"), \ + _entry_(33, "usb0", USB0, true, NULL),\ + _entry

Re: [PATCH V2 2/2] pinctrl: tegra: Add driver to configure voltage and power of io pads

2016-11-22 Thread Laxman Dewangan
On Tuesday 22 November 2016 02:07 AM, Jon Hunter wrote: On 21/11/16 12:49, Laxman Dewangan wrote: On Monday 21 November 2016 04:38 PM, Jon Hunter wrote: I had a discussion with the ASIC on this and as per them 1.8 V nominal is (1.62V, 1.98V) 3.3 V nominal is (2.97V,3.63V) I am

Re: [PATCH V2 2/2] pinctrl: tegra: Add driver to configure voltage and power of io pads

2016-11-21 Thread Laxman Dewangan
On Monday 21 November 2016 04:38 PM, Jon Hunter wrote: I had a discussion with the ASIC on this and as per them 1.8 V nominal is (1.62V, 1.98V) 3.3 V nominal is (2.97V,3.63V) I am working with them to update the TRM document but we can assume that this information will be there in

Re: [PATCH V2 2/2] pinctrl: tegra: Add driver to configure voltage and power of io pads

2016-11-21 Thread Laxman Dewangan
Hi Jon, I will update the patch per your comment. Here is answer for some of the query. Thanks, Laxman On Tuesday 15 November 2016 08:37 PM, Jon Hunter wrote: On 09/11/16 13:06, Laxman Dewangan wrote: +/** + * Macro for 1.8V, keep 200mV as tolerance for deciding that + * IO pads should

Re: [PATCH V2 1/2] pinctrl: tegra: Add DT binding for io pads control

2016-11-21 Thread Laxman Dewangan
On Wednesday 16 November 2016 12:18 AM, Jon Hunter wrote: On 09/11/16 13:06, Laxman Dewangan wrote: +NVIDIA Tegra124 and later SoCs support the multi-voltage level and +low power state of some of its IO pads. When IO interface are not +used then IO pads can be configure in low power state

[PATCH V2 1/2] regulator: pwm: DT: Add ramp delay for exponential voltage transition

2016-11-18 Thread Laxman Dewangan
Some PWM regulator has the exponential transition in voltage change as opposite to fixed slew-rate linear transition on other regulators. For such PWM regulators, add the property to tell that voltage change is exponential and having fixed delay for any level of change. Signed-off-by: Laxman

[PATCH V2 2/2] regulator: pwm: Add ramp delay for exponential voltage transition

2016-11-18 Thread Laxman Dewangan
Some PWM regulator has the exponential transition in voltage change as opposite to fixed slew-rate linear transition on other regulators. For such PWM regulators, add support for handling the exponential voltage ramp delay. Signed-off-by: Laxman Dewangan <ldewan...@nvidia.com> CC: D

Re: [PATCH 1/2] regulator: pwm: DT: Add ramp delay for exponential voltage transition

2016-11-15 Thread Laxman Dewangan
On Tuesday 15 November 2016 07:57 PM, Rob Herring wrote: On Tue, Nov 15, 2016 at 5:42 AM, Laxman Dewangan <ldewan...@nvidia.com> wrote: On Monday 14 November 2016 09:18 PM, Rob Herring wrote: On Fri, Nov 04, 2016 at 11:07:54PM +0530, Laxman Dewangan wrote: regulator +- pwm-reg

Re: [PATCH V2 1/2] pinctrl: tegra: Add DT binding for io pads control

2016-11-15 Thread Laxman Dewangan
On Tuesday 15 November 2016 01:04 AM, Rob Herring wrote: On Wed, Nov 09, 2016 at 06:36:21PM +0530, Laxman Dewangan wrote: + + audio { + pins = "audio", "dmic", "sdmmc3"; What's the purpose of grouping these?

Re: [PATCH 1/2] regulator: pwm: DT: Add ramp delay for exponential voltage transition

2016-11-15 Thread Laxman Dewangan
On Monday 14 November 2016 09:18 PM, Rob Herring wrote: On Fri, Nov 04, 2016 at 11:07:54PM +0530, Laxman Dewangan wrote: Some PWM regulator has the exponential transition in voltage change as opposite to fixed slew-rate linear transition on other regulators. For such PWM regulators, add

Re: [PATCH 1/1] gpio: lib: Add gpio_is_enabled() to get pin mode

2016-11-15 Thread Laxman Dewangan
On Tuesday 15 November 2016 02:33 PM, Linus Walleij wrote: On Fri, Nov 11, 2016 at 1:17 PM, Laxman Dewangan <ldewan...@nvidia.com> wrote: Yeah but since pinctrl and pinmux has its own debugfs files why is this necessary? I understand it is convenient but only for debugging

Re: [PATCH 1/1] gpio: lib: Add gpio_is_enabled() to get pin mode

2016-11-11 Thread Laxman Dewangan
On Saturday 05 November 2016 03:50 AM, Linus Walleij wrote: On Wed, Nov 2, 2016 at 1:17 PM, Laxman Dewangan <ldewan...@nvidia.com> wrote: Many of devices/SoCs supports the GPIO and special IO function from their pins. On such cases, there is always configuration bits to select the mode

[PATCH V2 1/4] soc/tegra: pmc: Remove legacy Tegra I/O rail API

2016-11-09 Thread Laxman Dewangan
Remove tegra_io_rail_power_on() and tegra_io_rail_power_off() from header as client has been moved to new APIs. Signed-off-by: Laxman Dewangan <ldewan...@nvidia.com> --- Changes from V1: None --- include/soc/tegra/pmc.h | 10 -- 1 file changed, 10 deletions(-) diff --git a/inclu

[PATCH V2 4/4] soc/tegra: pmc: Make configuration of IO pads in atomic context

2016-11-09 Thread Laxman Dewangan
The IO pad voltage configuration can be done in the regulator notifier callback which is atomic in nature. Replace the mutex with spin lock for the locking mechanism. Signed-off-by: Laxman Dewangan <ldewan...@nvidia.com> --- Changes from V1: New in series based on pinctrl driver requi

[PATCH V2 2/4] soc/tegra: pmc: Add interface to get IO pad power status

2016-11-09 Thread Laxman Dewangan
Add API to get the IO pad power status of the Tegra IO pads. This will help client driver to get the current power status of IO pads for handling IO pad power. Signed-off-by: Laxman Dewangan <ldewan...@nvidia.com> --- Changes from V1: None --- drivers/soc/tegra/pmc.

[PATCH V2 3/4] soc/tegra: pmc: Register PMC child devices as platform device

2016-11-09 Thread Laxman Dewangan
and fill the child devices table for Tegra124 and Tegra210. Signed-off-by: Laxman Dewangan <ldewan...@nvidia.com> --- Changes from V1: None --- drivers/soc/tegra/pmc.c | 59 + 1 file changed, 59 insertions(+) diff --git a/drivers/soc/tegra/p

[PATCH V2 0/4] soc/tegra: pmc: Add support for IO pad configuration and sub-driver

2016-11-09 Thread Laxman Dewangan
in https://github.com/thierryreding/linux/tree/tegra186 --- Changes from V1: - make the IO pad votlage configurations to the atomic context as 4th patch of series. Laxman Dewangan (4): soc/tegra: pmc: Remove legacy Tegra I/O rail API soc/tegra: pmc: Add interface to get IO pad power

[PATCH V2 2/2] pinctrl: tegra: Add driver to configure voltage and power of io pads

2016-11-09 Thread Laxman Dewangan
can be static and dynamic. Signed-off-by: Laxman Dewangan <ldewan...@nvidia.com> --- Changes from V1: - Dropped the custom properties to set pad voltage and use regulator. - Added support for regulator to get vottage in boot and configure IO pad voltage. - Add support for callback to

[PATCH V2 1/2] pinctrl: tegra: Add DT binding for io pads control

2016-11-09 Thread Laxman Dewangan
from SoC and hence SW need to configure the PMC register explicitly to set proper voltage in IO pads based on IO rail power source voltage. Add DT binding document for detailing the DT properties for configuring IO pads voltage levels and its power state. Signed-off-by: Laxman Dewangan <lde

[PATCH V2 0/2] pinctrl: tegra: Add support for IO pad control

2016-11-09 Thread Laxman Dewangan
i.e. Linus Welleij to apply in the Thierry's T186 branch along with PMC patches. --- Changes from V1: - use the regulator framework to get the IO voltage instead of table from DT. The regulator handle is provided from DT. Laxman Dewangan (2): pinctrl: tegra: Add DT binding for io pads control

Re: [PATCH 2/2] pinctrl: tegra: Add driver to configure voltage and power of io pads

2016-11-08 Thread Laxman Dewangan
On Tuesday 08 November 2016 09:16 PM, Linus Walleij wrote: On Tue, Nov 8, 2016 at 2:35 PM, Laxman Dewangan <ldewan...@nvidia.com> wrote: There is two types of configuration in given platform, the IO voltage does not get change (fixed in given platform) and in some of cases, get

Re: [PATCH 2/2] pinctrl: tegra: Add driver to configure voltage and power of io pads

2016-11-08 Thread Laxman Dewangan
On Tuesday 08 November 2016 08:12 PM, Thierry Reding wrote: * PGP Signed by an unknown key On Tue, Nov 08, 2016 at 07:05:26PM +0530, Laxman Dewangan wrote: Yes, it can be integrated with the regulator handle and then it can call the required configurations through notifier

Re: [PATCH 2/2] pinctrl: tegra: Add driver to configure voltage and power of io pads

2016-11-08 Thread Laxman Dewangan
On Tuesday 08 November 2016 06:59 PM, Linus Walleij wrote: On Tue, Nov 8, 2016 at 11:20 AM, Laxman Dewangan <ldewan...@nvidia.com> wrote: On Tuesday 08 November 2016 03:45 PM, Linus Walleij wrote: If you can *actually* change the volatage, it needs to be modeled as a (fixed v

Re: [PATCH 2/2] pinctrl: tegra: Add driver to configure voltage and power of io pads

2016-11-08 Thread Laxman Dewangan
On Tuesday 08 November 2016 03:45 PM, Linus Walleij wrote: On Mon, Nov 7, 2016 at 6:41 AM, Laxman Dewangan <ldewan...@nvidia.com> wrote: On Saturday 05 November 2016 03:54 AM, Linus Walleij wrote: On Wed, Nov 2, 2016 at 10:09 AM, Laxman Dewangan <ldewan...@nvidia.com> ()

Re: [PATCH 2/2] pinctrl: tegra: Add driver to configure voltage and power of io pads

2016-11-06 Thread Laxman Dewangan
On Saturday 05 November 2016 03:54 AM, Linus Walleij wrote: On Wed, Nov 2, 2016 at 10:09 AM, Laxman Dewangan <ldewan...@nvidia.com> wrote: NVIDIA Tegra124 and later SoCs support the multi-voltage level and low power state of some of its IO pads. The IO pads can work in the voltage of th

[PATCH 1/2] regulator: pwm: DT: Add ramp delay for exponential voltage transition

2016-11-04 Thread Laxman Dewangan
me-us" added for providing voltage transition delay. Signed-off-by: Laxman Dewangan <ldewan...@nvidia.com> CC: Douglas Anderson <diand...@chromium.org> CC: Aleksandr Frid <af...@nvidia.com> --- This patch is continuation of discussion on patch regulator: p

[PATCH 2/2] regulator: pwm: Add ramp delay for exponential voltage transition

2016-11-04 Thread Laxman Dewangan
is exponential. Signed-off-by: Laxman Dewangan <ldewan...@nvidia.com> CC: Douglas Anderson <diand...@chromium.org> CC: Aleksandr Frid <af...@nvidia.com> --- This patch is continuation of discussion on patch regulator: pwm: Fix regulator ramp delay for con

[PATCH 1/1] gpio: lib: Add gpio_is_enabled() to get pin mode

2016-11-02 Thread Laxman Dewangan
the current mode GPIO or functional mode. The typical utility looks as: pin_dump(pin) { if(gpio_is_enabled(pin)) { dump direction using get_direction() } else { dump pinmux option and its configurations. } } Signed-off-by: Laxman Dewangan

[PATCH 2/2] pinctrl: tegra: Add driver to configure voltage and power of io pads

2016-11-02 Thread Laxman Dewangan
pads based on IO rail power source voltage. This driver adds the IO pad driver to configure the power state and IO pad voltage based on the usage and power tree via pincontrol framework. The configuration can be static and dynamic. Signed-off-by: Laxman Dewangan <ldewan...@nvidia.com> ---

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