Hi Martin,
On 2019/4/19 3:44, Martin Blumenstingl wrote:
Hi Liang,
On Mon, Apr 15, 2019 at 8:04 AM Liang Yang wrote:
On 2019/4/12 6:00, Martin Blumenstingl wrote:
Documentation/scheduler/completion.txt states:
Calling init_completion() on the same completion object twice is
most
0,7 @@ static int meson_nfc_queue_rb(struct meson_nfc *nfc, int
timeout_ms)
cfg |= NFC_RB_IRQ_EN;
writel(cfg, nfc->reg_base + NFC_REG_CFG);
- init_completion(>completion);
+ reinit_completion(>completion);
Tested-by:Liang Yang
Acked-by: Liang Yang
/*
int datalen, void *infobuf, int infolen,
enum dma_data_direction dir)
Tested-by:Liang Yang
Acked-by: Liang Yang
{
struct meson_nfc *nfc = nand_get_controller_data(nand);
u32 cmd;
int ret = 0;
- nfc->daddr = dma_map_single(nf
g", sizeof(u32));
Tested-by:Liang Yang
Acked-by: Liang Yang
if (!nsels || nsels > MAX_CE_NUM) {
dev_err(dev, "invalid register property size\n");
return -EINVAL;
-by: Liang Yang
if (!meson_chip)
return -ENOMEM;
Hi Martin,
On 2019/4/11 1:54, Martin Blumenstingl wrote:
Hi Liang,
On Wed, Apr 10, 2019 at 1:08 PM Liang Yang wrote:
Hi Martin,
On 2019/4/5 12:30, Martin Blumenstingl wrote:
Hi Liang,
On Fri, Mar 29, 2019 at 8:44 AM Liang Yang wrote:
Hi Martin,
On 2019/3/29 2:03, Martin Blumenstingl
Hi Martin,
On 2019/4/5 12:30, Martin Blumenstingl wrote:
Hi Liang,
On Fri, Mar 29, 2019 at 8:44 AM Liang Yang wrote:
Hi Martin,
On 2019/3/29 2:03, Martin Blumenstingl wrote:
Hi Liang,
[..]
I don't think it is caused by a different NAND type, but i have followed
the some test on my
Hi Martin,
On 2019/3/29 2:03, Martin Blumenstingl wrote:
Hi Liang,
[..]
I don't think it is caused by a different NAND type, but i have followed
the some test on my GXL platform. we can see the result from the
attachment. By the way, i don't find any information about this on meson
NFC
Hi Martin,
Thanks a lot.
On 2019/3/26 2:31, Martin Blumenstingl wrote:
Hi Liang,
On Mon, Mar 25, 2019 at 11:03 AM Liang Yang wrote:
Hi Martin,
On 2019/3/23 5:07, Martin Blumenstingl wrote:
Hi Matthew,
On Thu, Mar 21, 2019 at 10:44 PM Matthew Wilcox wrote:
On Thu, Mar 21, 2019 at 09:17
Hi Martin,
On 2019/3/23 5:07, Martin Blumenstingl wrote:
Hi Matthew,
On Thu, Mar 21, 2019 at 10:44 PM Matthew Wilcox wrote:
On Thu, Mar 21, 2019 at 09:17:34PM +0100, Martin Blumenstingl wrote:
Hello,
I am experiencing the following crash:
[ cut here ]
kernel
Specify the oob layout operation to avoid no oob scheme defined for
some nand flash.
Fixes: 8fae856c5350 ("mtd: rawnand: meson: add support for Amlogic NAND flash
controller")
Signed-off-by: Liang Yang
---
drivers/mtd/nand/raw/meson_nand.c | 2 ++
1 file changed, 2 insertions(+)
Hi Martin,
On 2019/3/21 4:48, Martin Blumenstingl wrote:
Hi Liang,
On Wed, Mar 20, 2019 at 4:32 AM Liang Yang wrote:
Hi Martin,
Thanks for your time.
On 2019/3/20 4:27, Martin Blumenstingl wrote:
Hello Liang,
On Sat, Mar 16, 2019 at 11:55 AM Martin Blumenstingl
wrote
Hi Martin,
Thanks for your time.
On 2019/3/20 4:27, Martin Blumenstingl wrote:
Hello Liang,
On Sat, Mar 16, 2019 at 11:55 AM Martin Blumenstingl
wrote:
[...]
Martin, Now i am not sure whether NFC driver leads to kernel panic when
calling kmem_cache_alloc_trace.
thank you for confirming that
Hi Martin and Miquel,
On 2019/3/7 21:09, Miquel Raynal wrote:
Hello,
Martin Blumenstingl wrote on Tue,
5 Mar 2019 23:12:51 +0100:
Hi Liang,
On Mon, Mar 4, 2019 at 5:55 AM Liang Yang wrote:
Hello Martin,
On 2019/3/2 2:29, Martin Blumenstingl wrote:
Hi Liang,
I am trying to add support
Hi Martin,
On 2019/3/7 21:09, Miquel Raynal wrote:
Hello,
Martin Blumenstingl wrote on Tue,
5 Mar 2019 23:12:51 +0100:
Hi Liang,
On Mon, Mar 4, 2019 at 5:55 AM Liang Yang wrote:
Hello Martin,
On 2019/3/2 2:29, Martin Blumenstingl wrote:
Hi Liang,
I am trying to add support for older
Hello Martin,
On 2019/3/2 2:29, Martin Blumenstingl wrote:
Hi Liang,
I am trying to add support for older SoCs to the meson-nand driver.
Back when the driver was in development I used an early revision (of
your driver) and did some modifications to make it work on older SoCs.
Now that the
eson_nfc_dma_buffer_setup(nand, buf, len, info,
PER_INFO_BYTE, DMA_FROM_DEVICE);
if (ret)
- return ret;
+ goto out;
Looks good to me.
Acked-by: Liang Yang
cmd = NFC_CMD_N2M | (len & GENMASK(5, 0));
return -ENOMEM;
+
Thank you very much. it is really good to me.
Acked-by: Liang Yang
ret = meson_nfc_dma_buffer_setup(nand, buf, len, info,
PER_INFO_BYTE, DMA_FROM_DEVICE);
if (ret)
Hi Miquel, Nathan,
On 2019/1/30 23:27, Nathan Chancellor wrote:
On Wed, Jan 30, 2019 at 10:32:20AM +0100, Miquel Raynal wrote:
Hi Liang, Nathan,
Liang Yang wrote on Wed, 30 Jan 2019 17:26:39
+0800:
Hi Nathan,
On 2019/1/30 5:46, Nathan Chancellor wrote:
On arm little endian allyesconfig
Hi Miquel, Colin,
On 2019/1/30 17:34, Colin Ian King wrote:
On 30/01/2019 09:32, Miquel Raynal wrote:
Hi Liang, Colin,
Liang Yang wrote on Wed, 30 Jan 2019 17:26:49
+0800:
Hi Colin,
On 2019/1/29 18:57, Colin King wrote:
From: Colin Ian King
The call to meson_chip_buffer_init
clocks = DIV_ROUND_UP(PSEC_TO_NSEC(timings->tBERS_max),
- div * NFC_CLK_CYCLE);
+ tbers_clocks = DIV_ROUND_UP_ULL(PSEC_TO_NSEC(timings->tBERS_max),
+ div * NFC_CLK_CYCLE);
Looks good to me:
Acked-by: Liang Yang
init(nand);
+ ret = meson_chip_buffer_init(nand);
Looks good to me:
Acked-by: Liang Yang
if (ret)
return -ENOMEM;
_buf(const struct
nand_op_instr *instr)
instr->ctx.data.len, GFP_KERNEL);
}
-void
+static void
meson_nand_op_put_dma_safe_output_buf(const struct nand_op_instr *instr,
const void *buf)
{
Looks good to me:
Acked-by: Liang Yang
Hello Nathan,
On 2019/1/30 5:46, Nathan Chancellor wrote:
On arm little endian allyesconfig:
ld.lld: error: undefined symbol: __aeabi_uldivmod
>>> referenced by meson_nand.c
>>> mtd/nand/raw/meson_nand.o:(meson_nfc_setup_data_interface) in archive
drivers/built-in.a
The dividend
Hello Colin,
On 2019/1/29 18:57, Colin King wrote:
From: Colin Ian King
The call to meson_chip_buffer_init is not assigning ret, however, ret
is being checked for failure. Fix this by adding in the missing assignment.
ok. thanks for your time.
Fixes: 2d570b34b41a ("mtd: rawnand: meson:
Hello Colin,
On 2019/1/29 20:44, Colin King wrote:
From: Colin Ian King
There are several functions that are local to the source and do
not need to be in global scope, so make them static.
Cleans up sparse warnings.
ok. thanks
Signed-off-by: Colin Ian King
---
and its bindings[0].
[0]
https://lore.kernel.org/lkml/1547566684-57472-1-git-send-email-jianxin@amlogic.com/
Signed-off-by: Liang Yang
Signed-off-by: Jianxin Pan
If you are the author of the patch your Signed-off-by should come first.
OK.
Also, why is Liang the Maintainer? Why not you
Hi Martin,
On 2018/12/23 1:07, Martin Blumenstingl wrote:
Hi Jianxin, Hi Liang,
On Fri, Dec 21, 2018 at 12:45 PM Jianxin Pan wrote:
From: Liang Yang
Add initial support for the Amlogic NAND flash controller which found
in the Meson-GXBB/GXL/AXG SoCs.
Signed-off-by: Liang Yang
Signed-off
Hi Miquel,
On 2018/12/11 17:07, Miquel Raynal wrote:
Hi Liang,
Liang Yang wrote on Tue, 11 Dec 2018 16:36:47
+0800:
Hi Miquel,
Thanks for your quickly reply.
On 2018/12/11 15:54, Miquel Raynal wrote:
Hi Liang,
Liang Yang wrote on Tue, 11 Dec 2018 09:56:25
+0800:
Hi Miquel
Hi Boris,
On 2018/12/11 16:39, Boris Brezillon wrote:
On Tue, 11 Dec 2018 09:56:25 +0800
Liang Yang wrote:
Hi Miquel,
On 2018/12/10 22:50, Miquel Raynal wrote:
Hi Liang,
Liang Yang wrote on Mon, 10 Dec 2018 20:12:39
+0800:
On 2018/12/10 19:38, Boris Brezillon wrote:
On Mon, 10 Dec
Hi Miquel,
Thanks for your quickly reply.
On 2018/12/11 15:54, Miquel Raynal wrote:
Hi Liang,
Liang Yang wrote on Tue, 11 Dec 2018 09:56:25
+0800:
Hi Miquel,
On 2018/12/10 22:50, Miquel Raynal wrote:
Hi Liang,
Liang Yang wrote on Mon, 10 Dec 2018 20:12:39
+0800:
On 2018/12/10 19
Hi Miquel,
On 2018/12/10 22:50, Miquel Raynal wrote:
Hi Liang,
Liang Yang wrote on Mon, 10 Dec 2018 20:12:39
+0800:
On 2018/12/10 19:38, Boris Brezillon wrote:
On Mon, 10 Dec 2018 19:23:46 +0800
Liang Yang wrote:
+ mtd->ecc_stats.fai
On 2018/12/10 19:38, Boris Brezillon wrote:
On Mon, 10 Dec 2018 19:23:46 +0800
Liang Yang wrote:
+ mtd->ecc_stats.failed++;
+ continue;
+ }
+ mtd->ecc_stats.corrected += ECC_ERR_CNT(*info);
+ bi
On 2018/12/7 17:24, Miquel Raynal wrote:
Hi Jianxin,
Looks good to me overall, a few comments inline.
Jianxin Pan wrote on Sat, 17 Nov 2018
00:40:38 +0800:
From: Liang Yang
Add initial support for the Amlogic NAND flash controller which found
in the Meson-GXBB/GXL/AXG SoCs.
Signed-off
wrote on Sat, 17 Nov 2018
00:40:38 +0800:
From: Liang Yang
Add initial support for the Amlogic NAND flash controller which found
in the Meson-GXBB/GXL/AXG SoCs.
Signed-off-by: Liang Yang
Signed-off-by: Yixun Lan
Signed-off-by: Jianxin Pan
---
drivers/mtd/nand/raw/Kconfig | 10
wrote on Sat, 17 Nov 2018
00:40:38 +0800:
From: Liang Yang
Add initial support for the Amlogic NAND flash controller which found
in the Meson-GXBB/GXL/AXG SoCs.
Signed-off-by: Liang Yang
Signed-off-by: Yixun Lan
Signed-off-by: Jianxin Pan
---
drivers/mtd/nand/raw/Kconfig | 10
Hi Boris and Miquel,
How about the v7 patch?
On 2018/11/17 0:40, Jianxin Pan wrote:
These two patches try to add initial NAND driver support for Amlogic Meson
SoCs, current it has been tested on GXL(p212) and AXG(s400) platform.
Changes since V6 at [7]
- use timings->tBERS_max as the
Hi Boris and Miquel,
How about the v7 patch?
On 2018/11/17 0:40, Jianxin Pan wrote:
These two patches try to add initial NAND driver support for Amlogic Meson
SoCs, current it has been tested on GXL(p212) and AXG(s400) platform.
Changes since V6 at [7]
- use timings->tBERS_max as the
Hi Boris and Miquel,
understand. i will move helpers into nfc driver to avoid some errors
when sending the patch.
On 2018/11/15 21:09, Boris Brezillon wrote:
On Thu, 15 Nov 2018 14:04:00 +0100
Miquel Raynal wrote:
Hi Liang,
Liang Yang wrote on Thu, 15 Nov 2018 19:25:07
+0800:
Hi Boris
Hi Boris and Miquel,
understand. i will move helpers into nfc driver to avoid some errors
when sending the patch.
On 2018/11/15 21:09, Boris Brezillon wrote:
On Thu, 15 Nov 2018 14:04:00 +0100
Miquel Raynal wrote:
Hi Liang,
Liang Yang wrote on Thu, 15 Nov 2018 19:25:07
+0800:
Hi Boris
on the DMA issue.
On Mon, 12 Nov 2018 17:13:51 +0100
Miquel Raynal wrote:
Hello,
Boris Brezillon wrote on Tue, 6 Nov 2018
11:22:06 +0100:
On Tue, 6 Nov 2018 18:00:37 +0800
Liang Yang wrote:
On 2018/11/6 17:28, Boris Brezillon wrote:
On Tue, 6 Nov 2018 17:08:00 +0800
Liang Yang wrote
on the DMA issue.
On Mon, 12 Nov 2018 17:13:51 +0100
Miquel Raynal wrote:
Hello,
Boris Brezillon wrote on Tue, 6 Nov 2018
11:22:06 +0100:
On Tue, 6 Nov 2018 18:00:37 +0800
Liang Yang wrote:
On 2018/11/6 17:28, Boris Brezillon wrote:
On Tue, 6 Nov 2018 17:08:00 +0800
Liang Yang wrote
On 2018/11/7 0:16, Boris Brezillon wrote:
On Tue, 6 Nov 2018 19:08:27 +0800
Liang Yang wrote:
On 2018/11/6 18:22, Boris Brezillon wrote:
On Tue, 6 Nov 2018 18:00:37 +0800
Liang Yang wrote:
On 2018/11/6 17:28, Boris Brezillon wrote:
On Tue, 6 Nov 2018 17:08:00 +0800
Liang Yang wrote
On 2018/11/7 0:16, Boris Brezillon wrote:
On Tue, 6 Nov 2018 19:08:27 +0800
Liang Yang wrote:
On 2018/11/6 18:22, Boris Brezillon wrote:
On Tue, 6 Nov 2018 18:00:37 +0800
Liang Yang wrote:
On 2018/11/6 17:28, Boris Brezillon wrote:
On Tue, 6 Nov 2018 17:08:00 +0800
Liang Yang wrote
On 2018/11/7 0:16, Boris Brezillon wrote:
On Tue, 6 Nov 2018 19:08:27 +0800
Liang Yang wrote:
On 2018/11/6 18:22, Boris Brezillon wrote:
On Tue, 6 Nov 2018 18:00:37 +0800
Liang Yang wrote:
On 2018/11/6 17:28, Boris Brezillon wrote:
On Tue, 6 Nov 2018 17:08:00 +0800
Liang Yang
On 2018/11/7 0:16, Boris Brezillon wrote:
On Tue, 6 Nov 2018 19:08:27 +0800
Liang Yang wrote:
On 2018/11/6 18:22, Boris Brezillon wrote:
On Tue, 6 Nov 2018 18:00:37 +0800
Liang Yang wrote:
On 2018/11/6 17:28, Boris Brezillon wrote:
On Tue, 6 Nov 2018 17:08:00 +0800
Liang Yang
On 2018/11/6 18:22, Boris Brezillon wrote:
On Tue, 6 Nov 2018 18:00:37 +0800
Liang Yang wrote:
On 2018/11/6 17:28, Boris Brezillon wrote:
On Tue, 6 Nov 2018 17:08:00 +0800
Liang Yang wrote:
On 2018/11/5 23:53, Boris Brezillon wrote:
On Fri, 2 Nov 2018 00:42:21 +0800
Jianxin Pan
On 2018/11/6 18:22, Boris Brezillon wrote:
On Tue, 6 Nov 2018 18:00:37 +0800
Liang Yang wrote:
On 2018/11/6 17:28, Boris Brezillon wrote:
On Tue, 6 Nov 2018 17:08:00 +0800
Liang Yang wrote:
On 2018/11/5 23:53, Boris Brezillon wrote:
On Fri, 2 Nov 2018 00:42:21 +0800
Jianxin Pan
On 2018/11/6 17:28, Boris Brezillon wrote:
On Tue, 6 Nov 2018 17:08:00 +0800
Liang Yang wrote:
On 2018/11/5 23:53, Boris Brezillon wrote:
On Fri, 2 Nov 2018 00:42:21 +0800
Jianxin Pan wrote:
+
+static inline u8 meson_nfc_read_byte(struct mtd_info *mtd)
+{
+ struct nand_chip
On 2018/11/6 17:28, Boris Brezillon wrote:
On Tue, 6 Nov 2018 17:08:00 +0800
Liang Yang wrote:
On 2018/11/5 23:53, Boris Brezillon wrote:
On Fri, 2 Nov 2018 00:42:21 +0800
Jianxin Pan wrote:
+
+static inline u8 meson_nfc_read_byte(struct mtd_info *mtd)
+{
+ struct nand_chip
On 2018/11/5 23:53, Boris Brezillon wrote:
On Fri, 2 Nov 2018 00:42:21 +0800
Jianxin Pan wrote:
+#define NFC_REG_CMD0x00
+#define NFC_CMD_DRD(0x8 << 14)
+#define NFC_CMD_IDLE (0xc << 14)
+#define NFC_CMD_DWR(0x4 << 14)
+#define NFC_CMD_CLE
On 2018/11/5 23:53, Boris Brezillon wrote:
On Fri, 2 Nov 2018 00:42:21 +0800
Jianxin Pan wrote:
+#define NFC_REG_CMD0x00
+#define NFC_CMD_DRD(0x8 << 14)
+#define NFC_CMD_IDLE (0xc << 14)
+#define NFC_CMD_DWR(0x4 << 14)
+#define NFC_CMD_CLE
On 2018/10/19 16:42, Boris Brezillon wrote:
On Fri, 19 Oct 2018 16:29:40 +0800
Liang Yang wrote:
On 2018/10/19 4:50, Boris Brezillon wrote:
On Thu, 18 Oct 2018 13:09:05 +0800
Jianxin Pan wrote:
+static int meson_nfc_buffer_init(struct mtd_info *mtd)
+{
+ struct nand_chip *nand
On 2018/10/19 16:42, Boris Brezillon wrote:
On Fri, 19 Oct 2018 16:29:40 +0800
Liang Yang wrote:
On 2018/10/19 4:50, Boris Brezillon wrote:
On Thu, 18 Oct 2018 13:09:05 +0800
Jianxin Pan wrote:
+static int meson_nfc_buffer_init(struct mtd_info *mtd)
+{
+ struct nand_chip *nand
On 2018/10/19 16:10, Boris Brezillon wrote:
On Fri, 19 Oct 2018 15:29:05 +0800
Liang Yang wrote:
How about defining that the HW returns an array of __le64 instead and then
define the following macros which you can use after converting in the
CPU endianness
#define
On 2018/10/19 16:10, Boris Brezillon wrote:
On Fri, 19 Oct 2018 15:29:05 +0800
Liang Yang wrote:
How about defining that the HW returns an array of __le64 instead and then
define the following macros which you can use after converting in the
CPU endianness
#define
On 2018/10/19 4:50, Boris Brezillon wrote:
On Thu, 18 Oct 2018 13:09:05 +0800
Jianxin Pan wrote:
+static int meson_nfc_buffer_init(struct mtd_info *mtd)
+{
+ struct nand_chip *nand = mtd_to_nand(mtd);
+ struct meson_nfc *nfc = nand_get_controller_data(nand);
+ static int
On 2018/10/19 4:50, Boris Brezillon wrote:
On Thu, 18 Oct 2018 13:09:05 +0800
Jianxin Pan wrote:
+static int meson_nfc_buffer_init(struct mtd_info *mtd)
+{
+ struct nand_chip *nand = mtd_to_nand(mtd);
+ struct meson_nfc *nfc = nand_get_controller_data(nand);
+ static int
On 2018/10/19 4:39, Boris Brezillon wrote:
On Thu, 18 Oct 2018 13:09:05 +0800
Jianxin Pan wrote:
+static int meson_nfc_calc_set_timing(struct meson_nfc *nfc,
+const struct nand_sdr_timings *timings)
+{
+ struct nand_timing *timing = >timing;
+
On 2018/10/19 4:39, Boris Brezillon wrote:
On Thu, 18 Oct 2018 13:09:05 +0800
Jianxin Pan wrote:
+static int meson_nfc_calc_set_timing(struct meson_nfc *nfc,
+const struct nand_sdr_timings *timings)
+{
+ struct nand_timing *timing = >timing;
+
On 2018/10/19 3:33, Boris Brezillon wrote:
On Thu, 18 Oct 2018 13:09:05 +0800
Jianxin Pan wrote:
From: Liang Yang
Add initial support for the Amlogic NAND flash controller which found
in the Meson-GXBB/GXL/AXG SoCs.
Signed-off-by: Liang Yang
Signed-off-by: Yixun Lan
Signed-off
On 2018/10/19 3:33, Boris Brezillon wrote:
On Thu, 18 Oct 2018 13:09:05 +0800
Jianxin Pan wrote:
From: Liang Yang
Add initial support for the Amlogic NAND flash controller which found
in the Meson-GXBB/GXL/AXG SoCs.
Signed-off-by: Liang Yang
Signed-off-by: Yixun Lan
Signed-off
On 2018/10/18 22:24, Boris Brezillon wrote:
On Thu, 18 Oct 2018 13:09:05 +0800
Jianxin Pan wrote:
+static int meson_nfc_exec_op(struct nand_chip *chip,
+const struct nand_operation *op, bool check_only)
+{
+ struct mtd_info *mtd = nand_to_mtd(chip);
+
On 2018/10/18 22:24, Boris Brezillon wrote:
On Thu, 18 Oct 2018 13:09:05 +0800
Jianxin Pan wrote:
+static int meson_nfc_exec_op(struct nand_chip *chip,
+const struct nand_operation *op, bool check_only)
+{
+ struct mtd_info *mtd = nand_to_mtd(chip);
+
On 9/28/2018 2:16 AM, Rob Herring wrote:
On Thu, Sep 20, 2018 at 04:50:48PM +0800, Jianxin Pan wrote:
From: Liang Yang
Add Amlogic NAND controller dt-bindings for Meson SoC,
Current this driver support GXBB/GXL/AXG platform.
Signed-off-by: Liang Yang
Signed-off-by: Yixun Lan
On 9/28/2018 2:16 AM, Rob Herring wrote:
On Thu, Sep 20, 2018 at 04:50:48PM +0800, Jianxin Pan wrote:
From: Liang Yang
Add Amlogic NAND controller dt-bindings for Meson SoC,
Current this driver support GXBB/GXL/AXG platform.
Signed-off-by: Liang Yang
Signed-off-by: Yixun Lan
On 9/27/2018 5:12 PM, Martin Blumenstingl wrote:
Hello Liang,
On Thu, Sep 27, 2018 at 10:19 AM Liang Yang wrote:
Hello Martin,
On 9/22/2018 11:32 PM, Martin Blumenstingl wrote:
Hello,
On Thu, Sep 20, 2018 at 10:51 AM Jianxin Pan wrote:
[snip]
+static int meson_nfc_clk_init(struct
On 9/27/2018 5:12 PM, Martin Blumenstingl wrote:
Hello Liang,
On Thu, Sep 27, 2018 at 10:19 AM Liang Yang wrote:
Hello Martin,
On 9/22/2018 11:32 PM, Martin Blumenstingl wrote:
Hello,
On Thu, Sep 20, 2018 at 10:51 AM Jianxin Pan wrote:
[snip]
+static int meson_nfc_clk_init(struct
Hello Martin,
On 9/22/2018 11:32 PM, Martin Blumenstingl wrote:
Hello,
On Thu, Sep 20, 2018 at 10:51 AM Jianxin Pan wrote:
[snip]
+static int meson_nfc_clk_init(struct meson_nfc *nfc)
+{
+ int ret;
+
+ /* request core clock */
+ nfc->core_clk = devm_clk_get(nfc->dev,
Hello Martin,
On 9/22/2018 11:32 PM, Martin Blumenstingl wrote:
Hello,
On Thu, Sep 20, 2018 at 10:51 AM Jianxin Pan wrote:
[snip]
+static int meson_nfc_clk_init(struct meson_nfc *nfc)
+{
+ int ret;
+
+ /* request core clock */
+ nfc->core_clk = devm_clk_get(nfc->dev,
Hi boric,
Thanks for your quick reply.
On 9/7/2018 8:19 PM, Boris Brezillon wrote:
On Fri, 7 Sep 2018 18:57:10 +0800
Jianxin Pan wrote:
From: Liang Yang
Add Amlogic NAND controller dt-bindings for Meson SoC,
Current this driver support GXBB/GXL/AXG platform.
Signed-off-by: Liang Yang
Hi boric,
Thanks for your quick reply.
On 9/7/2018 8:19 PM, Boris Brezillon wrote:
On Fri, 7 Sep 2018 18:57:10 +0800
Jianxin Pan wrote:
From: Liang Yang
Add Amlogic NAND controller dt-bindings for Meson SoC,
Current this driver support GXBB/GXL/AXG platform.
Signed-off-by: Liang Yang
On 8/29/2018 6:08 PM, Liang Yang wrote:
On 8/28/2018 9:26 PM, Boris Brezillon wrote:
On Tue, 28 Aug 2018 21:21:48 +0800
Liang Yang wrote:
Hi Boris,
On 8/24/2018 8:48 PM, Boris Brezillon wrote:
On Wed, 22 Aug 2018 22:08:42 +0800
Liang Yang wrote:
You have to wait tWB, that's for sure
On 8/29/2018 6:08 PM, Liang Yang wrote:
On 8/28/2018 9:26 PM, Boris Brezillon wrote:
On Tue, 28 Aug 2018 21:21:48 +0800
Liang Yang wrote:
Hi Boris,
On 8/24/2018 8:48 PM, Boris Brezillon wrote:
On Wed, 22 Aug 2018 22:08:42 +0800
Liang Yang wrote:
You have to wait tWB, that's for sure
On 8/28/2018 9:26 PM, Boris Brezillon wrote:
On Tue, 28 Aug 2018 21:21:48 +0800
Liang Yang wrote:
Hi Boris,
On 8/24/2018 8:48 PM, Boris Brezillon wrote:
On Wed, 22 Aug 2018 22:08:42 +0800
Liang Yang wrote:
You have to wait tWB, that's for sure.
we have a maximum 32 commands
On 8/28/2018 9:26 PM, Boris Brezillon wrote:
On Tue, 28 Aug 2018 21:21:48 +0800
Liang Yang wrote:
Hi Boris,
On 8/24/2018 8:48 PM, Boris Brezillon wrote:
On Wed, 22 Aug 2018 22:08:42 +0800
Liang Yang wrote:
You have to wait tWB, that's for sure.
we have a maximum 32 commands
Hi Boris,
On 8/24/2018 8:48 PM, Boris Brezillon wrote:
On Wed, 22 Aug 2018 22:08:42 +0800
Liang Yang wrote:
You have to wait tWB, that's for sure.
we have a maximum 32 commands fifo. when command is written into
NFC_REG_CMD, it doesn't mean that command is executing right now, maybe
Hi Boris,
On 8/24/2018 8:48 PM, Boris Brezillon wrote:
On Wed, 22 Aug 2018 22:08:42 +0800
Liang Yang wrote:
You have to wait tWB, that's for sure.
we have a maximum 32 commands fifo. when command is written into
NFC_REG_CMD, it doesn't mean that command is executing right now, maybe
Hi Boris,
There is a question below. please see my comments.
Thanks.
On 8/17/2018 9:56 PM, Boris Brezillon wrote:
On Fri, 17 Aug 2018 21:03:59 +0800
Liang Yang wrote:
Hi Boris,
On 2018/8/2 5:50, Boris Brezillon wrote:
Hi Yixun,
On Thu, 19 Jul 2018 17:46:12 +0800
Yixun Lan wrote:
I
Hi Boris,
There is a question below. please see my comments.
Thanks.
On 8/17/2018 9:56 PM, Boris Brezillon wrote:
On Fri, 17 Aug 2018 21:03:59 +0800
Liang Yang wrote:
Hi Boris,
On 2018/8/2 5:50, Boris Brezillon wrote:
Hi Yixun,
On Thu, 19 Jul 2018 17:46:12 +0800
Yixun Lan wrote:
I
Hi Boris,
On 8/17/2018 9:56 PM, Boris Brezillon wrote:
On Fri, 17 Aug 2018 21:03:59 +0800
Liang Yang wrote:
Hi Boris,
On 2018/8/2 5:50, Boris Brezillon wrote:
Hi Yixun,
On Thu, 19 Jul 2018 17:46:12 +0800
Yixun Lan wrote:
I haven't finished reviewing the driver yet (I'll try to do
Hi Boris,
On 8/17/2018 9:56 PM, Boris Brezillon wrote:
On Fri, 17 Aug 2018 21:03:59 +0800
Liang Yang wrote:
Hi Boris,
On 2018/8/2 5:50, Boris Brezillon wrote:
Hi Yixun,
On Thu, 19 Jul 2018 17:46:12 +0800
Yixun Lan wrote:
I haven't finished reviewing the driver yet (I'll try to do
Hi Boris,
On 2018/8/2 5:50, Boris Brezillon wrote:
Hi Yixun,
On Thu, 19 Jul 2018 17:46:12 +0800
Yixun Lan wrote:
I haven't finished reviewing the driver yet (I'll try to do that later
this week), but I already pointed a few things to fix/improve.
+
+static int meson_nfc_exec_op(struct
Hi Boris,
On 2018/8/2 5:50, Boris Brezillon wrote:
Hi Yixun,
On Thu, 19 Jul 2018 17:46:12 +0800
Yixun Lan wrote:
I haven't finished reviewing the driver yet (I'll try to do that later
this week), but I already pointed a few things to fix/improve.
+
+static int meson_nfc_exec_op(struct
Do we need to consider the chunk size when we adjust the value of
Striped_Cache_Szie for the MD-RAID5 array?
Liang
- Original Message -
From: "Justin Piszcz" <[EMAIL PROTECTED]>
To: "kyle" <[EMAIL PROTECTED]>
Cc: ;
Sent: Monday, January 22, 2007 5:18 AM
Subject: Re: change
Do we need to consider the chunk size when we adjust the value of
Striped_Cache_Szie for the MD-RAID5 array?
Liang
- Original Message -
From: Justin Piszcz [EMAIL PROTECTED]
To: kyle [EMAIL PROTECTED]
Cc: linux-raid@vger.kernel.org; linux-kernel@vger.kernel.org
Sent: Monday, January
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