s: 973a28677e39 ("PCI: tegra: Convert to MSI domains")
> Signed-off-by: Marc Zyngier
> Cc: Lorenzo Pieralisi
> Cc: Bjorn Helgaas
> Cc: Thierry Reding
> ---
> drivers/pci/controller/pci-tegra.c | 8 +++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
Squash
On Tue, 20 Apr 2021 14:17:16 +0800, Jianjun Wang wrote:
> These series patches add pcie-mediatek-gen3.c and dt-bindings file to
> support new generation PCIe controller.
>
> Changes in v10:
> 1. Fix the subject line format in commit message;
> 2. Use EXPORT_SYMBOL_GPL() to export
On Fri, Apr 16, 2021 at 02:21:00PM -0500, Bjorn Helgaas wrote:
> On Wed, Mar 24, 2021 at 11:05:03AM +0800, Jianjun Wang wrote:
> > These series patches add pcie-mediatek-gen3.c and dt-bindings file to
> > support new generation PCIe controller.
>
> Incidental: b4 doesn't work on this thread, I
On Thu, 15 Apr 2021 16:32:57 +0800, Jiapeng Chong wrote:
> Fix the following clang warning:
>
> drivers/pci/controller/dwc/pcie-intel-gw.c:84:19: warning: unused
> function 'pcie_app_rd' [-Wunused-function].
Applied to pci/dwc, thanks!
[1/1] PCI: dwc/intel-gw: Remove unused function
On Thu, 25 Mar 2021 15:26:04 +0800, Jisheng Zhang wrote:
> If the host which makes use of IP's integrated MSI Receiver losts
> power during suspend, we need to reinit the RC and MSI Receiver in
> resume. But after we move dw_pcie_msi_init() into the core, we have no
> API to do so. Usually the dwc
On Fri, 9 Apr 2021 15:57:48 +0800, Chen Hui wrote:
> There is a error message within devm_ioremap_resource
> already, so remove the dev_err call to avoid redundant
> error message.
Applied to pci/altera-msi, thanks!
[1/1] PCI: altera-msi: Remove redundant dev_err call in altera_msi_probe()
On Wed, 31 Mar 2021 16:40:12 +0800, Yang Yingliang wrote:
> Add the missing destroy_workqueue() before return from
> pci_epf_test_init() in the error handling case and add
> destroy_workqueue() in pci_epf_test_exit().
Applied to pci/endpoint, thanks!
[1/1] PCI: endpoint: Fix missing
On Fri, 26 Mar 2021 19:09:09 +, Colin King wrote:
> The pointer dev is being initialized with a value that is
> never read and it is being updated later with a new value. The
> initialization is redundant and can be removed.
Applied to pci/endpoint, thanks!
[1/1] PCI: endpoint: Remove
On Wed, Mar 24, 2021 at 10:09:42AM +0100, Pali Rohár wrote:
> On Wednesday 24 March 2021 11:05:05 Jianjun Wang wrote:
> > This interface will be used by PCI host drivers for PIO translation,
> > export it to support compiling those drivers as kernel modules.
> >
> > Signed-off-by: Jianjun Wang
>
On Fri, Apr 09, 2021 at 10:17:12AM +, Rahul Tanwar wrote:
> On 9/4/2021 4:40 am, Martin Blumenstingl wrote:
> > This email was sent from outside of MaxLinear.
> >
> > Hi Lorenzo,
> >
> > On Tue, Mar 23, 2021 at 12:36 PM Lorenzo Pieralisi
> > wrote:
&
On Tue, 6 Apr 2021 17:26:28 +0800, Greentime Hu wrote:
> This patchset includes SiFive FU740 PCIe host controller driver. We also
> add pcie_aux clock and pcie_power_on_reset controller to prci driver for
> PCIe driver to use it.
>
> This is tested with e1000e: Intel(R) PRO/1000 Network Card, AMD
On Thu, 8 Apr 2021 15:26:58 +0800, Dinghao Liu wrote:
> pm_runtime_get_sync() will increase the runtime PM counter
> even it returns an error. Thus a pairing decrement is needed
> to prevent refcount leak. Fix this by replacing this API with
> pm_runtime_resume_and_get(), which will not change the
On Tue, Apr 06, 2021 at 05:26:28PM +0800, Greentime Hu wrote:
> This patchset includes SiFive FU740 PCIe host controller driver. We also
> add pcie_aux clock and pcie_power_on_reset controller to prci driver for
> PCIe driver to use it.
>
> This is tested with e1000e: Intel(R) PRO/1000 Network
On Mon, 22 Feb 2021 14:17:31 +0530, Bharat Kumar Gogada wrote:
> Add support for routing PCIe DMA traffic coherently when
> Cache Coherent Interconnect (CCI) is enabled in the system.
> The "dma-coherent" property is used to determine if CCI is enabled
> or not.
> Refer to
On Fri, 12 Mar 2021 15:45:53 -0500, Jim Quinlan wrote:
> v5 -- Improved (I hope) commit description (Bjorn).
>-- Rnamed error labels (Krzyszt).
>-- Fixed typos.
>
> v4 -- does not rely on a pending commit, unlike v3.
>
> v3 -- discard commit from v2; instead rely on the new function
>
On Fri, Mar 12, 2021 at 03:45:54PM -0500, Jim Quinlan wrote:
> This driver may use one of two resets controllers. Keep them in separate
> variables to keep things simple. The reset controller "rescal" is shared
> between the AHCI driver and the PCIe driver for the BrcmSTB 7216 chip. Use
>
[+ Rob, Robin]
On Mon, Feb 22, 2021 at 02:17:31PM +0530, Bharat Kumar Gogada wrote:
> Add support for routing PCIe DMA traffic coherently when
> Cache Coherent Interconnect (CCI) is enabled in the system.
> The "dma-coherent" property is used to determine if CCI is enabled
> or not.
> Refer to
On Tue, 30 Mar 2021 16:11:31 +0100, Marc Zyngier wrote:
> This is a respin of the series described at [1].
>
> * From v2 [2]:
> - Fixed the Xilinx driver, thanks to Bharat for testing it
> - Dropped the no_msi attribute, and solely rely on msi_domain, which
> has the same effect for the
On Thu, Apr 01, 2021 at 11:38:19AM +0100, Marc Zyngier wrote:
> On Thu, 01 Apr 2021 11:19:57 +0100,
> Lorenzo Pieralisi wrote:
> >
> > On Tue, Mar 30, 2021 at 04:11:34PM +0100, Marc Zyngier wrote:
> >
> > [...]
> >
> > > +static void rcar_compose_
On Tue, Mar 30, 2021 at 04:11:34PM +0100, Marc Zyngier wrote:
[...]
> +static void rcar_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
> +{
> + struct rcar_msi *msi = irq_data_get_irq_chip_data(data);
> + unsigned long pa = virt_to_phys(msi);
>
> - hwirq =
On Tue, Mar 30, 2021 at 02:19:26PM -0500, Bjorn Helgaas wrote:
> On Sun, Mar 28, 2021 at 10:41:18PM +0800, Dejin Zheng wrote:
> > It has a wrong modification to the xgene driver by the commit
> > e2dcd20b1645a. it use devm_platform_ioremap_resource_byname() to
> > simplify codes and remove the res
On Tue, Mar 30, 2021 at 04:11:33PM +0100, Marc Zyngier wrote:
> A long cargo-culted behaviour of PCI drivers is to allocate memory
> to obtain an address that is fed to the controller as the MSI
> capture address (i.e. the MSI doorbell).
>
> But there is no actual requirement for this address to
On Tue, Mar 30, 2021 at 12:05:46PM +0100, Lorenzo Pieralisi wrote:
> On Tue, Mar 30, 2021 at 11:33:13AM +0100, Marc Zyngier wrote:
> > [+Lorenzo, +Julien on an actual email address]
> >
> > On Tue, 30 Mar 2021 11:06:19 +0100,
> > Lecopzer Chen wrote:
> >
On Tue, Mar 30, 2021 at 11:33:13AM +0100, Marc Zyngier wrote:
> [+Lorenzo, +Julien on an actual email address]
>
> On Tue, 30 Mar 2021 11:06:19 +0100,
> Lecopzer Chen wrote:
> >
> > When pseudo-NMI enabled, register_nmi() set priority of specific IRQ
> > by byte ops, and this doesn't work in
On Mon, Mar 29, 2021 at 09:50:13AM -0700, Florian Fainelli wrote:
> On 3/29/21 9:10 AM, Lorenzo Pieralisi wrote:
> > On Fri, Mar 12, 2021 at 03:45:55PM -0500, Jim Quinlan wrote:
> >> The Broadcom STB PCIe RC uses a reset control "rescal" for certain chips.
> >
On Fri, Mar 12, 2021 at 03:45:55PM -0500, Jim Quinlan wrote:
> The Broadcom STB PCIe RC uses a reset control "rescal" for certain chips.
> The "rescal" implements a "pulse reset" so using assert/deassert is wrong
> for this device. Instead, we use reset/rearm. We need to use rearm so
> that we
On Fri, Mar 12, 2021 at 03:45:55PM -0500, Jim Quinlan wrote:
> The Broadcom STB PCIe RC uses a reset control "rescal" for certain chips.
> The "rescal" implements a "pulse reset" so using assert/deassert is wrong
> for this device. Instead, we use reset/rearm. We need to use rearm so
> that we
On Sun, 28 Mar 2021 22:41:18 +0800, Dejin Zheng wrote:
> It has a wrong modification to the xgene driver by the commit
> e2dcd20b1645a. it use devm_platform_ioremap_resource_byname() to
> simplify codes and remove the res variable, But the following code
> needs to use this res variable, So after
On Wed, 24 Mar 2021 15:46:09 +0530, Shradha Todi wrote:
> get_features ops of pci_epc_ops may return NULL, causing NULL pointer
> dereference in pci_epf_test_alloc_space function. Let us add a check for
> pci_epc_feature pointer in pci_epf_test_bind before we access it to avoid
> any such NULL
On Tue, Jan 26, 2021 at 10:53:51PM +, Will Deacon wrote:
> On Tue, Jan 26, 2021 at 11:08:31AM -0600, Vikram Sethi wrote:
> > On 1/22/2021 1:48 PM, Will Deacon wrote:
> > > On Fri, Jan 08, 2021 at 10:32:16AM +, Lorenzo Pieralisi wrote:
> > >> On Thu, Jan 07,
On Tue, Mar 23, 2021 at 06:09:36PM +, Marc Zyngier wrote:
> Hi Robin,
>
> On Tue, 23 Mar 2021 11:45:02 +,
> Robin Murphy wrote:
> >
> > On 2021-03-22 18:46, Marc Zyngier wrote:
> > > The new 'no_msi' attribute solves the problem of advertising the lack
> > > of MSI capability for host
On Wed, Jan 06, 2021 at 02:55:40PM +0100, Martin Blumenstingl wrote:
> The legacy PCI interrupt lines need to be enabled using PCIE_APP_IRNEN
> bits 13 (INTA), 14 (INTB), 15 (INTC) and 16 (INTD). The old code however
> was taking (for example) "13" as raw value instead of taking BIT(13).
> Define
On Mon, Sep 07, 2020 at 01:37:54PM +0800, Zhiqiang Hou wrote:
> From: Hou Zhiqiang
>
> This patch series is to add PCIe power management support for NXP
> Layerscape platfroms.
>
> Hou Zhiqiang (7):
> PCI: dwc: Fix a bug of the case dw_pci->ops is NULL
> PCI: layerscape: Change to use the
On Tue, Jan 19, 2021 at 03:25:10PM +0530, Shradha Todi wrote:
> > -Original Message-
> > From: Leon Romanovsky
> > Subject: Re: [PATCH v4] PCI: endpoint: Fix NULL pointer dereference for -
> > >get_features()
> >
> > On Tue, Jan 12, 2021 at 07:32:25PM +0530, Shradha Todi wrote:
> > >
On Mon, 8 Mar 2021 12:05:46 +0530, Kishon Vijay Abraham I wrote:
> AM64 uses the same PCIe controller as in J7200, however AM642 EVM
> doesn't have a clock generator (unlike J7200 base board). Here
> the clock from the SERDES has to be routed to the PCIE connector.
> This series provides an option
On Mon, 8 Feb 2021 15:23:01 +0100, Geert Uytterhoeven wrote:
> - Drop the dependency on PCI, as this is implied by the dependency on
> PCI_MSI_IRQ_DOMAIN,
> - Drop the dependencies on OF and ARM64, as the driver compiles fine
> without OF and/or on other architectures,
> - The
On Thu, 31 Dec 2020 11:25:39 +0800, Wesley Sheng wrote:
> In config PCIE_TEGRA194_EP the mode incorrectly referred to
> host mode.
Applied to pci/tegra, thanks!
[1/1] PCI: tegra: Fix typo for PCIe endpoint mode in Tegra194
https://git.kernel.org/lpieralisi/pci/c/10739e2a5e
Thanks,
Lorenzo
On Mon, Mar 22, 2021 at 06:03:57PM +, Lorenzo Pieralisi wrote:
> On Mon, 25 Jan 2021 12:48:03 +0800, Zhiqiang Hou wrote:
> > In the dw_pcie_ep_init(), it depends on the detected iATU region
> > numbers to allocate the in/outbound window management bit map.
> > It f
On Mon, 25 Jan 2021 12:48:03 +0800, Zhiqiang Hou wrote:
> In the dw_pcie_ep_init(), it depends on the detected iATU region
> numbers to allocate the in/outbound window management bit map.
> It fails after the commit 281f1f99cf3a ("PCI: dwc: Detect number
> of iATU windows").
>
> So this patch
On Wed, 17 Mar 2021 18:45:18 +0530, Kishon Vijay Abraham I wrote:
> Both TI's AM65x (K3) and TI's K2 PCIe driver are implemented in
> pci-keystone. However Only K2 PCIe driver should use it's own pci_ops
> for configuration space accesses. But commit 10a797c6e54a
> ("PCI: dwc: keystone: Use
/patch/20210311033745.1547044-1...@linux.com
For the future email exchanges: don't top-post please.
Thanks,
Lorenzo
> Thanks.
> Roy
>
> -Original Message-----
> From: Lorenzo Pieralisi
>
> On Sun, Mar 07, 2021 at 07:36:57PM +0100, Krzysztof Wilczyński wrote:
> > Hi,
> &g
On Wed, 3 Mar 2021 15:22:02 +0100, Pali Rohár wrote:
> IRQ domain alloc function should return zero on success. Non-zero value
> indicates failure.
Applied to pci/iproc, thanks!
[1/1] PCI: iproc: Fix return value of iproc_msi_irq_domain_alloc()
On Sun, 7 Feb 2021 23:16:04 +0100, Rikard Falkeborn wrote:
> The only usage of them is to assign their address to the 'ops' field in
> the pcie_port and the dw_pcie_ep structs, both which are pointers to
> const. Make them const to allow the compiler to put them in read-only
> memory.
Applied to
On Sun, Mar 07, 2021 at 07:36:57PM +0100, Krzysztof Wilczyński wrote:
> Hi,
>
> [...]
> > I would request NXP maintainers to take this patch, rewrite it as
> > Bjorn requested and resend it as fast as possible, this is a very
> > relevant fix.
> [...]
>
> Looking at the state of the
On Thu, Feb 25, 2021 at 03:10:13PM +, Marc Zyngier wrote:
> In anticipation of the removal of the msi_controller structure, convert
> the ancient xilinx host controller driver to MSI domains.
>
> We end-up with the usual two domain structure, the top one being a
> generic PCI/MSI domain, the
On Thu, Feb 25, 2021 at 03:10:13PM +, Marc Zyngier wrote:
> In anticipation of the removal of the msi_controller structure, convert
> the ancient xilinx host controller driver to MSI domains.
>
> We end-up with the usual two domain structure, the top one being a
> generic PCI/MSI domain, the
om Saeger
> ---
> Documentation/arm64/acpi_object_usage.rst | 10 +-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
Acked-by: Lorenzo Pieralisi
> diff --git a/Documentation/arm64/acpi_object_usage.rst
> b/Documentation/arm64/acpi_object_usage.rst
> index 377e9d224db0..0609da7
[+ Al, Ard]
On Thu, Mar 18, 2021 at 10:44:33AM +, Will Deacon wrote:
> [+Lorenzo]
>
> On Tue, Mar 16, 2021 at 12:50:41PM -0600, Tom Saeger wrote:
> > In commit 94bccc340710 ("iscsi_ibft: make ISCSI_IBFT dependson ACPI instead
> > of ISCSI_IBFT_FIND") Kconfig was disentangled to make
On Wed, Mar 17, 2021 at 02:04:36PM +, Marc Zyngier wrote:
> Hi Lorenzo,
>
> Wed, 17 Mar 2021 10:07:19 +,
> Lorenzo Pieralisi wrote:
> >
> > GIC CPU interfaces versions predating GIC v4.1 were not built to
> > accommodate vINTID within the vSGI
the GIC CPUIF version by reading the SYS_ID_AA64_PFR0_EL1.
Disable vSGIs if a CPUIF version < 4.1 is detected to prevent using
vSGIs on systems where they may misbehave.
Signed-off-by: Lorenzo Pieralisi
Cc: Marc Zyngier
---
arch/arm64/kvm/vgic/vgic-mmio-v3.c | 4 ++--
drivers/irqchip/irq-gic
.0 to GIC v4.1.
Cc: Marc Zyngier
Lorenzo Pieralisi (1):
irqchip/gic-v4.1: Disable vSGI upon (GIC CPUIF < v4.1) detection
arch/arm64/kvm/vgic/vgic-mmio-v3.c | 4 ++--
drivers/irqchip/irq-gic-v4.c | 27 +--
include/linux/irqchip/arm-gic-v4.h | 2 ++
3 files
On Mon, Mar 08, 2021 at 07:22:57PM +, Marc Zyngier wrote:
> Hi Lorenzo,
>
> On Tue, 02 Mar 2021 10:27:44 +,
> Lorenzo Pieralisi wrote:
> >
> > GIC CPU interfaces versions predating GIC v4.1 were not built to
> > accommodate vINTID within the vSGI
the GIC CPUIF version by reading the SYS_ID_AA64_PFR0_EL1.
Disable vSGIs if a CPUIF version < 4.1 is detected to prevent using
vSGIs on systems where they may misbehave.
Signed-off-by: Lorenzo Pieralisi
Cc: Marc Zyngier
---
arch/arm64/kvm/vgic/vgic-mmio-v3.c | 4 ++--
arch/arm64/kv
nce the protocol between the GIC redistributor and
the GIC CPUIF was not changed from GIC v4.0 to GIC v4.1.
Lorenzo Pieralisi (1):
irqchip/gic-v4.1: Disable vSGI upon (GIC CPUIF < v4.1) detection
arch/arm64/kvm/vgic/vgic-mmio-v3.c | 4 ++--
arch/arm64/kvm/vgic/vgic-v3.c | 3 ++-
d
On Thu, Feb 18, 2021 at 12:43:30PM -0500, Jon Masters wrote:
> Hi Bjorn, all,
>
> On Thu, Jan 28, 2021 at 6:31 PM Bjorn Helgaas wrote:
>
> On Tue, Jan 26, 2021 at 10:46:04AM -0600, Jeremy Linton wrote:
>
>
>
> > Does that mean its open season for ECAM quirks, and we can expect
>
On Wed, Feb 10, 2021 at 07:53:45AM +, Wei Yongjun wrote:
> It's not necessary to free memory allocated with devm_kzalloc
> and using kfree leads to a double free.
>
> Fixes: 363baf7d6051 ("NTB: Add support for EPF PCI-Express Non-Transparent
> Bridge")
Squashed it in the commit it is fixing
On Fri, Feb 12, 2021 at 12:00:15PM +, Lorenzo Pieralisi wrote:
> On Thu, Feb 11, 2021 at 03:33:52PM +, Vincenzo Frascino wrote:
> > When MTE async mode is enabled TFSR_EL1 contains the accumulative
> > asynchronous tag check faults for EL1 and EL0.
> >
> >
hange the state of the register resulting in
> a spurious tag check fault report.
>
> Report asynchronous tag faults before suspend and clear the TFSR_EL1
> register after resume to prevent this to happen.
>
> Cc: Catalin Marinas
> Cc: Will Deacon
> Cc: Lorenzo Pieral
On Tue, 9 Feb 2021 15:46:20 +0100, Nadeem Athani wrote:
> Cadence controller will not initiate autonomous speed change if strapped
> as Gen2. The Retrain Link bit is set as quirk to enable this speed change.
> Adding a quirk flag for defective IP. In future IP revisions this will not
> be
On Tue, Feb 09, 2021 at 11:55:33AM +, Catalin Marinas wrote:
> On Mon, Feb 08, 2021 at 04:56:16PM +, Vincenzo Frascino wrote:
> > When MTE async mode is enabled TFSR_EL1 contains the accumulative
> > asynchronous tag check faults for EL1 and EL0.
> >
> > During the suspend/resume
hange the state of the register resulting in
> a spurious tag check fault report.
>
> Save/restore the state of the TFSR_EL1 register during the
> suspend/resume operations to prevent this to happen.
>
> Cc: Catalin Marinas
> Cc: Will Deacon
> Cc: Lorenzo Pieral
On Wed, Dec 30, 2020 at 01:05:15PM +0100, Nadeem Athani wrote:
> Cadence controller will not initiate autonomous speed change if strapped
> as Gen2. The Retrain Link bit is set as quirk to enable this speed change.
>
> Signed-off-by: Nadeem Athani
> ---
>
On Thu, Feb 04, 2021 at 07:15:39PM +0530, Kishon Vijay Abraham I wrote:
> Hi Lorenzo,
>
> On 04/02/21 3:28 pm, Lorenzo Pieralisi wrote:
> > On Tue, Feb 02, 2021 at 12:12:55PM -0800, Randy Dunlap wrote:
> >> The pci-epf-ntb driver uses configfs APIs, so it should de
On Tue, 2 Feb 2021 12:58:38 +0530, Shradha Todi wrote:
> The size parameter is unsigned long type which can accept size > 4GB. In
> that case, the upper limit address must be programmed. Add support to
> program the upper limit address and set INCREASE_REGION_SIZE in case size >
> 4GB.
Applied to
t+0x1b): undefined reference to
> `config_group_init_type_name'
>
> Fixes: 7dc64244f9e9 ("PCI: endpoint: Add EP function driver to provide NTB
> functionality")
>
> Signed-off-by: Randy Dunlap
> Cc: Kishon Vijay Abraham I
> Cc: Lorenzo Pieralisi
> Cc: linu
On Tue, 2 Feb 2021 01:27:52 +0530, Kishon Vijay Abraham I wrote:
> This series is about implementing SW defined Non-Transparent Bridge (NTB)
> using multiple endpoint (EP) instances. This series has been tested using
> 2 endpoint instances in J7 connected to J7 board on one end and DRA7 board
> on
On Wed, Jan 06, 2021 at 04:20:10PM +0530, Shradha Todi wrote:
> The size parameter is unsigned long type which can accept size > 4GB. In
> that case, the upper limit address must be programmed. Add support to
> program the upper limit address and set INCREASE_REGION_SIZE in case size >
> 4GB.
>
>
On Wed, 6 Jan 2021 16:15:00 +0530, Shradha Todi wrote:
> Since outbound iATU permits size to be greater than 4GB for which the
> support is also available, allow EP function to send u64 size instead of
> truncating to u32.
Applied to pci/dwc, thanks!
[1/1] PCI: dwc: Change size to u64 for EP
On Fri, Jan 29, 2021 at 06:12:56PM +0530, Kishon Vijay Abraham I wrote:
> This series is about implementing SW defined Non-Transparent Bridge (NTB)
> using multiple endpoint (EP) instances. This series has been tested using
> 2 endpoint instances in J7 connected to J7 board on one end and DRA7
On Fri, Jan 22, 2021 at 07:48:52PM +0530, Kishon Vijay Abraham I wrote:
> Hi Bjorn,
>
> On 20/01/21 12:04 am, Bjorn Helgaas wrote:
> > On Mon, Jan 04, 2021 at 08:58:53PM +0530, Kishon Vijay Abraham I wrote:
> >> Add specification for the *PCI NTB* function device. The endpoint function
> >>
On Thu, 28 Jan 2021 14:42:13 +0800, Jisheng Zhang wrote:
> Some designware based device driver especially host only driver may
> work well with the default read_dbi/write_dbi/link_up implementation
> in pcie-designware.c, thus remove the assumption to simplify those
> drivers.
>
> Since v2:
> -
14 ++++++++--
> 1 file changed, 12 insertions(+), 2 deletions(-)
Acked-by: Lorenzo Pieralisi
> diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c
> index d4eac6d7e9fb..2494138a6905 100644
> --- a/drivers/acpi/arm64/iort.c
> +++ b/drivers/acpi/arm64/iort.c
> @@ -1107
On Wed, Jan 20, 2021 at 11:52:46AM +0100, Michael Walle wrote:
> fw_devlink will defer the probe until all suppliers are ready. We can't
> use builtin_platform_driver_probe() because it doesn't retry after probe
> deferral. Convert it to builtin_platform_driver().
>
> Fixes: e590474768f1 ("driver
On Wed, 20 Jan 2021 11:52:46 +0100, Michael Walle wrote:
> fw_devlink will defer the probe until all suppliers are ready. We can't
> use builtin_platform_driver_probe() because it doesn't retry after probe
> deferral. Convert it to builtin_platform_driver().
Applied to pci/dwc, thanks!
[1/1]
On Fri, 22 Jan 2021 00:23:17 +0800, Chen-Yu Tsai wrote:
> This is v4 of my Nanopi M4B series.
>
> Changes since v3 include:
>
> - Directly return dev_err_probe() instead of having a separate return
> statement
>
> [...]
Applied to pci/rockchip (dropped dts patches 3-4), thanks!
[1/2]
On Wed, Jan 20, 2021 at 08:28:36PM +0100, Michael Walle wrote:
> [RESEND, fat-fingered the buttons of my mail client and converted
> all CCs to BCCs :(]
>
> Am 2021-01-20 20:02, schrieb Saravana Kannan:
> > On Wed, Jan 20, 2021 at 6:24 AM Rob Herring wrote:
> > >
> > > On Wed, Jan 20, 2021 at
On Wed, 20 Jan 2021 06:37:45 -0800, Pan Bian wrote:
> Also drop the reference count of the node on error path.
Applied to pci/xilinx, thanks!
[1/1] PCI: xilinx-cpm: Fix reference count leak on error path
https://git.kernel.org/lpieralisi/pci/c/ae191d2e51
Thanks,
Lorenzo
On Fri, Nov 20, 2020 at 07:16:11PM +0800, Jisheng Zhang wrote:
> Some designware based device driver especially host only driver may
> work well with the default read_dbi/write_dbi/link_up implementation
> in pcie-designware.c, thus remove the assumption to simplify those
> drivers.
>
> Since v1:
On Wed, 20 Jan 2021 16:07:29 +0100, Arnd Bergmann wrote:
> The tango platform is getting removed, so the driver is no
> longer needed.
Applied to pci/tango, thanks!
[1/1] PCI: Remove tango host controller driver
https://git.kernel.org/lpieralisi/pci/c/de9427ca87
Thanks,
Lorenzo
On Fri, 15 Jan 2021 22:15:32 +0100, Martin Kaiser wrote:
> Call irq_set_chained_handler_and_data() to clear the chained handler
> and the handler's data under irq_desc->lock.
>
> See also 2cf5a03cb29d ("PCI/keystone: Fix race in installing chained
> IRQ handler").
Applied to pci/misc, thanks!
On Tue, 29 Dec 2020 17:08:48 +, Lad Prabhakar wrote:
> All the defconfig files have replaced PCIE_RCAR config option with
> PCIE_RCAR_HOST config option which built the same driver, so we can
> now safely drop PCIE_RCAR config option.
Applied to pci/misc, thanks!
[1/1] PCI: Drop PCIE_RCAR
On Mon, 4 Jan 2021 20:58:52 +0530, Kishon Vijay Abraham I wrote:
> This series is about implementing SW defined Non-Transparent Bridge (NTB)
> using multiple endpoint (EP) instances. This series has been tested using
> 2 endpoint instances in J7 connected to J7 board on one end and DRA7 board
> on
On Fri, 15 Jan 2021 22:24:33 +0100, Martin Kaiser wrote:
> Call irq_set_chained_handler_and_data() to clear the chained handler
> and the handler's data under irq_desc->lock.
>
> See also 2cf5a03cb29d ("PCI/keystone: Fix race in installing chained
> IRQ handler").
Applied to pci/misc, thanks!
On Mon, 19 Oct 2020 18:55:55 +0200, Ansuel Smith wrote:
> The use of PHY_REFCLK_USE_PAD introduced a regression for apq8064
> devices. It was tested that while apq doesn't require the padding, ipq
> SoC must use it or the kernel hangs on boot.
Applied to pci/dwc, thanks!
[1/1] PCI: qcom: use
On Mon, 26 Oct 2020 13:14:47 +0800, Zhiqiang Hou wrote:
> Add PCIe Endpoint mode compatible string "fsl,lx2160ar2-pcie-ep"
Applied to pci/dwc, thanks!
[1/2] dt-bindings: pci: layerscape-pci: Add compatible strings for LX2160A rev2
https://git.kernel.org/lpieralisi/pci/c/514a39a653
[2/2]
On Mon, Oct 19, 2020 at 06:55:55PM +0200, Ansuel Smith wrote:
> The use of PHY_REFCLK_USE_PAD introduced a regression for apq8064
> devices. It was tested that while apq doesn't require the padding, ipq
> SoC must use it or the kernel hangs on boot.
>
> Fixes: de3c4bf6489 ("PCI: qcom: Add support
On Wed, Oct 28, 2020 at 05:15:49PM +0800, Qinglang Miao wrote:
> Add the missing destroy_workqueue() before return from
> pci_epf_test_init() in the error handling case.
>
> Signed-off-by: Qinglang Miao
> ---
> drivers/pci/endpoint/functions/pci-epf-test.c | 1 +
> 1 file changed, 1
On Wed, 30 Dec 2020 22:27:23 +0530, Vidya Sagar wrote:
> DesignWare core has a TLP digest (TD) override bit in one of the control
> registers of ATU. This bit also needs to be programmed for proper ECRC
> functionality. This is currently identified as an issue with DesignWare
> IP version 4.90a.
On Wed, Jan 06, 2021 at 01:07:22PM -0600, Bjorn Helgaas wrote:
> On Wed, Dec 16, 2020 at 09:19:44PM +0800, Zheng Yongjun wrote:
> > Replace a comma between expression statements by a semicolon.
>
> Looks like a good fix, but read this about the changelog title:
>
>
On Thu, Jan 07, 2021 at 04:05:48PM -0500, Jon Masters wrote:
> Hi will, everyone,
>
> On 1/7/21 1:14 PM, Will Deacon wrote:
>
> > On Mon, Jan 04, 2021 at 10:57:35PM -0600, Jeremy Linton wrote:
> > > Given that most arm64 platform's PCI implementations needs quirks
> > > to deal with problematic
On Fri, Dec 11, 2020 at 08:49:16AM -0600, Rob Herring wrote:
> On Fri, Dec 11, 2020 at 7:58 AM Vidya Sagar wrote:
> >
> > Hi Lorenzo,
> > Apologies to bug you, but wondering if you have any further comments on
> > this patch that I need to take care of?
>
> You can check the status of your
On Thu, 10 Dec 2020 18:19:13 +0530, Kishon Vijay Abraham I wrote:
> Patch series adds PCIe binding for J7200 and and fixes
> "ti,syscon-pcie-ctrl" applicable to both J721E and J7200.
>
> All the four patches here have got Acks from Rob Herring.
>
> Ack for "dt-bindings: pci: ti,j721e: Fix
On Tue, 17 Nov 2020 22:23:12 +0530, Vidya Sagar wrote:
> Set DMA mask to 32-bit while allocating the MSI target address so that
> the address is usable for both 32-bit and 64-bit MSI capable devices.
> Throw a warning if it fails to set the mask to 32-bit to alert that
> devices that are only
On Tue, 8 Dec 2020 17:43:59 +0530, Manivannan Sadhasivam wrote:
> This series adds PCIe support for Qualcomm SM8250 SoC with relevant PHYs.
> There are 3 PCIe instances on this SoC each with different PHYs. The PCIe
> controller and PHYs are mostly comaptible with the ones found on SDM845
> SoC,
On Tue, Dec 08, 2020 at 04:15:57PM +0530, Manivannan Sadhasivam wrote:
> Hi Lorenzo,
>
> On Tue, Dec 08, 2020 at 09:47:12AM +, Lorenzo Pieralisi wrote:
> > On Tue, Oct 27, 2020 at 10:30:28PM +0530, Manivannan Sadhasivam wrote:
> > > Hello,
> > >
&g
On Tue, Oct 27, 2020 at 10:30:28PM +0530, Manivannan Sadhasivam wrote:
> Hello,
>
> This series adds PCIe support for Qualcomm SM8250 SoC with relevant PHYs.
> There are 3 PCIe instances on this SoC each with different PHYs. The PCIe
> controller and PHYs are mostly comaptible with the ones found
On Thu, 3 Dec 2020 19:04:46 +0530, Vidya Sagar wrote:
> This series of patches do some enhancements and some bug fixes to the
> Tegra194 PCIe platform driver like
> - Fix Vendor-ID corruption
> - Update DWC IP version
> - Continue with uninitialization sequence even if parts fail
> - Check return
On Wed, 2 Dec 2020 19:46:59 +0100, Pali Rohár wrote:
> It is not HW bug or workaround for some cards but it is requirement by PCI
> Express spec. After fundamental reset is needed 100ms delay prior enabling
> link training. So update comment in code to reflect this requirement.
Applied to
On Tue, Dec 01, 2020 at 03:24:24PM +0100, Thierry Reding wrote:
> On Mon, Nov 30, 2020 at 12:10:07PM +0000, Lorenzo Pieralisi wrote:
> > On Mon, Nov 09, 2020 at 10:49:35PM +0530, Vidya Sagar wrote:
> > > Currently the driver checks for error value of dif
On Mon, Nov 30, 2020 at 08:44:55PM -0800, Randy Dunlap wrote:
> On 11/30/20 12:36 AM, Stephen Rothwell wrote:
> > Hi all,
> >
> > Changes since 20201127:
> >
>
> on x86_64:
>
> WARNING: unmet direct dependencies detected for PCIE_DW_HOST
> Depends on [n]: PCI [=y] && PCI_MSI_IRQ_DOMAIN [=n]
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