Add new rx-tx-swap property to allow for RX & TX pin swapping.
Signed-off-by: Martin Devera
Acked-by: Fabrice Gasnier
Reviewed-by: Rob Herring
---
v8:
- rebase to the latest tty-next
v7:
- fix yaml linter warning
v6:
- add version changelog
v5:
- yaml fixes based on Rob Her
STM32 F7/H7 usarts supports RX & TX pin swapping.
Add option to turn it on.
Tested on STM32MP157.
Signed-off-by: Martin Devera
Acked-by: Fabrice Gasnier
---
v8:
- rebase to the latest tty-next
v6:
- add version changelog
v4:
- delete superfluous has_swap=false
v3:
- add has_
STM32 F7/H7 usarts supports RX & TX pin swapping.
Add option to turn it on.
Tested on STM32MP157.
Signed-off-by: Martin Devera
Acked-by: Fabrice Gasnier
---
v6:
- add version changelog
v4:
- delete superfluous has_swap=false
v3:
- add has_swap to stm32_usart_info (because F4
Add new rx-tx-swap property to allow for RX & TX pin swapping.
Signed-off-by: Martin Devera
Acked-by: Fabrice Gasnier
---
v7:
- fix yaml linter warning
v6:
- add version changelog
v5:
- yaml fixes based on Rob Herring comments
- add serial.yaml reference
- move compatible
On 3/12/21 3:56 PM, Martin DEVERA wrote:
On 3/12/21 3:23 PM, Rob Herring wrote:
On Fri, 12 Mar 2021 11:27:12 +0100, Martin Devera wrote:
Add new rx-tx-swap property to allow for RX & TX pin swapping.
Signed-off-by: Martin Devera
Acked-by: Fabrice Gasnier
---
v6:
- add version chang
On 3/12/21 3:23 PM, Rob Herring wrote:
On Fri, 12 Mar 2021 11:27:12 +0100, Martin Devera wrote:
Add new rx-tx-swap property to allow for RX & TX pin swapping.
Signed-off-by: Martin Devera
Acked-by: Fabrice Gasnier
---
v6:
- add version changelog
v5:
- yaml fixes based on Rob Her
STM32 F7/H7 usarts supports RX & TX pin swapping.
Add option to turn it on.
Tested on STM32MP157.
Signed-off-by: Martin Devera
Acked-by: Fabrice Gasnier
---
v6:
- add version changelog
v4:
- delete superfluous has_swap=false
v3:
- add has_swap to stm32_usart_info (because F4
Add new rx-tx-swap property to allow for RX & TX pin swapping.
Signed-off-by: Martin Devera
Acked-by: Fabrice Gasnier
---
v6:
- add version changelog
v5:
- yaml fixes based on Rob Herring comments
- add serial.yaml reference
- move compatible from 'then' to 'if'
v3:
- d
Add new rx-tx-swap property to allow for RX & TX pin swapping.
Signed-off-by: Martin Devera
Acked-by: Fabrice Gasnier
---
.../devicetree/bindings/serial/st,stm32-uart.yaml | 29 ++
1 file changed, 19 insertions(+), 10 deletions(-)
diff --git a/Documentation/device
STM32 F7/H7 usarts supports RX & TX pin swapping.
Add option to turn it on.
Tested on STM32MP157.
Signed-off-by: Martin Devera
Acked-by: Fabrice Gasnier
---
drivers/tty/serial/stm32-usart.c | 11 ++-
drivers/tty/serial/stm32-usart.h | 4
2 files changed, 14 insertions(+
There is no other way to directly report/query this
quantity. It is useful when planing how given filesystem
can be resized.
Signed-off-by: Martin Devera
---
fs/ubifs/super.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/fs/ubifs/super.c b/fs/ubifs/super.c
index
On 3/2/21 6:44 PM, Fabrice Gasnier wrote:
On 3/2/21 2:15 PM, Martin Devera wrote:
STM32 F7/H7 usarts supports RX & TX pin swapping.
Add option to turn it on.
Tested on STM32MP157.
Signed-off-by: Martin Devera
---
drivers/tty/serial/stm32-usart.c | 11 ++-
drivers/tty/serial/s
STM32 F7/H7 usarts supports RX & TX pin swapping.
Add option to turn it on.
Tested on STM32MP157.
Signed-off-by: Martin Devera
---
drivers/tty/serial/stm32-usart.c | 11 ++-
drivers/tty/serial/stm32-usart.h | 4
2 files changed, 14 insertions(+), 1 deletion(-)
diff -
Add new rx-tx-swap property to allow for RX & TX pin swapping.
Signed-off-by: Martin Devera
---
.../devicetree/bindings/serial/st,stm32-uart.yaml | 32 +++---
1 file changed, 22 insertions(+), 10 deletions(-)
diff --git a/Documentation/devicetree/bindings/serial/st,s
Add new rx-tx-swap property to allow for RX & TX pin swapping.
Signed-off-by: Martin Devera
---
.../devicetree/bindings/serial/st,stm32-uart.yaml | 32 +++---
1 file changed, 22 insertions(+), 10 deletions(-)
diff --git a/Documentation/devicetree/bindings/serial/st,s
STM32 F7/H7 usarts supports RX & TX pin swapping.
Add option to turn it on.
Tested on STM32MP157.
Signed-off-by: Martin Devera
---
drivers/tty/serial/stm32-usart.c | 11 ++-
drivers/tty/serial/stm32-usart.h | 5 +
2 files changed, 15 insertions(+), 1 deletion(-)
diff -
On 3/1/21 11:28 AM, Fabrice Gasnier wrote:
On 2/27/21 5:41 PM, Martin Devera wrote:
STM32 F7/H7 usarts supports RX & TX pin swapping.
Add option to turn it on.
Tested on STM32MP157.
Signed-off-by: Martin Devera
---
drivers/tty/serial/stm32-usart.c | 3 ++-
drivers/tty/serial/stm32-usa
These are entries related to STM32MP1 PHY control.
Signed-off-by: Martin Devera
---
drivers/usb/dwc2/debugfs.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/usb/dwc2/debugfs.c b/drivers/usb/dwc2/debugfs.c
index aaafd463d72a..f13eed4231e1 100644
--- a/drivers/usb/dwc2/debugfs.c
Add new rx-tx-swap property to allow for RX & TX pin swapping.
Signed-off-by: Martin Devera
---
Documentation/devicetree/bindings/serial/st,stm32-uart.yaml | 4
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml
b/Documenta
STM32 F7/H7 usarts supports RX & TX pin swapping.
Add option to turn it on.
Tested on STM32MP157.
Signed-off-by: Martin Devera
---
drivers/tty/serial/stm32-usart.c | 3 ++-
drivers/tty/serial/stm32-usart.h | 1 +
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/tty/se
On 11/30/20 4:08 PM, Ulf Hansson wrote:
On Sun, 29 Nov 2020 at 19:20, Martin DEVERA wrote:
Hello,
on STM32MP1 with almost vanilla 5.7.7 in single CPU mode. Pair of
modprobe armmmci ; rmmod armmmci
causes rmmod and kworker to hang. I should note that no MMC is detected
on the board (SDIO
Hello,
on STM32MP1 with almost vanilla 5.7.7 in single CPU mode. Pair of
modprobe armmmci ; rmmod armmmci
causes rmmod and kworker to hang. I should note that no MMC is detected
on the board (SDIO device on MMC bus is not responding).
On another board (where SDIO is responding) rmmod works.
It
Hello,
I encountered bug in SX1502 expander driver in 5.7.7. Here is relevant
DTS part:
compatible = "semtech,sx1502q";
gpio4_cfg_pins: gpio2-cfg {
pins = "gpio5";
output-high;
};
And part of OOPS:
[ 0.673996] [] (gpiochip_get_data)
Paul Bolle wrote:
(This hit my box with lkml mesages without lkml in the To: header. What
happened here?)
Ahh, have to check my sending script ..
On zo, 2015-07-12 at 11:20 +0200, Martin Devera wrote:
--- /dev/null
+++ b/drivers/spi/spi-lpc32xx.c
+#define DRIVER_NAME"spi-lp
Paul Bolle wrote:
(This hit my box with lkml mesages without lkml in the To: header. What
happened here?)
Ahh, have to check my sending script ..
On zo, 2015-07-12 at 11:20 +0200, Martin Devera wrote:
--- /dev/null
+++ b/drivers/spi/spi-lpc32xx.c
+#define DRIVER_NAMEspi-lpc32xx
Debug code is removed.
---
drivers/spi/spi-lpc32xx.c | 16
1 file changed, 16 deletions(-)
diff --git a/drivers/spi/spi-lpc32xx.c b/drivers/spi/spi-lpc32xx.c
index 5c6b1ca..11b2c21 100644
--- a/drivers/spi/spi-lpc32xx.c
+++ b/drivers/spi/spi-lpc32xx.c
@@ -71,15 +71,6 @@ struct
Clock support for SPIs on LPC32XX SoC.
---
arch/arm/mach-lpc32xx/clock.c | 20
1 file changed, 20 insertions(+)
diff --git a/arch/arm/mach-lpc32xx/clock.c b/arch/arm/mach-lpc32xx/clock.c
index dd5d6f5..672c9b3 100644
--- a/arch/arm/mach-lpc32xx/clock.c
+++
+= spi-meson-spifc.o
obj-$(CONFIG_SPI_MPC512x_PSC) += spi-mpc512x-psc.o
obj-$(CONFIG_SPI_MPC52xx_PSC) += spi-mpc52xx-psc.o
diff --git a/drivers/spi/spi-lpc32xx.c b/drivers/spi/spi-lpc32xx.c
new file mode 100644
index 000..5c6b1ca
--- /dev/null
+++ b/drivers/spi/spi-lpc32xx.c
In commit a71b092a9c68685a270ebdde7b5986ba8787e575
__handle_domain_irq was introduced by Marc Zyngier.
It tests hwirq on zero and rejects it. At least
LPC32XX uses IRQ 0 as chained entry for SIC1. Thus
all SIC1 connected devices doesn't work just now.
This patch fixes it - not sure whether it is
In commit a71b092a9c68685a270ebdde7b5986ba8787e575
__handle_domain_irq was introduced by Marc Zyngier.
It tests hwirq on zero and rejects it. At least
LPC32XX uses IRQ 0 as chained entry for SIC1. Thus
all SIC1 connected devices doesn't work just now.
This patch fixes it - not sure whether it is
Debug code is removed.
---
drivers/spi/spi-lpc32xx.c | 16
1 file changed, 16 deletions(-)
diff --git a/drivers/spi/spi-lpc32xx.c b/drivers/spi/spi-lpc32xx.c
index 5c6b1ca..11b2c21 100644
--- a/drivers/spi/spi-lpc32xx.c
+++ b/drivers/spi/spi-lpc32xx.c
@@ -71,15 +71,6 @@ struct
Clock support for SPIs on LPC32XX SoC.
---
arch/arm/mach-lpc32xx/clock.c | 20
1 file changed, 20 insertions(+)
diff --git a/arch/arm/mach-lpc32xx/clock.c b/arch/arm/mach-lpc32xx/clock.c
index dd5d6f5..672c9b3 100644
--- a/arch/arm/mach-lpc32xx/clock.c
+++
-$(CONFIG_SPI_MPC52xx_PSC) += spi-mpc52xx-psc.o
diff --git a/drivers/spi/spi-lpc32xx.c b/drivers/spi/spi-lpc32xx.c
new file mode 100644
index 000..5c6b1ca
--- /dev/null
+++ b/drivers/spi/spi-lpc32xx.c
@@ -0,0 +1,265 @@
+/*
+ * LPC32XX SPI bus driver
+ *
+ * Copyright (C) 2015 Martin Devera de...@cdi.cz
Hi,
I compiled vanilla 4.1.1 for LPC3240 MPU without loadable module support.
I created own dts and board .c source:
static void __init lpc3250_machine_init(void)
{
__raw_writel(0x1600 ,LPC32XX_GPIO_P_MUX_SET); // SSP0
__raw_writel(1<<6 , io_p2v(0x40028004)); // ETH unreset
Hi,
I compiled vanilla 4.1.1 for LPC3240 MPU without loadable module support.
I created own dts and board .c source:
static void __init lpc3250_machine_init(void)
{
__raw_writel(0x1600 ,LPC32XX_GPIO_P_MUX_SET); // SSP0
__raw_writel(16 , io_p2v(0x40028004)); // ETH unreset
David Miller wrote:
From: Martin Devera <[EMAIL PROTECTED]>
Date: Mon, 18 Feb 2008 09:03:52 +0100
aha, ok, I'm not so informed about crossplatform issues.
I was also thining about looking at jiffies value and stop once
it is startjiffy+2, but with NO_HZ introduction, are jiffies
up to single jiffy interval and then delay remainder to other
jiffy.
Signed-off-by: Martin Devera <[EMAIL PROTECTED]>
I think we would be wise to use something other than loops_per_jiffy.
Depending upon the loop calibration method used by a particular
architecture it can me one o
up to single jiffy interval and then delay remainder to other
jiffy.
Signed-off-by: Martin Devera [EMAIL PROTECTED]
I think we would be wise to use something other than loops_per_jiffy.
Depending upon the loop calibration method used by a particular
architecture it can me one of many
David Miller wrote:
From: Martin Devera [EMAIL PROTECTED]
Date: Mon, 18 Feb 2008 09:03:52 +0100
aha, ok, I'm not so informed about crossplatform issues.
I was also thining about looking at jiffies value and stop once
it is startjiffy+2, but with NO_HZ introduction, are jiffies
still
From: Martin Devera <[EMAIL PROTECTED]>
HTB is event driven algorithm and part of its work is to apply
scheduled events at proper times. It tried to defend itself from
livelock by processing only limited number of events per dequeue.
Because of faster computers some users alrea
From: Martin Devera [EMAIL PROTECTED]
HTB is event driven algorithm and part of its work is to apply
scheduled events at proper times. It tried to defend itself from
livelock by processing only limited number of events per dequeue.
Because of faster computers some users already hit this hardcoded
Benjamin Herrenschmidt wrote:
On Tue, 2006-11-28 at 23:22 +, David Woodhouse wrote:
On Thu, 2006-02-16 at 16:09 +0100, Martin Devera wrote:
From: Martin Devera <[EMAIL PROTECTED]>
Add hotswap capability to Serverworks/BroadCom SATA controlers. The
controler has SIM register and it s
Benjamin Herrenschmidt wrote:
On Tue, 2006-11-28 at 23:22 +, David Woodhouse wrote:
On Thu, 2006-02-16 at 16:09 +0100, Martin Devera wrote:
From: Martin Devera [EMAIL PROTECTED]
Add hotswap capability to Serverworks/BroadCom SATA controlers. The
controler has SIM register and it selects
> Threads are processes that share more
BTW is not possible to implement threads as subset of process ?
Like thread list pointed to from task_struct. It'd contain
thread_structs plus another scheduler's data.
The thread could be much smaller than process.
Probably there is
Threads are processes that share more
BTW is not possible to implement threads as subset of process ?
Like thread list pointed to from task_struct. It'd contain
thread_structs plus another scheduler's data.
The thread could be much smaller than process.
Probably there is
Hello all,
after weeks of uptime, 2.4.4 kernel freezed several of
my processes. It seems like deadlock.
I typed "whereis perl" and system got frozen. After quick
look I found that I typed the command while "makedb" script
was running. All processes are on down:
budha:~# ps -A -o
Hello all,
after weeks of uptime, 2.4.4 kernel freezed several of
my processes. It seems like deadlock.
I typed whereis perl and system got frozen. After quick
look I found that I typed the command while makedb script
was running. All processes are on down:
budha:~# ps -A -o
Hello,
I installed 2.4.4 on host which was running win95 (without problems).
It is MB Gigabyte GA6BXC with one PCI net card (J2585B) and 128MB memory.
CPU is Pentium III (Katmai) fam.6 model 7 @ 450MHz.
One 15G IDE HDD.
After approx 1hr it gines me oops. I used ksymoops and result is
attached.
Hello,
I installed 2.4.4 on host which was running win95 (without problems).
It is MB Gigabyte GA6BXC with one PCI net card (J2585B) and 128MB memory.
CPU is Pentium III (Katmai) fam.6 model 7 @ 450MHz.
One 15G IDE HDD.
After approx 1hr it gines me oops. I used ksymoops and result is
attached.
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