This adds a base device tree file for the RZN1-DB board, with only the
basic support allowing the system to boot to a prompt. Only one UART is
used, with only a single CPU running.
Signed-off-by: Michel Pollet
Reviewed-by: Geert Uytterhoeven
---
arch/arm/boot/dts/Makefile | 1
This adds a base device tree file for the RZN1-DB board, with only the
basic support allowing the system to boot to a prompt. Only one UART is
used, with only a single CPU running.
Signed-off-by: Michel Pollet
Reviewed-by: Geert Uytterhoeven
---
arch/arm/boot/dts/Makefile | 1
On 25 May 2018 10:49, Geert wrote:
> Subject: Re: [PATCH v3 2/3] arm: shmobile: Add the R9A06G032 SMP enabler
> driver
>
> Hi Michel,
Hi Geert,
>
> On Thu, May 24, 2018 at 12:30 PM, Michel Pollet
> wrote:
> > The Renesas R9A06G032 second CA7 is parked in a ROM pen at
On 25 May 2018 10:49, Geert wrote:
> Subject: Re: [PATCH v3 2/3] arm: shmobile: Add the R9A06G032 SMP enabler
> driver
>
> Hi Michel,
Hi Geert,
>
> On Thu, May 24, 2018 at 12:30 PM, Michel Pollet
> wrote:
> > The Renesas R9A06G032 second CA7 is parked in a ROM pen at
Add a special enable method for the second CA7 of the R9A06G032
as well as the default value for the "cpu-release-addr" property.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
arch/arm/boot/dts/r9a06g032.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git
Add a special enable method for the second CA7 of the R9A06G032
as well as the default value for the "cpu-release-addr" property.
Signed-off-by: Michel Pollet
---
arch/arm/boot/dts/r9a06g032.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/r9a06g032.dtsi
The Renesas R9A06G032 second CA7 is parked in a ROM pen at boot time, it
requires a special enable method to get it started.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
arch/arm/mach-shmobile/Makefile| 1 +
arch/arm/mach-shmobile/smp-r9a06g032.
The Renesas R9A06G032 second CA7 is parked in a ROM pen at boot time, it
requires a special enable method to get it started.
Signed-off-by: Michel Pollet
---
arch/arm/mach-shmobile/Makefile| 1 +
arch/arm/mach-shmobile/smp-r9a06g032.c | 85 ++
2 files
Add a special enable method for second CA7 of the R9A06G032
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
Reviewed-by: Rob Herring <r...@kernel.org>
---
Documentation/devicetree/bindings/arm/cpus.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentatio
Add a special enable method for second CA7 of the R9A06G032
Signed-off-by: Michel Pollet
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/arm/cpus.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt
b/Documentation/devicetree
patch v7
v2:
+ Added suggestions from Florian Fainelli
+ Use __pa_symbol()
+ Simplified logic in prepare_cpu()
+ Reordered the patches
+ Rebased on RZN1 Base patch v5
Michel Pollet (3):
dt-bindings: cpu: Add Renesas R9A06G032 SMP enable method.
arm: shmobile: Add the R9A06G032 SMP
patch v7
v2:
+ Added suggestions from Florian Fainelli
+ Use __pa_symbol()
+ Simplified logic in prepare_cpu()
+ Reordered the patches
+ Rebased on RZN1 Base patch v5
Michel Pollet (3):
dt-bindings: cpu: Add Renesas R9A06G032 SMP enable method.
arm: shmobile: Add the R9A06G032 SMP
This provides a clock driver for the Renesas R09A06G032.
This uses a structure derived from both the RCAR gen2 driver as well as
the renesas-cpg-mssr driver.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
drivers/clk/renesas/Kconfig| 6 +
drivers/clk/r
This provides a clock driver for the Renesas R09A06G032.
This uses a structure derived from both the RCAR gen2 driver as well as
the renesas-cpg-mssr driver.
Signed-off-by: Michel Pollet
---
drivers/clk/renesas/Kconfig| 6 +
drivers/clk/renesas/Makefile | 1 +
drivers
This adds a base device tree file for the RZN1-DB board, with only the
basic support allowing the system to boot to a prompt. Only one UART is
used, with only a single CPU running.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
arch/arm/boot/dts/Makefile
This adds a base device tree file for the RZN1-DB board, with only the
basic support allowing the system to boot to a prompt. Only one UART is
used, with only a single CPU running.
Signed-off-by: Michel Pollet
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/r9a06g032
This adds the Renesas R9A06G032 bare bone support.
This currently only handles generic parts (gic, architected timer)
and a UART.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
arch/arm/boot/dts/r9a06g032.dtsi | 86
1 file chang
This adds the Renesas R9A06G032 bare bone support.
This currently only handles generic parts (gic, architected timer)
and a UART.
Signed-off-by: Michel Pollet
---
arch/arm/boot/dts/r9a06g032.dtsi | 86
1 file changed, 86 insertions(+)
create mode
The Renesas R9A06G032 SYSCTRL node description.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
.../bindings/clock/renesas,r9a06g032-sysctrl.txt | 32 ++
1 file changed, 32 insertions(+)
create mode 100644
Documentation/devicetree/bindings/clock/r
The Renesas R9A06G032 SYSCTRL node description.
Signed-off-by: Michel Pollet
---
.../bindings/clock/renesas,r9a06g032-sysctrl.txt | 32 ++
1 file changed, 32 insertions(+)
create mode 100644
Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt
diff
This adds the constants necessary to use the renesas,r9a06g032-sysctrl node.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
Reviewed-by: Rob Herring <r...@kernel.org>
---
include/dt-bindings/clock/r9a06g032-sysctrl.h | 187 ++
1 file changed, 18
This adds the constants necessary to use the renesas,r9a06g032-sysctrl node.
Signed-off-by: Michel Pollet
Reviewed-by: Rob Herring
---
include/dt-bindings/clock/r9a06g032-sysctrl.h | 187 ++
1 file changed, 187 insertions(+)
create mode 100644 include/dt-bindings/clock
every warnings from the DTC compiler on W=12 mode.
+ Split the device-tree patches from the code.
Michel Pollet (5):
dt-bindings: Add the r9a06g032-sysctrl.h file
dt-bindings: clock: renesas,r9a06g032-sysctrl: documentation
ARM: dts: Renesas R9A06G032 base device tree file
ARM: dts: Re
every warnings from the DTC compiler on W=12 mode.
+ Split the device-tree patches from the code.
Michel Pollet (5):
dt-bindings: Add the r9a06g032-sysctrl.h file
dt-bindings: clock: renesas,r9a06g032-sysctrl: documentation
ARM: dts: Renesas R9A06G032 base device tree file
ARM: dts: Re
This provides a clock driver for the Renesas RZ/N1 parts (#R09A06G0xx).
This uses a structure derived from both the RCAR gen2 driver as well as
the renesas-cpg-mssr driver.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
drivers/clk/renesas/Kconfig | 6 +
drive
This provides a clock driver for the Renesas RZ/N1 parts (#R09A06G0xx).
This uses a structure derived from both the RCAR gen2 driver as well as
the renesas-cpg-mssr driver.
Signed-off-by: Michel Pollet
---
drivers/clk/renesas/Kconfig | 6 +
drivers/clk/renesas/Makefile | 1
This adds a base device tree file for the RZN1-DB board, with only the
basic support allowing the system to boot to a prompt. Only one UART is
used, with only a single CPU running.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
arch/arm/boot/dts/Makefile
This adds a base device tree file for the RZN1-DB board, with only the
basic support allowing the system to boot to a prompt. Only one UART is
used, with only a single CPU running.
Signed-off-by: Michel Pollet
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/r9a06g032
This adds the constants necessary to use the renesas,rzn1-clocks driver.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
include/dt-bindings/clock/rzn1-clocks.h | 187
1 file changed, 187 insertions(+)
create mode 100644 include/dt-bindings
This adds the constants necessary to use the renesas,rzn1-clocks driver.
Signed-off-by: Michel Pollet
---
include/dt-bindings/clock/rzn1-clocks.h | 187
1 file changed, 187 insertions(+)
create mode 100644 include/dt-bindings/clock/rzn1-clocks.h
diff --git
This adds the Renesas RZ/N1D (Part #R9A06G032) SoC bare
bone support.
This currently only handles generic parts (gic, architected timer)
and a UART.
For simplicity sake, this also relies on the bootloader to set the
pinctrl and clocks.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.
This adds the Renesas RZ/N1D (Part #R9A06G032) SoC bare
bone support.
This currently only handles generic parts (gic, architected timer)
and a UART.
For simplicity sake, this also relies on the bootloader to set the
pinctrl and clocks.
Signed-off-by: Michel Pollet
---
arch/arm/boot/dts
The Renesas RZ/N1 Family (Part #R9A06G0xx) requires a driver
to provide the SoC clock infrastructure for Linux.
This documents the driver bindings.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
.../bindings/clock/renesas,rzn1-clocks.txt | 44 +++
The Renesas RZ/N1 Family (Part #R9A06G0xx) requires a driver
to provide the SoC clock infrastructure for Linux.
This documents the driver bindings.
Signed-off-by: Michel Pollet
---
.../bindings/clock/renesas,rzn1-clocks.txt | 44 ++
1 file changed, 44 insertions
elly.
+ Fixed every warnings from the DTC compiler on W=12 mode.
+ Split the device-tree patches from the code.
Michel Pollet (6):
dt-bindings: arm: Document the RZN1D-DB board
dt-bindings: Add the rzn1-clocks.h file
dt-bindings: clock: renesas,rzn1-clocks: document RZ/N1 clock driver
ARM
elly.
+ Fixed every warnings from the DTC compiler on W=12 mode.
+ Split the device-tree patches from the code.
Michel Pollet (6):
dt-bindings: arm: Document the RZN1D-DB board
dt-bindings: Add the rzn1-clocks.h file
dt-bindings: clock: renesas,rzn1-clocks: document RZ/N1 clock driver
ARM
This documents the RZ/N1 bindings for the RZN1D-DB board.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
Reviewed-by: Rob Herring <r...@kernel.org>
---
Documentation/devicetree/bindings/arm/shmobile.txt | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
This documents the RZ/N1 bindings for the RZN1D-DB board.
Signed-off-by: Michel Pollet
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/arm/shmobile.txt | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt
b
Add a special enable method for second CA8 of the Renesas RZ/N1D
(R9A06G032).
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
Reviewed-by: Rob Herring <r...@kernel.org>
---
Documentation/devicetree/bindings/arm/cpus.txt | 1 +
1 file changed, 1 insertion(+)
Add a special enable method for the second CA7 of the Renesas RZ/N1D
(R9A06G032), as well as the default value for the "cpu-release-addr"
property.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
arch/arm/boot/dts/r9a06g032.dtsi | 2 ++
1 file changed, 2 insertion
Add a special enable method for second CA8 of the Renesas RZ/N1D
(R9A06G032).
Signed-off-by: Michel Pollet
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/arm/cpus.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt
b
Add a special enable method for the second CA7 of the Renesas RZ/N1D
(R9A06G032), as well as the default value for the "cpu-release-addr"
property.
Signed-off-by: Michel Pollet
---
arch/arm/boot/dts/r9a06g032.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts
The Renesas RZ/N1D second CA7 is parked in a ROM pen at boot time, it
requires a special enable method to get it started.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
arch/arm/mach-shmobile/Makefile| 1 +
arch/arm/mach-shmobile/smp-r9a06g032.
The Renesas RZ/N1D second CA7 is parked in a ROM pen at boot time, it
requires a special enable method to get it started.
Signed-off-by: Michel Pollet
---
arch/arm/mach-shmobile/Makefile| 1 +
arch/arm/mach-shmobile/smp-r9a06g032.c | 85 ++
2 files
()
+ Simplified logic in prepare_cpu()
+ Reordered the patches
+ Rebased on RZN1 Base patch v5
*** BLURB HERE ***
Michel Pollet (3):
dt-bindings: cpu: Add Renesas RZ/N1D SMP enable method.
arm: shmobile: Add the RZ/N1D SMP enabler driver
ARM: dts: Renesas RZ/N1D SMP enable method
()
+ Simplified logic in prepare_cpu()
+ Reordered the patches
+ Rebased on RZN1 Base patch v5
*** BLURB HERE ***
Michel Pollet (3):
dt-bindings: cpu: Add Renesas RZ/N1D SMP enable method.
arm: shmobile: Add the RZ/N1D SMP enabler driver
ARM: dts: Renesas RZ/N1D SMP enable method
This documents the RZ/N1 bindings for the RZN1D-DB board.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
Documentation/devicetree/bindings/arm/shmobile.txt | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/shmobi
The Renesas RZ/N1 Family (Part #R9A06G0xx) requires a driver
as part of the sysctrl MFD to handle rebooting the CA7 cores.
This documents the driver bindings.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
.../devicetree/bindings/power/renesas,rzn1-reboot.txt
This adds the Renesas RZ/N1D (Part #R9A06G032) SoC bare
bone support.
This currently only handles generic parts (gic, architected timer)
and a UART.
For simplicity sake, this also relies on the bootloader to set the
pinctrl and clocks.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.
This documents the RZ/N1 bindings for the RZN1D-DB board.
Signed-off-by: Michel Pollet
---
Documentation/devicetree/bindings/arm/shmobile.txt | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt
b/Documentation/devicetree
The Renesas RZ/N1 Family (Part #R9A06G0xx) requires a driver
as part of the sysctrl MFD to handle rebooting the CA7 cores.
This documents the driver bindings.
Signed-off-by: Michel Pollet
---
.../devicetree/bindings/power/renesas,rzn1-reboot.txt | 17 +
1 file changed, 17
This adds the Renesas RZ/N1D (Part #R9A06G032) SoC bare
bone support.
This currently only handles generic parts (gic, architected timer)
and a UART.
For simplicity sake, this also relies on the bootloader to set the
pinctrl and clocks.
Signed-off-by: Michel Pollet
---
arch/arm/boot/dts
The Renesas RZ/N1 Family (Part #R9A06G0xx) needs a small driver
to reboot the Cortex-A7 cores. This driver is a sub driver of
the sysctrl MFD.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
drivers/power/reset/Kconfig | 7 +++
drivers/power/reset/Makefile
The Renesas RZ/N1 Family (Part #R9A06G0xx) needs a small driver
to reboot the Cortex-A7 cores. This driver is a sub driver of
the sysctrl MFD.
Signed-off-by: Michel Pollet
---
drivers/power/reset/Kconfig | 7 +++
drivers/power/reset/Makefile | 1 +
drivers/power/reset/rzn1-reboot.c
This adds a base device tree file for the RZN1-DB board, with only the
basic support allowing the system to boot to a prompt. Only one UART is
used, with only a single CPU running.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
arch/arm/boot/dts/Makefile
This adds a base device tree file for the RZN1-DB board, with only the
basic support allowing the system to boot to a prompt. Only one UART is
used, with only a single CPU running.
Signed-off-by: Michel Pollet
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/r9a06g032
Add the RZ/N1D SoC to the reset of the Renesas SoC Collection.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
arch/arm/mach-shmobile/Kconfig | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 9
Add the RZ/N1D SoC to the reset of the Renesas SoC Collection.
Signed-off-by: Michel Pollet
---
arch/arm/mach-shmobile/Kconfig | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 96672da..fcc273f 100644
--- a/arch/arm
part'
distinction.
+ Removed the sysctrl.h file entirelly.
+ Fixed every warnings from the DTC compiler on W=12 mode.
+ Split the device-tree patches from the code.
Michel Pollet (6):
arm: shmobile: Add the RZ/N1D (R9A06G032) to the shmobile Kconfig
dt-bindings: reset: renesas,rzn1-re
part'
distinction.
+ Removed the sysctrl.h file entirelly.
+ Fixed every warnings from the DTC compiler on W=12 mode.
+ Split the device-tree patches from the code.
Michel Pollet (6):
arm: shmobile: Add the RZ/N1D (R9A06G032) to the shmobile Kconfig
dt-bindings: reset: renesas,rzn1-re
Hi Florian,
On 16 April 2018 22:46, Florian Fainelli:
> Hi Michel,
>
> On 04/16/2018 02:34 AM, Michel Pollet wrote:
> > The Renesas RZ/N1D second CA7 is parked in a ROM pen at boot time, it
> > requires a special enable method to get it started at boot time.
> >
>
Hi Florian,
On 16 April 2018 22:46, Florian Fainelli:
> Hi Michel,
>
> On 04/16/2018 02:34 AM, Michel Pollet wrote:
> > The Renesas RZ/N1D second CA7 is parked in a ROM pen at boot time, it
> > requires a special enable method to get it started at boot time.
> >
>
Hi Rob,
On 13 April 2018 19:06, Rob Herring:
> On Tue, Apr 10, 2018 at 09:30:03AM +0100, Michel Pollet wrote:
> > The Renesas RZ/N1 Family (Part #R9A06G0xx) has a multi-function system
> > controller. This documents the node used to encapsulate it's sub
> > drivers.
> >
Hi Rob,
On 13 April 2018 19:06, Rob Herring:
> On Tue, Apr 10, 2018 at 09:30:03AM +0100, Michel Pollet wrote:
> > The Renesas RZ/N1 Family (Part #R9A06G0xx) has a multi-function system
> > controller. This documents the node used to encapsulate it's sub
> > drivers.
> >
Please ignore this one... it's rebase junk
Michel
>
> This enables starting the second CA7 core. Also handles the case the
> bootloader has had to change the second CPU parking address to allow
> booting in NONSEC/HYP.
>
> Signed-off-by: Michel Pollet <michel.
Please ignore this one... it's rebase junk
Michel
>
> This enables starting the second CA7 core. Also handles the case the
> bootloader has had to change the second CPU parking address to allow
> booting in NONSEC/HYP.
>
> Signed-off-by: Michel Pollet
> ---
> arch/ar
Add a special enable method for the second CA7 of the Renesas RZ/N1D
(R9A06G032), as well as the default value for the "cpu-release-addr"
property.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
arch/arm/boot/dts/r9a06g032.dtsi | 2 ++
1 file changed, 2 insertion
Add a special enable method for the second CA7 of the Renesas RZ/N1D
(R9A06G032), as well as the default value for the "cpu-release-addr"
property.
Signed-off-by: Michel Pollet
---
arch/arm/boot/dts/r9a06g032.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts
This enables starting the second CA7 core. Also handles the case the
bootloader has had to change the second CPU parking address to allow
booting in NONSEC/HYP.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
arch/arm/mach-shmobile/Makefile | 1 +
arch/arm/mach-sh
The Renesas RZ/N1D second CA7 is parked in a ROM pen at boot time, it
requires a special enable method to get it started at boot time.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
arch/arm/mach-shmobile/Makefile| 1 +
arch/arm/mach-shmobile/smp-r9a06g032.
Add a special enable method for second CA8 of the Renesas RZ/N1D
(R9A06G032).
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
Documentation/devicetree/bindings/arm/cpus.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/cpus.
This enables starting the second CA7 core. Also handles the case the
bootloader has had to change the second CPU parking address to allow
booting in NONSEC/HYP.
Signed-off-by: Michel Pollet
---
arch/arm/mach-shmobile/Makefile | 1 +
arch/arm/mach-shmobile/r9a06g032.h | 7
The Renesas RZ/N1D second CA7 is parked in a ROM pen at boot time, it
requires a special enable method to get it started at boot time.
Signed-off-by: Michel Pollet
---
arch/arm/mach-shmobile/Makefile| 1 +
arch/arm/mach-shmobile/smp-r9a06g032.c | 87
Add a special enable method for second CA8 of the Renesas RZ/N1D
(R9A06G032).
Signed-off-by: Michel Pollet
---
Documentation/devicetree/bindings/arm/cpus.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt
b/Documentation/devicetree/bindings
, or is it sufficiently
clear?
Michel Pollet (3):
dt-bindings: cpu: Add Renesas RZ/N1D SMP enable method.
ARM: dts: Renesas RZ/N1D SMP enable method
arm: shmobile: Add the RZ/N1D SMP enabler driver.
Documentation/devicetree/bindings/arm/cpus.txt | 1 +
arch/arm/boot/dts/r9a06g032.dtsi
, or is it sufficiently
clear?
Michel Pollet (3):
dt-bindings: cpu: Add Renesas RZ/N1D SMP enable method.
ARM: dts: Renesas RZ/N1D SMP enable method
arm: shmobile: Add the RZ/N1D SMP enabler driver.
Documentation/devicetree/bindings/arm/cpus.txt | 1 +
arch/arm/boot/dts/r9a06g032.dtsi
The Renesas RZ/N1 Family (Part #R9A06G0xx) needs a small driver
to reboot the Cortex-A7 cores. This driver is a sub driver of
the sysctrl MFD.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
drivers/power/reset/Kconfig | 7 +++
drivers/power/reset/Makefile
The Renesas RZ/N1 Family (Part #R9A06G0xx) needs a small driver
to reboot the Cortex-A7 cores. This driver is a sub driver of
the sysctrl MFD.
Signed-off-by: Michel Pollet
---
drivers/power/reset/Kconfig | 7 +++
drivers/power/reset/Makefile | 1 +
drivers/power/reset/rzn1
This adds the Renesas RZ/N1D (Part #R9A06G032) SoC bare
bone support.
This currently only handles generic parts (gic, architected timer)
and a UART.
For simplicity sake, this also relies on the bootloader to set the
pinctrl and clocks.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.
This adds the Renesas RZ/N1D (Part #R9A06G032) SoC bare
bone support.
This currently only handles generic parts (gic, architected timer)
and a UART.
For simplicity sake, this also relies on the bootloader to set the
pinctrl and clocks.
Signed-off-by: Michel Pollet
---
arch/arm/boot/dts
This adds a base device tree file for the RZN1-DB board, with only the
basic support allowing the system to boot to a prompt. Only one UART is
used, with only a single CPU running.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
arch/arm/boot/dts/Makefile
This adds a base device tree file for the RZN1-DB board, with only the
basic support allowing the system to boot to a prompt. Only one UART is
used, with only a single CPU running.
Signed-off-by: Michel Pollet
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/r9a06g032
The Renesas RZ/N1 Family (Part #R9A06G0xx) has a multi-function
system controller. This documents the node used to encapsulate
it's sub drivers.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
.../bindings/mfd/renesas,rzn1-sysctrl.txt | 23 ++
The Renesas RZ/N1 Family (Part #R9A06G0xx) has a multi-function
system controller. This documents the node used to encapsulate
it's sub drivers.
Signed-off-by: Michel Pollet
---
.../bindings/mfd/renesas,rzn1-sysctrl.txt | 23 ++
1 file changed, 23 insertions
The Renesas RZ/N1 Family (Part #R9A06G0xx) requires a driver
as part of the sysctrl MFD to handle rebooting the CA7 cores.
This documents the driver bindings.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
.../bindings/power/renesas,rzn1-reboot.txt
The Renesas RZ/N1 Family (Part #R9A06G0xx) requires a driver
as part of the sysctrl MFD to handle rebooting the CA7 cores.
This documents the driver bindings.
Signed-off-by: Michel Pollet
---
.../bindings/power/renesas,rzn1-reboot.txt | 23 ++
1 file changed, 23
Add the RZ/N1D SoC to the reset of the Renesas SoC Collection.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
arch/arm/mach-shmobile/Kconfig | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 2
This documents the RZ/N1 bindings for the RZN1D-DB board.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
---
Documentation/devicetree/bindings/arm/shmobile.txt | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/shmobi
This documents the RZ/N1 bindings for the RZN1D-DB board.
Signed-off-by: Michel Pollet
---
Documentation/devicetree/bindings/arm/shmobile.txt | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt
b/Documentation/devicetree
Add the RZ/N1D SoC to the reset of the Renesas SoC Collection.
Signed-off-by: Michel Pollet
---
arch/arm/mach-shmobile/Kconfig | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 221fbcb..a80c0ed 100644
--- a/arch/arm
bile conventions
+ Adapted the compatible= strings to reflect 'family' vs 'part'
distinction.
+ Removed the sysctrl.h file entirelly.
+ Fixed every warnings from the DTC compiler on W=12 mode.
+ Split the device-tree patches from the code.
Michel Pollet (8):
arm: shmobile: Add the RZ/N1
bile conventions
+ Adapted the compatible= strings to reflect 'family' vs 'part'
distinction.
+ Removed the sysctrl.h file entirelly.
+ Fixed every warnings from the DTC compiler on W=12 mode.
+ Split the device-tree patches from the code.
Michel Pollet (8):
arm: shmobile: Add the RZ/N1
Add the RZ/N1 Family (Part #R9A06G0xx) ARCH config to the rest of
the Renesas SoC collection.
Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+rene...@glider.be>
---
arch/arm/mach-shmobile/Kconfig | 5 +
1 file changed, 5 inserti
Add the RZ/N1 Family (Part #R9A06G0xx) ARCH config to the rest of
the Renesas SoC collection.
Signed-off-by: Michel Pollet
Reviewed-by: Geert Uytterhoeven
---
arch/arm/mach-shmobile/Kconfig | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach
Hi Rob,
On 09 April 2018 21:10, Rob Herring wrote:
> On Thu, Mar 29, 2018 at 08:46:58AM +0100, Michel Pollet wrote:
> > The Renesas RZ/N1 Family (Part #R9A06G0xx) requires a driver as part
> > of the sysctrl MFD to handle rebooting the CA7 cores.
> > This document
Hi Rob,
On 09 April 2018 21:10, Rob Herring wrote:
> On Thu, Mar 29, 2018 at 08:46:58AM +0100, Michel Pollet wrote:
> > The Renesas RZ/N1 Family (Part #R9A06G0xx) requires a driver as part
> > of the sysctrl MFD to handle rebooting the CA7 cores.
> > This document
On 29 March 2018 08:47, I messed up:
[snip]
>
> The Renesas RZ/N1 Family (Part #R9A06G0xx) needs a small driver to reboot
> the Cortex-A7 cores. This driver is a sub driver of the sysctrl MFD.
>
> Signed-off-by: Michel Pollet <michel.pol...@bp.renesas.com>
> ---
>
On 29 March 2018 08:47, I messed up:
[snip]
>
> The Renesas RZ/N1 Family (Part #R9A06G0xx) needs a small driver to reboot
> the Cortex-A7 cores. This driver is a sub driver of the sysctrl MFD.
>
> Signed-off-by: Michel Pollet
> ---
> drivers/power/reset/Kconfig | 7
This adds the Renesas RZ/N1 Family (Part #R9A06G0xx) SoC
bare bone support.
This currently only handles generic parts (gic, architected timer)
and a UART.
For simplicity sake, this also relies on the bootloader to set the
pinctrl and clocks.
Signed-off-by: Michel Pollet <michel.
This adds the Renesas RZ/N1 Family (Part #R9A06G0xx) SoC
bare bone support.
This currently only handles generic parts (gic, architected timer)
and a UART.
For simplicity sake, this also relies on the bootloader to set the
pinctrl and clocks.
Signed-off-by: Michel Pollet
---
arch/arm/boot/dts
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