RE: [Patch v2 0/4] Add Nvidia Tegra GPC-DMA driver
> -Original Message- > From: Jonathan Hunter > Sent: Friday, January 15, 2021 6:51 PM > To: Vinod Koul > Cc: Rajesh Gumasta ; Laxman Dewangan > ; dan.j.willi...@intel.com; > thierry.red...@gmail.com; p.za...@pengutronix.de; > dmaeng...@vger.kernel.org; linux-te...@vger.kernel.org; linux- > ker...@vger.kernel.org; Krishna Yarlagadda > Subject: Re: [Patch v2 0/4] Add Nvidia Tegra GPC-DMA driver > > > On 15/01/2021 05:56, Vinod Koul wrote: > > On 14-01-21, 10:11, Jon Hunter wrote: > >> > >> On 06/08/2020 08:30, Rajesh Gumasta wrote: > >>> Changes in patch v2: > >>> Addressed review comments in patch v1 > >> > >> > >> Is there any update on this series? Would be good to get this upstream. > > > > Not sure why, this is is not in my queue, can someone please resend > > this to me > > Sorry, this question was meant for Rajesh. This series is not ready yet. > There are still some items that need to be addressed. > > Thanks > Jon > Yes, some pending review comments on v2 patch needs to addressed. Currently this is put on hold due to other priority things. I will update this thread once I resume working addressing the comments. Thanks Rajesh
RE: [Patch v2 2/4] dmaengine: tegra: Add Tegra GPC DMA driver
> -Original Message-
> From: Dmitry Osipenko
> Sent: Thursday, August 6, 2020 7:16 PM
> To: Rajesh Gumasta ; Laxman Dewangan
> ; Jonathan Hunter ;
> vk...@kernel.org; dan.j.willi...@intel.com; thierry.red...@gmail.com;
> p.za...@pengutronix.de; dmaeng...@vger.kernel.org; linux-
> te...@vger.kernel.org; linux-kernel@vger.kernel.org
> Cc: Krishna Yarlagadda ; Pavan Kunapuli
>
> Subject: Re: [Patch v2 2/4] dmaengine: tegra: Add Tegra GPC DMA driver
>
> External email: Use caution opening links or attachments
>
>
> 06.08.2020 10:30, Rajesh Gumasta пишет:
> ...
> > +/*
> > + * Save and restore csr and channel register on pm_suspend
> > + * and pm_resume respectively
> > + */
> > +static int __maybe_unused tegra_dma_pm_suspend(struct device *dev)
> {
> > + struct tegra_dma *tdma = dev_get_drvdata(dev);
> > + int i;
> > +
> > + for (i = 0; i < tdma->chip_data->nr_channels; i++) {
> > + struct tegra_dma_channel *tdc = >channels[i];
> > + struct tegra_dma_channel_regs *ch_reg =
> > + >channel_reg;
> > +
> > + ch_reg->csr = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSR);
> > + ch_reg->src_ptr = tdc_read(tdc,
> TEGRA_GPCDMA_CHAN_SRC_PTR);
> > + ch_reg->dst_ptr = tdc_read(tdc,
> TEGRA_GPCDMA_CHAN_DST_PTR);
> > + ch_reg->high_addr_ptr = tdc_read(tdc,
> > +
> > TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR);
> > + ch_reg->mc_seq = tdc_read(tdc,
> TEGRA_GPCDMA_CHAN_MCSEQ);
> > + ch_reg->mmio_seq = tdc_read(tdc,
> TEGRA_GPCDMA_CHAN_MMIOSEQ);
> > + ch_reg->wcount = tdc_read(tdc,
> TEGRA_GPCDMA_CHAN_WCOUNT);
> > + }
> > + return 0;
> > +}
> > +
> > +static int __maybe_unused tegra_dma_pm_resume(struct device *dev) {
> > + struct tegra_dma *tdma = dev_get_drvdata(dev);
> > + int i;
> > +
> > + for (i = 0; i < tdma->chip_data->nr_channels; i++) {
> > + struct tegra_dma_channel *tdc = >channels[i];
> > + struct tegra_dma_channel_regs *ch_reg =
> > + >channel_reg;
> > +
> > + tdc_write(tdc, TEGRA_GPCDMA_CHAN_WCOUNT, ch_reg-
> >wcount);
> > + tdc_write(tdc, TEGRA_GPCDMA_CHAN_DST_PTR, ch_reg-
> >dst_ptr);
> > + tdc_write(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR, ch_reg-
> >src_ptr);
> > + tdc_write(tdc, TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR,
> > + ch_reg->high_addr_ptr);
> > + tdc_write(tdc, TEGRA_GPCDMA_CHAN_MMIOSEQ, ch_reg-
> >mmio_seq);
> > + tdc_write(tdc, TEGRA_GPCDMA_CHAN_MCSEQ, ch_reg->mc_seq);
> > + tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR,
> > + (ch_reg->csr & ~TEGRA_GPCDMA_CSR_ENB));
> > + }
> > + return 0;
> > +}
> > +
> > +static const struct __maybe_unused dev_pm_ops
> tegra_dma_dev_pm_ops = {
> > + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_dma_pm_suspend,
> > +tegra_dma_pm_resume) };
>
> Please explain why this is needed. All DMA should be stopped (not
> paused) on system's suspend, shouldn't it?
I have rechecked with HW verification team and they confirmed that after
suspend, csr and channel registers will get reset hence on resume we need to
restore back.
Also GPCDMA does not support power gate as a unit.
Thanks
Rajesh
[Patch v2 3/4] arm64: configs: enable tegra gpc dma
Enable TEGRA_GPC_DMA in defconfig for Tegra186 and Tegra196 gpc dma controller driver Signed-off-by: Rajesh Gumasta --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 883e8ba..600f568 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -775,6 +775,7 @@ CONFIG_MV_XOR_V2=y CONFIG_OWL_DMA=y CONFIG_PL330_DMA=y CONFIG_TEGRA20_APB_DMA=y +CONFIG_TEGRA_GPC_DMA=m CONFIG_QCOM_BAM_DMA=y CONFIG_QCOM_HIDMA_MGMT=y CONFIG_QCOM_HIDMA=y -- 2.7.4
[Patch v2 4/4] arm64: tegra: Add GPCDMA node in dt
Add device tree node for GPCDMA controller on Tegra186 target
and Tegra194 target.
Signed-off-by: Rajesh Gumasta
---
arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 4 +++
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 46 ++
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 44
3 files changed, 94 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
index 2fcaa2e..56ed8d8 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
@@ -54,6 +54,10 @@
};
};
+ dma@260 {
+ status = "okay";
+ };
+
memory-controller@2c0 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 58100fb..91bb17e 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -70,6 +70,52 @@
snps,rxpbl = <8>;
};
+ gpcdma: dma@260 {
+ compatible = "nvidia,tegra186-gpcdma";
+ reg = <0x0 0x260 0x0 0x21>;
+ resets = < TEGRA186_RESET_GPCDMA>;
+ reset-names = "gpcdma";
+ interrupts = ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ;
+ #dma-cells = <1>;
+ iommus = < TEGRA186_SID_GPCDMA_0>;
+ dma-coherent;
+ nvidia,start-dma-channel-index = <1>;
+ dma-channels = <31>;
+ status = "disabled";
+ };
+
aconnect {
compatible = "nvidia,tegra186-aconnect",
"nvidia,tegra210-aconnect";
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index 4bc187a..0bd67bd 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -68,6 +68,50 @@
snps,rxpbl = <8>;
};
+ gpcdma: dma@260 {
+ compatible = "nvidia,tegra194-gpcdma";
+ reg = <0x0 0x260 0x0 0x21>;
+
[Patch v2 2/4] dmaengine: tegra: Add Tegra GPC DMA driver
Adding GPC DMA controller driver for Tegra186 and Tegra194. The driver supports dma transfers between memory to memory, IO peripheral to memory and memory to IO peripheral. Signed-off-by: Pavan Kunapuli Signed-off-by: Rajesh Gumasta --- drivers/dma/Kconfig | 12 + drivers/dma/Makefile|1 + drivers/dma/tegra-gpc-dma.c | 1472 +++ 3 files changed, 1485 insertions(+) create mode 100644 drivers/dma/tegra-gpc-dma.c diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index e9ed916..84b3a0a 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -639,6 +639,18 @@ config TEGRA210_ADMA peripheral and vice versa. It does not support memory to memory data transfer. +config TEGRA_GPC_DMA + tristate "NVIDIA Tegra GPC DMA support" + depends on ARCH_TEGRA_186_SOC || ARCH_TEGRA_194_SOC || COMPILE_TEST + select DMA_ENGINE + help + Support for the NVIDIA Tegra186 and Tegra194 GPC DMA controller + driver. The DMA controller has multiple DMA channels which can + be configured for different peripherals like UART, SPI, etc + which are on APB bus. + This DMA controller transfers data from memory to peripheral FIFO + or vice versa. It also supports memory to memory data transfer. + config TIMB_DMA tristate "Timberdale FPGA DMA support" depends on MFD_TIMBERDALE || COMPILE_TEST diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index e60f813..43e3a6e 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -76,6 +76,7 @@ obj-$(CONFIG_S3C24XX_DMAC) += s3c24xx-dma.o obj-$(CONFIG_TXX9_DMAC) += txx9dmac.o obj-$(CONFIG_TEGRA20_APB_DMA) += tegra20-apb-dma.o obj-$(CONFIG_TEGRA210_ADMA) += tegra210-adma.o +obj-$(CONFIG_TEGRA_GPC_DMA) += tegra-gpc-dma.o obj-$(CONFIG_TIMB_DMA) += timb_dma.o obj-$(CONFIG_UNIPHIER_MDMAC) += uniphier-mdmac.o obj-$(CONFIG_UNIPHIER_XDMAC) += uniphier-xdmac.o diff --git a/drivers/dma/tegra-gpc-dma.c b/drivers/dma/tegra-gpc-dma.c new file mode 100644 index 000..723b352 --- /dev/null +++ b/drivers/dma/tegra-gpc-dma.c @@ -0,0 +1,1472 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * DMA driver for Nvidia's Tegra186 and Tegra194 GPC DMA controller. + * + * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "virt-dma.h" + +/* CSR register */ +#define TEGRA_GPCDMA_CHAN_CSR 0x00 +#define TEGRA_GPCDMA_CSR_ENB BIT(31) +#define TEGRA_GPCDMA_CSR_IE_EOCBIT(30) +#define TEGRA_GPCDMA_CSR_ONCE BIT(27) +#define TEGRA_GPCDMA_CSR_FC_MODE_NO_MMIO (0 << 24) +#define TEGRA_GPCDMA_CSR_FC_MODE_ONE_MMIO BIT(24) +#define TEGRA_GPCDMA_CSR_FC_MODE_TWO_MMIO BIT(25) +#define TEGRA_GPCDMA_CSR_FC_MODE_FOUR_MMIO GENMASK(25, 24) +#define TEGRA_GPCDMA_CSR_DMA_IO2MEM_NO_FC (0 << 21) +#define TEGRA_GPCDMA_CSR_DMA_IO2MEM_FC BIT(21) +#define TEGRA_GPCDMA_CSR_DMA_MEM2IO_NO_FC BIT(22) +#define TEGRA_GPCDMA_CSR_DMA_MEM2IO_FC GENMASK(22, 21) +#define TEGRA_GPCDMA_CSR_DMA_MEM2MEM BIT(23) +#define TEGRA_GPCDMA_CSR_DMA_FIXED_PAT GENMASK(23, 22) +#define TEGRA_GPCDMA_CSR_REQ_SEL_SHIFT 16 +#define TEGRA_GPCDMA_CSR_REQ_SEL_MASK GENMASK(20, 16) +#define TEGRA_GPCDMA_CSR_REQ_SEL_UNUSEDBIT(18) +#define TEGRA_GPCDMA_CSR_IRQ_MASK BIT(15) +#define TEGRA_GPCDMA_CSR_WEIGHT_SHIFT 10 + +/* STATUS register */ +#define TEGRA_GPCDMA_CHAN_STATUS 0x004 +#define TEGRA_GPCDMA_STATUS_BUSY BIT(31) +#define TEGRA_GPCDMA_STATUS_ISE_EOCBIT(30) +#define TEGRA_GPCDMA_STATUS_PING_PONG BIT(28) +#define TEGRA_GPCDMA_STATUS_DMA_ACTIVITY BIT(27) +#define TEGRA_GPCDMA_STATUS_CHANNEL_PAUSE BIT(26) +#define TEGRA_GPCDMA_STATUS_CHANNEL_RX BIT(25) +#define TEGRA_GPCDMA_STATUS_CHANNEL_TX BIT(24) +#define TEGRA_GPCDMA_STATUS_IRQ_INTR_STA BIT(23) +#define TEGRA_GPCDMA_STATUS_IRQ_STABIT(21) +#define TEGRA_GPCDMA_STATUS_IRQ_TRIG_STA BIT(20) + +#define TEGRA_GPCDMA_CHAN_CSRE 0x008 +#define TEGRA_GPCDMA_CHAN_CSRE_PAUSE BIT(31) + +/* Source address */ +#define TEGRA_GPCDMA_CHAN_SRC_PTR 0x00C + +/* Destination address */ +#define TEGRA_GPCDMA_CHAN_DST_PTR 0x010 + +/* High address pointer */ +#define TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR0x014 +#define TEGRA_GPCDMA_HIGH_ADDR_SCR_PTR_SHIFT 0 +#define TEGRA_GPCDMA_HIGH_ADDR_SCR_PTR_MASK0xFF +#define TEGRA_GPCDMA_HIGH_ADDR_DST_PTR_SHIFT 16 +#define TEGRA_GPCDMA_HIGH_ADDR_DST_PTR_MASK0xFF + +/* MC sequence re
[Patch v2 0/4] Add Nvidia Tegra GPC-DMA driver
Changes in patch v2: Addressed review comments in patch v1 v1 - https://lkml.org/lkml/2020/7/20/96 Rajesh Gumasta (4): dt-bindings: dma: Add DT binding document dmaengine: tegra: Add Tegra GPC DMA driver arm64: configs: enable tegra gpc dma arm64: tegra: Add GPCDMA node in dt .../bindings/dma/nvidia,tegra-gpc-dma.yaml | 99 ++ arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi |4 + arch/arm64/boot/dts/nvidia/tegra186.dtsi | 46 + arch/arm64/boot/dts/nvidia/tegra194.dtsi | 44 + arch/arm64/configs/defconfig |1 + drivers/dma/Kconfig| 12 + drivers/dma/Makefile |1 + drivers/dma/tegra-gpc-dma.c| 1472 8 files changed, 1679 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/nvidia,tegra-gpc-dma.yaml create mode 100644 drivers/dma/tegra-gpc-dma.c -- 2.7.4
[Patch v2 1/4] dt-bindings: dma: Add DT binding document
Add DT binding document for Nvidia Tegra GPCDMA controller.
Signed-off-by: Rajesh Gumasta
---
.../bindings/dma/nvidia,tegra-gpc-dma.yaml | 99 ++
1 file changed, 99 insertions(+)
create mode 100644
Documentation/devicetree/bindings/dma/nvidia,tegra-gpc-dma.yaml
diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra-gpc-dma.yaml
b/Documentation/devicetree/bindings/dma/nvidia,tegra-gpc-dma.yaml
new file mode 100644
index 000..39827ab
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/nvidia,tegra-gpc-dma.yaml
@@ -0,0 +1,99 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/nvidia,tegra-gpc-dma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Nvidia Tegra GPC DMA Controller Device Tree Bindings
+
+description: |
+ Tegra GPC DMA controller is a general purpose dma used for faster data
+ transfers between memory to memory, memory to device and device to memory.
+ Terms 'dma' and 'gpcdma' can be used interchangeably.
+
+maintainers:
+ - Jon Hunter
+ - Rajesh Gumasta
+
+allOf:
+ - $ref: "dma-controller.yaml#"
+
+properties:
+ "#dma-cells":
+const: 1
+
+ compatible:
+- enum:
+ - nvidia,tegra186-gpcdma
+ - nvidia,tegra194-gpcdma
+
+ reg:
+maxItems: 1
+
+ interrupts:
+maxItems: 1
+
+ resets:
+maxItems: 1
+
+ reset-names:
+const: gpcdma
+
+ iommus:
+maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - resets
+ - reset-names
+ - "#dma-cells"
+ - iommus
+
+examples:
+ - |
+gpcdma: dma@260 {
+ compatible = "nvidia,tegra186-gpcdma";
+ reg = <0x0 0x260 0x0 0x21>;
+ resets = < TEGRA186_RESET_GPCDMA>;
+ reset-names = "gpcdma";
+ interrupts = ;
+ #dma-cells = <1>;
+ iommus = < TEGRA_SID_GPCDMA_0>;
+ dma-coherent;
+ };
+
+...
--
2.7.4
RE: [Patch v1 0/4] Add Nvidia Tegra GPC-DMA driver
> -Original Message- > From: Thierry Reding > Sent: Monday, July 20, 2020 2:56 PM > To: Rajesh Gumasta > Cc: Laxman Dewangan ; Jonathan Hunter > ; vk...@kernel.org; dan.j.willi...@intel.com; > p.za...@pengutronix.de; dmaeng...@vger.kernel.org; linux- > te...@vger.kernel.org; linux-kernel@vger.kernel.org; Krishna Yarlagadda > > Subject: Re: [Patch v1 0/4] Add Nvidia Tegra GPC-DMA driver > > On Mon, Jul 20, 2020 at 12:04:12PM +0530, Rajesh Gumasta wrote: > > Add support for Nvida Tegra general purpose DMA driver for > > Tegra186 and Tegra194 platform. > > > > Patch 1: Add dt-binding document for Tegra GPCDMA driver Patch 2: Add > > Tegra GPCDMA driver Patch 3: Enable Tegra GPCDMA as module Patch 4: > > Add GPCDMA DT node for Tegra186 and Tegra194 > > > > Rajesh Gumasta (4): > > dt-bindings: dma: Add DT binding document > > dma: tegra: Adding Tegra GPC DMA controller driver > > arm64: configs: enable tegra gpc dma > > arm64: tegra: Add GPCDMA node in dt > > > > .../bindings/dma/nvidia,tegra-gpc-dma.yaml | 99 ++ > > arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi |4 + > > arch/arm64/boot/dts/nvidia/tegra186.dtsi | 46 + > > arch/arm64/boot/dts/nvidia/tegra194.dtsi | 44 + > > arch/arm64/configs/defconfig |1 + > > drivers/dma/Kconfig| 12 + > > drivers/dma/Makefile |1 + > > drivers/dma/tegra-gpc-dma.c| 1512 > > > > 8 files changed, 1719 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/dma/nvidia,tegra-gpc-dma.yaml > > create mode 100644 drivers/dma/tegra-gpc-dma.c > > Hi Rajesh, > > can you provide instructions on how to test that this driver does what it's > supposed to? I could probably figure out how to run this with the kernel's > built-in > dmatest module, but if you could provide a set of parameters that you've used > or other instructions on how to validate this it would greatly help. > I have used below parameter setting with kernel's built-in dmatest module to test mem to mem copy cd /sys/module/dmatest/parameters echo 5 > iterations echo dma0chan20 > channel echo 1 > run > Thanks, > Thierry > > > > > -- > > 2.7.4 > > Thanks Rajesh Gumasta
[Patch v1 4/4] arm64: tegra: Add GPCDMA node in dt
Add device tree node for GPCDMA controller on Tegra186 target
and Tegra194 target.
Signed-off-by: Rajesh Gumasta
---
arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 4 +++
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 46 ++
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 44
3 files changed, 94 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
index 2fcaa2e..56ed8d8 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
@@ -54,6 +54,10 @@
};
};
+ dma@260 {
+ status = "okay";
+ };
+
memory-controller@2c0 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 58100fb..91bb17e 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -70,6 +70,52 @@
snps,rxpbl = <8>;
};
+ gpcdma: dma@260 {
+ compatible = "nvidia,tegra186-gpcdma";
+ reg = <0x0 0x260 0x0 0x21>;
+ resets = < TEGRA186_RESET_GPCDMA>;
+ reset-names = "gpcdma";
+ interrupts = ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ;
+ #dma-cells = <1>;
+ iommus = < TEGRA186_SID_GPCDMA_0>;
+ dma-coherent;
+ nvidia,start-dma-channel-index = <1>;
+ dma-channels = <31>;
+ status = "disabled";
+ };
+
aconnect {
compatible = "nvidia,tegra186-aconnect",
"nvidia,tegra210-aconnect";
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index 4bc187a..0bd67bd 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -68,6 +68,50 @@
snps,rxpbl = <8>;
};
+ gpcdma: dma@260 {
+ compatible = "nvidia,tegra194-gpcdma";
+ reg = <0x0 0x260 0x0 0x21>;
+
[Patch v1 1/4] dt-bindings: dma: Add DT binding document
Add DT binding document for Nvidia Tegra GPCDMA controller.
Signed-off-by: Rajesh Gumasta
---
.../bindings/dma/nvidia,tegra-gpc-dma.yaml | 99 ++
1 file changed, 99 insertions(+)
create mode 100644
Documentation/devicetree/bindings/dma/nvidia,tegra-gpc-dma.yaml
diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra-gpc-dma.yaml
b/Documentation/devicetree/bindings/dma/nvidia,tegra-gpc-dma.yaml
new file mode 100644
index 000..39827ab
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/nvidia,tegra-gpc-dma.yaml
@@ -0,0 +1,99 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/nvidia,tegra-gpc-dma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Nvidia Tegra GPC DMA Controller Device Tree Bindings
+
+description: |
+ Tegra GPC DMA controller is a general purpose dma used for faster data
+ transfers between memory to memory, memory to device and device to memory.
+ Terms 'dma' and 'gpcdma' can be used interchangeably.
+
+maintainers:
+ - Jon Hunter
+ - Rajesh Gumasta
+
+allOf:
+ - $ref: "dma-controller.yaml#"
+
+properties:
+ "#dma-cells":
+const: 1
+
+ compatible:
+- enum:
+ - nvidia,tegra186-gpcdma
+ - nvidia,tegra194-gpcdma
+
+ reg:
+maxItems: 1
+
+ interrupts:
+maxItems: 1
+
+ resets:
+maxItems: 1
+
+ reset-names:
+const: gpcdma
+
+ iommus:
+maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - resets
+ - reset-names
+ - "#dma-cells"
+ - iommus
+
+examples:
+ - |
+gpcdma: dma@260 {
+ compatible = "nvidia,tegra186-gpcdma";
+ reg = <0x0 0x260 0x0 0x21>;
+ resets = < TEGRA186_RESET_GPCDMA>;
+ reset-names = "gpcdma";
+ interrupts = ;
+ #dma-cells = <1>;
+ iommus = < TEGRA_SID_GPCDMA_0>;
+ dma-coherent;
+ };
+
+...
--
2.7.4
[Patch v1 2/4] dma: tegra: Adding Tegra GPC DMA controller driver
v4 changes: Removed pending dma desc list and other unused data structures v3 changes: Removed free list for dma_desc and sg Adding GPC DMA controller driver for Tegra186 and Tegra194. The driver supports dma transfers between memory to memory, IO to memory and memory to IO. Signed-off-by: Pavan Kunapuli Signed-off-by: Rajesh Gumasta --- drivers/dma/Kconfig | 12 + drivers/dma/Makefile|1 + drivers/dma/tegra-gpc-dma.c | 1512 +++ 3 files changed, 1525 insertions(+) create mode 100644 drivers/dma/tegra-gpc-dma.c diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index e9ed916..be4c395 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -639,6 +639,18 @@ config TEGRA210_ADMA peripheral and vice versa. It does not support memory to memory data transfer. +config TEGRA_GPC_DMA + tristate "NVIDIA Tegra GPC DMA support" + depends on ARCH_TEGRA_186_SOC || ARCH_TEGRA_194_SOC || COMPILE_TEST + select DMA_ENGINE + help + Support for the NVIDIA Tegra186 and Tegra194 GPC DMA controller + driver. The DMA controller is having multiple DMA channel which + can be configured for different peripherals like UART, SPI, etc + which are on APB bus. + This DMA controller transfers data from memory to peripheral fifo + or vice versa. It also supports memory to memory data transfer. + config TIMB_DMA tristate "Timberdale FPGA DMA support" depends on MFD_TIMBERDALE || COMPILE_TEST diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index e60f813..43e3a6e 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -76,6 +76,7 @@ obj-$(CONFIG_S3C24XX_DMAC) += s3c24xx-dma.o obj-$(CONFIG_TXX9_DMAC) += txx9dmac.o obj-$(CONFIG_TEGRA20_APB_DMA) += tegra20-apb-dma.o obj-$(CONFIG_TEGRA210_ADMA) += tegra210-adma.o +obj-$(CONFIG_TEGRA_GPC_DMA) += tegra-gpc-dma.o obj-$(CONFIG_TIMB_DMA) += timb_dma.o obj-$(CONFIG_UNIPHIER_MDMAC) += uniphier-mdmac.o obj-$(CONFIG_UNIPHIER_XDMAC) += uniphier-xdmac.o diff --git a/drivers/dma/tegra-gpc-dma.c b/drivers/dma/tegra-gpc-dma.c new file mode 100644 index 000..92b7219 --- /dev/null +++ b/drivers/dma/tegra-gpc-dma.c @@ -0,0 +1,1512 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * DMA driver for Nvidia's Tegra186 and Tegra194 GPC DMA controller. + * + * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "virt-dma.h" + +/* CSR register */ +#define TEGRA_GPCDMA_CHAN_CSR 0x00 +#define TEGRA_GPCDMA_CSR_ENB BIT(31) +#define TEGRA_GPCDMA_CSR_IE_EOCBIT(30) +#define TEGRA_GPCDMA_CSR_ONCE BIT(27) +#define TEGRA_GPCDMA_CSR_FC_MODE_NO_MMIO (0 << 24) +#define TEGRA_GPCDMA_CSR_FC_MODE_ONE_MMIO (1 << 24) +#define TEGRA_GPCDMA_CSR_FC_MODE_TWO_MMIO (2 << 24) +#define TEGRA_GPCDMA_CSR_FC_MODE_FOUR_MMIO (3 << 24) +#define TEGRA_GPCDMA_CSR_DMA_IO2MEM_NO_FC (0 << 21) +#define TEGRA_GPCDMA_CSR_DMA_IO2MEM_FC (1 << 21) +#define TEGRA_GPCDMA_CSR_DMA_MEM2IO_NO_FC (2 << 21) +#define TEGRA_GPCDMA_CSR_DMA_MEM2IO_FC (3 << 21) +#define TEGRA_GPCDMA_CSR_DMA_MEM2MEM (4 << 21) +#define TEGRA_GPCDMA_CSR_DMA_FIXED_PAT (6 << 21) +#define TEGRA_GPCDMA_CSR_REQ_SEL_SHIFT 16 +#define TEGRA_GPCDMA_CSR_REQ_SEL_MASK 0x1F +#define TEGRA_GPCDMA_CSR_REQ_SEL_UNUSED0x4 +#define TEGRA_GPCDMA_CSR_IRQ_MASK BIT(15) +#define TEGRA_GPCDMA_CSR_WEIGHT_SHIFT 10 + +/* STATUS register */ +#define TEGRA_GPCDMA_CHAN_STATUS 0x004 +#define TEGRA_GPCDMA_STATUS_BUSY BIT(31) +#define TEGRA_GPCDMA_STATUS_ISE_EOCBIT(30) +#define TEGRA_GPCDMA_STATUS_PING_PONG BIT(28) +#define TEGRA_GPCDMA_STATUS_DMA_ACTIVITY BIT(27) +#define TEGRA_GPCDMA_STATUS_CHANNEL_PAUSE BIT(26) +#define TEGRA_GPCDMA_STATUS_CHANNEL_RX BIT(25) +#define TEGRA_GPCDMA_STATUS_CHANNEL_TX BIT(24) +#define TEGRA_GPCDMA_STATUS_IRQ_INTR_STA BIT(23) +#define TEGRA_GPCDMA_STATUS_IRQ_STABIT(21) +#define TEGRA_GPCDMA_STATUS_IRQ_TRIG_STA BIT(20) + +#define TEGRA_GPCDMA_CHAN_CSRE 0x008 +#define TEGRA_GPCDMA_CHAN_CSRE_PAUSE BIT(31) + +/* Source address */ +#define TEGRA_GPCDMA_CHAN_SRC_PTR 0x00C + +/* Destination address */ +#define TEGRA_GPCDMA_CHAN_DST_PTR 0x010 + +/* High address pointer */ +#define TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR0x014 +#define TEGRA_GPCDMA_HIGH_ADDR_SCR_PTR_SHIFT 0 +#define TEGRA_GPCDMA_
[Patch v1 0/4] Add Nvidia Tegra GPC-DMA driver
Add support for Nvida Tegra general purpose DMA driver for Tegra186 and Tegra194 platform. Patch 1: Add dt-binding document for Tegra GPCDMA driver Patch 2: Add Tegra GPCDMA driver Patch 3: Enable Tegra GPCDMA as module Patch 4: Add GPCDMA DT node for Tegra186 and Tegra194 Rajesh Gumasta (4): dt-bindings: dma: Add DT binding document dma: tegra: Adding Tegra GPC DMA controller driver arm64: configs: enable tegra gpc dma arm64: tegra: Add GPCDMA node in dt .../bindings/dma/nvidia,tegra-gpc-dma.yaml | 99 ++ arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi |4 + arch/arm64/boot/dts/nvidia/tegra186.dtsi | 46 + arch/arm64/boot/dts/nvidia/tegra194.dtsi | 44 + arch/arm64/configs/defconfig |1 + drivers/dma/Kconfig| 12 + drivers/dma/Makefile |1 + drivers/dma/tegra-gpc-dma.c| 1512 8 files changed, 1719 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/nvidia,tegra-gpc-dma.yaml create mode 100644 drivers/dma/tegra-gpc-dma.c -- 2.7.4
[Patch v1 3/4] arm64: configs: enable tegra gpc dma
Enable TEGRA_GPC_DMA in defconfig for Tegra186 and Tegra196 gpc dma controller driver Signed-off-by: Rajesh Gumasta --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 883e8ba..600f568 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -775,6 +775,7 @@ CONFIG_MV_XOR_V2=y CONFIG_OWL_DMA=y CONFIG_PL330_DMA=y CONFIG_TEGRA20_APB_DMA=y +CONFIG_TEGRA_GPC_DMA=m CONFIG_QCOM_BAM_DMA=y CONFIG_QCOM_HIDMA_MGMT=y CONFIG_QCOM_HIDMA=y -- 2.7.4
