Hi Mark,
> -Original Message-
> From: Mark Brown [mailto:broo...@kernel.org]
> Sent: Thursday, September 03, 2015 5:43 PM
> To: Ranjit Abhimanyu Waghmode
> Cc: dw...@infradead.org; computersforpe...@gmail.com; Michal Simek;
> Soren Brinkmann; zaj...@gmail.com; b...@d
Hi Mark,
> -Original Message-
> From: Mark Brown [mailto:broo...@kernel.org]
> Sent: Thursday, September 03, 2015 5:43 PM
> To: Ranjit Abhimanyu Waghmode
> Cc: dw...@infradead.org; computersforpe...@gmail.com; Michal Simek;
> Soren Brinkmann; zaj...@gmail.com; b...@d
Hi,
> -Original Message-
> From: Marek Vasut [mailto:ma...@denx.de]
> Sent: Thursday, September 03, 2015 12:26 AM
> To: Ranjit Abhimanyu Waghmode
> Cc: dw...@infradead.org; computersforpe...@gmail.com;
> broo...@kernel.org; Michal Simek; Soren Brinkmann; zaj
Hi,
> -Original Message-
> From: Marek Vasut [mailto:ma...@denx.de]
> Sent: Thursday, September 03, 2015 12:26 AM
> To: Ranjit Abhimanyu Waghmode
> Cc: dw...@infradead.org; computersforpe...@gmail.com;
> broo...@kernel.org; Michal Simek; Soren Brinkmann; zaj
Hi Marek,
> -Original Message-
> From: Marek Vasut [mailto:ma...@denx.de]
> Sent: Wednesday, August 26, 2015 12:26 PM
> To: Ranjit Abhimanyu Waghmode
> Cc: dw...@infradead.org; computersforpe...@gmail.com;
> broo...@kernel.org; Michal Simek; Soren Brinkmann; zaj
Hi Marek,
> -Original Message-
> From: Marek Vasut [mailto:ma...@denx.de]
> Sent: Wednesday, August 26, 2015 12:26 PM
> To: Ranjit Abhimanyu Waghmode
> Cc: dw...@infradead.org; computersforpe...@gmail.com;
> broo...@kernel.org; Michal Simek; Soren Brinkmann; zaj
Hi Mark,
> -Original Message-
> From: Mark Brown [mailto:broo...@kernel.org]
> Sent: Monday, August 03, 2015 9:38 PM
> To: Ranjit Abhimanyu Waghmode
> Cc: dw...@infradead.org; computersforpe...@gmail.com; Michal Simek;
> Soren Brinkmann; zaj...@gmail.com; b...@d
Hi Mark,
-Original Message-
From: Mark Brown [mailto:broo...@kernel.org]
Sent: Monday, August 03, 2015 9:38 PM
To: Ranjit Abhimanyu Waghmode
Cc: dw...@infradead.org; computersforpe...@gmail.com; Michal Simek;
Soren Brinkmann; zaj...@gmail.com; b...@decadent.org.uk; ma...@denx.de
Hi Mark,
> -Original Message-
> From: Mark Brown [mailto:broo...@kernel.org]
> Sent: Friday, July 24, 2015 4:22 PM
> To: Ranjit Abhimanyu Waghmode
> Cc: Michal Simek; Soren Brinkmann; zaj...@gmail.com; ma...@denx.de;
> shijie.hu...@intel.com; juh...@openwrt.org; b.
Hi Mark,
-Original Message-
From: Mark Brown [mailto:broo...@kernel.org]
Sent: Friday, July 24, 2015 4:22 PM
To: Ranjit Abhimanyu Waghmode
Cc: Michal Simek; Soren Brinkmann; zaj...@gmail.com; ma...@denx.de;
shijie.hu...@intel.com; juh...@openwrt.org; b...@decadent.org.uk; linux-
m
Hi Mark,
> > > For an example take two flashes connected in stacked mode.
> > > For user it doesn't matter whether how many flashes are really connected.
> > > There will be situation like, single partition is spread across two
> > > flashes
> > (partition staring at the end of one flash and
Hi Mark,
For an example take two flashes connected in stacked mode.
For user it doesn't matter whether how many flashes are really connected.
There will be situation like, single partition is spread across two
flashes
(partition staring at the end of one flash and continued to the
Hi,
> -Original Message-
> From: Mark Brown [mailto:broo...@kernel.org]
> Sent: Thursday, July 16, 2015 2:28 PM
> To: Ranjit Abhimanyu Waghmode
> Cc: Michal Simek; Soren Brinkmann; dw...@infradead.org;
> computersforpe...@gmail.com; zaj...@gmail.com; ma...@de
Hi,
-Original Message-
From: Mark Brown [mailto:broo...@kernel.org]
Sent: Thursday, July 16, 2015 2:28 PM
To: Ranjit Abhimanyu Waghmode
Cc: Michal Simek; Soren Brinkmann; dw...@infradead.org;
computersforpe...@gmail.com; zaj...@gmail.com; ma...@denx.de;
shijie.hu...@intel.com; juh
Hi Mark,
> > > > What is stacked mode?
> > > > -
> > > > ZynqMP GQSPI controller supports stacked mode with following
> > > functionalities:
> > > > 1) The Generic Quad-SPI controller also supports two SPI flash memories
> > > >in a shared bus arrangement to reduce IO pin
Hi Mark,
What is stacked mode?
-
ZynqMP GQSPI controller supports stacked mode with following
functionalities:
1) The Generic Quad-SPI controller also supports two SPI flash memories
in a shared bus arrangement to reduce IO pin count.
2) Separate
Hi Mark,
> > What is dual parallel mode?
> > ---
> > ZynqMP GQSPI controller supports Dual Parallel mode with following
> functionalities:
> > 1) Supporting two SPI flash memories operating in parallel. 8 I/O lines.
> > 2) Chip selects and clock are shared to both the
Hi Mark,
What is dual parallel mode?
---
ZynqMP GQSPI controller supports Dual Parallel mode with following
functionalities:
1) Supporting two SPI flash memories operating in parallel. 8 I/O lines.
2) Chip selects and clock are shared to both the flash devices
Acked-by: Ranjit Waghmode
> -Original Message-
> From: Geert Uytterhoeven [mailto:ge...@linux-m68k.org]
> Sent: Friday, June 26, 2015 5:37 PM
> To: Mark Brown; Ranjit Abhimanyu Waghmode
> Cc: linux-...@vger.kernel.org; linux-kernel@vger.kernel.org; Geert
> Uytterhoeven
Acked-by: Ranjit Waghmode ranj...@xilinx.com
-Original Message-
From: Geert Uytterhoeven [mailto:ge...@linux-m68k.org]
Sent: Friday, June 26, 2015 5:37 PM
To: Mark Brown; Ranjit Abhimanyu Waghmode
Cc: linux-...@vger.kernel.org; linux-kernel@vger.kernel.org; Geert
Uytterhoeven
Hi Soren,
> > .../devicetree/bindings/spi/spi-zynqmp-qspi.txt| 26
> ++
> > 1 file changed, 26 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.txt
> >
> > diff --git
if (!master)
> > + return -ENOMEM;
> > +
> > + xqspi = spi_master_get_devdata(master);
> > + master->dev.of_node = pdev->dev.of_node;
> > + platform_set_drvdata(pdev, master);
> > +
> > + res = platform_get_resource(pdev, I
,
+ },
+};
+
+module_platform_driver(zynqmp_qspi_driver);
+
+MODULE_AUTHOR(Xilinx, Inc.);
+MODULE_DESCRIPTION(Xilinx Zynqmp QSPI driver);
+MODULE_LICENSE(GPL);
--
2.1.2
Thanks for your review.
Regards,
Ranjit Abhimanyu Waghmode,
ranjit.waghm...@xilinx.com
This email and any
Hi Soren,
.../devicetree/bindings/spi/spi-zynqmp-qspi.txt| 26
++
1 file changed, 26 insertions(+)
create mode 100644
Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.txt
diff --git a/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.txt
Hi Soren,
Sorry for being late for this reply as this thread is moved a step ahead.
On Wed, 2015-05-20 at 12:57PM +0530, Ranjit Waghmode wrote:
> This patch adds support for GQSPI controller driver used by Zynq
> Ultrascale+ MPSoC
>
> Signed-off-by: Ranjit Waghmode
> ---
[...]
> +/**
> + *
Hi Soren,
Sorry for being late for this reply as this thread is moved a step ahead.
On Wed, 2015-05-20 at 12:57PM +0530, Ranjit Waghmode wrote:
This patch adds support for GQSPI controller driver used by Zynq
Ultrascale+ MPSoC
Signed-off-by: Ranjit Waghmode ranjit.waghm...@xilinx.com
---
Hi Soren,
On Wed, 2015-05-20 at 12:57PM +0530, Ranjit Waghmode wrote:
> Add bindings documentation for GQSPI controller driver used by Zynq
> Ultrascale+ MPSoC
>
> Signed-off-by: Ranjit Waghmode
> ---
> .../devicetree/bindings/spi/spi-zynqmp-qspi.txt| 26
> ++
> 1
Hi Soren,
On Wed, 2015-05-20 at 12:57PM +0530, Ranjit Waghmode wrote:
Add bindings documentation for GQSPI controller driver used by Zynq
Ultrascale+ MPSoC
Signed-off-by: Ranjit Waghmode ranjit.waghm...@xilinx.com
---
.../devicetree/bindings/spi/spi-zynqmp-qspi.txt| 26
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