Thanks for your comments.
> What I think Rafał is saying is that it would be better to have this
> code in cfg80211 so other drivers including mac80211 could use it.
While I agree that moving all wireless LED triggers to cfg80211 would be an
ideal situation, it seems a bit out of scope for what
Thanks for your comments.
> What I think Rafał is saying is that it would be better to have this
> code in cfg80211 so other drivers including mac80211 could use it.
While I agree that moving all wireless LED triggers to cfg80211 would be an
ideal situation, it seems a bit out of scope for what
Miłecki <zaj...@gmail.com> wrote:
>
> On 7 July 2017 at 16:09, Russell Joyce <russell.jo...@york.ac.uk> wrote:
>> Add three basic LED triggers to brcmfmac, based on those in mac80211: one
>> for transmit, one for receive, and one for combined transmit/receive.
>&g
Miłecki wrote:
>
> On 7 July 2017 at 16:09, Russell Joyce wrote:
>> Add three basic LED triggers to brcmfmac, based on those in mac80211: one
>> for transmit, one for receive, and one for combined transmit/receive.
>>
>> Signed-off-by: Russell Joyce
>
> 1) I
Add three basic LED triggers to brcmfmac, based on those in mac80211: one
for transmit, one for receive, and one for combined transmit/receive.
Signed-off-by: Russell Joyce <russell.jo...@york.ac.uk>
---
drivers/net/wireless/broadcom/brcm80211/Kconfig| 12 +++
.../wireless/br
Add three basic LED triggers to brcmfmac, based on those in mac80211: one
for transmit, one for receive, and one for combined transmit/receive.
Signed-off-by: Russell Joyce
---
drivers/net/wireless/broadcom/brcm80211/Kconfig| 12 +++
.../wireless/broadcom/brcm80211/brcmfmac/Makefile | 2
be checked before handling
INTx interrupts.
> On 14 Jul 2015, at 23:24, Bjorn Helgaas wrote:
>
> On Tue, Jul 07, 2015 at 05:54:19PM +0100, Russell Joyce wrote:
>> Occasionally both MSI and INTx bits in the interrupt decode register are
>> set at once by the Xilinx AXI PCIe Br
be checked before handling
INTx interrupts.
On 14 Jul 2015, at 23:24, Bjorn Helgaas bhelg...@google.com wrote:
On Tue, Jul 07, 2015 at 05:54:19PM +0100, Russell Joyce wrote:
Occasionally both MSI and INTx bits in the interrupt decode register are
set at once by the Xilinx AXI PCIe Bridge, so
handler will be used erroneously when both type bits are set.
This will also be followed by a second read of the message FIFO, which can
result in the function returning early and the interrupt decode register
not being cleared if the FIFO is now empty.
Signed-off-by: Russell Joyce
---
drivers
handler will be used erroneously when both type bits are set.
This will also be followed by a second read of the message FIFO, which can
result in the function returning early and the interrupt decode register
not being cleared if the FIFO is now empty.
Signed-off-by: Russell Joyce russell.jo
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