from:"Sergio Paracuellos"

Vendor listed for mediatek in kernel vendor file 'vendor-prefixes.yaml'
contains 'mediatek' as a valid vendor string. Some nodes in the device
tree are using an invalid vendor string vfor 'mtk' instead. Fix all of
them in dts file. Update also ralink mt7621 related code to properly
match new strings. Even there are used in the device tree there are
some strings that are not referred anywhere but have been also updated
with new vendor name. These are 'mtk,mt7621-wdt', 'mtk,mt7621-nand',
'mtk,mt7621-mc', and 'mtk,mt7621-cpc'.

Acked-by: Greg Kroah-Hartman 
Acked-by: Thomas Bogendoerfer 
Signed-off-by: Sergio Paracuellos 
---
 arch/mips/ralink/mt7621.c  |  6 +++---
 drivers/staging/mt7621-dts/mt7621.dtsi | 12 ++--
 2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/arch/mips/ralink/mt7621.c b/arch/mips/ralink/mt7621.c
index 6b3db98894cb..f82ad2a621f6 100644
--- a/arch/mips/ralink/mt7621.c
+++ b/arch/mips/ralink/mt7621.c
@@ -136,8 +136,8 @@ static void __init mt7621_memory_detect(void)
 
 void __init ralink_of_remap(void)
 {
-   rt_sysc_membase = plat_of_remap_node("mtk,mt7621-sysc");
-   rt_memc_membase = plat_of_remap_node("mtk,mt7621-memc");
+   rt_sysc_membase = plat_of_remap_node("mediatek,mt7621-sysc");
+   rt_memc_membase = plat_of_remap_node("mediatek,mt7621-memc");
 
if (!rt_sysc_membase || !rt_memc_membase)
panic("Failed to remap core resources");
@@ -205,7 +205,7 @@ void __init prom_soc_init(struct ralink_soc_info *soc_info)
 
if (n0 == MT7621_CHIP_NAME0 && n1 == MT7621_CHIP_NAME1) {
name = "MT7621";
-   soc_info->compatible = "mtk,mt7621-soc";
+   soc_info->compatible = "mediatek,mt7621-soc";
} else {
panic("mt7621: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
}
diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi 
b/drivers/staging/mt7621-dts/mt7621.dtsi
index b68183e7e6ad..f0c9ae757bcd 100644
--- a/drivers/staging/mt7621-dts/mt7621.dtsi
+++ b/drivers/staging/mt7621-dts/mt7621.dtsi
@@ -56,7 +56,7 @@ palmbus: palmbus@1E00 {
#size-cells = <1>;
 
sysc: sysc@0 {
-   compatible = "mtk,mt7621-sysc", "syscon";
+   compatible = "mediatek,mt7621-sysc", "syscon";
reg = <0x0 0x100>;
#clock-cells = <1>;
ralink,memctl = <>;
@@ -66,7 +66,7 @@ sysc: sysc@0 {
};
 
wdt: wdt@100 {
-   compatible = "mtk,mt7621-wdt";
+   compatible = "mediatek,mt7621-wdt";
reg = <0x100 0x100>;
};
 
@@ -123,17 +123,17 @@ i2s: i2s@a00 {
};
 
memc: memc@5000 {
-   compatible = "mtk,mt7621-memc", "syscon";
+   compatible = "mediatek,mt7621-memc", "syscon";
reg = <0x5000 0x1000>;
};
 
cpc: cpc@1fbf {
-compatible = "mtk,mt7621-cpc";
+compatible = "mediatek,mt7621-cpc";
 reg = <0x1fbf 0x8000>;
};
 
mc: mc@1fbf8000 {
-   compatible = "mtk,mt7621-mc";
+   compatible = "mediatek,mt7621-mc";
reg = <0x1fbf8000 0x8000>;
};
 
@@ -361,7 +361,7 @@ timer {
nand: nand@1e003000 {
status = "disabled";
 
-   compatible = "mtk,mt7621-nand";
+   compatible = "mediatek,mt7621-nand";
bank-width = <2>;
reg = <0x1e003000 0x800
0x1e003800 0x800>;
-- 
2.25.1

[PATCH v13 4/4] MAINTAINERS: add MT7621 CLOCK maintainer

Adding myself as maintainer for mt7621 clock driver.

Signed-off-by: Sergio Paracuellos 
---
 MAINTAINERS | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 4d68184d3f76..02986055fdbc 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11484,6 +11484,12 @@ L: linux-wirel...@vger.kernel.org
 S: Maintained
 F: drivers/net/wireless/mediatek/mt7601u/
 
+MEDIATEK MT7621 CLOCK DRIVER
+M: Sergio Paracuellos 
+S: Maintained
+F: Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml
+F: drivers/clk/ralink/clk-mt7621.c
+
 MEDIATEK MT7621/28/88 I2C DRIVER
 M: Stefan Roese 
 L: linux-...@vger.kernel.org
-- 
2.25.1

[PATCH v13 1/4] clk: ralink: add clock driver for mt7621 SoC

The documentation for this SOC only talks about two
registers regarding to the clocks:
* SYSC_REG_CPLL_CLKCFG0 - provides some information about
boostrapped refclock. PLL and dividers used for CPU and some
sort of BUS.
* SYSC_REG_CPLL_CLKCFG1 - a banch of gates to enable/disable
clocks for all or some ip cores.

Looking into driver code, and some openWRT patched there are
another frequencies which are used in some drivers (uart, sd...).
According to all of this information the clock plan for this
SoC is set as follows:
- Main top clock "xtal" from where all the rest of the world is
derived.
- CPU clock "cpu" derived from "xtal" frequencies and a bunch of
register reads and predividers.
- BUS clock "bus" derived from "cpu" and with (cpu / 4) MHz.
- Fixed clocks from "xtal":
* "50m": 50 MHz.
* "125m": 125 MHz.
* "150m": 150 MHz.
* "250m": 250 MHz.
* "270m": 270 MHz.

We also have a buch of gate clocks with their parents:
  * "hsdma": "150m"
  * "fe": "250m"
  * "sp_divtx": "270m"
  * "timer": "50m"
  * "pcm": "270m"
  * "pio": "50m"
  * "gdma": "bus"
  * "nand": "125m"
  * "i2c": "50m"
  * "i2s": "270m"
  * "spi": "bus"
  * "uart1": "50m"
  * "uart2": "50m"
  * "uart3": "50m"
  * "eth": "50m"
  * "pcie0": "125m"
  * "pcie1": "125m"
  * "pcie2": "125m"
  * "crypto": "250m"
  * "shxc": "50m"

With this information the clk driver will provide clock and gates
functionality from a a set of hardcoded clocks allowing to define
a nice device tree without fixed clocks.

Signed-off-by: Sergio Paracuellos 
---
 drivers/clk/Kconfig |   1 +
 drivers/clk/Makefile|   1 +
 drivers/clk/ralink/Kconfig  |  11 +
 drivers/clk/ralink/Makefile |   2 +
 drivers/clk/ralink/clk-mt7621.c | 495 
 5 files changed, 510 insertions(+)
 create mode 100644 drivers/clk/ralink/Kconfig
 create mode 100644 drivers/clk/ralink/Makefile
 create mode 100644 drivers/clk/ralink/clk-mt7621.c

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 1d1891b9cad2..e80918be8e9c 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -390,6 +390,7 @@ source "drivers/clk/meson/Kconfig"
 source "drivers/clk/mstar/Kconfig"
 source "drivers/clk/mvebu/Kconfig"
 source "drivers/clk/qcom/Kconfig"
+source "drivers/clk/ralink/Kconfig"
 source "drivers/clk/renesas/Kconfig"
 source "drivers/clk/rockchip/Kconfig"
 source "drivers/clk/samsung/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 9b582b3fca34..5f06879d7fe9 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -100,6 +100,7 @@ obj-$(CONFIG_COMMON_CLK_NXP)+= nxp/
 obj-$(CONFIG_MACH_PISTACHIO)   += pistachio/
 obj-$(CONFIG_COMMON_CLK_PXA)   += pxa/
 obj-$(CONFIG_COMMON_CLK_QCOM)  += qcom/
+obj-y  += ralink/
 obj-y  += renesas/
 obj-$(CONFIG_ARCH_ROCKCHIP)+= rockchip/
 obj-$(CONFIG_COMMON_CLK_SAMSUNG)   += samsung/
diff --git a/drivers/clk/ralink/Kconfig b/drivers/clk/ralink/Kconfig
new file mode 100644
index ..6580d5edc676
--- /dev/null
+++ b/drivers/clk/ralink/Kconfig
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# MediaTek Mt7621 Clock Driver
+#
+config CLK_MT7621
+   bool "Clock driver for MediaTek MT7621"
+   depends on SOC_MT7621 || COMPILE_TEST
+   default SOC_MT7621
+   select MFD_SYSCON
+   help
+ This driver supports MediaTek MT7621 basic clocks.
diff --git a/drivers/clk/ralink/Makefile b/drivers/clk/ralink/Makefile
new file mode 100644
index ..cf6f9216379d
--- /dev/null
+++ b/drivers/clk/ralink/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_CLK_MT7621) += clk-mt7621.o
diff --git a/drivers/clk/ralink/clk-mt7621.c b/drivers/clk/ralink/clk-mt7621.c
new file mode 100644
index ..857da1e274be
--- /dev/null
+++ b/drivers/clk/ralink/clk-mt7621.c
@@ -0,0 +1,495 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Mediatek MT7621 Clock Driver
+ * Author: Sergio Paracuellos 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* Configuration registers */
+#define SYSC_REG_SYSTEM_CONFIG0 0x10
+#define SYSC_REG_SYSTEM_CONFIG1 0x14
+#define SYSC_REG_CLKCFG0   0x2c
+#define SYSC_REG_CLK

[PATCH v13 2/4] staging: mt7621-dts: make use of new 'mt7621-clk'

Clocks for SoC mt7621 have been properly integrated so there is
no need to declare fixed clocks at all in the device tree. Remove
all of them, add new device tree nodes for mt7621-clk and update
the rest of the nodes to use them.

Acked-by: Greg Kroah-Hartman 
Signed-off-by: Sergio Paracuellos 
---
 drivers/staging/mt7621-dts/gbpc1.dts   | 11 
 drivers/staging/mt7621-dts/mt7621.dtsi | 74 --
 2 files changed, 33 insertions(+), 52 deletions(-)

diff --git a/drivers/staging/mt7621-dts/gbpc1.dts 
b/drivers/staging/mt7621-dts/gbpc1.dts
index a7c0d3115d72..7716d0efe524 100644
--- a/drivers/staging/mt7621-dts/gbpc1.dts
+++ b/drivers/staging/mt7621-dts/gbpc1.dts
@@ -100,17 +100,6 @@ partition@5 {
};
 };
 
- {
-   compatible = "fixed-clock";
-   /* This is normally 1/4 of cpuclock */
-   clock-frequency = <22500>;
-};
-
- {
-   compatible = "fixed-clock";
-   clock-frequency = <9>;
-};
-
  {
pinctrl-names = "default";
pinctrl-0 = <_pins>;
diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi 
b/drivers/staging/mt7621-dts/mt7621.dtsi
index 16fc94f65486..b68183e7e6ad 100644
--- a/drivers/staging/mt7621-dts/mt7621.dtsi
+++ b/drivers/staging/mt7621-dts/mt7621.dtsi
@@ -1,5 +1,6 @@
 #include 
 #include 
+#include 
 
 / {
#address-cells = <1>;
@@ -27,27 +28,6 @@ aliases {
serial0 = 
};
 
-   cpuclock: cpuclock@0 {
-   #clock-cells = <0>;
-   compatible = "fixed-clock";
-
-   /* FIXME: there should be way to detect this */
-   clock-frequency = <88000>;
-   };
-
-   sysclock: sysclock@0 {
-   #clock-cells = <0>;
-   compatible = "fixed-clock";
-
-   /* This is normally 1/4 of cpuclock */
-   clock-frequency = <22000>;
-   };
-
-   mmc_clock: mmc_clock@0 {
-   #clock-cells = <0>;
-   compatible = "fixed-clock";
-   clock-frequency = <4800>;
-   };
 
mmc_fixed_3v3: fixedregulator@0 {
compatible = "regulator-fixed";
@@ -76,8 +56,13 @@ palmbus: palmbus@1E00 {
#size-cells = <1>;
 
sysc: sysc@0 {
-   compatible = "mtk,mt7621-sysc";
+   compatible = "mtk,mt7621-sysc", "syscon";
reg = <0x0 0x100>;
+   #clock-cells = <1>;
+   ralink,memctl = <>;
+   clock-output-names = "xtal", "cpu", "bus",
+"50m", "125m", "150m",
+"250m", "270m";
};
 
wdt: wdt@100 {
@@ -101,8 +86,8 @@ i2c: i2c@900 {
compatible = "mediatek,mt7621-i2c";
reg = <0x900 0x100>;
 
-   clocks = <>;
-
+   clocks = < MT7621_CLK_I2C>;
+   clock-names = "i2c";
resets = < 16>;
reset-names = "i2c";
 
@@ -119,8 +104,8 @@ i2s: i2s@a00 {
compatible = "mediatek,mt7621-i2s";
reg = <0xa00 0x100>;
 
-   clocks = <>;
-
+   clocks = < MT7621_CLK_I2S>;
+   clock-names = "i2s";
resets = < 17>;
reset-names = "i2s";
 
@@ -138,7 +123,7 @@ i2s: i2s@a00 {
};
 
memc: memc@5000 {
-   compatible = "mtk,mt7621-memc";
+   compatible = "mtk,mt7621-memc", "syscon";
reg = <0x5000 0x1000>;
};
 
@@ -156,8 +141,8 @@ uartlite: uartlite@c00 {
compatible = "ns16550a";
reg = <0xc00 0x100>;
 
-   clocks = <>;
-   clock-frequency = <5000>;
+   clocks = < MT7621_CLK_UART1>;
+   clock-names = "uart1";
 
interrupt-parent = <>;
interrupts = ;
@@ -173,7 +158,8 @@ spi0: spi@b00 {
compatible = "ralink,mt7621-spi";
reg = <0xb00 0x100>;
 
-   clocks = <>;
+   clocks = < MT7621_CLK_SPI>;
+

[PATCH v13 0/4] MIPS: ralink: add CPU clock detection and clock driver for MT7621

using the phandle function.
- Properly unregister clocks for the error path of the function
'mt7621_clk_init'.
- Include ARRAY_SIZE of fixed clocks in the 'count' to kzalloc
of 'clk_data'.
- Add new patch changing invalid vendor 'mtk' in favour of 'mediatek'
which is the one listed in 'vendor-prefixes.yaml'. Update mt7621 code
accordly. I have added this patch inside this series because clk
binding is referring syscon node and the string for that node was
with not listed vendor. Hence update and have all of this correct
in the same series.

Changes in v3:
- Fix compilation warnings reported by kernel test robot because of
ignoring return values of 'of_clk_hw_register' in functions
'mt7621_register_top_clocks' and 'mt7621_gate_ops_init'.
- Fix dts file and binding documentation 'clock-output-names'.

Changes in v2:
- Remove the following patches:
* dt: bindings: add mt7621-pll device tree binding documentation.
* MIPS: ralink: add clock device providing cpu/ahb/apb clock for mt7621.
- Move all relevant clock code to 'drivers/clk/ralink/clk-mt7621.c' and
unify there previous 'mt7621-pll' and 'mt7621-clk' into a unique driver
and binding 'mt7621-clk'.
- Driver is not a platform driver anymore and now make use of 'CLK_OF_DECLARE'
because we need clocks available in 'plat_time_init' before setting up
the timer for the GIC.
- Use new fixed clocks as parents for different gates and deriving from 'xtal'
using frequencies in[1].
- Adapt dts file and bindings header and documentation for new changes.
- Change MAINTAINERS file to only contains clk-mt7621.c code and
mediatek,mt7621-clk.yaml file.

[0]: https://www.lkml.org/lkml/2019/7/23/1044
[1]:
https://github.com/981213/linux/commit/2eca1f045e4c3db18c941135464c0d7422ad8133
[2]: https://lkml.org/lkml/2020/12/20/47
[3]:
http://driverdev.linuxdriverproject.org/pipermail/driverdev-devel/2021-February/150772.html

Sergio Paracuellos (4):
clk: ralink: add clock driver for mt7621 SoC
staging: mt7621-dts: make use of new 'mt7621-clk'
staging: mt7621-dts: use valid vendor 'mediatek' instead of invalid
'mtk'
MAINTAINERS: add MT7621 CLOCK maintainer

MAINTAINERS| 6 +
arch/mips/ralink/mt7621.c | 6 +-
drivers/clk/Kconfig| 1 +
drivers/clk/Makefile | 1 +
drivers/clk/ralink/Kconfig | 11 +
drivers/clk/ralink/Makefile| 2 +
drivers/clk/ralink/clk-mt7621.c| 495 +
drivers/staging/mt7621-dts/gbpc1.dts | 11 -
drivers/staging/mt7621-dts/mt7621.dtsi | 82 ++--
9 files changed, 556 insertions(+), 59 deletions(-)
create mode 100644 drivers/clk/ralink/Kconfig
create mode 100644 drivers/clk/ralink/Makefile
create mode 100644 drivers/clk/ralink/clk-mt7621.c

--
2.25.1

[PATCH v12 4/4] MAINTAINERS: add MT7621 CLOCK maintainer

Adding myself as maintainer for mt7621 clock driver.

Signed-off-by: Sergio Paracuellos 
---
 MAINTAINERS | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 809a68af5efd..ecad5d972122 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11288,6 +11288,12 @@ L: linux-wirel...@vger.kernel.org
 S: Maintained
 F: drivers/net/wireless/mediatek/mt7601u/
 
+MEDIATEK MT7621 CLOCK DRIVER
+M: Sergio Paracuellos 
+S: Maintained
+F: Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml
+F: drivers/clk/ralink/clk-mt7621.c
+
 MEDIATEK MT7621/28/88 I2C DRIVER
 M: Stefan Roese 
 L: linux-...@vger.kernel.org
-- 
2.25.1

[PATCH v12 2/4] staging: mt7621-dts: make use of new 'mt7621-clk'

Clocks for SoC mt7621 have been properly integrated so there is
no need to declare fixed clocks at all in the device tree. Remove
all of them, add new device tree nodes for mt7621-clk and update
the rest of the nodes to use them.

Acked-by: Greg Kroah-Hartman 
Signed-off-by: Sergio Paracuellos 
---
 drivers/staging/mt7621-dts/gbpc1.dts   | 11 
 drivers/staging/mt7621-dts/mt7621.dtsi | 74 --
 2 files changed, 33 insertions(+), 52 deletions(-)

diff --git a/drivers/staging/mt7621-dts/gbpc1.dts 
b/drivers/staging/mt7621-dts/gbpc1.dts
index a7c0d3115d72..7716d0efe524 100644
--- a/drivers/staging/mt7621-dts/gbpc1.dts
+++ b/drivers/staging/mt7621-dts/gbpc1.dts
@@ -100,17 +100,6 @@ partition@5 {
};
 };
 
- {
-   compatible = "fixed-clock";
-   /* This is normally 1/4 of cpuclock */
-   clock-frequency = <22500>;
-};
-
- {
-   compatible = "fixed-clock";
-   clock-frequency = <9>;
-};
-
  {
pinctrl-names = "default";
pinctrl-0 = <_pins>;
diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi 
b/drivers/staging/mt7621-dts/mt7621.dtsi
index 16fc94f65486..b68183e7e6ad 100644
--- a/drivers/staging/mt7621-dts/mt7621.dtsi
+++ b/drivers/staging/mt7621-dts/mt7621.dtsi
@@ -1,5 +1,6 @@
 #include 
 #include 
+#include 
 
 / {
#address-cells = <1>;
@@ -27,27 +28,6 @@ aliases {
serial0 = 
};
 
-   cpuclock: cpuclock@0 {
-   #clock-cells = <0>;
-   compatible = "fixed-clock";
-
-   /* FIXME: there should be way to detect this */
-   clock-frequency = <88000>;
-   };
-
-   sysclock: sysclock@0 {
-   #clock-cells = <0>;
-   compatible = "fixed-clock";
-
-   /* This is normally 1/4 of cpuclock */
-   clock-frequency = <22000>;
-   };
-
-   mmc_clock: mmc_clock@0 {
-   #clock-cells = <0>;
-   compatible = "fixed-clock";
-   clock-frequency = <4800>;
-   };
 
mmc_fixed_3v3: fixedregulator@0 {
compatible = "regulator-fixed";
@@ -76,8 +56,13 @@ palmbus: palmbus@1E00 {
#size-cells = <1>;
 
sysc: sysc@0 {
-   compatible = "mtk,mt7621-sysc";
+   compatible = "mtk,mt7621-sysc", "syscon";
reg = <0x0 0x100>;
+   #clock-cells = <1>;
+   ralink,memctl = <>;
+   clock-output-names = "xtal", "cpu", "bus",
+"50m", "125m", "150m",
+"250m", "270m";
};
 
wdt: wdt@100 {
@@ -101,8 +86,8 @@ i2c: i2c@900 {
compatible = "mediatek,mt7621-i2c";
reg = <0x900 0x100>;
 
-   clocks = <>;
-
+   clocks = < MT7621_CLK_I2C>;
+   clock-names = "i2c";
resets = < 16>;
reset-names = "i2c";
 
@@ -119,8 +104,8 @@ i2s: i2s@a00 {
compatible = "mediatek,mt7621-i2s";
reg = <0xa00 0x100>;
 
-   clocks = <>;
-
+   clocks = < MT7621_CLK_I2S>;
+   clock-names = "i2s";
resets = < 17>;
reset-names = "i2s";
 
@@ -138,7 +123,7 @@ i2s: i2s@a00 {
};
 
memc: memc@5000 {
-   compatible = "mtk,mt7621-memc";
+   compatible = "mtk,mt7621-memc", "syscon";
reg = <0x5000 0x1000>;
};
 
@@ -156,8 +141,8 @@ uartlite: uartlite@c00 {
compatible = "ns16550a";
reg = <0xc00 0x100>;
 
-   clocks = <>;
-   clock-frequency = <5000>;
+   clocks = < MT7621_CLK_UART1>;
+   clock-names = "uart1";
 
interrupt-parent = <>;
interrupts = ;
@@ -173,7 +158,8 @@ spi0: spi@b00 {
compatible = "ralink,mt7621-spi";
reg = <0xb00 0x100>;
 
-   clocks = <>;
+   clocks = < MT7621_CLK_SPI>;
+

[PATCH v12 3/4] staging: mt7621-dts: use valid vendor 'mediatek' instead of invalid 'mtk'

Vendor listed for mediatek in kernel vendor file 'vendor-prefixes.yaml'
contains 'mediatek' as a valid vendor string. Some nodes in the device
tree are using an invalid vendor string vfor 'mtk' instead. Fix all of
them in dts file. Update also ralink mt7621 related code to properly
match new strings. Even there are used in the device tree there are
some strings that are not referred anywhere but have been also updated
with new vendor name. These are 'mtk,mt7621-wdt', 'mtk,mt7621-nand',
'mtk,mt7621-mc', and 'mtk,mt7621-cpc'.

Acked-by: Greg Kroah-Hartman 
Acked-by: Thomas Bogendoerfer 
Signed-off-by: Sergio Paracuellos 
---
 arch/mips/ralink/mt7621.c  |  6 +++---
 drivers/staging/mt7621-dts/mt7621.dtsi | 12 ++--
 2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/arch/mips/ralink/mt7621.c b/arch/mips/ralink/mt7621.c
index ca0ac607b0f3..5d74fc1c96ac 100644
--- a/arch/mips/ralink/mt7621.c
+++ b/arch/mips/ralink/mt7621.c
@@ -112,8 +112,8 @@ phys_addr_t mips_cpc_default_phys_base(void)
 
 void __init ralink_of_remap(void)
 {
-   rt_sysc_membase = plat_of_remap_node("mtk,mt7621-sysc");
-   rt_memc_membase = plat_of_remap_node("mtk,mt7621-memc");
+   rt_sysc_membase = plat_of_remap_node("mediatek,mt7621-sysc");
+   rt_memc_membase = plat_of_remap_node("mediatek,mt7621-memc");
 
if (!rt_sysc_membase || !rt_memc_membase)
panic("Failed to remap core resources");
@@ -181,7 +181,7 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
 
if (n0 == MT7621_CHIP_NAME0 && n1 == MT7621_CHIP_NAME1) {
name = "MT7621";
-   soc_info->compatible = "mtk,mt7621-soc";
+   soc_info->compatible = "mediatek,mt7621-soc";
} else {
panic("mt7621: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
}
diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi 
b/drivers/staging/mt7621-dts/mt7621.dtsi
index b68183e7e6ad..f0c9ae757bcd 100644
--- a/drivers/staging/mt7621-dts/mt7621.dtsi
+++ b/drivers/staging/mt7621-dts/mt7621.dtsi
@@ -56,7 +56,7 @@ palmbus: palmbus@1E00 {
#size-cells = <1>;
 
sysc: sysc@0 {
-   compatible = "mtk,mt7621-sysc", "syscon";
+   compatible = "mediatek,mt7621-sysc", "syscon";
reg = <0x0 0x100>;
#clock-cells = <1>;
ralink,memctl = <>;
@@ -66,7 +66,7 @@ sysc: sysc@0 {
};
 
wdt: wdt@100 {
-   compatible = "mtk,mt7621-wdt";
+   compatible = "mediatek,mt7621-wdt";
reg = <0x100 0x100>;
};
 
@@ -123,17 +123,17 @@ i2s: i2s@a00 {
};
 
memc: memc@5000 {
-   compatible = "mtk,mt7621-memc", "syscon";
+   compatible = "mediatek,mt7621-memc", "syscon";
reg = <0x5000 0x1000>;
};
 
cpc: cpc@1fbf {
-compatible = "mtk,mt7621-cpc";
+compatible = "mediatek,mt7621-cpc";
 reg = <0x1fbf 0x8000>;
};
 
mc: mc@1fbf8000 {
-   compatible = "mtk,mt7621-mc";
+   compatible = "mediatek,mt7621-mc";
reg = <0x1fbf8000 0x8000>;
};
 
@@ -361,7 +361,7 @@ timer {
nand: nand@1e003000 {
status = "disabled";
 
-   compatible = "mtk,mt7621-nand";
+   compatible = "mediatek,mt7621-nand";
bank-width = <2>;
reg = <0x1e003000 0x800
0x1e003800 0x800>;
-- 
2.25.1

[PATCH v12 1/4] clk: ralink: add clock driver for mt7621 SoC

The documentation for this SOC only talks about two
registers regarding to the clocks:
* SYSC_REG_CPLL_CLKCFG0 - provides some information about
boostrapped refclock. PLL and dividers used for CPU and some
sort of BUS.
* SYSC_REG_CPLL_CLKCFG1 - a banch of gates to enable/disable
clocks for all or some ip cores.

Looking into driver code, and some openWRT patched there are
another frequencies which are used in some drivers (uart, sd...).
According to all of this information the clock plan for this
SoC is set as follows:
- Main top clock "xtal" from where all the rest of the world is
derived.
- CPU clock "cpu" derived from "xtal" frequencies and a bunch of
register reads and predividers.
- BUS clock "bus" derived from "cpu" and with (cpu / 4) MHz.
- Fixed clocks from "xtal":
* "50m": 50 MHz.
* "125m": 125 MHz.
* "150m": 150 MHz.
* "250m": 250 MHz.
* "270m": 270 MHz.

We also have a buch of gate clocks with their parents:
  * "hsdma": "150m"
  * "fe": "250m"
  * "sp_divtx": "270m"
  * "timer": "50m"
  * "pcm": "270m"
  * "pio": "50m"
  * "gdma": "bus"
  * "nand": "125m"
  * "i2c": "50m"
  * "i2s": "270m"
  * "spi": "bus"
  * "uart1": "50m"
  * "uart2": "50m"
  * "uart3": "50m"
  * "eth": "50m"
  * "pcie0": "125m"
  * "pcie1": "125m"
  * "pcie2": "125m"
  * "crypto": "250m"
  * "shxc": "50m"

With this information the clk driver will provide clock and gates
functionality from a a set of hardcoded clocks allowing to define
a nice device tree without fixed clocks.

Signed-off-by: Sergio Paracuellos 
---
 drivers/clk/Kconfig |   1 +
 drivers/clk/Makefile|   1 +
 drivers/clk/ralink/Kconfig  |  12 +
 drivers/clk/ralink/Makefile |   2 +
 drivers/clk/ralink/clk-mt7621.c | 499 
 5 files changed, 515 insertions(+)
 create mode 100644 drivers/clk/ralink/Kconfig
 create mode 100644 drivers/clk/ralink/Makefile
 create mode 100644 drivers/clk/ralink/clk-mt7621.c

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 7c5dc348c16f..70b23da997bf 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -382,6 +382,7 @@ source "drivers/clk/mediatek/Kconfig"
 source "drivers/clk/meson/Kconfig"
 source "drivers/clk/mvebu/Kconfig"
 source "drivers/clk/qcom/Kconfig"
+source "drivers/clk/ralink/Kconfig"
 source "drivers/clk/renesas/Kconfig"
 source "drivers/clk/rockchip/Kconfig"
 source "drivers/clk/samsung/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 5325847469e9..1b35ad852721 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -98,6 +98,7 @@ obj-$(CONFIG_COMMON_CLK_NXP)  += nxp/
 obj-$(CONFIG_MACH_PISTACHIO)   += pistachio/
 obj-$(CONFIG_COMMON_CLK_PXA)   += pxa/
 obj-$(CONFIG_COMMON_CLK_QCOM)  += qcom/
+obj-y  += ralink/
 obj-y  += renesas/
 obj-$(CONFIG_ARCH_ROCKCHIP)+= rockchip/
 obj-$(CONFIG_COMMON_CLK_SAMSUNG)   += samsung/
diff --git a/drivers/clk/ralink/Kconfig b/drivers/clk/ralink/Kconfig
new file mode 100644
index ..edee32afdeaa
--- /dev/null
+++ b/drivers/clk/ralink/Kconfig
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# MediaTek Mt7621 Clock Driver
+#
+
+config CLK_MT7621
+   bool "Clock driver for MediaTek MT7621"
+   depends on SOC_MT7621 || COMPILE_TEST
+   default SOC_MT7621
+   select MFD_SYSCON
+   help
+ This driver supports MediaTek MT7621 basic clocks.
diff --git a/drivers/clk/ralink/Makefile b/drivers/clk/ralink/Makefile
new file mode 100644
index ..cf6f9216379d
--- /dev/null
+++ b/drivers/clk/ralink/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_CLK_MT7621) += clk-mt7621.o
diff --git a/drivers/clk/ralink/clk-mt7621.c b/drivers/clk/ralink/clk-mt7621.c
new file mode 100644
index ..823638a7f485
--- /dev/null
+++ b/drivers/clk/ralink/clk-mt7621.c
@@ -0,0 +1,499 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Mediatek MT7621 Clock Driver
+ * Author: Sergio Paracuellos 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* Configuration registers */
+#define SYSC_REG_SYSTEM_CONFIG0 0x10
+#define SYSC_REG_SYSTEM_CONFIG1 0x14
+#define SYSC_REG_CLKCFG0   0x2c
+#define SYSC_REG_CLKCFG1

[PATCH v12 0/4] MIPS: ralink: add CPU clock detection and clock driver for MT7621

his patch inside this series because clk
   binding is referring syscon node and the string for that node was
   with not listed vendor. Hence update and have all of this correct
   in the same series.

Changes in v3:
 - Fix compilation warnings reported by kernel test robot because of
   ignoring return values of 'of_clk_hw_register' in functions
   'mt7621_register_top_clocks' and 'mt7621_gate_ops_init'.
 - Fix dts file and binding documentation 'clock-output-names'.

Changes in v2:
 - Remove the following patches:
   * dt: bindings: add mt7621-pll device tree binding documentation.
   * MIPS: ralink: add clock device providing cpu/ahb/apb clock for mt7621.
 - Move all relevant clock code to 'drivers/clk/ralink/clk-mt7621.c' and
   unify there previous 'mt7621-pll' and 'mt7621-clk' into a unique driver
   and binding 'mt7621-clk'.
 - Driver is not a platform driver anymore and now make use of 'CLK_OF_DECLARE'
   because we need clocks available in 'plat_time_init' before setting up
   the timer for the GIC.
 - Use new fixed clocks as parents for different gates and deriving from 'xtal'
   using frequencies in[1].
 - Adapt dts file and bindings header and documentation for new changes.
 - Change MAINTAINERS file to only contains clk-mt7621.c code and
   mediatek,mt7621-clk.yaml file.

[0]: https://www.lkml.org/lkml/2019/7/23/1044
[1]: 
https://github.com/981213/linux/commit/2eca1f045e4c3db18c941135464c0d7422ad8133
[2]: https://lkml.org/lkml/2020/12/20/47
[3]: 
http://driverdev.linuxdriverproject.org/pipermail/driverdev-devel/2021-February/150772.html

Sergio Paracuellos (4):
  clk: ralink: add clock driver for mt7621 SoC
  staging: mt7621-dts: make use of new 'mt7621-clk'
  staging: mt7621-dts: use valid vendor 'mediatek' instead of invalid
'mtk'
  MAINTAINERS: add MT7621 CLOCK maintainer

 MAINTAINERS|   6 +
 arch/mips/ralink/mt7621.c  |   6 +-
 drivers/clk/Kconfig|   1 +
 drivers/clk/Makefile   |   1 +
 drivers/clk/ralink/Kconfig |  12 +
 drivers/clk/ralink/Makefile|   2 +
 drivers/clk/ralink/clk-mt7621.c| 499 +
 drivers/staging/mt7621-dts/gbpc1.dts   |  11 -
 drivers/staging/mt7621-dts/mt7621.dtsi |  82 ++--
 9 files changed, 561 insertions(+), 59 deletions(-)
 create mode 100644 drivers/clk/ralink/Kconfig
 create mode 100644 drivers/clk/ralink/Makefile
 create mode 100644 drivers/clk/ralink/clk-mt7621.c

-- 
2.25.1

Re: [PATCH v11 3/6] clk: ralink: add clock driver for mt7621 SoC

Hi,

On Fri, Apr 9, 2021 at 8:14 PM Stephen Boyd  wrote:
>
> Quoting Sergio Paracuellos (2021-03-08 21:22:23)
> > diff --git a/drivers/clk/ralink/Kconfig b/drivers/clk/ralink/Kconfig
> > new file mode 100644
> > index ..3e3f5cb9ad88
> > --- /dev/null
> > +++ b/drivers/clk/ralink/Kconfig
> > @@ -0,0 +1,15 @@
> > +# SPDX-License-Identifier: GPL-2.0-only
> > +#
> > +# MediaTek Mt7621 Clock Driver
> > +#
> > +menu "Clock driver for Mediatek mt7621 SoC"
> > +   depends on SOC_MT7621 || COMPILE_TEST
>
> Do we need a menu and a config that says the same thing? Maybe the menu
> can be dropped?

Ok, I will drop the menu from this Kconfig.

>
> > +
> > +config CLK_MT7621
> > +   bool "Clock driver for MediaTek MT7621"
> > +   depends on SOC_MT7621 || COMPILE_TEST
> > +   default SOC_MT7621
> > +   select MFD_SYSCON
> > +   help
> > + This driver supports MediaTek MT7621 basic clocks.
> > +endmenu
> > diff --git a/drivers/clk/ralink/Makefile b/drivers/clk/ralink/Makefile
> > new file mode 100644
> > index ..cf6f9216379d
> > --- /dev/null
> > +++ b/drivers/clk/ralink/Makefile
> > @@ -0,0 +1,2 @@
> > +# SPDX-License-Identifier: GPL-2.0
> > +obj-$(CONFIG_CLK_MT7621) += clk-mt7621.o
> > diff --git a/drivers/clk/ralink/clk-mt7621.c 
> > b/drivers/clk/ralink/clk-mt7621.c
> > new file mode 100644
> > index ..6aea5accd51c
> > --- /dev/null
> > +++ b/drivers/clk/ralink/clk-mt7621.c
> > @@ -0,0 +1,528 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Mediatek MT7621 Clock Driver
> > + * Author: Sergio Paracuellos 
> > + */
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +/* Configuration registers */
> > +#define SYSC_REG_SYSTEM_CONFIG0 0x10
> > +#define SYSC_REG_SYSTEM_CONFIG1 0x14
> > +#define SYSC_REG_CLKCFG0   0x2c
> > +#define SYSC_REG_CLKCFG1   0x30
> > +#define SYSC_REG_CUR_CLK_STS   0x44
> > +#define MEMC_REG_CPU_PLL   0x648
> > +
> > +#define XTAL_MODE_SEL_MASK GENMASK(8, 6)
> > +#define CPU_CLK_SEL_MASK   GENMASK(31, 30)
> > +#define CUR_CPU_FDIV_MASK  GENMASK(12, 8)
> > +#define CUR_CPU_FFRAC_MASK GENMASK(4, 0)
> > +#define CPU_PLL_PREDIV_MASKGENMASK(13, 12)
> > +#define CPU_PLL_FBDIV_MASK GENMASK(10, 4)
> > +
> > +struct mt7621_clk_priv {
> > +   struct regmap *sysc;
> > +   struct regmap *memc;
> > +};
> > +
> > +struct mt7621_clk {
> > +   struct clk_hw hw;
> > +   struct mt7621_clk_priv *priv;
> > +};
> > +
> > +struct mt7621_fixed_clk {
> > +   u8 idx;
> > +   const char *name;
> > +   const char *parent_name;
> > +   unsigned long rate;
> > +   struct clk_hw *hw;
> > +};
> > +
> > +struct mt7621_gate {
> > +   u8 idx;
> > +   const char *name;
> > +   const char *parent_name;
> > +   struct mt7621_clk_priv *priv;
> > +   u32 bit_idx;
> > +   struct clk_hw hw;
> > +};
> > +
> > +#define GATE(_id, _name, _pname, _shift)   \
> > +   {   \
> > +   .idx= _id,  \
> > +   .name   = _name,\
> > +   .parent_name= _pname,   \
> > +   .bit_idx= _shift\
> > +   }
> > +
> > +static struct mt7621_gate mt7621_gates[] = {
> > +   GATE(MT7621_CLK_HSDMA, "hsdma", "150m", BIT(5)),
> > +   GATE(MT7621_CLK_FE, "fe", "250m", BIT(6)),
> > +   GATE(MT7621_CLK_SP_DIVTX, "sp_divtx", "270m", BIT(7)),
> > +   GATE(MT7621_CLK_TIMER, "timer", "50m", BIT(8)),
> > +   GATE(MT7621_CLK_PCM, "pcm", "270m", BIT(11)),
> > +   GATE(MT7621_CLK_PIO, "pio", "50m", BIT(13)),
> > +   GATE(MT7621_CLK_GDMA, "gdma", "bus", BIT(14)),
> > +   GATE(MT7621_CLK_NAND, "nand", "125m", BIT(15)),
> > +   GATE(MT7621_CLK_I2C, "i2c", "50m", BIT(16)),
> > +   GATE(MT7621_CLK_I2S, "i2s", "270m", BIT(17)),

Re: [PATCH v11 0/6] MIPS: ralink: add CPU clock detection and clock driver for MT7621

Hi Stephen,

On Fri, Apr 9, 2021 at 8:17 PM Stephen Boyd  wrote:
>
> Quoting Sergio Paracuellos (2021-03-23 01:13:22)
> > On Tue, Mar 9, 2021 at 6:22 AM Sergio Paracuellos
> >  wrote:
> > >
> > > Changes in v11:
> > >  - Collect Rob's Reviewed-by in bindings documentation patch.
> > >  - Fix MAINTAINERS patch using file 'mediatek,mt7621-sysc.yaml'
> > >for documentation bindings.
> >
> > Something still missing or something that is needed to be fixed to get
> > this series applied through your tree?
> >
> > Thanks in advance for your time.
> >
>
> Sorry I missed this series. I thought it was going through another tree.
> It can merge through clk tree. Just a few nits on the clk driver patch
> but otherwise I've merged the first two patches. If you resend in the
> next few days it would be great. Thanks.

I will hopefully do during this weekend. Since you already merge the
first two patches, the remaining four should be sent as v12, right?

Re: [PATCH v11 0/6] MIPS: ralink: add CPU clock detection and clock driver for MT7621

2021-03-23 Thread Sergio Paracuellos

Hi Stephen,

On Tue, Mar 9, 2021 at 6:22 AM Sergio Paracuellos
 wrote:
>
> This patchset ports CPU clock detection for MT7621 from OpenWrt
> and adds a complete clock plan for the mt7621 SOC.
>
> The documentation for this SOC only talks about two registers
> regarding to the clocks:
> * SYSC_REG_CPLL_CLKCFG0 - provides some information about boostrapped
> refclock. PLL and dividers used for CPU and some sort of BUS (AHB?).
> * SYSC_REG_CPLL_CLKCFG1 - a banch of gates to enable/disable clocks for
> all or some ip cores.
>
> Registers needed for this driver to work are in two already mapped areas
> in its platform's device tree. These are 'sysc' and 'memc' nodes. Most
> of other drivers just make use of platform operations defined in
> 'asm/mach-ralink/ralink_regs.h' but this can be avoided declaring this
> two nodes to be accesible through syscon. Main registers for the clocks
> are in the sysc control node so this node is merged with clock properties
> and will also be the clock provider for the SoC.
>
> No documentation about a probably existent set of dividers for each ip
> core is included in the datasheets. So we cannot make anything better,
> AFAICT.
>
> Looking into driver code, and some openWRT patched there are
> another frequences which are used in some drivers (uart, sd...).
> According to all of this information the clock plan for this
> SoC is set as follows:
>  - Main top clock "xtal" from where all the rest of the world is
>derived.
>  - CPU clock "cpu" derived from "xtal" frequencies and a bunch of
>register reads and predividers.
>  - BUS clock "bus" derived from "cpu" and with (cpu / 4) MHz.
>  - Fixed clocks from "xtal":
> * "50m": 50 MHz.
> * "125m": 125 MHz.
> * "150m": 150 MHz.
> * "250m": 250 MHz.
> * "270m": 270 MHz.
>
> We also have a buch of gate clocks with their parents:
>  - "hsdma": "150m"
>  - "fe": "250m"
>  - "sp_divtx": "270m"
>  - "timer": "50m"
>  - "pcm": "270m"
>  - "pio": "50m"
>  - "gdma": "bus"
>  - "nand": "125m"
>  - "i2c": "50m"
>  - "i2s": "270m"
>  - "spi": "bus"
>  - "uart1": "50m"
>  - "uart2": "50m"
>  - "uart3": "50m"
>  - "eth": "50m"
>  - "pcie0": "125m"
>  - "pcie1": "125m"
>  - "pcie2": "125m"
>  - "crypto": "250m"
>  - "shxc": "50m"
>
> There was a previous attempt of doing this here[0] but the author
> (Chuanhong Guo) did not wanted to make assumptions of a clock plan
> for the platform that time. It seems that now he has a better idea of
> how the clocks are dispossed for this SoC so he share code[1] where
> some frequencies and clock parents for the gates are coded from a
> real mediatek private clock plan.
>
> I do really want this to be upstreamed so according to the comments
> in previous attempt[0] from Oleksij Rempel and the frequencies in
> code[1] I have tried to do this by myself.
>
> All of this patches have been tested in a GNUBee PC1 resulting in a
> working platform.
>
> Changes in v11:
>  - Collect Rob's Reviewed-by in bindings documentation patch.
>  - Fix MAINTAINERS patch using file 'mediatek,mt7621-sysc.yaml'
>for documentation bindings.

Something still missing or something that is needed to be fixed to get
this series applied through your tree?

Thanks in advance for your time.

Best regards,
 Sergio Paracuellos

>
> Changes in v10:
>  - Merge clock properties into 'sysc' system control node making
>this node a clock provider.
>  - Update driver to use 'mediatek,mt7621-sysc' as compatible string.
>  - Update documentation bindings and its related filename to
>'mediatek,mt7621-sysc.yaml'.
>  - Make use of 'linux/bitfields.h' header to avoid some preprocesor
>shift definitions and just use bit masks decreasing a bit LOC.
>
> Changes in v9:
>  - Set two missing ret values to its related PTR_ERR in function
>'mt7621_clk_probe' (also related with [3]).
>  - Select MFC_SYSCON in Kconfig.
>
> Changes in v8:
>  - Fix kernel test robot complain about the use of 'ret' variable
>initialized: see [3]
>
> Changes in v7:
>  - Make use of CLK_OF_DECLARE_DRIVER instead of CLK_OF_DECLARE and
>register there only the top clocks that are needed in 'of_clk_init'.
>The rest of th

[PATCH v11 5/6] staging: mt7621-dts: use valid vendor 'mediatek' instead of invalid 'mtk'

Vendor listed for mediatek in kernel vendor file 'vendor-prefixes.yaml'
contains 'mediatek' as a valid vendor string. Some nodes in the device
tree are using an invalid vendor string vfor 'mtk' instead. Fix all of
them in dts file. Update also ralink mt7621 related code to properly
match new strings. Even there are used in the device tree there are
some strings that are not referred anywhere but have been also updated
with new vendor name. These are 'mtk,mt7621-wdt', 'mtk,mt7621-nand',
'mtk,mt7621-mc', and 'mtk,mt7621-cpc'.

Acked-by: Greg Kroah-Hartman 
Signed-off-by: Sergio Paracuellos 
---
 arch/mips/ralink/mt7621.c  |  6 +++---
 drivers/staging/mt7621-dts/mt7621.dtsi | 12 ++--
 2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/arch/mips/ralink/mt7621.c b/arch/mips/ralink/mt7621.c
index ca0ac607b0f3..5d74fc1c96ac 100644
--- a/arch/mips/ralink/mt7621.c
+++ b/arch/mips/ralink/mt7621.c
@@ -112,8 +112,8 @@ phys_addr_t mips_cpc_default_phys_base(void)
 
 void __init ralink_of_remap(void)
 {
-   rt_sysc_membase = plat_of_remap_node("mtk,mt7621-sysc");
-   rt_memc_membase = plat_of_remap_node("mtk,mt7621-memc");
+   rt_sysc_membase = plat_of_remap_node("mediatek,mt7621-sysc");
+   rt_memc_membase = plat_of_remap_node("mediatek,mt7621-memc");
 
if (!rt_sysc_membase || !rt_memc_membase)
panic("Failed to remap core resources");
@@ -181,7 +181,7 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
 
if (n0 == MT7621_CHIP_NAME0 && n1 == MT7621_CHIP_NAME1) {
name = "MT7621";
-   soc_info->compatible = "mtk,mt7621-soc";
+   soc_info->compatible = "mediatek,mt7621-soc";
} else {
panic("mt7621: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
}
diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi 
b/drivers/staging/mt7621-dts/mt7621.dtsi
index b68183e7e6ad..f0c9ae757bcd 100644
--- a/drivers/staging/mt7621-dts/mt7621.dtsi
+++ b/drivers/staging/mt7621-dts/mt7621.dtsi
@@ -56,7 +56,7 @@ palmbus: palmbus@1E00 {
#size-cells = <1>;
 
sysc: sysc@0 {
-   compatible = "mtk,mt7621-sysc", "syscon";
+   compatible = "mediatek,mt7621-sysc", "syscon";
reg = <0x0 0x100>;
#clock-cells = <1>;
ralink,memctl = <>;
@@ -66,7 +66,7 @@ sysc: sysc@0 {
};
 
wdt: wdt@100 {
-   compatible = "mtk,mt7621-wdt";
+   compatible = "mediatek,mt7621-wdt";
reg = <0x100 0x100>;
};
 
@@ -123,17 +123,17 @@ i2s: i2s@a00 {
};
 
memc: memc@5000 {
-   compatible = "mtk,mt7621-memc", "syscon";
+   compatible = "mediatek,mt7621-memc", "syscon";
reg = <0x5000 0x1000>;
};
 
cpc: cpc@1fbf {
-compatible = "mtk,mt7621-cpc";
+compatible = "mediatek,mt7621-cpc";
 reg = <0x1fbf 0x8000>;
};
 
mc: mc@1fbf8000 {
-   compatible = "mtk,mt7621-mc";
+   compatible = "mediatek,mt7621-mc";
reg = <0x1fbf8000 0x8000>;
};
 
@@ -361,7 +361,7 @@ timer {
nand: nand@1e003000 {
status = "disabled";
 
-   compatible = "mtk,mt7621-nand";
+   compatible = "mediatek,mt7621-nand";
bank-width = <2>;
reg = <0x1e003000 0x800
0x1e003800 0x800>;
-- 
2.25.1

[PATCH v11 3/6] clk: ralink: add clock driver for mt7621 SoC

The documentation for this SOC only talks about two
registers regarding to the clocks:
* SYSC_REG_CPLL_CLKCFG0 - provides some information about
boostrapped refclock. PLL and dividers used for CPU and some
sort of BUS.
* SYSC_REG_CPLL_CLKCFG1 - a banch of gates to enable/disable
clocks for all or some ip cores.

Looking into driver code, and some openWRT patched there are
another frequencies which are used in some drivers (uart, sd...).
According to all of this information the clock plan for this
SoC is set as follows:
- Main top clock "xtal" from where all the rest of the world is
derived.
- CPU clock "cpu" derived from "xtal" frequencies and a bunch of
register reads and predividers.
- BUS clock "bus" derived from "cpu" and with (cpu / 4) MHz.
- Fixed clocks from "xtal":
* "50m": 50 MHz.
* "125m": 125 MHz.
* "150m": 150 MHz.
* "250m": 250 MHz.
* "270m": 270 MHz.

We also have a buch of gate clocks with their parents:
  * "hsdma": "150m"
  * "fe": "250m"
  * "sp_divtx": "270m"
  * "timer": "50m"
  * "pcm": "270m"
  * "pio": "50m"
  * "gdma": "bus"
  * "nand": "125m"
  * "i2c": "50m"
  * "i2s": "270m"
  * "spi": "bus"
  * "uart1": "50m"
  * "uart2": "50m"
  * "uart3": "50m"
  * "eth": "50m"
  * "pcie0": "125m"
  * "pcie1": "125m"
  * "pcie2": "125m"
  * "crypto": "250m"
  * "shxc": "50m"

With this information the clk driver will provide clock and gates
functionality from a a set of hardcoded clocks allowing to define
a nice device tree without fixed clocks.

Signed-off-by: Sergio Paracuellos 
---
 drivers/clk/Kconfig |   1 +
 drivers/clk/Makefile|   1 +
 drivers/clk/ralink/Kconfig  |  15 +
 drivers/clk/ralink/Makefile |   2 +
 drivers/clk/ralink/clk-mt7621.c | 528 
 5 files changed, 547 insertions(+)
 create mode 100644 drivers/clk/ralink/Kconfig
 create mode 100644 drivers/clk/ralink/Makefile
 create mode 100644 drivers/clk/ralink/clk-mt7621.c

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 7c5dc348c16f..70b23da997bf 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -382,6 +382,7 @@ source "drivers/clk/mediatek/Kconfig"
 source "drivers/clk/meson/Kconfig"
 source "drivers/clk/mvebu/Kconfig"
 source "drivers/clk/qcom/Kconfig"
+source "drivers/clk/ralink/Kconfig"
 source "drivers/clk/renesas/Kconfig"
 source "drivers/clk/rockchip/Kconfig"
 source "drivers/clk/samsung/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 5325847469e9..1b35ad852721 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -98,6 +98,7 @@ obj-$(CONFIG_COMMON_CLK_NXP)  += nxp/
 obj-$(CONFIG_MACH_PISTACHIO)   += pistachio/
 obj-$(CONFIG_COMMON_CLK_PXA)   += pxa/
 obj-$(CONFIG_COMMON_CLK_QCOM)  += qcom/
+obj-y  += ralink/
 obj-y  += renesas/
 obj-$(CONFIG_ARCH_ROCKCHIP)+= rockchip/
 obj-$(CONFIG_COMMON_CLK_SAMSUNG)   += samsung/
diff --git a/drivers/clk/ralink/Kconfig b/drivers/clk/ralink/Kconfig
new file mode 100644
index ..3e3f5cb9ad88
--- /dev/null
+++ b/drivers/clk/ralink/Kconfig
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# MediaTek Mt7621 Clock Driver
+#
+menu "Clock driver for Mediatek mt7621 SoC"
+   depends on SOC_MT7621 || COMPILE_TEST
+
+config CLK_MT7621
+   bool "Clock driver for MediaTek MT7621"
+   depends on SOC_MT7621 || COMPILE_TEST
+   default SOC_MT7621
+   select MFD_SYSCON
+   help
+ This driver supports MediaTek MT7621 basic clocks.
+endmenu
diff --git a/drivers/clk/ralink/Makefile b/drivers/clk/ralink/Makefile
new file mode 100644
index ..cf6f9216379d
--- /dev/null
+++ b/drivers/clk/ralink/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_CLK_MT7621) += clk-mt7621.o
diff --git a/drivers/clk/ralink/clk-mt7621.c b/drivers/clk/ralink/clk-mt7621.c
new file mode 100644
index ..6aea5accd51c
--- /dev/null
+++ b/drivers/clk/ralink/clk-mt7621.c
@@ -0,0 +1,528 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Mediatek MT7621 Clock Driver
+ * Author: Sergio Paracuellos 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* Configuration registers */
+#define SYSC_REG_SYSTEM_CONFIG0 0x10
+#de

[PATCH v11 2/6] dt: bindings: add mt7621-sysc device tree binding documentation

Adds device tree binding documentation for clocks in the
MT7621 SOC.

Reviewed-by: Rob Herring 
Signed-off-by: Sergio Paracuellos 
---
 .../bindings/clock/mediatek,mt7621-sysc.yaml  | 68 +++
 1 file changed, 68 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml

diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml 
b/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml
new file mode 100644
index ..915f84efd763
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/mediatek,mt7621-sysc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MT7621 Clock Device Tree Bindings
+
+maintainers:
+  - Sergio Paracuellos 
+
+description: |
+  The MT7621 has a PLL controller from where the cpu clock is provided
+  as well as derived clocks for the bus and the peripherals. It also
+  can gate SoC device clocks.
+
+  Each clock is assigned an identifier and client nodes use this identifier
+  to specify the clock which they consume.
+
+  All these identifiers could be found in:
+  [1]: .
+
+  The clocks are provided inside a system controller node.
+
+properties:
+  compatible:
+items:
+  - const: mediatek,mt7621-sysc
+  - const: syscon
+
+  reg:
+maxItems: 1
+
+  "#clock-cells":
+description:
+  The first cell indicates the clock number, see [1] for available
+  clocks.
+const: 1
+
+  ralink,memctl:
+$ref: /schemas/types.yaml#/definitions/phandle
+description:
+  phandle of syscon used to control memory registers
+
+  clock-output-names:
+maxItems: 8
+
+required:
+  - compatible
+  - reg
+  - '#clock-cells'
+  - ralink,memctl
+
+additionalProperties: false
+
+examples:
+  - |
+#include 
+
+sysc: sysc@0 {
+  compatible = "mediatek,mt7621-sysc", "syscon";
+  reg = <0x0 0x100>;
+  #clock-cells = <1>;
+  ralink,memctl = <>;
+  clock-output-names = "xtal", "cpu", "bus",
+   "50m", "125m", "150m",
+   "250m", "270m";
+};
-- 
2.25.1

[PATCH v11 4/6] staging: mt7621-dts: make use of new 'mt7621-clk'

Clocks for SoC mt7621 have been properly integrated so there is
no need to declare fixed clocks at all in the device tree. Remove
all of them, add new device tree nodes for mt7621-clk and update
the rest of the nodes to use them.

Acked-by: Greg Kroah-Hartman 
Signed-off-by: Sergio Paracuellos 
---
 drivers/staging/mt7621-dts/gbpc1.dts   | 11 
 drivers/staging/mt7621-dts/mt7621.dtsi | 74 --
 2 files changed, 33 insertions(+), 52 deletions(-)

diff --git a/drivers/staging/mt7621-dts/gbpc1.dts 
b/drivers/staging/mt7621-dts/gbpc1.dts
index a7c0d3115d72..7716d0efe524 100644
--- a/drivers/staging/mt7621-dts/gbpc1.dts
+++ b/drivers/staging/mt7621-dts/gbpc1.dts
@@ -100,17 +100,6 @@ partition@5 {
};
 };
 
- {
-   compatible = "fixed-clock";
-   /* This is normally 1/4 of cpuclock */
-   clock-frequency = <22500>;
-};
-
- {
-   compatible = "fixed-clock";
-   clock-frequency = <9>;
-};
-
  {
pinctrl-names = "default";
pinctrl-0 = <_pins>;
diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi 
b/drivers/staging/mt7621-dts/mt7621.dtsi
index 16fc94f65486..b68183e7e6ad 100644
--- a/drivers/staging/mt7621-dts/mt7621.dtsi
+++ b/drivers/staging/mt7621-dts/mt7621.dtsi
@@ -1,5 +1,6 @@
 #include 
 #include 
+#include 
 
 / {
#address-cells = <1>;
@@ -27,27 +28,6 @@ aliases {
serial0 = 
};
 
-   cpuclock: cpuclock@0 {
-   #clock-cells = <0>;
-   compatible = "fixed-clock";
-
-   /* FIXME: there should be way to detect this */
-   clock-frequency = <88000>;
-   };
-
-   sysclock: sysclock@0 {
-   #clock-cells = <0>;
-   compatible = "fixed-clock";
-
-   /* This is normally 1/4 of cpuclock */
-   clock-frequency = <22000>;
-   };
-
-   mmc_clock: mmc_clock@0 {
-   #clock-cells = <0>;
-   compatible = "fixed-clock";
-   clock-frequency = <4800>;
-   };
 
mmc_fixed_3v3: fixedregulator@0 {
compatible = "regulator-fixed";
@@ -76,8 +56,13 @@ palmbus: palmbus@1E00 {
#size-cells = <1>;
 
sysc: sysc@0 {
-   compatible = "mtk,mt7621-sysc";
+   compatible = "mtk,mt7621-sysc", "syscon";
reg = <0x0 0x100>;
+   #clock-cells = <1>;
+   ralink,memctl = <>;
+   clock-output-names = "xtal", "cpu", "bus",
+"50m", "125m", "150m",
+"250m", "270m";
};
 
wdt: wdt@100 {
@@ -101,8 +86,8 @@ i2c: i2c@900 {
compatible = "mediatek,mt7621-i2c";
reg = <0x900 0x100>;
 
-   clocks = <>;
-
+   clocks = < MT7621_CLK_I2C>;
+   clock-names = "i2c";
resets = < 16>;
reset-names = "i2c";
 
@@ -119,8 +104,8 @@ i2s: i2s@a00 {
compatible = "mediatek,mt7621-i2s";
reg = <0xa00 0x100>;
 
-   clocks = <>;
-
+   clocks = < MT7621_CLK_I2S>;
+   clock-names = "i2s";
resets = < 17>;
reset-names = "i2s";
 
@@ -138,7 +123,7 @@ i2s: i2s@a00 {
};
 
memc: memc@5000 {
-   compatible = "mtk,mt7621-memc";
+   compatible = "mtk,mt7621-memc", "syscon";
reg = <0x5000 0x1000>;
};
 
@@ -156,8 +141,8 @@ uartlite: uartlite@c00 {
compatible = "ns16550a";
reg = <0xc00 0x100>;
 
-   clocks = <>;
-   clock-frequency = <5000>;
+   clocks = < MT7621_CLK_UART1>;
+   clock-names = "uart1";
 
interrupt-parent = <>;
interrupts = ;
@@ -173,7 +158,8 @@ spi0: spi@b00 {
compatible = "ralink,mt7621-spi";
reg = <0xb00 0x100>;
 
-   clocks = <>;
+   clocks = < MT7621_CLK_SPI>;
+

[PATCH v11 6/6] MAINTAINERS: add MT7621 CLOCK maintainer

Adding myself as maintainer for mt7621 clock driver.

Signed-off-by: Sergio Paracuellos 
---
 MAINTAINERS | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 809a68af5efd..ecad5d972122 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11288,6 +11288,12 @@ L: linux-wirel...@vger.kernel.org
 S: Maintained
 F: drivers/net/wireless/mediatek/mt7601u/
 
+MEDIATEK MT7621 CLOCK DRIVER
+M: Sergio Paracuellos 
+S: Maintained
+F: Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml
+F: drivers/clk/ralink/clk-mt7621.c
+
 MEDIATEK MT7621/28/88 I2C DRIVER
 M: Stefan Roese 
 L: linux-...@vger.kernel.org
-- 
2.25.1

[PATCH v11 1/6] dt-bindings: clock: add dt binding header for mt7621 clocks

Adds dt binding header for 'mediatek,mt7621-clk' clocks.

Acked-by: Rob Herring 
Signed-off-by: Sergio Paracuellos 
---
 include/dt-bindings/clock/mt7621-clk.h | 41 ++
 1 file changed, 41 insertions(+)
 create mode 100644 include/dt-bindings/clock/mt7621-clk.h

diff --git a/include/dt-bindings/clock/mt7621-clk.h 
b/include/dt-bindings/clock/mt7621-clk.h
new file mode 100644
index ..1422badcf9de
--- /dev/null
+++ b/include/dt-bindings/clock/mt7621-clk.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Author: Sergio Paracuellos 
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT7621_H
+#define _DT_BINDINGS_CLK_MT7621_H
+
+#define MT7621_CLK_XTAL0
+#define MT7621_CLK_CPU 1
+#define MT7621_CLK_BUS 2
+#define MT7621_CLK_50M 3
+#define MT7621_CLK_125M4
+#define MT7621_CLK_150M5
+#define MT7621_CLK_250M6
+#define MT7621_CLK_270M7
+
+#define MT7621_CLK_HSDMA   8
+#define MT7621_CLK_FE  9
+#define MT7621_CLK_SP_DIVTX10
+#define MT7621_CLK_TIMER   11
+#define MT7621_CLK_PCM 12
+#define MT7621_CLK_PIO 13
+#define MT7621_CLK_GDMA14
+#define MT7621_CLK_NAND15
+#define MT7621_CLK_I2C 16
+#define MT7621_CLK_I2S 17
+#define MT7621_CLK_SPI 18
+#define MT7621_CLK_UART1   19
+#define MT7621_CLK_UART2   20
+#define MT7621_CLK_UART3   21
+#define MT7621_CLK_ETH 22
+#define MT7621_CLK_PCIE0   23
+#define MT7621_CLK_PCIE1   24
+#define MT7621_CLK_PCIE2   25
+#define MT7621_CLK_CRYPTO  26
+#define MT7621_CLK_SHXC27
+
+#define MT7621_CLK_MAX 28
+
+#endif /* _DT_BINDINGS_CLK_MT7621_H */
-- 
2.25.1

[PATCH v11 0/6] MIPS: ralink: add CPU clock detection and clock driver for MT7621

ant clock code to 'drivers/clk/ralink/clk-mt7621.c' and
   unify there previous 'mt7621-pll' and 'mt7621-clk' into a unique driver
   and binding 'mt7621-clk'.
 - Driver is not a platform driver anymore and now make use of 'CLK_OF_DECLARE'
   because we need clocks available in 'plat_time_init' before setting up
   the timer for the GIC.
 - Use new fixed clocks as parents for different gates and deriving from 'xtal'
   using frequencies in[1].
 - Adapt dts file and bindings header and documentation for new changes.
 - Change MAINTAINERS file to only contains clk-mt7621.c code and
   mediatek,mt7621-clk.yaml file.

[0]: https://www.lkml.org/lkml/2019/7/23/1044
[1]: 
https://github.com/981213/linux/commit/2eca1f045e4c3db18c941135464c0d7422ad8133
[2]: https://lkml.org/lkml/2020/12/20/47
[3]: 
http://driverdev.linuxdriverproject.org/pipermail/driverdev-devel/2021-February/150772.html

Sergio Paracuellos (6):
  dt-bindings: clock: add dt binding header for mt7621 clocks
  dt: bindings: add mt7621-sysc device tree binding documentation
  clk: ralink: add clock driver for mt7621 SoC
  staging: mt7621-dts: make use of new 'mt7621-clk'
  staging: mt7621-dts: use valid vendor 'mediatek' instead of invalid
'mtk'
  MAINTAINERS: add MT7621 CLOCK maintainer

 .../bindings/clock/mediatek,mt7621-sysc.yaml  |  68 +++
 MAINTAINERS   |   6 +
 arch/mips/ralink/mt7621.c |   6 +-
 drivers/clk/Kconfig   |   1 +
 drivers/clk/Makefile  |   1 +
 drivers/clk/ralink/Kconfig|  15 +
 drivers/clk/ralink/Makefile   |   2 +
 drivers/clk/ralink/clk-mt7621.c   | 528 ++
 drivers/staging/mt7621-dts/gbpc1.dts  |  11 -
 drivers/staging/mt7621-dts/mt7621.dtsi|  82 ++-
 include/dt-bindings/clock/mt7621-clk.h|  41 ++
 11 files changed, 702 insertions(+), 59 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml
 create mode 100644 drivers/clk/ralink/Kconfig
 create mode 100644 drivers/clk/ralink/Makefile
 create mode 100644 drivers/clk/ralink/clk-mt7621.c
 create mode 100644 include/dt-bindings/clock/mt7621-clk.h

-- 
2.25.1

[PATCH v10 3/6] clk: ralink: add clock driver for mt7621 SoC

The documentation for this SOC only talks about two
registers regarding to the clocks:
* SYSC_REG_CPLL_CLKCFG0 - provides some information about
boostrapped refclock. PLL and dividers used for CPU and some
sort of BUS.
* SYSC_REG_CPLL_CLKCFG1 - a banch of gates to enable/disable
clocks for all or some ip cores.

Looking into driver code, and some openWRT patched there are
another frequencies which are used in some drivers (uart, sd...).
According to all of this information the clock plan for this
SoC is set as follows:
- Main top clock "xtal" from where all the rest of the world is
derived.
- CPU clock "cpu" derived from "xtal" frequencies and a bunch of
register reads and predividers.
- BUS clock "bus" derived from "cpu" and with (cpu / 4) MHz.
- Fixed clocks from "xtal":
* "50m": 50 MHz.
* "125m": 125 MHz.
* "150m": 150 MHz.
* "250m": 250 MHz.
* "270m": 270 MHz.

We also have a buch of gate clocks with their parents:
  * "hsdma": "150m"
  * "fe": "250m"
  * "sp_divtx": "270m"
  * "timer": "50m"
  * "pcm": "270m"
  * "pio": "50m"
  * "gdma": "bus"
  * "nand": "125m"
  * "i2c": "50m"
  * "i2s": "270m"
  * "spi": "bus"
  * "uart1": "50m"
  * "uart2": "50m"
  * "uart3": "50m"
  * "eth": "50m"
  * "pcie0": "125m"
  * "pcie1": "125m"
  * "pcie2": "125m"
  * "crypto": "250m"
  * "shxc": "50m"

With this information the clk driver will provide clock and gates
functionality from a a set of hardcoded clocks allowing to define
a nice device tree without fixed clocks.

Signed-off-by: Sergio Paracuellos 
---
 drivers/clk/Kconfig |   1 +
 drivers/clk/Makefile|   1 +
 drivers/clk/ralink/Kconfig  |  15 +
 drivers/clk/ralink/Makefile |   2 +
 drivers/clk/ralink/clk-mt7621.c | 528 
 5 files changed, 547 insertions(+)
 create mode 100644 drivers/clk/ralink/Kconfig
 create mode 100644 drivers/clk/ralink/Makefile
 create mode 100644 drivers/clk/ralink/clk-mt7621.c

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 7c5dc348c16f..70b23da997bf 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -382,6 +382,7 @@ source "drivers/clk/mediatek/Kconfig"
 source "drivers/clk/meson/Kconfig"
 source "drivers/clk/mvebu/Kconfig"
 source "drivers/clk/qcom/Kconfig"
+source "drivers/clk/ralink/Kconfig"
 source "drivers/clk/renesas/Kconfig"
 source "drivers/clk/rockchip/Kconfig"
 source "drivers/clk/samsung/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 5325847469e9..1b35ad852721 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -98,6 +98,7 @@ obj-$(CONFIG_COMMON_CLK_NXP)  += nxp/
 obj-$(CONFIG_MACH_PISTACHIO)   += pistachio/
 obj-$(CONFIG_COMMON_CLK_PXA)   += pxa/
 obj-$(CONFIG_COMMON_CLK_QCOM)  += qcom/
+obj-y  += ralink/
 obj-y  += renesas/
 obj-$(CONFIG_ARCH_ROCKCHIP)+= rockchip/
 obj-$(CONFIG_COMMON_CLK_SAMSUNG)   += samsung/
diff --git a/drivers/clk/ralink/Kconfig b/drivers/clk/ralink/Kconfig
new file mode 100644
index ..3e3f5cb9ad88
--- /dev/null
+++ b/drivers/clk/ralink/Kconfig
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# MediaTek Mt7621 Clock Driver
+#
+menu "Clock driver for Mediatek mt7621 SoC"
+   depends on SOC_MT7621 || COMPILE_TEST
+
+config CLK_MT7621
+   bool "Clock driver for MediaTek MT7621"
+   depends on SOC_MT7621 || COMPILE_TEST
+   default SOC_MT7621
+   select MFD_SYSCON
+   help
+ This driver supports MediaTek MT7621 basic clocks.
+endmenu
diff --git a/drivers/clk/ralink/Makefile b/drivers/clk/ralink/Makefile
new file mode 100644
index ..cf6f9216379d
--- /dev/null
+++ b/drivers/clk/ralink/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_CLK_MT7621) += clk-mt7621.o
diff --git a/drivers/clk/ralink/clk-mt7621.c b/drivers/clk/ralink/clk-mt7621.c
new file mode 100644
index ..6aea5accd51c
--- /dev/null
+++ b/drivers/clk/ralink/clk-mt7621.c
@@ -0,0 +1,528 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Mediatek MT7621 Clock Driver
+ * Author: Sergio Paracuellos 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* Configuration registers */
+#define SYSC_REG_SYSTEM_CONFIG0 0x10
+#de

[PATCH v10 6/6] MAINTAINERS: add MT7621 CLOCK maintainer

Adding myself as maintainer for mt7621 clock driver.

Signed-off-by: Sergio Paracuellos 
---
 MAINTAINERS | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 809a68af5efd..be5ada6b4309 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11288,6 +11288,12 @@ L: linux-wirel...@vger.kernel.org
 S: Maintained
 F: drivers/net/wireless/mediatek/mt7601u/
 
+MEDIATEK MT7621 CLOCK DRIVER
+M: Sergio Paracuellos 
+S: Maintained
+F: Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
+F: drivers/clk/ralink/clk-mt7621.c
+
 MEDIATEK MT7621/28/88 I2C DRIVER
 M: Stefan Roese 
 L: linux-...@vger.kernel.org
-- 
2.25.1

[PATCH v10 5/6] staging: mt7621-dts: use valid vendor 'mediatek' instead of invalid 'mtk'

Vendor listed for mediatek in kernel vendor file 'vendor-prefixes.yaml'
contains 'mediatek' as a valid vendor string. Some nodes in the device
tree are using an invalid vendor string vfor 'mtk' instead. Fix all of
them in dts file. Update also ralink mt7621 related code to properly
match new strings. Even there are used in the device tree there are
some strings that are not referred anywhere but have been also updated
with new vendor name. These are 'mtk,mt7621-wdt', 'mtk,mt7621-nand',
'mtk,mt7621-mc', and 'mtk,mt7621-cpc'.

Acked-by: Greg Kroah-Hartman 
Signed-off-by: Sergio Paracuellos 
---
 arch/mips/ralink/mt7621.c  |  6 +++---
 drivers/staging/mt7621-dts/mt7621.dtsi | 12 ++--
 2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/arch/mips/ralink/mt7621.c b/arch/mips/ralink/mt7621.c
index ca0ac607b0f3..5d74fc1c96ac 100644
--- a/arch/mips/ralink/mt7621.c
+++ b/arch/mips/ralink/mt7621.c
@@ -112,8 +112,8 @@ phys_addr_t mips_cpc_default_phys_base(void)
 
 void __init ralink_of_remap(void)
 {
-   rt_sysc_membase = plat_of_remap_node("mtk,mt7621-sysc");
-   rt_memc_membase = plat_of_remap_node("mtk,mt7621-memc");
+   rt_sysc_membase = plat_of_remap_node("mediatek,mt7621-sysc");
+   rt_memc_membase = plat_of_remap_node("mediatek,mt7621-memc");
 
if (!rt_sysc_membase || !rt_memc_membase)
panic("Failed to remap core resources");
@@ -181,7 +181,7 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
 
if (n0 == MT7621_CHIP_NAME0 && n1 == MT7621_CHIP_NAME1) {
name = "MT7621";
-   soc_info->compatible = "mtk,mt7621-soc";
+   soc_info->compatible = "mediatek,mt7621-soc";
} else {
panic("mt7621: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
}
diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi 
b/drivers/staging/mt7621-dts/mt7621.dtsi
index b68183e7e6ad..f0c9ae757bcd 100644
--- a/drivers/staging/mt7621-dts/mt7621.dtsi
+++ b/drivers/staging/mt7621-dts/mt7621.dtsi
@@ -56,7 +56,7 @@ palmbus: palmbus@1E00 {
#size-cells = <1>;
 
sysc: sysc@0 {
-   compatible = "mtk,mt7621-sysc", "syscon";
+   compatible = "mediatek,mt7621-sysc", "syscon";
reg = <0x0 0x100>;
#clock-cells = <1>;
ralink,memctl = <>;
@@ -66,7 +66,7 @@ sysc: sysc@0 {
};
 
wdt: wdt@100 {
-   compatible = "mtk,mt7621-wdt";
+   compatible = "mediatek,mt7621-wdt";
reg = <0x100 0x100>;
};
 
@@ -123,17 +123,17 @@ i2s: i2s@a00 {
};
 
memc: memc@5000 {
-   compatible = "mtk,mt7621-memc", "syscon";
+   compatible = "mediatek,mt7621-memc", "syscon";
reg = <0x5000 0x1000>;
};
 
cpc: cpc@1fbf {
-compatible = "mtk,mt7621-cpc";
+compatible = "mediatek,mt7621-cpc";
 reg = <0x1fbf 0x8000>;
};
 
mc: mc@1fbf8000 {
-   compatible = "mtk,mt7621-mc";
+   compatible = "mediatek,mt7621-mc";
reg = <0x1fbf8000 0x8000>;
};
 
@@ -361,7 +361,7 @@ timer {
nand: nand@1e003000 {
status = "disabled";
 
-   compatible = "mtk,mt7621-nand";
+   compatible = "mediatek,mt7621-nand";
bank-width = <2>;
reg = <0x1e003000 0x800
0x1e003800 0x800>;
-- 
2.25.1

[PATCH v10 2/6] dt: bindings: add mt7621-sysc device tree binding documentation

Adds device tree binding documentation for clocks in the
MT7621 SOC.

Signed-off-by: Sergio Paracuellos 
---
 .../bindings/clock/mediatek,mt7621-sysc.yaml  | 68 +++
 1 file changed, 68 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml

diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml 
b/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml
new file mode 100644
index ..ef2d71b23ba0
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/mediatek,mt7621-sysc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MT7621 Clock Device Tree Bindings
+
+maintainers:
+  - Sergio Paracuellos 
+
+description: |
+  The MT7621 has a PLL controller from where the cpu clock is provided
+  as well as derived clocks for the bus and the peripherals. It also
+  can gate SoC device clocks.
+
+  Each clock is assigned an identifier and client nodes use this identifier
+  to specify the clock which they consume.
+
+  All these identifiers could be found in:
+  [1]: .
+
+  The clocks are provided inside a system controller node.
+
+properties:
+  compatible:
+items:
+  - const: mediatek,mt7621-sysc
+  - const: syscon
+
+  reg:
+maxItems: 1
+
+  "#clock-cells":
+description:
+  The first cell indicates the clock number, see [1] for available
+  clocks.
+const: 1
+
+  ralink,memctl:
+$ref: /schemas/types.yaml#/definitions/phandle
+description:
+  phandle of syscon used to control memory registers
+
+  clock-output-names:
+maxItems: 8
+
+required:
+  - compatible
+  - reg
+  - '#clock-cells'
+  - ralink,memctl
+
+additionalProperties: false
+
+examples:
+  - |
+#include 
+
+sysc: sysc@0 {
+  compatible = "mediatek,mt7621-sysc", "syscon";
+  reg = <0x0 0x100>;
+  #clock-cells = <1>;
+  ralink,memctl = <>;
+  clock-output-names = "xtal", "cpu", "bus",
+   "50m", "125m", "150m",
+   "250m", "270m";
+};
-- 
2.25.1

[PATCH v10 4/6] staging: mt7621-dts: make use of new 'mt7621-clk'

Clocks for SoC mt7621 have been properly integrated so there is
no need to declare fixed clocks at all in the device tree. Remove
all of them, add new device tree nodes for mt7621-clk and update
the rest of the nodes to use them.

Acked-by: Greg Kroah-Hartman 
Signed-off-by: Sergio Paracuellos 
---
 drivers/staging/mt7621-dts/gbpc1.dts   | 11 
 drivers/staging/mt7621-dts/mt7621.dtsi | 74 --
 2 files changed, 33 insertions(+), 52 deletions(-)

diff --git a/drivers/staging/mt7621-dts/gbpc1.dts 
b/drivers/staging/mt7621-dts/gbpc1.dts
index a7c0d3115d72..7716d0efe524 100644
--- a/drivers/staging/mt7621-dts/gbpc1.dts
+++ b/drivers/staging/mt7621-dts/gbpc1.dts
@@ -100,17 +100,6 @@ partition@5 {
};
 };
 
- {
-   compatible = "fixed-clock";
-   /* This is normally 1/4 of cpuclock */
-   clock-frequency = <22500>;
-};
-
- {
-   compatible = "fixed-clock";
-   clock-frequency = <9>;
-};
-
  {
pinctrl-names = "default";
pinctrl-0 = <_pins>;
diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi 
b/drivers/staging/mt7621-dts/mt7621.dtsi
index 16fc94f65486..b68183e7e6ad 100644
--- a/drivers/staging/mt7621-dts/mt7621.dtsi
+++ b/drivers/staging/mt7621-dts/mt7621.dtsi
@@ -1,5 +1,6 @@
 #include 
 #include 
+#include 
 
 / {
#address-cells = <1>;
@@ -27,27 +28,6 @@ aliases {
serial0 = 
};
 
-   cpuclock: cpuclock@0 {
-   #clock-cells = <0>;
-   compatible = "fixed-clock";
-
-   /* FIXME: there should be way to detect this */
-   clock-frequency = <88000>;
-   };
-
-   sysclock: sysclock@0 {
-   #clock-cells = <0>;
-   compatible = "fixed-clock";
-
-   /* This is normally 1/4 of cpuclock */
-   clock-frequency = <22000>;
-   };
-
-   mmc_clock: mmc_clock@0 {
-   #clock-cells = <0>;
-   compatible = "fixed-clock";
-   clock-frequency = <4800>;
-   };
 
mmc_fixed_3v3: fixedregulator@0 {
compatible = "regulator-fixed";
@@ -76,8 +56,13 @@ palmbus: palmbus@1E00 {
#size-cells = <1>;
 
sysc: sysc@0 {
-   compatible = "mtk,mt7621-sysc";
+   compatible = "mtk,mt7621-sysc", "syscon";
reg = <0x0 0x100>;
+   #clock-cells = <1>;
+   ralink,memctl = <>;
+   clock-output-names = "xtal", "cpu", "bus",
+"50m", "125m", "150m",
+"250m", "270m";
};
 
wdt: wdt@100 {
@@ -101,8 +86,8 @@ i2c: i2c@900 {
compatible = "mediatek,mt7621-i2c";
reg = <0x900 0x100>;
 
-   clocks = <>;
-
+   clocks = < MT7621_CLK_I2C>;
+   clock-names = "i2c";
resets = < 16>;
reset-names = "i2c";
 
@@ -119,8 +104,8 @@ i2s: i2s@a00 {
compatible = "mediatek,mt7621-i2s";
reg = <0xa00 0x100>;
 
-   clocks = <>;
-
+   clocks = < MT7621_CLK_I2S>;
+   clock-names = "i2s";
resets = < 17>;
reset-names = "i2s";
 
@@ -138,7 +123,7 @@ i2s: i2s@a00 {
};
 
memc: memc@5000 {
-   compatible = "mtk,mt7621-memc";
+   compatible = "mtk,mt7621-memc", "syscon";
reg = <0x5000 0x1000>;
};
 
@@ -156,8 +141,8 @@ uartlite: uartlite@c00 {
compatible = "ns16550a";
reg = <0xc00 0x100>;
 
-   clocks = <>;
-   clock-frequency = <5000>;
+   clocks = < MT7621_CLK_UART1>;
+   clock-names = "uart1";
 
interrupt-parent = <>;
interrupts = ;
@@ -173,7 +158,8 @@ spi0: spi@b00 {
compatible = "ralink,mt7621-spi";
reg = <0xb00 0x100>;
 
-   clocks = <>;
+   clocks = < MT7621_CLK_SPI>;
+

[PATCH v10 1/6] dt-bindings: clock: add dt binding header for mt7621 clocks

Adds dt binding header for 'mediatek,mt7621-clk' clocks.

Acked-by: Rob Herring 
Signed-off-by: Sergio Paracuellos 
---
 include/dt-bindings/clock/mt7621-clk.h | 41 ++
 1 file changed, 41 insertions(+)
 create mode 100644 include/dt-bindings/clock/mt7621-clk.h

diff --git a/include/dt-bindings/clock/mt7621-clk.h 
b/include/dt-bindings/clock/mt7621-clk.h
new file mode 100644
index ..1422badcf9de
--- /dev/null
+++ b/include/dt-bindings/clock/mt7621-clk.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Author: Sergio Paracuellos 
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT7621_H
+#define _DT_BINDINGS_CLK_MT7621_H
+
+#define MT7621_CLK_XTAL0
+#define MT7621_CLK_CPU 1
+#define MT7621_CLK_BUS 2
+#define MT7621_CLK_50M 3
+#define MT7621_CLK_125M4
+#define MT7621_CLK_150M5
+#define MT7621_CLK_250M6
+#define MT7621_CLK_270M7
+
+#define MT7621_CLK_HSDMA   8
+#define MT7621_CLK_FE  9
+#define MT7621_CLK_SP_DIVTX10
+#define MT7621_CLK_TIMER   11
+#define MT7621_CLK_PCM 12
+#define MT7621_CLK_PIO 13
+#define MT7621_CLK_GDMA14
+#define MT7621_CLK_NAND15
+#define MT7621_CLK_I2C 16
+#define MT7621_CLK_I2S 17
+#define MT7621_CLK_SPI 18
+#define MT7621_CLK_UART1   19
+#define MT7621_CLK_UART2   20
+#define MT7621_CLK_UART3   21
+#define MT7621_CLK_ETH 22
+#define MT7621_CLK_PCIE0   23
+#define MT7621_CLK_PCIE1   24
+#define MT7621_CLK_PCIE2   25
+#define MT7621_CLK_CRYPTO  26
+#define MT7621_CLK_SHXC27
+
+#define MT7621_CLK_MAX 28
+
+#endif /* _DT_BINDINGS_CLK_MT7621_H */
-- 
2.25.1

[PATCH v10 0/6] MIPS: ralink: add CPU clock detection and clock driver for MT7621

7621-clk'.
 - Driver is not a platform driver anymore and now make use of 'CLK_OF_DECLARE'
   because we need clocks available in 'plat_time_init' before setting up
   the timer for the GIC.
 - Use new fixed clocks as parents for different gates and deriving from 'xtal'
   using frequencies in[1].
 - Adapt dts file and bindings header and documentation for new changes.
 - Change MAINTAINERS file to only contains clk-mt7621.c code and
   mediatek,mt7621-clk.yaml file.

[0]: https://www.lkml.org/lkml/2019/7/23/1044
[1]: 
https://github.com/981213/linux/commit/2eca1f045e4c3db18c941135464c0d7422ad8133
[2]: https://lkml.org/lkml/2020/12/20/47
[3]: 
http://driverdev.linuxdriverproject.org/pipermail/driverdev-devel/2021-February/150772.html

Sergio Paracuellos (6):
  dt-bindings: clock: add dt binding header for mt7621 clocks
  dt: bindings: add mt7621-sysc device tree binding documentation
  clk: ralink: add clock driver for mt7621 SoC
  staging: mt7621-dts: make use of new 'mt7621-clk'
  staging: mt7621-dts: use valid vendor 'mediatek' instead of invalid
'mtk'
  MAINTAINERS: add MT7621 CLOCK maintainer

 .../bindings/clock/mediatek,mt7621-sysc.yaml  |  68 +++
 MAINTAINERS   |   6 +
 arch/mips/ralink/mt7621.c |   6 +-
 drivers/clk/Kconfig   |   1 +
 drivers/clk/Makefile  |   1 +
 drivers/clk/ralink/Kconfig|  15 +
 drivers/clk/ralink/Makefile   |   2 +
 drivers/clk/ralink/clk-mt7621.c   | 528 ++
 drivers/staging/mt7621-dts/gbpc1.dts  |  11 -
 drivers/staging/mt7621-dts/mt7621.dtsi|  82 ++-
 include/dt-bindings/clock/mt7621-clk.h|  41 ++
 11 files changed, 702 insertions(+), 59 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml
 create mode 100644 drivers/clk/ralink/Kconfig
 create mode 100644 drivers/clk/ralink/Makefile
 create mode 100644 drivers/clk/ralink/clk-mt7621.c
 create mode 100644 include/dt-bindings/clock/mt7621-clk.h

-- 
2.25.1

Re: [PATCH v9 2/6] dt: bindings: add mt7621-clk device tree binding documentation

Hi,
On Sat, Mar 6, 2021 at 10:54 AM Sergio Paracuellos
 wrote:
>
> Hi again,
>
> On Sat, Mar 6, 2021 at 8:12 AM Sergio Paracuellos
>  wrote:
> >
> > Hi Rob,
> >
> > On Fri, Mar 5, 2021 at 11:47 PM Rob Herring  wrote:
> > [snip]
> > > > +
> > > > +  ralink,sysctl:
> > > > +$ref: /schemas/types.yaml#/definitions/phandle
> > > > +description:
> > > > +  phandle of syscon used to control system registers
> > > > +
> > > > +  ralink,memctl:
> > > > +$ref: /schemas/types.yaml#/definitions/phandle
> > > > +description:
> > > > +  phandle of syscon used to control memory registers
> > >
> > > I assume one of these phandles are the main registers for the clocks?
> > > Make this a child node and drop that phandle.
> >
> > The 'ralink,sysctl' phandle is to read bootstrap register to be able
> > to derive xtal and a clk gate register for the peripherals.
> > The 'ralink,memctl' phandle is to read the cpu clock frequency from
> > the memory controller.
> >
> > So there is not "main registers". I already put this as a child node
> > in v4 and I was told to get rid of child nodes. I need this as a
> > regmap to other DT node registers (sysctl, and memctl) to be able to
> > use the driver without specific architecture operations and properly
> > enable for COMPILE_TEST without dirty Makefile arch flags. Both sysctl
> > and memctl has no other child nodes, and I think that's why I was told
> > to avoid child nodes at the end. I explained here [0] current sysctl
> > and memctl in the mt7621 device tree and my view of the need for this
> > two syscons:
> >
> > [0]: https://lkml.org/lkml/2021/1/2/9
> >
> > So to avoid to send again "a previous version" on this patch, please
> > guide me in the correct thing to do. Stephen, Rob, I will be really
> > happy with your help :)
>
> Since there are no other child nodes for this sysc, should merge clock
> properties
> with this node in the following way a valid approach:
>
>  sysc: sysc@0 {
>  compatible = "mediatek,mt7621-sysc", "syscon";
>  reg = <0x0 0x100>;
>  #clock-cells = <1>;
>  ralink,memctl = <>;
>  clock-output-names = "xtal", "cpu", "bus",
> "50m", "125m", "150m",
> "250m", "270m";
> };
>
> Consumer clock:
>
> node: node@0 {
>   ...
>   clocks = < MT7621_CLK_WHATEVER>;
>  ...
> };

I have been reviewing bindings review comments along the time and I
was already suggested to do this I am saying here (see [0]) but my
mind seems that filtered it for any reason I don't really understand.
Maybe I should sleep a bit more :).

I will send v10 with these changes that hopefully will be the correct ones.

Thanks and sorry for bothering you with already suggested things.

Best regards,
Sergio Paracuellos

[0]: https://lkml.org/lkml/2020/12/31/206

>
> If that is the case... and since 'sysc' is used as system control
> registers for all the rest of the world, where should be the yaml file
> with bindings placed?
>
> Thanks in advance again for your help.
>
> Best regards,
> Sergio Paracuellos
>
> >
> > Best regards,
> > Sergio Paracuellos
> > >
> > > > +
> > > > +  clock-output-names:
> > > > +maxItems: 8
> > > > +
> > > > +required:
> > > > +  - compatible
> > > > +  - '#clock-cells'
> > > > +  - ralink,sysctl
> > > > +  - ralink,memctl
> > > > +
> > > > +additionalProperties: false
> > > > +
> > > > +examples:
> > > > +  - |
> > > > +#include 
> > > > +
> > > > +pll {
> > > > +  compatible = "mediatek,mt7621-clk";
> > > > +  #clock-cells = <1>;
> > > > +  ralink,sysctl = <>;
> > > > +  ralink,memctl = <>;
> > > > +  clock-output-names = "xtal", "cpu", "bus",
> > > > +   "50m", "125m", "150m",
> > > > +   "250m", "270m";
> > > > +};
> > > > --
> > > > 2.25.1
> > > >

Re: [PATCH v9 2/6] dt: bindings: add mt7621-clk device tree binding documentation

Hi again,

On Sat, Mar 6, 2021 at 8:12 AM Sergio Paracuellos
 wrote:
>
> Hi Rob,
>
> On Fri, Mar 5, 2021 at 11:47 PM Rob Herring  wrote:
> [snip]
> > > +
> > > +  ralink,sysctl:
> > > +$ref: /schemas/types.yaml#/definitions/phandle
> > > +description:
> > > +  phandle of syscon used to control system registers
> > > +
> > > +  ralink,memctl:
> > > +$ref: /schemas/types.yaml#/definitions/phandle
> > > +description:
> > > +  phandle of syscon used to control memory registers
> >
> > I assume one of these phandles are the main registers for the clocks?
> > Make this a child node and drop that phandle.
>
> The 'ralink,sysctl' phandle is to read bootstrap register to be able
> to derive xtal and a clk gate register for the peripherals.
> The 'ralink,memctl' phandle is to read the cpu clock frequency from
> the memory controller.
>
> So there is not "main registers". I already put this as a child node
> in v4 and I was told to get rid of child nodes. I need this as a
> regmap to other DT node registers (sysctl, and memctl) to be able to
> use the driver without specific architecture operations and properly
> enable for COMPILE_TEST without dirty Makefile arch flags. Both sysctl
> and memctl has no other child nodes, and I think that's why I was told
> to avoid child nodes at the end. I explained here [0] current sysctl
> and memctl in the mt7621 device tree and my view of the need for this
> two syscons:
>
> [0]: https://lkml.org/lkml/2021/1/2/9
>
> So to avoid to send again "a previous version" on this patch, please
> guide me in the correct thing to do. Stephen, Rob, I will be really
> happy with your help :)

Since there are no other child nodes for this sysc, should merge clock
properties
with this node in the following way a valid approach:

 sysc: sysc@0 {
 compatible = "mediatek,mt7621-sysc", "syscon";
 reg = <0x0 0x100>;
 #clock-cells = <1>;
 ralink,memctl = <>;
 clock-output-names = "xtal", "cpu", "bus",
"50m", "125m", "150m",
"250m", "270m";
};

Consumer clock:

node: node@0 {
  ...
  clocks = < MT7621_CLK_WHATEVER>;
 ...
};

If that is the case... and since 'sysc' is used as system control
registers for all the rest of the world, where should be the yaml file
with bindings placed?

Thanks in advance again for your help.

Best regards,
Sergio Paracuellos

>
> Best regards,
> Sergio Paracuellos
> >
> > > +
> > > +  clock-output-names:
> > > +maxItems: 8
> > > +
> > > +required:
> > > +  - compatible
> > > +  - '#clock-cells'
> > > +  - ralink,sysctl
> > > +  - ralink,memctl
> > > +
> > > +additionalProperties: false
> > > +
> > > +examples:
> > > +  - |
> > > +#include 
> > > +
> > > +pll {
> > > +  compatible = "mediatek,mt7621-clk";
> > > +  #clock-cells = <1>;
> > > +  ralink,sysctl = <>;
> > > +  ralink,memctl = <>;
> > > +  clock-output-names = "xtal", "cpu", "bus",
> > > +   "50m", "125m", "150m",
> > > +   "250m", "270m";
> > > +};
> > > --
> > > 2.25.1
> > >

Re: [PATCH v9 2/6] dt: bindings: add mt7621-clk device tree binding documentation

2021-03-05 Thread Sergio Paracuellos

Hi Rob,

On Fri, Mar 5, 2021 at 11:47 PM Rob Herring  wrote:
[snip]
> > +
> > +  ralink,sysctl:
> > +$ref: /schemas/types.yaml#/definitions/phandle
> > +description:
> > +  phandle of syscon used to control system registers
> > +
> > +  ralink,memctl:
> > +$ref: /schemas/types.yaml#/definitions/phandle
> > +description:
> > +  phandle of syscon used to control memory registers
>
> I assume one of these phandles are the main registers for the clocks?
> Make this a child node and drop that phandle.

The 'ralink,sysctl' phandle is to read bootstrap register to be able
to derive xtal and a clk gate register for the peripherals.
The 'ralink,memctl' phandle is to read the cpu clock frequency from
the memory controller.

So there is not "main registers". I already put this as a child node
in v4 and I was told to get rid of child nodes. I need this as a
regmap to other DT node registers (sysctl, and memctl) to be able to
use the driver without specific architecture operations and properly
enable for COMPILE_TEST without dirty Makefile arch flags. Both sysctl
and memctl has no other child nodes, and I think that's why I was told
to avoid child nodes at the end. I explained here [0] current sysctl
and memctl in the mt7621 device tree and my view of the need for this
two syscons:

[0]: https://lkml.org/lkml/2021/1/2/9

So to avoid to send again "a previous version" on this patch, please
guide me in the correct thing to do. Stephen, Rob, I will be really
happy with your help :)

Best regards,
Sergio Paracuellos
>
> > +
> > +  clock-output-names:
> > +maxItems: 8
> > +
> > +required:
> > +  - compatible
> > +  - '#clock-cells'
> > +  - ralink,sysctl
> > +  - ralink,memctl
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +#include 
> > +
> > +pll {
> > +  compatible = "mediatek,mt7621-clk";
> > +  #clock-cells = <1>;
> > +  ralink,sysctl = <>;
> > +  ralink,memctl = <>;
> > +  clock-output-names = "xtal", "cpu", "bus",
> > +   "50m", "125m", "150m",
> > +   "250m", "270m";
> > +};
> > --
> > 2.25.1
> >

Re: [PATCH -next] phy: ralink: phy-mt7621-pci: fix return value check in mt7621_pci_phy_probe()

2021-03-04 Thread Sergio Paracuellos

On Fri, Mar 5, 2021 at 4:40 AM 'Wei Yongjun  wrote:
>
> From: Wei Yongjun 
>
> Fix the return value check which testing the wrong variable
> in mt7621_pci_phy_probe().
>
> Fixes: d87da32372a0 ("phy: ralink: Add PHY driver for MT7621 PCIe PHY")
> Reported-by: Hulk Robot 
> Signed-off-by: Wei Yongjun 
> ---
>  drivers/phy/ralink/phy-mt7621-pci.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)

Reviewed-by: Sergio Paracuellos

[PATCH] phy: ralink: phy-mt7621-pci: fix XTAL bitmask

2021-03-02 Thread Sergio Paracuellos

When this was rewriten to get mainlined and start to
use 'linux/bitfield.h' headers, XTAL_MASK was wrong.
It must mask three bits but only two were used. Hence
properly fix it to make things work.

Fixes: d87da32372a0 ("phy: ralink: Add PHY driver for MT7621 PCIe PHY")
Signed-off-by: Sergio Paracuellos 
---
 drivers/phy/ralink/phy-mt7621-pci.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/phy/ralink/phy-mt7621-pci.c 
b/drivers/phy/ralink/phy-mt7621-pci.c
index 9a610b414b1f..84ee2b5c2228 100644
--- a/drivers/phy/ralink/phy-mt7621-pci.c
+++ b/drivers/phy/ralink/phy-mt7621-pci.c
@@ -62,7 +62,7 @@
 
 #define RG_PE1_FRC_MSTCKDIVBIT(5)
 
-#define XTAL_MASK  GENMASK(7, 6)
+#define XTAL_MASK  GENMASK(8, 6)
 
 #define MAX_PHYS   2
 
-- 
2.25.1

[PATCH v9 6/6] MAINTAINERS: add MT7621 CLOCK maintainer

Adding myself as maintainer for mt7621 clock driver.

Signed-off-by: Sergio Paracuellos 
---
 MAINTAINERS | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 809a68af5efd..be5ada6b4309 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11288,6 +11288,12 @@ L: linux-wirel...@vger.kernel.org
 S: Maintained
 F: drivers/net/wireless/mediatek/mt7601u/
 
+MEDIATEK MT7621 CLOCK DRIVER
+M: Sergio Paracuellos 
+S: Maintained
+F: Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
+F: drivers/clk/ralink/clk-mt7621.c
+
 MEDIATEK MT7621/28/88 I2C DRIVER
 M: Stefan Roese 
 L: linux-...@vger.kernel.org
-- 
2.25.1

[PATCH v9 5/6] staging: mt7621-dts: use valid vendor 'mediatek' instead of invalid 'mtk'

Vendor listed for mediatek in kernel vendor file 'vendor-prefixes.yaml'
contains 'mediatek' as a valid vendor string. Some nodes in the device
tree are using an invalid vendor string vfor 'mtk' instead. Fix all of
them in dts file. Update also ralink mt7621 related code to properly
match new strings. Even there are used in the device tree there are
some strings that are not referred anywhere but have been also updated
with new vendor name. These are 'mtk,mt7621-wdt', 'mtk,mt7621-nand',
'mtk,mt7621-mc', and 'mtk,mt7621-cpc'.

Acked-by: Greg Kroah-Hartman 
Signed-off-by: Sergio Paracuellos 
---
 arch/mips/ralink/mt7621.c  |  6 +++---
 drivers/staging/mt7621-dts/mt7621.dtsi | 12 ++--
 2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/arch/mips/ralink/mt7621.c b/arch/mips/ralink/mt7621.c
index ca0ac607b0f3..5d74fc1c96ac 100644
--- a/arch/mips/ralink/mt7621.c
+++ b/arch/mips/ralink/mt7621.c
@@ -112,8 +112,8 @@ phys_addr_t mips_cpc_default_phys_base(void)
 
 void __init ralink_of_remap(void)
 {
-   rt_sysc_membase = plat_of_remap_node("mtk,mt7621-sysc");
-   rt_memc_membase = plat_of_remap_node("mtk,mt7621-memc");
+   rt_sysc_membase = plat_of_remap_node("mediatek,mt7621-sysc");
+   rt_memc_membase = plat_of_remap_node("mediatek,mt7621-memc");
 
if (!rt_sysc_membase || !rt_memc_membase)
panic("Failed to remap core resources");
@@ -181,7 +181,7 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
 
if (n0 == MT7621_CHIP_NAME0 && n1 == MT7621_CHIP_NAME1) {
name = "MT7621";
-   soc_info->compatible = "mtk,mt7621-soc";
+   soc_info->compatible = "mediatek,mt7621-soc";
} else {
panic("mt7621: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
}
diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi 
b/drivers/staging/mt7621-dts/mt7621.dtsi
index 11d1670d4339..55784dd48dc5 100644
--- a/drivers/staging/mt7621-dts/mt7621.dtsi
+++ b/drivers/staging/mt7621-dts/mt7621.dtsi
@@ -56,7 +56,7 @@ palmbus: palmbus@1E00 {
#size-cells = <1>;
 
sysc: sysc@0 {
-   compatible = "mtk,mt7621-sysc", "syscon";
+   compatible = "mediatek,mt7621-sysc", "syscon";
reg = <0x0 0x100>;
};
 
@@ -71,7 +71,7 @@ pll: pll {
};
 
wdt: wdt@100 {
-   compatible = "mtk,mt7621-wdt";
+   compatible = "mediatek,mt7621-wdt";
reg = <0x100 0x100>;
};
 
@@ -128,17 +128,17 @@ i2s: i2s@a00 {
};
 
memc: memc@5000 {
-   compatible = "mtk,mt7621-memc", "syscon";
+   compatible = "mediatek,mt7621-memc", "syscon";
reg = <0x5000 0x1000>;
};
 
cpc: cpc@1fbf {
-compatible = "mtk,mt7621-cpc";
+compatible = "mediatek,mt7621-cpc";
 reg = <0x1fbf 0x8000>;
};
 
mc: mc@1fbf8000 {
-   compatible = "mtk,mt7621-mc";
+   compatible = "mediatek,mt7621-mc";
reg = <0x1fbf8000 0x8000>;
};
 
@@ -366,7 +366,7 @@ timer {
nand: nand@1e003000 {
status = "disabled";
 
-   compatible = "mtk,mt7621-nand";
+   compatible = "mediatek,mt7621-nand";
bank-width = <2>;
reg = <0x1e003000 0x800
0x1e003800 0x800>;
-- 
2.25.1

[PATCH v9 3/6] clk: ralink: add clock driver for mt7621 SoC

The documentation for this SOC only talks about two
registers regarding to the clocks:
* SYSC_REG_CPLL_CLKCFG0 - provides some information about
boostrapped refclock. PLL and dividers used for CPU and some
sort of BUS.
* SYSC_REG_CPLL_CLKCFG1 - a banch of gates to enable/disable
clocks for all or some ip cores.

Looking into driver code, and some openWRT patched there are
another frequencies which are used in some drivers (uart, sd...).
According to all of this information the clock plan for this
SoC is set as follows:
- Main top clock "xtal" from where all the rest of the world is
derived.
- CPU clock "cpu" derived from "xtal" frequencies and a bunch of
register reads and predividers.
- BUS clock "bus" derived from "cpu" and with (cpu / 4) MHz.
- Fixed clocks from "xtal":
* "50m": 50 MHz.
* "125m": 125 MHz.
* "150m": 150 MHz.
* "250m": 250 MHz.
* "270m": 270 MHz.

We also have a buch of gate clocks with their parents:
  * "hsdma": "150m"
  * "fe": "250m"
  * "sp_divtx": "270m"
  * "timer": "50m"
  * "pcm": "270m"
  * "pio": "50m"
  * "gdma": "bus"
  * "nand": "125m"
  * "i2c": "50m"
  * "i2s": "270m"
  * "spi": "bus"
  * "uart1": "50m"
  * "uart2": "50m"
  * "uart3": "50m"
  * "eth": "50m"
  * "pcie0": "125m"
  * "pcie1": "125m"
  * "pcie2": "125m"
  * "crypto": "250m"
  * "shxc": "50m"

With this information the clk driver will provide clock and gates
functionality from a a set of hardcoded clocks allowing to define
a nice device tree without fixed clocks.

Signed-off-by: Sergio Paracuellos 
---
 drivers/clk/Kconfig |   1 +
 drivers/clk/Makefile|   1 +
 drivers/clk/ralink/Kconfig  |  15 +
 drivers/clk/ralink/Makefile |   2 +
 drivers/clk/ralink/clk-mt7621.c | 536 
 5 files changed, 555 insertions(+)
 create mode 100644 drivers/clk/ralink/Kconfig
 create mode 100644 drivers/clk/ralink/Makefile
 create mode 100644 drivers/clk/ralink/clk-mt7621.c

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 7c5dc348c16f..70b23da997bf 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -382,6 +382,7 @@ source "drivers/clk/mediatek/Kconfig"
 source "drivers/clk/meson/Kconfig"
 source "drivers/clk/mvebu/Kconfig"
 source "drivers/clk/qcom/Kconfig"
+source "drivers/clk/ralink/Kconfig"
 source "drivers/clk/renesas/Kconfig"
 source "drivers/clk/rockchip/Kconfig"
 source "drivers/clk/samsung/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 5325847469e9..1b35ad852721 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -98,6 +98,7 @@ obj-$(CONFIG_COMMON_CLK_NXP)  += nxp/
 obj-$(CONFIG_MACH_PISTACHIO)   += pistachio/
 obj-$(CONFIG_COMMON_CLK_PXA)   += pxa/
 obj-$(CONFIG_COMMON_CLK_QCOM)  += qcom/
+obj-y  += ralink/
 obj-y  += renesas/
 obj-$(CONFIG_ARCH_ROCKCHIP)+= rockchip/
 obj-$(CONFIG_COMMON_CLK_SAMSUNG)   += samsung/
diff --git a/drivers/clk/ralink/Kconfig b/drivers/clk/ralink/Kconfig
new file mode 100644
index ..3e3f5cb9ad88
--- /dev/null
+++ b/drivers/clk/ralink/Kconfig
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# MediaTek Mt7621 Clock Driver
+#
+menu "Clock driver for Mediatek mt7621 SoC"
+   depends on SOC_MT7621 || COMPILE_TEST
+
+config CLK_MT7621
+   bool "Clock driver for MediaTek MT7621"
+   depends on SOC_MT7621 || COMPILE_TEST
+   default SOC_MT7621
+   select MFD_SYSCON
+   help
+ This driver supports MediaTek MT7621 basic clocks.
+endmenu
diff --git a/drivers/clk/ralink/Makefile b/drivers/clk/ralink/Makefile
new file mode 100644
index ..cf6f9216379d
--- /dev/null
+++ b/drivers/clk/ralink/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_CLK_MT7621) += clk-mt7621.o
diff --git a/drivers/clk/ralink/clk-mt7621.c b/drivers/clk/ralink/clk-mt7621.c
new file mode 100644
index ..b32b19fd093e
--- /dev/null
+++ b/drivers/clk/ralink/clk-mt7621.c
@@ -0,0 +1,536 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Mediatek MT7621 Clock Driver
+ * Author: Sergio Paracuellos 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* Configuration registers */
+#define SYSC_REG_SYSTEM_CONFIG0 0x10
+#define SYSC_REG_SYSTEM

[PATCH v9 2/6] dt: bindings: add mt7621-clk device tree binding documentation

Adds device tree binding documentation for clocks in the
MT7621 SOC.

Signed-off-by: Sergio Paracuellos 
---
 .../bindings/clock/mediatek,mt7621-clk.yaml   | 66 +++
 1 file changed, 66 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml

diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml 
b/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
new file mode 100644
index ..842a0f2c9d40
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
@@ -0,0 +1,66 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/mediatek,mt7621-clk.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MT7621 Clock Device Tree Bindings
+
+maintainers:
+  - Sergio Paracuellos 
+
+description: |
+  The MT7621 has a PLL controller from where the cpu clock is provided
+  as well as derived clocks for the bus and the peripherals. It also
+  can gate SoC device clocks.
+
+  Each clock is assigned an identifier and client nodes use this identifier
+  to specify the clock which they consume.
+
+  All these identifiers could be found in:
+  [1]: .
+
+properties:
+  compatible:
+const: mediatek,mt7621-clk
+
+  "#clock-cells":
+description:
+  The first cell indicates the clock number, see [1] for available
+  clocks.
+const: 1
+
+  ralink,sysctl:
+$ref: /schemas/types.yaml#/definitions/phandle
+description:
+  phandle of syscon used to control system registers
+
+  ralink,memctl:
+$ref: /schemas/types.yaml#/definitions/phandle
+description:
+  phandle of syscon used to control memory registers
+
+  clock-output-names:
+maxItems: 8
+
+required:
+  - compatible
+  - '#clock-cells'
+  - ralink,sysctl
+  - ralink,memctl
+
+additionalProperties: false
+
+examples:
+  - |
+#include 
+
+pll {
+  compatible = "mediatek,mt7621-clk";
+  #clock-cells = <1>;
+  ralink,sysctl = <>;
+  ralink,memctl = <>;
+  clock-output-names = "xtal", "cpu", "bus",
+   "50m", "125m", "150m",
+   "250m", "270m";
+};
-- 
2.25.1

[PATCH v9 1/6] dt-bindings: clock: add dt binding header for mt7621 clocks

Adds dt binding header for 'mediatek,mt7621-clk' clocks.

Acked-by: Rob Herring 
Signed-off-by: Sergio Paracuellos 
---
 include/dt-bindings/clock/mt7621-clk.h | 41 ++
 1 file changed, 41 insertions(+)
 create mode 100644 include/dt-bindings/clock/mt7621-clk.h

diff --git a/include/dt-bindings/clock/mt7621-clk.h 
b/include/dt-bindings/clock/mt7621-clk.h
new file mode 100644
index ..1422badcf9de
--- /dev/null
+++ b/include/dt-bindings/clock/mt7621-clk.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Author: Sergio Paracuellos 
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT7621_H
+#define _DT_BINDINGS_CLK_MT7621_H
+
+#define MT7621_CLK_XTAL0
+#define MT7621_CLK_CPU 1
+#define MT7621_CLK_BUS 2
+#define MT7621_CLK_50M 3
+#define MT7621_CLK_125M4
+#define MT7621_CLK_150M5
+#define MT7621_CLK_250M6
+#define MT7621_CLK_270M7
+
+#define MT7621_CLK_HSDMA   8
+#define MT7621_CLK_FE  9
+#define MT7621_CLK_SP_DIVTX10
+#define MT7621_CLK_TIMER   11
+#define MT7621_CLK_PCM 12
+#define MT7621_CLK_PIO 13
+#define MT7621_CLK_GDMA14
+#define MT7621_CLK_NAND15
+#define MT7621_CLK_I2C 16
+#define MT7621_CLK_I2S 17
+#define MT7621_CLK_SPI 18
+#define MT7621_CLK_UART1   19
+#define MT7621_CLK_UART2   20
+#define MT7621_CLK_UART3   21
+#define MT7621_CLK_ETH 22
+#define MT7621_CLK_PCIE0   23
+#define MT7621_CLK_PCIE1   24
+#define MT7621_CLK_PCIE2   25
+#define MT7621_CLK_CRYPTO  26
+#define MT7621_CLK_SHXC27
+
+#define MT7621_CLK_MAX 28
+
+#endif /* _DT_BINDINGS_CLK_MT7621_H */
-- 
2.25.1

[PATCH v9 4/6] staging: mt7621-dts: make use of new 'mt7621-clk'

Clocks for SoC mt7621 have been properly integrated so there is
no need to declare fixed clocks at all in the device tree. Remove
all of them, add new device tree nodes for mt7621-clk and update
the rest of the nodes to use them.

Acked-by: Greg Kroah-Hartman 
Signed-off-by: Sergio Paracuellos 
---
 drivers/staging/mt7621-dts/gbpc1.dts   | 11 
 drivers/staging/mt7621-dts/mt7621.dtsi | 79 +-
 2 files changed, 38 insertions(+), 52 deletions(-)

diff --git a/drivers/staging/mt7621-dts/gbpc1.dts 
b/drivers/staging/mt7621-dts/gbpc1.dts
index a7c0d3115d72..7716d0efe524 100644
--- a/drivers/staging/mt7621-dts/gbpc1.dts
+++ b/drivers/staging/mt7621-dts/gbpc1.dts
@@ -100,17 +100,6 @@ partition@5 {
};
 };
 
- {
-   compatible = "fixed-clock";
-   /* This is normally 1/4 of cpuclock */
-   clock-frequency = <22500>;
-};
-
- {
-   compatible = "fixed-clock";
-   clock-frequency = <9>;
-};
-
  {
pinctrl-names = "default";
pinctrl-0 = <_pins>;
diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi 
b/drivers/staging/mt7621-dts/mt7621.dtsi
index 16fc94f65486..11d1670d4339 100644
--- a/drivers/staging/mt7621-dts/mt7621.dtsi
+++ b/drivers/staging/mt7621-dts/mt7621.dtsi
@@ -1,5 +1,6 @@
 #include 
 #include 
+#include 
 
 / {
#address-cells = <1>;
@@ -27,27 +28,6 @@ aliases {
serial0 = 
};
 
-   cpuclock: cpuclock@0 {
-   #clock-cells = <0>;
-   compatible = "fixed-clock";
-
-   /* FIXME: there should be way to detect this */
-   clock-frequency = <88000>;
-   };
-
-   sysclock: sysclock@0 {
-   #clock-cells = <0>;
-   compatible = "fixed-clock";
-
-   /* This is normally 1/4 of cpuclock */
-   clock-frequency = <22000>;
-   };
-
-   mmc_clock: mmc_clock@0 {
-   #clock-cells = <0>;
-   compatible = "fixed-clock";
-   clock-frequency = <4800>;
-   };
 
mmc_fixed_3v3: fixedregulator@0 {
compatible = "regulator-fixed";
@@ -76,10 +56,20 @@ palmbus: palmbus@1E00 {
#size-cells = <1>;
 
sysc: sysc@0 {
-   compatible = "mtk,mt7621-sysc";
+   compatible = "mtk,mt7621-sysc", "syscon";
reg = <0x0 0x100>;
};
 
+   pll: pll {
+   compatible = "mediatek,mt7621-clk";
+   #clock-cells = <1>;
+   ralink,sysctl = <>;
+   ralink,memctl = <>;
+   clock-output-names = "xtal", "cpu", "bus",
+"50m", "125m", "150m",
+"250m", "270m";
+   };
+
wdt: wdt@100 {
compatible = "mtk,mt7621-wdt";
reg = <0x100 0x100>;
@@ -101,8 +91,8 @@ i2c: i2c@900 {
compatible = "mediatek,mt7621-i2c";
reg = <0x900 0x100>;
 
-   clocks = <>;
-
+   clocks = < MT7621_CLK_I2C>;
+   clock-names = "i2c";
resets = < 16>;
reset-names = "i2c";
 
@@ -119,8 +109,8 @@ i2s: i2s@a00 {
compatible = "mediatek,mt7621-i2s";
reg = <0xa00 0x100>;
 
-   clocks = <>;
-
+   clocks = < MT7621_CLK_I2S>;
+   clock-names = "i2s";
resets = < 17>;
reset-names = "i2s";
 
@@ -138,7 +128,7 @@ i2s: i2s@a00 {
};
 
memc: memc@5000 {
-   compatible = "mtk,mt7621-memc";
+   compatible = "mtk,mt7621-memc", "syscon";
reg = <0x5000 0x1000>;
};
 
@@ -156,8 +146,8 @@ uartlite: uartlite@c00 {
compatible = "ns16550a";
reg = <0xc00 0x100>;
 
-   clocks = <>;
-   clock-frequency = <5000>;
+   clocks = < MT7621_CLK_UART1>;
+   clock-names = "uart1";
 
interrupt-parent = <>;

[PATCH v9 0/6] MIPS: ralink: add CPU clock detection and clock driver for MT7621

ap handlers
   to be able to use regmap operations from normal clock api functions. Add
   this pointer in 'mt7621_clk' and 'mt7621_clk_gate' before register its
   related clocks to make things work.
 - Add Greg's Acked-by in patches 4 and 5.
 - Rebase this series on the top of linux-next tag 'next-20210215'.

v5 RESEND notes:
 - I am resending this as I was told to do that.
 - Please, take into account Rob's comments to DT node patch and my
   reply with explanation about how are the current device tree nodes
   for this architecture being used in [2].

Changes in v5:
 - Avoid the use of syscon. All drivers of this platform are just using
   platform operations defined in 'asm/mach-ralink/ralink_regs.h'. We also
   need them for some PLL registers that are not in the sys control area.
   Hence, since we must use this dependency avoid to define clock driver
   as a child of the sysc node in the device tree and follow current
   platform code style.
 - Update bindings documentation to don't refer the syscon and make
   remove 'clock-output-names' property from required ones.
 - Use 'asm/mach-ralink/ralink_regs.h' platform read and write operations
   instead of regmap from the syscon node.
 - Remove 'mt7621_clk_provider' and directly declare 'clk_hw_onecell_data'
   pointer in 'mt7621_clk_init' and pass from there into different register
   functions. Remove pointers to 'mt7621_clk_provider' in the rest fo structs
   used in this driver.
 - Remove MHZ macro and just pass values directly in hertzs.
 - Avoid 'CLK_IGNORE_UNUSED' flag for gates and add a new function called
   'mt7621_prepare_enable_clocks' to prepare all of them to make clocks
   referenced and don't affect current driver code.
 - Remove COMPILE_TEST from Kconfig because of the use of especific arch
   stuff.
 - Fix commit message where a typo for "frequencies" word was present.
 - Make use of parent_clk_data in 'CLK_BASE' macro.
 - Remove MODULE_* macros from code since this is not a module.
 - Remove not needed includes.
 - Hardcode "xtal" as parent in FIXED macro.
 - Change 'else if' clause into 'if' clause since a return statement was
   being used in 'mt7621_xtal_recalc_rate'.

 NOTES:
   - Driver is still being declared using 'CLK_OF_DECLARE' for all the  
 clocks. I have explored the possibility to make some of them available
 afterwards using 'CLK_OF_DECLARE_DRIVER' for top clocks and the rest
 using a platform driver. The resulting code was uglier since we only want
 to use the same device tree node and the top clocks must be copied again
 for the new platform register stuff to properly have a good hierarchy.
 New globals needs to be introduced and in this particular case I don't
 really see the benefits of doing in this way. I am totally ok to have all
 the clocks registered at early stage since from other drivers perspective
 we only really need to enable gates. So, I prefer to have them in that
 way if it is not a real problem, of course.

Changes in v4:
 - Add Acked-by from Rob Herring for binding headers (PATCH 1/6).
 - Convert bindings to not use syscon phandle and declare clock as
   a child of the syscon node. Update device tree and binding doc
   accordly.
 - Make use of 'syscon_node_to_regmap' in driver code instead of
   get this using the phandle function.
 - Properly unregister clocks for the error path of the function
   'mt7621_clk_init'.
 - Include ARRAY_SIZE of fixed clocks in the 'count' to kzalloc
   of 'clk_data'.
 - Add new patch changing invalid vendor 'mtk' in favour of 'mediatek'
   which is the one listed in 'vendor-prefixes.yaml'. Update mt7621 code
   accordly. I have added this patch inside this series because clk
   binding is referring syscon node and the string for that node was
   with not listed vendor. Hence update and have all of this correct
   in the same series.

Changes in v3:
 - Fix compilation warnings reported by kernel test robot because of
   ignoring return values of 'of_clk_hw_register' in functions
   'mt7621_register_top_clocks' and 'mt7621_gate_ops_init'.
 - Fix dts file and binding documentation 'clock-output-names'.

Changes in v2:
 - Remove the following patches:
   * dt: bindings: add mt7621-pll device tree binding documentation.
   * MIPS: ralink: add clock device providing cpu/ahb/apb clock for mt7621.
 - Move all relevant clock code to 'drivers/clk/ralink/clk-mt7621.c' and
   unify there previous 'mt7621-pll' and 'mt7621-clk' into a unique driver
   and binding 'mt7621-clk'.
 - Driver is not a platform driver anymore and now make use of 'CLK_OF_DECLARE'
   because we need clocks available in 'plat_time_init' before setting up
   the timer for the GIC.
 - Use new fixed clocks as parents for different gates and deriving from 'xtal'
   using frequencies in[1].
 - Adapt dts file and bindings header and documentation for new changes.
 - Change MAINTAINERS file to only contains clk-mt7621.c code and
   mediatek,mt7621-clk.ya

[PATCH v8 6/6] MAINTAINERS: add MT7621 CLOCK maintainer

Adding myself as maintainer for mt7621 clock driver.

Signed-off-by: Sergio Paracuellos 
---
 MAINTAINERS | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 809a68af5efd..be5ada6b4309 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11288,6 +11288,12 @@ L: linux-wirel...@vger.kernel.org
 S: Maintained
 F: drivers/net/wireless/mediatek/mt7601u/
 
+MEDIATEK MT7621 CLOCK DRIVER
+M: Sergio Paracuellos 
+S: Maintained
+F: Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
+F: drivers/clk/ralink/clk-mt7621.c
+
 MEDIATEK MT7621/28/88 I2C DRIVER
 M: Stefan Roese 
 L: linux-...@vger.kernel.org
-- 
2.25.1

[PATCH v8 4/6] staging: mt7621-dts: make use of new 'mt7621-clk'

Clocks for SoC mt7621 have been properly integrated so there is
no need to declare fixed clocks at all in the device tree. Remove
all of them, add new device tree nodes for mt7621-clk and update
the rest of the nodes to use them.

Acked-by: Greg Kroah-Hartman 
Signed-off-by: Sergio Paracuellos 
---
 drivers/staging/mt7621-dts/gbpc1.dts   | 11 
 drivers/staging/mt7621-dts/mt7621.dtsi | 79 +-
 2 files changed, 38 insertions(+), 52 deletions(-)

diff --git a/drivers/staging/mt7621-dts/gbpc1.dts 
b/drivers/staging/mt7621-dts/gbpc1.dts
index a7c0d3115d72..7716d0efe524 100644
--- a/drivers/staging/mt7621-dts/gbpc1.dts
+++ b/drivers/staging/mt7621-dts/gbpc1.dts
@@ -100,17 +100,6 @@ partition@5 {
};
 };
 
- {
-   compatible = "fixed-clock";
-   /* This is normally 1/4 of cpuclock */
-   clock-frequency = <22500>;
-};
-
- {
-   compatible = "fixed-clock";
-   clock-frequency = <9>;
-};
-
  {
pinctrl-names = "default";
pinctrl-0 = <_pins>;
diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi 
b/drivers/staging/mt7621-dts/mt7621.dtsi
index 16fc94f65486..11d1670d4339 100644
--- a/drivers/staging/mt7621-dts/mt7621.dtsi
+++ b/drivers/staging/mt7621-dts/mt7621.dtsi
@@ -1,5 +1,6 @@
 #include 
 #include 
+#include 
 
 / {
#address-cells = <1>;
@@ -27,27 +28,6 @@ aliases {
serial0 = 
};
 
-   cpuclock: cpuclock@0 {
-   #clock-cells = <0>;
-   compatible = "fixed-clock";
-
-   /* FIXME: there should be way to detect this */
-   clock-frequency = <88000>;
-   };
-
-   sysclock: sysclock@0 {
-   #clock-cells = <0>;
-   compatible = "fixed-clock";
-
-   /* This is normally 1/4 of cpuclock */
-   clock-frequency = <22000>;
-   };
-
-   mmc_clock: mmc_clock@0 {
-   #clock-cells = <0>;
-   compatible = "fixed-clock";
-   clock-frequency = <4800>;
-   };
 
mmc_fixed_3v3: fixedregulator@0 {
compatible = "regulator-fixed";
@@ -76,10 +56,20 @@ palmbus: palmbus@1E00 {
#size-cells = <1>;
 
sysc: sysc@0 {
-   compatible = "mtk,mt7621-sysc";
+   compatible = "mtk,mt7621-sysc", "syscon";
reg = <0x0 0x100>;
};
 
+   pll: pll {
+   compatible = "mediatek,mt7621-clk";
+   #clock-cells = <1>;
+   ralink,sysctl = <>;
+   ralink,memctl = <>;
+   clock-output-names = "xtal", "cpu", "bus",
+"50m", "125m", "150m",
+"250m", "270m";
+   };
+
wdt: wdt@100 {
compatible = "mtk,mt7621-wdt";
reg = <0x100 0x100>;
@@ -101,8 +91,8 @@ i2c: i2c@900 {
compatible = "mediatek,mt7621-i2c";
reg = <0x900 0x100>;
 
-   clocks = <>;
-
+   clocks = < MT7621_CLK_I2C>;
+   clock-names = "i2c";
resets = < 16>;
reset-names = "i2c";
 
@@ -119,8 +109,8 @@ i2s: i2s@a00 {
compatible = "mediatek,mt7621-i2s";
reg = <0xa00 0x100>;
 
-   clocks = <>;
-
+   clocks = < MT7621_CLK_I2S>;
+   clock-names = "i2s";
resets = < 17>;
reset-names = "i2s";
 
@@ -138,7 +128,7 @@ i2s: i2s@a00 {
};
 
memc: memc@5000 {
-   compatible = "mtk,mt7621-memc";
+   compatible = "mtk,mt7621-memc", "syscon";
reg = <0x5000 0x1000>;
};
 
@@ -156,8 +146,8 @@ uartlite: uartlite@c00 {
compatible = "ns16550a";
reg = <0xc00 0x100>;
 
-   clocks = <>;
-   clock-frequency = <5000>;
+   clocks = < MT7621_CLK_UART1>;
+   clock-names = "uart1";
 
interrupt-parent = <>;

[PATCH v8 5/6] staging: mt7621-dts: use valid vendor 'mediatek' instead of invalid 'mtk'

Vendor listed for mediatek in kernel vendor file 'vendor-prefixes.yaml'
contains 'mediatek' as a valid vendor string. Some nodes in the device
tree are using an invalid vendor string vfor 'mtk' instead. Fix all of
them in dts file. Update also ralink mt7621 related code to properly
match new strings. Even there are used in the device tree there are
some strings that are not referred anywhere but have been also updated
with new vendor name. These are 'mtk,mt7621-wdt', 'mtk,mt7621-nand',
'mtk,mt7621-mc', and 'mtk,mt7621-cpc'.

Acked-by: Greg Kroah-Hartman 
Signed-off-by: Sergio Paracuellos 
---
 arch/mips/ralink/mt7621.c  |  6 +++---
 drivers/staging/mt7621-dts/mt7621.dtsi | 12 ++--
 2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/arch/mips/ralink/mt7621.c b/arch/mips/ralink/mt7621.c
index ca0ac607b0f3..5d74fc1c96ac 100644
--- a/arch/mips/ralink/mt7621.c
+++ b/arch/mips/ralink/mt7621.c
@@ -112,8 +112,8 @@ phys_addr_t mips_cpc_default_phys_base(void)
 
 void __init ralink_of_remap(void)
 {
-   rt_sysc_membase = plat_of_remap_node("mtk,mt7621-sysc");
-   rt_memc_membase = plat_of_remap_node("mtk,mt7621-memc");
+   rt_sysc_membase = plat_of_remap_node("mediatek,mt7621-sysc");
+   rt_memc_membase = plat_of_remap_node("mediatek,mt7621-memc");
 
if (!rt_sysc_membase || !rt_memc_membase)
panic("Failed to remap core resources");
@@ -181,7 +181,7 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
 
if (n0 == MT7621_CHIP_NAME0 && n1 == MT7621_CHIP_NAME1) {
name = "MT7621";
-   soc_info->compatible = "mtk,mt7621-soc";
+   soc_info->compatible = "mediatek,mt7621-soc";
} else {
panic("mt7621: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
}
diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi 
b/drivers/staging/mt7621-dts/mt7621.dtsi
index 11d1670d4339..55784dd48dc5 100644
--- a/drivers/staging/mt7621-dts/mt7621.dtsi
+++ b/drivers/staging/mt7621-dts/mt7621.dtsi
@@ -56,7 +56,7 @@ palmbus: palmbus@1E00 {
#size-cells = <1>;
 
sysc: sysc@0 {
-   compatible = "mtk,mt7621-sysc", "syscon";
+   compatible = "mediatek,mt7621-sysc", "syscon";
reg = <0x0 0x100>;
};
 
@@ -71,7 +71,7 @@ pll: pll {
};
 
wdt: wdt@100 {
-   compatible = "mtk,mt7621-wdt";
+   compatible = "mediatek,mt7621-wdt";
reg = <0x100 0x100>;
};
 
@@ -128,17 +128,17 @@ i2s: i2s@a00 {
};
 
memc: memc@5000 {
-   compatible = "mtk,mt7621-memc", "syscon";
+   compatible = "mediatek,mt7621-memc", "syscon";
reg = <0x5000 0x1000>;
};
 
cpc: cpc@1fbf {
-compatible = "mtk,mt7621-cpc";
+compatible = "mediatek,mt7621-cpc";
 reg = <0x1fbf 0x8000>;
};
 
mc: mc@1fbf8000 {
-   compatible = "mtk,mt7621-mc";
+   compatible = "mediatek,mt7621-mc";
reg = <0x1fbf8000 0x8000>;
};
 
@@ -366,7 +366,7 @@ timer {
nand: nand@1e003000 {
status = "disabled";
 
-   compatible = "mtk,mt7621-nand";
+   compatible = "mediatek,mt7621-nand";
bank-width = <2>;
reg = <0x1e003000 0x800
0x1e003800 0x800>;
-- 
2.25.1

[PATCH v8 0/6] MIPS: ralink: add CPU clock detection and clock driver for MT7621

   related clocks to make things work.
 - Add Greg's Acked-by in patches 4 and 5.
 - Rebase this series on the top of linux-next tag 'next-20210215'.

v5 RESEND notes:
 - I am resending this as I was told to do that.
 - Please, take into account Rob's comments to DT node patch and my
   reply with explanation about how are the current device tree nodes
   for this architecture being used in [2].

Changes in v5:
 - Avoid the use of syscon. All drivers of this platform are just using
   platform operations defined in 'asm/mach-ralink/ralink_regs.h'. We also
   need them for some PLL registers that are not in the sys control area.
   Hence, since we must use this dependency avoid to define clock driver
   as a child of the sysc node in the device tree and follow current
   platform code style.
 - Update bindings documentation to don't refer the syscon and make
   remove 'clock-output-names' property from required ones.
 - Use 'asm/mach-ralink/ralink_regs.h' platform read and write operations
   instead of regmap from the syscon node.
 - Remove 'mt7621_clk_provider' and directly declare 'clk_hw_onecell_data'
   pointer in 'mt7621_clk_init' and pass from there into different register
   functions. Remove pointers to 'mt7621_clk_provider' in the rest fo structs
   used in this driver.
 - Remove MHZ macro and just pass values directly in hertzs.
 - Avoid 'CLK_IGNORE_UNUSED' flag for gates and add a new function called
   'mt7621_prepare_enable_clocks' to prepare all of them to make clocks
   referenced and don't affect current driver code.
 - Remove COMPILE_TEST from Kconfig because of the use of especific arch
   stuff.
 - Fix commit message where a typo for "frequencies" word was present.
 - Make use of parent_clk_data in 'CLK_BASE' macro.
 - Remove MODULE_* macros from code since this is not a module.
 - Remove not needed includes.
 - Hardcode "xtal" as parent in FIXED macro.
 - Change 'else if' clause into 'if' clause since a return statement was
   being used in 'mt7621_xtal_recalc_rate'.

 NOTES:
   - Driver is still being declared using 'CLK_OF_DECLARE' for all the  
 clocks. I have explored the possibility to make some of them available
 afterwards using 'CLK_OF_DECLARE_DRIVER' for top clocks and the rest
 using a platform driver. The resulting code was uglier since we only want
 to use the same device tree node and the top clocks must be copied again
 for the new platform register stuff to properly have a good hierarchy.
 New globals needs to be introduced and in this particular case I don't
 really see the benefits of doing in this way. I am totally ok to have all
 the clocks registered at early stage since from other drivers perspective
 we only really need to enable gates. So, I prefer to have them in that
 way if it is not a real problem, of course.

Changes in v4:
 - Add Acked-by from Rob Herring for binding headers (PATCH 1/6).
 - Convert bindings to not use syscon phandle and declare clock as
   a child of the syscon node. Update device tree and binding doc
   accordly.
 - Make use of 'syscon_node_to_regmap' in driver code instead of
   get this using the phandle function.
 - Properly unregister clocks for the error path of the function
   'mt7621_clk_init'.
 - Include ARRAY_SIZE of fixed clocks in the 'count' to kzalloc
   of 'clk_data'.
 - Add new patch changing invalid vendor 'mtk' in favour of 'mediatek'
   which is the one listed in 'vendor-prefixes.yaml'. Update mt7621 code
   accordly. I have added this patch inside this series because clk
   binding is referring syscon node and the string for that node was
   with not listed vendor. Hence update and have all of this correct
   in the same series.

Changes in v3:
 - Fix compilation warnings reported by kernel test robot because of
   ignoring return values of 'of_clk_hw_register' in functions
   'mt7621_register_top_clocks' and 'mt7621_gate_ops_init'.
 - Fix dts file and binding documentation 'clock-output-names'.

Changes in v2:
 - Remove the following patches:
   * dt: bindings: add mt7621-pll device tree binding documentation.
   * MIPS: ralink: add clock device providing cpu/ahb/apb clock for mt7621.
 - Move all relevant clock code to 'drivers/clk/ralink/clk-mt7621.c' and
   unify there previous 'mt7621-pll' and 'mt7621-clk' into a unique driver
   and binding 'mt7621-clk'.
 - Driver is not a platform driver anymore and now make use of 'CLK_OF_DECLARE'
   because we need clocks available in 'plat_time_init' before setting up
   the timer for the GIC.
 - Use new fixed clocks as parents for different gates and deriving from 'xtal'
   using frequencies in[1].
 - Adapt dts file and bindings header and documentation for new changes.
 - Change MAINTAINERS file to only contains clk-mt7621.c code and
   mediatek,mt7621-clk.yaml file.

[0]: https://www.lkml.org/lkml/2019/7/23/1044
[1]: 
https://github.com/981213/linux/commit/2eca1f045e4c3db18c941135464c0d7422ad8133
[2]: https://lkml.o

[PATCH v8 3/6] clk: ralink: add clock driver for mt7621 SoC

The documentation for this SOC only talks about two
registers regarding to the clocks:
* SYSC_REG_CPLL_CLKCFG0 - provides some information about
boostrapped refclock. PLL and dividers used for CPU and some
sort of BUS.
* SYSC_REG_CPLL_CLKCFG1 - a banch of gates to enable/disable
clocks for all or some ip cores.

Looking into driver code, and some openWRT patched there are
another frequencies which are used in some drivers (uart, sd...).
According to all of this information the clock plan for this
SoC is set as follows:
- Main top clock "xtal" from where all the rest of the world is
derived.
- CPU clock "cpu" derived from "xtal" frequencies and a bunch of
register reads and predividers.
- BUS clock "bus" derived from "cpu" and with (cpu / 4) MHz.
- Fixed clocks from "xtal":
* "50m": 50 MHz.
* "125m": 125 MHz.
* "150m": 150 MHz.
* "250m": 250 MHz.
* "270m": 270 MHz.

We also have a buch of gate clocks with their parents:
  * "hsdma": "150m"
  * "fe": "250m"
  * "sp_divtx": "270m"
  * "timer": "50m"
  * "pcm": "270m"
  * "pio": "50m"
  * "gdma": "bus"
  * "nand": "125m"
  * "i2c": "50m"
  * "i2s": "270m"
  * "spi": "bus"
  * "uart1": "50m"
  * "uart2": "50m"
  * "uart3": "50m"
  * "eth": "50m"
  * "pcie0": "125m"
  * "pcie1": "125m"
  * "pcie2": "125m"
  * "crypto": "250m"
  * "shxc": "50m"

With this information the clk driver will provide clock and gates
functionality from a a set of hardcoded clocks allowing to define
a nice device tree without fixed clocks.

Signed-off-by: Sergio Paracuellos 
---
 drivers/clk/Kconfig |   1 +
 drivers/clk/Makefile|   1 +
 drivers/clk/ralink/Kconfig  |  14 +
 drivers/clk/ralink/Makefile |   2 +
 drivers/clk/ralink/clk-mt7621.c | 534 
 5 files changed, 552 insertions(+)
 create mode 100644 drivers/clk/ralink/Kconfig
 create mode 100644 drivers/clk/ralink/Makefile
 create mode 100644 drivers/clk/ralink/clk-mt7621.c

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 7c5dc348c16f..70b23da997bf 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -382,6 +382,7 @@ source "drivers/clk/mediatek/Kconfig"
 source "drivers/clk/meson/Kconfig"
 source "drivers/clk/mvebu/Kconfig"
 source "drivers/clk/qcom/Kconfig"
+source "drivers/clk/ralink/Kconfig"
 source "drivers/clk/renesas/Kconfig"
 source "drivers/clk/rockchip/Kconfig"
 source "drivers/clk/samsung/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 5325847469e9..1b35ad852721 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -98,6 +98,7 @@ obj-$(CONFIG_COMMON_CLK_NXP)  += nxp/
 obj-$(CONFIG_MACH_PISTACHIO)   += pistachio/
 obj-$(CONFIG_COMMON_CLK_PXA)   += pxa/
 obj-$(CONFIG_COMMON_CLK_QCOM)  += qcom/
+obj-y  += ralink/
 obj-y  += renesas/
 obj-$(CONFIG_ARCH_ROCKCHIP)+= rockchip/
 obj-$(CONFIG_COMMON_CLK_SAMSUNG)   += samsung/
diff --git a/drivers/clk/ralink/Kconfig b/drivers/clk/ralink/Kconfig
new file mode 100644
index ..9f39c282fdc5
--- /dev/null
+++ b/drivers/clk/ralink/Kconfig
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# MediaTek Mt7621 Clock Driver
+#
+menu "Clock driver for Mediatek mt7621 SoC"
+   depends on SOC_MT7621 || COMPILE_TEST
+
+config CLK_MT7621
+   bool "Clock driver for MediaTek MT7621"
+   depends on SOC_MT7621 || COMPILE_TEST
+   default SOC_MT7621
+   help
+ This driver supports MediaTek MT7621 basic clocks.
+endmenu
diff --git a/drivers/clk/ralink/Makefile b/drivers/clk/ralink/Makefile
new file mode 100644
index ..cf6f9216379d
--- /dev/null
+++ b/drivers/clk/ralink/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_CLK_MT7621) += clk-mt7621.o
diff --git a/drivers/clk/ralink/clk-mt7621.c b/drivers/clk/ralink/clk-mt7621.c
new file mode 100644
index ..1ac169e1fe3a
--- /dev/null
+++ b/drivers/clk/ralink/clk-mt7621.c
@@ -0,0 +1,534 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Mediatek MT7621 Clock Driver
+ * Author: Sergio Paracuellos 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* Configuration registers */
+#define SYSC_REG_SYSTEM_CONFIG0 0x10
+#define SYSC_REG_SYSTEM_CONFIG1 0x14

[PATCH v8 2/6] dt: bindings: add mt7621-clk device tree binding documentation

Adds device tree binding documentation for clocks in the
MT7621 SOC.

Signed-off-by: Sergio Paracuellos 
---
 .../bindings/clock/mediatek,mt7621-clk.yaml   | 66 +++
 1 file changed, 66 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml

diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml 
b/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
new file mode 100644
index ..842a0f2c9d40
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
@@ -0,0 +1,66 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/mediatek,mt7621-clk.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MT7621 Clock Device Tree Bindings
+
+maintainers:
+  - Sergio Paracuellos 
+
+description: |
+  The MT7621 has a PLL controller from where the cpu clock is provided
+  as well as derived clocks for the bus and the peripherals. It also
+  can gate SoC device clocks.
+
+  Each clock is assigned an identifier and client nodes use this identifier
+  to specify the clock which they consume.
+
+  All these identifiers could be found in:
+  [1]: .
+
+properties:
+  compatible:
+const: mediatek,mt7621-clk
+
+  "#clock-cells":
+description:
+  The first cell indicates the clock number, see [1] for available
+  clocks.
+const: 1
+
+  ralink,sysctl:
+$ref: /schemas/types.yaml#/definitions/phandle
+description:
+  phandle of syscon used to control system registers
+
+  ralink,memctl:
+$ref: /schemas/types.yaml#/definitions/phandle
+description:
+  phandle of syscon used to control memory registers
+
+  clock-output-names:
+maxItems: 8
+
+required:
+  - compatible
+  - '#clock-cells'
+  - ralink,sysctl
+  - ralink,memctl
+
+additionalProperties: false
+
+examples:
+  - |
+#include 
+
+pll {
+  compatible = "mediatek,mt7621-clk";
+  #clock-cells = <1>;
+  ralink,sysctl = <>;
+  ralink,memctl = <>;
+  clock-output-names = "xtal", "cpu", "bus",
+   "50m", "125m", "150m",
+   "250m", "270m";
+};
-- 
2.25.1

[PATCH v8 1/6] dt-bindings: clock: add dt binding header for mt7621 clocks

Adds dt binding header for 'mediatek,mt7621-clk' clocks.

Acked-by: Rob Herring 
Signed-off-by: Sergio Paracuellos 
---
 include/dt-bindings/clock/mt7621-clk.h | 41 ++
 1 file changed, 41 insertions(+)
 create mode 100644 include/dt-bindings/clock/mt7621-clk.h

diff --git a/include/dt-bindings/clock/mt7621-clk.h 
b/include/dt-bindings/clock/mt7621-clk.h
new file mode 100644
index ..1422badcf9de
--- /dev/null
+++ b/include/dt-bindings/clock/mt7621-clk.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Author: Sergio Paracuellos 
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT7621_H
+#define _DT_BINDINGS_CLK_MT7621_H
+
+#define MT7621_CLK_XTAL0
+#define MT7621_CLK_CPU 1
+#define MT7621_CLK_BUS 2
+#define MT7621_CLK_50M 3
+#define MT7621_CLK_125M4
+#define MT7621_CLK_150M5
+#define MT7621_CLK_250M6
+#define MT7621_CLK_270M7
+
+#define MT7621_CLK_HSDMA   8
+#define MT7621_CLK_FE  9
+#define MT7621_CLK_SP_DIVTX10
+#define MT7621_CLK_TIMER   11
+#define MT7621_CLK_PCM 12
+#define MT7621_CLK_PIO 13
+#define MT7621_CLK_GDMA14
+#define MT7621_CLK_NAND15
+#define MT7621_CLK_I2C 16
+#define MT7621_CLK_I2S 17
+#define MT7621_CLK_SPI 18
+#define MT7621_CLK_UART1   19
+#define MT7621_CLK_UART2   20
+#define MT7621_CLK_UART3   21
+#define MT7621_CLK_ETH 22
+#define MT7621_CLK_PCIE0   23
+#define MT7621_CLK_PCIE1   24
+#define MT7621_CLK_PCIE2   25
+#define MT7621_CLK_CRYPTO  26
+#define MT7621_CLK_SHXC27
+
+#define MT7621_CLK_MAX 28
+
+#endif /* _DT_BINDINGS_CLK_MT7621_H */
-- 
2.25.1

[PATCH v7 4/6] staging: mt7621-dts: make use of new 'mt7621-clk'

Clocks for SoC mt7621 have been properly integrated so there is
no need to declare fixed clocks at all in the device tree. Remove
all of them, add new device tree nodes for mt7621-clk and update
the rest of the nodes to use them.

Acked-by: Greg Kroah-Hartman 
Signed-off-by: Sergio Paracuellos 
---
 drivers/staging/mt7621-dts/gbpc1.dts   | 11 
 drivers/staging/mt7621-dts/mt7621.dtsi | 79 +-
 2 files changed, 38 insertions(+), 52 deletions(-)

diff --git a/drivers/staging/mt7621-dts/gbpc1.dts 
b/drivers/staging/mt7621-dts/gbpc1.dts
index a7c0d3115d72..7716d0efe524 100644
--- a/drivers/staging/mt7621-dts/gbpc1.dts
+++ b/drivers/staging/mt7621-dts/gbpc1.dts
@@ -100,17 +100,6 @@ partition@5 {
};
 };
 
- {
-   compatible = "fixed-clock";
-   /* This is normally 1/4 of cpuclock */
-   clock-frequency = <22500>;
-};
-
- {
-   compatible = "fixed-clock";
-   clock-frequency = <9>;
-};
-
  {
pinctrl-names = "default";
pinctrl-0 = <_pins>;
diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi 
b/drivers/staging/mt7621-dts/mt7621.dtsi
index 16fc94f65486..11d1670d4339 100644
--- a/drivers/staging/mt7621-dts/mt7621.dtsi
+++ b/drivers/staging/mt7621-dts/mt7621.dtsi
@@ -1,5 +1,6 @@
 #include 
 #include 
+#include 
 
 / {
#address-cells = <1>;
@@ -27,27 +28,6 @@ aliases {
serial0 = 
};
 
-   cpuclock: cpuclock@0 {
-   #clock-cells = <0>;
-   compatible = "fixed-clock";
-
-   /* FIXME: there should be way to detect this */
-   clock-frequency = <88000>;
-   };
-
-   sysclock: sysclock@0 {
-   #clock-cells = <0>;
-   compatible = "fixed-clock";
-
-   /* This is normally 1/4 of cpuclock */
-   clock-frequency = <22000>;
-   };
-
-   mmc_clock: mmc_clock@0 {
-   #clock-cells = <0>;
-   compatible = "fixed-clock";
-   clock-frequency = <4800>;
-   };
 
mmc_fixed_3v3: fixedregulator@0 {
compatible = "regulator-fixed";
@@ -76,10 +56,20 @@ palmbus: palmbus@1E00 {
#size-cells = <1>;
 
sysc: sysc@0 {
-   compatible = "mtk,mt7621-sysc";
+   compatible = "mtk,mt7621-sysc", "syscon";
reg = <0x0 0x100>;
};
 
+   pll: pll {
+   compatible = "mediatek,mt7621-clk";
+   #clock-cells = <1>;
+   ralink,sysctl = <>;
+   ralink,memctl = <>;
+   clock-output-names = "xtal", "cpu", "bus",
+"50m", "125m", "150m",
+"250m", "270m";
+   };
+
wdt: wdt@100 {
compatible = "mtk,mt7621-wdt";
reg = <0x100 0x100>;
@@ -101,8 +91,8 @@ i2c: i2c@900 {
compatible = "mediatek,mt7621-i2c";
reg = <0x900 0x100>;
 
-   clocks = <>;
-
+   clocks = < MT7621_CLK_I2C>;
+   clock-names = "i2c";
resets = < 16>;
reset-names = "i2c";
 
@@ -119,8 +109,8 @@ i2s: i2s@a00 {
compatible = "mediatek,mt7621-i2s";
reg = <0xa00 0x100>;
 
-   clocks = <>;
-
+   clocks = < MT7621_CLK_I2S>;
+   clock-names = "i2s";
resets = < 17>;
reset-names = "i2s";
 
@@ -138,7 +128,7 @@ i2s: i2s@a00 {
};
 
memc: memc@5000 {
-   compatible = "mtk,mt7621-memc";
+   compatible = "mtk,mt7621-memc", "syscon";
reg = <0x5000 0x1000>;
};
 
@@ -156,8 +146,8 @@ uartlite: uartlite@c00 {
compatible = "ns16550a";
reg = <0xc00 0x100>;
 
-   clocks = <>;
-   clock-frequency = <5000>;
+   clocks = < MT7621_CLK_UART1>;
+   clock-names = "uart1";
 
interrupt-parent = <>;

[PATCH v7 6/6] MAINTAINERS: add MT7621 CLOCK maintainer

Adding myself as maintainer for mt7621 clock driver.

Signed-off-by: Sergio Paracuellos 
---
 MAINTAINERS | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 809a68af5efd..be5ada6b4309 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11288,6 +11288,12 @@ L: linux-wirel...@vger.kernel.org
 S: Maintained
 F: drivers/net/wireless/mediatek/mt7601u/
 
+MEDIATEK MT7621 CLOCK DRIVER
+M: Sergio Paracuellos 
+S: Maintained
+F: Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
+F: drivers/clk/ralink/clk-mt7621.c
+
 MEDIATEK MT7621/28/88 I2C DRIVER
 M: Stefan Roese 
 L: linux-...@vger.kernel.org
-- 
2.25.1

[PATCH v7 5/6] staging: mt7621-dts: use valid vendor 'mediatek' instead of invalid 'mtk'

Vendor listed for mediatek in kernel vendor file 'vendor-prefixes.yaml'
contains 'mediatek' as a valid vendor string. Some nodes in the device
tree are using an invalid vendor string vfor 'mtk' instead. Fix all of
them in dts file. Update also ralink mt7621 related code to properly
match new strings. Even there are used in the device tree there are
some strings that are not referred anywhere but have been also updated
with new vendor name. These are 'mtk,mt7621-wdt', 'mtk,mt7621-nand',
'mtk,mt7621-mc', and 'mtk,mt7621-cpc'.

Acked-by: Greg Kroah-Hartman 
Signed-off-by: Sergio Paracuellos 
---
 arch/mips/ralink/mt7621.c  |  6 +++---
 drivers/staging/mt7621-dts/mt7621.dtsi | 12 ++--
 2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/arch/mips/ralink/mt7621.c b/arch/mips/ralink/mt7621.c
index ca0ac607b0f3..5d74fc1c96ac 100644
--- a/arch/mips/ralink/mt7621.c
+++ b/arch/mips/ralink/mt7621.c
@@ -112,8 +112,8 @@ phys_addr_t mips_cpc_default_phys_base(void)
 
 void __init ralink_of_remap(void)
 {
-   rt_sysc_membase = plat_of_remap_node("mtk,mt7621-sysc");
-   rt_memc_membase = plat_of_remap_node("mtk,mt7621-memc");
+   rt_sysc_membase = plat_of_remap_node("mediatek,mt7621-sysc");
+   rt_memc_membase = plat_of_remap_node("mediatek,mt7621-memc");
 
if (!rt_sysc_membase || !rt_memc_membase)
panic("Failed to remap core resources");
@@ -181,7 +181,7 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
 
if (n0 == MT7621_CHIP_NAME0 && n1 == MT7621_CHIP_NAME1) {
name = "MT7621";
-   soc_info->compatible = "mtk,mt7621-soc";
+   soc_info->compatible = "mediatek,mt7621-soc";
} else {
panic("mt7621: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
}
diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi 
b/drivers/staging/mt7621-dts/mt7621.dtsi
index 11d1670d4339..55784dd48dc5 100644
--- a/drivers/staging/mt7621-dts/mt7621.dtsi
+++ b/drivers/staging/mt7621-dts/mt7621.dtsi
@@ -56,7 +56,7 @@ palmbus: palmbus@1E00 {
#size-cells = <1>;
 
sysc: sysc@0 {
-   compatible = "mtk,mt7621-sysc", "syscon";
+   compatible = "mediatek,mt7621-sysc", "syscon";
reg = <0x0 0x100>;
};
 
@@ -71,7 +71,7 @@ pll: pll {
};
 
wdt: wdt@100 {
-   compatible = "mtk,mt7621-wdt";
+   compatible = "mediatek,mt7621-wdt";
reg = <0x100 0x100>;
};
 
@@ -128,17 +128,17 @@ i2s: i2s@a00 {
};
 
memc: memc@5000 {
-   compatible = "mtk,mt7621-memc", "syscon";
+   compatible = "mediatek,mt7621-memc", "syscon";
reg = <0x5000 0x1000>;
};
 
cpc: cpc@1fbf {
-compatible = "mtk,mt7621-cpc";
+compatible = "mediatek,mt7621-cpc";
 reg = <0x1fbf 0x8000>;
};
 
mc: mc@1fbf8000 {
-   compatible = "mtk,mt7621-mc";
+   compatible = "mediatek,mt7621-mc";
reg = <0x1fbf8000 0x8000>;
};
 
@@ -366,7 +366,7 @@ timer {
nand: nand@1e003000 {
status = "disabled";
 
-   compatible = "mtk,mt7621-nand";
+   compatible = "mediatek,mt7621-nand";
bank-width = <2>;
reg = <0x1e003000 0x800
0x1e003800 0x800>;
-- 
2.25.1

[PATCH v7 3/6] clk: ralink: add clock driver for mt7621 SoC

The documentation for this SOC only talks about two
registers regarding to the clocks:
* SYSC_REG_CPLL_CLKCFG0 - provides some information about
boostrapped refclock. PLL and dividers used for CPU and some
sort of BUS.
* SYSC_REG_CPLL_CLKCFG1 - a banch of gates to enable/disable
clocks for all or some ip cores.

Looking into driver code, and some openWRT patched there are
another frequencies which are used in some drivers (uart, sd...).
According to all of this information the clock plan for this
SoC is set as follows:
- Main top clock "xtal" from where all the rest of the world is
derived.
- CPU clock "cpu" derived from "xtal" frequencies and a bunch of
register reads and predividers.
- BUS clock "bus" derived from "cpu" and with (cpu / 4) MHz.
- Fixed clocks from "xtal":
* "50m": 50 MHz.
* "125m": 125 MHz.
* "150m": 150 MHz.
* "250m": 250 MHz.
* "270m": 270 MHz.

We also have a buch of gate clocks with their parents:
  * "hsdma": "150m"
  * "fe": "250m"
  * "sp_divtx": "270m"
  * "timer": "50m"
  * "pcm": "270m"
  * "pio": "50m"
  * "gdma": "bus"
  * "nand": "125m"
  * "i2c": "50m"
  * "i2s": "270m"
  * "spi": "bus"
  * "uart1": "50m"
  * "uart2": "50m"
  * "uart3": "50m"
  * "eth": "50m"
  * "pcie0": "125m"
  * "pcie1": "125m"
  * "pcie2": "125m"
  * "crypto": "250m"
  * "shxc": "50m"

With this information the clk driver will provide clock and gates
functionality from a a set of hardcoded clocks allowing to define
a nice device tree without fixed clocks.

Signed-off-by: Sergio Paracuellos 
---
 drivers/clk/Kconfig |   1 +
 drivers/clk/Makefile|   1 +
 drivers/clk/ralink/Kconfig  |  14 +
 drivers/clk/ralink/Makefile |   2 +
 drivers/clk/ralink/clk-mt7621.c | 532 
 5 files changed, 550 insertions(+)
 create mode 100644 drivers/clk/ralink/Kconfig
 create mode 100644 drivers/clk/ralink/Makefile
 create mode 100644 drivers/clk/ralink/clk-mt7621.c

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 7c5dc348c16f..70b23da997bf 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -382,6 +382,7 @@ source "drivers/clk/mediatek/Kconfig"
 source "drivers/clk/meson/Kconfig"
 source "drivers/clk/mvebu/Kconfig"
 source "drivers/clk/qcom/Kconfig"
+source "drivers/clk/ralink/Kconfig"
 source "drivers/clk/renesas/Kconfig"
 source "drivers/clk/rockchip/Kconfig"
 source "drivers/clk/samsung/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 5325847469e9..1b35ad852721 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -98,6 +98,7 @@ obj-$(CONFIG_COMMON_CLK_NXP)  += nxp/
 obj-$(CONFIG_MACH_PISTACHIO)   += pistachio/
 obj-$(CONFIG_COMMON_CLK_PXA)   += pxa/
 obj-$(CONFIG_COMMON_CLK_QCOM)  += qcom/
+obj-y  += ralink/
 obj-y  += renesas/
 obj-$(CONFIG_ARCH_ROCKCHIP)+= rockchip/
 obj-$(CONFIG_COMMON_CLK_SAMSUNG)   += samsung/
diff --git a/drivers/clk/ralink/Kconfig b/drivers/clk/ralink/Kconfig
new file mode 100644
index ..9f39c282fdc5
--- /dev/null
+++ b/drivers/clk/ralink/Kconfig
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# MediaTek Mt7621 Clock Driver
+#
+menu "Clock driver for Mediatek mt7621 SoC"
+   depends on SOC_MT7621 || COMPILE_TEST
+
+config CLK_MT7621
+   bool "Clock driver for MediaTek MT7621"
+   depends on SOC_MT7621 || COMPILE_TEST
+   default SOC_MT7621
+   help
+ This driver supports MediaTek MT7621 basic clocks.
+endmenu
diff --git a/drivers/clk/ralink/Makefile b/drivers/clk/ralink/Makefile
new file mode 100644
index ..cf6f9216379d
--- /dev/null
+++ b/drivers/clk/ralink/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_CLK_MT7621) += clk-mt7621.o
diff --git a/drivers/clk/ralink/clk-mt7621.c b/drivers/clk/ralink/clk-mt7621.c
new file mode 100644
index ..55b415e74cd1
--- /dev/null
+++ b/drivers/clk/ralink/clk-mt7621.c
@@ -0,0 +1,532 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Mediatek MT7621 Clock Driver
+ * Author: Sergio Paracuellos 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* Configuration registers */
+#define SYSC_REG_SYSTEM_CONFIG0 0x10
+#define SYSC_REG_SYSTEM_CONFIG1 0x14

[PATCH v7 2/6] dt: bindings: add mt7621-clk device tree binding documentation

Adds device tree binding documentation for clocks in the
MT7621 SOC.

Signed-off-by: Sergio Paracuellos 
---
 .../bindings/clock/mediatek,mt7621-clk.yaml   | 66 +++
 1 file changed, 66 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml

diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml 
b/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
new file mode 100644
index ..842a0f2c9d40
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
@@ -0,0 +1,66 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/mediatek,mt7621-clk.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MT7621 Clock Device Tree Bindings
+
+maintainers:
+  - Sergio Paracuellos 
+
+description: |
+  The MT7621 has a PLL controller from where the cpu clock is provided
+  as well as derived clocks for the bus and the peripherals. It also
+  can gate SoC device clocks.
+
+  Each clock is assigned an identifier and client nodes use this identifier
+  to specify the clock which they consume.
+
+  All these identifiers could be found in:
+  [1]: .
+
+properties:
+  compatible:
+const: mediatek,mt7621-clk
+
+  "#clock-cells":
+description:
+  The first cell indicates the clock number, see [1] for available
+  clocks.
+const: 1
+
+  ralink,sysctl:
+$ref: /schemas/types.yaml#/definitions/phandle
+description:
+  phandle of syscon used to control system registers
+
+  ralink,memctl:
+$ref: /schemas/types.yaml#/definitions/phandle
+description:
+  phandle of syscon used to control memory registers
+
+  clock-output-names:
+maxItems: 8
+
+required:
+  - compatible
+  - '#clock-cells'
+  - ralink,sysctl
+  - ralink,memctl
+
+additionalProperties: false
+
+examples:
+  - |
+#include 
+
+pll {
+  compatible = "mediatek,mt7621-clk";
+  #clock-cells = <1>;
+  ralink,sysctl = <>;
+  ralink,memctl = <>;
+  clock-output-names = "xtal", "cpu", "bus",
+   "50m", "125m", "150m",
+   "250m", "270m";
+};
-- 
2.25.1

[PATCH v7 0/6] MIPS: ralink: add CPU clock detection and clock driver for MT7621

base this series on the top of linux-next tag 'next-20210215'.

v5 RESEND notes:
 - I am resending this as I was told to do that.
 - Please, take into account Rob's comments to DT node patch and my
   reply with explanation about how are the current device tree nodes
   for this architecture being used in [2].

Changes in v5:
 - Avoid the use of syscon. All drivers of this platform are just using
   platform operations defined in 'asm/mach-ralink/ralink_regs.h'. We also
   need them for some PLL registers that are not in the sys control area.
   Hence, since we must use this dependency avoid to define clock driver
   as a child of the sysc node in the device tree and follow current
   platform code style.
 - Update bindings documentation to don't refer the syscon and make
   remove 'clock-output-names' property from required ones.
 - Use 'asm/mach-ralink/ralink_regs.h' platform read and write operations
   instead of regmap from the syscon node.
 - Remove 'mt7621_clk_provider' and directly declare 'clk_hw_onecell_data'
   pointer in 'mt7621_clk_init' and pass from there into different register
   functions. Remove pointers to 'mt7621_clk_provider' in the rest fo structs
   used in this driver.
 - Remove MHZ macro and just pass values directly in hertzs.
 - Avoid 'CLK_IGNORE_UNUSED' flag for gates and add a new function called
   'mt7621_prepare_enable_clocks' to prepare all of them to make clocks
   referenced and don't affect current driver code.
 - Remove COMPILE_TEST from Kconfig because of the use of especific arch
   stuff.
 - Fix commit message where a typo for "frequencies" word was present.
 - Make use of parent_clk_data in 'CLK_BASE' macro.
 - Remove MODULE_* macros from code since this is not a module.
 - Remove not needed includes.
 - Hardcode "xtal" as parent in FIXED macro.
 - Change 'else if' clause into 'if' clause since a return statement was
   being used in 'mt7621_xtal_recalc_rate'.

 NOTES:
   - Driver is still being declared using 'CLK_OF_DECLARE' for all the  
 clocks. I have explored the possibility to make some of them available
 afterwards using 'CLK_OF_DECLARE_DRIVER' for top clocks and the rest
 using a platform driver. The resulting code was uglier since we only want
 to use the same device tree node and the top clocks must be copied again
 for the new platform register stuff to properly have a good hierarchy.
 New globals needs to be introduced and in this particular case I don't
 really see the benefits of doing in this way. I am totally ok to have all
 the clocks registered at early stage since from other drivers perspective
 we only really need to enable gates. So, I prefer to have them in that
 way if it is not a real problem, of course.

Changes in v4:
 - Add Acked-by from Rob Herring for binding headers (PATCH 1/6).
 - Convert bindings to not use syscon phandle and declare clock as
   a child of the syscon node. Update device tree and binding doc
   accordly.
 - Make use of 'syscon_node_to_regmap' in driver code instead of
   get this using the phandle function.
 - Properly unregister clocks for the error path of the function
   'mt7621_clk_init'.
 - Include ARRAY_SIZE of fixed clocks in the 'count' to kzalloc
   of 'clk_data'.
 - Add new patch changing invalid vendor 'mtk' in favour of 'mediatek'
   which is the one listed in 'vendor-prefixes.yaml'. Update mt7621 code
   accordly. I have added this patch inside this series because clk
   binding is referring syscon node and the string for that node was
   with not listed vendor. Hence update and have all of this correct
   in the same series.

Changes in v3:
 - Fix compilation warnings reported by kernel test robot because of
   ignoring return values of 'of_clk_hw_register' in functions
   'mt7621_register_top_clocks' and 'mt7621_gate_ops_init'.
 - Fix dts file and binding documentation 'clock-output-names'.

Changes in v2:
 - Remove the following patches:
   * dt: bindings: add mt7621-pll device tree binding documentation.
   * MIPS: ralink: add clock device providing cpu/ahb/apb clock for mt7621.
 - Move all relevant clock code to 'drivers/clk/ralink/clk-mt7621.c' and
   unify there previous 'mt7621-pll' and 'mt7621-clk' into a unique driver
   and binding 'mt7621-clk'.
 - Driver is not a platform driver anymore and now make use of 'CLK_OF_DECLARE'
   because we need clocks available in 'plat_time_init' before setting up
   the timer for the GIC.
 - Use new fixed clocks as parents for different gates and deriving from 'xtal'
   using frequencies in[1].
 - Adapt dts file and bindings header and documentation for new changes.
 - Change MAINTAINERS file to only contains clk-mt7621.c code and
   mediatek,mt7621-clk.yaml file.

[0]: https://www.lkml.org/lkml/2019/7/23/1044
[1]: 
https://github.com/981213/linux/commit/2eca1f045e4c3db18c941135464c0d7422ad8133
[2]: https://lkml.org/lkml/2020/12/20/47

Sergio Paracuellos (6):
  dt-bindings: clock: add dt binding header for mt7621 clocks

[PATCH v7 1/6] dt-bindings: clock: add dt binding header for mt7621 clocks

Adds dt binding header for 'mediatek,mt7621-clk' clocks.

Acked-by: Rob Herring 
Signed-off-by: Sergio Paracuellos 
---
 include/dt-bindings/clock/mt7621-clk.h | 41 ++
 1 file changed, 41 insertions(+)
 create mode 100644 include/dt-bindings/clock/mt7621-clk.h

diff --git a/include/dt-bindings/clock/mt7621-clk.h 
b/include/dt-bindings/clock/mt7621-clk.h
new file mode 100644
index ..1422badcf9de
--- /dev/null
+++ b/include/dt-bindings/clock/mt7621-clk.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Author: Sergio Paracuellos 
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT7621_H
+#define _DT_BINDINGS_CLK_MT7621_H
+
+#define MT7621_CLK_XTAL0
+#define MT7621_CLK_CPU 1
+#define MT7621_CLK_BUS 2
+#define MT7621_CLK_50M 3
+#define MT7621_CLK_125M4
+#define MT7621_CLK_150M5
+#define MT7621_CLK_250M6
+#define MT7621_CLK_270M7
+
+#define MT7621_CLK_HSDMA   8
+#define MT7621_CLK_FE  9
+#define MT7621_CLK_SP_DIVTX10
+#define MT7621_CLK_TIMER   11
+#define MT7621_CLK_PCM 12
+#define MT7621_CLK_PIO 13
+#define MT7621_CLK_GDMA14
+#define MT7621_CLK_NAND15
+#define MT7621_CLK_I2C 16
+#define MT7621_CLK_I2S 17
+#define MT7621_CLK_SPI 18
+#define MT7621_CLK_UART1   19
+#define MT7621_CLK_UART2   20
+#define MT7621_CLK_UART3   21
+#define MT7621_CLK_ETH 22
+#define MT7621_CLK_PCIE0   23
+#define MT7621_CLK_PCIE1   24
+#define MT7621_CLK_PCIE2   25
+#define MT7621_CLK_CRYPTO  26
+#define MT7621_CLK_SHXC27
+
+#define MT7621_CLK_MAX 28
+
+#endif /* _DT_BINDINGS_CLK_MT7621_H */
-- 
2.25.1

Re: [PATCH v2] Staging: mt7621-pci: fixed a blank line coding style issue

On Wed, Feb 17, 2021 at 8:07 AM Selvakumar Elangovan
 wrote:>
> Removed an unnecessary blank line before closing brace reported by
> checkpatch.pl
>
> Signed-off-by: Selvakumar Elangovan 
> ---
>  drivers/staging/mt7621-pci/pci-mt7621.c | 1 -
>  1 file changed, 1 deletion(-)

Reviewed-by: Sergio Paracuellos 

Best regards,
Sergio Paracuellos

Re: [PATCH] Staging: mt7621-pci: pci-mt7621: fixed a blank line coding style issue

Hi Selvakumar,

On Wed, Feb 17, 2021 at 7:53 AM Selvakumar Elangovan
 wrote:
>
> Removed an unecessary blank line before closing brace reported by
> checkpatch.pl

Typo:

s/unecessary/unnecessary/g

>
> Signed-off-by: Selvakumar Elangovan 
> ---
>  drivers/staging/mt7621-pci/pci-mt7621.c | 1 -
>  1 file changed, 1 deletion(-)
>
> diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c 
> b/drivers/staging/mt7621-pci/pci-mt7621.c
> index c3532bc138fb..1781c1dcf5b4 100644
> --- a/drivers/staging/mt7621-pci/pci-mt7621.c
> +++ b/drivers/staging/mt7621-pci/pci-mt7621.c
> @@ -521,7 +521,6 @@ static void mt7621_pcie_init_ports(struct mt7621_pcie 
> *pcie)
>
> if (slot == 1 && tmp && !tmp->enabled)
> phy_power_off(tmp->phy);
> -
> }
> }
>  }
> --
> 2.17.1
>

Please, also change commit short message to:

staging: mt7621-pci: fixed a blank line coding style issue

With that changes:

Reviewed-by: Sergio Paracuellos 

Best regards,
Sergio Paracuellos

[PATCH v6 6/6] MAINTAINERS: add MT7621 CLOCK maintainer

Adding myself as maintainer for mt7621 clock driver.

Signed-off-by: Sergio Paracuellos 
---
 MAINTAINERS | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 809a68af5efd..be5ada6b4309 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11288,6 +11288,12 @@ L: linux-wirel...@vger.kernel.org
 S: Maintained
 F: drivers/net/wireless/mediatek/mt7601u/
 
+MEDIATEK MT7621 CLOCK DRIVER
+M: Sergio Paracuellos 
+S: Maintained
+F: Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
+F: drivers/clk/ralink/clk-mt7621.c
+
 MEDIATEK MT7621/28/88 I2C DRIVER
 M: Stefan Roese 
 L: linux-...@vger.kernel.org
-- 
2.25.1

[PATCH v6 3/6] clk: ralink: add clock driver for mt7621 SoC

The documentation for this SOC only talks about two
registers regarding to the clocks:
* SYSC_REG_CPLL_CLKCFG0 - provides some information about
boostrapped refclock. PLL and dividers used for CPU and some
sort of BUS.
* SYSC_REG_CPLL_CLKCFG1 - a banch of gates to enable/disable
clocks for all or some ip cores.

Looking into driver code, and some openWRT patched there are
another frequencies which are used in some drivers (uart, sd...).
According to all of this information the clock plan for this
SoC is set as follows:
- Main top clock "xtal" from where all the rest of the world is
derived.
- CPU clock "cpu" derived from "xtal" frequencies and a bunch of
register reads and predividers.
- BUS clock "bus" derived from "cpu" and with (cpu / 4) MHz.
- Fixed clocks from "xtal":
* "50m": 50 MHz.
* "125m": 125 MHz.
* "150m": 150 MHz.
* "250m": 250 MHz.
* "270m": 270 MHz.

We also have a buch of gate clocks with their parents:
  * "hsdma": "150m"
  * "fe": "250m"
  * "sp_divtx": "270m"
  * "timer": "50m"
  * "pcm": "270m"
  * "pio": "50m"
  * "gdma": "bus"
  * "nand": "125m"
  * "i2c": "50m"
  * "i2s": "270m"
  * "spi": "bus"
  * "uart1": "50m"
  * "uart2": "50m"
  * "uart3": "50m"
  * "eth": "50m"
  * "pcie0": "125m"
  * "pcie1": "125m"
  * "pcie2": "125m"
  * "crypto": "250m"
  * "shxc": "50m"

With this information the clk driver will provide clock and gates
functionality from a a set of hardcoded clocks allowing to define
a nice device tree without fixed clocks.

Signed-off-by: Sergio Paracuellos 
---
 drivers/clk/Kconfig |   1 +
 drivers/clk/Makefile|   1 +
 drivers/clk/ralink/Kconfig  |  14 +
 drivers/clk/ralink/Makefile |   2 +
 drivers/clk/ralink/clk-mt7621.c | 459 
 5 files changed, 477 insertions(+)
 create mode 100644 drivers/clk/ralink/Kconfig
 create mode 100644 drivers/clk/ralink/Makefile
 create mode 100644 drivers/clk/ralink/clk-mt7621.c

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 7c5dc348c16f..70b23da997bf 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -382,6 +382,7 @@ source "drivers/clk/mediatek/Kconfig"
 source "drivers/clk/meson/Kconfig"
 source "drivers/clk/mvebu/Kconfig"
 source "drivers/clk/qcom/Kconfig"
+source "drivers/clk/ralink/Kconfig"
 source "drivers/clk/renesas/Kconfig"
 source "drivers/clk/rockchip/Kconfig"
 source "drivers/clk/samsung/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 5325847469e9..1b35ad852721 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -98,6 +98,7 @@ obj-$(CONFIG_COMMON_CLK_NXP)  += nxp/
 obj-$(CONFIG_MACH_PISTACHIO)   += pistachio/
 obj-$(CONFIG_COMMON_CLK_PXA)   += pxa/
 obj-$(CONFIG_COMMON_CLK_QCOM)  += qcom/
+obj-y  += ralink/
 obj-y  += renesas/
 obj-$(CONFIG_ARCH_ROCKCHIP)+= rockchip/
 obj-$(CONFIG_COMMON_CLK_SAMSUNG)   += samsung/
diff --git a/drivers/clk/ralink/Kconfig b/drivers/clk/ralink/Kconfig
new file mode 100644
index ..f1de548ed781
--- /dev/null
+++ b/drivers/clk/ralink/Kconfig
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# MediaTek Mt7621 Clock Driver
+#
+menu "Clock driver for Mediatek mt7621 SoC"
+   depends on SOC_MT7621
+
+config CLK_MT7621
+   bool "Clock driver for MediaTek MT7621"
+   depends on SOC_MT7621
+   default SOC_MT7621
+   help
+ This driver supports MediaTek MT7621 basic clocks.
+endmenu
diff --git a/drivers/clk/ralink/Makefile b/drivers/clk/ralink/Makefile
new file mode 100644
index ..cf6f9216379d
--- /dev/null
+++ b/drivers/clk/ralink/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_CLK_MT7621) += clk-mt7621.o
diff --git a/drivers/clk/ralink/clk-mt7621.c b/drivers/clk/ralink/clk-mt7621.c
new file mode 100644
index ..f28f6bdce4c7
--- /dev/null
+++ b/drivers/clk/ralink/clk-mt7621.c
@@ -0,0 +1,459 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Mediatek MT7621 Clock Driver
+ * Author: Sergio Paracuellos 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* Configuration registers */
+#define SYSC_REG_SYSTEM_CONFIG0 0x10
+#define SYSC_REG_SYSTEM_CONFIG1 0x14
+#define SYSC_REG_CLKCFG0

[PATCH v6 5/6] staging: mt7621-dts: use valid vendor 'mediatek' instead of invalid 'mtk'

Vendor listed for mediatek in kernel vendor file 'vendor-prefixes.yaml'
contains 'mediatek' as a valid vendor string. Some nodes in the device
tree are using an invalid vendor string vfor 'mtk' instead. Fix all of
them in dts file. Update also ralink mt7621 related code to properly
match new strings. Even there are used in the device tree there are
some strings that are not referred anywhere but have been also updated
with new vendor name. These are 'mtk,mt7621-wdt', 'mtk,mt7621-nand',
'mtk,mt7621-mc', and 'mtk,mt7621-cpc'.

Acked-by: Greg Kroah-Hartman 
Signed-off-by: Sergio Paracuellos 
---
 arch/mips/ralink/mt7621.c  |  6 +++---
 drivers/staging/mt7621-dts/mt7621.dtsi | 12 ++--
 2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/arch/mips/ralink/mt7621.c b/arch/mips/ralink/mt7621.c
index ca0ac607b0f3..5d74fc1c96ac 100644
--- a/arch/mips/ralink/mt7621.c
+++ b/arch/mips/ralink/mt7621.c
@@ -112,8 +112,8 @@ phys_addr_t mips_cpc_default_phys_base(void)
 
 void __init ralink_of_remap(void)
 {
-   rt_sysc_membase = plat_of_remap_node("mtk,mt7621-sysc");
-   rt_memc_membase = plat_of_remap_node("mtk,mt7621-memc");
+   rt_sysc_membase = plat_of_remap_node("mediatek,mt7621-sysc");
+   rt_memc_membase = plat_of_remap_node("mediatek,mt7621-memc");
 
if (!rt_sysc_membase || !rt_memc_membase)
panic("Failed to remap core resources");
@@ -181,7 +181,7 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
 
if (n0 == MT7621_CHIP_NAME0 && n1 == MT7621_CHIP_NAME1) {
name = "MT7621";
-   soc_info->compatible = "mtk,mt7621-soc";
+   soc_info->compatible = "mediatek,mt7621-soc";
} else {
panic("mt7621: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
}
diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi 
b/drivers/staging/mt7621-dts/mt7621.dtsi
index 11d1670d4339..55784dd48dc5 100644
--- a/drivers/staging/mt7621-dts/mt7621.dtsi
+++ b/drivers/staging/mt7621-dts/mt7621.dtsi
@@ -56,7 +56,7 @@ palmbus: palmbus@1E00 {
#size-cells = <1>;
 
sysc: sysc@0 {
-   compatible = "mtk,mt7621-sysc", "syscon";
+   compatible = "mediatek,mt7621-sysc", "syscon";
reg = <0x0 0x100>;
};
 
@@ -71,7 +71,7 @@ pll: pll {
};
 
wdt: wdt@100 {
-   compatible = "mtk,mt7621-wdt";
+   compatible = "mediatek,mt7621-wdt";
reg = <0x100 0x100>;
};
 
@@ -128,17 +128,17 @@ i2s: i2s@a00 {
};
 
memc: memc@5000 {
-   compatible = "mtk,mt7621-memc", "syscon";
+   compatible = "mediatek,mt7621-memc", "syscon";
reg = <0x5000 0x1000>;
};
 
cpc: cpc@1fbf {
-compatible = "mtk,mt7621-cpc";
+compatible = "mediatek,mt7621-cpc";
 reg = <0x1fbf 0x8000>;
};
 
mc: mc@1fbf8000 {
-   compatible = "mtk,mt7621-mc";
+   compatible = "mediatek,mt7621-mc";
reg = <0x1fbf8000 0x8000>;
};
 
@@ -366,7 +366,7 @@ timer {
nand: nand@1e003000 {
status = "disabled";
 
-   compatible = "mtk,mt7621-nand";
+   compatible = "mediatek,mt7621-nand";
bank-width = <2>;
reg = <0x1e003000 0x800
0x1e003800 0x800>;
-- 
2.25.1

[PATCH v6 4/6] staging: mt7621-dts: make use of new 'mt7621-clk'

Clocks for SoC mt7621 have been properly integrated so there is
no need to declare fixed clocks at all in the device tree. Remove
all of them, add new device tree nodes for mt7621-clk and update
the rest of the nodes to use them.

Acked-by: Greg Kroah-Hartman 
Signed-off-by: Sergio Paracuellos 
---
 drivers/staging/mt7621-dts/gbpc1.dts   | 11 
 drivers/staging/mt7621-dts/mt7621.dtsi | 79 +-
 2 files changed, 38 insertions(+), 52 deletions(-)

diff --git a/drivers/staging/mt7621-dts/gbpc1.dts 
b/drivers/staging/mt7621-dts/gbpc1.dts
index a7c0d3115d72..7716d0efe524 100644
--- a/drivers/staging/mt7621-dts/gbpc1.dts
+++ b/drivers/staging/mt7621-dts/gbpc1.dts
@@ -100,17 +100,6 @@ partition@5 {
};
 };
 
- {
-   compatible = "fixed-clock";
-   /* This is normally 1/4 of cpuclock */
-   clock-frequency = <22500>;
-};
-
- {
-   compatible = "fixed-clock";
-   clock-frequency = <9>;
-};
-
  {
pinctrl-names = "default";
pinctrl-0 = <_pins>;
diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi 
b/drivers/staging/mt7621-dts/mt7621.dtsi
index 16fc94f65486..11d1670d4339 100644
--- a/drivers/staging/mt7621-dts/mt7621.dtsi
+++ b/drivers/staging/mt7621-dts/mt7621.dtsi
@@ -1,5 +1,6 @@
 #include 
 #include 
+#include 
 
 / {
#address-cells = <1>;
@@ -27,27 +28,6 @@ aliases {
serial0 = 
};
 
-   cpuclock: cpuclock@0 {
-   #clock-cells = <0>;
-   compatible = "fixed-clock";
-
-   /* FIXME: there should be way to detect this */
-   clock-frequency = <88000>;
-   };
-
-   sysclock: sysclock@0 {
-   #clock-cells = <0>;
-   compatible = "fixed-clock";
-
-   /* This is normally 1/4 of cpuclock */
-   clock-frequency = <22000>;
-   };
-
-   mmc_clock: mmc_clock@0 {
-   #clock-cells = <0>;
-   compatible = "fixed-clock";
-   clock-frequency = <4800>;
-   };
 
mmc_fixed_3v3: fixedregulator@0 {
compatible = "regulator-fixed";
@@ -76,10 +56,20 @@ palmbus: palmbus@1E00 {
#size-cells = <1>;
 
sysc: sysc@0 {
-   compatible = "mtk,mt7621-sysc";
+   compatible = "mtk,mt7621-sysc", "syscon";
reg = <0x0 0x100>;
};
 
+   pll: pll {
+   compatible = "mediatek,mt7621-clk";
+   #clock-cells = <1>;
+   ralink,sysctl = <>;
+   ralink,memctl = <>;
+   clock-output-names = "xtal", "cpu", "bus",
+"50m", "125m", "150m",
+"250m", "270m";
+   };
+
wdt: wdt@100 {
compatible = "mtk,mt7621-wdt";
reg = <0x100 0x100>;
@@ -101,8 +91,8 @@ i2c: i2c@900 {
compatible = "mediatek,mt7621-i2c";
reg = <0x900 0x100>;
 
-   clocks = <>;
-
+   clocks = < MT7621_CLK_I2C>;
+   clock-names = "i2c";
resets = < 16>;
reset-names = "i2c";
 
@@ -119,8 +109,8 @@ i2s: i2s@a00 {
compatible = "mediatek,mt7621-i2s";
reg = <0xa00 0x100>;
 
-   clocks = <>;
-
+   clocks = < MT7621_CLK_I2S>;
+   clock-names = "i2s";
resets = < 17>;
reset-names = "i2s";
 
@@ -138,7 +128,7 @@ i2s: i2s@a00 {
};
 
memc: memc@5000 {
-   compatible = "mtk,mt7621-memc";
+   compatible = "mtk,mt7621-memc", "syscon";
reg = <0x5000 0x1000>;
};
 
@@ -156,8 +146,8 @@ uartlite: uartlite@c00 {
compatible = "ns16550a";
reg = <0xc00 0x100>;
 
-   clocks = <>;
-   clock-frequency = <5000>;
+   clocks = < MT7621_CLK_UART1>;
+   clock-names = "uart1";
 
interrupt-parent = <>;

[PATCH v6 2/6] dt: bindings: add mt7621-clk device tree binding documentation

Adds device tree binding documentation for clocks in the
MT7621 SOC.

Signed-off-by: Sergio Paracuellos 
---
 .../bindings/clock/mediatek,mt7621-clk.yaml   | 66 +++
 1 file changed, 66 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml

diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml 
b/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
new file mode 100644
index ..842a0f2c9d40
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
@@ -0,0 +1,66 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/mediatek,mt7621-clk.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MT7621 Clock Device Tree Bindings
+
+maintainers:
+  - Sergio Paracuellos 
+
+description: |
+  The MT7621 has a PLL controller from where the cpu clock is provided
+  as well as derived clocks for the bus and the peripherals. It also
+  can gate SoC device clocks.
+
+  Each clock is assigned an identifier and client nodes use this identifier
+  to specify the clock which they consume.
+
+  All these identifiers could be found in:
+  [1]: .
+
+properties:
+  compatible:
+const: mediatek,mt7621-clk
+
+  "#clock-cells":
+description:
+  The first cell indicates the clock number, see [1] for available
+  clocks.
+const: 1
+
+  ralink,sysctl:
+$ref: /schemas/types.yaml#/definitions/phandle
+description:
+  phandle of syscon used to control system registers
+
+  ralink,memctl:
+$ref: /schemas/types.yaml#/definitions/phandle
+description:
+  phandle of syscon used to control memory registers
+
+  clock-output-names:
+maxItems: 8
+
+required:
+  - compatible
+  - '#clock-cells'
+  - ralink,sysctl
+  - ralink,memctl
+
+additionalProperties: false
+
+examples:
+  - |
+#include 
+
+pll {
+  compatible = "mediatek,mt7621-clk";
+  #clock-cells = <1>;
+  ralink,sysctl = <>;
+  ralink,memctl = <>;
+  clock-output-names = "xtal", "cpu", "bus",
+   "50m", "125m", "150m",
+   "250m", "270m";
+};
-- 
2.25.1

[PATCH v6 1/6] dt-bindings: clock: add dt binding header for mt7621 clocks

Adds dt binding header for 'mediatek,mt7621-clk' clocks.

Acked-by: Rob Herring 
Signed-off-by: Sergio Paracuellos 
---
 include/dt-bindings/clock/mt7621-clk.h | 41 ++
 1 file changed, 41 insertions(+)
 create mode 100644 include/dt-bindings/clock/mt7621-clk.h

diff --git a/include/dt-bindings/clock/mt7621-clk.h 
b/include/dt-bindings/clock/mt7621-clk.h
new file mode 100644
index ..1422badcf9de
--- /dev/null
+++ b/include/dt-bindings/clock/mt7621-clk.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Author: Sergio Paracuellos 
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT7621_H
+#define _DT_BINDINGS_CLK_MT7621_H
+
+#define MT7621_CLK_XTAL0
+#define MT7621_CLK_CPU 1
+#define MT7621_CLK_BUS 2
+#define MT7621_CLK_50M 3
+#define MT7621_CLK_125M4
+#define MT7621_CLK_150M5
+#define MT7621_CLK_250M6
+#define MT7621_CLK_270M7
+
+#define MT7621_CLK_HSDMA   8
+#define MT7621_CLK_FE  9
+#define MT7621_CLK_SP_DIVTX10
+#define MT7621_CLK_TIMER   11
+#define MT7621_CLK_PCM 12
+#define MT7621_CLK_PIO 13
+#define MT7621_CLK_GDMA14
+#define MT7621_CLK_NAND15
+#define MT7621_CLK_I2C 16
+#define MT7621_CLK_I2S 17
+#define MT7621_CLK_SPI 18
+#define MT7621_CLK_UART1   19
+#define MT7621_CLK_UART2   20
+#define MT7621_CLK_UART3   21
+#define MT7621_CLK_ETH 22
+#define MT7621_CLK_PCIE0   23
+#define MT7621_CLK_PCIE1   24
+#define MT7621_CLK_PCIE2   25
+#define MT7621_CLK_CRYPTO  26
+#define MT7621_CLK_SHXC27
+
+#define MT7621_CLK_MAX 28
+
+#endif /* _DT_BINDINGS_CLK_MT7621_H */
-- 
2.25.1

[PATCH v6 0/6] MIPS: ralink: add CPU clock detection and clock driver for MT7621

lk_init' and pass from there into different register
   functions. Remove pointers to 'mt7621_clk_provider' in the rest fo structs
   used in this driver.
 - Remove MHZ macro and just pass values directly in hertzs.
 - Avoid 'CLK_IGNORE_UNUSED' flag for gates and add a new function called
   'mt7621_prepare_enable_clocks' to prepare all of them to make clocks
   referenced and don't affect current driver code.
 - Remove COMPILE_TEST from Kconfig because of the use of especific arch
   stuff.
 - Fix commit message where a typo for "frequencies" word was present.
 - Make use of parent_clk_data in 'CLK_BASE' macro.
 - Remove MODULE_* macros from code since this is not a module.
 - Remove not needed includes.
 - Hardcode "xtal" as parent in FIXED macro.
 - Change 'else if' clause into 'if' clause since a return statement was
   being used in 'mt7621_xtal_recalc_rate'.

 NOTES:
   - Driver is still being declared using 'CLK_OF_DECLARE' for all the  
 clocks. I have explored the possibility to make some of them available
 afterwards using 'CLK_OF_DECLARE_DRIVER' for top clocks and the rest
 using a platform driver. The resulting code was uglier since we only want
 to use the same device tree node and the top clocks must be copied again
 for the new platform register stuff to properly have a good hierarchy.
 New globals needs to be introduced and in this particular case I don't
 really see the benefits of doing in this way. I am totally ok to have all
 the clocks registered at early stage since from other drivers perspective
 we only really need to enable gates. So, I prefer to have them in that
 way if it is not a real problem, of course.

Changes in v4:
 - Add Acked-by from Rob Herring for binding headers (PATCH 1/6).
 - Convert bindings to not use syscon phandle and declare clock as
   a child of the syscon node. Update device tree and binding doc
   accordly.
 - Make use of 'syscon_node_to_regmap' in driver code instead of
   get this using the phandle function.
 - Properly unregister clocks for the error path of the function
   'mt7621_clk_init'.
 - Include ARRAY_SIZE of fixed clocks in the 'count' to kzalloc
   of 'clk_data'.
 - Add new patch changing invalid vendor 'mtk' in favour of 'mediatek'
   which is the one listed in 'vendor-prefixes.yaml'. Update mt7621 code
   accordly. I have added this patch inside this series because clk
   binding is referring syscon node and the string for that node was
   with not listed vendor. Hence update and have all of this correct
   in the same series.

Changes in v3:
 - Fix compilation warnings reported by kernel test robot because of
   ignoring return values of 'of_clk_hw_register' in functions
   'mt7621_register_top_clocks' and 'mt7621_gate_ops_init'.
 - Fix dts file and binding documentation 'clock-output-names'.

Changes in v2:
 - Remove the following patches:
   * dt: bindings: add mt7621-pll device tree binding documentation.
   * MIPS: ralink: add clock device providing cpu/ahb/apb clock for mt7621.
 - Move all relevant clock code to 'drivers/clk/ralink/clk-mt7621.c' and
   unify there previous 'mt7621-pll' and 'mt7621-clk' into a unique driver
   and binding 'mt7621-clk'.
 - Driver is not a platform driver anymore and now make use of 'CLK_OF_DECLARE'
   because we need clocks available in 'plat_time_init' before setting up
   the timer for the GIC.
 - Use new fixed clocks as parents for different gates and deriving from 'xtal'
   using frequencies in[1].
 - Adapt dts file and bindings header and documentation for new changes.
 - Change MAINTAINERS file to only contains clk-mt7621.c code and
   mediatek,mt7621-clk.yaml file.

[0]: https://www.lkml.org/lkml/2019/7/23/1044
[1]: 
https://github.com/981213/linux/commit/2eca1f045e4c3db18c941135464c0d7422ad8133
[2]: https://lkml.org/lkml/2020/12/20/47

Sergio Paracuellos (6):
  dt-bindings: clock: add dt binding header for mt7621 clocks
  dt: bindings: add mt7621-clk device tree binding documentation
  clk: ralink: add clock driver for mt7621 SoC
  staging: mt7621-dts: make use of new 'mt7621-clk'
  staging: mt7621-dts: use valid vendor 'mediatek' instead of invalid
'mtk'
  MAINTAINERS: add MT7621 CLOCK maintainer

 .../bindings/clock/mediatek,mt7621-clk.yaml   |  66 +++
 MAINTAINERS   |   6 +
 arch/mips/ralink/mt7621.c |   6 +-
 drivers/clk/Kconfig   |   1 +
 drivers/clk/Makefile  |   1 +
 drivers/clk/ralink/Kconfig|  14 +
 drivers/clk/ralink/Makefile   |   2 +
 drivers/clk/ralink/clk-mt7621.c   | 459 ++
 drivers/staging/mt7621-dts/gbpc1.dts  |  11 -
 drivers/staging/mt7621-dts/mt7621.dtsi|  87 ++--
 include/dt-bindings/clock/mt7621-clk.h|  41 ++
 11 files changed, 635 insertions(+), 59 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
 create mode 100644 drivers/clk/ralink/Kconfig
 create mode 100644 drivers/clk/ralink/Makefile
 create mode 100644 drivers/clk/ralink/clk-mt7621.c
 create mode 100644 include/dt-bindings/clock/mt7621-clk.h

-- 
2.25.1

Re: [PATCH v5 0/6] MIPS: ralink: add CPU clock detection and clock driver for MT7621

2021-01-17 Thread Sergio Paracuellos

Hi all,

On Sun, Dec 20, 2020 at 10:37 AM Sergio Paracuellos
 wrote:
>
> This patchset ports CPU clock detection for MT7621 from OpenWrt
> and adds a complete clock plan for the mt7621 SOC.
>
> The documentation for this SOC only talks about two registers
> regarding to the clocks:
> * SYSC_REG_CPLL_CLKCFG0 - provides some information about boostrapped
> refclock. PLL and dividers used for CPU and some sort of BUS (AHB?).
> * SYSC_REG_CPLL_CLKCFG1 - a banch of gates to enable/disable clocks for
> all or some ip cores.
>
> No documentation about a probably existent set of dividers for each ip
> core is included in the datasheets. So we cannot make anything better,
> AFAICT.
>
> Looking into driver code, and some openWRT patched there are
> another frequences which are used in some drivers (uart, sd...).
> According to all of this information the clock plan for this
> SoC is set as follows:
>  - Main top clock "xtal" from where all the rest of the world is
>derived.
>  - CPU clock "cpu" derived from "xtal" frequencies and a bunch of
>register reads and predividers.
>  - BUS clock "bus" derived from "cpu" and with (cpu / 4) MHz.
>  - Fixed clocks from "xtal":
> * "50m": 50 MHz.
> * "125m": 125 MHz.
> * "150m": 150 MHz.
> * "250m": 250 MHz.
> * "270m": 270 MHz.
>
> We also have a buch of gate clocks with their parents:
>  - "hsdma": "150m"
>  - "fe": "250m"
>  - "sp_divtx": "270m"
>  - "timer": "50m"
>  - "pcm": "270m"
>  - "pio": "50m"
>  - "gdma": "bus"
>  - "nand": "125m"
>  - "i2c": "50m"
>  - "i2s": "270m"
>  - "spi": "bus"
>  - "uart1": "50m"
>  - "uart2": "50m"
>  - "uart3": "50m"
>  - "eth": "50m"
>  - "pcie0": "125m"
>  - "pcie1": "125m"
>  - "pcie2": "125m"
>  - "crypto": "250m"
>  - "shxc": "50m"
>
> There was a previous attempt of doing this here[0] but the author
> (Chuanhong Guo) did not wanted to make assumptions of a clock plan
> for the platform that time. It seems that now he has a better idea of
> how the clocks are dispossed for this SoC so he share code[1] where
> some frequencies and clock parents for the gates are coded from a
> real mediatek private clock plan.
>
> I do really want this to be upstreamed so according to the comments
> in previous attempt[0] from Oleksij Rempel and the frequencies in
> code[1] I have tried to do this by myself.
>
> All of this patches have been tested in a GNUBee PC1 resulting in a
> working platform.
>
> Changes in v5:
>  - Avoid the use of syscon. All drivers of this platform are just using
>platform operations defined in 'asm/mach-ralink/ralink_regs.h'. We also
>need them for some PLL registers that are not in the sys control area.
>Hence, since we must use this dependency avoid to define clock driver
>as a child of the sysc node in the device tree and follow current
>platform code style.
>  - Update bindings documentation to don't refer the syscon and make
>remove 'clock-output-names' property from required ones.
>  - Use 'asm/mach-ralink/ralink_regs.h' platform read and write operations
>instead of regmap from the syscon node.
>  - Remove 'mt7621_clk_provider' and directly declare 'clk_hw_onecell_data'
>pointer in 'mt7621_clk_init' and pass from there into different register
>functions. Remove pointers to 'mt7621_clk_provider' in the rest fo structs
>used in this driver.
>  - Remove MHZ macro and just pass values directly in hertzs.
>  - Avoid 'CLK_IGNORE_UNUSED' flag for gates and add a new function called
>'mt7621_prepare_enable_clocks' to prepare all of them to make clocks
>referenced and don't affect current driver code.
>  - Remove COMPILE_TEST from Kconfig because of the use of especific arch
>stuff.
>  - Fix commit message where a typo for "frequencies" word was present.
>  - Make use of parent_clk_data in 'CLK_BASE' macro.
>  - Remove MODULE_* macros from code since this is not a module.
>  - Remove not needed includes.
>  - Hardcode "xtal" as parent in FIXED macro.
>  - Change 'else if' clause into 'if' clause since a return statement was
>being used in 'mt7621_xtal_recalc_rate'.
>
>  NOTES:
>- Driver is still being declared using 'CLK_OF

Re: [PATCH] staging: mt7621-dts: remove obsolete switch node

2021-01-07 Thread Sergio Paracuellos

On Fri, Jan 8, 2021 at 3:52 AM DENG Qingfang  wrote:
>
> This was for OpenWrt's swconfig driver, which never made it upstream,
> and was also superseded by MT7530 DSA driver.
>
> Signed-off-by: DENG Qingfang 
> ---
>  drivers/staging/mt7621-dts/mt7621.dtsi | 7 ---
>  1 file changed, 7 deletions(-)

Reviewed-by: Sergio Paracuellos

Re: [PATCH v5 2/6] dt: bindings: add mt7621-clk device tree binding documentation

2021-01-02 Thread Sergio Paracuellos

On Fri, Jan 1, 2021 at 12:51 AM Sergio Paracuellos
 wrote:
>
> Hi Rob,
>
> Thanks for the review.

Hi again,

>
> On Thu, Dec 31, 2020 at 11:38 PM Rob Herring  wrote:
> >
> > On Sun, Dec 20, 2020 at 10:37:20AM +0100, Sergio Paracuellos wrote:
> > > Adds device tree binding documentation for clocks in the
> > > MT7621 SOC.
> > >
> > > Signed-off-by: Sergio Paracuellos 
> > > ---
> > >  .../bindings/clock/mediatek,mt7621-clk.yaml   | 52 +++
> > >  1 file changed, 52 insertions(+)
> > >  create mode 100644 
> > > Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
> > >
> > > diff --git 
> > > a/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml 
> > > b/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
> > > new file mode 100644
> > > index ..f58d01bdc82c
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
> > > @@ -0,0 +1,52 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > +%YAML 1.2
> > > +---
> > > +$id: http://devicetree.org/schemas/clock/mediatek,mt7621-clk.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: MT7621 Clock Device Tree Bindings
> > > +
> > > +maintainers:
> > > +  - Sergio Paracuellos 
> > > +
> > > +description: |
> > > +  The MT7621 has a PLL controller from where the cpu clock is provided
> > > +  as well as derived clocks for the bus and the peripherals. It also
> > > +  can gate SoC device clocks.
> > > +
> > > +  Each clock is assigned an identifier and client nodes use this 
> > > identifier
> > > +  to specify the clock which they consume.
> > > +
> > > +  All these identifiers could be found in:
> > > +  [1]: .
> > > +
> > > +properties:
> > > +  compatible:
> > > +const: mediatek,mt7621-clk
> > > +
> > > +  "#clock-cells":
> > > +description:
> > > +  The first cell indicates the clock number, see [1] for available
> > > +  clocks.
> > > +const: 1
> > > +
> > > +  clock-output-names:
> > > +maxItems: 8
> > > +
> > > +required:
> > > +  - compatible
> > > +  - '#clock-cells'
> > > +
> > > +additionalProperties: false
> > > +
> > > +examples:
> > > +  - |
> > > +#include 
> > > +
> > > +pll {
> > > +  compatible = "mediatek,mt7621-clk";
> > > +  #clock-cells = <1>;
> > > +  clock-output-names = "xtal", "cpu", "bus",
> > > +   "50m", "125m", "150m",
> > > +   "250m", "270m";
> >
> > How do you access this h/w. There's nothing defined like 'reg' or
> > a parent node or...
>
> Through read write operations defined in
> "asm/mach-ralink/ralink_regs.h. Please, see my explanation below.
>
> >
> > The suggestion on v4 was to get rid of the child node by merging it with
> > the parent like this:
> >
> > +sysc: sysc@0 {
> > +  compatible = "mediatek,mt7621-sysc", "syscon";
> > +  reg = <0x0 0x100>;
> > +  #clock-cells = <1>;
> > +  clock-output-names = "xtal", "cpu", "bus",
> > + "50m", "125m", "150m",
> > + "250m", "270m";
> > +};
> >
> > Whether you need child nodes or not really depends on what all is in the
> > 'mt7621-sysc' h/w block.
>
> All the drivers in this platform make use of arch operations defined
> in "asm/mach-ralink/ralink_regs.h". This mediatek,mt7621-sysc is
> directly mapped by the architecture
> in arch/mips/ralink/mt7621.c in function void __init
> ralink_of_remap(void). This is the first address in the virtual space
> and from here "rt_sysc_membase" and "rt_memc_membase" are used to
> access the hardware control registers through read and write
> operations. So "mediatek,mt7621-sysc" cannot be remapped from clock
> driver. The benefits I found at first of using the syscon as child
> node was to avoid the use of architecture dependant operations but at
> the end I r

Re: [PATCH v5 2/6] dt: bindings: add mt7621-clk device tree binding documentation

2020-12-31 Thread Sergio Paracuellos

Hi Rob,

Thanks for the review.

On Thu, Dec 31, 2020 at 11:38 PM Rob Herring  wrote:
>
> On Sun, Dec 20, 2020 at 10:37:20AM +0100, Sergio Paracuellos wrote:
> > Adds device tree binding documentation for clocks in the
> > MT7621 SOC.
> >
> > Signed-off-by: Sergio Paracuellos 
> > ---
> >  .../bindings/clock/mediatek,mt7621-clk.yaml   | 52 +++
> >  1 file changed, 52 insertions(+)
> >  create mode 100644 
> > Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
> >
> > diff --git 
> > a/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml 
> > b/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
> > new file mode 100644
> > index ..f58d01bdc82c
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
> > @@ -0,0 +1,52 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/clock/mediatek,mt7621-clk.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: MT7621 Clock Device Tree Bindings
> > +
> > +maintainers:
> > +  - Sergio Paracuellos 
> > +
> > +description: |
> > +  The MT7621 has a PLL controller from where the cpu clock is provided
> > +  as well as derived clocks for the bus and the peripherals. It also
> > +  can gate SoC device clocks.
> > +
> > +  Each clock is assigned an identifier and client nodes use this identifier
> > +  to specify the clock which they consume.
> > +
> > +  All these identifiers could be found in:
> > +  [1]: .
> > +
> > +properties:
> > +  compatible:
> > +const: mediatek,mt7621-clk
> > +
> > +  "#clock-cells":
> > +description:
> > +  The first cell indicates the clock number, see [1] for available
> > +  clocks.
> > +const: 1
> > +
> > +  clock-output-names:
> > +maxItems: 8
> > +
> > +required:
> > +  - compatible
> > +  - '#clock-cells'
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +#include 
> > +
> > +pll {
> > +  compatible = "mediatek,mt7621-clk";
> > +  #clock-cells = <1>;
> > +  clock-output-names = "xtal", "cpu", "bus",
> > +   "50m", "125m", "150m",
> > +   "250m", "270m";
>
> How do you access this h/w. There's nothing defined like 'reg' or
> a parent node or...

Through read write operations defined in
"asm/mach-ralink/ralink_regs.h. Please, see my explanation below.

>
> The suggestion on v4 was to get rid of the child node by merging it with
> the parent like this:
>
> +sysc: sysc@0 {
> +  compatible = "mediatek,mt7621-sysc", "syscon";
> +  reg = <0x0 0x100>;
> +  #clock-cells = <1>;
> +  clock-output-names = "xtal", "cpu", "bus",
> + "50m", "125m", "150m",
> + "250m", "270m";
> +};
>
> Whether you need child nodes or not really depends on what all is in the
> 'mt7621-sysc' h/w block.

All the drivers in this platform make use of arch operations defined
in "asm/mach-ralink/ralink_regs.h". This mediatek,mt7621-sysc is
directly mapped by the architecture
in arch/mips/ralink/mt7621.c in function void __init
ralink_of_remap(void). This is the first address in the virtual space
and from here "rt_sysc_membase" and "rt_memc_membase" are used to
access the hardware control registers through read and write
operations. So "mediatek,mt7621-sysc" cannot be remapped from clock
driver. The benefits I found at first of using the syscon as child
node was to avoid the use of architecture dependant operations but at
the end I realized that we need to access another register which is
not in the syscon block and it is not also well documented so the use
of arch operations is mandatory to make things work. That's why I end
up in just follow the architecture driver style and use this in the
same way, trying to maintain as clean as possible. Is it ok then to
declare it as it is in this way?

>
> Rob

Best regards,
Sergio Paracuellos

Re: drivers/pinctrl/ralink/pinctrl-rt2880.c:365:12: warning: no previous prototype for function 'rt2880_pinmux_init'

2020-12-28 Thread Sergio Paracuellos

Hi,

On Mon, Dec 28, 2020 at 12:15 PM kernel test robot  wrote:
>
> Hi Sergio,
>
> First bad commit (maybe != root cause):
>
> tree:   https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 
> master
> head:   5c8fe583cce542aa0b84adc939ce85293de36e5e
> commit: 518b466a21ad7fa1e338fa4ed9d180ef439d3bc0 pinctrl: ralink: add a 
> pinctrl driver for the rt2880 family
> date:   3 weeks ago
> config: mips-randconfig-r012-20201228 (attached as .config)
> compiler: clang version 12.0.0 (https://github.com/llvm/llvm-project 
> cee1e7d14f4628d6174b33640d502bff3b54ae45)
> reproduce (this is a W=1 build):
> wget 
> https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O 
> ~/bin/make.cross
> chmod +x ~/bin/make.cross
> # install mips cross compiling tool for clang build
> # apt-get install binutils-mips-linux-gnu
> # 
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=518b466a21ad7fa1e338fa4ed9d180ef439d3bc0
> git remote add linus 
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
> git fetch --no-tags linus master
> git checkout 518b466a21ad7fa1e338fa4ed9d180ef439d3bc0
> # save the attached .config to linux build tree
> COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=mips
>
> If you fix the issue, kindly add following tag as appropriate
> Reported-by: kernel test robot 
>
> All warnings (new ones prefixed by >>):
>
> >> drivers/pinctrl/ralink/pinctrl-rt2880.c:365:12: warning: no previous 
> >> prototype for function 'rt2880_pinmux_init' [-Wmissing-prototypes]
>int __init rt2880_pinmux_init(void)
>   ^
>drivers/pinctrl/ralink/pinctrl-rt2880.c:365:1: note: declare 'static' if 
> the function is not intended to be used outside of this translation unit
>int __init rt2880_pinmux_init(void)
>^
>static
>1 warning generated.
>
>
> vim +/rt2880_pinmux_init +365 drivers/pinctrl/ralink/pinctrl-rt2880.c
>
> 0317d60de869786 drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c John Crispin  
>  2018-03-15  364
> 1d2d116a93f0e9b drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c Sergio 
> Paracuellos 2018-07-09 @365  int __init rt2880_pinmux_init(void)
> 1d2d116a93f0e9b drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c Sergio 
> Paracuellos 2018-07-09  366  {
> 1d2d116a93f0e9b drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c Sergio 
> Paracuellos 2018-07-09  367  return 
> platform_driver_register(_pinmux_driver);
> 1d2d116a93f0e9b drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c Sergio 
> Paracuellos 2018-07-09  368  }
> 1d2d116a93f0e9b drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c Sergio 
> Paracuellos 2018-07-09  369
>
> :: The code at line 365 was first introduced by commit
> :: 1d2d116a93f0e9bf0bca72da76a96edef8a1d36d Revert "staging: 
> mt7621-pinctrl: replace core_initcall_sync with builtin_platform_driver"
>
> :: TO: Sergio Paracuellos 
> :: CC: Greg Kroah-Hartman 
>
> ---
> 0-DAY CI Kernel Test Service, Intel Corporation
> https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org

Already sent this morning: https://lkml.org/lkml/2020/12/28/16

Thanks,
Sergio Paracuellos

[PATCH] pinctrl: ralink: rt2880: fix '-Wmissing-prototypes' in init function

2020-12-27 Thread Sergio Paracuellos

Kernel test robot reported the following warning:
'warning: no previous prototype for 'rt2880_pinmux_init''.
This function is the entry point for the platform driver and
it is private to this driver. Hence declare it 'static' which is
the correct thing to do fixing also this warning.

Reported-by: kernel test robot 
Signed-off-by: Sergio Paracuellos 
---
Hi Linus, 

Just a note to let you know that this patch is rebased on the top of this
series which are pending to be applied:
http://driverdev.linuxdriverproject.org/pipermail/driverdev-devel/2020-December/149353.html

Thanks in advance for your time!

Best regards,
Sergio Paracuellos

 drivers/pinctrl/ralink/pinctrl-rt2880.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pinctrl/ralink/pinctrl-rt2880.c 
b/drivers/pinctrl/ralink/pinctrl-rt2880.c
index 983da62ff3be..1f8e8d5b71fd 100644
--- a/drivers/pinctrl/ralink/pinctrl-rt2880.c
+++ b/drivers/pinctrl/ralink/pinctrl-rt2880.c
@@ -361,7 +361,7 @@ static struct platform_driver rt2880_pinmux_driver = {
},
 };
 
-int __init rt2880_pinmux_init(void)
+static int __init rt2880_pinmux_init(void)
 {
return platform_driver_register(_pinmux_driver);
 }
-- 
2.25.1

[PATCH v5 6/6] MAINTAINERS: add MT7621 CLOCK maintainer

Adding myself as maintainer for mt7621 clock driver.

Signed-off-by: Sergio Paracuellos 
---
 MAINTAINERS | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index f5eafee83bc6..f0c51d9760ec 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11247,6 +11247,12 @@ L: linux-wirel...@vger.kernel.org
 S: Maintained
 F: drivers/net/wireless/mediatek/mt7601u/
 
+MEDIATEK MT7621 CLOCK DRIVER
+M: Sergio Paracuellos 
+S: Maintained
+F: Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
+F: drivers/clk/ralink/clk-mt7621.c
+
 MEDIATEK MT7621/28/88 I2C DRIVER
 M: Stefan Roese 
 L: linux-...@vger.kernel.org
-- 
2.25.1

[PATCH v5 5/6] staging: mt7621-dts: use valid vendor 'mediatek' instead of invalid 'mtk'

Vendor listed for mediatek in kernel vendor file 'vendor-prefixes.yaml'
contains 'mediatek' as a valid vendor string. Some nodes in the device
tree are using an invalid vendor string vfor 'mtk' instead. Fix all of
them in dts file. Update also ralink mt7621 related code to properly
match new strings. Even there are used in the device tree there are
some strings that are not referred anywhere but have been also updated
with new vendor name. These are 'mtk,mt7621-wdt', 'mtk,mt7621-nand',
'mtk,mt7621-mc', and 'mtk,mt7621-cpc'.

Signed-off-by: Sergio Paracuellos 
---
 arch/mips/ralink/mt7621.c  |  6 +++---
 drivers/staging/mt7621-dts/mt7621.dtsi | 12 ++--
 2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/arch/mips/ralink/mt7621.c b/arch/mips/ralink/mt7621.c
index ca0ac607b0f3..5d74fc1c96ac 100644
--- a/arch/mips/ralink/mt7621.c
+++ b/arch/mips/ralink/mt7621.c
@@ -112,8 +112,8 @@ phys_addr_t mips_cpc_default_phys_base(void)
 
 void __init ralink_of_remap(void)
 {
-   rt_sysc_membase = plat_of_remap_node("mtk,mt7621-sysc");
-   rt_memc_membase = plat_of_remap_node("mtk,mt7621-memc");
+   rt_sysc_membase = plat_of_remap_node("mediatek,mt7621-sysc");
+   rt_memc_membase = plat_of_remap_node("mediatek,mt7621-memc");
 
if (!rt_sysc_membase || !rt_memc_membase)
panic("Failed to remap core resources");
@@ -181,7 +181,7 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
 
if (n0 == MT7621_CHIP_NAME0 && n1 == MT7621_CHIP_NAME1) {
name = "MT7621";
-   soc_info->compatible = "mtk,mt7621-soc";
+   soc_info->compatible = "mediatek,mt7621-soc";
} else {
panic("mt7621: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
}
diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi 
b/drivers/staging/mt7621-dts/mt7621.dtsi
index 51d83cb3b4ee..ba113e5ced51 100644
--- a/drivers/staging/mt7621-dts/mt7621.dtsi
+++ b/drivers/staging/mt7621-dts/mt7621.dtsi
@@ -56,7 +56,7 @@ palmbus: palmbus@1E00 {
#size-cells = <1>;
 
sysc: sysc@0 {
-   compatible = "mtk,mt7621-sysc";
+   compatible = "mediatek,mt7621-sysc";
reg = <0x0 0x100>;
};
 
@@ -69,7 +69,7 @@ pll: pll {
};
 
wdt: wdt@100 {
-   compatible = "mtk,mt7621-wdt";
+   compatible = "mediatek,mt7621-wdt";
reg = <0x100 0x100>;
};
 
@@ -126,17 +126,17 @@ i2s: i2s@a00 {
};
 
memc: memc@5000 {
-   compatible = "mtk,mt7621-memc";
+   compatible = "mediatek,mt7621-memc";
reg = <0x5000 0x1000>;
};
 
cpc: cpc@1fbf {
-compatible = "mtk,mt7621-cpc";
+compatible = "mediatek,mt7621-cpc";
 reg = <0x1fbf 0x8000>;
};
 
mc: mc@1fbf8000 {
-   compatible = "mtk,mt7621-mc";
+   compatible = "mediatek,mt7621-mc";
reg = <0x1fbf8000 0x8000>;
};
 
@@ -369,7 +369,7 @@ timer {
nand: nand@1e003000 {
status = "disabled";
 
-   compatible = "mtk,mt7621-nand";
+   compatible = "mediatek,mt7621-nand";
bank-width = <2>;
reg = <0x1e003000 0x800
0x1e003800 0x800>;
-- 
2.25.1

[PATCH v5 4/6] staging: mt7621-dts: make use of new 'mt7621-clk'

Clocks for SoC mt7621 have been properly integrated so there is
no need to declare fixed clocks at all in the device tree. Remove
all of them, add new device tree nodes for mt7621-clk and update
the rest of the nodes to use them.

Signed-off-by: Sergio Paracuellos 
---
 drivers/staging/mt7621-dts/gbpc1.dts   | 11 
 drivers/staging/mt7621-dts/mt7621.dtsi | 73 --
 2 files changed, 34 insertions(+), 50 deletions(-)

diff --git a/drivers/staging/mt7621-dts/gbpc1.dts 
b/drivers/staging/mt7621-dts/gbpc1.dts
index a7c0d3115d72..7716d0efe524 100644
--- a/drivers/staging/mt7621-dts/gbpc1.dts
+++ b/drivers/staging/mt7621-dts/gbpc1.dts
@@ -100,17 +100,6 @@ partition@5 {
};
 };
 
- {
-   compatible = "fixed-clock";
-   /* This is normally 1/4 of cpuclock */
-   clock-frequency = <22500>;
-};
-
- {
-   compatible = "fixed-clock";
-   clock-frequency = <9>;
-};
-
  {
pinctrl-names = "default";
pinctrl-0 = <_pins>;
diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi 
b/drivers/staging/mt7621-dts/mt7621.dtsi
index 5b9d3bf82cb1..51d83cb3b4ee 100644
--- a/drivers/staging/mt7621-dts/mt7621.dtsi
+++ b/drivers/staging/mt7621-dts/mt7621.dtsi
@@ -1,5 +1,6 @@
 #include 
 #include 
+#include 
 
 / {
#address-cells = <1>;
@@ -27,27 +28,6 @@ aliases {
serial0 = 
};
 
-   cpuclock: cpuclock@0 {
-   #clock-cells = <0>;
-   compatible = "fixed-clock";
-
-   /* FIXME: there should be way to detect this */
-   clock-frequency = <88000>;
-   };
-
-   sysclock: sysclock@0 {
-   #clock-cells = <0>;
-   compatible = "fixed-clock";
-
-   /* This is normally 1/4 of cpuclock */
-   clock-frequency = <22000>;
-   };
-
-   mmc_clock: mmc_clock@0 {
-   #clock-cells = <0>;
-   compatible = "fixed-clock";
-   clock-frequency = <4800>;
-   };
 
mmc_fixed_3v3: fixedregulator@0 {
compatible = "regulator-fixed";
@@ -80,6 +60,14 @@ sysc: sysc@0 {
reg = <0x0 0x100>;
};
 
+   pll: pll {
+   compatible = "mediatek,mt7621-clk";
+   #clock-cells = <1>;
+   clock-output-names = "xtal", "cpu", "bus",
+"50m", "125m", "150m",
+"250m", "270m";
+   };
+
wdt: wdt@100 {
compatible = "mtk,mt7621-wdt";
reg = <0x100 0x100>;
@@ -101,8 +89,8 @@ i2c: i2c@900 {
compatible = "mediatek,mt7621-i2c";
reg = <0x900 0x100>;
 
-   clocks = <>;
-
+   clocks = < MT7621_CLK_I2C>;
+   clock-names = "i2c";
resets = < 16>;
reset-names = "i2c";
 
@@ -119,8 +107,8 @@ i2s: i2s@a00 {
compatible = "mediatek,mt7621-i2s";
reg = <0xa00 0x100>;
 
-   clocks = <>;
-
+   clocks = < MT7621_CLK_I2S>;
+   clock-names = "i2s";
resets = < 17>;
reset-names = "i2s";
 
@@ -156,8 +144,8 @@ uartlite: uartlite@c00 {
compatible = "ns16550a";
reg = <0xc00 0x100>;
 
-   clocks = <>;
-   clock-frequency = <5000>;
+   clocks = < MT7621_CLK_UART1>;
+   clock-names = "uart1";
 
interrupt-parent = <>;
interrupts = ;
@@ -173,7 +161,8 @@ spi0: spi@b00 {
compatible = "ralink,mt7621-spi";
reg = <0xb00 0x100>;
 
-   clocks = <>;
+   clocks = < MT7621_CLK_SPI>;
+   clock-names = "spi";
 
resets = < 18>;
reset-names = "spi";
@@ -189,6 +178,8 @@ gdma: gdma@2800 {
compatible = "ralink,rt3883-gdma";
reg = <0x2800 0x800>;
 
+   clocks = < MT7621_CLK_GDMA>;
+   cloc

[PATCH v5 0/6] MIPS: ralink: add CPU clock detection and clock driver for MT7621

e benefits of doing in this way. I am totally ok to have all
 the clocks registered at early stage since from other drivers perspective
 we only really need to enable gates. So, I prefer to have them in that
 way if it is not a real problem, of course.

Changes in v4:
 - Add Acked-by from Rob Herring for binding headers (PATCH 1/6).
 - Convert bindings to not use syscon phandle and declare clock as
   a child of the syscon node. Update device tree and binding doc
   accordly.
 - Make use of 'syscon_node_to_regmap' in driver code instead of
   get this using the phandle function.
 - Properly unregister clocks for the error path of the function
   'mt7621_clk_init'.
 - Include ARRAY_SIZE of fixed clocks in the 'count' to kzalloc
   of 'clk_data'.
 - Add new patch changing invalid vendor 'mtk' in favour of 'mediatek'
   which is the one listed in 'vendor-prefixes.yaml'. Update mt7621 code
   accordly. I have added this patch inside this series because clk
   binding is referring syscon node and the string for that node was
   with not listed vendor. Hence update and have all of this correct
   in the same series.

Changes in v3:
 - Fix compilation warnings reported by kernel test robot because of
   ignoring return values of 'of_clk_hw_register' in functions
   'mt7621_register_top_clocks' and 'mt7621_gate_ops_init'.
 - Fix dts file and binding documentation 'clock-output-names'.

Changes in v2:
 - Remove the following patches:
   * dt: bindings: add mt7621-pll device tree binding documentation.
   * MIPS: ralink: add clock device providing cpu/ahb/apb clock for mt7621.
 - Move all relevant clock code to 'drivers/clk/ralink/clk-mt7621.c' and
   unify there previous 'mt7621-pll' and 'mt7621-clk' into a unique driver
   and binding 'mt7621-clk'.
 - Driver is not a platform driver anymore and now make use of 'CLK_OF_DECLARE'
   because we need clocks available in 'plat_time_init' before setting up
   the timer for the GIC.
 - Use new fixed clocks as parents for different gates and deriving from 'xtal'
   using frequencies in[1].
 - Adapt dts file and bindings header and documentation for new changes.
 - Change MAINTAINERS file to only contains clk-mt7621.c code and
   mediatek,mt7621-clk.yaml file.

[0]: https://www.lkml.org/lkml/2019/7/23/1044
[1]: 
https://github.com/981213/linux/commit/2eca1f045e4c3db18c941135464c0d7422ad8133

Sergio Paracuellos (6):
  dt-bindings: clock: add dt binding header for mt7621 clocks
  dt: bindings: add mt7621-clk device tree binding documentation
  clk: ralink: add clock driver for mt7621 SoC
  staging: mt7621-dts: make use of new 'mt7621-clk'
  staging: mt7621-dts: use valid vendor 'mediatek' instead of invalid
'mtk'
  MAINTAINERS: add MT7621 CLOCK maintainer

 .../bindings/clock/mediatek,mt7621-clk.yaml   |  52 +++
 MAINTAINERS   |   6 +
 arch/mips/ralink/mt7621.c |   6 +-
 drivers/clk/Kconfig   |   1 +
 drivers/clk/Makefile  |   1 +
 drivers/clk/ralink/Kconfig|  14 +
 drivers/clk/ralink/Makefile   |   2 +
 drivers/clk/ralink/clk-mt7621.c   | 411 ++
 drivers/staging/mt7621-dts/gbpc1.dts  |  11 -
 drivers/staging/mt7621-dts/mt7621.dtsi|  85 ++--
 include/dt-bindings/clock/mt7621-clk.h|  41 ++
 11 files changed, 571 insertions(+), 59 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
 create mode 100644 drivers/clk/ralink/Kconfig
 create mode 100644 drivers/clk/ralink/Makefile
 create mode 100644 drivers/clk/ralink/clk-mt7621.c
 create mode 100644 include/dt-bindings/clock/mt7621-clk.h

-- 
2.25.1

[PATCH v5 3/6] clk: ralink: add clock driver for mt7621 SoC

The documentation for this SOC only talks about two
registers regarding to the clocks:
* SYSC_REG_CPLL_CLKCFG0 - provides some information about
boostrapped refclock. PLL and dividers used for CPU and some
sort of BUS.
* SYSC_REG_CPLL_CLKCFG1 - a banch of gates to enable/disable
clocks for all or some ip cores.

Looking into driver code, and some openWRT patched there are
another frequencies which are used in some drivers (uart, sd...).
According to all of this information the clock plan for this
SoC is set as follows:
- Main top clock "xtal" from where all the rest of the world is
derived.
- CPU clock "cpu" derived from "xtal" frequencies and a bunch of
register reads and predividers.
- BUS clock "bus" derived from "cpu" and with (cpu / 4) MHz.
- Fixed clocks from "xtal":
* "50m": 50 MHz.
* "125m": 125 MHz.
* "150m": 150 MHz.
* "250m": 250 MHz.
* "270m": 270 MHz.

We also have a buch of gate clocks with their parents:
  * "hsdma": "150m"
  * "fe": "250m"
  * "sp_divtx": "270m"
  * "timer": "50m"
  * "pcm": "270m"
  * "pio": "50m"
  * "gdma": "bus"
  * "nand": "125m"
  * "i2c": "50m"
  * "i2s": "270m"
  * "spi": "bus"
  * "uart1": "50m"
  * "uart2": "50m"
  * "uart3": "50m"
  * "eth": "50m"
  * "pcie0": "125m"
  * "pcie1": "125m"
  * "pcie2": "125m"
  * "crypto": "250m"
  * "shxc": "50m"

With this information the clk driver will provide clock and gates
functionality from a a set of hardcoded clocks allowing to define
a nice device tree without fixed clocks.

Signed-off-by: Sergio Paracuellos 
---
 drivers/clk/Kconfig |   1 +
 drivers/clk/Makefile|   1 +
 drivers/clk/ralink/Kconfig  |  14 ++
 drivers/clk/ralink/Makefile |   2 +
 drivers/clk/ralink/clk-mt7621.c | 411 
 5 files changed, 429 insertions(+)
 create mode 100644 drivers/clk/ralink/Kconfig
 create mode 100644 drivers/clk/ralink/Makefile
 create mode 100644 drivers/clk/ralink/clk-mt7621.c

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 85856cff506c..7c6ad73c985c 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -381,6 +381,7 @@ source "drivers/clk/mediatek/Kconfig"
 source "drivers/clk/meson/Kconfig"
 source "drivers/clk/mvebu/Kconfig"
 source "drivers/clk/qcom/Kconfig"
+source "drivers/clk/ralink/Kconfig"
 source "drivers/clk/renesas/Kconfig"
 source "drivers/clk/rockchip/Kconfig"
 source "drivers/clk/samsung/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index dbdc590e7de3..29b957d83c4e 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -101,6 +101,7 @@ obj-$(CONFIG_COMMON_CLK_NXP)+= nxp/
 obj-$(CONFIG_MACH_PISTACHIO)   += pistachio/
 obj-$(CONFIG_COMMON_CLK_PXA)   += pxa/
 obj-$(CONFIG_COMMON_CLK_QCOM)  += qcom/
+obj-y  += ralink/
 obj-y  += renesas/
 obj-$(CONFIG_ARCH_ROCKCHIP)+= rockchip/
 obj-$(CONFIG_COMMON_CLK_SAMSUNG)   += samsung/
diff --git a/drivers/clk/ralink/Kconfig b/drivers/clk/ralink/Kconfig
new file mode 100644
index ..f1de548ed781
--- /dev/null
+++ b/drivers/clk/ralink/Kconfig
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# MediaTek Mt7621 Clock Driver
+#
+menu "Clock driver for Mediatek mt7621 SoC"
+   depends on SOC_MT7621
+
+config CLK_MT7621
+   bool "Clock driver for MediaTek MT7621"
+   depends on SOC_MT7621
+   default SOC_MT7621
+   help
+ This driver supports MediaTek MT7621 basic clocks.
+endmenu
diff --git a/drivers/clk/ralink/Makefile b/drivers/clk/ralink/Makefile
new file mode 100644
index ..cf6f9216379d
--- /dev/null
+++ b/drivers/clk/ralink/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_CLK_MT7621) += clk-mt7621.o
diff --git a/drivers/clk/ralink/clk-mt7621.c b/drivers/clk/ralink/clk-mt7621.c
new file mode 100644
index ..52aa98318abf
--- /dev/null
+++ b/drivers/clk/ralink/clk-mt7621.c
@@ -0,0 +1,411 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Mediatek MT7621 Clock Driver
+ * Author: Sergio Paracuellos 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* Configuration registers */
+#define SYSC_REG_SYSTEM_CONFIG0 0x10
+#define SYSC_REG_SYSTEM_CONFIG1 0x14
+#define SYSC_REG_CLKCFG0

[PATCH v5 2/6] dt: bindings: add mt7621-clk device tree binding documentation

Adds device tree binding documentation for clocks in the
MT7621 SOC.

Signed-off-by: Sergio Paracuellos 
---
 .../bindings/clock/mediatek,mt7621-clk.yaml   | 52 +++
 1 file changed, 52 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml

diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml 
b/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
new file mode 100644
index ..f58d01bdc82c
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/mediatek,mt7621-clk.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MT7621 Clock Device Tree Bindings
+
+maintainers:
+  - Sergio Paracuellos 
+
+description: |
+  The MT7621 has a PLL controller from where the cpu clock is provided
+  as well as derived clocks for the bus and the peripherals. It also
+  can gate SoC device clocks.
+
+  Each clock is assigned an identifier and client nodes use this identifier
+  to specify the clock which they consume.
+
+  All these identifiers could be found in:
+  [1]: .
+
+properties:
+  compatible:
+const: mediatek,mt7621-clk
+
+  "#clock-cells":
+description:
+  The first cell indicates the clock number, see [1] for available
+  clocks.
+const: 1
+
+  clock-output-names:
+maxItems: 8
+
+required:
+  - compatible
+  - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+#include 
+
+pll {
+  compatible = "mediatek,mt7621-clk";
+  #clock-cells = <1>;
+  clock-output-names = "xtal", "cpu", "bus",
+   "50m", "125m", "150m",
+   "250m", "270m";
+};
-- 
2.25.1

[PATCH v5 1/6] dt-bindings: clock: add dt binding header for mt7621 clocks

Adds dt binding header for 'mediatek,mt7621-clk' clocks.

Acked-by: Rob Herring 
Signed-off-by: Sergio Paracuellos 
---
 include/dt-bindings/clock/mt7621-clk.h | 41 ++
 1 file changed, 41 insertions(+)
 create mode 100644 include/dt-bindings/clock/mt7621-clk.h

diff --git a/include/dt-bindings/clock/mt7621-clk.h 
b/include/dt-bindings/clock/mt7621-clk.h
new file mode 100644
index ..1422badcf9de
--- /dev/null
+++ b/include/dt-bindings/clock/mt7621-clk.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Author: Sergio Paracuellos 
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT7621_H
+#define _DT_BINDINGS_CLK_MT7621_H
+
+#define MT7621_CLK_XTAL0
+#define MT7621_CLK_CPU 1
+#define MT7621_CLK_BUS 2
+#define MT7621_CLK_50M 3
+#define MT7621_CLK_125M4
+#define MT7621_CLK_150M5
+#define MT7621_CLK_250M6
+#define MT7621_CLK_270M7
+
+#define MT7621_CLK_HSDMA   8
+#define MT7621_CLK_FE  9
+#define MT7621_CLK_SP_DIVTX10
+#define MT7621_CLK_TIMER   11
+#define MT7621_CLK_PCM 12
+#define MT7621_CLK_PIO 13
+#define MT7621_CLK_GDMA14
+#define MT7621_CLK_NAND15
+#define MT7621_CLK_I2C 16
+#define MT7621_CLK_I2S 17
+#define MT7621_CLK_SPI 18
+#define MT7621_CLK_UART1   19
+#define MT7621_CLK_UART2   20
+#define MT7621_CLK_UART3   21
+#define MT7621_CLK_ETH 22
+#define MT7621_CLK_PCIE0   23
+#define MT7621_CLK_PCIE1   24
+#define MT7621_CLK_PCIE2   25
+#define MT7621_CLK_CRYPTO  26
+#define MT7621_CLK_SHXC27
+
+#define MT7621_CLK_MAX 28
+
+#endif /* _DT_BINDINGS_CLK_MT7621_H */
-- 
2.25.1

Re: [PATCH v4 2/6] dt: bindings: add mt7621-clk device tree binding documentation

Hi Rob,

On Thu, Dec 17, 2020 at 4:05 PM Rob Herring  wrote:
>
> On Thu, Dec 17, 2020 at 2:58 AM Stephen Boyd  wrote:
> >
> > Quoting Sergio Paracuellos (2020-11-22 01:55:52)
> > > Adds device tree binding documentation for clocks in the
> > > MT7621 SOC.
> > >
> > > Signed-off-by: Sergio Paracuellos 
> > > ---
> > >  .../bindings/clock/mediatek,mt7621-clk.yaml   | 67 +++
> > >  1 file changed, 67 insertions(+)
> > >  create mode 100644 
> > > Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
> > >
> >
> > Rob?
>
> Send to the DT list please.

Sorry, there was a typo 'evicet...@vger.kernel.org' in CC list.

>
> But I agree with Stephen's comment. Either make the syscon complete
> (fully describe the h/w, not just what you need ATM) to show the need
> for child nodes or get rid of the child nodes.

Got it. Will try to do something better and send v5.

>
> Rob

Thanks,
Sergio Paracuellos

Re: [PATCH v4 2/6] dt: bindings: add mt7621-clk device tree binding documentation

On Thu, Dec 17, 2020 at 11:50 AM Stephen Boyd  wrote:
>
> Quoting Sergio Paracuellos (2020-12-17 02:38:37)
> > On Thu, Dec 17, 2020 at 11:32 AM Stephen Boyd  wrote:
> > >
> > > Quoting Sergio Paracuellos (2020-12-17 02:14:10)
> > > > node is to use architecture operations in
> > > > 'arch/mips/include/asm/mach-ralink/ralink_regs.h'
> > > > instead of getting a phandle using the regmap is being currently used...
> > >
> > > Can that be done with
> > >
> > > CLK_OF_DECLARE_DRIVER("mediatek,mt7621-sysc", my_timer_clk_init)
> > >
> > > ? Is the syscon used anywhere besides by the clk driver?
> >
> > Yes, for example all the gates use them to access SYSC_REG_CLKCFG1 in
> > all of their 'mt7621_gate_ops' and also in all 'recalc_rate' functions
> > where SYSC_REG_SYSTEM_CONFIG0, is readed.
>
> That sounds like it's only used by the clk provider/driver? Any other
> code uses the syscon?

The only child node for the syscon for this platform is the clock
driver now, I introduced it in this series, so no other driver is
using this syscon now. All of them use global arch operations in
'arch/mips/include/asm/mach-ralink/ralink_regs.h'.

Re: [PATCH v4 2/6] dt: bindings: add mt7621-clk device tree binding documentation

On Thu, Dec 17, 2020 at 11:32 AM Stephen Boyd  wrote:
>
> Quoting Sergio Paracuellos (2020-12-17 02:14:10)
> > On Thu, Dec 17, 2020 at 11:07 AM Stephen Boyd  wrote:
> > >
> > > Quoting Sergio Paracuellos (2020-12-17 02:01:39)
> > > >
> > > > On Thu, Dec 17, 2020 at 9:58 AM Stephen Boyd  wrote:
> > > > >
> > > > > Quoting Sergio Paracuellos (2020-11-22 01:55:52)
> > > > >
> > > > > > diff --git 
> > > > > > a/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml 
> > > > > > b/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
> > > > > > new file mode 100644
> > > > > > index ..6aca4c1a4a46
> > > > > > --- /dev/null
> > > > > > +++ 
> > > > > > b/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
> > > > >
> > > > > > +  compatible = "mediatek,mt7621-sysc", "syscon";
> > > > > > +  reg = <0x0 0x100>;
> > > > > > +
> > > > > > +  pll {
> > > > >
> > > > > clock-controller? Why can't the parent device be the clk provider and
> > > > > have #clock-cells?
> > > > >
> > > >
> > > > I don't get your point, sorry. Can you please explain this a bit more
> > > > or point to me to an example to understand the real meaning of this?
> > >
> > > It looks like this is a made up child node of syscon so that a driver
> > > can probe in the kernel. It would be more DT friendly to create a
> > > platform device from the parent node's driver, or just register the clks
> > > with the framework directly in that driver.
> >
> > We cannot create a platform device because we need clocks available in
> > 'plat_time_init' before setting up the timer for the GIC.
> > The only way I see to avoid this syscon and having this as a child
> > node is to use architecture operations in
> > 'arch/mips/include/asm/mach-ralink/ralink_regs.h'
> > instead of getting a phandle using the regmap is being currently used...
>
> Can that be done with
>
> CLK_OF_DECLARE_DRIVER("mediatek,mt7621-sysc", my_timer_clk_init)
>
> ? Is the syscon used anywhere besides by the clk driver?

Yes, for example all the gates use them to access SYSC_REG_CLKCFG1 in
all of their 'mt7621_gate_ops' and also in all 'recalc_rate' functions
where SYSC_REG_SYSTEM_CONFIG0, is readed.

Re: [PATCH v4 3/6] clk: ralink: add clock driver for mt7621 SoC

On Thu, Dec 17, 2020 at 11:12 AM Stephen Boyd  wrote:
>
> Quoting Sergio Paracuellos (2020-12-17 01:54:18)
> >
> > On Thu, Dec 17, 2020 at 10:09 AM Stephen Boyd  wrote:
> > >
> > > Quoting Sergio Paracuellos (2020-11-22 01:55:53)
> > > > diff --git a/drivers/clk/ralink/Makefile b/drivers/clk/ralink/Makefile
> > > > new file mode 100644
> > > > index ..cf6f9216379d
> > > > --- /dev/null
> > > > +++ b/drivers/clk/ralink/Makefile
> > > > @@ -0,0 +1,2 @@
> > > > +# SPDX-License-Identifier: GPL-2.0
> > > > +obj-$(CONFIG_CLK_MT7621) += clk-mt7621.o
> > > > diff --git a/drivers/clk/ralink/clk-mt7621.c 
> > > > b/drivers/clk/ralink/clk-mt7621.c
> > > > new file mode 100644
> > > > index ..4e929f13fe7c
> > > > --- /dev/null
> > > > +++ b/drivers/clk/ralink/clk-mt7621.c
> > > > @@ -0,0 +1,435 @@
> > > > +// SPDX-License-Identifier: GPL-2.0
> > > > +/*
> > > > + * Mediatek MT7621 Clock Driver
> > > > + * Author: Sergio Paracuellos 
> > > > + */
> > > > +
> > > > +#include 
> > > > +#include 
> > > > +#include 
> > > > +#include 
> > > > +#include 
> > > > +#include 
> > > > +#include 
> > >
> > > Is it possible to drop this include? Doing so would make this portable
> > > and compilable on more architectures so us cross compilers can check
> > > build stuff and make changes easily.
> >
> > No, this is not possible. This old arch makes some global functions
> > there to properly access different registers in the palmbus. It is not
> > also well documented so it is really difficult to make something
> > better with this.
> > This is needed to use 'rt_memc_r32'
> > (arch/mips/include/asm/mach-ralink/ralink_regs.h) for reading
> > MEMC_REG_CPU_PLL.
> >
> > This is a not documented register and is not in the syscon related
> > part and we need it to derive the clock frequency for the XTAL clock.
>
> Ok.
>
> > > > +static int mt7621_gate_ops_init(struct device_node *np,
> > > > +struct mt7621_gate *sclk)
> > > > +{
> > > > +   struct clk_init_data init = {
> > > > +   .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > >
> > > Why ignore unused? Are they CLK_IS_CRITICAL? Can they be enabled at
> > > driver probe instead of here? Or left out of the kernel entirely if they
> > > shouldn't be turned off?
> >
> > Because all the platform drivers are not changed to use this gates yet
> > and all gates are enabled by default (related registers are set to all
> > ones),  kernel disables all the stuff because they are not being
> > referenced, but yes, you are right, I think I can call
> > clk_prepare_enable for all of them at init time and avoid this
> > 'CLK_IGNORE_UNUSED' flag to don't break anything of the current other
> > upstream code.
>
> Does something crash if they're turned off? We have CLK_IS_CRITICAL for
> that. The CLK_IGNORE_UNUSED flag is sort of deprecated now.

Well, as drivers are not getting into account gates and not referenced
real hw bits are disabled by kernel because nobody requested them so
for example my uart gets down and cannot really see anything :). I
think call to 'clk_prepare_enable' should be enough since by default
all of them are setting up in registers, so call that will also
reference them...

>
> > > > +
> > > > +#define CLK_BASE(_name, _parent, _recalc) {
> > > > \
> > > > +   .init = &(struct clk_init_data) {   
> > > > \
> > > > +   .name = _name,  
> > > > \
> > > > +   .ops = &(const struct clk_ops) {
> > > > \
> > > > +   .recalc_rate = _recalc, 
> > > > \
> > > > +   },  
> > > > \
> > > > +   .parent_names = (const char *const[]) { _parent },  
> > > > \
> > >
> > > Please use clk_parent_data instead
> >
> > parent can also be NULL here and num_parents zero, but I will search
> > what do you really mean with this 'clk_parent_data' :).
>
> Heh, 'git grep clk_parent_data -- drivers/clk/' sh

Re: [PATCH v4 2/6] dt: bindings: add mt7621-clk device tree binding documentation

On Thu, Dec 17, 2020 at 11:07 AM Stephen Boyd  wrote:
>
> Quoting Sergio Paracuellos (2020-12-17 02:01:39)
> >
> > On Thu, Dec 17, 2020 at 9:58 AM Stephen Boyd  wrote:
> > >
> > > Quoting Sergio Paracuellos (2020-11-22 01:55:52)
> > >
> > > > diff --git 
> > > > a/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml 
> > > > b/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
> > > > new file mode 100644
> > > > index ..6aca4c1a4a46
> > > > --- /dev/null
> > > > +++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
> > >
> > > > +  compatible = "mediatek,mt7621-sysc", "syscon";
> > > > +  reg = <0x0 0x100>;
> > > > +
> > > > +  pll {
> > >
> > > clock-controller? Why can't the parent device be the clk provider and
> > > have #clock-cells?
> > >
> >
> > I don't get your point, sorry. Can you please explain this a bit more
> > or point to me to an example to understand the real meaning of this?
>
> It looks like this is a made up child node of syscon so that a driver
> can probe in the kernel. It would be more DT friendly to create a
> platform device from the parent node's driver, or just register the clks
> with the framework directly in that driver.

We cannot create a platform device because we need clocks available in
'plat_time_init' before setting up the timer for the GIC.
The only way I see to avoid this syscon and having this as a child
node is to use architecture operations in
'arch/mips/include/asm/mach-ralink/ralink_regs.h'
instead of getting a phandle using the regmap is being currently used...

Re: [PATCH v4 2/6] dt: bindings: add mt7621-clk device tree binding documentation

Hi Stephen,

Thanks for the review!

On Thu, Dec 17, 2020 at 9:58 AM Stephen Boyd  wrote:
>
> Quoting Sergio Paracuellos (2020-11-22 01:55:52)
> > Adds device tree binding documentation for clocks in the
> > MT7621 SOC.
> >
> > Signed-off-by: Sergio Paracuellos 
> > ---
> >  .../bindings/clock/mediatek,mt7621-clk.yaml   | 67 +++
> >  1 file changed, 67 insertions(+)
> >  create mode 100644 
> > Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
> >
>
> Rob?
>
> > diff --git 
> > a/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml 
> > b/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
> > new file mode 100644
> > index ..6aca4c1a4a46
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
> > @@ -0,0 +1,67 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/clock/mediatek,mt7621-clk.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: MT7621 Clock Device Tree Bindings
> > +
> > +maintainers:
> > +  - Sergio Paracuellos 
> > +
> > +description: |
> > +  The MT7621 has a PLL controller from where the cpu clock is provided
> > +  as well as derived clocks for the bus and the peripherals. It also
> > +  can gate SoC device clocks.
> > +
> > +  Each clock is assigned an identifier and client nodes use this identifier
> > +  to specify the clock which they consume.
> > +
> > +  All these identifiers could be found in:
> > +  [1]: .
> > +
> > +  The mt7621 clock node should be the child of a syscon node with the
> > +  required property:
> > +
> > +  - compatible: Should be one of the following:
> > +"mediatek,mt7621-sysc", "syscon"
> > +
> > +  Refer to the bindings described in
> > +  Documentation/devicetree/bindings/mfd/syscon.yaml
> > +
> > +properties:
> > +  compatible:
> > +const: mediatek,mt7621-clk
> > +
> > +  "#clock-cells":
> > +description:
> > +  The first cell indicates the clock gate number, see [1] for available
> > +  clocks.
> > +const: 1
> > +
> > +  clock-output-names:
> > +maxItems: 8
> > +
> > +required:
> > +  - compatible
> > +  - '#clock-cells'
> > +  - clock-output-names
>
> Why is clock-output-names required? Hopefully it is not required.

Not really, can be removed from here.

>
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +#include 
> > +
> > +sysc: sysc@0 {
>
> syscon@0? I don't think sysc is a standard node name.

Ok, I will change this into syscon@0 in both bindings and device tree file.

>
> > +  compatible = "mediatek,mt7621-sysc", "syscon";
> > +  reg = <0x0 0x100>;
> > +
> > +  pll {
>
> clock-controller? Why can't the parent device be the clk provider and
> have #clock-cells?
>

I don't get your point, sorry. Can you please explain this a bit more
or point to me to an example to understand the real meaning of this?


> > +compatible = "mediatek,mt7621-clk";
> > +#clock-cells = <1>;
> > +clock-output-names = "xtal", "cpu", "bus",
> > + "50m", "125m", "150m",
> > + "250m", "270m";
> > +  };
> > +};

Best regards,
Sergio Paracuellos

Re: [PATCH v4 3/6] clk: ralink: add clock driver for mt7621 SoC

Hi Stephen,

Thanks for the review.

On Thu, Dec 17, 2020 at 10:09 AM Stephen Boyd  wrote:
>
> Quoting Sergio Paracuellos (2020-11-22 01:55:53)
> > The documentation for this SOC only talks about two
> > registers regarding to the clocks:
> > * SYSC_REG_CPLL_CLKCFG0 - provides some information about
> > boostrapped refclock. PLL and dividers used for CPU and some
> > sort of BUS.
> > * SYSC_REG_CPLL_CLKCFG1 - a banch of gates to enable/disable
> > clocks for all or some ip cores.
> >
> > Looking into driver code, and some openWRT patched there are
> > another frequences which are used in some drivers (uart, sd...).
>
> s/frequences/frequencies/

Ok!

>
> > According to all of this information the clock plan for this
> > SoC is set as follows:
> > - Main top clock "xtal" from where all the rest of the world is
> > derived.
> > - CPU clock "cpu" derived from "xtal" frequencies and a bunch of
> > register reads and predividers.
> > - BUS clock "bus" derived from "cpu" and with (cpu / 4) MHz.
> > - Fixed clocks from "xtal":
> > * "50m": 50 MHz.
> > * "125m": 125 MHz.
> > * "150m": 150 MHz.
> > * "250m": 250 MHz.
> > * "270m": 270 MHz.
> >
> > We also have a buch of gate clocks with their parents:
> >   * "hsdma": "150m"
> >   * "fe": "250m"
> >   * "sp_divtx": "270m"
> >   * "timer": "50m"
> >   * "pcm": "270m"
> >   * "pio": "50m"
> >   * "gdma": "bus"
> >   * "nand": "125m"
> >   * "i2c": "50m"
> >   * "i2s": "270m"
> >   * "spi": "bus"
> >   * "uart1": "50m"
> >   * "uart2": "50m"
> >   * "uart3": "50m"
> >   * "eth": "50m"
> >   * "pcie0": "125m"
> >   * "pcie1": "125m"
> >   * "pcie2": "125m"
> >   * "crypto": "250m"
> >   * "shxc": "50m"
> >
> > With this information the clk driver will provide clock and gates
> > functionality from a a set of hardcoded clocks allowing to define
> > a nice device tree without fixed clocks.
> >
> > Signed-off-by: Sergio Paracuellos 
> > ---
> >  drivers/clk/Kconfig |   1 +
> >  drivers/clk/Makefile|   1 +
> >  drivers/clk/ralink/Kconfig  |  14 +
> >  drivers/clk/ralink/Makefile |   2 +
> >  drivers/clk/ralink/clk-mt7621.c | 435 
> >  5 files changed, 453 insertions(+)
> >  create mode 100644 drivers/clk/ralink/Kconfig
> >  create mode 100644 drivers/clk/ralink/Makefile
> >  create mode 100644 drivers/clk/ralink/clk-mt7621.c
> >
> > diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> > index c715d4681a0b..5f94c4329033 100644
> > --- a/drivers/clk/Kconfig
> > +++ b/drivers/clk/Kconfig
> > @@ -372,6 +372,7 @@ source "drivers/clk/mediatek/Kconfig"
> >  source "drivers/clk/meson/Kconfig"
> >  source "drivers/clk/mvebu/Kconfig"
> >  source "drivers/clk/qcom/Kconfig"
> > +source "drivers/clk/ralink/Kconfig"
> >  source "drivers/clk/renesas/Kconfig"
> >  source "drivers/clk/rockchip/Kconfig"
> >  source "drivers/clk/samsung/Kconfig"
> > diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
> > index da8fcf147eb1..6578e167b047 100644
> > --- a/drivers/clk/Makefile
> > +++ b/drivers/clk/Makefile
> > @@ -100,6 +100,7 @@ obj-$(CONFIG_COMMON_CLK_NXP)+= nxp/
> >  obj-$(CONFIG_MACH_PISTACHIO)   += pistachio/
> >  obj-$(CONFIG_COMMON_CLK_PXA)   += pxa/
> >  obj-$(CONFIG_COMMON_CLK_QCOM)  += qcom/
> > +obj-y  += ralink/
> >  obj-y  += renesas/
> >  obj-$(CONFIG_ARCH_ROCKCHIP)+= rockchip/
> >  obj-$(CONFIG_COMMON_CLK_SAMSUNG)   += samsung/
>
> Thanks for keeping it sorted!

It was so clean sorted so I just followed the style there.

>
> > diff --git a/drivers/clk/ralink/Kconfig b/drivers/clk/ralink/Kconfig
> > new file mode 100644
> > index ..7e8697327e0c
> > --- /dev/null
> > +++ b/drivers/clk/ralink/Kconfig
> > @@ -0,0

Re: drivers/pinctrl/ralink/pinctrl-rt2880.c:365:12: warning: no previous prototype for 'rt2880_pinmux_init'

Hi,

On Thu, Dec 17, 2020 at 3:17 AM kernel test robot  wrote:
>
> Hi Sergio,
>
> First bad commit (maybe != root cause):
>
> tree:   https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 
> master
> head:   accefff5b547a9a1d959c7e76ad539bf2480e78b
> commit: 518b466a21ad7fa1e338fa4ed9d180ef439d3bc0 pinctrl: ralink: add a 
> pinctrl driver for the rt2880 family
> date:   9 days ago
> config: mips-randconfig-r025-20201217 (attached as .config)
> compiler: mipsel-linux-gcc (GCC) 9.3.0
> reproduce (this is a W=1 build):
> wget 
> https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O 
> ~/bin/make.cross
> chmod +x ~/bin/make.cross
> # 
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=518b466a21ad7fa1e338fa4ed9d180ef439d3bc0
> git remote add linus 
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
> git fetch --no-tags linus master
> git checkout 518b466a21ad7fa1e338fa4ed9d180ef439d3bc0
> # save the attached .config to linux build tree
> COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross 
> ARCH=mips
>
> If you fix the issue, kindly add following tag as appropriate
> Reported-by: kernel test robot 
>
> All warnings (new ones prefixed by >>):
>
> >> drivers/pinctrl/ralink/pinctrl-rt2880.c:365:12: warning: no previous 
> >> prototype for 'rt2880_pinmux_init' [-Wmissing-prototypes]
>  365 | int __init rt2880_pinmux_init(void)
>  |^~
>
>
> vim +/rt2880_pinmux_init +365 drivers/pinctrl/ralink/pinctrl-rt2880.c
>
> 0317d60de869786 drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c John Crispin  
>  2018-03-15  364
> 1d2d116a93f0e9b drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c Sergio 
> Paracuellos 2018-07-09 @365  int __init rt2880_pinmux_init(void)
> 1d2d116a93f0e9b drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c Sergio 
> Paracuellos 2018-07-09  366  {
> 1d2d116a93f0e9b drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c Sergio 
> Paracuellos 2018-07-09  367  return 
> platform_driver_register(_pinmux_driver);
> 1d2d116a93f0e9b drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c Sergio 
> Paracuellos 2018-07-09  368  }
> 1d2d116a93f0e9b drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c Sergio 
> Paracuellos 2018-07-09  369

Yes, there is no such prototype for this global. This should be
declared 'static' instead as it is only used from this driver code
using 'core_initcall_sync'.
Will send a patch with this change. CC'ed Linus because this driver is
in his subsystem now.

>
> :: The code at line 365 was first introduced by commit
> :: 1d2d116a93f0e9bf0bca72da76a96edef8a1d36d Revert "staging: 
> mt7621-pinctrl: replace core_initcall_sync with builtin_platform_driver"

Not really, it was there from the very beginning but I made a change
to try to use this in a later stage in the boot process without
success. Thus, this commit is the revert for that one.

>
> :::::: TO: Sergio Paracuellos 
> :: CC: Greg Kroah-Hartman 
>
> ---
> 0-DAY CI Kernel Test Service, Intel Corporation
> https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org

Best regards,
Sergio Paracuellos

Re: [PATCH v4 0/6] MIPS: ralink: add CPU clock detection and clock driver for MT7621

2020-12-09 Thread Sergio Paracuellos

Hi all,

On Sun, Nov 22, 2020 at 10:55 AM Sergio Paracuellos
 wrote:
>
> This patchset ports CPU clock detection for MT7621 from OpenWrt
> and adds a complete clock plan for the mt7621 SOC.
>
> The documentation for this SOC only talks about two registers
> regarding to the clocks:
> * SYSC_REG_CPLL_CLKCFG0 - provides some information about boostrapped
> refclock. PLL and dividers used for CPU and some sort of BUS (AHB?).
> * SYSC_REG_CPLL_CLKCFG1 - a banch of gates to enable/disable clocks for
> all or some ip cores.
>
> No documentation about a probably existent set of dividers for each ip
> core is included in the datasheets. So we cannot make anything better,
> AFAICT.
>
> Looking into driver code, and some openWRT patched there are
> another frequences which are used in some drivers (uart, sd...).
> According to all of this information the clock plan for this
> SoC is set as follows:
>  - Main top clock "xtal" from where all the rest of the world is
>derived.
>  - CPU clock "cpu" derived from "xtal" frequencies and a bunch of
>register reads and predividers.
>  - BUS clock "bus" derived from "cpu" and with (cpu / 4) MHz.
>  - Fixed clocks from "xtal":
> * "50m": 50 MHz.
> * "125m": 125 MHz.
> * "150m": 150 MHz.
> * "250m": 250 MHz.
> * "270m": 270 MHz.
>
> We also have a buch of gate clocks with their parents:
>  - "hsdma": "150m"
>  - "fe": "250m"
>  - "sp_divtx": "270m"
>  - "timer": "50m"
>  - "pcm": "270m"
>  - "pio": "50m"
>  - "gdma": "bus"
>  - "nand": "125m"
>  - "i2c": "50m"
>  - "i2s": "270m"
>  - "spi": "bus"
>  - "uart1": "50m"
>  - "uart2": "50m"
>  - "uart3": "50m"
>  - "eth": "50m"
>  - "pcie0": "125m"
>  - "pcie1": "125m"
>  - "pcie2": "125m"
>  - "crypto": "250m"
>  - "shxc": "50m"
>
> There was a previous attempt of doing this here[0] but the author
> (Chuanhong Guo) did not wanted to make assumptions of a clock plan
> for the platform that time. It seems that now he has a better idea of
> how the clocks are dispossed for this SoC so he share code[1] where
> some frequencies and clock parents for the gates are coded from a
> real mediatek private clock plan.
>
> I do really want this to be upstreamed so according to the comments
> in previous attempt[0] from Oleksij Rempel and the frequencies in
> code[1] I have tried to do this by myself.
>
> All of this patches have been tested in a GNUBee PC1 resulting in a
> working platform.


>
> Changes in v4:
>  - Add Acked-by from Rob Herring for binding headers (PATCH 1/6).
>  - Convert bindings to not use syscon phandle and declare clock as
>a child of the syscon node. Update device tree and binding doc
>accordly.
>  - Make use of 'syscon_node_to_regmap' in driver code instead of
>get this using the phandle function.
>  - Properly unregister clocks for the error path of the function
>'mt7621_clk_init'.
>  - Include ARRAY_SIZE of fixed clocks in the 'count' to kzalloc
>of 'clk_data'.
>  - Add new patch changing invalid vendor 'mtk' in favour of 'mediatek'
>which is the one listed in 'vendor-prefixes.yaml'. Update mt7621 code
>accordly. I have added this patch inside this series because clk
>binding is referring syscon node and the string for that node was
>with not listed vendor. Hence update and have all of this correct
>in the same series.


Any comments on this?? Should I resend the series to get reviewed?

Thanks in advance for your time!

Best regards,
Sergio Paracuellos

>
> Changes in v3:
>  - Fix compilation warnings reported by kernel test robot because of
>ignoring return values of 'of_clk_hw_register' in functions
>'mt7621_register_top_clocks' and 'mt7621_gate_ops_init'.
>  - Fix dts file and binding documentation 'clock-output-names'.
>
> Changes in v2:
>  - Remove the following patches:
>* dt: bindings: add mt7621-pll device tree binding documentation.
>* MIPS: ralink: add clock device providing cpu/ahb/apb clock for mt7621.
>  - Move all relevant clock code to 'drivers/clk/ralink/clk-mt7621.c' and
>unify there previous 'mt7621-pll' and 'mt7621-clk' into a unique driver
>and binding 'mt7621-clk'.
>  - Driver is not a platform driver anymore

Re: linux-next: manual merge of the staging tree with the phy-next tree

2020-12-09 Thread Sergio Paracuellos

Hi Stephen,

On Thu, Dec 10, 2020 at 7:40 AM Stephen Rothwell  wrote:
>
> Hi all,
>
> Today's linux-next merge of the staging tree got conflicts in:
>
>   drivers/staging/Kconfig
>   drivers/staging/Makefile
>
> between commit:
>
>   53e7c92c7fa0 ("staging: mt7621-pci-phy: remove driver from staging")
>
> from the phy-next tree and commit:
>
>   518b466a21ad ("pinctrl: ralink: add a pinctrl driver for the rt2880 family")
>
> from the staging tree.
>
> I fixed it up (see below) and can carry the fix as necessary. This
> is now fixed as far as linux-next is concerned, but any non trivial
> conflicts should be mentioned to your upstream maintainer when your tree
> is submitted for merging.  You may also want to consider cooperating
> with the maintainer of the conflicting tree to minimise any particularly
> complex conflicts.

Thanks for doing this. Removing both in staging is the correct thing to do.

>
> --
> Cheers,
> Stephen Rothwell

Best regards,
Sergio Paracuellos
>
> diff --cc drivers/staging/Kconfig
> index 4d7a5ddf9992,c42708e60afc..
> --- a/drivers/staging/Kconfig
> +++ b/drivers/staging/Kconfig
> @@@ -94,8 -92,8 +92,6 @@@ source "drivers/staging/pi433/Kconfig
>
>   source "drivers/staging/mt7621-pci/Kconfig"
>
> - source "drivers/staging/mt7621-pinctrl/Kconfig"
>  -source "drivers/staging/mt7621-pci-phy/Kconfig"
> --
>   source "drivers/staging/mt7621-dma/Kconfig"
>
>   source "drivers/staging/ralink-gdma/Kconfig"
> diff --cc drivers/staging/Makefile
> index 89bde2370eee,ebcc646d7b51..
> --- a/drivers/staging/Makefile
> +++ b/drivers/staging/Makefile
> @@@ -37,7 -36,7 +36,6 @@@ obj-$(CONFIG_GREYBUS) += greybus
>   obj-$(CONFIG_BCM2835_VCHIQ)   += vc04_services/
>   obj-$(CONFIG_PI433)   += pi433/
>   obj-$(CONFIG_PCI_MT7621)  += mt7621-pci/
> - obj-$(CONFIG_PINCTRL_RT2880)  += mt7621-pinctrl/
>  -obj-$(CONFIG_PCI_MT7621_PHY)  += mt7621-pci-phy/
>   obj-$(CONFIG_SOC_MT7621)  += mt7621-dma/
>   obj-$(CONFIG_DMA_RALINK)  += ralink-gdma/
>   obj-$(CONFIG_SOC_MT7621)  += mt7621-dts/

Re: [PATCH v3 0/2] phy: ralink: phy-mt7621-pci: some fixes for COMPILE_TEST

On Tue, Dec 1, 2020 at 12:44 PM Vinod Koul  wrote:
>
> On 01-12-20, 12:20, Sergio Paracuellos wrote:
> > Hi Vinod,
> >
> > After merging the phy-next tree, today's linux-next build (x86_64
> > allmodconfig) failed like this:
> >
> > drivers/phy/ralink/phy-mt7621-pci.c:17:10: fatal error: mt7621.h: No such 
> > file or directory
> > 17 | #include 
> >  |  ^~
> >
> > This driver has two includes which are in
> > "arch/mips/include/asm/mach-ralink" and are directly included in the
> > driver:
> > * mt7621.h
> > * ralink_regs.h
> >
> > This is because this path is directly included in 
> > 'arch/mips/ralink/Platform'
> > for "ralink".
> >
> > Adding the include search path to the phy ralink directory fix the problem 
> > but
> > as you told me I finally end up removing COMPILE_TEST from Kconfig.
> >
> > Making 'allmodconfig' in x86_64 also showed two warnings for this driver
> > because of pointer size and not valid name for MODULE_DEVICE_TABLE ids.
> >
> > Ids for the macro has been also included in this series.
>
> Applied, thanks
>

Thanks for letting me know.

Best regards,
Sergio Paracuellos
> --
> ~Vinod

[PATCH v3 2/2] phy: ralink: phy-mt7621-pci: set correct name in MODULE_DEVICE_TABLE macro

Correct name passed into 'MODULE_DEVICE_TABLE' which was wrong and
was showing a warning when the driver is enabled for 'COMPILE_TEST'.

Signed-off-by: Sergio Paracuellos 
---
 drivers/phy/ralink/phy-mt7621-pci.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/phy/ralink/phy-mt7621-pci.c 
b/drivers/phy/ralink/phy-mt7621-pci.c
index db79088d5362..9a610b414b1f 100644
--- a/drivers/phy/ralink/phy-mt7621-pci.c
+++ b/drivers/phy/ralink/phy-mt7621-pci.c
@@ -335,7 +335,7 @@ static const struct of_device_id mt7621_pci_phy_ids[] = {
{ .compatible = "mediatek,mt7621-pci-phy" },
{},
 };
-MODULE_DEVICE_TABLE(of, mt7621_pci_ids);
+MODULE_DEVICE_TABLE(of, mt7621_pci_phy_ids);
 
 static struct platform_driver mt7621_pci_phy_driver = {
.probe = mt7621_pci_phy_probe,
-- 
2.25.1

[PATCH v3 0/2] phy: ralink: phy-mt7621-pci: some fixes for COMPILE_TEST

Hi Vinod,

After merging the phy-next tree, today's linux-next build (x86_64
allmodconfig) failed like this:

drivers/phy/ralink/phy-mt7621-pci.c:17:10: fatal error: mt7621.h: No such file 
or directory
17 | #include 
 |  ^~

This driver has two includes which are in
"arch/mips/include/asm/mach-ralink" and are directly included in the
driver:
* mt7621.h
* ralink_regs.h

This is because this path is directly included in 'arch/mips/ralink/Platform'
for "ralink".

Adding the include search path to the phy ralink directory fix the problem but
as you told me I finally end up removing COMPILE_TEST from Kconfig.

Making 'allmodconfig' in x86_64 also showed two warnings for this driver
because of pointer size and not valid name for MODULE_DEVICE_TABLE ids.

Ids for the macro has been also included in this series.

Changes in v3:
- PATCH 1/3 completely changed:
- Makefile is not touched.
- Drop 'COMPILE_TEST' in Kconfig.
- Drop PATCH 2/3 in previous series because COMPILE_TEST does not apply 
anymore.

Changes in v2:
- Added 'Reported-by' tag in PATCH 1/3.

Best regards,
    Sergio Paracuellos

Sergio Paracuellos (2):
  phy: ralink: phy-mt7621-pci: drop 'COMPILE_TEST' from Kconfig
  phy: ralink: phy-mt7621-pci: set correct name in MODULE_DEVICE_TABLE
macro

 drivers/phy/ralink/Kconfig  | 2 +-
 drivers/phy/ralink/phy-mt7621-pci.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

-- 
2.25.1

[PATCH v3 1/2] phy: ralink: phy-mt7621-pci: drop 'COMPILE_TEST' from Kconfig

This driver includes the following two files directly:
- mt7621.h
- ralink_regs.h

Compilation for its related platform properly works because
its real path is included in 'arch/mips/ralink/Platform' as
cflags.

This driver depends on RALINK but also is enabled for COMPILE_TEST
where nothing about its platform is known and this directly
included files are not found at all breaking compilation.

If we want 'COMPILE_TEST' we have to change cflags also inside
'phy/ralink' subdirectory Makefile which seems that does not
like to linux-phy maintainers. Hence remove COMPILE_TEST from
Kconfig to avoid the problem.

Fixes: d87da32372a0 ("phy: ralink: Add PHY driver for MT7621 PCIe PHY")
Reported-by: Stephen Rothwell 
Signed-off-by: Sergio Paracuellos 
---
 drivers/phy/ralink/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/phy/ralink/Kconfig b/drivers/phy/ralink/Kconfig
index 2fabb14d2998..ecc309ba9fee 100644
--- a/drivers/phy/ralink/Kconfig
+++ b/drivers/phy/ralink/Kconfig
@@ -4,7 +4,7 @@
 #
 config PHY_MT7621_PCI
tristate "MediaTek MT7621 PCI PHY Driver"
-   depends on (RALINK || COMPILE_TEST) && OF
+   depends on RALINK && OF
select GENERIC_PHY
select REGMAP_MMIO
help
-- 
2.25.1

Re: [PATCH 1/3] phy: ralink: phy-mt7621-pci: add include search path in Makefile

Hi Vinod,

On Tue, Dec 1, 2020 at 12:02 PM Vinod Koul  wrote:
>
> On 01-12-20, 11:47, Sergio Paracuellos wrote:
> > Hi Vinod,
> >
> > On Tue, Dec 1, 2020 at 11:42 AM Vinod Koul  wrote:
> > >
> > > On 01-12-20, 11:16, Sergio Paracuellos wrote:
> > > > This driver includes the following two files directly:
> > > > - mt7621.h
> > > > - ralink_regs.h
> > > >
> > > > Compilation for its related platform properly works because
> > > > its real path is included in 'arch/mips/ralink/Platform' as
> > > > cflags.
> > > >
> > > > This driver depends on RALINK but also is enabled for COMPILE_TEST
> > > > where nothing about its platform is known and this directly
> > > > included files are not found at all breaking compilation.
> > > >
> > > > Fix this problem adding include search path for ralink in
> > > > ralink phy directory Makefile.
> > > >
> > > > Fixes: d87da32372a0 ("phy: ralink: Add PHY driver for MT7621 PCIe PHY")
> > >
> > > Pls add reported-by sfr..
> >
> > Ok, Will change this and send v2.
> >
> > >
> > > > Signed-off-by: Sergio Paracuellos 
> > > > ---
> > > >  drivers/phy/ralink/Makefile | 3 +++
> > > >  1 file changed, 3 insertions(+)
> > > >
> > > > diff --git a/drivers/phy/ralink/Makefile b/drivers/phy/ralink/Makefile
> > > > index cda2a4a7ca5e..c8f9adba0d82 100644
> > > > --- a/drivers/phy/ralink/Makefile
> > > > +++ b/drivers/phy/ralink/Makefile
> > > > @@ -1,3 +1,6 @@
> > > >  # SPDX-License-Identifier: GPL-2.0-only
> > > > +
> > > > +ccflags-y+= -I$(srctree)/arch/mips/include/asm/mach-ralink
> > >
> > > Can we include  instead of using this?
> >
> > Doing that also fails because path for 'arch/mips/include' is not
> > added also because we are compiling in x86_64.
> > Looking into other drivers I see the way to avoid this kind of
> > platform specific stuff is adding related paths in
> > cflags. So I don't really know if there is another way.
>
> Right, ideally these headers should have been in include/linux, but.. I
> dont like this way, can we drop compile test..?

Ok, will drop it then and resend.

Thanks,
Sergio Paracuellos
>
> --
> ~Vinod

[PATCH v2 2/3] phy: ralink: phy-mt7621-pci: avoid warning if COMPILE_TEST is enabled

This driver can be enabled for COMPILE_TEST. Casting to unsigned
int for address shows a compilation warning because of size of the
pointer in x86_64 architecture using 'make allmodconfig' target.
Avoid the warning in any architecture casting to unsigned long and
properly setting format also for 'dev_info' macro.

Signed-off-by: Sergio Paracuellos 
---
 drivers/phy/ralink/phy-mt7621-pci.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/phy/ralink/phy-mt7621-pci.c 
b/drivers/phy/ralink/phy-mt7621-pci.c
index db79088d5362..befa282e2447 100644
--- a/drivers/phy/ralink/phy-mt7621-pci.c
+++ b/drivers/phy/ralink/phy-mt7621-pci.c
@@ -272,8 +272,8 @@ static struct phy *mt7621_pcie_phy_of_xlate(struct device 
*dev,
 
mt7621_phy->has_dual_port = args->args[0];
 
-   dev_info(dev, "PHY for 0x%08x (dual port = %d)\n",
-(unsigned int)mt7621_phy->port_base, 
mt7621_phy->has_dual_port);
+   dev_info(dev, "PHY for 0x%08lx (dual port = %d)\n",
+(unsigned long)mt7621_phy->port_base, 
mt7621_phy->has_dual_port);
 
return mt7621_phy->phy;
 }
-- 
2.25.1

[PATCH v2 0/3] phy: ralink: phy-mt7621-pci: some fixes for COMPILE_TEST

Hi Vinod,

After merging the phy-next tree, today's linux-next build (x86_64
allmodconfig) failed like this:

drivers/phy/ralink/phy-mt7621-pci.c:17:10: fatal error: mt7621.h: No such file 
or directory
17 | #include 
 |  ^~

This driver has two includes which are in
"arch/mips/include/asm/mach-ralink" and are directly included in the
driver:
* mt7621.h
* ralink_regs.h

This is because this path is directly included in 'arch/mips/ralink/Platform'
for "ralink".

Adding the include search path to the phy ralink directory fix the problem.

Making 'allmodconfig' in x86_64 also showed two warnings for this driver
because of pointer size and not valid name for MODULE_DEVICE_TABLE ids.

This two have been also fixed and included in this series.

Changes in v2:
- Added 'Reported-by' tag in PATCH 1/3.

Best regards,
    Sergio Paracuellos

Sergio Paracuellos (3):
  phy: ralink: phy-mt7621-pci: add include search path in Makefile
  phy: ralink: phy-mt7621-pci: avoid warning if COMPILE_TEST is enabled
  phy: ralink: phy-mt7621-pci: set correct name in MODULE_DEVICE_TABLE
macro

 drivers/phy/ralink/Makefile | 3 +++
 drivers/phy/ralink/phy-mt7621-pci.c | 6 +++---
 2 files changed, 6 insertions(+), 3 deletions(-)

-- 
2.25.1

[PATCH v2 3/3] phy: ralink: phy-mt7621-pci: set correct name in MODULE_DEVICE_TABLE macro

Correct name passed into 'MODULE_DEVICE_TABLE' which was wrong and
was showing a warning when the driver is enabled for 'COMPILE_TEST'.

Signed-off-by: Sergio Paracuellos 
---
 drivers/phy/ralink/phy-mt7621-pci.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/phy/ralink/phy-mt7621-pci.c 
b/drivers/phy/ralink/phy-mt7621-pci.c
index befa282e2447..072f848ec0cf 100644
--- a/drivers/phy/ralink/phy-mt7621-pci.c
+++ b/drivers/phy/ralink/phy-mt7621-pci.c
@@ -335,7 +335,7 @@ static const struct of_device_id mt7621_pci_phy_ids[] = {
{ .compatible = "mediatek,mt7621-pci-phy" },
{},
 };
-MODULE_DEVICE_TABLE(of, mt7621_pci_ids);
+MODULE_DEVICE_TABLE(of, mt7621_pci_phy_ids);
 
 static struct platform_driver mt7621_pci_phy_driver = {
.probe = mt7621_pci_phy_probe,
-- 
2.25.1

[PATCH v2 1/3] phy: ralink: phy-mt7621-pci: add include search path in Makefile

This driver includes the following two files directly:
- mt7621.h
- ralink_regs.h

Compilation for its related platform properly works because
its real path is included in 'arch/mips/ralink/Platform' as
cflags.

This driver depends on RALINK but also is enabled for COMPILE_TEST
where nothing about its platform is known and this directly
included files are not found at all breaking compilation.

Fix this problem adding include search path for ralink in
ralink phy directory Makefile.

Fixes: d87da32372a0 ("phy: ralink: Add PHY driver for MT7621 PCIe PHY")
Reported-by: Stephen Rothwell 
Signed-off-by: Sergio Paracuellos 
---
 drivers/phy/ralink/Makefile | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/phy/ralink/Makefile b/drivers/phy/ralink/Makefile
index cda2a4a7ca5e..c8f9adba0d82 100644
--- a/drivers/phy/ralink/Makefile
+++ b/drivers/phy/ralink/Makefile
@@ -1,3 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0-only
+
+ccflags-y  += -I$(srctree)/arch/mips/include/asm/mach-ralink
+
 obj-$(CONFIG_PHY_MT7621_PCI)   += phy-mt7621-pci.o
 obj-$(CONFIG_PHY_RALINK_USB)   += phy-ralink-usb.o
-- 
2.25.1

Re: [PATCH 1/3] phy: ralink: phy-mt7621-pci: add include search path in Makefile

Hi Vinod,

On Tue, Dec 1, 2020 at 11:42 AM Vinod Koul  wrote:
>
> On 01-12-20, 11:16, Sergio Paracuellos wrote:
> > This driver includes the following two files directly:
> > - mt7621.h
> > - ralink_regs.h
> >
> > Compilation for its related platform properly works because
> > its real path is included in 'arch/mips/ralink/Platform' as
> > cflags.
> >
> > This driver depends on RALINK but also is enabled for COMPILE_TEST
> > where nothing about its platform is known and this directly
> > included files are not found at all breaking compilation.
> >
> > Fix this problem adding include search path for ralink in
> > ralink phy directory Makefile.
> >
> > Fixes: d87da32372a0 ("phy: ralink: Add PHY driver for MT7621 PCIe PHY")
>
> Pls add reported-by sfr..

Ok, Will change this and send v2.

>
> > Signed-off-by: Sergio Paracuellos 
> > ---
> >  drivers/phy/ralink/Makefile | 3 +++
> >  1 file changed, 3 insertions(+)
> >
> > diff --git a/drivers/phy/ralink/Makefile b/drivers/phy/ralink/Makefile
> > index cda2a4a7ca5e..c8f9adba0d82 100644
> > --- a/drivers/phy/ralink/Makefile
> > +++ b/drivers/phy/ralink/Makefile
> > @@ -1,3 +1,6 @@
> >  # SPDX-License-Identifier: GPL-2.0-only
> > +
> > +ccflags-y+= -I$(srctree)/arch/mips/include/asm/mach-ralink
>
> Can we include  instead of using this?

Doing that also fails because path for 'arch/mips/include' is not
added also because we are compiling in x86_64.
Looking into other drivers I see the way to avoid this kind of
platform specific stuff is adding related paths in
cflags. So I don't really know if there is another way.

>
> > +
> >  obj-$(CONFIG_PHY_MT7621_PCI) += phy-mt7621-pci.o
> >  obj-$(CONFIG_PHY_RALINK_USB) += phy-ralink-usb.o
> > --
> > 2.25.1
>
> --
> ~Vinod

Best regards,
Sergio Paracuellos

[PATCH 1/3] phy: ralink: phy-mt7621-pci: add include search path in Makefile

This driver includes the following two files directly:
- mt7621.h
- ralink_regs.h

Compilation for its related platform properly works because
its real path is included in 'arch/mips/ralink/Platform' as
cflags.

This driver depends on RALINK but also is enabled for COMPILE_TEST
where nothing about its platform is known and this directly
included files are not found at all breaking compilation.

Fix this problem adding include search path for ralink in
ralink phy directory Makefile.

Fixes: d87da32372a0 ("phy: ralink: Add PHY driver for MT7621 PCIe PHY")
Signed-off-by: Sergio Paracuellos 
---
 drivers/phy/ralink/Makefile | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/phy/ralink/Makefile b/drivers/phy/ralink/Makefile
index cda2a4a7ca5e..c8f9adba0d82 100644
--- a/drivers/phy/ralink/Makefile
+++ b/drivers/phy/ralink/Makefile
@@ -1,3 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0-only
+
+ccflags-y  += -I$(srctree)/arch/mips/include/asm/mach-ralink
+
 obj-$(CONFIG_PHY_MT7621_PCI)   += phy-mt7621-pci.o
 obj-$(CONFIG_PHY_RALINK_USB)   += phy-ralink-usb.o
-- 
2.25.1

[PATCH 0/3] phy: ralink: phy-mt7621-pci: some fixes for COMPILE_TEST