[PATCH] drm: bridge: adv7511: Support I2S IEC958 encoded PCM format
Support IEC958 encoded PCM format for ADV7511 so that ADV7511 HDMI audio driver can accept the IEC958 data from the I2S input. Signed-off-by: Sia Jee Heng --- drivers/gpu/drm/bridge/adv7511/adv7511.h | 1 + drivers/gpu/drm/bridge/adv7511/adv7511_audio.c | 6 ++ 2 files changed, 7 insertions(+) diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511.h b/drivers/gpu/drm/bridge/adv7511/adv7511.h index a9bb734366ae..05e3abb5a0c9 100644 --- a/drivers/gpu/drm/bridge/adv7511/adv7511.h +++ b/drivers/gpu/drm/bridge/adv7511/adv7511.h @@ -191,6 +191,7 @@ #define ADV7511_I2S_FORMAT_I2S 0 #define ADV7511_I2S_FORMAT_RIGHT_J 1 #define ADV7511_I2S_FORMAT_LEFT_J 2 +#define ADV7511_I2S_IEC958_DIRECT 3 #define ADV7511_PACKET(p, x) ((p) * 0x20 + (x)) #define ADV7511_PACKET_SDP(x) ADV7511_PACKET(0, x) diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511_audio.c b/drivers/gpu/drm/bridge/adv7511/adv7511_audio.c index 45838bd08d37..61f4a38e7d2b 100644 --- a/drivers/gpu/drm/bridge/adv7511/adv7511_audio.c +++ b/drivers/gpu/drm/bridge/adv7511/adv7511_audio.c @@ -101,6 +101,10 @@ static int adv7511_hdmi_hw_params(struct device *dev, void *data, case 20: len = ADV7511_I2S_SAMPLE_LEN_20; break; + case 32: + if (fmt->bit_fmt != SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE) + return -EINVAL; + fallthrough; case 24: len = ADV7511_I2S_SAMPLE_LEN_24; break; @@ -112,6 +116,8 @@ static int adv7511_hdmi_hw_params(struct device *dev, void *data, case HDMI_I2S: audio_source = ADV7511_AUDIO_SOURCE_I2S; i2s_format = ADV7511_I2S_FORMAT_I2S; + if (fmt->bit_fmt == SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE) + i2s_format = ADV7511_I2S_IEC958_DIRECT; break; case HDMI_RIGHT_J: audio_source = ADV7511_AUDIO_SOURCE_I2S; base-commit: de066e116306baf3a6a62691ac63cfc0b1dabddb -- 2.18.0
RE: [PATCH][next] dmaengine: dw-axi-dmac: remove redundant null check on desc
The code looks good to me. I have also verified it on Intel KeemBay platform.
Reviewed-by: Sia Jee Heng
Tested-by: Sia Jee Heng
Thanks
Regards
Jee Heng
> -Original Message-
> From: Colin King
> Sent: 03 February 2021 9:47 PM
> To: Eugeniy Paltsev ; Vinod Koul
> ; Sia, Jee Heng ; Andy
> Shevchenko ;
> dmaeng...@vger.kernel.org
> Cc: kernel-janit...@vger.kernel.org; linux-kernel@vger.kernel.org
> Subject: [PATCH][next] dmaengine: dw-axi-dmac: remove redundant
> null check on desc
>
> From: Colin Ian King
>
> The pointer desc is being null checked twice, the second null check is
> redundant because desc has not been re-assigned between the checks.
> Remove the redundant second null check on desc.
>
> Addresses-Coverity: ("Logically dead code")
> Fixes: ef6fb2d6f1ab ("dmaengine: dw-axi-dmac: simplify descriptor
> management")
> Signed-off-by: Colin Ian King
> ---
> drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 4
> 1 file changed, 4 deletions(-)
>
> diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
> b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
> index ac3d81b72a15..d9e4ac3edb4e 100644
> --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
> +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
> @@ -919,10 +919,6 @@ dma_chan_prep_dma_memcpy(struct
> dma_chan *dchan, dma_addr_t dst_adr,
> num++;
> }
>
> - /* Total len of src/dest sg == 0, so no descriptor were
> allocated */
> - if (unlikely(!desc))
> - return NULL;
> -
> /* Set end-of-link to the last link descriptor of list */
> set_desc_last(>hw_desc[num - 1]);
> /* Managed transfer list */
> --
> 2.29.2
[PATCH v12 07/17] dmaegine: dw-axi-dmac: Support device_prep_dma_cyclic()
Add support for device_prep_dma_cyclic() callback function to benefit
DMA cyclic client, for example ALSA.
Existing AxiDMA driver only support data transfer between memory to memory.
Data transfer between device to memory and memory to device in cyclic mode
would failed if this interface is not supported by the AxiDMA driver.
Signed-off-by: Sia Jee Heng
Reviewed-by: Andy Shevchenko
Reviewed-by: Eugeniy Paltsev
Tested-by: Eugeniy Paltsev
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c| 111 --
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 2 +
2 files changed, 106 insertions(+), 7 deletions(-)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 7ff30b0f44ed..a76299360f69 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -15,6 +15,8 @@
#include
#include
#include
+#include
+#include
#include
#include
#include
@@ -549,6 +551,64 @@ static int dw_axi_dma_set_hw_desc(struct axi_dma_chan
*chan,
return 0;
}
+static struct dma_async_tx_descriptor *
+dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan, dma_addr_t dma_addr,
+ size_t buf_len, size_t period_len,
+ enum dma_transfer_direction direction,
+ unsigned long flags)
+{
+ struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
+ struct axi_dma_hw_desc *hw_desc = NULL;
+ struct axi_dma_desc *desc = NULL;
+ dma_addr_t src_addr = dma_addr;
+ u32 num_periods = buf_len / period_len;
+ unsigned int i;
+ int status;
+ u64 llp = 0;
+ u8 lms = 0; /* Select AXI0 master for LLI fetching */
+
+ desc = axi_desc_alloc(num_periods);
+ if (unlikely(!desc))
+ goto err_desc_get;
+
+ chan->direction = direction;
+ desc->chan = chan;
+ chan->cyclic = true;
+
+ for (i = 0; i < num_periods; i++) {
+ hw_desc = >hw_desc[i];
+
+ status = dw_axi_dma_set_hw_desc(chan, hw_desc, src_addr,
+ period_len);
+ if (status < 0)
+ goto err_desc_get;
+
+ /* Set end-of-link to the linked descriptor, so that cyclic
+* callback function can be triggered during interrupt.
+*/
+ set_desc_last(hw_desc);
+
+ src_addr += period_len;
+ }
+
+ llp = desc->hw_desc[0].llp;
+
+ /* Managed transfer list */
+ do {
+ hw_desc = >hw_desc[--num_periods];
+ write_desc_llp(hw_desc, llp | lms);
+ llp = hw_desc->llp;
+ } while (num_periods);
+
+ return vchan_tx_prep(>vc, >vd, flags);
+
+err_desc_get:
+ if (desc)
+ axi_desc_put(desc);
+
+ return NULL;
+}
+
static struct dma_async_tx_descriptor *
dw_axi_dma_chan_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl,
unsigned int sg_len,
@@ -773,8 +833,13 @@ static noinline void axi_chan_handle_err(struct
axi_dma_chan *chan, u32 status)
static void axi_chan_block_xfer_complete(struct axi_dma_chan *chan)
{
+ int count = atomic_read(>descs_allocated);
+ struct axi_dma_hw_desc *hw_desc;
+ struct axi_dma_desc *desc;
struct virt_dma_desc *vd;
unsigned long flags;
+ u64 llp;
+ int i;
spin_lock_irqsave(>vc.lock, flags);
if (unlikely(axi_chan_is_hw_enable(chan))) {
@@ -785,12 +850,32 @@ static void axi_chan_block_xfer_complete(struct
axi_dma_chan *chan)
/* The completed descriptor currently is in the head of vc list */
vd = vchan_next_desc(>vc);
- /* Remove the completed descriptor from issued list before completing */
- list_del(>node);
- vchan_cookie_complete(vd);
- /* Submit queued descriptors after processing the completed ones */
- axi_chan_start_first_queued(chan);
+ if (chan->cyclic) {
+ vchan_cyclic_callback(vd);
+ desc = vd_to_axi_desc(vd);
+ if (desc) {
+ llp = lo_hi_readq(chan->chan_regs + CH_LLP);
+ for (i = 0; i < count; i++) {
+ hw_desc = >hw_desc[i];
+ if (hw_desc->llp == llp) {
+ axi_chan_irq_clear(chan,
hw_desc->lli->status_lo);
+ hw_desc->lli->ctl_hi |=
CH_CTL_H_LLI_VALID;
+ desc->completed_blocks = i;
+ break;
+ }
+ }
+
+ axi_chan_enable(chan);
+ }
+ } else {
+
[PATCH v12 10/17] dt-binding: dma: dw-axi-dmac: Add support for Intel KeemBay AxiDMA
Add support for Intel KeemBay AxiDMA to the dw-axi-dmac Schemas DT binding. Signed-off-by: Sia Jee Heng Reviewed-by: Eugeniy Paltsev Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml | 5 + 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml index 3d2515463d56..79e241498e25 100644 --- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml +++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml @@ -8,6 +8,7 @@ title: Synopsys DesignWare AXI DMA Controller maintainers: - Eugeniy Paltsev + - Jee Heng Sia description: Synopsys DesignWare AXI DMA Controller DT Binding @@ -19,14 +20,18 @@ properties: compatible: enum: - snps,axi-dma-1.01a + - intel,kmb-axi-dma reg: +minItems: 1 items: - description: Address range of the DMAC registers + - description: Address range of the DMAC APB registers reg-names: items: - const: axidma_ctrl_regs + - const: axidma_apb_regs interrupts: maxItems: 1 -- 2.18.0
[PATCH v12 09/17] dmaengine: dw-axi-dmac: Support burst residue granularity
Add support for DMA_RESIDUE_GRANULARITY_BURST so that AxiDMA can report
DMA residue.
Existing AxiDMA driver only support data transfer between
memory to memory operation, therefore reporting DMA residue
to the DMA clients is not supported.
Reporting DMA residue to the DMA clients is important as DMA clients
shall invoke dmaengine_tx_status() to understand the number of bytes
been transferred so that the buffer pointer can be updated accordingly.
Signed-off-by: Sia Jee Heng
Reviewed-by: Andy Shevchenko
Reviewed-by: Eugeniy Paltsev
Tested-by: Eugeniy Paltsev
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c| 43 ---
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 2 +
2 files changed, 38 insertions(+), 7 deletions(-)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index a8b6c8c8ef58..830d3de76abd 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -265,14 +265,36 @@ dma_chan_tx_status(struct dma_chan *dchan, dma_cookie_t
cookie,
struct dma_tx_state *txstate)
{
struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
- enum dma_status ret;
+ struct virt_dma_desc *vdesc;
+ enum dma_status status;
+ u32 completed_length;
+ unsigned long flags;
+ u32 completed_blocks;
+ size_t bytes = 0;
+ u32 length;
+ u32 len;
- ret = dma_cookie_status(dchan, cookie, txstate);
+ status = dma_cookie_status(dchan, cookie, txstate);
+ if (status == DMA_COMPLETE || !txstate)
+ return status;
- if (chan->is_paused && ret == DMA_IN_PROGRESS)
- ret = DMA_PAUSED;
+ spin_lock_irqsave(>vc.lock, flags);
- return ret;
+ vdesc = vchan_find_desc(>vc, cookie);
+ if (vdesc) {
+ length = vd_to_axi_desc(vdesc)->length;
+ completed_blocks = vd_to_axi_desc(vdesc)->completed_blocks;
+ len = vd_to_axi_desc(vdesc)->hw_desc[0].len;
+ completed_length = completed_blocks * len;
+ bytes = length - completed_length;
+ } else {
+ bytes = vd_to_axi_desc(vdesc)->length;
+ }
+
+ spin_unlock_irqrestore(>vc.lock, flags);
+ dma_set_residue(txstate, bytes);
+
+ return status;
}
static void write_desc_llp(struct axi_dma_hw_desc *desc, dma_addr_t adr)
@@ -549,6 +571,7 @@ static int dw_axi_dma_set_hw_desc(struct axi_dma_chan *chan,
set_desc_src_master(hw_desc);
+ hw_desc->len = len;
return 0;
}
@@ -575,6 +598,7 @@ dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan,
dma_addr_t dma_addr,
chan->direction = direction;
desc->chan = chan;
chan->cyclic = true;
+ desc->length = 0;
for (i = 0; i < num_periods; i++) {
hw_desc = >hw_desc[i];
@@ -584,6 +608,7 @@ dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan,
dma_addr_t dma_addr,
if (status < 0)
goto err_desc_get;
+ desc->length += hw_desc->len;
/* Set end-of-link to the linked descriptor, so that cyclic
* callback function can be triggered during interrupt.
*/
@@ -636,6 +661,7 @@ dw_axi_dma_chan_prep_slave_sg(struct dma_chan *dchan,
struct scatterlist *sgl,
goto err_desc_get;
desc->chan = chan;
+ desc->length = 0;
for_each_sg(sgl, sg, sg_len, i) {
mem = sg_dma_address(sg);
@@ -645,6 +671,7 @@ dw_axi_dma_chan_prep_slave_sg(struct dma_chan *dchan,
struct scatterlist *sgl,
status = dw_axi_dma_set_hw_desc(chan, hw_desc, mem, len);
if (status < 0)
goto err_desc_get;
+ desc->length += hw_desc->len;
}
/* Set end-of-link to the last link descriptor of list */
@@ -690,6 +717,7 @@ dma_chan_prep_dma_memcpy(struct dma_chan *dchan, dma_addr_t
dst_adr,
desc->chan = chan;
num = 0;
+ desc->length = 0;
while (len) {
xfer_len = len;
@@ -742,7 +770,8 @@ dma_chan_prep_dma_memcpy(struct dma_chan *dchan, dma_addr_t
dst_adr,
set_desc_src_master(hw_desc);
set_desc_dest_master(hw_desc, desc);
-
+ hw_desc->len = xfer_len;
+ desc->length += hw_desc->len;
/* update the length and addresses for the next loop cycle */
len -= xfer_len;
dst_adr += xfer_len;
@@ -1210,7 +1239,7 @@ static int dw_probe(struct platform_device *pdev)
dw->dma.dst_addr_widths = AXI_DMA_BUSWIDTHS;
dw->dma.directions = BIT(DMA_MEM_TO_MEM);
dw->dma.directions |= BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM);
-
[PATCH v12 12/17] dmaengine: drivers: Kconfig: add HAS_IOMEM dependency to DW_AXI_DMAC
If HAS_IOMEM is not defined and DW_AXI_DMAC is enabled under COMPILE_TEST, the build fails with the following error: dw-axi-dmac-platform.c:(.text+0xc4): undefined reference to `devm_ioremap_resource' Link: https://www.spinics.net/lists/dmaengine/msg25188.html Reported-by: kernel test robot Signed-off-by: Sia Jee Heng --- drivers/dma/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index d242c7632621..38eb40ccd5e0 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -179,6 +179,7 @@ config DMA_SUN6I config DW_AXI_DMAC tristate "Synopsys DesignWare AXI DMA support" depends on OF || COMPILE_TEST + depends on HAS_IOMEM select DMA_ENGINE select DMA_VIRTUAL_CHANNELS help -- 2.18.0
[PATCH v12 13/17] dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA support
Add support for Intel KeemBay AxiDMA to the .compatible field.
The AxiDMA Apb region will be accessible if the compatible string
matches the "intel,kmb-axi-dma".
Signed-off-by: Sia Jee Heng
Reviewed-by: Andy Shevchenko
Reviewed-by: Eugeniy Paltsev
Tested-by: Eugeniy Paltsev
---
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 830d3de76abd..062d27c61983 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -1160,6 +1160,7 @@ static int parse_device_properties(struct axi_dma_chip
*chip)
static int dw_probe(struct platform_device *pdev)
{
+ struct device_node *node = pdev->dev.of_node;
struct axi_dma_chip *chip;
struct resource *mem;
struct dw_axi_dma *dw;
@@ -1192,6 +1193,12 @@ static int dw_probe(struct platform_device *pdev)
if (IS_ERR(chip->regs))
return PTR_ERR(chip->regs);
+ if (of_device_is_compatible(node, "intel,kmb-axi-dma")) {
+ chip->apb_regs = devm_platform_ioremap_resource(pdev, 1);
+ if (IS_ERR(chip->apb_regs))
+ return PTR_ERR(chip->apb_regs);
+ }
+
chip->core_clk = devm_clk_get(chip->dev, "core-clk");
if (IS_ERR(chip->core_clk))
return PTR_ERR(chip->core_clk);
@@ -1336,6 +1343,7 @@ static const struct dev_pm_ops dw_axi_dma_pm_ops = {
static const struct of_device_id dw_dma_of_id_table[] = {
{ .compatible = "snps,axi-dma-1.01a" },
+ { .compatible = "intel,kmb-axi-dma" },
{}
};
MODULE_DEVICE_TABLE(of, dw_dma_of_id_table);
--
2.18.0
[PATCH v12 14/17] dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA handshake
Add support for Intel KeemBay AxiDMA device handshake programming.
Device handshake number passed in to the AxiDMA shall be written to
the Intel KeemBay AxiDMA hardware handshake registers before DMA
operations are started.
Signed-off-by: Sia Jee Heng
Reviewed-by: Andy Shevchenko
Reviewed-by: Eugeniy Paltsev
Tested-by: Eugeniy Paltsev
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c| 50 +++
1 file changed, 50 insertions(+)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 062d27c61983..e19369f9365a 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -445,6 +445,48 @@ static void dma_chan_free_chan_resources(struct dma_chan
*dchan)
pm_runtime_put(chan->chip->dev);
}
+static void dw_axi_dma_set_hw_channel(struct axi_dma_chip *chip,
+ u32 handshake_num, bool set)
+{
+ unsigned long start = 0;
+ unsigned long reg_value;
+ unsigned long reg_mask;
+ unsigned long reg_set;
+ unsigned long mask;
+ unsigned long val;
+
+ if (!chip->apb_regs) {
+ dev_dbg(chip->dev, "apb_regs not initialized\n");
+ return;
+ }
+
+ /*
+* An unused DMA channel has a default value of 0x3F.
+* Lock the DMA channel by assign a handshake number to the channel.
+* Unlock the DMA channel by assign 0x3F to the channel.
+*/
+ if (set) {
+ reg_set = UNUSED_CHANNEL;
+ val = handshake_num;
+ } else {
+ reg_set = handshake_num;
+ val = UNUSED_CHANNEL;
+ }
+
+ reg_value = lo_hi_readq(chip->apb_regs + DMAC_APB_HW_HS_SEL_0);
+
+ for_each_set_clump8(start, reg_mask, _value, 64) {
+ if (reg_mask == reg_set) {
+ mask = GENMASK_ULL(start + 7, start);
+ reg_value &= ~mask;
+ reg_value |= rol64(val, start);
+ lo_hi_writeq(reg_value,
+chip->apb_regs + DMAC_APB_HW_HS_SEL_0);
+ break;
+ }
+ }
+}
+
/*
* If DW_axi_dmac sees CHx_CTL.ShadowReg_Or_LLI_Last bit of the fetched LLI
* as 1, it understands that the current block is the final block in the
@@ -626,6 +668,8 @@ dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan,
dma_addr_t dma_addr,
llp = hw_desc->llp;
} while (num_periods);
+ dw_axi_dma_set_hw_channel(chan->chip, chan->hw_handshake_num, true);
+
return vchan_tx_prep(>vc, >vd, flags);
err_desc_get:
@@ -684,6 +728,8 @@ dw_axi_dma_chan_prep_slave_sg(struct dma_chan *dchan,
struct scatterlist *sgl,
llp = hw_desc->llp;
} while (sg_len);
+ dw_axi_dma_set_hw_channel(chan->chip, chan->hw_handshake_num, true);
+
return vchan_tx_prep(>vc, >vd, flags);
err_desc_get:
@@ -959,6 +1005,10 @@ static int dma_chan_terminate_all(struct dma_chan *dchan)
dev_warn(dchan2dev(dchan),
"%s failed to stop\n", axi_chan_name(chan));
+ if (chan->direction != DMA_MEM_TO_MEM)
+ dw_axi_dma_set_hw_channel(chan->chip,
+ chan->hw_handshake_num, false);
+
spin_lock_irqsave(>vc.lock, flags);
vchan_get_all_descriptors(>vc, );
--
2.18.0
[PATCH v12 17/17] dmaengine: dw-axi-dmac: Virtually split the linked-list
AxiDMA driver exposed the dma_set_max_seg_size() to the DMAENGINE.
It shall helps the DMA clients to create size-optimized linked-list
for the controller.
However, there are certain situations where DMA client might not be
abled to benefit from the dma_get_max_seg_size() if the segment size
can't meet the nature of the DMA client's operation.
In the case of ALSA operation, ALSA application and driver expecting
to run in a period of larger than 10ms regardless of the bit depth.
With this large period, there is a strong request to split the linked-list
in the AxiDMA driver.
Signed-off-by: Sia Jee Heng
Reviewed-by: Eugeniy Paltsev
Tested-by: Eugeniy Paltsev
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c| 111 ++
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 1 +
2 files changed, 92 insertions(+), 20 deletions(-)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 88d4923dee6c..ac3d81b72a15 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -581,6 +581,11 @@ static int dw_axi_dma_set_hw_desc(struct axi_dma_chan
*chan,
if (mem_width > DWAXIDMAC_TRANS_WIDTH_32)
mem_width = DWAXIDMAC_TRANS_WIDTH_32;
+ if (!IS_ALIGNED(mem_addr, 4)) {
+ dev_err(chan->chip->dev, "invalid buffer alignment\n");
+ return -EINVAL;
+ }
+
switch (chan->direction) {
case DMA_MEM_TO_DEV:
reg_width = __ffs(chan->config.dst_addr_width);
@@ -642,6 +647,35 @@ static int dw_axi_dma_set_hw_desc(struct axi_dma_chan
*chan,
return 0;
}
+static size_t calculate_block_len(struct axi_dma_chan *chan,
+ dma_addr_t dma_addr, size_t buf_len,
+ enum dma_transfer_direction direction)
+{
+ u32 data_width, reg_width, mem_width;
+ size_t axi_block_ts, block_len;
+
+ axi_block_ts = chan->chip->dw->hdata->block_size[chan->id];
+
+ switch (direction) {
+ case DMA_MEM_TO_DEV:
+ data_width = BIT(chan->chip->dw->hdata->m_data_width);
+ mem_width = __ffs(data_width | dma_addr | buf_len);
+ if (mem_width > DWAXIDMAC_TRANS_WIDTH_32)
+ mem_width = DWAXIDMAC_TRANS_WIDTH_32;
+
+ block_len = axi_block_ts << mem_width;
+ break;
+ case DMA_DEV_TO_MEM:
+ reg_width = __ffs(chan->config.src_addr_width);
+ block_len = axi_block_ts << reg_width;
+ break;
+ default:
+ block_len = 0;
+ }
+
+ return block_len;
+}
+
static struct dma_async_tx_descriptor *
dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan, dma_addr_t dma_addr,
size_t buf_len, size_t period_len,
@@ -652,13 +686,27 @@ dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan,
dma_addr_t dma_addr,
struct axi_dma_hw_desc *hw_desc = NULL;
struct axi_dma_desc *desc = NULL;
dma_addr_t src_addr = dma_addr;
- u32 num_periods = buf_len / period_len;
+ u32 num_periods, num_segments;
+ size_t axi_block_len;
+ u32 total_segments;
+ u32 segment_len;
unsigned int i;
int status;
u64 llp = 0;
u8 lms = 0; /* Select AXI0 master for LLI fetching */
- desc = axi_desc_alloc(num_periods);
+ num_periods = buf_len / period_len;
+
+ axi_block_len = calculate_block_len(chan, dma_addr, buf_len, direction);
+ if (axi_block_len == 0)
+ return NULL;
+
+ num_segments = DIV_ROUND_UP(period_len, axi_block_len);
+ segment_len = DIV_ROUND_UP(period_len, num_segments);
+
+ total_segments = num_periods * num_segments;
+
+ desc = axi_desc_alloc(total_segments);
if (unlikely(!desc))
goto err_desc_get;
@@ -666,12 +714,13 @@ dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan,
dma_addr_t dma_addr,
desc->chan = chan;
chan->cyclic = true;
desc->length = 0;
+ desc->period_len = period_len;
- for (i = 0; i < num_periods; i++) {
+ for (i = 0; i < total_segments; i++) {
hw_desc = >hw_desc[i];
status = dw_axi_dma_set_hw_desc(chan, hw_desc, src_addr,
- period_len);
+ segment_len);
if (status < 0)
goto err_desc_get;
@@ -681,17 +730,17 @@ dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan,
dma_addr_t dma_addr,
*/
set_desc_last(hw_desc);
- src_addr += period_len;
+ src_addr += segment_len;
}
llp = desc->hw_desc[0].llp;
/* Managed transfer list */
[PATCH v12 03/17] dmaengine: dw-axi-dmac: move dma_pool_create() to alloc_chan_resources()
The DMA memory block is created at driver load time and exist for
device lifetime. Move the dma_pool_create() to the ->chan_resource()
callback function allowing the DMA memory blocks to be created as needed
and destroyed when the channel is freed.
Signed-off-by: Sia Jee Heng
Reviewed-by: Andy Shevchenko
Reviewed-by: Eugeniy Paltsev
Tested-by: Eugeniy Paltsev
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c| 24 ++-
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 2 +-
2 files changed, 14 insertions(+), 12 deletions(-)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 350968baaf88..3737e1c3c793 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -216,11 +216,10 @@ static struct axi_dma_desc *axi_desc_alloc(u32 num)
static struct axi_dma_lli *axi_desc_get(struct axi_dma_chan *chan,
dma_addr_t *addr)
{
- struct dw_axi_dma *dw = chan->chip->dw;
struct axi_dma_lli *lli;
dma_addr_t phys;
- lli = dma_pool_zalloc(dw->desc_pool, GFP_NOWAIT, );
+ lli = dma_pool_zalloc(chan->desc_pool, GFP_NOWAIT, );
if (unlikely(!lli)) {
dev_err(chan2dev(chan), "%s: not enough descriptors
available\n",
axi_chan_name(chan));
@@ -236,14 +235,13 @@ static struct axi_dma_lli *axi_desc_get(struct
axi_dma_chan *chan,
static void axi_desc_put(struct axi_dma_desc *desc)
{
struct axi_dma_chan *chan = desc->chan;
- struct dw_axi_dma *dw = chan->chip->dw;
int count = atomic_read(>descs_allocated);
struct axi_dma_hw_desc *hw_desc;
int descs_put;
for (descs_put = 0; descs_put < count; descs_put++) {
hw_desc = >hw_desc[descs_put];
- dma_pool_free(dw->desc_pool, hw_desc->lli, hw_desc->llp);
+ dma_pool_free(chan->desc_pool, hw_desc->lli, hw_desc->llp);
}
kfree(desc->hw_desc);
@@ -360,6 +358,15 @@ static int dma_chan_alloc_chan_resources(struct dma_chan
*dchan)
return -EBUSY;
}
+ /* LLI address must be aligned to a 64-byte boundary */
+ chan->desc_pool = dma_pool_create(dev_name(chan2dev(chan)),
+ chan->chip->dev,
+ sizeof(struct axi_dma_lli),
+ 64, 0);
+ if (!chan->desc_pool) {
+ dev_err(chan2dev(chan), "No memory for descriptors\n");
+ return -ENOMEM;
+ }
dev_vdbg(dchan2dev(dchan), "%s: allocating\n", axi_chan_name(chan));
pm_runtime_get(chan->chip->dev);
@@ -381,6 +388,8 @@ static void dma_chan_free_chan_resources(struct dma_chan
*dchan)
vchan_free_chan_resources(>vc);
+ dma_pool_destroy(chan->desc_pool);
+ chan->desc_pool = NULL;
dev_vdbg(dchan2dev(dchan),
"%s: free resources, descriptor still allocated: %u\n",
axi_chan_name(chan), atomic_read(>descs_allocated));
@@ -896,13 +905,6 @@ static int dw_probe(struct platform_device *pdev)
if (ret)
return ret;
- /* Lli address must be aligned to a 64-byte boundary */
- dw->desc_pool = dmam_pool_create(KBUILD_MODNAME, chip->dev,
-sizeof(struct axi_dma_lli), 64, 0);
- if (!dw->desc_pool) {
- dev_err(chip->dev, "No memory for descriptors dma pool\n");
- return -ENOMEM;
- }
INIT_LIST_HEAD(>dma.channels);
for (i = 0; i < hdata->nr_channels; i++) {
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
index 41e775e6e593..f886b2bb75de 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
@@ -39,6 +39,7 @@ struct axi_dma_chan {
u8 id;
atomic_tdescs_allocated;
+ struct dma_pool *desc_pool;
struct virt_dma_chanvc;
struct axi_dma_desc *desc;
@@ -49,7 +50,6 @@ struct axi_dma_chan {
struct dw_axi_dma {
struct dma_device dma;
struct dw_axi_dma_hcfg *hdata;
- struct dma_pool *desc_pool;
/* channels */
struct axi_dma_chan *chan;
--
2.18.0
[PATCH v12 15/17] dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA BYTE and HALFWORD registers
Add support for Intel KeemBay AxiDMA BYTE and HALFWORD registers
programming.
Intel KeemBay AxiDMA supports data transfer between device to memory
and memory to device operations.
This code is needed by I2C, I3C, I2S, SPI and UART which uses FIFO
size of 8bits and 16bits to perform memory to device data transfer
operation. 0-padding functionality is provided to avoid
pre-processing of data on CPU.
Signed-off-by: Sia Jee Heng
Reviewed-by: Andy Shevchenko
Reviewed-by: Eugeniy Paltsev
Tested-by: Eugeniy Paltsev
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c| 26 +++
1 file changed, 26 insertions(+)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index e19369f9365a..a1dddec95316 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -307,6 +307,29 @@ static void write_chan_llp(struct axi_dma_chan *chan,
dma_addr_t adr)
axi_chan_iowrite64(chan, CH_LLP, adr);
}
+static void dw_axi_dma_set_byte_halfword(struct axi_dma_chan *chan, bool set)
+{
+ u32 offset = DMAC_APB_BYTE_WR_CH_EN;
+ u32 reg_width, val;
+
+ if (!chan->chip->apb_regs) {
+ dev_dbg(chan->chip->dev, "apb_regs not initialized\n");
+ return;
+ }
+
+ reg_width = __ffs(chan->config.dst_addr_width);
+ if (reg_width == DWAXIDMAC_TRANS_WIDTH_16)
+ offset = DMAC_APB_HALFWORD_WR_CH_EN;
+
+ val = ioread32(chan->chip->apb_regs + offset);
+
+ if (set)
+ val |= BIT(chan->id);
+ else
+ val &= ~BIT(chan->id);
+
+ iowrite32(val, chan->chip->apb_regs + offset);
+}
/* Called in chan locked context */
static void axi_chan_block_xfer_start(struct axi_dma_chan *chan,
struct axi_dma_desc *first)
@@ -334,6 +357,7 @@ static void axi_chan_block_xfer_start(struct axi_dma_chan
*chan,
DWAXIDMAC_HS_SEL_HW << CH_CFG_H_HS_SEL_SRC_POS);
switch (chan->direction) {
case DMA_MEM_TO_DEV:
+ dw_axi_dma_set_byte_halfword(chan, true);
reg |= (chan->config.device_fc ?
DWAXIDMAC_TT_FC_MEM_TO_PER_DST :
DWAXIDMAC_TT_FC_MEM_TO_PER_DMAC)
@@ -1008,6 +1032,8 @@ static int dma_chan_terminate_all(struct dma_chan *dchan)
if (chan->direction != DMA_MEM_TO_MEM)
dw_axi_dma_set_hw_channel(chan->chip,
chan->hw_handshake_num, false);
+ if (chan->direction == DMA_MEM_TO_DEV)
+ dw_axi_dma_set_byte_halfword(chan, false);
spin_lock_irqsave(>vc.lock, flags);
--
2.18.0
[PATCH v12 16/17] dmaengine: dw-axi-dmac: Set constraint to the Max segment size
Add support for DMA Scatter-Gather (SG) constraint so that DMA clients can
handle the AxiDMA limitation.
Without supporting DMA constraint the default Max segment size reported by
dmaengine is 64KB, which is not supported by Intel KeemBay AxiDMA.
Signed-off-by: Sia Jee Heng
Reviewed-by: Andy Shevchenko
Reviewed-by: Eugeniy Paltsev
Tested-by: Eugeniy Paltsev
---
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 8
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 1 +
2 files changed, 9 insertions(+)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index a1dddec95316..88d4923dee6c 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -1340,6 +1341,13 @@ static int dw_probe(struct platform_device *pdev)
dw->dma.device_prep_slave_sg = dw_axi_dma_chan_prep_slave_sg;
dw->dma.device_prep_dma_cyclic = dw_axi_dma_chan_prep_cyclic;
+ /*
+* Synopsis DesignWare AxiDMA datasheet mentioned Maximum
+* supported blocks is 1024. Device register width is 4 bytes.
+* Therefore, set constraint to 1024 * 4.
+*/
+ dw->dma.dev->dma_parms = >dma_parms;
+ dma_set_max_seg_size(>dev, MAX_BLOCK_SIZE);
platform_set_drvdata(pdev, chip);
pm_runtime_enable(chip->dev);
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
index 3a357f7fda02..1e937ea2a96d 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
@@ -54,6 +54,7 @@ struct axi_dma_chan {
struct dw_axi_dma {
struct dma_device dma;
struct dw_axi_dma_hcfg *hdata;
+ struct device_dma_parametersdma_parms;
/* channels */
struct axi_dma_chan *chan;
--
2.18.0
[PATCH v12 11/17] dmaengine: dw-axi-dmac: Add Intel KeemBay DMA register fields
Add support for Intel KeemBay DMA registers. These registers are required
to run data transfer between device to memory and memory to device on Intel
KeemBay SoC.
Signed-off-by: Sia Jee Heng
Reviewed-by: Andy Shevchenko
Reviewed-by: Eugeniy Paltsev
Tested-by: Eugeniy Paltsev
---
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
index 46baf93de617..3a357f7fda02 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
@@ -63,6 +63,7 @@ struct axi_dma_chip {
struct device *dev;
int irq;
void __iomem*regs;
+ void __iomem*apb_regs;
struct clk *core_clk;
struct clk *cfgr_clk;
struct dw_axi_dma *dw;
@@ -169,6 +170,19 @@ static inline struct axi_dma_chan
*dchan_to_axi_dma_chan(struct dma_chan *dchan)
#define CH_INTSIGNAL_ENA 0x090 /* R/W Chan Interrupt Signal Enable */
#define CH_INTCLEAR0x098 /* W Chan Interrupt Clear */
+/* These Apb registers are used by Intel KeemBay SoC */
+#define DMAC_APB_CFG 0x000 /* DMAC Apb Configuration Register */
+#define DMAC_APB_STAT 0x004 /* DMAC Apb Status Register */
+#define DMAC_APB_DEBUG_STAT_0 0x008 /* DMAC Apb Debug Status Register 0 */
+#define DMAC_APB_DEBUG_STAT_1 0x00C /* DMAC Apb Debug Status Register 1 */
+#define DMAC_APB_HW_HS_SEL_0 0x010 /* DMAC Apb HW HS register 0 */
+#define DMAC_APB_HW_HS_SEL_1 0x014 /* DMAC Apb HW HS register 1 */
+#define DMAC_APB_LPI 0x018 /* DMAC Apb Low Power Interface Reg */
+#define DMAC_APB_BYTE_WR_CH_EN 0x01C /* DMAC Apb Byte Write Enable */
+#define DMAC_APB_HALFWORD_WR_CH_EN 0x020 /* DMAC Halfword write enables */
+
+#define UNUSED_CHANNEL 0x3F /* Set unused DMA channel to 0x3F */
+#define MAX_BLOCK_SIZE 0x1000 /* 1024 blocks * 4 bytes data width */
/* DMAC_CFG */
#define DMAC_EN_POS0
--
2.18.0
[PATCH v12 06/17] dmaengine: dw-axi-dmac: Support device_prep_slave_sg
Add device_prep_slave_sg() callback function so that DMA_MEM_TO_DEV
and DMA_DEV_TO_MEM operations in single mode can be supported.
Existing AxiDMA driver only support data transfer between
memory to memory. Data transfer between device to memory and
memory to device in single mode would failed if this interface
is not supported by the AxiDMA driver.
Signed-off-by: Sia Jee Heng
Reviewed-by: Andy Shevchenko
Reviewed-by: Eugeniy Paltsev
Tested-by: Eugeniy Paltsev
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c| 154 ++
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 1 +
2 files changed, 155 insertions(+)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index eaa7c4c404ca..7ff30b0f44ed 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -307,6 +307,22 @@ static void axi_chan_block_xfer_start(struct axi_dma_chan
*chan,
priority << CH_CFG_H_PRIORITY_POS |
DWAXIDMAC_HS_SEL_HW << CH_CFG_H_HS_SEL_DST_POS |
DWAXIDMAC_HS_SEL_HW << CH_CFG_H_HS_SEL_SRC_POS);
+ switch (chan->direction) {
+ case DMA_MEM_TO_DEV:
+ reg |= (chan->config.device_fc ?
+ DWAXIDMAC_TT_FC_MEM_TO_PER_DST :
+ DWAXIDMAC_TT_FC_MEM_TO_PER_DMAC)
+ << CH_CFG_H_TT_FC_POS;
+ break;
+ case DMA_DEV_TO_MEM:
+ reg |= (chan->config.device_fc ?
+ DWAXIDMAC_TT_FC_PER_TO_MEM_SRC :
+ DWAXIDMAC_TT_FC_PER_TO_MEM_DMAC)
+ << CH_CFG_H_TT_FC_POS;
+ break;
+ default:
+ break;
+ }
axi_chan_iowrite32(chan, CH_CFG_H, reg);
write_chan_llp(chan, first->hw_desc[0].llp | lms);
@@ -454,6 +470,141 @@ static void set_desc_dest_master(struct axi_dma_hw_desc
*hw_desc,
hw_desc->lli->ctl_lo = cpu_to_le32(val);
}
+static int dw_axi_dma_set_hw_desc(struct axi_dma_chan *chan,
+ struct axi_dma_hw_desc *hw_desc,
+ dma_addr_t mem_addr, size_t len)
+{
+ unsigned int data_width = BIT(chan->chip->dw->hdata->m_data_width);
+ unsigned int reg_width;
+ unsigned int mem_width;
+ dma_addr_t device_addr;
+ size_t axi_block_ts;
+ size_t block_ts;
+ u32 ctllo, ctlhi;
+ u32 burst_len;
+
+ axi_block_ts = chan->chip->dw->hdata->block_size[chan->id];
+
+ mem_width = __ffs(data_width | mem_addr | len);
+ if (mem_width > DWAXIDMAC_TRANS_WIDTH_32)
+ mem_width = DWAXIDMAC_TRANS_WIDTH_32;
+
+ switch (chan->direction) {
+ case DMA_MEM_TO_DEV:
+ reg_width = __ffs(chan->config.dst_addr_width);
+ device_addr = chan->config.dst_addr;
+ ctllo = reg_width << CH_CTL_L_DST_WIDTH_POS |
+ mem_width << CH_CTL_L_SRC_WIDTH_POS |
+ DWAXIDMAC_CH_CTL_L_NOINC << CH_CTL_L_DST_INC_POS |
+ DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_SRC_INC_POS;
+ block_ts = len >> mem_width;
+ break;
+ case DMA_DEV_TO_MEM:
+ reg_width = __ffs(chan->config.src_addr_width);
+ device_addr = chan->config.src_addr;
+ ctllo = reg_width << CH_CTL_L_SRC_WIDTH_POS |
+ mem_width << CH_CTL_L_DST_WIDTH_POS |
+ DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_DST_INC_POS |
+ DWAXIDMAC_CH_CTL_L_NOINC << CH_CTL_L_SRC_INC_POS;
+ block_ts = len >> reg_width;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (block_ts > axi_block_ts)
+ return -EINVAL;
+
+ hw_desc->lli = axi_desc_get(chan, _desc->llp);
+ if (unlikely(!hw_desc->lli))
+ return -ENOMEM;
+
+ ctlhi = CH_CTL_H_LLI_VALID;
+
+ if (chan->chip->dw->hdata->restrict_axi_burst_len) {
+ burst_len = chan->chip->dw->hdata->axi_rw_burst_len;
+ ctlhi |= CH_CTL_H_ARLEN_EN | CH_CTL_H_AWLEN_EN |
+burst_len << CH_CTL_H_ARLEN_POS |
+burst_len << CH_CTL_H_AWLEN_POS;
+ }
+
+ hw_desc->lli->ctl_hi = cpu_to_le32(ctlhi);
+
+ if (chan->direction == DMA_MEM_TO_DEV) {
+ write_desc_sar(hw_desc, mem_addr);
+ write_desc_dar(hw_desc, device_addr);
+ } else {
+ write_desc_sar(hw_desc, device_addr);
+ write_desc_dar(hw_desc, mem_addr);
+ }
+
+ hw_desc->lli->block_ts_lo = cpu_to_le32(block_ts - 1);
+
+ ctllo |=
[PATCH v12 08/17] dmaengine: dw-axi-dmac: Support of_dma_controller_register()
Add support for of_dma_controller_register() so that DMA clients
can pass in device handshake number to the AxiDMA driver.
DMA clients shall code the device handshake number in the Device tree.
When DMA activities are needed, DMA clients shall invoke OF helper
function to pass in the device handshake number to the AxiDMA.
Without register to the of_dma_controller_register(), data transfer
between memory to device and device to memory operations would failed.
Signed-off-by: Sia Jee Heng
Reviewed-by: Andy Shevchenko
Reviewed-by: Eugeniy Paltsev
Tested-by: Eugeniy Paltsev
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c| 26 +++
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 1 +
2 files changed, 27 insertions(+)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index a76299360f69..a8b6c8c8ef58 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -20,6 +20,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -1044,6 +1045,22 @@ static int __maybe_unused axi_dma_runtime_resume(struct
device *dev)
return axi_dma_resume(chip);
}
+static struct dma_chan *dw_axi_dma_of_xlate(struct of_phandle_args *dma_spec,
+ struct of_dma *ofdma)
+{
+ struct dw_axi_dma *dw = ofdma->of_dma_data;
+ struct axi_dma_chan *chan;
+ struct dma_chan *dchan;
+
+ dchan = dma_get_any_slave_channel(>dma);
+ if (!dchan)
+ return NULL;
+
+ chan = dchan_to_axi_dma_chan(dchan);
+ chan->hw_handshake_num = dma_spec->args[0];
+ return dchan;
+}
+
static int parse_device_properties(struct axi_dma_chip *chip)
{
struct device *dev = chip->dev;
@@ -1233,6 +1250,13 @@ static int dw_probe(struct platform_device *pdev)
if (ret)
goto err_pm_disable;
+ /* Register with OF helpers for DMA lookups */
+ ret = of_dma_controller_register(pdev->dev.of_node,
+dw_axi_dma_of_xlate, dw);
+ if (ret < 0)
+ dev_warn(>dev,
+"Failed to register OF DMA controller, fallback to
MEM_TO_MEM mode\n");
+
dev_info(chip->dev, "DesignWare AXI DMA Controller, %d channels\n",
dw->hdata->nr_channels);
@@ -1266,6 +1290,8 @@ static int dw_remove(struct platform_device *pdev)
devm_free_irq(chip->dev, chip->irq, chip);
+ of_dma_controller_free(chip->dev->of_node);
+
list_for_each_entry_safe(chan, _chan, >dma.channels,
vc.chan.device_node) {
list_del(>vc.chan.device_node);
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
index a26b0a242a93..3498bef5453b 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
@@ -37,6 +37,7 @@ struct axi_dma_chan {
struct axi_dma_chip *chip;
void __iomem*chan_regs;
u8 id;
+ u8 hw_handshake_num;
atomic_tdescs_allocated;
struct dma_pool *desc_pool;
--
2.18.0
[PATCH v12 05/17] dmaengine: dw-axi-dmac: Add device_config operation
Add device_config() callback function so that the device address
can be passed to the dma driver.
DMA clients use this interface to pass in the device address to the
AxiDMA. Without this interface, data transfer between device to memory
and memory to device would failed.
Signed-off-by: Sia Jee Heng
Reviewed-by: Andy Shevchenko
Reviewed-by: Eugeniy Paltsev
Tested-by: Eugeniy Paltsev
---
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 11 +++
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 1 +
2 files changed, 12 insertions(+)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 241ab7a24e2a..eaa7c4c404ca 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -559,6 +559,16 @@ dma_chan_prep_dma_memcpy(struct dma_chan *dchan,
dma_addr_t dst_adr,
return NULL;
}
+static int dw_axi_dma_chan_slave_config(struct dma_chan *dchan,
+ struct dma_slave_config *config)
+{
+ struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
+
+ memcpy(>config, config, sizeof(*config));
+
+ return 0;
+}
+
static void axi_chan_dump_lli(struct axi_dma_chan *chan,
struct axi_dma_hw_desc *desc)
{
@@ -948,6 +958,7 @@ static int dw_probe(struct platform_device *pdev)
dw->dma.device_prep_dma_memcpy = dma_chan_prep_dma_memcpy;
dw->dma.device_synchronize = dw_axi_dma_synchronize;
+ dw->dma.device_config = dw_axi_dma_chan_slave_config;
platform_set_drvdata(pdev, chip);
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
index f886b2bb75de..a75b921d6b1a 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
@@ -43,6 +43,7 @@ struct axi_dma_chan {
struct virt_dma_chanvc;
struct axi_dma_desc *desc;
+ struct dma_slave_config config;
/* these other elements are all protected by vc.lock */
boolis_paused;
};
--
2.18.0
[PATCH v12 04/17] dmaengine: dw-axi-dmac: Add device_synchronize() callback
Add support for device_synchronize() callback function to sync with
dmaengine_terminate_sync().
Signed-off-by: Sia Jee Heng
Reviewed-by: Andy Shevchenko
Reviewed-by: Eugeniy Paltsev
Tested-by: Eugeniy Paltsev
---
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 3737e1c3c793..241ab7a24e2a 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -347,6 +347,13 @@ static void dma_chan_issue_pending(struct dma_chan *dchan)
spin_unlock_irqrestore(>vc.lock, flags);
}
+static void dw_axi_dma_synchronize(struct dma_chan *dchan)
+{
+ struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
+
+ vchan_synchronize(>vc);
+}
+
static int dma_chan_alloc_chan_resources(struct dma_chan *dchan)
{
struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
@@ -940,6 +947,7 @@ static int dw_probe(struct platform_device *pdev)
dw->dma.device_free_chan_resources = dma_chan_free_chan_resources;
dw->dma.device_prep_dma_memcpy = dma_chan_prep_dma_memcpy;
+ dw->dma.device_synchronize = dw_axi_dma_synchronize;
platform_set_drvdata(pdev, chip);
--
2.18.0
[PATCH v12 01/17] dt-bindings: dma: Add YAML schemas for dw-axi-dmac
YAML schemas Device Tree (DT) binding is the new format for DT to replace
the old format. Introduce YAML schemas DT binding for dw-axi-dmac and
remove the old version.
Signed-off-by: Sia Jee Heng
Reviewed-by: Eugeniy Paltsev
Reviewed-by: Rob Herring
---
.../bindings/dma/snps,dw-axi-dmac.txt | 39 --
.../bindings/dma/snps,dw-axi-dmac.yaml| 121 ++
2 files changed, 121 insertions(+), 39 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt
create mode 100644 Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt
b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt
deleted file mode 100644
index dbe160400adc..
--- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt
+++ /dev/null
@@ -1,39 +0,0 @@
-Synopsys DesignWare AXI DMA Controller
-
-Required properties:
-- compatible: "snps,axi-dma-1.01a"
-- reg: Address range of the DMAC registers. This should include
- all of the per-channel registers.
-- interrupt: Should contain the DMAC interrupt number.
-- dma-channels: Number of channels supported by hardware.
-- snps,dma-masters: Number of AXI masters supported by the hardware.
-- snps,data-width: Maximum AXI data width supported by hardware.
- (0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits)
-- snps,priority: Priority of channel. Array size is equal to the number of
- dma-channels. Priority value must be programmed within [0:dma-channels-1]
- range. (0 - minimum priority)
-- snps,block-size: Maximum block size supported by the controller channel.
- Array size is equal to the number of dma-channels.
-
-Optional properties:
-- snps,axi-max-burst-len: Restrict master AXI burst length by value specified
- in this property. If this property is missing the maximum AXI burst length
- supported by DMAC is used. [1:256]
-
-Example:
-
-dmac: dma-controller@8 {
- compatible = "snps,axi-dma-1.01a";
- reg = <0x8 0x400>;
- clocks = <_clk>, <_clk>;
- clock-names = "core-clk", "cfgr-clk";
- interrupt-parent = <>;
- interrupts = <27>;
-
- dma-channels = <4>;
- snps,dma-masters = <2>;
- snps,data-width = <3>;
- snps,block-size = <4096 4096 4096 4096>;
- snps,priority = <0 1 2 3>;
- snps,axi-max-burst-len = <16>;
-};
diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
new file mode 100644
index ..3d2515463d56
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
@@ -0,0 +1,121 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/snps,dw-axi-dmac.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Synopsys DesignWare AXI DMA Controller
+
+maintainers:
+ - Eugeniy Paltsev
+
+description:
+ Synopsys DesignWare AXI DMA Controller DT Binding
+
+allOf:
+ - $ref: "dma-controller.yaml#"
+
+properties:
+ compatible:
+enum:
+ - snps,axi-dma-1.01a
+
+ reg:
+items:
+ - description: Address range of the DMAC registers
+
+ reg-names:
+items:
+ - const: axidma_ctrl_regs
+
+ interrupts:
+maxItems: 1
+
+ clocks:
+items:
+ - description: Bus Clock
+ - description: Module Clock
+
+ clock-names:
+items:
+ - const: core-clk
+ - const: cfgr-clk
+
+ '#dma-cells':
+const: 1
+
+ dma-channels:
+minimum: 1
+maximum: 8
+
+ snps,dma-masters:
+description: |
+ Number of AXI masters supported by the hardware.
+$ref: /schemas/types.yaml#/definitions/uint32
+enum: [1, 2]
+
+ snps,data-width:
+description: |
+ AXI data width supported by hardware.
+ (0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits)
+$ref: /schemas/types.yaml#/definitions/uint32
+enum: [0, 1, 2, 3, 4, 5, 6]
+
+ snps,priority:
+description: |
+ Channel priority specifier associated with the DMA channels.
+$ref: /schemas/types.yaml#/definitions/uint32-array
+minItems: 1
+maxItems: 8
+
+ snps,block-size:
+description: |
+ Channel block size specifier associated with the DMA channels.
+$ref: /schemas/types.yaml#/definitions/uint32-array
+minItems: 1
+maxItems: 8
+
+ snps,axi-max-burst-len:
+description: |
+ Restrict master AXI burst length by value specified in this property.
+ If this property is missing the maximum AXI burst length supported by
+ DMAC is used.
+$ref: /schemas/types.yaml#/definitions/uint32
+minimum: 1
+maximum: 256
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - interrupts
+ - '#dma-cells'
+ - dma-channels
+ - snps,dma-masters
+ - snps,data-width
+ -
[PATCH v12 00/17] dmaengine: dw-axi-dmac: support Intel KeemBay AxiDMA
The below patch series are to support AxiDMA running on Intel KeemBay SoC. The base driver is dw-axi-dmac. This driver only support DMA memory copy transfers. Code refactoring is needed so that additional features can be supported. The features added in this patch series are: - Replacing Linked List with virtual descriptor management. - Remove unrelated hw desc stuff from dma memory pool. - Manage dma memory pool alloc/destroy based on channel activity. - Support dmaengine device_sync() callback. - Support dmaengine device_config(). - Support dmaengine device_prep_slave_sg(). - Support dmaengine device_prep_dma_cyclic(). - Support of_dma_controller_register(). - Support burst residue granularity. - Support Intel KeemBay AxiDMA registers. - Support Intel KeemBay AxiDMA device handshake. - Support Intel KeemBay AxiDMA BYTE and HALFWORD device operation. - Add constraint to Max segment size. - Virtually split the linked-list. This patch series are tested on Intel KeemBay platform. Eugeniy Paltsev has runtime tested this patch series on HSDK SoC/board. v12: - Fixed bot build error by adding HAS_IOMEM dependency to Kconfig. v11: - Fixed bot build warning. v10: - Rebased to kernel v5.11-rc4 - Added Reviewed-by and Tested-by tag from Eugeniy Paltsev. v9: - Logic checked on apb_regs inside the function. - Improved code scalability so that missing of apb_regs wouldn't failed the common callback functions. v8: - Rebased to kernel v5.11-rc1. - Added reviewed-by tag from Rob. v7: - Added 'allOf' and '$ref:dma-controller.yaml#' in DT binding. - Removed the dma-channels common description in DT binding. - Removed the default fields in DT binding. v6: - Removed 'allOf' cases in DT binding. - Added '>' at the end of the email address. - Removed additional '|' at the start of description. - Fixed space indent. - Added proper constraint in DT binding. - Removed second example in DT binding. v5: - Added comment to the Apb registers used by Intel KeemBay Soc. - Renamed "hs_num" to "handshake_num". - Conditional check for the compatible property and return error instead of printing warning. - Added patch 16th to virtually split the linked-list as per request from ALSA team. v4: - Fixed bot found errors running make_dt_binding_check. - Added minItems: 1 to the YAML schemas DT binding. - Updated "reg" field to the YAML schemas DT binding. v3: - Added additionalProperties: false to the YAML schemas DT binding. - Reordered patch sequence for patch 10th, 11th and 12th so that DT binding come first, follow by adding Intel KeemBay SoC registers and update .compatible field. - Checked txstate NULL condition. - Created helper function dw_axi_dma_set_hw_desc() to handle common code. v2: - Rebased to v5.10-rc1 kernel. - Added support for dmaengine device_config(). - Added support for dmaengine device_prep_slave_sg(). - Added support for dmaengine device_prep_dma_cyclic(). - Added support for of_dma_controller_register(). - Added support for burst residue granularity. - Added support for Intel KeemBay AxiDMA registers. - Added support for Intel KeemBay AxiDMA device handshake. - Added support for Intel KeemBay AxiDMA BYTE and HALFWORD device operation. - Added constraint to Max segment size. v1: - Initial version. Patch on top of dw-axi-dma driver. This version improve the descriptor management by replacing Linked List Item (LLI) with virtual descriptor management, only allocate hardware LLI memories from DMA memory pool, manage DMA memory pool alloc/destroy based on channel activity and to support device_sync callback. Sia Jee Heng (17): dt-bindings: dma: Add YAML schemas for dw-axi-dmac dmaengine: dw-axi-dmac: simplify descriptor management dmaengine: dw-axi-dmac: move dma_pool_create() to alloc_chan_resources() dmaengine: dw-axi-dmac: Add device_synchronize() callback dmaengine: dw-axi-dmac: Add device_config operation dmaengine: dw-axi-dmac: Support device_prep_slave_sg dmaegine: dw-axi-dmac: Support device_prep_dma_cyclic() dmaengine: dw-axi-dmac: Support of_dma_controller_register() dmaengine: dw-axi-dmac: Support burst residue granularity dt-binding: dma: dw-axi-dmac: Add support for Intel KeemBay AxiDMA dmaengine: dw-axi-dmac: Add Intel KeemBay DMA register fields dmaengine: drivers: Kconfig: add HAS_IOMEM dependency to DW_AXI_DMAC dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA support dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA handshake dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA BYTE and HALFWORD registers dmaengine: dw-axi-dmac: Set constraint to the Max segment size dmaengine: dw-axi-dmac: Virtually split the linked-list .../bindings/dma/snps,dw-axi-dmac.txt | 39 - .../bindings/dma/snps,dw-axi-dmac.yaml| 126 drivers/dma/Kconfig | 1 + .../dma/dw-axi-dmac/dw-axi-dmac-platform.c| 696 +++--- drivers/dma/dw-axi-dmac/dw-axi-dmac.h
[PATCH v12 02/17] dmaengine: dw-axi-dmac: simplify descriptor management
Simplify and refactor the descriptor management by removing the redundant
Linked List Item (LLI) queue control logic from the AxiDMA driver.
The descriptor is split into virtual descriptor and hardware LLI so that
only hardware LLI memories are allocated from the DMA memory pool.
Up to 64 descriptors can be allocated within a PAGE_SIZE compare to 16
descriptors in previous version. This solves the problem where an
ALSA driver expects more than 16 DMA descriptors to run.
Signed-off-by: Sia Jee Heng
Reviewed-by: Andy Shevchenko
Reviewed-by: Eugeniy Paltsev
Tested-by: Eugeniy Paltsev
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c| 164 ++
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 9 +-
2 files changed, 102 insertions(+), 71 deletions(-)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index e164f3295f5d..350968baaf88 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -21,6 +21,7 @@
#include
#include
#include
+#include
#include
#include "dw-axi-dmac.h"
@@ -195,43 +196,58 @@ static inline const char *axi_chan_name(struct
axi_dma_chan *chan)
return dma_chan_name(>vc.chan);
}
-static struct axi_dma_desc *axi_desc_get(struct axi_dma_chan *chan)
+static struct axi_dma_desc *axi_desc_alloc(u32 num)
{
- struct dw_axi_dma *dw = chan->chip->dw;
struct axi_dma_desc *desc;
+
+ desc = kzalloc(sizeof(*desc), GFP_NOWAIT);
+ if (!desc)
+ return NULL;
+
+ desc->hw_desc = kcalloc(num, sizeof(*desc->hw_desc), GFP_NOWAIT);
+ if (!desc->hw_desc) {
+ kfree(desc);
+ return NULL;
+ }
+
+ return desc;
+}
+
+static struct axi_dma_lli *axi_desc_get(struct axi_dma_chan *chan,
+ dma_addr_t *addr)
+{
+ struct dw_axi_dma *dw = chan->chip->dw;
+ struct axi_dma_lli *lli;
dma_addr_t phys;
- desc = dma_pool_zalloc(dw->desc_pool, GFP_NOWAIT, );
- if (unlikely(!desc)) {
+ lli = dma_pool_zalloc(dw->desc_pool, GFP_NOWAIT, );
+ if (unlikely(!lli)) {
dev_err(chan2dev(chan), "%s: not enough descriptors
available\n",
axi_chan_name(chan));
return NULL;
}
atomic_inc(>descs_allocated);
- INIT_LIST_HEAD(>xfer_list);
- desc->vd.tx.phys = phys;
- desc->chan = chan;
+ *addr = phys;
- return desc;
+ return lli;
}
static void axi_desc_put(struct axi_dma_desc *desc)
{
struct axi_dma_chan *chan = desc->chan;
struct dw_axi_dma *dw = chan->chip->dw;
- struct axi_dma_desc *child, *_next;
- unsigned int descs_put = 0;
+ int count = atomic_read(>descs_allocated);
+ struct axi_dma_hw_desc *hw_desc;
+ int descs_put;
- list_for_each_entry_safe(child, _next, >xfer_list, xfer_list) {
- list_del(>xfer_list);
- dma_pool_free(dw->desc_pool, child, child->vd.tx.phys);
- descs_put++;
+ for (descs_put = 0; descs_put < count; descs_put++) {
+ hw_desc = >hw_desc[descs_put];
+ dma_pool_free(dw->desc_pool, hw_desc->lli, hw_desc->llp);
}
- dma_pool_free(dw->desc_pool, desc, desc->vd.tx.phys);
- descs_put++;
-
+ kfree(desc->hw_desc);
+ kfree(desc);
atomic_sub(descs_put, >descs_allocated);
dev_vdbg(chan2dev(chan), "%s: %d descs put, %d still allocated\n",
axi_chan_name(chan), descs_put,
@@ -258,9 +274,9 @@ dma_chan_tx_status(struct dma_chan *dchan, dma_cookie_t
cookie,
return ret;
}
-static void write_desc_llp(struct axi_dma_desc *desc, dma_addr_t adr)
+static void write_desc_llp(struct axi_dma_hw_desc *desc, dma_addr_t adr)
{
- desc->lli.llp = cpu_to_le64(adr);
+ desc->lli->llp = cpu_to_le64(adr);
}
static void write_chan_llp(struct axi_dma_chan *chan, dma_addr_t adr)
@@ -295,7 +311,7 @@ static void axi_chan_block_xfer_start(struct axi_dma_chan
*chan,
DWAXIDMAC_HS_SEL_HW << CH_CFG_H_HS_SEL_SRC_POS);
axi_chan_iowrite32(chan, CH_CFG_H, reg);
- write_chan_llp(chan, first->vd.tx.phys | lms);
+ write_chan_llp(chan, first->hw_desc[0].llp | lms);
irq_mask = DWAXIDMAC_IRQ_DMA_TRF | DWAXIDMAC_IRQ_ALL_ERR;
axi_chan_irq_sig_set(chan, irq_mask);
@@ -378,67 +394,78 @@ static void dma_chan_free_chan_resources(struct dma_chan
*dchan)
* transfer and completes the DMA transfer operation at the end of current
* block transfer.
*/
-static void set_desc_last(struct axi_dma_desc *desc)
+static void set_desc_last(struct axi_dma_hw_desc *desc)
{
u32 val;
- val = le32_to_cpu(desc->lli.ctl_
[PATCH v11 00/16] dmaengine: dw-axi-dmac: support Intel KeemBay AxiDMA
The below patch series are to support AxiDMA running on Intel KeemBay SoC. The base driver is dw-axi-dmac. This driver only support DMA memory copy transfers. Code refactoring is needed so that additional features can be supported. The features added in this patch series are: - Replacing Linked List with virtual descriptor management. - Remove unrelated hw desc stuff from dma memory pool. - Manage dma memory pool alloc/destroy based on channel activity. - Support dmaengine device_sync() callback. - Support dmaengine device_config(). - Support dmaengine device_prep_slave_sg(). - Support dmaengine device_prep_dma_cyclic(). - Support of_dma_controller_register(). - Support burst residue granularity. - Support Intel KeemBay AxiDMA registers. - Support Intel KeemBay AxiDMA device handshake. - Support Intel KeemBay AxiDMA BYTE and HALFWORD device operation. - Add constraint to Max segment size. - Virtually split the linked-list. This patch series are tested on Intel KeemBay platform. Eugeniy Paltsev has runtime tested this patch series on HSDK SoC/board. v11: - Fixed bot build warning. v10: - Rebased to kernel v5.11-rc4 - Added Reviewed-by and Tested-by tag from Eugeniy Paltsev. v9: - Logic checked on apb_regs inside the function. - Improved code scalability so that missing of apb_regs wouldn't failed the common callback functions. v8: - Rebased to kernel v5.11-rc1. - Added reviewed-by tag from Rob. v7: - Added 'allOf' and '$ref:dma-controller.yaml#' in DT binding. - Removed the dma-channels common description in DT binding. - Removed the default fields in DT binding. v6: - Removed 'allOf' cases in DT binding. - Added '>' at the end of the email address. - Removed additional '|' at the start of description. - Fixed space indent. - Added proper constraint in DT binding. - Removed second example in DT binding. v5: - Added comment to the Apb registers used by Intel KeemBay Soc. - Renamed "hs_num" to "handshake_num". - Conditional check for the compatible property and return error instead of printing warning. - Added patch 16th to virtually split the linked-list as per request from ALSA team. v4: - Fixed bot found errors running make_dt_binding_check. - Added minItems: 1 to the YAML schemas DT binding. - Updated "reg" field to the YAML schemas DT binding. v3: - Added additionalProperties: false to the YAML schemas DT binding. - Reordered patch sequence for patch 10th, 11th and 12th so that DT binding come first, follow by adding Intel KeemBay SoC registers and update .compatible field. - Checked txstate NULL condition. - Created helper function dw_axi_dma_set_hw_desc() to handle common code. v2: - Rebased to v5.10-rc1 kernel. - Added support for dmaengine device_config(). - Added support for dmaengine device_prep_slave_sg(). - Added support for dmaengine device_prep_dma_cyclic(). - Added support for of_dma_controller_register(). - Added support for burst residue granularity. - Added support for Intel KeemBay AxiDMA registers. - Added support for Intel KeemBay AxiDMA device handshake. - Added support for Intel KeemBay AxiDMA BYTE and HALFWORD device operation. - Added constraint to Max segment size. v1: - Initial version. Patch on top of dw-axi-dma driver. This version improve the descriptor management by replacing Linked List Item (LLI) with virtual descriptor management, only allocate hardware LLI memories from DMA memory pool, manage DMA memory pool alloc/destroy based on channel activity and to support device_sync callback. Sia Jee Heng (16): dt-bindings: dma: Add YAML schemas for dw-axi-dmac dmaengine: dw-axi-dmac: simplify descriptor management dmaengine: dw-axi-dmac: move dma_pool_create() to alloc_chan_resources() dmaengine: dw-axi-dmac: Add device_synchronize() callback dmaengine: dw-axi-dmac: Add device_config operation dmaengine: dw-axi-dmac: Support device_prep_slave_sg dmaegine: dw-axi-dmac: Support device_prep_dma_cyclic() dmaengine: dw-axi-dmac: Support of_dma_controller_register() dmaengine: dw-axi-dmac: Support burst residue granularity dt-binding: dma: dw-axi-dmac: Add support for Intel KeemBay AxiDMA dmaengine: dw-axi-dmac: Add Intel KeemBay DMA register fields dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA support dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA handshake dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA BYTE and HALFWORD registers dmaengine: dw-axi-dmac: Set constraint to the Max segment size dmaengine: dw-axi-dmac: Virtually split the linked-list .../bindings/dma/snps,dw-axi-dmac.txt | 39 - .../bindings/dma/snps,dw-axi-dmac.yaml| 126 .../dma/dw-axi-dmac/dw-axi-dmac-platform.c| 696 +++--- drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 34 +- 4 files changed, 763 insertions(+), 132 deletions(-) delete mode 100644 Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt create mode 100644 Documentation/devicetree/bindings/dma/sn
[PATCH v11 16/16] dmaengine: dw-axi-dmac: Virtually split the linked-list
AxiDMA driver exposed the dma_set_max_seg_size() to the DMAENGINE.
It shall helps the DMA clients to create size-optimized linked-list
for the controller.
However, there are certain situations where DMA client might not be
abled to benefit from the dma_get_max_seg_size() if the segment size
can't meet the nature of the DMA client's operation.
In the case of ALSA operation, ALSA application and driver expecting
to run in a period of larger than 10ms regardless of the bit depth.
With this large period, there is a strong request to split the linked-list
in the AxiDMA driver.
Signed-off-by: Sia Jee Heng
Reviewed-by: Eugeniy Paltsev
Tested-by: Eugeniy Paltsev
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c| 111 ++
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 1 +
2 files changed, 92 insertions(+), 20 deletions(-)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 88d4923dee6c..ac3d81b72a15 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -581,6 +581,11 @@ static int dw_axi_dma_set_hw_desc(struct axi_dma_chan
*chan,
if (mem_width > DWAXIDMAC_TRANS_WIDTH_32)
mem_width = DWAXIDMAC_TRANS_WIDTH_32;
+ if (!IS_ALIGNED(mem_addr, 4)) {
+ dev_err(chan->chip->dev, "invalid buffer alignment\n");
+ return -EINVAL;
+ }
+
switch (chan->direction) {
case DMA_MEM_TO_DEV:
reg_width = __ffs(chan->config.dst_addr_width);
@@ -642,6 +647,35 @@ static int dw_axi_dma_set_hw_desc(struct axi_dma_chan
*chan,
return 0;
}
+static size_t calculate_block_len(struct axi_dma_chan *chan,
+ dma_addr_t dma_addr, size_t buf_len,
+ enum dma_transfer_direction direction)
+{
+ u32 data_width, reg_width, mem_width;
+ size_t axi_block_ts, block_len;
+
+ axi_block_ts = chan->chip->dw->hdata->block_size[chan->id];
+
+ switch (direction) {
+ case DMA_MEM_TO_DEV:
+ data_width = BIT(chan->chip->dw->hdata->m_data_width);
+ mem_width = __ffs(data_width | dma_addr | buf_len);
+ if (mem_width > DWAXIDMAC_TRANS_WIDTH_32)
+ mem_width = DWAXIDMAC_TRANS_WIDTH_32;
+
+ block_len = axi_block_ts << mem_width;
+ break;
+ case DMA_DEV_TO_MEM:
+ reg_width = __ffs(chan->config.src_addr_width);
+ block_len = axi_block_ts << reg_width;
+ break;
+ default:
+ block_len = 0;
+ }
+
+ return block_len;
+}
+
static struct dma_async_tx_descriptor *
dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan, dma_addr_t dma_addr,
size_t buf_len, size_t period_len,
@@ -652,13 +686,27 @@ dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan,
dma_addr_t dma_addr,
struct axi_dma_hw_desc *hw_desc = NULL;
struct axi_dma_desc *desc = NULL;
dma_addr_t src_addr = dma_addr;
- u32 num_periods = buf_len / period_len;
+ u32 num_periods, num_segments;
+ size_t axi_block_len;
+ u32 total_segments;
+ u32 segment_len;
unsigned int i;
int status;
u64 llp = 0;
u8 lms = 0; /* Select AXI0 master for LLI fetching */
- desc = axi_desc_alloc(num_periods);
+ num_periods = buf_len / period_len;
+
+ axi_block_len = calculate_block_len(chan, dma_addr, buf_len, direction);
+ if (axi_block_len == 0)
+ return NULL;
+
+ num_segments = DIV_ROUND_UP(period_len, axi_block_len);
+ segment_len = DIV_ROUND_UP(period_len, num_segments);
+
+ total_segments = num_periods * num_segments;
+
+ desc = axi_desc_alloc(total_segments);
if (unlikely(!desc))
goto err_desc_get;
@@ -666,12 +714,13 @@ dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan,
dma_addr_t dma_addr,
desc->chan = chan;
chan->cyclic = true;
desc->length = 0;
+ desc->period_len = period_len;
- for (i = 0; i < num_periods; i++) {
+ for (i = 0; i < total_segments; i++) {
hw_desc = >hw_desc[i];
status = dw_axi_dma_set_hw_desc(chan, hw_desc, src_addr,
- period_len);
+ segment_len);
if (status < 0)
goto err_desc_get;
@@ -681,17 +730,17 @@ dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan,
dma_addr_t dma_addr,
*/
set_desc_last(hw_desc);
- src_addr += period_len;
+ src_addr += segment_len;
}
llp = desc->hw_desc[0].llp;
/* Managed transfer list */
[PATCH v11 12/16] dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA support
Add support for Intel KeemBay AxiDMA to the .compatible field.
The AxiDMA Apb region will be accessible if the compatible string
matches the "intel,kmb-axi-dma".
Signed-off-by: Sia Jee Heng
Reviewed-by: Andy Shevchenko
Reviewed-by: Eugeniy Paltsev
Tested-by: Eugeniy Paltsev
---
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 830d3de76abd..062d27c61983 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -1160,6 +1160,7 @@ static int parse_device_properties(struct axi_dma_chip
*chip)
static int dw_probe(struct platform_device *pdev)
{
+ struct device_node *node = pdev->dev.of_node;
struct axi_dma_chip *chip;
struct resource *mem;
struct dw_axi_dma *dw;
@@ -1192,6 +1193,12 @@ static int dw_probe(struct platform_device *pdev)
if (IS_ERR(chip->regs))
return PTR_ERR(chip->regs);
+ if (of_device_is_compatible(node, "intel,kmb-axi-dma")) {
+ chip->apb_regs = devm_platform_ioremap_resource(pdev, 1);
+ if (IS_ERR(chip->apb_regs))
+ return PTR_ERR(chip->apb_regs);
+ }
+
chip->core_clk = devm_clk_get(chip->dev, "core-clk");
if (IS_ERR(chip->core_clk))
return PTR_ERR(chip->core_clk);
@@ -1336,6 +1343,7 @@ static const struct dev_pm_ops dw_axi_dma_pm_ops = {
static const struct of_device_id dw_dma_of_id_table[] = {
{ .compatible = "snps,axi-dma-1.01a" },
+ { .compatible = "intel,kmb-axi-dma" },
{}
};
MODULE_DEVICE_TABLE(of, dw_dma_of_id_table);
--
2.18.0
[PATCH v11 01/16] dt-bindings: dma: Add YAML schemas for dw-axi-dmac
YAML schemas Device Tree (DT) binding is the new format for DT to replace
the old format. Introduce YAML schemas DT binding for dw-axi-dmac and
remove the old version.
Signed-off-by: Sia Jee Heng
Reviewed-by: Eugeniy Paltsev
Reviewed-by: Rob Herring
---
.../bindings/dma/snps,dw-axi-dmac.txt | 39 --
.../bindings/dma/snps,dw-axi-dmac.yaml| 121 ++
2 files changed, 121 insertions(+), 39 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt
create mode 100644 Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt
b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt
deleted file mode 100644
index dbe160400adc..
--- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt
+++ /dev/null
@@ -1,39 +0,0 @@
-Synopsys DesignWare AXI DMA Controller
-
-Required properties:
-- compatible: "snps,axi-dma-1.01a"
-- reg: Address range of the DMAC registers. This should include
- all of the per-channel registers.
-- interrupt: Should contain the DMAC interrupt number.
-- dma-channels: Number of channels supported by hardware.
-- snps,dma-masters: Number of AXI masters supported by the hardware.
-- snps,data-width: Maximum AXI data width supported by hardware.
- (0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits)
-- snps,priority: Priority of channel. Array size is equal to the number of
- dma-channels. Priority value must be programmed within [0:dma-channels-1]
- range. (0 - minimum priority)
-- snps,block-size: Maximum block size supported by the controller channel.
- Array size is equal to the number of dma-channels.
-
-Optional properties:
-- snps,axi-max-burst-len: Restrict master AXI burst length by value specified
- in this property. If this property is missing the maximum AXI burst length
- supported by DMAC is used. [1:256]
-
-Example:
-
-dmac: dma-controller@8 {
- compatible = "snps,axi-dma-1.01a";
- reg = <0x8 0x400>;
- clocks = <_clk>, <_clk>;
- clock-names = "core-clk", "cfgr-clk";
- interrupt-parent = <>;
- interrupts = <27>;
-
- dma-channels = <4>;
- snps,dma-masters = <2>;
- snps,data-width = <3>;
- snps,block-size = <4096 4096 4096 4096>;
- snps,priority = <0 1 2 3>;
- snps,axi-max-burst-len = <16>;
-};
diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
new file mode 100644
index ..3d2515463d56
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
@@ -0,0 +1,121 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/snps,dw-axi-dmac.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Synopsys DesignWare AXI DMA Controller
+
+maintainers:
+ - Eugeniy Paltsev
+
+description:
+ Synopsys DesignWare AXI DMA Controller DT Binding
+
+allOf:
+ - $ref: "dma-controller.yaml#"
+
+properties:
+ compatible:
+enum:
+ - snps,axi-dma-1.01a
+
+ reg:
+items:
+ - description: Address range of the DMAC registers
+
+ reg-names:
+items:
+ - const: axidma_ctrl_regs
+
+ interrupts:
+maxItems: 1
+
+ clocks:
+items:
+ - description: Bus Clock
+ - description: Module Clock
+
+ clock-names:
+items:
+ - const: core-clk
+ - const: cfgr-clk
+
+ '#dma-cells':
+const: 1
+
+ dma-channels:
+minimum: 1
+maximum: 8
+
+ snps,dma-masters:
+description: |
+ Number of AXI masters supported by the hardware.
+$ref: /schemas/types.yaml#/definitions/uint32
+enum: [1, 2]
+
+ snps,data-width:
+description: |
+ AXI data width supported by hardware.
+ (0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits)
+$ref: /schemas/types.yaml#/definitions/uint32
+enum: [0, 1, 2, 3, 4, 5, 6]
+
+ snps,priority:
+description: |
+ Channel priority specifier associated with the DMA channels.
+$ref: /schemas/types.yaml#/definitions/uint32-array
+minItems: 1
+maxItems: 8
+
+ snps,block-size:
+description: |
+ Channel block size specifier associated with the DMA channels.
+$ref: /schemas/types.yaml#/definitions/uint32-array
+minItems: 1
+maxItems: 8
+
+ snps,axi-max-burst-len:
+description: |
+ Restrict master AXI burst length by value specified in this property.
+ If this property is missing the maximum AXI burst length supported by
+ DMAC is used.
+$ref: /schemas/types.yaml#/definitions/uint32
+minimum: 1
+maximum: 256
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - interrupts
+ - '#dma-cells'
+ - dma-channels
+ - snps,dma-masters
+ - snps,data-width
+ -
[PATCH v11 02/16] dmaengine: dw-axi-dmac: simplify descriptor management
Simplify and refactor the descriptor management by removing the redundant
Linked List Item (LLI) queue control logic from the AxiDMA driver.
The descriptor is split into virtual descriptor and hardware LLI so that
only hardware LLI memories are allocated from the DMA memory pool.
Up to 64 descriptors can be allocated within a PAGE_SIZE compare to 16
descriptors in previous version. This solves the problem where an
ALSA driver expects more than 16 DMA descriptors to run.
Signed-off-by: Sia Jee Heng
Reviewed-by: Andy Shevchenko
Reviewed-by: Eugeniy Paltsev
Tested-by: Eugeniy Paltsev
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c| 164 ++
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 9 +-
2 files changed, 102 insertions(+), 71 deletions(-)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index e164f3295f5d..350968baaf88 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -21,6 +21,7 @@
#include
#include
#include
+#include
#include
#include "dw-axi-dmac.h"
@@ -195,43 +196,58 @@ static inline const char *axi_chan_name(struct
axi_dma_chan *chan)
return dma_chan_name(>vc.chan);
}
-static struct axi_dma_desc *axi_desc_get(struct axi_dma_chan *chan)
+static struct axi_dma_desc *axi_desc_alloc(u32 num)
{
- struct dw_axi_dma *dw = chan->chip->dw;
struct axi_dma_desc *desc;
+
+ desc = kzalloc(sizeof(*desc), GFP_NOWAIT);
+ if (!desc)
+ return NULL;
+
+ desc->hw_desc = kcalloc(num, sizeof(*desc->hw_desc), GFP_NOWAIT);
+ if (!desc->hw_desc) {
+ kfree(desc);
+ return NULL;
+ }
+
+ return desc;
+}
+
+static struct axi_dma_lli *axi_desc_get(struct axi_dma_chan *chan,
+ dma_addr_t *addr)
+{
+ struct dw_axi_dma *dw = chan->chip->dw;
+ struct axi_dma_lli *lli;
dma_addr_t phys;
- desc = dma_pool_zalloc(dw->desc_pool, GFP_NOWAIT, );
- if (unlikely(!desc)) {
+ lli = dma_pool_zalloc(dw->desc_pool, GFP_NOWAIT, );
+ if (unlikely(!lli)) {
dev_err(chan2dev(chan), "%s: not enough descriptors
available\n",
axi_chan_name(chan));
return NULL;
}
atomic_inc(>descs_allocated);
- INIT_LIST_HEAD(>xfer_list);
- desc->vd.tx.phys = phys;
- desc->chan = chan;
+ *addr = phys;
- return desc;
+ return lli;
}
static void axi_desc_put(struct axi_dma_desc *desc)
{
struct axi_dma_chan *chan = desc->chan;
struct dw_axi_dma *dw = chan->chip->dw;
- struct axi_dma_desc *child, *_next;
- unsigned int descs_put = 0;
+ int count = atomic_read(>descs_allocated);
+ struct axi_dma_hw_desc *hw_desc;
+ int descs_put;
- list_for_each_entry_safe(child, _next, >xfer_list, xfer_list) {
- list_del(>xfer_list);
- dma_pool_free(dw->desc_pool, child, child->vd.tx.phys);
- descs_put++;
+ for (descs_put = 0; descs_put < count; descs_put++) {
+ hw_desc = >hw_desc[descs_put];
+ dma_pool_free(dw->desc_pool, hw_desc->lli, hw_desc->llp);
}
- dma_pool_free(dw->desc_pool, desc, desc->vd.tx.phys);
- descs_put++;
-
+ kfree(desc->hw_desc);
+ kfree(desc);
atomic_sub(descs_put, >descs_allocated);
dev_vdbg(chan2dev(chan), "%s: %d descs put, %d still allocated\n",
axi_chan_name(chan), descs_put,
@@ -258,9 +274,9 @@ dma_chan_tx_status(struct dma_chan *dchan, dma_cookie_t
cookie,
return ret;
}
-static void write_desc_llp(struct axi_dma_desc *desc, dma_addr_t adr)
+static void write_desc_llp(struct axi_dma_hw_desc *desc, dma_addr_t adr)
{
- desc->lli.llp = cpu_to_le64(adr);
+ desc->lli->llp = cpu_to_le64(adr);
}
static void write_chan_llp(struct axi_dma_chan *chan, dma_addr_t adr)
@@ -295,7 +311,7 @@ static void axi_chan_block_xfer_start(struct axi_dma_chan
*chan,
DWAXIDMAC_HS_SEL_HW << CH_CFG_H_HS_SEL_SRC_POS);
axi_chan_iowrite32(chan, CH_CFG_H, reg);
- write_chan_llp(chan, first->vd.tx.phys | lms);
+ write_chan_llp(chan, first->hw_desc[0].llp | lms);
irq_mask = DWAXIDMAC_IRQ_DMA_TRF | DWAXIDMAC_IRQ_ALL_ERR;
axi_chan_irq_sig_set(chan, irq_mask);
@@ -378,67 +394,78 @@ static void dma_chan_free_chan_resources(struct dma_chan
*dchan)
* transfer and completes the DMA transfer operation at the end of current
* block transfer.
*/
-static void set_desc_last(struct axi_dma_desc *desc)
+static void set_desc_last(struct axi_dma_hw_desc *desc)
{
u32 val;
- val = le32_to_cpu(desc->lli.ctl_
[PATCH v11 03/16] dmaengine: dw-axi-dmac: move dma_pool_create() to alloc_chan_resources()
The DMA memory block is created at driver load time and exist for
device lifetime. Move the dma_pool_create() to the ->chan_resource()
callback function allowing the DMA memory blocks to be created as needed
and destroyed when the channel is freed.
Signed-off-by: Sia Jee Heng
Reviewed-by: Andy Shevchenko
Reviewed-by: Eugeniy Paltsev
Tested-by: Eugeniy Paltsev
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c| 24 ++-
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 2 +-
2 files changed, 14 insertions(+), 12 deletions(-)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 350968baaf88..3737e1c3c793 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -216,11 +216,10 @@ static struct axi_dma_desc *axi_desc_alloc(u32 num)
static struct axi_dma_lli *axi_desc_get(struct axi_dma_chan *chan,
dma_addr_t *addr)
{
- struct dw_axi_dma *dw = chan->chip->dw;
struct axi_dma_lli *lli;
dma_addr_t phys;
- lli = dma_pool_zalloc(dw->desc_pool, GFP_NOWAIT, );
+ lli = dma_pool_zalloc(chan->desc_pool, GFP_NOWAIT, );
if (unlikely(!lli)) {
dev_err(chan2dev(chan), "%s: not enough descriptors
available\n",
axi_chan_name(chan));
@@ -236,14 +235,13 @@ static struct axi_dma_lli *axi_desc_get(struct
axi_dma_chan *chan,
static void axi_desc_put(struct axi_dma_desc *desc)
{
struct axi_dma_chan *chan = desc->chan;
- struct dw_axi_dma *dw = chan->chip->dw;
int count = atomic_read(>descs_allocated);
struct axi_dma_hw_desc *hw_desc;
int descs_put;
for (descs_put = 0; descs_put < count; descs_put++) {
hw_desc = >hw_desc[descs_put];
- dma_pool_free(dw->desc_pool, hw_desc->lli, hw_desc->llp);
+ dma_pool_free(chan->desc_pool, hw_desc->lli, hw_desc->llp);
}
kfree(desc->hw_desc);
@@ -360,6 +358,15 @@ static int dma_chan_alloc_chan_resources(struct dma_chan
*dchan)
return -EBUSY;
}
+ /* LLI address must be aligned to a 64-byte boundary */
+ chan->desc_pool = dma_pool_create(dev_name(chan2dev(chan)),
+ chan->chip->dev,
+ sizeof(struct axi_dma_lli),
+ 64, 0);
+ if (!chan->desc_pool) {
+ dev_err(chan2dev(chan), "No memory for descriptors\n");
+ return -ENOMEM;
+ }
dev_vdbg(dchan2dev(dchan), "%s: allocating\n", axi_chan_name(chan));
pm_runtime_get(chan->chip->dev);
@@ -381,6 +388,8 @@ static void dma_chan_free_chan_resources(struct dma_chan
*dchan)
vchan_free_chan_resources(>vc);
+ dma_pool_destroy(chan->desc_pool);
+ chan->desc_pool = NULL;
dev_vdbg(dchan2dev(dchan),
"%s: free resources, descriptor still allocated: %u\n",
axi_chan_name(chan), atomic_read(>descs_allocated));
@@ -896,13 +905,6 @@ static int dw_probe(struct platform_device *pdev)
if (ret)
return ret;
- /* Lli address must be aligned to a 64-byte boundary */
- dw->desc_pool = dmam_pool_create(KBUILD_MODNAME, chip->dev,
-sizeof(struct axi_dma_lli), 64, 0);
- if (!dw->desc_pool) {
- dev_err(chip->dev, "No memory for descriptors dma pool\n");
- return -ENOMEM;
- }
INIT_LIST_HEAD(>dma.channels);
for (i = 0; i < hdata->nr_channels; i++) {
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
index 41e775e6e593..f886b2bb75de 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
@@ -39,6 +39,7 @@ struct axi_dma_chan {
u8 id;
atomic_tdescs_allocated;
+ struct dma_pool *desc_pool;
struct virt_dma_chanvc;
struct axi_dma_desc *desc;
@@ -49,7 +50,6 @@ struct axi_dma_chan {
struct dw_axi_dma {
struct dma_device dma;
struct dw_axi_dma_hcfg *hdata;
- struct dma_pool *desc_pool;
/* channels */
struct axi_dma_chan *chan;
--
2.18.0
[PATCH v11 07/16] dmaegine: dw-axi-dmac: Support device_prep_dma_cyclic()
Add support for device_prep_dma_cyclic() callback function to benefit
DMA cyclic client, for example ALSA.
Existing AxiDMA driver only support data transfer between memory to memory.
Data transfer between device to memory and memory to device in cyclic mode
would failed if this interface is not supported by the AxiDMA driver.
Signed-off-by: Sia Jee Heng
Reviewed-by: Andy Shevchenko
Reviewed-by: Eugeniy Paltsev
Tested-by: Eugeniy Paltsev
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c| 111 --
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 2 +
2 files changed, 106 insertions(+), 7 deletions(-)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 7ff30b0f44ed..a76299360f69 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -15,6 +15,8 @@
#include
#include
#include
+#include
+#include
#include
#include
#include
@@ -549,6 +551,64 @@ static int dw_axi_dma_set_hw_desc(struct axi_dma_chan
*chan,
return 0;
}
+static struct dma_async_tx_descriptor *
+dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan, dma_addr_t dma_addr,
+ size_t buf_len, size_t period_len,
+ enum dma_transfer_direction direction,
+ unsigned long flags)
+{
+ struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
+ struct axi_dma_hw_desc *hw_desc = NULL;
+ struct axi_dma_desc *desc = NULL;
+ dma_addr_t src_addr = dma_addr;
+ u32 num_periods = buf_len / period_len;
+ unsigned int i;
+ int status;
+ u64 llp = 0;
+ u8 lms = 0; /* Select AXI0 master for LLI fetching */
+
+ desc = axi_desc_alloc(num_periods);
+ if (unlikely(!desc))
+ goto err_desc_get;
+
+ chan->direction = direction;
+ desc->chan = chan;
+ chan->cyclic = true;
+
+ for (i = 0; i < num_periods; i++) {
+ hw_desc = >hw_desc[i];
+
+ status = dw_axi_dma_set_hw_desc(chan, hw_desc, src_addr,
+ period_len);
+ if (status < 0)
+ goto err_desc_get;
+
+ /* Set end-of-link to the linked descriptor, so that cyclic
+* callback function can be triggered during interrupt.
+*/
+ set_desc_last(hw_desc);
+
+ src_addr += period_len;
+ }
+
+ llp = desc->hw_desc[0].llp;
+
+ /* Managed transfer list */
+ do {
+ hw_desc = >hw_desc[--num_periods];
+ write_desc_llp(hw_desc, llp | lms);
+ llp = hw_desc->llp;
+ } while (num_periods);
+
+ return vchan_tx_prep(>vc, >vd, flags);
+
+err_desc_get:
+ if (desc)
+ axi_desc_put(desc);
+
+ return NULL;
+}
+
static struct dma_async_tx_descriptor *
dw_axi_dma_chan_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl,
unsigned int sg_len,
@@ -773,8 +833,13 @@ static noinline void axi_chan_handle_err(struct
axi_dma_chan *chan, u32 status)
static void axi_chan_block_xfer_complete(struct axi_dma_chan *chan)
{
+ int count = atomic_read(>descs_allocated);
+ struct axi_dma_hw_desc *hw_desc;
+ struct axi_dma_desc *desc;
struct virt_dma_desc *vd;
unsigned long flags;
+ u64 llp;
+ int i;
spin_lock_irqsave(>vc.lock, flags);
if (unlikely(axi_chan_is_hw_enable(chan))) {
@@ -785,12 +850,32 @@ static void axi_chan_block_xfer_complete(struct
axi_dma_chan *chan)
/* The completed descriptor currently is in the head of vc list */
vd = vchan_next_desc(>vc);
- /* Remove the completed descriptor from issued list before completing */
- list_del(>node);
- vchan_cookie_complete(vd);
- /* Submit queued descriptors after processing the completed ones */
- axi_chan_start_first_queued(chan);
+ if (chan->cyclic) {
+ vchan_cyclic_callback(vd);
+ desc = vd_to_axi_desc(vd);
+ if (desc) {
+ llp = lo_hi_readq(chan->chan_regs + CH_LLP);
+ for (i = 0; i < count; i++) {
+ hw_desc = >hw_desc[i];
+ if (hw_desc->llp == llp) {
+ axi_chan_irq_clear(chan,
hw_desc->lli->status_lo);
+ hw_desc->lli->ctl_hi |=
CH_CTL_H_LLI_VALID;
+ desc->completed_blocks = i;
+ break;
+ }
+ }
+
+ axi_chan_enable(chan);
+ }
+ } else {
+
[PATCH v11 05/16] dmaengine: dw-axi-dmac: Add device_config operation
Add device_config() callback function so that the device address
can be passed to the dma driver.
DMA clients use this interface to pass in the device address to the
AxiDMA. Without this interface, data transfer between device to memory
and memory to device would failed.
Signed-off-by: Sia Jee Heng
Reviewed-by: Andy Shevchenko
Reviewed-by: Eugeniy Paltsev
Tested-by: Eugeniy Paltsev
---
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 11 +++
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 1 +
2 files changed, 12 insertions(+)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 241ab7a24e2a..eaa7c4c404ca 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -559,6 +559,16 @@ dma_chan_prep_dma_memcpy(struct dma_chan *dchan,
dma_addr_t dst_adr,
return NULL;
}
+static int dw_axi_dma_chan_slave_config(struct dma_chan *dchan,
+ struct dma_slave_config *config)
+{
+ struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
+
+ memcpy(>config, config, sizeof(*config));
+
+ return 0;
+}
+
static void axi_chan_dump_lli(struct axi_dma_chan *chan,
struct axi_dma_hw_desc *desc)
{
@@ -948,6 +958,7 @@ static int dw_probe(struct platform_device *pdev)
dw->dma.device_prep_dma_memcpy = dma_chan_prep_dma_memcpy;
dw->dma.device_synchronize = dw_axi_dma_synchronize;
+ dw->dma.device_config = dw_axi_dma_chan_slave_config;
platform_set_drvdata(pdev, chip);
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
index f886b2bb75de..a75b921d6b1a 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
@@ -43,6 +43,7 @@ struct axi_dma_chan {
struct virt_dma_chanvc;
struct axi_dma_desc *desc;
+ struct dma_slave_config config;
/* these other elements are all protected by vc.lock */
boolis_paused;
};
--
2.18.0
[PATCH v11 08/16] dmaengine: dw-axi-dmac: Support of_dma_controller_register()
Add support for of_dma_controller_register() so that DMA clients
can pass in device handshake number to the AxiDMA driver.
DMA clients shall code the device handshake number in the Device tree.
When DMA activities are needed, DMA clients shall invoke OF helper
function to pass in the device handshake number to the AxiDMA.
Without register to the of_dma_controller_register(), data transfer
between memory to device and device to memory operations would failed.
Signed-off-by: Sia Jee Heng
Reviewed-by: Andy Shevchenko
Reviewed-by: Eugeniy Paltsev
Tested-by: Eugeniy Paltsev
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c| 26 +++
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 1 +
2 files changed, 27 insertions(+)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index a76299360f69..a8b6c8c8ef58 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -20,6 +20,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -1044,6 +1045,22 @@ static int __maybe_unused axi_dma_runtime_resume(struct
device *dev)
return axi_dma_resume(chip);
}
+static struct dma_chan *dw_axi_dma_of_xlate(struct of_phandle_args *dma_spec,
+ struct of_dma *ofdma)
+{
+ struct dw_axi_dma *dw = ofdma->of_dma_data;
+ struct axi_dma_chan *chan;
+ struct dma_chan *dchan;
+
+ dchan = dma_get_any_slave_channel(>dma);
+ if (!dchan)
+ return NULL;
+
+ chan = dchan_to_axi_dma_chan(dchan);
+ chan->hw_handshake_num = dma_spec->args[0];
+ return dchan;
+}
+
static int parse_device_properties(struct axi_dma_chip *chip)
{
struct device *dev = chip->dev;
@@ -1233,6 +1250,13 @@ static int dw_probe(struct platform_device *pdev)
if (ret)
goto err_pm_disable;
+ /* Register with OF helpers for DMA lookups */
+ ret = of_dma_controller_register(pdev->dev.of_node,
+dw_axi_dma_of_xlate, dw);
+ if (ret < 0)
+ dev_warn(>dev,
+"Failed to register OF DMA controller, fallback to
MEM_TO_MEM mode\n");
+
dev_info(chip->dev, "DesignWare AXI DMA Controller, %d channels\n",
dw->hdata->nr_channels);
@@ -1266,6 +1290,8 @@ static int dw_remove(struct platform_device *pdev)
devm_free_irq(chip->dev, chip->irq, chip);
+ of_dma_controller_free(chip->dev->of_node);
+
list_for_each_entry_safe(chan, _chan, >dma.channels,
vc.chan.device_node) {
list_del(>vc.chan.device_node);
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
index a26b0a242a93..3498bef5453b 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
@@ -37,6 +37,7 @@ struct axi_dma_chan {
struct axi_dma_chip *chip;
void __iomem*chan_regs;
u8 id;
+ u8 hw_handshake_num;
atomic_tdescs_allocated;
struct dma_pool *desc_pool;
--
2.18.0
[PATCH v11 11/16] dmaengine: dw-axi-dmac: Add Intel KeemBay DMA register fields
Add support for Intel KeemBay DMA registers. These registers are required
to run data transfer between device to memory and memory to device on Intel
KeemBay SoC.
Signed-off-by: Sia Jee Heng
Reviewed-by: Andy Shevchenko
Reviewed-by: Eugeniy Paltsev
Tested-by: Eugeniy Paltsev
---
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
index 46baf93de617..3a357f7fda02 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
@@ -63,6 +63,7 @@ struct axi_dma_chip {
struct device *dev;
int irq;
void __iomem*regs;
+ void __iomem*apb_regs;
struct clk *core_clk;
struct clk *cfgr_clk;
struct dw_axi_dma *dw;
@@ -169,6 +170,19 @@ static inline struct axi_dma_chan
*dchan_to_axi_dma_chan(struct dma_chan *dchan)
#define CH_INTSIGNAL_ENA 0x090 /* R/W Chan Interrupt Signal Enable */
#define CH_INTCLEAR0x098 /* W Chan Interrupt Clear */
+/* These Apb registers are used by Intel KeemBay SoC */
+#define DMAC_APB_CFG 0x000 /* DMAC Apb Configuration Register */
+#define DMAC_APB_STAT 0x004 /* DMAC Apb Status Register */
+#define DMAC_APB_DEBUG_STAT_0 0x008 /* DMAC Apb Debug Status Register 0 */
+#define DMAC_APB_DEBUG_STAT_1 0x00C /* DMAC Apb Debug Status Register 1 */
+#define DMAC_APB_HW_HS_SEL_0 0x010 /* DMAC Apb HW HS register 0 */
+#define DMAC_APB_HW_HS_SEL_1 0x014 /* DMAC Apb HW HS register 1 */
+#define DMAC_APB_LPI 0x018 /* DMAC Apb Low Power Interface Reg */
+#define DMAC_APB_BYTE_WR_CH_EN 0x01C /* DMAC Apb Byte Write Enable */
+#define DMAC_APB_HALFWORD_WR_CH_EN 0x020 /* DMAC Halfword write enables */
+
+#define UNUSED_CHANNEL 0x3F /* Set unused DMA channel to 0x3F */
+#define MAX_BLOCK_SIZE 0x1000 /* 1024 blocks * 4 bytes data width */
/* DMAC_CFG */
#define DMAC_EN_POS0
--
2.18.0
[PATCH v11 13/16] dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA handshake
Add support for Intel KeemBay AxiDMA device handshake programming.
Device handshake number passed in to the AxiDMA shall be written to
the Intel KeemBay AxiDMA hardware handshake registers before DMA
operations are started.
Signed-off-by: Sia Jee Heng
Reviewed-by: Andy Shevchenko
Reviewed-by: Eugeniy Paltsev
Tested-by: Eugeniy Paltsev
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c| 50 +++
1 file changed, 50 insertions(+)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 062d27c61983..e19369f9365a 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -445,6 +445,48 @@ static void dma_chan_free_chan_resources(struct dma_chan
*dchan)
pm_runtime_put(chan->chip->dev);
}
+static void dw_axi_dma_set_hw_channel(struct axi_dma_chip *chip,
+ u32 handshake_num, bool set)
+{
+ unsigned long start = 0;
+ unsigned long reg_value;
+ unsigned long reg_mask;
+ unsigned long reg_set;
+ unsigned long mask;
+ unsigned long val;
+
+ if (!chip->apb_regs) {
+ dev_dbg(chip->dev, "apb_regs not initialized\n");
+ return;
+ }
+
+ /*
+* An unused DMA channel has a default value of 0x3F.
+* Lock the DMA channel by assign a handshake number to the channel.
+* Unlock the DMA channel by assign 0x3F to the channel.
+*/
+ if (set) {
+ reg_set = UNUSED_CHANNEL;
+ val = handshake_num;
+ } else {
+ reg_set = handshake_num;
+ val = UNUSED_CHANNEL;
+ }
+
+ reg_value = lo_hi_readq(chip->apb_regs + DMAC_APB_HW_HS_SEL_0);
+
+ for_each_set_clump8(start, reg_mask, _value, 64) {
+ if (reg_mask == reg_set) {
+ mask = GENMASK_ULL(start + 7, start);
+ reg_value &= ~mask;
+ reg_value |= rol64(val, start);
+ lo_hi_writeq(reg_value,
+chip->apb_regs + DMAC_APB_HW_HS_SEL_0);
+ break;
+ }
+ }
+}
+
/*
* If DW_axi_dmac sees CHx_CTL.ShadowReg_Or_LLI_Last bit of the fetched LLI
* as 1, it understands that the current block is the final block in the
@@ -626,6 +668,8 @@ dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan,
dma_addr_t dma_addr,
llp = hw_desc->llp;
} while (num_periods);
+ dw_axi_dma_set_hw_channel(chan->chip, chan->hw_handshake_num, true);
+
return vchan_tx_prep(>vc, >vd, flags);
err_desc_get:
@@ -684,6 +728,8 @@ dw_axi_dma_chan_prep_slave_sg(struct dma_chan *dchan,
struct scatterlist *sgl,
llp = hw_desc->llp;
} while (sg_len);
+ dw_axi_dma_set_hw_channel(chan->chip, chan->hw_handshake_num, true);
+
return vchan_tx_prep(>vc, >vd, flags);
err_desc_get:
@@ -959,6 +1005,10 @@ static int dma_chan_terminate_all(struct dma_chan *dchan)
dev_warn(dchan2dev(dchan),
"%s failed to stop\n", axi_chan_name(chan));
+ if (chan->direction != DMA_MEM_TO_MEM)
+ dw_axi_dma_set_hw_channel(chan->chip,
+ chan->hw_handshake_num, false);
+
spin_lock_irqsave(>vc.lock, flags);
vchan_get_all_descriptors(>vc, );
--
2.18.0
[PATCH v11 15/16] dmaengine: dw-axi-dmac: Set constraint to the Max segment size
Add support for DMA Scatter-Gather (SG) constraint so that DMA clients can
handle the AxiDMA limitation.
Without supporting DMA constraint the default Max segment size reported by
dmaengine is 64KB, which is not supported by Intel KeemBay AxiDMA.
Signed-off-by: Sia Jee Heng
Reviewed-by: Andy Shevchenko
Reviewed-by: Eugeniy Paltsev
Tested-by: Eugeniy Paltsev
---
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 8
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 1 +
2 files changed, 9 insertions(+)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index a1dddec95316..88d4923dee6c 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -1340,6 +1341,13 @@ static int dw_probe(struct platform_device *pdev)
dw->dma.device_prep_slave_sg = dw_axi_dma_chan_prep_slave_sg;
dw->dma.device_prep_dma_cyclic = dw_axi_dma_chan_prep_cyclic;
+ /*
+* Synopsis DesignWare AxiDMA datasheet mentioned Maximum
+* supported blocks is 1024. Device register width is 4 bytes.
+* Therefore, set constraint to 1024 * 4.
+*/
+ dw->dma.dev->dma_parms = >dma_parms;
+ dma_set_max_seg_size(>dev, MAX_BLOCK_SIZE);
platform_set_drvdata(pdev, chip);
pm_runtime_enable(chip->dev);
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
index 3a357f7fda02..1e937ea2a96d 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
@@ -54,6 +54,7 @@ struct axi_dma_chan {
struct dw_axi_dma {
struct dma_device dma;
struct dw_axi_dma_hcfg *hdata;
+ struct device_dma_parametersdma_parms;
/* channels */
struct axi_dma_chan *chan;
--
2.18.0
[PATCH v11 09/16] dmaengine: dw-axi-dmac: Support burst residue granularity
Add support for DMA_RESIDUE_GRANULARITY_BURST so that AxiDMA can report
DMA residue.
Existing AxiDMA driver only support data transfer between
memory to memory operation, therefore reporting DMA residue
to the DMA clients is not supported.
Reporting DMA residue to the DMA clients is important as DMA clients
shall invoke dmaengine_tx_status() to understand the number of bytes
been transferred so that the buffer pointer can be updated accordingly.
Signed-off-by: Sia Jee Heng
Reviewed-by: Andy Shevchenko
Reviewed-by: Eugeniy Paltsev
Tested-by: Eugeniy Paltsev
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c| 43 ---
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 2 +
2 files changed, 38 insertions(+), 7 deletions(-)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index a8b6c8c8ef58..830d3de76abd 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -265,14 +265,36 @@ dma_chan_tx_status(struct dma_chan *dchan, dma_cookie_t
cookie,
struct dma_tx_state *txstate)
{
struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
- enum dma_status ret;
+ struct virt_dma_desc *vdesc;
+ enum dma_status status;
+ u32 completed_length;
+ unsigned long flags;
+ u32 completed_blocks;
+ size_t bytes = 0;
+ u32 length;
+ u32 len;
- ret = dma_cookie_status(dchan, cookie, txstate);
+ status = dma_cookie_status(dchan, cookie, txstate);
+ if (status == DMA_COMPLETE || !txstate)
+ return status;
- if (chan->is_paused && ret == DMA_IN_PROGRESS)
- ret = DMA_PAUSED;
+ spin_lock_irqsave(>vc.lock, flags);
- return ret;
+ vdesc = vchan_find_desc(>vc, cookie);
+ if (vdesc) {
+ length = vd_to_axi_desc(vdesc)->length;
+ completed_blocks = vd_to_axi_desc(vdesc)->completed_blocks;
+ len = vd_to_axi_desc(vdesc)->hw_desc[0].len;
+ completed_length = completed_blocks * len;
+ bytes = length - completed_length;
+ } else {
+ bytes = vd_to_axi_desc(vdesc)->length;
+ }
+
+ spin_unlock_irqrestore(>vc.lock, flags);
+ dma_set_residue(txstate, bytes);
+
+ return status;
}
static void write_desc_llp(struct axi_dma_hw_desc *desc, dma_addr_t adr)
@@ -549,6 +571,7 @@ static int dw_axi_dma_set_hw_desc(struct axi_dma_chan *chan,
set_desc_src_master(hw_desc);
+ hw_desc->len = len;
return 0;
}
@@ -575,6 +598,7 @@ dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan,
dma_addr_t dma_addr,
chan->direction = direction;
desc->chan = chan;
chan->cyclic = true;
+ desc->length = 0;
for (i = 0; i < num_periods; i++) {
hw_desc = >hw_desc[i];
@@ -584,6 +608,7 @@ dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan,
dma_addr_t dma_addr,
if (status < 0)
goto err_desc_get;
+ desc->length += hw_desc->len;
/* Set end-of-link to the linked descriptor, so that cyclic
* callback function can be triggered during interrupt.
*/
@@ -636,6 +661,7 @@ dw_axi_dma_chan_prep_slave_sg(struct dma_chan *dchan,
struct scatterlist *sgl,
goto err_desc_get;
desc->chan = chan;
+ desc->length = 0;
for_each_sg(sgl, sg, sg_len, i) {
mem = sg_dma_address(sg);
@@ -645,6 +671,7 @@ dw_axi_dma_chan_prep_slave_sg(struct dma_chan *dchan,
struct scatterlist *sgl,
status = dw_axi_dma_set_hw_desc(chan, hw_desc, mem, len);
if (status < 0)
goto err_desc_get;
+ desc->length += hw_desc->len;
}
/* Set end-of-link to the last link descriptor of list */
@@ -690,6 +717,7 @@ dma_chan_prep_dma_memcpy(struct dma_chan *dchan, dma_addr_t
dst_adr,
desc->chan = chan;
num = 0;
+ desc->length = 0;
while (len) {
xfer_len = len;
@@ -742,7 +770,8 @@ dma_chan_prep_dma_memcpy(struct dma_chan *dchan, dma_addr_t
dst_adr,
set_desc_src_master(hw_desc);
set_desc_dest_master(hw_desc, desc);
-
+ hw_desc->len = xfer_len;
+ desc->length += hw_desc->len;
/* update the length and addresses for the next loop cycle */
len -= xfer_len;
dst_adr += xfer_len;
@@ -1210,7 +1239,7 @@ static int dw_probe(struct platform_device *pdev)
dw->dma.dst_addr_widths = AXI_DMA_BUSWIDTHS;
dw->dma.directions = BIT(DMA_MEM_TO_MEM);
dw->dma.directions |= BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM);
-
[PATCH v11 14/16] dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA BYTE and HALFWORD registers
Add support for Intel KeemBay AxiDMA BYTE and HALFWORD registers
programming.
Intel KeemBay AxiDMA supports data transfer between device to memory
and memory to device operations.
This code is needed by I2C, I3C, I2S, SPI and UART which uses FIFO
size of 8bits and 16bits to perform memory to device data transfer
operation. 0-padding functionality is provided to avoid
pre-processing of data on CPU.
Signed-off-by: Sia Jee Heng
Reviewed-by: Andy Shevchenko
Reviewed-by: Eugeniy Paltsev
Tested-by: Eugeniy Paltsev
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c| 26 +++
1 file changed, 26 insertions(+)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index e19369f9365a..a1dddec95316 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -307,6 +307,29 @@ static void write_chan_llp(struct axi_dma_chan *chan,
dma_addr_t adr)
axi_chan_iowrite64(chan, CH_LLP, adr);
}
+static void dw_axi_dma_set_byte_halfword(struct axi_dma_chan *chan, bool set)
+{
+ u32 offset = DMAC_APB_BYTE_WR_CH_EN;
+ u32 reg_width, val;
+
+ if (!chan->chip->apb_regs) {
+ dev_dbg(chan->chip->dev, "apb_regs not initialized\n");
+ return;
+ }
+
+ reg_width = __ffs(chan->config.dst_addr_width);
+ if (reg_width == DWAXIDMAC_TRANS_WIDTH_16)
+ offset = DMAC_APB_HALFWORD_WR_CH_EN;
+
+ val = ioread32(chan->chip->apb_regs + offset);
+
+ if (set)
+ val |= BIT(chan->id);
+ else
+ val &= ~BIT(chan->id);
+
+ iowrite32(val, chan->chip->apb_regs + offset);
+}
/* Called in chan locked context */
static void axi_chan_block_xfer_start(struct axi_dma_chan *chan,
struct axi_dma_desc *first)
@@ -334,6 +357,7 @@ static void axi_chan_block_xfer_start(struct axi_dma_chan
*chan,
DWAXIDMAC_HS_SEL_HW << CH_CFG_H_HS_SEL_SRC_POS);
switch (chan->direction) {
case DMA_MEM_TO_DEV:
+ dw_axi_dma_set_byte_halfword(chan, true);
reg |= (chan->config.device_fc ?
DWAXIDMAC_TT_FC_MEM_TO_PER_DST :
DWAXIDMAC_TT_FC_MEM_TO_PER_DMAC)
@@ -1008,6 +1032,8 @@ static int dma_chan_terminate_all(struct dma_chan *dchan)
if (chan->direction != DMA_MEM_TO_MEM)
dw_axi_dma_set_hw_channel(chan->chip,
chan->hw_handshake_num, false);
+ if (chan->direction == DMA_MEM_TO_DEV)
+ dw_axi_dma_set_byte_halfword(chan, false);
spin_lock_irqsave(>vc.lock, flags);
--
2.18.0
[PATCH v11 10/16] dt-binding: dma: dw-axi-dmac: Add support for Intel KeemBay AxiDMA
Add support for Intel KeemBay AxiDMA to the dw-axi-dmac Schemas DT binding. Signed-off-by: Sia Jee Heng Reviewed-by: Eugeniy Paltsev Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml | 5 + 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml index 3d2515463d56..79e241498e25 100644 --- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml +++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml @@ -8,6 +8,7 @@ title: Synopsys DesignWare AXI DMA Controller maintainers: - Eugeniy Paltsev + - Jee Heng Sia description: Synopsys DesignWare AXI DMA Controller DT Binding @@ -19,14 +20,18 @@ properties: compatible: enum: - snps,axi-dma-1.01a + - intel,kmb-axi-dma reg: +minItems: 1 items: - description: Address range of the DMAC registers + - description: Address range of the DMAC APB registers reg-names: items: - const: axidma_ctrl_regs + - const: axidma_apb_regs interrupts: maxItems: 1 -- 2.18.0
[PATCH v11 06/16] dmaengine: dw-axi-dmac: Support device_prep_slave_sg
Add device_prep_slave_sg() callback function so that DMA_MEM_TO_DEV
and DMA_DEV_TO_MEM operations in single mode can be supported.
Existing AxiDMA driver only support data transfer between
memory to memory. Data transfer between device to memory and
memory to device in single mode would failed if this interface
is not supported by the AxiDMA driver.
Signed-off-by: Sia Jee Heng
Reviewed-by: Andy Shevchenko
Reviewed-by: Eugeniy Paltsev
Tested-by: Eugeniy Paltsev
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c| 154 ++
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 1 +
2 files changed, 155 insertions(+)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index eaa7c4c404ca..7ff30b0f44ed 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -307,6 +307,22 @@ static void axi_chan_block_xfer_start(struct axi_dma_chan
*chan,
priority << CH_CFG_H_PRIORITY_POS |
DWAXIDMAC_HS_SEL_HW << CH_CFG_H_HS_SEL_DST_POS |
DWAXIDMAC_HS_SEL_HW << CH_CFG_H_HS_SEL_SRC_POS);
+ switch (chan->direction) {
+ case DMA_MEM_TO_DEV:
+ reg |= (chan->config.device_fc ?
+ DWAXIDMAC_TT_FC_MEM_TO_PER_DST :
+ DWAXIDMAC_TT_FC_MEM_TO_PER_DMAC)
+ << CH_CFG_H_TT_FC_POS;
+ break;
+ case DMA_DEV_TO_MEM:
+ reg |= (chan->config.device_fc ?
+ DWAXIDMAC_TT_FC_PER_TO_MEM_SRC :
+ DWAXIDMAC_TT_FC_PER_TO_MEM_DMAC)
+ << CH_CFG_H_TT_FC_POS;
+ break;
+ default:
+ break;
+ }
axi_chan_iowrite32(chan, CH_CFG_H, reg);
write_chan_llp(chan, first->hw_desc[0].llp | lms);
@@ -454,6 +470,141 @@ static void set_desc_dest_master(struct axi_dma_hw_desc
*hw_desc,
hw_desc->lli->ctl_lo = cpu_to_le32(val);
}
+static int dw_axi_dma_set_hw_desc(struct axi_dma_chan *chan,
+ struct axi_dma_hw_desc *hw_desc,
+ dma_addr_t mem_addr, size_t len)
+{
+ unsigned int data_width = BIT(chan->chip->dw->hdata->m_data_width);
+ unsigned int reg_width;
+ unsigned int mem_width;
+ dma_addr_t device_addr;
+ size_t axi_block_ts;
+ size_t block_ts;
+ u32 ctllo, ctlhi;
+ u32 burst_len;
+
+ axi_block_ts = chan->chip->dw->hdata->block_size[chan->id];
+
+ mem_width = __ffs(data_width | mem_addr | len);
+ if (mem_width > DWAXIDMAC_TRANS_WIDTH_32)
+ mem_width = DWAXIDMAC_TRANS_WIDTH_32;
+
+ switch (chan->direction) {
+ case DMA_MEM_TO_DEV:
+ reg_width = __ffs(chan->config.dst_addr_width);
+ device_addr = chan->config.dst_addr;
+ ctllo = reg_width << CH_CTL_L_DST_WIDTH_POS |
+ mem_width << CH_CTL_L_SRC_WIDTH_POS |
+ DWAXIDMAC_CH_CTL_L_NOINC << CH_CTL_L_DST_INC_POS |
+ DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_SRC_INC_POS;
+ block_ts = len >> mem_width;
+ break;
+ case DMA_DEV_TO_MEM:
+ reg_width = __ffs(chan->config.src_addr_width);
+ device_addr = chan->config.src_addr;
+ ctllo = reg_width << CH_CTL_L_SRC_WIDTH_POS |
+ mem_width << CH_CTL_L_DST_WIDTH_POS |
+ DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_DST_INC_POS |
+ DWAXIDMAC_CH_CTL_L_NOINC << CH_CTL_L_SRC_INC_POS;
+ block_ts = len >> reg_width;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (block_ts > axi_block_ts)
+ return -EINVAL;
+
+ hw_desc->lli = axi_desc_get(chan, _desc->llp);
+ if (unlikely(!hw_desc->lli))
+ return -ENOMEM;
+
+ ctlhi = CH_CTL_H_LLI_VALID;
+
+ if (chan->chip->dw->hdata->restrict_axi_burst_len) {
+ burst_len = chan->chip->dw->hdata->axi_rw_burst_len;
+ ctlhi |= CH_CTL_H_ARLEN_EN | CH_CTL_H_AWLEN_EN |
+burst_len << CH_CTL_H_ARLEN_POS |
+burst_len << CH_CTL_H_AWLEN_POS;
+ }
+
+ hw_desc->lli->ctl_hi = cpu_to_le32(ctlhi);
+
+ if (chan->direction == DMA_MEM_TO_DEV) {
+ write_desc_sar(hw_desc, mem_addr);
+ write_desc_dar(hw_desc, device_addr);
+ } else {
+ write_desc_sar(hw_desc, device_addr);
+ write_desc_dar(hw_desc, mem_addr);
+ }
+
+ hw_desc->lli->block_ts_lo = cpu_to_le32(block_ts - 1);
+
+ ctllo |=
[PATCH v11 04/16] dmaengine: dw-axi-dmac: Add device_synchronize() callback
Add support for device_synchronize() callback function to sync with
dmaengine_terminate_sync().
Signed-off-by: Sia Jee Heng
Reviewed-by: Andy Shevchenko
Reviewed-by: Eugeniy Paltsev
Tested-by: Eugeniy Paltsev
---
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 3737e1c3c793..241ab7a24e2a 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -347,6 +347,13 @@ static void dma_chan_issue_pending(struct dma_chan *dchan)
spin_unlock_irqrestore(>vc.lock, flags);
}
+static void dw_axi_dma_synchronize(struct dma_chan *dchan)
+{
+ struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
+
+ vchan_synchronize(>vc);
+}
+
static int dma_chan_alloc_chan_resources(struct dma_chan *dchan)
{
struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
@@ -940,6 +947,7 @@ static int dw_probe(struct platform_device *pdev)
dw->dma.device_free_chan_resources = dma_chan_free_chan_resources;
dw->dma.device_prep_dma_memcpy = dma_chan_prep_dma_memcpy;
+ dw->dma.device_synchronize = dw_axi_dma_synchronize;
platform_set_drvdata(pdev, chip);
--
2.18.0
[PATCH v10 02/16] dmaengine: dw-axi-dmac: simplify descriptor management
Simplify and refactor the descriptor management by removing the redundant
Linked List Item (LLI) queue control logic from the AxiDMA driver.
The descriptor is split into virtual descriptor and hardware LLI so that
only hardware LLI memories are allocated from the DMA memory pool.
Up to 64 descriptors can be allocated within a PAGE_SIZE compare to 16
descriptors in previous version. This solves the problem where an
ALSA driver expects more than 16 DMA descriptors to run.
Signed-off-by: Sia Jee Heng
Reviewed-by: Andy Shevchenko
Reviewed-by: Eugeniy Paltsev
Tested-by: Eugeniy Paltsev
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c| 164 ++
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 9 +-
2 files changed, 102 insertions(+), 71 deletions(-)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index e164f3295f5d..350968baaf88 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -21,6 +21,7 @@
#include
#include
#include
+#include
#include
#include "dw-axi-dmac.h"
@@ -195,43 +196,58 @@ static inline const char *axi_chan_name(struct
axi_dma_chan *chan)
return dma_chan_name(>vc.chan);
}
-static struct axi_dma_desc *axi_desc_get(struct axi_dma_chan *chan)
+static struct axi_dma_desc *axi_desc_alloc(u32 num)
{
- struct dw_axi_dma *dw = chan->chip->dw;
struct axi_dma_desc *desc;
+
+ desc = kzalloc(sizeof(*desc), GFP_NOWAIT);
+ if (!desc)
+ return NULL;
+
+ desc->hw_desc = kcalloc(num, sizeof(*desc->hw_desc), GFP_NOWAIT);
+ if (!desc->hw_desc) {
+ kfree(desc);
+ return NULL;
+ }
+
+ return desc;
+}
+
+static struct axi_dma_lli *axi_desc_get(struct axi_dma_chan *chan,
+ dma_addr_t *addr)
+{
+ struct dw_axi_dma *dw = chan->chip->dw;
+ struct axi_dma_lli *lli;
dma_addr_t phys;
- desc = dma_pool_zalloc(dw->desc_pool, GFP_NOWAIT, );
- if (unlikely(!desc)) {
+ lli = dma_pool_zalloc(dw->desc_pool, GFP_NOWAIT, );
+ if (unlikely(!lli)) {
dev_err(chan2dev(chan), "%s: not enough descriptors
available\n",
axi_chan_name(chan));
return NULL;
}
atomic_inc(>descs_allocated);
- INIT_LIST_HEAD(>xfer_list);
- desc->vd.tx.phys = phys;
- desc->chan = chan;
+ *addr = phys;
- return desc;
+ return lli;
}
static void axi_desc_put(struct axi_dma_desc *desc)
{
struct axi_dma_chan *chan = desc->chan;
struct dw_axi_dma *dw = chan->chip->dw;
- struct axi_dma_desc *child, *_next;
- unsigned int descs_put = 0;
+ int count = atomic_read(>descs_allocated);
+ struct axi_dma_hw_desc *hw_desc;
+ int descs_put;
- list_for_each_entry_safe(child, _next, >xfer_list, xfer_list) {
- list_del(>xfer_list);
- dma_pool_free(dw->desc_pool, child, child->vd.tx.phys);
- descs_put++;
+ for (descs_put = 0; descs_put < count; descs_put++) {
+ hw_desc = >hw_desc[descs_put];
+ dma_pool_free(dw->desc_pool, hw_desc->lli, hw_desc->llp);
}
- dma_pool_free(dw->desc_pool, desc, desc->vd.tx.phys);
- descs_put++;
-
+ kfree(desc->hw_desc);
+ kfree(desc);
atomic_sub(descs_put, >descs_allocated);
dev_vdbg(chan2dev(chan), "%s: %d descs put, %d still allocated\n",
axi_chan_name(chan), descs_put,
@@ -258,9 +274,9 @@ dma_chan_tx_status(struct dma_chan *dchan, dma_cookie_t
cookie,
return ret;
}
-static void write_desc_llp(struct axi_dma_desc *desc, dma_addr_t adr)
+static void write_desc_llp(struct axi_dma_hw_desc *desc, dma_addr_t adr)
{
- desc->lli.llp = cpu_to_le64(adr);
+ desc->lli->llp = cpu_to_le64(adr);
}
static void write_chan_llp(struct axi_dma_chan *chan, dma_addr_t adr)
@@ -295,7 +311,7 @@ static void axi_chan_block_xfer_start(struct axi_dma_chan
*chan,
DWAXIDMAC_HS_SEL_HW << CH_CFG_H_HS_SEL_SRC_POS);
axi_chan_iowrite32(chan, CH_CFG_H, reg);
- write_chan_llp(chan, first->vd.tx.phys | lms);
+ write_chan_llp(chan, first->hw_desc[0].llp | lms);
irq_mask = DWAXIDMAC_IRQ_DMA_TRF | DWAXIDMAC_IRQ_ALL_ERR;
axi_chan_irq_sig_set(chan, irq_mask);
@@ -378,67 +394,78 @@ static void dma_chan_free_chan_resources(struct dma_chan
*dchan)
* transfer and completes the DMA transfer operation at the end of current
* block transfer.
*/
-static void set_desc_last(struct axi_dma_desc *desc)
+static void set_desc_last(struct axi_dma_hw_desc *desc)
{
u32 val;
- val = le32_to_cpu(desc->lli.ctl_
[PATCH v10 04/16] dmaengine: dw-axi-dmac: Add device_synchronize() callback
Add support for device_synchronize() callback function to sync with
dmaengine_terminate_sync().
Signed-off-by: Sia Jee Heng
Reviewed-by: Andy Shevchenko
Reviewed-by: Eugeniy Paltsev
Tested-by: Eugeniy Paltsev
---
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 3737e1c3c793..241ab7a24e2a 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -347,6 +347,13 @@ static void dma_chan_issue_pending(struct dma_chan *dchan)
spin_unlock_irqrestore(>vc.lock, flags);
}
+static void dw_axi_dma_synchronize(struct dma_chan *dchan)
+{
+ struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
+
+ vchan_synchronize(>vc);
+}
+
static int dma_chan_alloc_chan_resources(struct dma_chan *dchan)
{
struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
@@ -940,6 +947,7 @@ static int dw_probe(struct platform_device *pdev)
dw->dma.device_free_chan_resources = dma_chan_free_chan_resources;
dw->dma.device_prep_dma_memcpy = dma_chan_prep_dma_memcpy;
+ dw->dma.device_synchronize = dw_axi_dma_synchronize;
platform_set_drvdata(pdev, chip);
--
2.18.0
[PATCH v10 05/16] dmaengine: dw-axi-dmac: Add device_config operation
Add device_config() callback function so that the device address
can be passed to the dma driver.
DMA clients use this interface to pass in the device address to the
AxiDMA. Without this interface, data transfer between device to memory
and memory to device would failed.
Signed-off-by: Sia Jee Heng
Reviewed-by: Andy Shevchenko
Reviewed-by: Eugeniy Paltsev
Tested-by: Eugeniy Paltsev
---
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 11 +++
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 1 +
2 files changed, 12 insertions(+)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 241ab7a24e2a..eaa7c4c404ca 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -559,6 +559,16 @@ dma_chan_prep_dma_memcpy(struct dma_chan *dchan,
dma_addr_t dst_adr,
return NULL;
}
+static int dw_axi_dma_chan_slave_config(struct dma_chan *dchan,
+ struct dma_slave_config *config)
+{
+ struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
+
+ memcpy(>config, config, sizeof(*config));
+
+ return 0;
+}
+
static void axi_chan_dump_lli(struct axi_dma_chan *chan,
struct axi_dma_hw_desc *desc)
{
@@ -948,6 +958,7 @@ static int dw_probe(struct platform_device *pdev)
dw->dma.device_prep_dma_memcpy = dma_chan_prep_dma_memcpy;
dw->dma.device_synchronize = dw_axi_dma_synchronize;
+ dw->dma.device_config = dw_axi_dma_chan_slave_config;
platform_set_drvdata(pdev, chip);
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
index f886b2bb75de..a75b921d6b1a 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
@@ -43,6 +43,7 @@ struct axi_dma_chan {
struct virt_dma_chanvc;
struct axi_dma_desc *desc;
+ struct dma_slave_config config;
/* these other elements are all protected by vc.lock */
boolis_paused;
};
--
2.18.0
[PATCH v10 06/16] dmaengine: dw-axi-dmac: Support device_prep_slave_sg
Add device_prep_slave_sg() callback function so that DMA_MEM_TO_DEV
and DMA_DEV_TO_MEM operations in single mode can be supported.
Existing AxiDMA driver only support data transfer between
memory to memory. Data transfer between device to memory and
memory to device in single mode would failed if this interface
is not supported by the AxiDMA driver.
Signed-off-by: Sia Jee Heng
Reviewed-by: Andy Shevchenko
Reviewed-by: Eugeniy Paltsev
Tested-by: Eugeniy Paltsev
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c| 154 ++
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 1 +
2 files changed, 155 insertions(+)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index eaa7c4c404ca..7ff30b0f44ed 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -307,6 +307,22 @@ static void axi_chan_block_xfer_start(struct axi_dma_chan
*chan,
priority << CH_CFG_H_PRIORITY_POS |
DWAXIDMAC_HS_SEL_HW << CH_CFG_H_HS_SEL_DST_POS |
DWAXIDMAC_HS_SEL_HW << CH_CFG_H_HS_SEL_SRC_POS);
+ switch (chan->direction) {
+ case DMA_MEM_TO_DEV:
+ reg |= (chan->config.device_fc ?
+ DWAXIDMAC_TT_FC_MEM_TO_PER_DST :
+ DWAXIDMAC_TT_FC_MEM_TO_PER_DMAC)
+ << CH_CFG_H_TT_FC_POS;
+ break;
+ case DMA_DEV_TO_MEM:
+ reg |= (chan->config.device_fc ?
+ DWAXIDMAC_TT_FC_PER_TO_MEM_SRC :
+ DWAXIDMAC_TT_FC_PER_TO_MEM_DMAC)
+ << CH_CFG_H_TT_FC_POS;
+ break;
+ default:
+ break;
+ }
axi_chan_iowrite32(chan, CH_CFG_H, reg);
write_chan_llp(chan, first->hw_desc[0].llp | lms);
@@ -454,6 +470,141 @@ static void set_desc_dest_master(struct axi_dma_hw_desc
*hw_desc,
hw_desc->lli->ctl_lo = cpu_to_le32(val);
}
+static int dw_axi_dma_set_hw_desc(struct axi_dma_chan *chan,
+ struct axi_dma_hw_desc *hw_desc,
+ dma_addr_t mem_addr, size_t len)
+{
+ unsigned int data_width = BIT(chan->chip->dw->hdata->m_data_width);
+ unsigned int reg_width;
+ unsigned int mem_width;
+ dma_addr_t device_addr;
+ size_t axi_block_ts;
+ size_t block_ts;
+ u32 ctllo, ctlhi;
+ u32 burst_len;
+
+ axi_block_ts = chan->chip->dw->hdata->block_size[chan->id];
+
+ mem_width = __ffs(data_width | mem_addr | len);
+ if (mem_width > DWAXIDMAC_TRANS_WIDTH_32)
+ mem_width = DWAXIDMAC_TRANS_WIDTH_32;
+
+ switch (chan->direction) {
+ case DMA_MEM_TO_DEV:
+ reg_width = __ffs(chan->config.dst_addr_width);
+ device_addr = chan->config.dst_addr;
+ ctllo = reg_width << CH_CTL_L_DST_WIDTH_POS |
+ mem_width << CH_CTL_L_SRC_WIDTH_POS |
+ DWAXIDMAC_CH_CTL_L_NOINC << CH_CTL_L_DST_INC_POS |
+ DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_SRC_INC_POS;
+ block_ts = len >> mem_width;
+ break;
+ case DMA_DEV_TO_MEM:
+ reg_width = __ffs(chan->config.src_addr_width);
+ device_addr = chan->config.src_addr;
+ ctllo = reg_width << CH_CTL_L_SRC_WIDTH_POS |
+ mem_width << CH_CTL_L_DST_WIDTH_POS |
+ DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_DST_INC_POS |
+ DWAXIDMAC_CH_CTL_L_NOINC << CH_CTL_L_SRC_INC_POS;
+ block_ts = len >> reg_width;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (block_ts > axi_block_ts)
+ return -EINVAL;
+
+ hw_desc->lli = axi_desc_get(chan, _desc->llp);
+ if (unlikely(!hw_desc->lli))
+ return -ENOMEM;
+
+ ctlhi = CH_CTL_H_LLI_VALID;
+
+ if (chan->chip->dw->hdata->restrict_axi_burst_len) {
+ burst_len = chan->chip->dw->hdata->axi_rw_burst_len;
+ ctlhi |= CH_CTL_H_ARLEN_EN | CH_CTL_H_AWLEN_EN |
+burst_len << CH_CTL_H_ARLEN_POS |
+burst_len << CH_CTL_H_AWLEN_POS;
+ }
+
+ hw_desc->lli->ctl_hi = cpu_to_le32(ctlhi);
+
+ if (chan->direction == DMA_MEM_TO_DEV) {
+ write_desc_sar(hw_desc, mem_addr);
+ write_desc_dar(hw_desc, device_addr);
+ } else {
+ write_desc_sar(hw_desc, device_addr);
+ write_desc_dar(hw_desc, mem_addr);
+ }
+
+ hw_desc->lli->block_ts_lo = cpu_to_le32(block_ts - 1);
+
+ ctllo |=
[PATCH v10 15/16] dmaengine: dw-axi-dmac: Set constraint to the Max segment size
Add support for DMA Scatter-Gather (SG) constraint so that DMA clients can
handle the AxiDMA limitation.
Without supporting DMA constraint the default Max segment size reported by
dmaengine is 64KB, which is not supported by Intel KeemBay AxiDMA.
Signed-off-by: Sia Jee Heng
Reviewed-by: Andy Shevchenko
Reviewed-by: Eugeniy Paltsev
Tested-by: Eugeniy Paltsev
---
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 8
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 1 +
2 files changed, 9 insertions(+)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index ea527b92e0fc..1f9522caf876 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -1341,6 +1342,13 @@ static int dw_probe(struct platform_device *pdev)
dw->dma.device_prep_slave_sg = dw_axi_dma_chan_prep_slave_sg;
dw->dma.device_prep_dma_cyclic = dw_axi_dma_chan_prep_cyclic;
+ /*
+* Synopsis DesignWare AxiDMA datasheet mentioned Maximum
+* supported blocks is 1024. Device register width is 4 bytes.
+* Therefore, set constraint to 1024 * 4.
+*/
+ dw->dma.dev->dma_parms = >dma_parms;
+ dma_set_max_seg_size(>dev, MAX_BLOCK_SIZE);
platform_set_drvdata(pdev, chip);
pm_runtime_enable(chip->dev);
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
index 3a357f7fda02..1e937ea2a96d 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
@@ -54,6 +54,7 @@ struct axi_dma_chan {
struct dw_axi_dma {
struct dma_device dma;
struct dw_axi_dma_hcfg *hdata;
+ struct device_dma_parametersdma_parms;
/* channels */
struct axi_dma_chan *chan;
--
2.18.0
[PATCH v10 12/16] dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA support
Add support for Intel KeemBay AxiDMA to the .compatible field.
The AxiDMA Apb region will be accessible if the compatible string
matches the "intel,kmb-axi-dma".
Signed-off-by: Sia Jee Heng
Reviewed-by: Andy Shevchenko
Reviewed-by: Eugeniy Paltsev
Tested-by: Eugeniy Paltsev
---
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 830d3de76abd..062d27c61983 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -1160,6 +1160,7 @@ static int parse_device_properties(struct axi_dma_chip
*chip)
static int dw_probe(struct platform_device *pdev)
{
+ struct device_node *node = pdev->dev.of_node;
struct axi_dma_chip *chip;
struct resource *mem;
struct dw_axi_dma *dw;
@@ -1192,6 +1193,12 @@ static int dw_probe(struct platform_device *pdev)
if (IS_ERR(chip->regs))
return PTR_ERR(chip->regs);
+ if (of_device_is_compatible(node, "intel,kmb-axi-dma")) {
+ chip->apb_regs = devm_platform_ioremap_resource(pdev, 1);
+ if (IS_ERR(chip->apb_regs))
+ return PTR_ERR(chip->apb_regs);
+ }
+
chip->core_clk = devm_clk_get(chip->dev, "core-clk");
if (IS_ERR(chip->core_clk))
return PTR_ERR(chip->core_clk);
@@ -1336,6 +1343,7 @@ static const struct dev_pm_ops dw_axi_dma_pm_ops = {
static const struct of_device_id dw_dma_of_id_table[] = {
{ .compatible = "snps,axi-dma-1.01a" },
+ { .compatible = "intel,kmb-axi-dma" },
{}
};
MODULE_DEVICE_TABLE(of, dw_dma_of_id_table);
--
2.18.0
[PATCH v10 11/16] dmaengine: dw-axi-dmac: Add Intel KeemBay DMA register fields
Add support for Intel KeemBay DMA registers. These registers are required
to run data transfer between device to memory and memory to device on Intel
KeemBay SoC.
Signed-off-by: Sia Jee Heng
Reviewed-by: Andy Shevchenko
Reviewed-by: Eugeniy Paltsev
Tested-by: Eugeniy Paltsev
---
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
index 46baf93de617..3a357f7fda02 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
@@ -63,6 +63,7 @@ struct axi_dma_chip {
struct device *dev;
int irq;
void __iomem*regs;
+ void __iomem*apb_regs;
struct clk *core_clk;
struct clk *cfgr_clk;
struct dw_axi_dma *dw;
@@ -169,6 +170,19 @@ static inline struct axi_dma_chan
*dchan_to_axi_dma_chan(struct dma_chan *dchan)
#define CH_INTSIGNAL_ENA 0x090 /* R/W Chan Interrupt Signal Enable */
#define CH_INTCLEAR0x098 /* W Chan Interrupt Clear */
+/* These Apb registers are used by Intel KeemBay SoC */
+#define DMAC_APB_CFG 0x000 /* DMAC Apb Configuration Register */
+#define DMAC_APB_STAT 0x004 /* DMAC Apb Status Register */
+#define DMAC_APB_DEBUG_STAT_0 0x008 /* DMAC Apb Debug Status Register 0 */
+#define DMAC_APB_DEBUG_STAT_1 0x00C /* DMAC Apb Debug Status Register 1 */
+#define DMAC_APB_HW_HS_SEL_0 0x010 /* DMAC Apb HW HS register 0 */
+#define DMAC_APB_HW_HS_SEL_1 0x014 /* DMAC Apb HW HS register 1 */
+#define DMAC_APB_LPI 0x018 /* DMAC Apb Low Power Interface Reg */
+#define DMAC_APB_BYTE_WR_CH_EN 0x01C /* DMAC Apb Byte Write Enable */
+#define DMAC_APB_HALFWORD_WR_CH_EN 0x020 /* DMAC Halfword write enables */
+
+#define UNUSED_CHANNEL 0x3F /* Set unused DMA channel to 0x3F */
+#define MAX_BLOCK_SIZE 0x1000 /* 1024 blocks * 4 bytes data width */
/* DMAC_CFG */
#define DMAC_EN_POS0
--
2.18.0
[PATCH v10 16/16] dmaengine: dw-axi-dmac: Virtually split the linked-list
AxiDMA driver exposed the dma_set_max_seg_size() to the DMAENGINE.
It shall helps the DMA clients to create size-optimized linked-list
for the controller.
However, there are certain situations where DMA client might not be
abled to benefit from the dma_get_max_seg_size() if the segment size
can't meet the nature of the DMA client's operation.
In the case of ALSA operation, ALSA application and driver expecting
to run in a period of larger than 10ms regardless of the bit depth.
With this large period, there is a strong request to split the linked-list
in the AxiDMA driver.
Signed-off-by: Sia Jee Heng
Reviewed-by: Eugeniy Paltsev
Tested-by: Eugeniy Paltsev
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c| 111 ++
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 1 +
2 files changed, 92 insertions(+), 20 deletions(-)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 1f9522caf876..dd1af6056d94 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -582,6 +582,11 @@ static int dw_axi_dma_set_hw_desc(struct axi_dma_chan
*chan,
if (mem_width > DWAXIDMAC_TRANS_WIDTH_32)
mem_width = DWAXIDMAC_TRANS_WIDTH_32;
+ if (!IS_ALIGNED(mem_addr, 4)) {
+ dev_err(chan->chip->dev, "invalid buffer alignment\n");
+ return -EINVAL;
+ }
+
switch (chan->direction) {
case DMA_MEM_TO_DEV:
reg_width = __ffs(chan->config.dst_addr_width);
@@ -643,6 +648,35 @@ static int dw_axi_dma_set_hw_desc(struct axi_dma_chan
*chan,
return 0;
}
+static size_t calculate_block_len(struct axi_dma_chan *chan,
+ dma_addr_t dma_addr, size_t buf_len,
+ enum dma_transfer_direction direction)
+{
+ u32 data_width, reg_width, mem_width;
+ size_t axi_block_ts, block_len;
+
+ axi_block_ts = chan->chip->dw->hdata->block_size[chan->id];
+
+ switch (direction) {
+ case DMA_MEM_TO_DEV:
+ data_width = BIT(chan->chip->dw->hdata->m_data_width);
+ mem_width = __ffs(data_width | dma_addr | buf_len);
+ if (mem_width > DWAXIDMAC_TRANS_WIDTH_32)
+ mem_width = DWAXIDMAC_TRANS_WIDTH_32;
+
+ block_len = axi_block_ts << mem_width;
+ break;
+ case DMA_DEV_TO_MEM:
+ reg_width = __ffs(chan->config.src_addr_width);
+ block_len = axi_block_ts << reg_width;
+ break;
+ default:
+ block_len = 0;
+ }
+
+ return block_len;
+}
+
static struct dma_async_tx_descriptor *
dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan, dma_addr_t dma_addr,
size_t buf_len, size_t period_len,
@@ -653,13 +687,27 @@ dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan,
dma_addr_t dma_addr,
struct axi_dma_hw_desc *hw_desc = NULL;
struct axi_dma_desc *desc = NULL;
dma_addr_t src_addr = dma_addr;
- u32 num_periods = buf_len / period_len;
+ u32 num_periods, num_segments;
+ size_t axi_block_len;
+ u32 total_segments;
+ u32 segment_len;
unsigned int i;
int status;
u64 llp = 0;
u8 lms = 0; /* Select AXI0 master for LLI fetching */
- desc = axi_desc_alloc(num_periods);
+ num_periods = buf_len / period_len;
+
+ axi_block_len = calculate_block_len(chan, dma_addr, buf_len, direction);
+ if (axi_block_len == 0)
+ return NULL;
+
+ num_segments = DIV_ROUND_UP(period_len, axi_block_len);
+ segment_len = DIV_ROUND_UP(period_len, num_segments);
+
+ total_segments = num_periods * num_segments;
+
+ desc = axi_desc_alloc(total_segments);
if (unlikely(!desc))
goto err_desc_get;
@@ -667,12 +715,13 @@ dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan,
dma_addr_t dma_addr,
desc->chan = chan;
chan->cyclic = true;
desc->length = 0;
+ desc->period_len = period_len;
- for (i = 0; i < num_periods; i++) {
+ for (i = 0; i < total_segments; i++) {
hw_desc = >hw_desc[i];
status = dw_axi_dma_set_hw_desc(chan, hw_desc, src_addr,
- period_len);
+ segment_len);
if (status < 0)
goto err_desc_get;
@@ -682,17 +731,17 @@ dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan,
dma_addr_t dma_addr,
*/
set_desc_last(hw_desc);
- src_addr += period_len;
+ src_addr += segment_len;
}
llp = desc->hw_desc[0].llp;
/* Managed transfer list */
[PATCH v10 14/16] dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA BYTE and HALFWORD registers
Add support for Intel KeemBay AxiDMA BYTE and HALFWORD registers
programming.
Intel KeemBay AxiDMA supports data transfer between device to memory
and memory to device operations.
This code is needed by I2C, I3C, I2S, SPI and UART which uses FIFO
size of 8bits and 16bits to perform memory to device data transfer
operation. 0-padding functionality is provided to avoid
pre-processing of data on CPU.
Signed-off-by: Sia Jee Heng
Reviewed-by: Andy Shevchenko
Reviewed-by: Eugeniy Paltsev
Tested-by: Eugeniy Paltsev
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c| 27 +++
1 file changed, 27 insertions(+)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index e19369f9365a..ea527b92e0fc 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -307,6 +307,30 @@ static void write_chan_llp(struct axi_dma_chan *chan,
dma_addr_t adr)
axi_chan_iowrite64(chan, CH_LLP, adr);
}
+static void dw_axi_dma_set_byte_halfword(struct axi_dma_chan *chan, bool set)
+{
+ u32 reg_width, offset, val;
+
+ if (!chan->chip->apb_regs) {
+ dev_dbg(chan->chip->dev, "apb_regs not initialized\n");
+ return;
+ }
+
+ reg_width = __ffs(chan->config.dst_addr_width);
+ if (reg_width == DWAXIDMAC_TRANS_WIDTH_8)
+ offset = DMAC_APB_BYTE_WR_CH_EN;
+ else if (reg_width == DWAXIDMAC_TRANS_WIDTH_16)
+ offset = DMAC_APB_HALFWORD_WR_CH_EN;
+
+ val = ioread32(chan->chip->apb_regs + offset);
+
+ if (set)
+ val |= BIT(chan->id);
+ else
+ val &= ~BIT(chan->id);
+
+ iowrite32(val, chan->chip->apb_regs + offset);
+}
/* Called in chan locked context */
static void axi_chan_block_xfer_start(struct axi_dma_chan *chan,
struct axi_dma_desc *first)
@@ -334,6 +358,7 @@ static void axi_chan_block_xfer_start(struct axi_dma_chan
*chan,
DWAXIDMAC_HS_SEL_HW << CH_CFG_H_HS_SEL_SRC_POS);
switch (chan->direction) {
case DMA_MEM_TO_DEV:
+ dw_axi_dma_set_byte_halfword(chan, true);
reg |= (chan->config.device_fc ?
DWAXIDMAC_TT_FC_MEM_TO_PER_DST :
DWAXIDMAC_TT_FC_MEM_TO_PER_DMAC)
@@ -1008,6 +1033,8 @@ static int dma_chan_terminate_all(struct dma_chan *dchan)
if (chan->direction != DMA_MEM_TO_MEM)
dw_axi_dma_set_hw_channel(chan->chip,
chan->hw_handshake_num, false);
+ if (chan->direction == DMA_MEM_TO_DEV)
+ dw_axi_dma_set_byte_halfword(chan, false);
spin_lock_irqsave(>vc.lock, flags);
--
2.18.0
[PATCH v10 13/16] dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA handshake
Add support for Intel KeemBay AxiDMA device handshake programming.
Device handshake number passed in to the AxiDMA shall be written to
the Intel KeemBay AxiDMA hardware handshake registers before DMA
operations are started.
Signed-off-by: Sia Jee Heng
Reviewed-by: Andy Shevchenko
Reviewed-by: Eugeniy Paltsev
Tested-by: Eugeniy Paltsev
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c| 50 +++
1 file changed, 50 insertions(+)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 062d27c61983..e19369f9365a 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -445,6 +445,48 @@ static void dma_chan_free_chan_resources(struct dma_chan
*dchan)
pm_runtime_put(chan->chip->dev);
}
+static void dw_axi_dma_set_hw_channel(struct axi_dma_chip *chip,
+ u32 handshake_num, bool set)
+{
+ unsigned long start = 0;
+ unsigned long reg_value;
+ unsigned long reg_mask;
+ unsigned long reg_set;
+ unsigned long mask;
+ unsigned long val;
+
+ if (!chip->apb_regs) {
+ dev_dbg(chip->dev, "apb_regs not initialized\n");
+ return;
+ }
+
+ /*
+* An unused DMA channel has a default value of 0x3F.
+* Lock the DMA channel by assign a handshake number to the channel.
+* Unlock the DMA channel by assign 0x3F to the channel.
+*/
+ if (set) {
+ reg_set = UNUSED_CHANNEL;
+ val = handshake_num;
+ } else {
+ reg_set = handshake_num;
+ val = UNUSED_CHANNEL;
+ }
+
+ reg_value = lo_hi_readq(chip->apb_regs + DMAC_APB_HW_HS_SEL_0);
+
+ for_each_set_clump8(start, reg_mask, _value, 64) {
+ if (reg_mask == reg_set) {
+ mask = GENMASK_ULL(start + 7, start);
+ reg_value &= ~mask;
+ reg_value |= rol64(val, start);
+ lo_hi_writeq(reg_value,
+chip->apb_regs + DMAC_APB_HW_HS_SEL_0);
+ break;
+ }
+ }
+}
+
/*
* If DW_axi_dmac sees CHx_CTL.ShadowReg_Or_LLI_Last bit of the fetched LLI
* as 1, it understands that the current block is the final block in the
@@ -626,6 +668,8 @@ dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan,
dma_addr_t dma_addr,
llp = hw_desc->llp;
} while (num_periods);
+ dw_axi_dma_set_hw_channel(chan->chip, chan->hw_handshake_num, true);
+
return vchan_tx_prep(>vc, >vd, flags);
err_desc_get:
@@ -684,6 +728,8 @@ dw_axi_dma_chan_prep_slave_sg(struct dma_chan *dchan,
struct scatterlist *sgl,
llp = hw_desc->llp;
} while (sg_len);
+ dw_axi_dma_set_hw_channel(chan->chip, chan->hw_handshake_num, true);
+
return vchan_tx_prep(>vc, >vd, flags);
err_desc_get:
@@ -959,6 +1005,10 @@ static int dma_chan_terminate_all(struct dma_chan *dchan)
dev_warn(dchan2dev(dchan),
"%s failed to stop\n", axi_chan_name(chan));
+ if (chan->direction != DMA_MEM_TO_MEM)
+ dw_axi_dma_set_hw_channel(chan->chip,
+ chan->hw_handshake_num, false);
+
spin_lock_irqsave(>vc.lock, flags);
vchan_get_all_descriptors(>vc, );
--
2.18.0
[PATCH v10 08/16] dmaengine: dw-axi-dmac: Support of_dma_controller_register()
Add support for of_dma_controller_register() so that DMA clients
can pass in device handshake number to the AxiDMA driver.
DMA clients shall code the device handshake number in the Device tree.
When DMA activities are needed, DMA clients shall invoke OF helper
function to pass in the device handshake number to the AxiDMA.
Without register to the of_dma_controller_register(), data transfer
between memory to device and device to memory operations would failed.
Signed-off-by: Sia Jee Heng
Reviewed-by: Andy Shevchenko
Reviewed-by: Eugeniy Paltsev
Tested-by: Eugeniy Paltsev
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c| 26 +++
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 1 +
2 files changed, 27 insertions(+)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index a76299360f69..a8b6c8c8ef58 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -20,6 +20,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -1044,6 +1045,22 @@ static int __maybe_unused axi_dma_runtime_resume(struct
device *dev)
return axi_dma_resume(chip);
}
+static struct dma_chan *dw_axi_dma_of_xlate(struct of_phandle_args *dma_spec,
+ struct of_dma *ofdma)
+{
+ struct dw_axi_dma *dw = ofdma->of_dma_data;
+ struct axi_dma_chan *chan;
+ struct dma_chan *dchan;
+
+ dchan = dma_get_any_slave_channel(>dma);
+ if (!dchan)
+ return NULL;
+
+ chan = dchan_to_axi_dma_chan(dchan);
+ chan->hw_handshake_num = dma_spec->args[0];
+ return dchan;
+}
+
static int parse_device_properties(struct axi_dma_chip *chip)
{
struct device *dev = chip->dev;
@@ -1233,6 +1250,13 @@ static int dw_probe(struct platform_device *pdev)
if (ret)
goto err_pm_disable;
+ /* Register with OF helpers for DMA lookups */
+ ret = of_dma_controller_register(pdev->dev.of_node,
+dw_axi_dma_of_xlate, dw);
+ if (ret < 0)
+ dev_warn(>dev,
+"Failed to register OF DMA controller, fallback to
MEM_TO_MEM mode\n");
+
dev_info(chip->dev, "DesignWare AXI DMA Controller, %d channels\n",
dw->hdata->nr_channels);
@@ -1266,6 +1290,8 @@ static int dw_remove(struct platform_device *pdev)
devm_free_irq(chip->dev, chip->irq, chip);
+ of_dma_controller_free(chip->dev->of_node);
+
list_for_each_entry_safe(chan, _chan, >dma.channels,
vc.chan.device_node) {
list_del(>vc.chan.device_node);
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
index a26b0a242a93..3498bef5453b 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
@@ -37,6 +37,7 @@ struct axi_dma_chan {
struct axi_dma_chip *chip;
void __iomem*chan_regs;
u8 id;
+ u8 hw_handshake_num;
atomic_tdescs_allocated;
struct dma_pool *desc_pool;
--
2.18.0
[PATCH v10 07/16] dmaegine: dw-axi-dmac: Support device_prep_dma_cyclic()
Add support for device_prep_dma_cyclic() callback function to benefit
DMA cyclic client, for example ALSA.
Existing AxiDMA driver only support data transfer between memory to memory.
Data transfer between device to memory and memory to device in cyclic mode
would failed if this interface is not supported by the AxiDMA driver.
Signed-off-by: Sia Jee Heng
Reviewed-by: Andy Shevchenko
Reviewed-by: Eugeniy Paltsev
Tested-by: Eugeniy Paltsev
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c| 111 --
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 2 +
2 files changed, 106 insertions(+), 7 deletions(-)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 7ff30b0f44ed..a76299360f69 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -15,6 +15,8 @@
#include
#include
#include
+#include
+#include
#include
#include
#include
@@ -549,6 +551,64 @@ static int dw_axi_dma_set_hw_desc(struct axi_dma_chan
*chan,
return 0;
}
+static struct dma_async_tx_descriptor *
+dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan, dma_addr_t dma_addr,
+ size_t buf_len, size_t period_len,
+ enum dma_transfer_direction direction,
+ unsigned long flags)
+{
+ struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
+ struct axi_dma_hw_desc *hw_desc = NULL;
+ struct axi_dma_desc *desc = NULL;
+ dma_addr_t src_addr = dma_addr;
+ u32 num_periods = buf_len / period_len;
+ unsigned int i;
+ int status;
+ u64 llp = 0;
+ u8 lms = 0; /* Select AXI0 master for LLI fetching */
+
+ desc = axi_desc_alloc(num_periods);
+ if (unlikely(!desc))
+ goto err_desc_get;
+
+ chan->direction = direction;
+ desc->chan = chan;
+ chan->cyclic = true;
+
+ for (i = 0; i < num_periods; i++) {
+ hw_desc = >hw_desc[i];
+
+ status = dw_axi_dma_set_hw_desc(chan, hw_desc, src_addr,
+ period_len);
+ if (status < 0)
+ goto err_desc_get;
+
+ /* Set end-of-link to the linked descriptor, so that cyclic
+* callback function can be triggered during interrupt.
+*/
+ set_desc_last(hw_desc);
+
+ src_addr += period_len;
+ }
+
+ llp = desc->hw_desc[0].llp;
+
+ /* Managed transfer list */
+ do {
+ hw_desc = >hw_desc[--num_periods];
+ write_desc_llp(hw_desc, llp | lms);
+ llp = hw_desc->llp;
+ } while (num_periods);
+
+ return vchan_tx_prep(>vc, >vd, flags);
+
+err_desc_get:
+ if (desc)
+ axi_desc_put(desc);
+
+ return NULL;
+}
+
static struct dma_async_tx_descriptor *
dw_axi_dma_chan_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl,
unsigned int sg_len,
@@ -773,8 +833,13 @@ static noinline void axi_chan_handle_err(struct
axi_dma_chan *chan, u32 status)
static void axi_chan_block_xfer_complete(struct axi_dma_chan *chan)
{
+ int count = atomic_read(>descs_allocated);
+ struct axi_dma_hw_desc *hw_desc;
+ struct axi_dma_desc *desc;
struct virt_dma_desc *vd;
unsigned long flags;
+ u64 llp;
+ int i;
spin_lock_irqsave(>vc.lock, flags);
if (unlikely(axi_chan_is_hw_enable(chan))) {
@@ -785,12 +850,32 @@ static void axi_chan_block_xfer_complete(struct
axi_dma_chan *chan)
/* The completed descriptor currently is in the head of vc list */
vd = vchan_next_desc(>vc);
- /* Remove the completed descriptor from issued list before completing */
- list_del(>node);
- vchan_cookie_complete(vd);
- /* Submit queued descriptors after processing the completed ones */
- axi_chan_start_first_queued(chan);
+ if (chan->cyclic) {
+ vchan_cyclic_callback(vd);
+ desc = vd_to_axi_desc(vd);
+ if (desc) {
+ llp = lo_hi_readq(chan->chan_regs + CH_LLP);
+ for (i = 0; i < count; i++) {
+ hw_desc = >hw_desc[i];
+ if (hw_desc->llp == llp) {
+ axi_chan_irq_clear(chan,
hw_desc->lli->status_lo);
+ hw_desc->lli->ctl_hi |=
CH_CTL_H_LLI_VALID;
+ desc->completed_blocks = i;
+ break;
+ }
+ }
+
+ axi_chan_enable(chan);
+ }
+ } else {
+
[PATCH v10 10/16] dt-binding: dma: dw-axi-dmac: Add support for Intel KeemBay AxiDMA
Add support for Intel KeemBay AxiDMA to the dw-axi-dmac Schemas DT binding. Signed-off-by: Sia Jee Heng Reviewed-by: Eugeniy Paltsev Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml | 5 + 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml index 3d2515463d56..79e241498e25 100644 --- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml +++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml @@ -8,6 +8,7 @@ title: Synopsys DesignWare AXI DMA Controller maintainers: - Eugeniy Paltsev + - Jee Heng Sia description: Synopsys DesignWare AXI DMA Controller DT Binding @@ -19,14 +20,18 @@ properties: compatible: enum: - snps,axi-dma-1.01a + - intel,kmb-axi-dma reg: +minItems: 1 items: - description: Address range of the DMAC registers + - description: Address range of the DMAC APB registers reg-names: items: - const: axidma_ctrl_regs + - const: axidma_apb_regs interrupts: maxItems: 1 -- 2.18.0
[PATCH v10 09/16] dmaengine: dw-axi-dmac: Support burst residue granularity
Add support for DMA_RESIDUE_GRANULARITY_BURST so that AxiDMA can report
DMA residue.
Existing AxiDMA driver only support data transfer between
memory to memory operation, therefore reporting DMA residue
to the DMA clients is not supported.
Reporting DMA residue to the DMA clients is important as DMA clients
shall invoke dmaengine_tx_status() to understand the number of bytes
been transferred so that the buffer pointer can be updated accordingly.
Signed-off-by: Sia Jee Heng
Reviewed-by: Andy Shevchenko
Reviewed-by: Eugeniy Paltsev
Tested-by: Eugeniy Paltsev
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c| 43 ---
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 2 +
2 files changed, 38 insertions(+), 7 deletions(-)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index a8b6c8c8ef58..830d3de76abd 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -265,14 +265,36 @@ dma_chan_tx_status(struct dma_chan *dchan, dma_cookie_t
cookie,
struct dma_tx_state *txstate)
{
struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
- enum dma_status ret;
+ struct virt_dma_desc *vdesc;
+ enum dma_status status;
+ u32 completed_length;
+ unsigned long flags;
+ u32 completed_blocks;
+ size_t bytes = 0;
+ u32 length;
+ u32 len;
- ret = dma_cookie_status(dchan, cookie, txstate);
+ status = dma_cookie_status(dchan, cookie, txstate);
+ if (status == DMA_COMPLETE || !txstate)
+ return status;
- if (chan->is_paused && ret == DMA_IN_PROGRESS)
- ret = DMA_PAUSED;
+ spin_lock_irqsave(>vc.lock, flags);
- return ret;
+ vdesc = vchan_find_desc(>vc, cookie);
+ if (vdesc) {
+ length = vd_to_axi_desc(vdesc)->length;
+ completed_blocks = vd_to_axi_desc(vdesc)->completed_blocks;
+ len = vd_to_axi_desc(vdesc)->hw_desc[0].len;
+ completed_length = completed_blocks * len;
+ bytes = length - completed_length;
+ } else {
+ bytes = vd_to_axi_desc(vdesc)->length;
+ }
+
+ spin_unlock_irqrestore(>vc.lock, flags);
+ dma_set_residue(txstate, bytes);
+
+ return status;
}
static void write_desc_llp(struct axi_dma_hw_desc *desc, dma_addr_t adr)
@@ -549,6 +571,7 @@ static int dw_axi_dma_set_hw_desc(struct axi_dma_chan *chan,
set_desc_src_master(hw_desc);
+ hw_desc->len = len;
return 0;
}
@@ -575,6 +598,7 @@ dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan,
dma_addr_t dma_addr,
chan->direction = direction;
desc->chan = chan;
chan->cyclic = true;
+ desc->length = 0;
for (i = 0; i < num_periods; i++) {
hw_desc = >hw_desc[i];
@@ -584,6 +608,7 @@ dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan,
dma_addr_t dma_addr,
if (status < 0)
goto err_desc_get;
+ desc->length += hw_desc->len;
/* Set end-of-link to the linked descriptor, so that cyclic
* callback function can be triggered during interrupt.
*/
@@ -636,6 +661,7 @@ dw_axi_dma_chan_prep_slave_sg(struct dma_chan *dchan,
struct scatterlist *sgl,
goto err_desc_get;
desc->chan = chan;
+ desc->length = 0;
for_each_sg(sgl, sg, sg_len, i) {
mem = sg_dma_address(sg);
@@ -645,6 +671,7 @@ dw_axi_dma_chan_prep_slave_sg(struct dma_chan *dchan,
struct scatterlist *sgl,
status = dw_axi_dma_set_hw_desc(chan, hw_desc, mem, len);
if (status < 0)
goto err_desc_get;
+ desc->length += hw_desc->len;
}
/* Set end-of-link to the last link descriptor of list */
@@ -690,6 +717,7 @@ dma_chan_prep_dma_memcpy(struct dma_chan *dchan, dma_addr_t
dst_adr,
desc->chan = chan;
num = 0;
+ desc->length = 0;
while (len) {
xfer_len = len;
@@ -742,7 +770,8 @@ dma_chan_prep_dma_memcpy(struct dma_chan *dchan, dma_addr_t
dst_adr,
set_desc_src_master(hw_desc);
set_desc_dest_master(hw_desc, desc);
-
+ hw_desc->len = xfer_len;
+ desc->length += hw_desc->len;
/* update the length and addresses for the next loop cycle */
len -= xfer_len;
dst_adr += xfer_len;
@@ -1210,7 +1239,7 @@ static int dw_probe(struct platform_device *pdev)
dw->dma.dst_addr_widths = AXI_DMA_BUSWIDTHS;
dw->dma.directions = BIT(DMA_MEM_TO_MEM);
dw->dma.directions |= BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM);
-
[PATCH v10 00/16] dmaengine: dw-axi-dmac: support Intel KeemBay AxiDMA
The below patch series are to support AxiDMA running on Intel KeemBay SoC. The base driver is dw-axi-dmac. This driver only support DMA memory copy transfers. Code refactoring is needed so that additional features can be supported. The features added in this patch series are: - Replacing Linked List with virtual descriptor management. - Remove unrelated hw desc stuff from dma memory pool. - Manage dma memory pool alloc/destroy based on channel activity. - Support dmaengine device_sync() callback. - Support dmaengine device_config(). - Support dmaengine device_prep_slave_sg(). - Support dmaengine device_prep_dma_cyclic(). - Support of_dma_controller_register(). - Support burst residue granularity. - Support Intel KeemBay AxiDMA registers. - Support Intel KeemBay AxiDMA device handshake. - Support Intel KeemBay AxiDMA BYTE and HALFWORD device operation. - Add constraint to Max segment size. - Virtually split the linked-list. This patch series are tested on Intel KeemBay platform. Eugeniy Paltsev has runtime tested this patch series on HSDK SoC/board. v10: - Rebased to kernel v5.11-rc4 - Added Reviewed-by and Tested-by tag from Eugeniy Paltsev. v9: - Logic checked on apb_regs inside the function. - Improved code scalability so that missing of apb_regs wouldn't failed the common callback functions. v8: - Rebased to kernel v5.11-rc1. - Added reviewed-by tag from Rob. v7: - Added 'allOf' and '$ref:dma-controller.yaml#' in DT binding. - Removed the dma-channels common description in DT binding. - Removed the default fields in DT binding. v6: - Removed 'allOf' cases in DT binding. - Added '>' at the end of the email address. - Removed additional '|' at the start of description. - Fixed space indent. - Added proper constraint in DT binding. - Removed second example in DT binding. v5: - Added comment to the Apb registers used by Intel KeemBay Soc. - Renamed "hs_num" to "handshake_num". - Conditional check for the compatible property and return error instead of printing warning. - Added patch 16th to virtually split the linked-list as per request from ALSA team. v4: - Fixed bot found errors running make_dt_binding_check. - Added minItems: 1 to the YAML schemas DT binding. - Updated "reg" field to the YAML schemas DT binding. v3: - Added additionalProperties: false to the YAML schemas DT binding. - Reordered patch sequence for patch 10th, 11th and 12th so that DT binding come first, follow by adding Intel KeemBay SoC registers and update .compatible field. - Checked txstate NULL condition. - Created helper function dw_axi_dma_set_hw_desc() to handle common code. v2: - Rebased to v5.10-rc1 kernel. - Added support for dmaengine device_config(). - Added support for dmaengine device_prep_slave_sg(). - Added support for dmaengine device_prep_dma_cyclic(). - Added support for of_dma_controller_register(). - Added support for burst residue granularity. - Added support for Intel KeemBay AxiDMA registers. - Added support for Intel KeemBay AxiDMA device handshake. - Added support for Intel KeemBay AxiDMA BYTE and HALFWORD device operation. - Added constraint to Max segment size. v1: - Initial version. Patch on top of dw-axi-dma driver. This version improve the descriptor management by replacing Linked List Item (LLI) with virtual descriptor management, only allocate hardware LLI memories from DMA memory pool, manage DMA memory pool alloc/destroy based on channel activity and to support device_sync callback. Sia Jee Heng (16): dt-bindings: dma: Add YAML schemas for dw-axi-dmac dmaengine: dw-axi-dmac: simplify descriptor management dmaengine: dw-axi-dmac: move dma_pool_create() to alloc_chan_resources() dmaengine: dw-axi-dmac: Add device_synchronize() callback dmaengine: dw-axi-dmac: Add device_config operation dmaengine: dw-axi-dmac: Support device_prep_slave_sg dmaegine: dw-axi-dmac: Support device_prep_dma_cyclic() dmaengine: dw-axi-dmac: Support of_dma_controller_register() dmaengine: dw-axi-dmac: Support burst residue granularity dt-binding: dma: dw-axi-dmac: Add support for Intel KeemBay AxiDMA dmaengine: dw-axi-dmac: Add Intel KeemBay DMA register fields dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA support dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA handshake dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA BYTE and HALFWORD registers dmaengine: dw-axi-dmac: Set constraint to the Max segment size dmaengine: dw-axi-dmac: Virtually split the linked-list .../bindings/dma/snps,dw-axi-dmac.txt | 39 - .../bindings/dma/snps,dw-axi-dmac.yaml| 126 .../dma/dw-axi-dmac/dw-axi-dmac-platform.c| 697 +++--- drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 34 +- 4 files changed, 764 insertions(+), 132 deletions(-) delete mode 100644 Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt create mode 100644 Documentation/devicetree/bindings/dma/sn
[PATCH v10 03/16] dmaengine: dw-axi-dmac: move dma_pool_create() to alloc_chan_resources()
The DMA memory block is created at driver load time and exist for
device lifetime. Move the dma_pool_create() to the ->chan_resource()
callback function allowing the DMA memory blocks to be created as needed
and destroyed when the channel is freed.
Signed-off-by: Sia Jee Heng
Reviewed-by: Andy Shevchenko
Reviewed-by: Eugeniy Paltsev
Tested-by: Eugeniy Paltsev
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c| 24 ++-
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 2 +-
2 files changed, 14 insertions(+), 12 deletions(-)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 350968baaf88..3737e1c3c793 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -216,11 +216,10 @@ static struct axi_dma_desc *axi_desc_alloc(u32 num)
static struct axi_dma_lli *axi_desc_get(struct axi_dma_chan *chan,
dma_addr_t *addr)
{
- struct dw_axi_dma *dw = chan->chip->dw;
struct axi_dma_lli *lli;
dma_addr_t phys;
- lli = dma_pool_zalloc(dw->desc_pool, GFP_NOWAIT, );
+ lli = dma_pool_zalloc(chan->desc_pool, GFP_NOWAIT, );
if (unlikely(!lli)) {
dev_err(chan2dev(chan), "%s: not enough descriptors
available\n",
axi_chan_name(chan));
@@ -236,14 +235,13 @@ static struct axi_dma_lli *axi_desc_get(struct
axi_dma_chan *chan,
static void axi_desc_put(struct axi_dma_desc *desc)
{
struct axi_dma_chan *chan = desc->chan;
- struct dw_axi_dma *dw = chan->chip->dw;
int count = atomic_read(>descs_allocated);
struct axi_dma_hw_desc *hw_desc;
int descs_put;
for (descs_put = 0; descs_put < count; descs_put++) {
hw_desc = >hw_desc[descs_put];
- dma_pool_free(dw->desc_pool, hw_desc->lli, hw_desc->llp);
+ dma_pool_free(chan->desc_pool, hw_desc->lli, hw_desc->llp);
}
kfree(desc->hw_desc);
@@ -360,6 +358,15 @@ static int dma_chan_alloc_chan_resources(struct dma_chan
*dchan)
return -EBUSY;
}
+ /* LLI address must be aligned to a 64-byte boundary */
+ chan->desc_pool = dma_pool_create(dev_name(chan2dev(chan)),
+ chan->chip->dev,
+ sizeof(struct axi_dma_lli),
+ 64, 0);
+ if (!chan->desc_pool) {
+ dev_err(chan2dev(chan), "No memory for descriptors\n");
+ return -ENOMEM;
+ }
dev_vdbg(dchan2dev(dchan), "%s: allocating\n", axi_chan_name(chan));
pm_runtime_get(chan->chip->dev);
@@ -381,6 +388,8 @@ static void dma_chan_free_chan_resources(struct dma_chan
*dchan)
vchan_free_chan_resources(>vc);
+ dma_pool_destroy(chan->desc_pool);
+ chan->desc_pool = NULL;
dev_vdbg(dchan2dev(dchan),
"%s: free resources, descriptor still allocated: %u\n",
axi_chan_name(chan), atomic_read(>descs_allocated));
@@ -896,13 +905,6 @@ static int dw_probe(struct platform_device *pdev)
if (ret)
return ret;
- /* Lli address must be aligned to a 64-byte boundary */
- dw->desc_pool = dmam_pool_create(KBUILD_MODNAME, chip->dev,
-sizeof(struct axi_dma_lli), 64, 0);
- if (!dw->desc_pool) {
- dev_err(chip->dev, "No memory for descriptors dma pool\n");
- return -ENOMEM;
- }
INIT_LIST_HEAD(>dma.channels);
for (i = 0; i < hdata->nr_channels; i++) {
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
index 41e775e6e593..f886b2bb75de 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
@@ -39,6 +39,7 @@ struct axi_dma_chan {
u8 id;
atomic_tdescs_allocated;
+ struct dma_pool *desc_pool;
struct virt_dma_chanvc;
struct axi_dma_desc *desc;
@@ -49,7 +50,6 @@ struct axi_dma_chan {
struct dw_axi_dma {
struct dma_device dma;
struct dw_axi_dma_hcfg *hdata;
- struct dma_pool *desc_pool;
/* channels */
struct axi_dma_chan *chan;
--
2.18.0
[PATCH v10 01/16] dt-bindings: dma: Add YAML schemas for dw-axi-dmac
YAML schemas Device Tree (DT) binding is the new format for DT to replace
the old format. Introduce YAML schemas DT binding for dw-axi-dmac and
remove the old version.
Signed-off-by: Sia Jee Heng
Reviewed-by: Eugeniy Paltsev
Reviewed-by: Rob Herring
---
.../bindings/dma/snps,dw-axi-dmac.txt | 39 --
.../bindings/dma/snps,dw-axi-dmac.yaml| 121 ++
2 files changed, 121 insertions(+), 39 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt
create mode 100644 Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt
b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt
deleted file mode 100644
index dbe160400adc..
--- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt
+++ /dev/null
@@ -1,39 +0,0 @@
-Synopsys DesignWare AXI DMA Controller
-
-Required properties:
-- compatible: "snps,axi-dma-1.01a"
-- reg: Address range of the DMAC registers. This should include
- all of the per-channel registers.
-- interrupt: Should contain the DMAC interrupt number.
-- dma-channels: Number of channels supported by hardware.
-- snps,dma-masters: Number of AXI masters supported by the hardware.
-- snps,data-width: Maximum AXI data width supported by hardware.
- (0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits)
-- snps,priority: Priority of channel. Array size is equal to the number of
- dma-channels. Priority value must be programmed within [0:dma-channels-1]
- range. (0 - minimum priority)
-- snps,block-size: Maximum block size supported by the controller channel.
- Array size is equal to the number of dma-channels.
-
-Optional properties:
-- snps,axi-max-burst-len: Restrict master AXI burst length by value specified
- in this property. If this property is missing the maximum AXI burst length
- supported by DMAC is used. [1:256]
-
-Example:
-
-dmac: dma-controller@8 {
- compatible = "snps,axi-dma-1.01a";
- reg = <0x8 0x400>;
- clocks = <_clk>, <_clk>;
- clock-names = "core-clk", "cfgr-clk";
- interrupt-parent = <>;
- interrupts = <27>;
-
- dma-channels = <4>;
- snps,dma-masters = <2>;
- snps,data-width = <3>;
- snps,block-size = <4096 4096 4096 4096>;
- snps,priority = <0 1 2 3>;
- snps,axi-max-burst-len = <16>;
-};
diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
new file mode 100644
index ..3d2515463d56
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
@@ -0,0 +1,121 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/snps,dw-axi-dmac.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Synopsys DesignWare AXI DMA Controller
+
+maintainers:
+ - Eugeniy Paltsev
+
+description:
+ Synopsys DesignWare AXI DMA Controller DT Binding
+
+allOf:
+ - $ref: "dma-controller.yaml#"
+
+properties:
+ compatible:
+enum:
+ - snps,axi-dma-1.01a
+
+ reg:
+items:
+ - description: Address range of the DMAC registers
+
+ reg-names:
+items:
+ - const: axidma_ctrl_regs
+
+ interrupts:
+maxItems: 1
+
+ clocks:
+items:
+ - description: Bus Clock
+ - description: Module Clock
+
+ clock-names:
+items:
+ - const: core-clk
+ - const: cfgr-clk
+
+ '#dma-cells':
+const: 1
+
+ dma-channels:
+minimum: 1
+maximum: 8
+
+ snps,dma-masters:
+description: |
+ Number of AXI masters supported by the hardware.
+$ref: /schemas/types.yaml#/definitions/uint32
+enum: [1, 2]
+
+ snps,data-width:
+description: |
+ AXI data width supported by hardware.
+ (0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits)
+$ref: /schemas/types.yaml#/definitions/uint32
+enum: [0, 1, 2, 3, 4, 5, 6]
+
+ snps,priority:
+description: |
+ Channel priority specifier associated with the DMA channels.
+$ref: /schemas/types.yaml#/definitions/uint32-array
+minItems: 1
+maxItems: 8
+
+ snps,block-size:
+description: |
+ Channel block size specifier associated with the DMA channels.
+$ref: /schemas/types.yaml#/definitions/uint32-array
+minItems: 1
+maxItems: 8
+
+ snps,axi-max-burst-len:
+description: |
+ Restrict master AXI burst length by value specified in this property.
+ If this property is missing the maximum AXI burst length supported by
+ DMAC is used.
+$ref: /schemas/types.yaml#/definitions/uint32
+minimum: 1
+maximum: 256
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - interrupts
+ - '#dma-cells'
+ - dma-channels
+ - snps,dma-masters
+ - snps,data-width
+ -
Re: [PATCH v9 00/16] dmaengine: dw-axi-dmac: support Intel KeemBay AxiDMA
Hi Eugeniy Paltsev, Could you please resend your below Reviewed-by and tested-by tag with plain text format? I am not seeing your below acknowledgement reflected to the mailing list. In fact, when I replied on top of your mail, I am receiving below errors: The following message to was undeliverable. The reason for the problem: 5.3.0 - Other mail system problem 550-'5.7.1 Content-Policy reject msg: The message contains HTML subpart, therefore we consider it SPAM or Outlook Virus. TEXT/PLAIN is accepted.! BF:; S1731521AbhATMql' The following message to was undeliverable. The reason for the problem: 5.3.0 - Other mail system problem 550-'5.7.1 Content-Policy reject msg: The message contains HTML subpart, therefore we consider it SPAM or Outlook Virus. TEXT/PLAIN is accepted.! BF:; S1731521AbhATMql' The following message to was undeliverable. The reason for the problem: 5.3.0 - Other mail system problem 550-'5.7.1 Content-Policy reject msg: The message contains HTML subpart, therefore we consider it SPAM or Outlook Virus. TEXT/PLAIN is accepted.! BF:; S1731521AbhATMql' Thanks Regards Jee Heng From: Eugeniy Paltsev Sent: 18 January 2021 8:54 PM To: Sia, Jee Heng ; vk...@kernel.org Cc: andriy.shevche...@linux.intel.com; dmaeng...@vger.kernel.org; linux-kernel@vger.kernel.org; devicet...@vger.kernel.org; robh...@kernel.org Subject: Re: [PATCH v9 00/16] dmaengine: dw-axi-dmac: support Intel KeemBay AxiDMA Hi Sia Jee Heng, Reviewed-by: Eugeniy Paltsev I've runtime tested this series on HSDK SoC/board, so Tested-by: Eugeniy Paltsev --- Eugeniy Paltsev From: Sia Jee Heng Sent: Tuesday, January 5, 2021 03:42 To: vk...@kernel.org ; Eugeniy Paltsev ; robh...@kernel.org Cc: andriy.shevche...@linux.intel.com ; dmaeng...@vger.kernel.org ; linux-kernel@vger.kernel.org ; devicet...@vger.kernel.org Subject: [PATCH v9 00/16] dmaengine: dw-axi-dmac: support Intel KeemBay AxiDMA The below patch series are to support AxiDMA running on Intel KeemBay SoC. The base driver is dw-axi-dmac. This driver only support DMA memory copy transfers. Code refactoring is needed so that additional features can be supported. The features added in this patch series are: - Replacing Linked List with virtual descriptor management. - Remove unrelated hw desc stuff from dma memory pool. - Manage dma memory pool alloc/destroy based on channel activity. - Support dmaengine device_sync() callback. - Support dmaengine device_config(). - Support dmaengine device_prep_slave_sg(). - Support dmaengine device_prep_dma_cyclic(). - Support of_dma_controller_register(). - Support burst residue granularity. - Support Intel KeemBay AxiDMA registers. - Support Intel KeemBay AxiDMA device handshake. - Support Intel KeemBay AxiDMA BYTE and HALFWORD device operation. - Add constraint to Max segment size. - Virtually split the linked-list. This patch series are tested on Intel KeemBay platform. v9: - Logic checked on apb_regs inside the function. - Improved code scalability so that missing of apb_regs wouldn't failed the common callback functions. v8: - Rebased to kernel v5.11-rc1. - Added reviewed-by tag from Rob. v7: - Added 'allOf' and '$ref:dma-controller.yaml#' in DT binding. - Removed the dma-channels common description in DT binding. - Removed the default fields in DT binding. v6: - Removed 'allOf' cases in DT binding. - Added '>' at the end of the email address. - Removed additional '|' at the start of description. - Fixed space indent. - Added proper constraint in DT binding. - Removed second example in DT binding. v5: - Added comment to the Apb registers used by Intel KeemBay Soc. - Renamed "hs_num" to "handshake_num". - Conditional check for the compatible property and return error instead of printing warning. - Added patch 16th to virtually split the linked-list as per request from ALSA team. v4: - Fixed bot found errors running make_dt_binding_check. - Added minItems: 1 to the YAML schemas DT binding. - Updated "reg" field to the YAML schemas DT binding. v3: - Added additionalProperties: false to the YAML schemas DT binding. - Reordered patch sequence for patch 10th, 11th and 12th so that DT binding come first, follow by adding Intel KeemBay SoC registers and update .compatible field. - Checked txstate NULL condition. - Created helper function dw_axi_dma_set_hw_desc() to handle common code. v2: - Rebased to v5.10-rc1 kernel. - Added support for dmaengine device_config(). - Added support for dmaengine device_prep_slave_sg(). - Added support for dmaengine device_prep_dma_cyclic(). - Added support for of_dma_controller_register(). - Added support for burst residue granularity. - Added support for Intel KeemBay AxiDMA registers. - Added support for Intel KeemBay AxiDMA device handshake. - Added support for Intel KeemBay AxiDMA BYTE and HALFWORD device operation. - Added constraint to
[PATCH v9 02/16] dmaengine: dw-axi-dmac: simplify descriptor management
Simplify and refactor the descriptor management by removing the redundant
Linked List Item (LLI) queue control logic from the AxiDMA driver.
The descriptor is split into virtual descriptor and hardware LLI so that
only hardware LLI memories are allocated from the DMA memory pool.
Up to 64 descriptors can be allocated within a PAGE_SIZE compare to 16
descriptors in previous version. This solves the problem where an
ALSA driver expects more than 16 DMA descriptors to run.
Reviewed-by: Andy Shevchenko
Signed-off-by: Sia Jee Heng
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c| 164 ++
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 9 +-
2 files changed, 102 insertions(+), 71 deletions(-)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index e164f3295f5d..350968baaf88 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -21,6 +21,7 @@
#include
#include
#include
+#include
#include
#include "dw-axi-dmac.h"
@@ -195,43 +196,58 @@ static inline const char *axi_chan_name(struct
axi_dma_chan *chan)
return dma_chan_name(>vc.chan);
}
-static struct axi_dma_desc *axi_desc_get(struct axi_dma_chan *chan)
+static struct axi_dma_desc *axi_desc_alloc(u32 num)
{
- struct dw_axi_dma *dw = chan->chip->dw;
struct axi_dma_desc *desc;
+
+ desc = kzalloc(sizeof(*desc), GFP_NOWAIT);
+ if (!desc)
+ return NULL;
+
+ desc->hw_desc = kcalloc(num, sizeof(*desc->hw_desc), GFP_NOWAIT);
+ if (!desc->hw_desc) {
+ kfree(desc);
+ return NULL;
+ }
+
+ return desc;
+}
+
+static struct axi_dma_lli *axi_desc_get(struct axi_dma_chan *chan,
+ dma_addr_t *addr)
+{
+ struct dw_axi_dma *dw = chan->chip->dw;
+ struct axi_dma_lli *lli;
dma_addr_t phys;
- desc = dma_pool_zalloc(dw->desc_pool, GFP_NOWAIT, );
- if (unlikely(!desc)) {
+ lli = dma_pool_zalloc(dw->desc_pool, GFP_NOWAIT, );
+ if (unlikely(!lli)) {
dev_err(chan2dev(chan), "%s: not enough descriptors
available\n",
axi_chan_name(chan));
return NULL;
}
atomic_inc(>descs_allocated);
- INIT_LIST_HEAD(>xfer_list);
- desc->vd.tx.phys = phys;
- desc->chan = chan;
+ *addr = phys;
- return desc;
+ return lli;
}
static void axi_desc_put(struct axi_dma_desc *desc)
{
struct axi_dma_chan *chan = desc->chan;
struct dw_axi_dma *dw = chan->chip->dw;
- struct axi_dma_desc *child, *_next;
- unsigned int descs_put = 0;
+ int count = atomic_read(>descs_allocated);
+ struct axi_dma_hw_desc *hw_desc;
+ int descs_put;
- list_for_each_entry_safe(child, _next, >xfer_list, xfer_list) {
- list_del(>xfer_list);
- dma_pool_free(dw->desc_pool, child, child->vd.tx.phys);
- descs_put++;
+ for (descs_put = 0; descs_put < count; descs_put++) {
+ hw_desc = >hw_desc[descs_put];
+ dma_pool_free(dw->desc_pool, hw_desc->lli, hw_desc->llp);
}
- dma_pool_free(dw->desc_pool, desc, desc->vd.tx.phys);
- descs_put++;
-
+ kfree(desc->hw_desc);
+ kfree(desc);
atomic_sub(descs_put, >descs_allocated);
dev_vdbg(chan2dev(chan), "%s: %d descs put, %d still allocated\n",
axi_chan_name(chan), descs_put,
@@ -258,9 +274,9 @@ dma_chan_tx_status(struct dma_chan *dchan, dma_cookie_t
cookie,
return ret;
}
-static void write_desc_llp(struct axi_dma_desc *desc, dma_addr_t adr)
+static void write_desc_llp(struct axi_dma_hw_desc *desc, dma_addr_t adr)
{
- desc->lli.llp = cpu_to_le64(adr);
+ desc->lli->llp = cpu_to_le64(adr);
}
static void write_chan_llp(struct axi_dma_chan *chan, dma_addr_t adr)
@@ -295,7 +311,7 @@ static void axi_chan_block_xfer_start(struct axi_dma_chan
*chan,
DWAXIDMAC_HS_SEL_HW << CH_CFG_H_HS_SEL_SRC_POS);
axi_chan_iowrite32(chan, CH_CFG_H, reg);
- write_chan_llp(chan, first->vd.tx.phys | lms);
+ write_chan_llp(chan, first->hw_desc[0].llp | lms);
irq_mask = DWAXIDMAC_IRQ_DMA_TRF | DWAXIDMAC_IRQ_ALL_ERR;
axi_chan_irq_sig_set(chan, irq_mask);
@@ -378,67 +394,78 @@ static void dma_chan_free_chan_resources(struct dma_chan
*dchan)
* transfer and completes the DMA transfer operation at the end of current
* block transfer.
*/
-static void set_desc_last(struct axi_dma_desc *desc)
+static void set_desc_last(struct axi_dma_hw_desc *desc)
{
u32 val;
- val = le32_to_cpu(desc->lli.ctl_hi);
+ val = le32_to_cpu(desc->lli-&g
[PATCH v9 01/16] dt-bindings: dma: Add YAML schemas for dw-axi-dmac
YAML schemas Device Tree (DT) binding is the new format for DT to replace
the old format. Introduce YAML schemas DT binding for dw-axi-dmac and
remove the old version.
Signed-off-by: Sia Jee Heng
Reviewed-by: Rob Herring
---
.../bindings/dma/snps,dw-axi-dmac.txt | 39 --
.../bindings/dma/snps,dw-axi-dmac.yaml| 121 ++
2 files changed, 121 insertions(+), 39 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt
create mode 100644 Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt
b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt
deleted file mode 100644
index dbe160400adc..
--- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt
+++ /dev/null
@@ -1,39 +0,0 @@
-Synopsys DesignWare AXI DMA Controller
-
-Required properties:
-- compatible: "snps,axi-dma-1.01a"
-- reg: Address range of the DMAC registers. This should include
- all of the per-channel registers.
-- interrupt: Should contain the DMAC interrupt number.
-- dma-channels: Number of channels supported by hardware.
-- snps,dma-masters: Number of AXI masters supported by the hardware.
-- snps,data-width: Maximum AXI data width supported by hardware.
- (0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits)
-- snps,priority: Priority of channel. Array size is equal to the number of
- dma-channels. Priority value must be programmed within [0:dma-channels-1]
- range. (0 - minimum priority)
-- snps,block-size: Maximum block size supported by the controller channel.
- Array size is equal to the number of dma-channels.
-
-Optional properties:
-- snps,axi-max-burst-len: Restrict master AXI burst length by value specified
- in this property. If this property is missing the maximum AXI burst length
- supported by DMAC is used. [1:256]
-
-Example:
-
-dmac: dma-controller@8 {
- compatible = "snps,axi-dma-1.01a";
- reg = <0x8 0x400>;
- clocks = <_clk>, <_clk>;
- clock-names = "core-clk", "cfgr-clk";
- interrupt-parent = <>;
- interrupts = <27>;
-
- dma-channels = <4>;
- snps,dma-masters = <2>;
- snps,data-width = <3>;
- snps,block-size = <4096 4096 4096 4096>;
- snps,priority = <0 1 2 3>;
- snps,axi-max-burst-len = <16>;
-};
diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
new file mode 100644
index ..3d2515463d56
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
@@ -0,0 +1,121 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/snps,dw-axi-dmac.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Synopsys DesignWare AXI DMA Controller
+
+maintainers:
+ - Eugeniy Paltsev
+
+description:
+ Synopsys DesignWare AXI DMA Controller DT Binding
+
+allOf:
+ - $ref: "dma-controller.yaml#"
+
+properties:
+ compatible:
+enum:
+ - snps,axi-dma-1.01a
+
+ reg:
+items:
+ - description: Address range of the DMAC registers
+
+ reg-names:
+items:
+ - const: axidma_ctrl_regs
+
+ interrupts:
+maxItems: 1
+
+ clocks:
+items:
+ - description: Bus Clock
+ - description: Module Clock
+
+ clock-names:
+items:
+ - const: core-clk
+ - const: cfgr-clk
+
+ '#dma-cells':
+const: 1
+
+ dma-channels:
+minimum: 1
+maximum: 8
+
+ snps,dma-masters:
+description: |
+ Number of AXI masters supported by the hardware.
+$ref: /schemas/types.yaml#/definitions/uint32
+enum: [1, 2]
+
+ snps,data-width:
+description: |
+ AXI data width supported by hardware.
+ (0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits)
+$ref: /schemas/types.yaml#/definitions/uint32
+enum: [0, 1, 2, 3, 4, 5, 6]
+
+ snps,priority:
+description: |
+ Channel priority specifier associated with the DMA channels.
+$ref: /schemas/types.yaml#/definitions/uint32-array
+minItems: 1
+maxItems: 8
+
+ snps,block-size:
+description: |
+ Channel block size specifier associated with the DMA channels.
+$ref: /schemas/types.yaml#/definitions/uint32-array
+minItems: 1
+maxItems: 8
+
+ snps,axi-max-burst-len:
+description: |
+ Restrict master AXI burst length by value specified in this property.
+ If this property is missing the maximum AXI burst length supported by
+ DMAC is used.
+$ref: /schemas/types.yaml#/definitions/uint32
+minimum: 1
+maximum: 256
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - interrupts
+ - '#dma-cells'
+ - dma-channels
+ - snps,dma-masters
+ - snps,data-width
+ - snps,priority
+ - snps,block-size
+
+ad
[PATCH v9 06/16] dmaengine: dw-axi-dmac: Support device_prep_slave_sg
Add device_prep_slave_sg() callback function so that DMA_MEM_TO_DEV
and DMA_DEV_TO_MEM operations in single mode can be supported.
Existing AxiDMA driver only support data transfer between
memory to memory. Data transfer between device to memory and
memory to device in single mode would failed if this interface
is not supported by the AxiDMA driver.
Reviewed-by: Andy Shevchenko
Signed-off-by: Sia Jee Heng
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c| 154 ++
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 1 +
2 files changed, 155 insertions(+)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index eaa7c4c404ca..7ff30b0f44ed 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -307,6 +307,22 @@ static void axi_chan_block_xfer_start(struct axi_dma_chan
*chan,
priority << CH_CFG_H_PRIORITY_POS |
DWAXIDMAC_HS_SEL_HW << CH_CFG_H_HS_SEL_DST_POS |
DWAXIDMAC_HS_SEL_HW << CH_CFG_H_HS_SEL_SRC_POS);
+ switch (chan->direction) {
+ case DMA_MEM_TO_DEV:
+ reg |= (chan->config.device_fc ?
+ DWAXIDMAC_TT_FC_MEM_TO_PER_DST :
+ DWAXIDMAC_TT_FC_MEM_TO_PER_DMAC)
+ << CH_CFG_H_TT_FC_POS;
+ break;
+ case DMA_DEV_TO_MEM:
+ reg |= (chan->config.device_fc ?
+ DWAXIDMAC_TT_FC_PER_TO_MEM_SRC :
+ DWAXIDMAC_TT_FC_PER_TO_MEM_DMAC)
+ << CH_CFG_H_TT_FC_POS;
+ break;
+ default:
+ break;
+ }
axi_chan_iowrite32(chan, CH_CFG_H, reg);
write_chan_llp(chan, first->hw_desc[0].llp | lms);
@@ -454,6 +470,141 @@ static void set_desc_dest_master(struct axi_dma_hw_desc
*hw_desc,
hw_desc->lli->ctl_lo = cpu_to_le32(val);
}
+static int dw_axi_dma_set_hw_desc(struct axi_dma_chan *chan,
+ struct axi_dma_hw_desc *hw_desc,
+ dma_addr_t mem_addr, size_t len)
+{
+ unsigned int data_width = BIT(chan->chip->dw->hdata->m_data_width);
+ unsigned int reg_width;
+ unsigned int mem_width;
+ dma_addr_t device_addr;
+ size_t axi_block_ts;
+ size_t block_ts;
+ u32 ctllo, ctlhi;
+ u32 burst_len;
+
+ axi_block_ts = chan->chip->dw->hdata->block_size[chan->id];
+
+ mem_width = __ffs(data_width | mem_addr | len);
+ if (mem_width > DWAXIDMAC_TRANS_WIDTH_32)
+ mem_width = DWAXIDMAC_TRANS_WIDTH_32;
+
+ switch (chan->direction) {
+ case DMA_MEM_TO_DEV:
+ reg_width = __ffs(chan->config.dst_addr_width);
+ device_addr = chan->config.dst_addr;
+ ctllo = reg_width << CH_CTL_L_DST_WIDTH_POS |
+ mem_width << CH_CTL_L_SRC_WIDTH_POS |
+ DWAXIDMAC_CH_CTL_L_NOINC << CH_CTL_L_DST_INC_POS |
+ DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_SRC_INC_POS;
+ block_ts = len >> mem_width;
+ break;
+ case DMA_DEV_TO_MEM:
+ reg_width = __ffs(chan->config.src_addr_width);
+ device_addr = chan->config.src_addr;
+ ctllo = reg_width << CH_CTL_L_SRC_WIDTH_POS |
+ mem_width << CH_CTL_L_DST_WIDTH_POS |
+ DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_DST_INC_POS |
+ DWAXIDMAC_CH_CTL_L_NOINC << CH_CTL_L_SRC_INC_POS;
+ block_ts = len >> reg_width;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (block_ts > axi_block_ts)
+ return -EINVAL;
+
+ hw_desc->lli = axi_desc_get(chan, _desc->llp);
+ if (unlikely(!hw_desc->lli))
+ return -ENOMEM;
+
+ ctlhi = CH_CTL_H_LLI_VALID;
+
+ if (chan->chip->dw->hdata->restrict_axi_burst_len) {
+ burst_len = chan->chip->dw->hdata->axi_rw_burst_len;
+ ctlhi |= CH_CTL_H_ARLEN_EN | CH_CTL_H_AWLEN_EN |
+burst_len << CH_CTL_H_ARLEN_POS |
+burst_len << CH_CTL_H_AWLEN_POS;
+ }
+
+ hw_desc->lli->ctl_hi = cpu_to_le32(ctlhi);
+
+ if (chan->direction == DMA_MEM_TO_DEV) {
+ write_desc_sar(hw_desc, mem_addr);
+ write_desc_dar(hw_desc, device_addr);
+ } else {
+ write_desc_sar(hw_desc, device_addr);
+ write_desc_dar(hw_desc, mem_addr);
+ }
+
+ hw_desc->lli->block_ts_lo = cpu_to_le32(block_ts - 1);
+
+ ctllo |= DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CT
[PATCH v9 07/16] dmaegine: dw-axi-dmac: Support device_prep_dma_cyclic()
Add support for device_prep_dma_cyclic() callback function to benefit
DMA cyclic client, for example ALSA.
Existing AxiDMA driver only support data transfer between memory to memory.
Data transfer between device to memory and memory to device in cyclic mode
would failed if this interface is not supported by the AxiDMA driver.
Reviewed-by: Andy Shevchenko
Signed-off-by: Sia Jee Heng
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c| 111 --
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 2 +
2 files changed, 106 insertions(+), 7 deletions(-)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 7ff30b0f44ed..a76299360f69 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -15,6 +15,8 @@
#include
#include
#include
+#include
+#include
#include
#include
#include
@@ -549,6 +551,64 @@ static int dw_axi_dma_set_hw_desc(struct axi_dma_chan
*chan,
return 0;
}
+static struct dma_async_tx_descriptor *
+dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan, dma_addr_t dma_addr,
+ size_t buf_len, size_t period_len,
+ enum dma_transfer_direction direction,
+ unsigned long flags)
+{
+ struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
+ struct axi_dma_hw_desc *hw_desc = NULL;
+ struct axi_dma_desc *desc = NULL;
+ dma_addr_t src_addr = dma_addr;
+ u32 num_periods = buf_len / period_len;
+ unsigned int i;
+ int status;
+ u64 llp = 0;
+ u8 lms = 0; /* Select AXI0 master for LLI fetching */
+
+ desc = axi_desc_alloc(num_periods);
+ if (unlikely(!desc))
+ goto err_desc_get;
+
+ chan->direction = direction;
+ desc->chan = chan;
+ chan->cyclic = true;
+
+ for (i = 0; i < num_periods; i++) {
+ hw_desc = >hw_desc[i];
+
+ status = dw_axi_dma_set_hw_desc(chan, hw_desc, src_addr,
+ period_len);
+ if (status < 0)
+ goto err_desc_get;
+
+ /* Set end-of-link to the linked descriptor, so that cyclic
+* callback function can be triggered during interrupt.
+*/
+ set_desc_last(hw_desc);
+
+ src_addr += period_len;
+ }
+
+ llp = desc->hw_desc[0].llp;
+
+ /* Managed transfer list */
+ do {
+ hw_desc = >hw_desc[--num_periods];
+ write_desc_llp(hw_desc, llp | lms);
+ llp = hw_desc->llp;
+ } while (num_periods);
+
+ return vchan_tx_prep(>vc, >vd, flags);
+
+err_desc_get:
+ if (desc)
+ axi_desc_put(desc);
+
+ return NULL;
+}
+
static struct dma_async_tx_descriptor *
dw_axi_dma_chan_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl,
unsigned int sg_len,
@@ -773,8 +833,13 @@ static noinline void axi_chan_handle_err(struct
axi_dma_chan *chan, u32 status)
static void axi_chan_block_xfer_complete(struct axi_dma_chan *chan)
{
+ int count = atomic_read(>descs_allocated);
+ struct axi_dma_hw_desc *hw_desc;
+ struct axi_dma_desc *desc;
struct virt_dma_desc *vd;
unsigned long flags;
+ u64 llp;
+ int i;
spin_lock_irqsave(>vc.lock, flags);
if (unlikely(axi_chan_is_hw_enable(chan))) {
@@ -785,12 +850,32 @@ static void axi_chan_block_xfer_complete(struct
axi_dma_chan *chan)
/* The completed descriptor currently is in the head of vc list */
vd = vchan_next_desc(>vc);
- /* Remove the completed descriptor from issued list before completing */
- list_del(>node);
- vchan_cookie_complete(vd);
- /* Submit queued descriptors after processing the completed ones */
- axi_chan_start_first_queued(chan);
+ if (chan->cyclic) {
+ vchan_cyclic_callback(vd);
+ desc = vd_to_axi_desc(vd);
+ if (desc) {
+ llp = lo_hi_readq(chan->chan_regs + CH_LLP);
+ for (i = 0; i < count; i++) {
+ hw_desc = >hw_desc[i];
+ if (hw_desc->llp == llp) {
+ axi_chan_irq_clear(chan,
hw_desc->lli->status_lo);
+ hw_desc->lli->ctl_hi |=
CH_CTL_H_LLI_VALID;
+ desc->completed_blocks = i;
+ break;
+ }
+ }
+
+ axi_chan_enable(chan);
+ }
+ } else {
+ /* Remove the completed descriptor from issued list before
completing *
[PATCH v9 14/16] dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA BYTE and HALFWORD registers
Add support for Intel KeemBay AxiDMA BYTE and HALFWORD registers
programming.
Intel KeemBay AxiDMA supports data transfer between device to memory
and memory to device operations.
This code is needed by I2C, I3C, I2S, SPI and UART which uses FIFO
size of 8bits and 16bits to perform memory to device data transfer
operation. 0-padding functionality is provided to avoid
pre-processing of data on CPU.
Reviewed-by: Andy Shevchenko
Signed-off-by: Sia Jee Heng
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c| 27 +++
1 file changed, 27 insertions(+)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index e19369f9365a..ea527b92e0fc 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -307,6 +307,30 @@ static void write_chan_llp(struct axi_dma_chan *chan,
dma_addr_t adr)
axi_chan_iowrite64(chan, CH_LLP, adr);
}
+static void dw_axi_dma_set_byte_halfword(struct axi_dma_chan *chan, bool set)
+{
+ u32 reg_width, offset, val;
+
+ if (!chan->chip->apb_regs) {
+ dev_dbg(chan->chip->dev, "apb_regs not initialized\n");
+ return;
+ }
+
+ reg_width = __ffs(chan->config.dst_addr_width);
+ if (reg_width == DWAXIDMAC_TRANS_WIDTH_8)
+ offset = DMAC_APB_BYTE_WR_CH_EN;
+ else if (reg_width == DWAXIDMAC_TRANS_WIDTH_16)
+ offset = DMAC_APB_HALFWORD_WR_CH_EN;
+
+ val = ioread32(chan->chip->apb_regs + offset);
+
+ if (set)
+ val |= BIT(chan->id);
+ else
+ val &= ~BIT(chan->id);
+
+ iowrite32(val, chan->chip->apb_regs + offset);
+}
/* Called in chan locked context */
static void axi_chan_block_xfer_start(struct axi_dma_chan *chan,
struct axi_dma_desc *first)
@@ -334,6 +358,7 @@ static void axi_chan_block_xfer_start(struct axi_dma_chan
*chan,
DWAXIDMAC_HS_SEL_HW << CH_CFG_H_HS_SEL_SRC_POS);
switch (chan->direction) {
case DMA_MEM_TO_DEV:
+ dw_axi_dma_set_byte_halfword(chan, true);
reg |= (chan->config.device_fc ?
DWAXIDMAC_TT_FC_MEM_TO_PER_DST :
DWAXIDMAC_TT_FC_MEM_TO_PER_DMAC)
@@ -1008,6 +1033,8 @@ static int dma_chan_terminate_all(struct dma_chan *dchan)
if (chan->direction != DMA_MEM_TO_MEM)
dw_axi_dma_set_hw_channel(chan->chip,
chan->hw_handshake_num, false);
+ if (chan->direction == DMA_MEM_TO_DEV)
+ dw_axi_dma_set_byte_halfword(chan, false);
spin_lock_irqsave(>vc.lock, flags);
--
2.18.0
[PATCH v9 16/16] dmaengine: dw-axi-dmac: Virtually split the linked-list
AxiDMA driver exposed the dma_set_max_seg_size() to the DMAENGINE.
It shall helps the DMA clients to create size-optimized linked-list
for the controller.
However, there are certain situations where DMA client might not be
abled to benefit from the dma_get_max_seg_size() if the segment size
can't meet the nature of the DMA client's operation.
In the case of ALSA operation, ALSA application and driver expecting
to run in a period of larger than 10ms regardless of the bit depth.
With this large period, there is a strong request to split the linked-list
in the AxiDMA driver.
Signed-off-by: Sia Jee Heng
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c| 111 ++
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 1 +
2 files changed, 92 insertions(+), 20 deletions(-)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 1f9522caf876..dd1af6056d94 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -582,6 +582,11 @@ static int dw_axi_dma_set_hw_desc(struct axi_dma_chan
*chan,
if (mem_width > DWAXIDMAC_TRANS_WIDTH_32)
mem_width = DWAXIDMAC_TRANS_WIDTH_32;
+ if (!IS_ALIGNED(mem_addr, 4)) {
+ dev_err(chan->chip->dev, "invalid buffer alignment\n");
+ return -EINVAL;
+ }
+
switch (chan->direction) {
case DMA_MEM_TO_DEV:
reg_width = __ffs(chan->config.dst_addr_width);
@@ -643,6 +648,35 @@ static int dw_axi_dma_set_hw_desc(struct axi_dma_chan
*chan,
return 0;
}
+static size_t calculate_block_len(struct axi_dma_chan *chan,
+ dma_addr_t dma_addr, size_t buf_len,
+ enum dma_transfer_direction direction)
+{
+ u32 data_width, reg_width, mem_width;
+ size_t axi_block_ts, block_len;
+
+ axi_block_ts = chan->chip->dw->hdata->block_size[chan->id];
+
+ switch (direction) {
+ case DMA_MEM_TO_DEV:
+ data_width = BIT(chan->chip->dw->hdata->m_data_width);
+ mem_width = __ffs(data_width | dma_addr | buf_len);
+ if (mem_width > DWAXIDMAC_TRANS_WIDTH_32)
+ mem_width = DWAXIDMAC_TRANS_WIDTH_32;
+
+ block_len = axi_block_ts << mem_width;
+ break;
+ case DMA_DEV_TO_MEM:
+ reg_width = __ffs(chan->config.src_addr_width);
+ block_len = axi_block_ts << reg_width;
+ break;
+ default:
+ block_len = 0;
+ }
+
+ return block_len;
+}
+
static struct dma_async_tx_descriptor *
dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan, dma_addr_t dma_addr,
size_t buf_len, size_t period_len,
@@ -653,13 +687,27 @@ dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan,
dma_addr_t dma_addr,
struct axi_dma_hw_desc *hw_desc = NULL;
struct axi_dma_desc *desc = NULL;
dma_addr_t src_addr = dma_addr;
- u32 num_periods = buf_len / period_len;
+ u32 num_periods, num_segments;
+ size_t axi_block_len;
+ u32 total_segments;
+ u32 segment_len;
unsigned int i;
int status;
u64 llp = 0;
u8 lms = 0; /* Select AXI0 master for LLI fetching */
- desc = axi_desc_alloc(num_periods);
+ num_periods = buf_len / period_len;
+
+ axi_block_len = calculate_block_len(chan, dma_addr, buf_len, direction);
+ if (axi_block_len == 0)
+ return NULL;
+
+ num_segments = DIV_ROUND_UP(period_len, axi_block_len);
+ segment_len = DIV_ROUND_UP(period_len, num_segments);
+
+ total_segments = num_periods * num_segments;
+
+ desc = axi_desc_alloc(total_segments);
if (unlikely(!desc))
goto err_desc_get;
@@ -667,12 +715,13 @@ dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan,
dma_addr_t dma_addr,
desc->chan = chan;
chan->cyclic = true;
desc->length = 0;
+ desc->period_len = period_len;
- for (i = 0; i < num_periods; i++) {
+ for (i = 0; i < total_segments; i++) {
hw_desc = >hw_desc[i];
status = dw_axi_dma_set_hw_desc(chan, hw_desc, src_addr,
- period_len);
+ segment_len);
if (status < 0)
goto err_desc_get;
@@ -682,17 +731,17 @@ dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan,
dma_addr_t dma_addr,
*/
set_desc_last(hw_desc);
- src_addr += period_len;
+ src_addr += segment_len;
}
llp = desc->hw_desc[0].llp;
/* Managed transfer list */
do {
- hw_desc = >hw_desc[--num_pe
[PATCH v9 15/16] dmaengine: dw-axi-dmac: Set constraint to the Max segment size
Add support for DMA Scatter-Gather (SG) constraint so that DMA clients can
handle the AxiDMA limitation.
Without supporting DMA constraint the default Max segment size reported by
dmaengine is 64KB, which is not supported by Intel KeemBay AxiDMA.
Reviewed-by: Andy Shevchenko
Signed-off-by: Sia Jee Heng
---
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 8
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 1 +
2 files changed, 9 insertions(+)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index ea527b92e0fc..1f9522caf876 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -1341,6 +1342,13 @@ static int dw_probe(struct platform_device *pdev)
dw->dma.device_prep_slave_sg = dw_axi_dma_chan_prep_slave_sg;
dw->dma.device_prep_dma_cyclic = dw_axi_dma_chan_prep_cyclic;
+ /*
+* Synopsis DesignWare AxiDMA datasheet mentioned Maximum
+* supported blocks is 1024. Device register width is 4 bytes.
+* Therefore, set constraint to 1024 * 4.
+*/
+ dw->dma.dev->dma_parms = >dma_parms;
+ dma_set_max_seg_size(>dev, MAX_BLOCK_SIZE);
platform_set_drvdata(pdev, chip);
pm_runtime_enable(chip->dev);
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
index 3a357f7fda02..1e937ea2a96d 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
@@ -54,6 +54,7 @@ struct axi_dma_chan {
struct dw_axi_dma {
struct dma_device dma;
struct dw_axi_dma_hcfg *hdata;
+ struct device_dma_parametersdma_parms;
/* channels */
struct axi_dma_chan *chan;
--
2.18.0
[PATCH v9 13/16] dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA handshake
Add support for Intel KeemBay AxiDMA device handshake programming.
Device handshake number passed in to the AxiDMA shall be written to
the Intel KeemBay AxiDMA hardware handshake registers before DMA
operations are started.
Reviewed-by: Andy Shevchenko
Signed-off-by: Sia Jee Heng
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c| 50 +++
1 file changed, 50 insertions(+)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 062d27c61983..e19369f9365a 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -445,6 +445,48 @@ static void dma_chan_free_chan_resources(struct dma_chan
*dchan)
pm_runtime_put(chan->chip->dev);
}
+static void dw_axi_dma_set_hw_channel(struct axi_dma_chip *chip,
+ u32 handshake_num, bool set)
+{
+ unsigned long start = 0;
+ unsigned long reg_value;
+ unsigned long reg_mask;
+ unsigned long reg_set;
+ unsigned long mask;
+ unsigned long val;
+
+ if (!chip->apb_regs) {
+ dev_dbg(chip->dev, "apb_regs not initialized\n");
+ return;
+ }
+
+ /*
+* An unused DMA channel has a default value of 0x3F.
+* Lock the DMA channel by assign a handshake number to the channel.
+* Unlock the DMA channel by assign 0x3F to the channel.
+*/
+ if (set) {
+ reg_set = UNUSED_CHANNEL;
+ val = handshake_num;
+ } else {
+ reg_set = handshake_num;
+ val = UNUSED_CHANNEL;
+ }
+
+ reg_value = lo_hi_readq(chip->apb_regs + DMAC_APB_HW_HS_SEL_0);
+
+ for_each_set_clump8(start, reg_mask, _value, 64) {
+ if (reg_mask == reg_set) {
+ mask = GENMASK_ULL(start + 7, start);
+ reg_value &= ~mask;
+ reg_value |= rol64(val, start);
+ lo_hi_writeq(reg_value,
+chip->apb_regs + DMAC_APB_HW_HS_SEL_0);
+ break;
+ }
+ }
+}
+
/*
* If DW_axi_dmac sees CHx_CTL.ShadowReg_Or_LLI_Last bit of the fetched LLI
* as 1, it understands that the current block is the final block in the
@@ -626,6 +668,8 @@ dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan,
dma_addr_t dma_addr,
llp = hw_desc->llp;
} while (num_periods);
+ dw_axi_dma_set_hw_channel(chan->chip, chan->hw_handshake_num, true);
+
return vchan_tx_prep(>vc, >vd, flags);
err_desc_get:
@@ -684,6 +728,8 @@ dw_axi_dma_chan_prep_slave_sg(struct dma_chan *dchan,
struct scatterlist *sgl,
llp = hw_desc->llp;
} while (sg_len);
+ dw_axi_dma_set_hw_channel(chan->chip, chan->hw_handshake_num, true);
+
return vchan_tx_prep(>vc, >vd, flags);
err_desc_get:
@@ -959,6 +1005,10 @@ static int dma_chan_terminate_all(struct dma_chan *dchan)
dev_warn(dchan2dev(dchan),
"%s failed to stop\n", axi_chan_name(chan));
+ if (chan->direction != DMA_MEM_TO_MEM)
+ dw_axi_dma_set_hw_channel(chan->chip,
+ chan->hw_handshake_num, false);
+
spin_lock_irqsave(>vc.lock, flags);
vchan_get_all_descriptors(>vc, );
--
2.18.0
[PATCH v9 12/16] dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA support
Add support for Intel KeemBay AxiDMA to the .compatible field.
The AxiDMA Apb region will be accessible if the compatible string
matches the "intel,kmb-axi-dma".
Reviewed-by: Andy Shevchenko
Signed-off-by: Sia Jee Heng
---
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 830d3de76abd..062d27c61983 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -1160,6 +1160,7 @@ static int parse_device_properties(struct axi_dma_chip
*chip)
static int dw_probe(struct platform_device *pdev)
{
+ struct device_node *node = pdev->dev.of_node;
struct axi_dma_chip *chip;
struct resource *mem;
struct dw_axi_dma *dw;
@@ -1192,6 +1193,12 @@ static int dw_probe(struct platform_device *pdev)
if (IS_ERR(chip->regs))
return PTR_ERR(chip->regs);
+ if (of_device_is_compatible(node, "intel,kmb-axi-dma")) {
+ chip->apb_regs = devm_platform_ioremap_resource(pdev, 1);
+ if (IS_ERR(chip->apb_regs))
+ return PTR_ERR(chip->apb_regs);
+ }
+
chip->core_clk = devm_clk_get(chip->dev, "core-clk");
if (IS_ERR(chip->core_clk))
return PTR_ERR(chip->core_clk);
@@ -1336,6 +1343,7 @@ static const struct dev_pm_ops dw_axi_dma_pm_ops = {
static const struct of_device_id dw_dma_of_id_table[] = {
{ .compatible = "snps,axi-dma-1.01a" },
+ { .compatible = "intel,kmb-axi-dma" },
{}
};
MODULE_DEVICE_TABLE(of, dw_dma_of_id_table);
--
2.18.0
[PATCH v9 11/16] dmaengine: dw-axi-dmac: Add Intel KeemBay DMA register fields
Add support for Intel KeemBay DMA registers. These registers are required
to run data transfer between device to memory and memory to device on Intel
KeemBay SoC.
Reviewed-by: Andy Shevchenko
Signed-off-by: Sia Jee Heng
---
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
index 46baf93de617..3a357f7fda02 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
@@ -63,6 +63,7 @@ struct axi_dma_chip {
struct device *dev;
int irq;
void __iomem*regs;
+ void __iomem*apb_regs;
struct clk *core_clk;
struct clk *cfgr_clk;
struct dw_axi_dma *dw;
@@ -169,6 +170,19 @@ static inline struct axi_dma_chan
*dchan_to_axi_dma_chan(struct dma_chan *dchan)
#define CH_INTSIGNAL_ENA 0x090 /* R/W Chan Interrupt Signal Enable */
#define CH_INTCLEAR0x098 /* W Chan Interrupt Clear */
+/* These Apb registers are used by Intel KeemBay SoC */
+#define DMAC_APB_CFG 0x000 /* DMAC Apb Configuration Register */
+#define DMAC_APB_STAT 0x004 /* DMAC Apb Status Register */
+#define DMAC_APB_DEBUG_STAT_0 0x008 /* DMAC Apb Debug Status Register 0 */
+#define DMAC_APB_DEBUG_STAT_1 0x00C /* DMAC Apb Debug Status Register 1 */
+#define DMAC_APB_HW_HS_SEL_0 0x010 /* DMAC Apb HW HS register 0 */
+#define DMAC_APB_HW_HS_SEL_1 0x014 /* DMAC Apb HW HS register 1 */
+#define DMAC_APB_LPI 0x018 /* DMAC Apb Low Power Interface Reg */
+#define DMAC_APB_BYTE_WR_CH_EN 0x01C /* DMAC Apb Byte Write Enable */
+#define DMAC_APB_HALFWORD_WR_CH_EN 0x020 /* DMAC Halfword write enables */
+
+#define UNUSED_CHANNEL 0x3F /* Set unused DMA channel to 0x3F */
+#define MAX_BLOCK_SIZE 0x1000 /* 1024 blocks * 4 bytes data width */
/* DMAC_CFG */
#define DMAC_EN_POS0
--
2.18.0
[PATCH v9 10/16] dt-binding: dma: dw-axi-dmac: Add support for Intel KeemBay AxiDMA
Add support for Intel KeemBay AxiDMA to the dw-axi-dmac Schemas DT binding. Signed-off-by: Sia Jee Heng Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml | 5 + 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml index 3d2515463d56..79e241498e25 100644 --- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml +++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml @@ -8,6 +8,7 @@ title: Synopsys DesignWare AXI DMA Controller maintainers: - Eugeniy Paltsev + - Jee Heng Sia description: Synopsys DesignWare AXI DMA Controller DT Binding @@ -19,14 +20,18 @@ properties: compatible: enum: - snps,axi-dma-1.01a + - intel,kmb-axi-dma reg: +minItems: 1 items: - description: Address range of the DMAC registers + - description: Address range of the DMAC APB registers reg-names: items: - const: axidma_ctrl_regs + - const: axidma_apb_regs interrupts: maxItems: 1 -- 2.18.0
[PATCH v9 08/16] dmaengine: dw-axi-dmac: Support of_dma_controller_register()
Add support for of_dma_controller_register() so that DMA clients
can pass in device handshake number to the AxiDMA driver.
DMA clients shall code the device handshake number in the Device tree.
When DMA activities are needed, DMA clients shall invoke OF helper
function to pass in the device handshake number to the AxiDMA.
Without register to the of_dma_controller_register(), data transfer
between memory to device and device to memory operations would failed.
Reviewed-by: Andy Shevchenko
Signed-off-by: Sia Jee Heng
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c| 26 +++
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 1 +
2 files changed, 27 insertions(+)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index a76299360f69..a8b6c8c8ef58 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -20,6 +20,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -1044,6 +1045,22 @@ static int __maybe_unused axi_dma_runtime_resume(struct
device *dev)
return axi_dma_resume(chip);
}
+static struct dma_chan *dw_axi_dma_of_xlate(struct of_phandle_args *dma_spec,
+ struct of_dma *ofdma)
+{
+ struct dw_axi_dma *dw = ofdma->of_dma_data;
+ struct axi_dma_chan *chan;
+ struct dma_chan *dchan;
+
+ dchan = dma_get_any_slave_channel(>dma);
+ if (!dchan)
+ return NULL;
+
+ chan = dchan_to_axi_dma_chan(dchan);
+ chan->hw_handshake_num = dma_spec->args[0];
+ return dchan;
+}
+
static int parse_device_properties(struct axi_dma_chip *chip)
{
struct device *dev = chip->dev;
@@ -1233,6 +1250,13 @@ static int dw_probe(struct platform_device *pdev)
if (ret)
goto err_pm_disable;
+ /* Register with OF helpers for DMA lookups */
+ ret = of_dma_controller_register(pdev->dev.of_node,
+dw_axi_dma_of_xlate, dw);
+ if (ret < 0)
+ dev_warn(>dev,
+"Failed to register OF DMA controller, fallback to
MEM_TO_MEM mode\n");
+
dev_info(chip->dev, "DesignWare AXI DMA Controller, %d channels\n",
dw->hdata->nr_channels);
@@ -1266,6 +1290,8 @@ static int dw_remove(struct platform_device *pdev)
devm_free_irq(chip->dev, chip->irq, chip);
+ of_dma_controller_free(chip->dev->of_node);
+
list_for_each_entry_safe(chan, _chan, >dma.channels,
vc.chan.device_node) {
list_del(>vc.chan.device_node);
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
index a26b0a242a93..3498bef5453b 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
@@ -37,6 +37,7 @@ struct axi_dma_chan {
struct axi_dma_chip *chip;
void __iomem*chan_regs;
u8 id;
+ u8 hw_handshake_num;
atomic_tdescs_allocated;
struct dma_pool *desc_pool;
--
2.18.0
[PATCH v9 09/16] dmaengine: dw-axi-dmac: Support burst residue granularity
Add support for DMA_RESIDUE_GRANULARITY_BURST so that AxiDMA can report
DMA residue.
Existing AxiDMA driver only support data transfer between
memory to memory operation, therefore reporting DMA residue
to the DMA clients is not supported.
Reporting DMA residue to the DMA clients is important as DMA clients
shall invoke dmaengine_tx_status() to understand the number of bytes
been transferred so that the buffer pointer can be updated accordingly.
Reviewed-by: Andy Shevchenko
Signed-off-by: Sia Jee Heng
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c| 43 ---
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 2 +
2 files changed, 38 insertions(+), 7 deletions(-)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index a8b6c8c8ef58..830d3de76abd 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -265,14 +265,36 @@ dma_chan_tx_status(struct dma_chan *dchan, dma_cookie_t
cookie,
struct dma_tx_state *txstate)
{
struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
- enum dma_status ret;
+ struct virt_dma_desc *vdesc;
+ enum dma_status status;
+ u32 completed_length;
+ unsigned long flags;
+ u32 completed_blocks;
+ size_t bytes = 0;
+ u32 length;
+ u32 len;
- ret = dma_cookie_status(dchan, cookie, txstate);
+ status = dma_cookie_status(dchan, cookie, txstate);
+ if (status == DMA_COMPLETE || !txstate)
+ return status;
- if (chan->is_paused && ret == DMA_IN_PROGRESS)
- ret = DMA_PAUSED;
+ spin_lock_irqsave(>vc.lock, flags);
- return ret;
+ vdesc = vchan_find_desc(>vc, cookie);
+ if (vdesc) {
+ length = vd_to_axi_desc(vdesc)->length;
+ completed_blocks = vd_to_axi_desc(vdesc)->completed_blocks;
+ len = vd_to_axi_desc(vdesc)->hw_desc[0].len;
+ completed_length = completed_blocks * len;
+ bytes = length - completed_length;
+ } else {
+ bytes = vd_to_axi_desc(vdesc)->length;
+ }
+
+ spin_unlock_irqrestore(>vc.lock, flags);
+ dma_set_residue(txstate, bytes);
+
+ return status;
}
static void write_desc_llp(struct axi_dma_hw_desc *desc, dma_addr_t adr)
@@ -549,6 +571,7 @@ static int dw_axi_dma_set_hw_desc(struct axi_dma_chan *chan,
set_desc_src_master(hw_desc);
+ hw_desc->len = len;
return 0;
}
@@ -575,6 +598,7 @@ dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan,
dma_addr_t dma_addr,
chan->direction = direction;
desc->chan = chan;
chan->cyclic = true;
+ desc->length = 0;
for (i = 0; i < num_periods; i++) {
hw_desc = >hw_desc[i];
@@ -584,6 +608,7 @@ dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan,
dma_addr_t dma_addr,
if (status < 0)
goto err_desc_get;
+ desc->length += hw_desc->len;
/* Set end-of-link to the linked descriptor, so that cyclic
* callback function can be triggered during interrupt.
*/
@@ -636,6 +661,7 @@ dw_axi_dma_chan_prep_slave_sg(struct dma_chan *dchan,
struct scatterlist *sgl,
goto err_desc_get;
desc->chan = chan;
+ desc->length = 0;
for_each_sg(sgl, sg, sg_len, i) {
mem = sg_dma_address(sg);
@@ -645,6 +671,7 @@ dw_axi_dma_chan_prep_slave_sg(struct dma_chan *dchan,
struct scatterlist *sgl,
status = dw_axi_dma_set_hw_desc(chan, hw_desc, mem, len);
if (status < 0)
goto err_desc_get;
+ desc->length += hw_desc->len;
}
/* Set end-of-link to the last link descriptor of list */
@@ -690,6 +717,7 @@ dma_chan_prep_dma_memcpy(struct dma_chan *dchan, dma_addr_t
dst_adr,
desc->chan = chan;
num = 0;
+ desc->length = 0;
while (len) {
xfer_len = len;
@@ -742,7 +770,8 @@ dma_chan_prep_dma_memcpy(struct dma_chan *dchan, dma_addr_t
dst_adr,
set_desc_src_master(hw_desc);
set_desc_dest_master(hw_desc, desc);
-
+ hw_desc->len = xfer_len;
+ desc->length += hw_desc->len;
/* update the length and addresses for the next loop cycle */
len -= xfer_len;
dst_adr += xfer_len;
@@ -1210,7 +1239,7 @@ static int dw_probe(struct platform_device *pdev)
dw->dma.dst_addr_widths = AXI_DMA_BUSWIDTHS;
dw->dma.directions = BIT(DMA_MEM_TO_MEM);
dw->dma.directions |= BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM);
- dw->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
+ dw
[PATCH v9 05/16] dmaengine: dw-axi-dmac: Add device_config operation
Add device_config() callback function so that the device address
can be passed to the dma driver.
DMA clients use this interface to pass in the device address to the
AxiDMA. Without this interface, data transfer between device to memory
and memory to device would failed.
Reviewed-by: Andy Shevchenko
Signed-off-by: Sia Jee Heng
---
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 11 +++
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 1 +
2 files changed, 12 insertions(+)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 241ab7a24e2a..eaa7c4c404ca 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -559,6 +559,16 @@ dma_chan_prep_dma_memcpy(struct dma_chan *dchan,
dma_addr_t dst_adr,
return NULL;
}
+static int dw_axi_dma_chan_slave_config(struct dma_chan *dchan,
+ struct dma_slave_config *config)
+{
+ struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
+
+ memcpy(>config, config, sizeof(*config));
+
+ return 0;
+}
+
static void axi_chan_dump_lli(struct axi_dma_chan *chan,
struct axi_dma_hw_desc *desc)
{
@@ -948,6 +958,7 @@ static int dw_probe(struct platform_device *pdev)
dw->dma.device_prep_dma_memcpy = dma_chan_prep_dma_memcpy;
dw->dma.device_synchronize = dw_axi_dma_synchronize;
+ dw->dma.device_config = dw_axi_dma_chan_slave_config;
platform_set_drvdata(pdev, chip);
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
index f886b2bb75de..a75b921d6b1a 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
@@ -43,6 +43,7 @@ struct axi_dma_chan {
struct virt_dma_chanvc;
struct axi_dma_desc *desc;
+ struct dma_slave_config config;
/* these other elements are all protected by vc.lock */
boolis_paused;
};
--
2.18.0
[PATCH v9 04/16] dmaengine: dw-axi-dmac: Add device_synchronize() callback
Add support for device_synchronize() callback function to sync with
dmaengine_terminate_sync().
Reviewed-by: Andy Shevchenko
Signed-off-by: Sia Jee Heng
---
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 3737e1c3c793..241ab7a24e2a 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -347,6 +347,13 @@ static void dma_chan_issue_pending(struct dma_chan *dchan)
spin_unlock_irqrestore(>vc.lock, flags);
}
+static void dw_axi_dma_synchronize(struct dma_chan *dchan)
+{
+ struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
+
+ vchan_synchronize(>vc);
+}
+
static int dma_chan_alloc_chan_resources(struct dma_chan *dchan)
{
struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
@@ -940,6 +947,7 @@ static int dw_probe(struct platform_device *pdev)
dw->dma.device_free_chan_resources = dma_chan_free_chan_resources;
dw->dma.device_prep_dma_memcpy = dma_chan_prep_dma_memcpy;
+ dw->dma.device_synchronize = dw_axi_dma_synchronize;
platform_set_drvdata(pdev, chip);
--
2.18.0
[PATCH v9 03/16] dmaengine: dw-axi-dmac: move dma_pool_create() to alloc_chan_resources()
The DMA memory block is created at driver load time and exist for
device lifetime. Move the dma_pool_create() to the ->chan_resource()
callback function allowing the DMA memory blocks to be created as needed
and destroyed when the channel is freed.
Reviewed-by: Andy Shevchenko
Signed-off-by: Sia Jee Heng
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c| 24 ++-
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 2 +-
2 files changed, 14 insertions(+), 12 deletions(-)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 350968baaf88..3737e1c3c793 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -216,11 +216,10 @@ static struct axi_dma_desc *axi_desc_alloc(u32 num)
static struct axi_dma_lli *axi_desc_get(struct axi_dma_chan *chan,
dma_addr_t *addr)
{
- struct dw_axi_dma *dw = chan->chip->dw;
struct axi_dma_lli *lli;
dma_addr_t phys;
- lli = dma_pool_zalloc(dw->desc_pool, GFP_NOWAIT, );
+ lli = dma_pool_zalloc(chan->desc_pool, GFP_NOWAIT, );
if (unlikely(!lli)) {
dev_err(chan2dev(chan), "%s: not enough descriptors
available\n",
axi_chan_name(chan));
@@ -236,14 +235,13 @@ static struct axi_dma_lli *axi_desc_get(struct
axi_dma_chan *chan,
static void axi_desc_put(struct axi_dma_desc *desc)
{
struct axi_dma_chan *chan = desc->chan;
- struct dw_axi_dma *dw = chan->chip->dw;
int count = atomic_read(>descs_allocated);
struct axi_dma_hw_desc *hw_desc;
int descs_put;
for (descs_put = 0; descs_put < count; descs_put++) {
hw_desc = >hw_desc[descs_put];
- dma_pool_free(dw->desc_pool, hw_desc->lli, hw_desc->llp);
+ dma_pool_free(chan->desc_pool, hw_desc->lli, hw_desc->llp);
}
kfree(desc->hw_desc);
@@ -360,6 +358,15 @@ static int dma_chan_alloc_chan_resources(struct dma_chan
*dchan)
return -EBUSY;
}
+ /* LLI address must be aligned to a 64-byte boundary */
+ chan->desc_pool = dma_pool_create(dev_name(chan2dev(chan)),
+ chan->chip->dev,
+ sizeof(struct axi_dma_lli),
+ 64, 0);
+ if (!chan->desc_pool) {
+ dev_err(chan2dev(chan), "No memory for descriptors\n");
+ return -ENOMEM;
+ }
dev_vdbg(dchan2dev(dchan), "%s: allocating\n", axi_chan_name(chan));
pm_runtime_get(chan->chip->dev);
@@ -381,6 +388,8 @@ static void dma_chan_free_chan_resources(struct dma_chan
*dchan)
vchan_free_chan_resources(>vc);
+ dma_pool_destroy(chan->desc_pool);
+ chan->desc_pool = NULL;
dev_vdbg(dchan2dev(dchan),
"%s: free resources, descriptor still allocated: %u\n",
axi_chan_name(chan), atomic_read(>descs_allocated));
@@ -896,13 +905,6 @@ static int dw_probe(struct platform_device *pdev)
if (ret)
return ret;
- /* Lli address must be aligned to a 64-byte boundary */
- dw->desc_pool = dmam_pool_create(KBUILD_MODNAME, chip->dev,
-sizeof(struct axi_dma_lli), 64, 0);
- if (!dw->desc_pool) {
- dev_err(chip->dev, "No memory for descriptors dma pool\n");
- return -ENOMEM;
- }
INIT_LIST_HEAD(>dma.channels);
for (i = 0; i < hdata->nr_channels; i++) {
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
index 41e775e6e593..f886b2bb75de 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
@@ -39,6 +39,7 @@ struct axi_dma_chan {
u8 id;
atomic_tdescs_allocated;
+ struct dma_pool *desc_pool;
struct virt_dma_chanvc;
struct axi_dma_desc *desc;
@@ -49,7 +50,6 @@ struct axi_dma_chan {
struct dw_axi_dma {
struct dma_device dma;
struct dw_axi_dma_hcfg *hdata;
- struct dma_pool *desc_pool;
/* channels */
struct axi_dma_chan *chan;
--
2.18.0
[PATCH v9 00/16] dmaengine: dw-axi-dmac: support Intel KeemBay AxiDMA
The below patch series are to support AxiDMA running on Intel KeemBay SoC. The base driver is dw-axi-dmac. This driver only support DMA memory copy transfers. Code refactoring is needed so that additional features can be supported. The features added in this patch series are: - Replacing Linked List with virtual descriptor management. - Remove unrelated hw desc stuff from dma memory pool. - Manage dma memory pool alloc/destroy based on channel activity. - Support dmaengine device_sync() callback. - Support dmaengine device_config(). - Support dmaengine device_prep_slave_sg(). - Support dmaengine device_prep_dma_cyclic(). - Support of_dma_controller_register(). - Support burst residue granularity. - Support Intel KeemBay AxiDMA registers. - Support Intel KeemBay AxiDMA device handshake. - Support Intel KeemBay AxiDMA BYTE and HALFWORD device operation. - Add constraint to Max segment size. - Virtually split the linked-list. This patch series are tested on Intel KeemBay platform. v9: - Logic checked on apb_regs inside the function. - Improved code scalability so that missing of apb_regs wouldn't failed the common callback functions. v8: - Rebased to kernel v5.11-rc1. - Added reviewed-by tag from Rob. v7: - Added 'allOf' and '$ref:dma-controller.yaml#' in DT binding. - Removed the dma-channels common description in DT binding. - Removed the default fields in DT binding. v6: - Removed 'allOf' cases in DT binding. - Added '>' at the end of the email address. - Removed additional '|' at the start of description. - Fixed space indent. - Added proper constraint in DT binding. - Removed second example in DT binding. v5: - Added comment to the Apb registers used by Intel KeemBay Soc. - Renamed "hs_num" to "handshake_num". - Conditional check for the compatible property and return error instead of printing warning. - Added patch 16th to virtually split the linked-list as per request from ALSA team. v4: - Fixed bot found errors running make_dt_binding_check. - Added minItems: 1 to the YAML schemas DT binding. - Updated "reg" field to the YAML schemas DT binding. v3: - Added additionalProperties: false to the YAML schemas DT binding. - Reordered patch sequence for patch 10th, 11th and 12th so that DT binding come first, follow by adding Intel KeemBay SoC registers and update .compatible field. - Checked txstate NULL condition. - Created helper function dw_axi_dma_set_hw_desc() to handle common code. v2: - Rebased to v5.10-rc1 kernel. - Added support for dmaengine device_config(). - Added support for dmaengine device_prep_slave_sg(). - Added support for dmaengine device_prep_dma_cyclic(). - Added support for of_dma_controller_register(). - Added support for burst residue granularity. - Added support for Intel KeemBay AxiDMA registers. - Added support for Intel KeemBay AxiDMA device handshake. - Added support for Intel KeemBay AxiDMA BYTE and HALFWORD device operation. - Added constraint to Max segment size. v1: - Initial version. Patch on top of dw-axi-dma driver. This version improve the descriptor management by replacing Linked List Item (LLI) with virtual descriptor management, only allocate hardware LLI memories from DMA memory pool, manage DMA memory pool alloc/destroy based on channel activity and to support device_sync callback. Sia Jee Heng (16): dt-bindings: dma: Add YAML schemas for dw-axi-dmac dmaengine: dw-axi-dmac: simplify descriptor management dmaengine: dw-axi-dmac: move dma_pool_create() to alloc_chan_resources() dmaengine: dw-axi-dmac: Add device_synchronize() callback dmaengine: dw-axi-dmac: Add device_config operation dmaengine: dw-axi-dmac: Support device_prep_slave_sg dmaegine: dw-axi-dmac: Support device_prep_dma_cyclic() dmaengine: dw-axi-dmac: Support of_dma_controller_register() dmaengine: dw-axi-dmac: Support burst residue granularity dt-binding: dma: dw-axi-dmac: Add support for Intel KeemBay AxiDMA dmaengine: dw-axi-dmac: Add Intel KeemBay DMA register fields dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA support dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA handshake dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA BYTE and HALFWORD registers dmaengine: dw-axi-dmac: Set constraint to the Max segment size dmaengine: dw-axi-dmac: Virtually split the linked-list .../bindings/dma/snps,dw-axi-dmac.txt | 39 - .../bindings/dma/snps,dw-axi-dmac.yaml| 126 .../dma/dw-axi-dmac/dw-axi-dmac-platform.c| 697 +++--- drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 34 +- 4 files changed, 764 insertions(+), 132 deletions(-) delete mode 100644 Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt create mode 100644 Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml base-commit: e71ba9452f0b5b2e8dc8aa5445198cd9214a6a62 -- 2.18.0
RE: [PATCH v8 13/16] dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA handshake
> -Original Message- > From: Eugeniy Paltsev > Sent: 31 December 2020 8:44 PM > To: Sia, Jee Heng ; Vinod Koul > > Cc: andriy.shevche...@linux.intel.com; dmaeng...@vger.kernel.org; > linux-kernel@vger.kernel.org; devicet...@vger.kernel.org; > robh...@kernel.org > Subject: Re: [PATCH v8 13/16] dmaengine: dw-axi-dmac: Add Intel > KeemBay AxiDMA handshake > > Hi Sia Jee Heng, > > see my comments inlined: > > > From: Sia Jee Heng > > Sent: Tuesday, December 29, 2020 07:47 > > To: vk...@kernel.org; Eugeniy Paltsev; robh...@kernel.org > > Cc: andriy.shevche...@linux.intel.com; > dmaeng...@vger.kernel.org; > > linux-kernel@vger.kernel.org; devicet...@vger.kernel.org > > Subject: [PATCH v8 13/16] dmaengine: dw-axi-dmac: Add Intel > KeemBay > > AxiDMA handshake > > > > Add support for Intel KeemBay AxiDMA device handshake > programming. > > Device handshake number passed in to the AxiDMA shall be written > to > > the Intel KeemBay AxiDMA hardware handshake registers before > DMA > > operations are started. > > > > Reviewed-by: Andy Shevchenko > > > Signed-off-by: Sia Jee Heng > > --- > > .../dma/dw-axi-dmac/dw-axi-dmac-platform.c| 52 > +++ > > 1 file changed, 52 insertions(+) > > > > diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c > > b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c > > index 062d27c61983..5e77eb3d040f 100644 > > --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c > > +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c > [snip] > > + > > + return 0; > > +} > > + > > /* > > * If DW_axi_dmac sees CHx_CTL.ShadowReg_Or_LLI_Last bit of > the fetched LLI > > * as 1, it understands that the current block is the final block in > > the @@ -626,6 +668,9 @@ dw_axi_dma_chan_prep_cyclic(struct > dma_chan *dchan, dma_addr_t dma_addr, > > llp = hw_desc->llp; > > } while (num_periods); > > > > + if (dw_axi_dma_set_hw_channel(chan->chip, chan- > >hw_handshake_num, true)) > > + goto err_desc_get; > > + > > In this implementation 'dw_axi_dma_chan_prep_cyclic' callback will > fail if we don't have APB registers which are only specific for KeemBay. > Looking for the code of 'dw_axi_dma_chan_prep_cyclic' I don't see > the reason why it shouldn't work for vanila DW AXI DMAC without this > extension. So, could you please change this so we wouldn't reject > dw_axi_dma_chan_prep_cyclic in case of APB registers are missed. [>>] OK, I can change the code in such a way that dw_axi_dma_set_hw_channel() will be executed only if apb_reg is valid. > > > return vchan_tx_prep(>vc, >vd, flags); > > > > err_desc_get: > > @@ -684,6 +729,9 @@ dw_axi_dma_chan_prep_slave_sg(struct > dma_chan *dchan, struct scatterlist *sgl, > > llp = hw_desc->llp; > > } while (sg_len); > > > > + if (dw_axi_dma_set_hw_channel(chan->chip, chan- > >hw_handshake_num, true)) > > + goto err_desc_get; > > + > > Same here. [>>] Sure, same method described above will be used. > > > > return vchan_tx_prep(>vc, >vd, flags); > > > > err_desc_get: > > @@ -959,6 +1007,10 @@ static int dma_chan_terminate_all(struct > dma_chan *dchan) > > dev_warn(dchan2dev(dchan), > > "%s failed to stop\n", axi_chan_name(chan)); > > > > + if (chan->direction != DMA_MEM_TO_MEM) > > + dw_axi_dma_set_hw_channel(chan->chip, > > + chan->hw_handshake_num, > > + false); > > + > > spin_lock_irqsave(>vc.lock, flags); > > > > vchan_get_all_descriptors(>vc, ); > > -- > > 2.18.0 > >
[PATCH v8 13/16] dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA handshake
Add support for Intel KeemBay AxiDMA device handshake programming.
Device handshake number passed in to the AxiDMA shall be written to
the Intel KeemBay AxiDMA hardware handshake registers before DMA
operations are started.
Reviewed-by: Andy Shevchenko
Signed-off-by: Sia Jee Heng
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c| 52 +++
1 file changed, 52 insertions(+)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 062d27c61983..5e77eb3d040f 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -445,6 +445,48 @@ static void dma_chan_free_chan_resources(struct dma_chan
*dchan)
pm_runtime_put(chan->chip->dev);
}
+static int dw_axi_dma_set_hw_channel(struct axi_dma_chip *chip,
+u32 handshake_num, bool set)
+{
+ unsigned long start = 0;
+ unsigned long reg_value;
+ unsigned long reg_mask;
+ unsigned long reg_set;
+ unsigned long mask;
+ unsigned long val;
+
+ if (!chip->apb_regs)
+ return -ENODEV;
+
+ /*
+* An unused DMA channel has a default value of 0x3F.
+* Lock the DMA channel by assign a handshake number to the channel.
+* Unlock the DMA channel by assign 0x3F to the channel.
+*/
+ if (set) {
+ reg_set = UNUSED_CHANNEL;
+ val = handshake_num;
+ } else {
+ reg_set = handshake_num;
+ val = UNUSED_CHANNEL;
+ }
+
+ reg_value = lo_hi_readq(chip->apb_regs + DMAC_APB_HW_HS_SEL_0);
+
+ for_each_set_clump8(start, reg_mask, _value, 64) {
+ if (reg_mask == reg_set) {
+ mask = GENMASK_ULL(start + 7, start);
+ reg_value &= ~mask;
+ reg_value |= rol64(val, start);
+ lo_hi_writeq(reg_value,
+chip->apb_regs + DMAC_APB_HW_HS_SEL_0);
+ break;
+ }
+ }
+
+ return 0;
+}
+
/*
* If DW_axi_dmac sees CHx_CTL.ShadowReg_Or_LLI_Last bit of the fetched LLI
* as 1, it understands that the current block is the final block in the
@@ -626,6 +668,9 @@ dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan,
dma_addr_t dma_addr,
llp = hw_desc->llp;
} while (num_periods);
+ if (dw_axi_dma_set_hw_channel(chan->chip, chan->hw_handshake_num, true))
+ goto err_desc_get;
+
return vchan_tx_prep(>vc, >vd, flags);
err_desc_get:
@@ -684,6 +729,9 @@ dw_axi_dma_chan_prep_slave_sg(struct dma_chan *dchan,
struct scatterlist *sgl,
llp = hw_desc->llp;
} while (sg_len);
+ if (dw_axi_dma_set_hw_channel(chan->chip, chan->hw_handshake_num, true))
+ goto err_desc_get;
+
return vchan_tx_prep(>vc, >vd, flags);
err_desc_get:
@@ -959,6 +1007,10 @@ static int dma_chan_terminate_all(struct dma_chan *dchan)
dev_warn(dchan2dev(dchan),
"%s failed to stop\n", axi_chan_name(chan));
+ if (chan->direction != DMA_MEM_TO_MEM)
+ dw_axi_dma_set_hw_channel(chan->chip,
+ chan->hw_handshake_num, false);
+
spin_lock_irqsave(>vc.lock, flags);
vchan_get_all_descriptors(>vc, );
--
2.18.0
[PATCH v8 15/16] dmaengine: dw-axi-dmac: Set constraint to the Max segment size
Add support for DMA Scatter-Gather (SG) constraint so that DMA clients can
handle the AxiDMA limitation.
Without supporting DMA constraint the default Max segment size reported by
dmaengine is 64KB, which is not supported by Intel KeemBay AxiDMA.
Reviewed-by: Andy Shevchenko
Signed-off-by: Sia Jee Heng
---
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 8
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 1 +
2 files changed, 9 insertions(+)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index ab145a84b0c0..58845b058d9d 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -1350,6 +1351,13 @@ static int dw_probe(struct platform_device *pdev)
dw->dma.device_prep_slave_sg = dw_axi_dma_chan_prep_slave_sg;
dw->dma.device_prep_dma_cyclic = dw_axi_dma_chan_prep_cyclic;
+ /*
+* Synopsis DesignWare AxiDMA datasheet mentioned Maximum
+* supported blocks is 1024. Device register width is 4 bytes.
+* Therefore, set constraint to 1024 * 4.
+*/
+ dw->dma.dev->dma_parms = >dma_parms;
+ dma_set_max_seg_size(>dev, MAX_BLOCK_SIZE);
platform_set_drvdata(pdev, chip);
pm_runtime_enable(chip->dev);
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
index 3a357f7fda02..1e937ea2a96d 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
@@ -54,6 +54,7 @@ struct axi_dma_chan {
struct dw_axi_dma {
struct dma_device dma;
struct dw_axi_dma_hcfg *hdata;
+ struct device_dma_parametersdma_parms;
/* channels */
struct axi_dma_chan *chan;
--
2.18.0
[PATCH v8 16/16] dmaengine: dw-axi-dmac: Virtually split the linked-list
AxiDMA driver exposed the dma_set_max_seg_size() to the DMAENGINE.
It shall helps the DMA clients to create size-optimized linked-list
for the controller.
However, there are certain situations where DMA client might not be
abled to benefit from the dma_get_max_seg_size() if the segment size
can't meet the nature of the DMA client's operation.
In the case of ALSA operation, ALSA application and driver expecting
to run in a period of larger than 10ms regardless of the bit depth.
With this large period, there is a strong request to split the linked-list
in the AxiDMA driver.
Signed-off-by: Sia Jee Heng
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c| 111 ++
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 1 +
2 files changed, 92 insertions(+), 20 deletions(-)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 58845b058d9d..c17b96245f13 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -576,6 +576,11 @@ static int dw_axi_dma_set_hw_desc(struct axi_dma_chan
*chan,
if (mem_width > DWAXIDMAC_TRANS_WIDTH_32)
mem_width = DWAXIDMAC_TRANS_WIDTH_32;
+ if (!IS_ALIGNED(mem_addr, 4)) {
+ dev_err(chan->chip->dev, "invalid buffer alignment\n");
+ return -EINVAL;
+ }
+
switch (chan->direction) {
case DMA_MEM_TO_DEV:
reg_width = __ffs(chan->config.dst_addr_width);
@@ -637,6 +642,35 @@ static int dw_axi_dma_set_hw_desc(struct axi_dma_chan
*chan,
return 0;
}
+static size_t calculate_block_len(struct axi_dma_chan *chan,
+ dma_addr_t dma_addr, size_t buf_len,
+ enum dma_transfer_direction direction)
+{
+ u32 data_width, reg_width, mem_width;
+ size_t axi_block_ts, block_len;
+
+ axi_block_ts = chan->chip->dw->hdata->block_size[chan->id];
+
+ switch (direction) {
+ case DMA_MEM_TO_DEV:
+ data_width = BIT(chan->chip->dw->hdata->m_data_width);
+ mem_width = __ffs(data_width | dma_addr | buf_len);
+ if (mem_width > DWAXIDMAC_TRANS_WIDTH_32)
+ mem_width = DWAXIDMAC_TRANS_WIDTH_32;
+
+ block_len = axi_block_ts << mem_width;
+ break;
+ case DMA_DEV_TO_MEM:
+ reg_width = __ffs(chan->config.src_addr_width);
+ block_len = axi_block_ts << reg_width;
+ break;
+ default:
+ block_len = 0;
+ }
+
+ return block_len;
+}
+
static struct dma_async_tx_descriptor *
dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan, dma_addr_t dma_addr,
size_t buf_len, size_t period_len,
@@ -647,13 +681,27 @@ dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan,
dma_addr_t dma_addr,
struct axi_dma_hw_desc *hw_desc = NULL;
struct axi_dma_desc *desc = NULL;
dma_addr_t src_addr = dma_addr;
- u32 num_periods = buf_len / period_len;
+ u32 num_periods, num_segments;
+ size_t axi_block_len;
+ u32 total_segments;
+ u32 segment_len;
unsigned int i;
int status;
u64 llp = 0;
u8 lms = 0; /* Select AXI0 master for LLI fetching */
- desc = axi_desc_alloc(num_periods);
+ num_periods = buf_len / period_len;
+
+ axi_block_len = calculate_block_len(chan, dma_addr, buf_len, direction);
+ if (axi_block_len == 0)
+ return NULL;
+
+ num_segments = DIV_ROUND_UP(period_len, axi_block_len);
+ segment_len = DIV_ROUND_UP(period_len, num_segments);
+
+ total_segments = num_periods * num_segments;
+
+ desc = axi_desc_alloc(total_segments);
if (unlikely(!desc))
goto err_desc_get;
@@ -661,12 +709,13 @@ dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan,
dma_addr_t dma_addr,
desc->chan = chan;
chan->cyclic = true;
desc->length = 0;
+ desc->period_len = period_len;
- for (i = 0; i < num_periods; i++) {
+ for (i = 0; i < total_segments; i++) {
hw_desc = >hw_desc[i];
status = dw_axi_dma_set_hw_desc(chan, hw_desc, src_addr,
- period_len);
+ segment_len);
if (status < 0)
goto err_desc_get;
@@ -676,17 +725,17 @@ dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan,
dma_addr_t dma_addr,
*/
set_desc_last(hw_desc);
- src_addr += period_len;
+ src_addr += segment_len;
}
llp = desc->hw_desc[0].llp;
/* Managed transfer list */
do {
- hw_desc = >hw_desc[--num_pe
[PATCH v8 12/16] dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA support
Add support for Intel KeemBay AxiDMA to the .compatible field.
The AxiDMA Apb region will be accessible if the compatible string
matches the "intel,kmb-axi-dma".
Reviewed-by: Andy Shevchenko
Signed-off-by: Sia Jee Heng
---
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 830d3de76abd..062d27c61983 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -1160,6 +1160,7 @@ static int parse_device_properties(struct axi_dma_chip
*chip)
static int dw_probe(struct platform_device *pdev)
{
+ struct device_node *node = pdev->dev.of_node;
struct axi_dma_chip *chip;
struct resource *mem;
struct dw_axi_dma *dw;
@@ -1192,6 +1193,12 @@ static int dw_probe(struct platform_device *pdev)
if (IS_ERR(chip->regs))
return PTR_ERR(chip->regs);
+ if (of_device_is_compatible(node, "intel,kmb-axi-dma")) {
+ chip->apb_regs = devm_platform_ioremap_resource(pdev, 1);
+ if (IS_ERR(chip->apb_regs))
+ return PTR_ERR(chip->apb_regs);
+ }
+
chip->core_clk = devm_clk_get(chip->dev, "core-clk");
if (IS_ERR(chip->core_clk))
return PTR_ERR(chip->core_clk);
@@ -1336,6 +1343,7 @@ static const struct dev_pm_ops dw_axi_dma_pm_ops = {
static const struct of_device_id dw_dma_of_id_table[] = {
{ .compatible = "snps,axi-dma-1.01a" },
+ { .compatible = "intel,kmb-axi-dma" },
{}
};
MODULE_DEVICE_TABLE(of, dw_dma_of_id_table);
--
2.18.0
[PATCH v8 14/16] dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA BYTE and HALFWORD registers
Add support for Intel KeemBay AxiDMA BYTE and HALFWORD registers
programming.
Intel KeemBay AxiDMA supports data transfer between device to memory
and memory to device operations.
This code is needed by I2C, I3C, I2S, SPI and UART which uses FIFO
size of 8bits and 16bits to perform memory to device data transfer
operation. 0-padding functionality is provided to avoid
pre-processing of data on CPU.
Reviewed-by: Andy Shevchenko
Signed-off-by: Sia Jee Heng
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c| 44 ---
1 file changed, 39 insertions(+), 5 deletions(-)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 5e77eb3d040f..ab145a84b0c0 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -312,7 +312,7 @@ static void axi_chan_block_xfer_start(struct axi_dma_chan
*chan,
struct axi_dma_desc *first)
{
u32 priority = chan->chip->dw->hdata->priority[chan->id];
- u32 reg, irq_mask;
+ u32 reg, irq_mask, reg_width, offset, val;
u8 lms = 0; /* Select AXI0 master for LLI fetching */
if (unlikely(axi_chan_is_hw_enable(chan))) {
@@ -334,6 +334,25 @@ static void axi_chan_block_xfer_start(struct axi_dma_chan
*chan,
DWAXIDMAC_HS_SEL_HW << CH_CFG_H_HS_SEL_SRC_POS);
switch (chan->direction) {
case DMA_MEM_TO_DEV:
+ if (chan->chip->apb_regs) {
+ reg_width = __ffs(chan->config.dst_addr_width);
+ /*
+* Configure Byte and Halfword register
+* for MEM_TO_DEV only.
+*/
+ if (reg_width == DWAXIDMAC_TRANS_WIDTH_16) {
+ offset = DMAC_APB_HALFWORD_WR_CH_EN;
+ val = ioread32(chan->chip->apb_regs + offset);
+ val |= BIT(chan->id);
+ iowrite32(val, chan->chip->apb_regs + offset);
+ } else if (reg_width == DWAXIDMAC_TRANS_WIDTH_8) {
+ offset = DMAC_APB_BYTE_WR_CH_EN;
+ val = ioread32(chan->chip->apb_regs + offset);
+ val |= BIT(chan->id);
+ iowrite32(val, chan->chip->apb_regs + offset);
+ }
+ }
+
reg |= (chan->config.device_fc ?
DWAXIDMAC_TT_FC_MEM_TO_PER_DST :
DWAXIDMAC_TT_FC_MEM_TO_PER_DMAC)
@@ -994,8 +1013,9 @@ static int dma_chan_terminate_all(struct dma_chan *dchan)
{
struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
u32 chan_active = BIT(chan->id) << DMAC_CHAN_EN_SHIFT;
+ u32 reg_width = __ffs(chan->config.dst_addr_width);
unsigned long flags;
- u32 val;
+ u32 offset, val;
int ret;
LIST_HEAD(head);
@@ -1007,9 +1027,23 @@ static int dma_chan_terminate_all(struct dma_chan *dchan)
dev_warn(dchan2dev(dchan),
"%s failed to stop\n", axi_chan_name(chan));
- if (chan->direction != DMA_MEM_TO_MEM)
- dw_axi_dma_set_hw_channel(chan->chip,
- chan->hw_handshake_num, false);
+ if (chan->direction != DMA_MEM_TO_MEM) {
+ ret = dw_axi_dma_set_hw_channel(chan->chip,
+ chan->hw_handshake_num, false);
+ if (ret == 0 && chan->direction == DMA_MEM_TO_DEV) {
+ if (reg_width == DWAXIDMAC_TRANS_WIDTH_8) {
+ offset = DMAC_APB_BYTE_WR_CH_EN;
+ val = ioread32(chan->chip->apb_regs + offset);
+ val &= ~BIT(chan->id);
+ iowrite32(val, chan->chip->apb_regs + offset);
+ } else if (reg_width == DWAXIDMAC_TRANS_WIDTH_16) {
+ offset = DMAC_APB_HALFWORD_WR_CH_EN;
+ val = ioread32(chan->chip->apb_regs + offset);
+ val &= ~BIT(chan->id);
+ iowrite32(val, chan->chip->apb_regs + offset);
+ }
+ }
+ }
spin_lock_irqsave(>vc.lock, flags);
--
2.18.0
[PATCH v8 11/16] dmaengine: dw-axi-dmac: Add Intel KeemBay DMA register fields
Add support for Intel KeemBay DMA registers. These registers are required
to run data transfer between device to memory and memory to device on Intel
KeemBay SoC.
Reviewed-by: Andy Shevchenko
Signed-off-by: Sia Jee Heng
---
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
index 46baf93de617..3a357f7fda02 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
@@ -63,6 +63,7 @@ struct axi_dma_chip {
struct device *dev;
int irq;
void __iomem*regs;
+ void __iomem*apb_regs;
struct clk *core_clk;
struct clk *cfgr_clk;
struct dw_axi_dma *dw;
@@ -169,6 +170,19 @@ static inline struct axi_dma_chan
*dchan_to_axi_dma_chan(struct dma_chan *dchan)
#define CH_INTSIGNAL_ENA 0x090 /* R/W Chan Interrupt Signal Enable */
#define CH_INTCLEAR0x098 /* W Chan Interrupt Clear */
+/* These Apb registers are used by Intel KeemBay SoC */
+#define DMAC_APB_CFG 0x000 /* DMAC Apb Configuration Register */
+#define DMAC_APB_STAT 0x004 /* DMAC Apb Status Register */
+#define DMAC_APB_DEBUG_STAT_0 0x008 /* DMAC Apb Debug Status Register 0 */
+#define DMAC_APB_DEBUG_STAT_1 0x00C /* DMAC Apb Debug Status Register 1 */
+#define DMAC_APB_HW_HS_SEL_0 0x010 /* DMAC Apb HW HS register 0 */
+#define DMAC_APB_HW_HS_SEL_1 0x014 /* DMAC Apb HW HS register 1 */
+#define DMAC_APB_LPI 0x018 /* DMAC Apb Low Power Interface Reg */
+#define DMAC_APB_BYTE_WR_CH_EN 0x01C /* DMAC Apb Byte Write Enable */
+#define DMAC_APB_HALFWORD_WR_CH_EN 0x020 /* DMAC Halfword write enables */
+
+#define UNUSED_CHANNEL 0x3F /* Set unused DMA channel to 0x3F */
+#define MAX_BLOCK_SIZE 0x1000 /* 1024 blocks * 4 bytes data width */
/* DMAC_CFG */
#define DMAC_EN_POS0
--
2.18.0
[PATCH v8 10/16] dt-binding: dma: dw-axi-dmac: Add support for Intel KeemBay AxiDMA
Add support for Intel KeemBay AxiDMA to the dw-axi-dmac Schemas DT binding. Signed-off-by: Sia Jee Heng Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml | 5 + 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml index 3d2515463d56..79e241498e25 100644 --- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml +++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml @@ -8,6 +8,7 @@ title: Synopsys DesignWare AXI DMA Controller maintainers: - Eugeniy Paltsev + - Jee Heng Sia description: Synopsys DesignWare AXI DMA Controller DT Binding @@ -19,14 +20,18 @@ properties: compatible: enum: - snps,axi-dma-1.01a + - intel,kmb-axi-dma reg: +minItems: 1 items: - description: Address range of the DMAC registers + - description: Address range of the DMAC APB registers reg-names: items: - const: axidma_ctrl_regs + - const: axidma_apb_regs interrupts: maxItems: 1 -- 2.18.0
[PATCH v8 08/16] dmaengine: dw-axi-dmac: Support of_dma_controller_register()
Add support for of_dma_controller_register() so that DMA clients
can pass in device handshake number to the AxiDMA driver.
DMA clients shall code the device handshake number in the Device tree.
When DMA activities are needed, DMA clients shall invoke OF helper
function to pass in the device handshake number to the AxiDMA.
Without register to the of_dma_controller_register(), data transfer
between memory to device and device to memory operations would failed.
Reviewed-by: Andy Shevchenko
Signed-off-by: Sia Jee Heng
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c| 26 +++
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 1 +
2 files changed, 27 insertions(+)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index a76299360f69..a8b6c8c8ef58 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -20,6 +20,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -1044,6 +1045,22 @@ static int __maybe_unused axi_dma_runtime_resume(struct
device *dev)
return axi_dma_resume(chip);
}
+static struct dma_chan *dw_axi_dma_of_xlate(struct of_phandle_args *dma_spec,
+ struct of_dma *ofdma)
+{
+ struct dw_axi_dma *dw = ofdma->of_dma_data;
+ struct axi_dma_chan *chan;
+ struct dma_chan *dchan;
+
+ dchan = dma_get_any_slave_channel(>dma);
+ if (!dchan)
+ return NULL;
+
+ chan = dchan_to_axi_dma_chan(dchan);
+ chan->hw_handshake_num = dma_spec->args[0];
+ return dchan;
+}
+
static int parse_device_properties(struct axi_dma_chip *chip)
{
struct device *dev = chip->dev;
@@ -1233,6 +1250,13 @@ static int dw_probe(struct platform_device *pdev)
if (ret)
goto err_pm_disable;
+ /* Register with OF helpers for DMA lookups */
+ ret = of_dma_controller_register(pdev->dev.of_node,
+dw_axi_dma_of_xlate, dw);
+ if (ret < 0)
+ dev_warn(>dev,
+"Failed to register OF DMA controller, fallback to
MEM_TO_MEM mode\n");
+
dev_info(chip->dev, "DesignWare AXI DMA Controller, %d channels\n",
dw->hdata->nr_channels);
@@ -1266,6 +1290,8 @@ static int dw_remove(struct platform_device *pdev)
devm_free_irq(chip->dev, chip->irq, chip);
+ of_dma_controller_free(chip->dev->of_node);
+
list_for_each_entry_safe(chan, _chan, >dma.channels,
vc.chan.device_node) {
list_del(>vc.chan.device_node);
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
index a26b0a242a93..3498bef5453b 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
@@ -37,6 +37,7 @@ struct axi_dma_chan {
struct axi_dma_chip *chip;
void __iomem*chan_regs;
u8 id;
+ u8 hw_handshake_num;
atomic_tdescs_allocated;
struct dma_pool *desc_pool;
--
2.18.0
[PATCH v8 09/16] dmaengine: dw-axi-dmac: Support burst residue granularity
Add support for DMA_RESIDUE_GRANULARITY_BURST so that AxiDMA can report
DMA residue.
Existing AxiDMA driver only support data transfer between
memory to memory operation, therefore reporting DMA residue
to the DMA clients is not supported.
Reporting DMA residue to the DMA clients is important as DMA clients
shall invoke dmaengine_tx_status() to understand the number of bytes
been transferred so that the buffer pointer can be updated accordingly.
Reviewed-by: Andy Shevchenko
Signed-off-by: Sia Jee Heng
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c| 43 ---
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 2 +
2 files changed, 38 insertions(+), 7 deletions(-)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index a8b6c8c8ef58..830d3de76abd 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -265,14 +265,36 @@ dma_chan_tx_status(struct dma_chan *dchan, dma_cookie_t
cookie,
struct dma_tx_state *txstate)
{
struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
- enum dma_status ret;
+ struct virt_dma_desc *vdesc;
+ enum dma_status status;
+ u32 completed_length;
+ unsigned long flags;
+ u32 completed_blocks;
+ size_t bytes = 0;
+ u32 length;
+ u32 len;
- ret = dma_cookie_status(dchan, cookie, txstate);
+ status = dma_cookie_status(dchan, cookie, txstate);
+ if (status == DMA_COMPLETE || !txstate)
+ return status;
- if (chan->is_paused && ret == DMA_IN_PROGRESS)
- ret = DMA_PAUSED;
+ spin_lock_irqsave(>vc.lock, flags);
- return ret;
+ vdesc = vchan_find_desc(>vc, cookie);
+ if (vdesc) {
+ length = vd_to_axi_desc(vdesc)->length;
+ completed_blocks = vd_to_axi_desc(vdesc)->completed_blocks;
+ len = vd_to_axi_desc(vdesc)->hw_desc[0].len;
+ completed_length = completed_blocks * len;
+ bytes = length - completed_length;
+ } else {
+ bytes = vd_to_axi_desc(vdesc)->length;
+ }
+
+ spin_unlock_irqrestore(>vc.lock, flags);
+ dma_set_residue(txstate, bytes);
+
+ return status;
}
static void write_desc_llp(struct axi_dma_hw_desc *desc, dma_addr_t adr)
@@ -549,6 +571,7 @@ static int dw_axi_dma_set_hw_desc(struct axi_dma_chan *chan,
set_desc_src_master(hw_desc);
+ hw_desc->len = len;
return 0;
}
@@ -575,6 +598,7 @@ dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan,
dma_addr_t dma_addr,
chan->direction = direction;
desc->chan = chan;
chan->cyclic = true;
+ desc->length = 0;
for (i = 0; i < num_periods; i++) {
hw_desc = >hw_desc[i];
@@ -584,6 +608,7 @@ dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan,
dma_addr_t dma_addr,
if (status < 0)
goto err_desc_get;
+ desc->length += hw_desc->len;
/* Set end-of-link to the linked descriptor, so that cyclic
* callback function can be triggered during interrupt.
*/
@@ -636,6 +661,7 @@ dw_axi_dma_chan_prep_slave_sg(struct dma_chan *dchan,
struct scatterlist *sgl,
goto err_desc_get;
desc->chan = chan;
+ desc->length = 0;
for_each_sg(sgl, sg, sg_len, i) {
mem = sg_dma_address(sg);
@@ -645,6 +671,7 @@ dw_axi_dma_chan_prep_slave_sg(struct dma_chan *dchan,
struct scatterlist *sgl,
status = dw_axi_dma_set_hw_desc(chan, hw_desc, mem, len);
if (status < 0)
goto err_desc_get;
+ desc->length += hw_desc->len;
}
/* Set end-of-link to the last link descriptor of list */
@@ -690,6 +717,7 @@ dma_chan_prep_dma_memcpy(struct dma_chan *dchan, dma_addr_t
dst_adr,
desc->chan = chan;
num = 0;
+ desc->length = 0;
while (len) {
xfer_len = len;
@@ -742,7 +770,8 @@ dma_chan_prep_dma_memcpy(struct dma_chan *dchan, dma_addr_t
dst_adr,
set_desc_src_master(hw_desc);
set_desc_dest_master(hw_desc, desc);
-
+ hw_desc->len = xfer_len;
+ desc->length += hw_desc->len;
/* update the length and addresses for the next loop cycle */
len -= xfer_len;
dst_adr += xfer_len;
@@ -1210,7 +1239,7 @@ static int dw_probe(struct platform_device *pdev)
dw->dma.dst_addr_widths = AXI_DMA_BUSWIDTHS;
dw->dma.directions = BIT(DMA_MEM_TO_MEM);
dw->dma.directions |= BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM);
- dw->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
+ dw
[PATCH v8 07/16] dmaegine: dw-axi-dmac: Support device_prep_dma_cyclic()
Add support for device_prep_dma_cyclic() callback function to benefit
DMA cyclic client, for example ALSA.
Existing AxiDMA driver only support data transfer between memory to memory.
Data transfer between device to memory and memory to device in cyclic mode
would failed if this interface is not supported by the AxiDMA driver.
Reviewed-by: Andy Shevchenko
Signed-off-by: Sia Jee Heng
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c| 111 --
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 2 +
2 files changed, 106 insertions(+), 7 deletions(-)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 7ff30b0f44ed..a76299360f69 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -15,6 +15,8 @@
#include
#include
#include
+#include
+#include
#include
#include
#include
@@ -549,6 +551,64 @@ static int dw_axi_dma_set_hw_desc(struct axi_dma_chan
*chan,
return 0;
}
+static struct dma_async_tx_descriptor *
+dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan, dma_addr_t dma_addr,
+ size_t buf_len, size_t period_len,
+ enum dma_transfer_direction direction,
+ unsigned long flags)
+{
+ struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
+ struct axi_dma_hw_desc *hw_desc = NULL;
+ struct axi_dma_desc *desc = NULL;
+ dma_addr_t src_addr = dma_addr;
+ u32 num_periods = buf_len / period_len;
+ unsigned int i;
+ int status;
+ u64 llp = 0;
+ u8 lms = 0; /* Select AXI0 master for LLI fetching */
+
+ desc = axi_desc_alloc(num_periods);
+ if (unlikely(!desc))
+ goto err_desc_get;
+
+ chan->direction = direction;
+ desc->chan = chan;
+ chan->cyclic = true;
+
+ for (i = 0; i < num_periods; i++) {
+ hw_desc = >hw_desc[i];
+
+ status = dw_axi_dma_set_hw_desc(chan, hw_desc, src_addr,
+ period_len);
+ if (status < 0)
+ goto err_desc_get;
+
+ /* Set end-of-link to the linked descriptor, so that cyclic
+* callback function can be triggered during interrupt.
+*/
+ set_desc_last(hw_desc);
+
+ src_addr += period_len;
+ }
+
+ llp = desc->hw_desc[0].llp;
+
+ /* Managed transfer list */
+ do {
+ hw_desc = >hw_desc[--num_periods];
+ write_desc_llp(hw_desc, llp | lms);
+ llp = hw_desc->llp;
+ } while (num_periods);
+
+ return vchan_tx_prep(>vc, >vd, flags);
+
+err_desc_get:
+ if (desc)
+ axi_desc_put(desc);
+
+ return NULL;
+}
+
static struct dma_async_tx_descriptor *
dw_axi_dma_chan_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl,
unsigned int sg_len,
@@ -773,8 +833,13 @@ static noinline void axi_chan_handle_err(struct
axi_dma_chan *chan, u32 status)
static void axi_chan_block_xfer_complete(struct axi_dma_chan *chan)
{
+ int count = atomic_read(>descs_allocated);
+ struct axi_dma_hw_desc *hw_desc;
+ struct axi_dma_desc *desc;
struct virt_dma_desc *vd;
unsigned long flags;
+ u64 llp;
+ int i;
spin_lock_irqsave(>vc.lock, flags);
if (unlikely(axi_chan_is_hw_enable(chan))) {
@@ -785,12 +850,32 @@ static void axi_chan_block_xfer_complete(struct
axi_dma_chan *chan)
/* The completed descriptor currently is in the head of vc list */
vd = vchan_next_desc(>vc);
- /* Remove the completed descriptor from issued list before completing */
- list_del(>node);
- vchan_cookie_complete(vd);
- /* Submit queued descriptors after processing the completed ones */
- axi_chan_start_first_queued(chan);
+ if (chan->cyclic) {
+ vchan_cyclic_callback(vd);
+ desc = vd_to_axi_desc(vd);
+ if (desc) {
+ llp = lo_hi_readq(chan->chan_regs + CH_LLP);
+ for (i = 0; i < count; i++) {
+ hw_desc = >hw_desc[i];
+ if (hw_desc->llp == llp) {
+ axi_chan_irq_clear(chan,
hw_desc->lli->status_lo);
+ hw_desc->lli->ctl_hi |=
CH_CTL_H_LLI_VALID;
+ desc->completed_blocks = i;
+ break;
+ }
+ }
+
+ axi_chan_enable(chan);
+ }
+ } else {
+ /* Remove the completed descriptor from issued list before
completing *
[PATCH v8 06/16] dmaengine: dw-axi-dmac: Support device_prep_slave_sg
Add device_prep_slave_sg() callback function so that DMA_MEM_TO_DEV
and DMA_DEV_TO_MEM operations in single mode can be supported.
Existing AxiDMA driver only support data transfer between
memory to memory. Data transfer between device to memory and
memory to device in single mode would failed if this interface
is not supported by the AxiDMA driver.
Reviewed-by: Andy Shevchenko
Signed-off-by: Sia Jee Heng
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c| 154 ++
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 1 +
2 files changed, 155 insertions(+)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index eaa7c4c404ca..7ff30b0f44ed 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -307,6 +307,22 @@ static void axi_chan_block_xfer_start(struct axi_dma_chan
*chan,
priority << CH_CFG_H_PRIORITY_POS |
DWAXIDMAC_HS_SEL_HW << CH_CFG_H_HS_SEL_DST_POS |
DWAXIDMAC_HS_SEL_HW << CH_CFG_H_HS_SEL_SRC_POS);
+ switch (chan->direction) {
+ case DMA_MEM_TO_DEV:
+ reg |= (chan->config.device_fc ?
+ DWAXIDMAC_TT_FC_MEM_TO_PER_DST :
+ DWAXIDMAC_TT_FC_MEM_TO_PER_DMAC)
+ << CH_CFG_H_TT_FC_POS;
+ break;
+ case DMA_DEV_TO_MEM:
+ reg |= (chan->config.device_fc ?
+ DWAXIDMAC_TT_FC_PER_TO_MEM_SRC :
+ DWAXIDMAC_TT_FC_PER_TO_MEM_DMAC)
+ << CH_CFG_H_TT_FC_POS;
+ break;
+ default:
+ break;
+ }
axi_chan_iowrite32(chan, CH_CFG_H, reg);
write_chan_llp(chan, first->hw_desc[0].llp | lms);
@@ -454,6 +470,141 @@ static void set_desc_dest_master(struct axi_dma_hw_desc
*hw_desc,
hw_desc->lli->ctl_lo = cpu_to_le32(val);
}
+static int dw_axi_dma_set_hw_desc(struct axi_dma_chan *chan,
+ struct axi_dma_hw_desc *hw_desc,
+ dma_addr_t mem_addr, size_t len)
+{
+ unsigned int data_width = BIT(chan->chip->dw->hdata->m_data_width);
+ unsigned int reg_width;
+ unsigned int mem_width;
+ dma_addr_t device_addr;
+ size_t axi_block_ts;
+ size_t block_ts;
+ u32 ctllo, ctlhi;
+ u32 burst_len;
+
+ axi_block_ts = chan->chip->dw->hdata->block_size[chan->id];
+
+ mem_width = __ffs(data_width | mem_addr | len);
+ if (mem_width > DWAXIDMAC_TRANS_WIDTH_32)
+ mem_width = DWAXIDMAC_TRANS_WIDTH_32;
+
+ switch (chan->direction) {
+ case DMA_MEM_TO_DEV:
+ reg_width = __ffs(chan->config.dst_addr_width);
+ device_addr = chan->config.dst_addr;
+ ctllo = reg_width << CH_CTL_L_DST_WIDTH_POS |
+ mem_width << CH_CTL_L_SRC_WIDTH_POS |
+ DWAXIDMAC_CH_CTL_L_NOINC << CH_CTL_L_DST_INC_POS |
+ DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_SRC_INC_POS;
+ block_ts = len >> mem_width;
+ break;
+ case DMA_DEV_TO_MEM:
+ reg_width = __ffs(chan->config.src_addr_width);
+ device_addr = chan->config.src_addr;
+ ctllo = reg_width << CH_CTL_L_SRC_WIDTH_POS |
+ mem_width << CH_CTL_L_DST_WIDTH_POS |
+ DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_DST_INC_POS |
+ DWAXIDMAC_CH_CTL_L_NOINC << CH_CTL_L_SRC_INC_POS;
+ block_ts = len >> reg_width;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (block_ts > axi_block_ts)
+ return -EINVAL;
+
+ hw_desc->lli = axi_desc_get(chan, _desc->llp);
+ if (unlikely(!hw_desc->lli))
+ return -ENOMEM;
+
+ ctlhi = CH_CTL_H_LLI_VALID;
+
+ if (chan->chip->dw->hdata->restrict_axi_burst_len) {
+ burst_len = chan->chip->dw->hdata->axi_rw_burst_len;
+ ctlhi |= CH_CTL_H_ARLEN_EN | CH_CTL_H_AWLEN_EN |
+burst_len << CH_CTL_H_ARLEN_POS |
+burst_len << CH_CTL_H_AWLEN_POS;
+ }
+
+ hw_desc->lli->ctl_hi = cpu_to_le32(ctlhi);
+
+ if (chan->direction == DMA_MEM_TO_DEV) {
+ write_desc_sar(hw_desc, mem_addr);
+ write_desc_dar(hw_desc, device_addr);
+ } else {
+ write_desc_sar(hw_desc, device_addr);
+ write_desc_dar(hw_desc, mem_addr);
+ }
+
+ hw_desc->lli->block_ts_lo = cpu_to_le32(block_ts - 1);
+
+ ctllo |= DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CT
[PATCH v8 05/16] dmaengine: dw-axi-dmac: Add device_config operation
Add device_config() callback function so that the device address
can be passed to the dma driver.
DMA clients use this interface to pass in the device address to the
AxiDMA. Without this interface, data transfer between device to memory
and memory to device would failed.
Reviewed-by: Andy Shevchenko
Signed-off-by: Sia Jee Heng
---
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 11 +++
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 1 +
2 files changed, 12 insertions(+)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 241ab7a24e2a..eaa7c4c404ca 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -559,6 +559,16 @@ dma_chan_prep_dma_memcpy(struct dma_chan *dchan,
dma_addr_t dst_adr,
return NULL;
}
+static int dw_axi_dma_chan_slave_config(struct dma_chan *dchan,
+ struct dma_slave_config *config)
+{
+ struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
+
+ memcpy(>config, config, sizeof(*config));
+
+ return 0;
+}
+
static void axi_chan_dump_lli(struct axi_dma_chan *chan,
struct axi_dma_hw_desc *desc)
{
@@ -948,6 +958,7 @@ static int dw_probe(struct platform_device *pdev)
dw->dma.device_prep_dma_memcpy = dma_chan_prep_dma_memcpy;
dw->dma.device_synchronize = dw_axi_dma_synchronize;
+ dw->dma.device_config = dw_axi_dma_chan_slave_config;
platform_set_drvdata(pdev, chip);
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
index f886b2bb75de..a75b921d6b1a 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
@@ -43,6 +43,7 @@ struct axi_dma_chan {
struct virt_dma_chanvc;
struct axi_dma_desc *desc;
+ struct dma_slave_config config;
/* these other elements are all protected by vc.lock */
boolis_paused;
};
--
2.18.0
[PATCH v8 03/16] dmaengine: dw-axi-dmac: move dma_pool_create() to alloc_chan_resources()
The DMA memory block is created at driver load time and exist for
device lifetime. Move the dma_pool_create() to the ->chan_resource()
callback function allowing the DMA memory blocks to be created as needed
and destroyed when the channel is freed.
Reviewed-by: Andy Shevchenko
Signed-off-by: Sia Jee Heng
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c| 24 ++-
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 2 +-
2 files changed, 14 insertions(+), 12 deletions(-)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 350968baaf88..3737e1c3c793 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -216,11 +216,10 @@ static struct axi_dma_desc *axi_desc_alloc(u32 num)
static struct axi_dma_lli *axi_desc_get(struct axi_dma_chan *chan,
dma_addr_t *addr)
{
- struct dw_axi_dma *dw = chan->chip->dw;
struct axi_dma_lli *lli;
dma_addr_t phys;
- lli = dma_pool_zalloc(dw->desc_pool, GFP_NOWAIT, );
+ lli = dma_pool_zalloc(chan->desc_pool, GFP_NOWAIT, );
if (unlikely(!lli)) {
dev_err(chan2dev(chan), "%s: not enough descriptors
available\n",
axi_chan_name(chan));
@@ -236,14 +235,13 @@ static struct axi_dma_lli *axi_desc_get(struct
axi_dma_chan *chan,
static void axi_desc_put(struct axi_dma_desc *desc)
{
struct axi_dma_chan *chan = desc->chan;
- struct dw_axi_dma *dw = chan->chip->dw;
int count = atomic_read(>descs_allocated);
struct axi_dma_hw_desc *hw_desc;
int descs_put;
for (descs_put = 0; descs_put < count; descs_put++) {
hw_desc = >hw_desc[descs_put];
- dma_pool_free(dw->desc_pool, hw_desc->lli, hw_desc->llp);
+ dma_pool_free(chan->desc_pool, hw_desc->lli, hw_desc->llp);
}
kfree(desc->hw_desc);
@@ -360,6 +358,15 @@ static int dma_chan_alloc_chan_resources(struct dma_chan
*dchan)
return -EBUSY;
}
+ /* LLI address must be aligned to a 64-byte boundary */
+ chan->desc_pool = dma_pool_create(dev_name(chan2dev(chan)),
+ chan->chip->dev,
+ sizeof(struct axi_dma_lli),
+ 64, 0);
+ if (!chan->desc_pool) {
+ dev_err(chan2dev(chan), "No memory for descriptors\n");
+ return -ENOMEM;
+ }
dev_vdbg(dchan2dev(dchan), "%s: allocating\n", axi_chan_name(chan));
pm_runtime_get(chan->chip->dev);
@@ -381,6 +388,8 @@ static void dma_chan_free_chan_resources(struct dma_chan
*dchan)
vchan_free_chan_resources(>vc);
+ dma_pool_destroy(chan->desc_pool);
+ chan->desc_pool = NULL;
dev_vdbg(dchan2dev(dchan),
"%s: free resources, descriptor still allocated: %u\n",
axi_chan_name(chan), atomic_read(>descs_allocated));
@@ -896,13 +905,6 @@ static int dw_probe(struct platform_device *pdev)
if (ret)
return ret;
- /* Lli address must be aligned to a 64-byte boundary */
- dw->desc_pool = dmam_pool_create(KBUILD_MODNAME, chip->dev,
-sizeof(struct axi_dma_lli), 64, 0);
- if (!dw->desc_pool) {
- dev_err(chip->dev, "No memory for descriptors dma pool\n");
- return -ENOMEM;
- }
INIT_LIST_HEAD(>dma.channels);
for (i = 0; i < hdata->nr_channels; i++) {
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
index 41e775e6e593..f886b2bb75de 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
@@ -39,6 +39,7 @@ struct axi_dma_chan {
u8 id;
atomic_tdescs_allocated;
+ struct dma_pool *desc_pool;
struct virt_dma_chanvc;
struct axi_dma_desc *desc;
@@ -49,7 +50,6 @@ struct axi_dma_chan {
struct dw_axi_dma {
struct dma_device dma;
struct dw_axi_dma_hcfg *hdata;
- struct dma_pool *desc_pool;
/* channels */
struct axi_dma_chan *chan;
--
2.18.0
[PATCH v8 01/16] dt-bindings: dma: Add YAML schemas for dw-axi-dmac
YAML schemas Device Tree (DT) binding is the new format for DT to replace
the old format. Introduce YAML schemas DT binding for dw-axi-dmac and
remove the old version.
Signed-off-by: Sia Jee Heng
Reviewed-by: Rob Herring
---
.../bindings/dma/snps,dw-axi-dmac.txt | 39 --
.../bindings/dma/snps,dw-axi-dmac.yaml| 121 ++
2 files changed, 121 insertions(+), 39 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt
create mode 100644 Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt
b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt
deleted file mode 100644
index dbe160400adc..
--- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt
+++ /dev/null
@@ -1,39 +0,0 @@
-Synopsys DesignWare AXI DMA Controller
-
-Required properties:
-- compatible: "snps,axi-dma-1.01a"
-- reg: Address range of the DMAC registers. This should include
- all of the per-channel registers.
-- interrupt: Should contain the DMAC interrupt number.
-- dma-channels: Number of channels supported by hardware.
-- snps,dma-masters: Number of AXI masters supported by the hardware.
-- snps,data-width: Maximum AXI data width supported by hardware.
- (0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits)
-- snps,priority: Priority of channel. Array size is equal to the number of
- dma-channels. Priority value must be programmed within [0:dma-channels-1]
- range. (0 - minimum priority)
-- snps,block-size: Maximum block size supported by the controller channel.
- Array size is equal to the number of dma-channels.
-
-Optional properties:
-- snps,axi-max-burst-len: Restrict master AXI burst length by value specified
- in this property. If this property is missing the maximum AXI burst length
- supported by DMAC is used. [1:256]
-
-Example:
-
-dmac: dma-controller@8 {
- compatible = "snps,axi-dma-1.01a";
- reg = <0x8 0x400>;
- clocks = <_clk>, <_clk>;
- clock-names = "core-clk", "cfgr-clk";
- interrupt-parent = <>;
- interrupts = <27>;
-
- dma-channels = <4>;
- snps,dma-masters = <2>;
- snps,data-width = <3>;
- snps,block-size = <4096 4096 4096 4096>;
- snps,priority = <0 1 2 3>;
- snps,axi-max-burst-len = <16>;
-};
diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
new file mode 100644
index ..3d2515463d56
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
@@ -0,0 +1,121 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/snps,dw-axi-dmac.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Synopsys DesignWare AXI DMA Controller
+
+maintainers:
+ - Eugeniy Paltsev
+
+description:
+ Synopsys DesignWare AXI DMA Controller DT Binding
+
+allOf:
+ - $ref: "dma-controller.yaml#"
+
+properties:
+ compatible:
+enum:
+ - snps,axi-dma-1.01a
+
+ reg:
+items:
+ - description: Address range of the DMAC registers
+
+ reg-names:
+items:
+ - const: axidma_ctrl_regs
+
+ interrupts:
+maxItems: 1
+
+ clocks:
+items:
+ - description: Bus Clock
+ - description: Module Clock
+
+ clock-names:
+items:
+ - const: core-clk
+ - const: cfgr-clk
+
+ '#dma-cells':
+const: 1
+
+ dma-channels:
+minimum: 1
+maximum: 8
+
+ snps,dma-masters:
+description: |
+ Number of AXI masters supported by the hardware.
+$ref: /schemas/types.yaml#/definitions/uint32
+enum: [1, 2]
+
+ snps,data-width:
+description: |
+ AXI data width supported by hardware.
+ (0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits)
+$ref: /schemas/types.yaml#/definitions/uint32
+enum: [0, 1, 2, 3, 4, 5, 6]
+
+ snps,priority:
+description: |
+ Channel priority specifier associated with the DMA channels.
+$ref: /schemas/types.yaml#/definitions/uint32-array
+minItems: 1
+maxItems: 8
+
+ snps,block-size:
+description: |
+ Channel block size specifier associated with the DMA channels.
+$ref: /schemas/types.yaml#/definitions/uint32-array
+minItems: 1
+maxItems: 8
+
+ snps,axi-max-burst-len:
+description: |
+ Restrict master AXI burst length by value specified in this property.
+ If this property is missing the maximum AXI burst length supported by
+ DMAC is used.
+$ref: /schemas/types.yaml#/definitions/uint32
+minimum: 1
+maximum: 256
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - interrupts
+ - '#dma-cells'
+ - dma-channels
+ - snps,dma-masters
+ - snps,data-width
+ - snps,priority
+ - snps,block-size
+
+ad
[PATCH v8 04/16] dmaengine: dw-axi-dmac: Add device_synchronize() callback
Add support for device_synchronize() callback function to sync with
dmaengine_terminate_sync().
Reviewed-by: Andy Shevchenko
Signed-off-by: Sia Jee Heng
---
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 3737e1c3c793..241ab7a24e2a 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -347,6 +347,13 @@ static void dma_chan_issue_pending(struct dma_chan *dchan)
spin_unlock_irqrestore(>vc.lock, flags);
}
+static void dw_axi_dma_synchronize(struct dma_chan *dchan)
+{
+ struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
+
+ vchan_synchronize(>vc);
+}
+
static int dma_chan_alloc_chan_resources(struct dma_chan *dchan)
{
struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
@@ -940,6 +947,7 @@ static int dw_probe(struct platform_device *pdev)
dw->dma.device_free_chan_resources = dma_chan_free_chan_resources;
dw->dma.device_prep_dma_memcpy = dma_chan_prep_dma_memcpy;
+ dw->dma.device_synchronize = dw_axi_dma_synchronize;
platform_set_drvdata(pdev, chip);
--
2.18.0
[PATCH v8 02/16] dmaengine: dw-axi-dmac: simplify descriptor management
Simplify and refactor the descriptor management by removing the redundant
Linked List Item (LLI) queue control logic from the AxiDMA driver.
The descriptor is split into virtual descriptor and hardware LLI so that
only hardware LLI memories are allocated from the DMA memory pool.
Up to 64 descriptors can be allocated within a PAGE_SIZE compare to 16
descriptors in previous version. This solves the problem where an
ALSA driver expects more than 16 DMA descriptors to run.
Reviewed-by: Andy Shevchenko
Signed-off-by: Sia Jee Heng
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c| 164 ++
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 9 +-
2 files changed, 102 insertions(+), 71 deletions(-)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index e164f3295f5d..350968baaf88 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -21,6 +21,7 @@
#include
#include
#include
+#include
#include
#include "dw-axi-dmac.h"
@@ -195,43 +196,58 @@ static inline const char *axi_chan_name(struct
axi_dma_chan *chan)
return dma_chan_name(>vc.chan);
}
-static struct axi_dma_desc *axi_desc_get(struct axi_dma_chan *chan)
+static struct axi_dma_desc *axi_desc_alloc(u32 num)
{
- struct dw_axi_dma *dw = chan->chip->dw;
struct axi_dma_desc *desc;
+
+ desc = kzalloc(sizeof(*desc), GFP_NOWAIT);
+ if (!desc)
+ return NULL;
+
+ desc->hw_desc = kcalloc(num, sizeof(*desc->hw_desc), GFP_NOWAIT);
+ if (!desc->hw_desc) {
+ kfree(desc);
+ return NULL;
+ }
+
+ return desc;
+}
+
+static struct axi_dma_lli *axi_desc_get(struct axi_dma_chan *chan,
+ dma_addr_t *addr)
+{
+ struct dw_axi_dma *dw = chan->chip->dw;
+ struct axi_dma_lli *lli;
dma_addr_t phys;
- desc = dma_pool_zalloc(dw->desc_pool, GFP_NOWAIT, );
- if (unlikely(!desc)) {
+ lli = dma_pool_zalloc(dw->desc_pool, GFP_NOWAIT, );
+ if (unlikely(!lli)) {
dev_err(chan2dev(chan), "%s: not enough descriptors
available\n",
axi_chan_name(chan));
return NULL;
}
atomic_inc(>descs_allocated);
- INIT_LIST_HEAD(>xfer_list);
- desc->vd.tx.phys = phys;
- desc->chan = chan;
+ *addr = phys;
- return desc;
+ return lli;
}
static void axi_desc_put(struct axi_dma_desc *desc)
{
struct axi_dma_chan *chan = desc->chan;
struct dw_axi_dma *dw = chan->chip->dw;
- struct axi_dma_desc *child, *_next;
- unsigned int descs_put = 0;
+ int count = atomic_read(>descs_allocated);
+ struct axi_dma_hw_desc *hw_desc;
+ int descs_put;
- list_for_each_entry_safe(child, _next, >xfer_list, xfer_list) {
- list_del(>xfer_list);
- dma_pool_free(dw->desc_pool, child, child->vd.tx.phys);
- descs_put++;
+ for (descs_put = 0; descs_put < count; descs_put++) {
+ hw_desc = >hw_desc[descs_put];
+ dma_pool_free(dw->desc_pool, hw_desc->lli, hw_desc->llp);
}
- dma_pool_free(dw->desc_pool, desc, desc->vd.tx.phys);
- descs_put++;
-
+ kfree(desc->hw_desc);
+ kfree(desc);
atomic_sub(descs_put, >descs_allocated);
dev_vdbg(chan2dev(chan), "%s: %d descs put, %d still allocated\n",
axi_chan_name(chan), descs_put,
@@ -258,9 +274,9 @@ dma_chan_tx_status(struct dma_chan *dchan, dma_cookie_t
cookie,
return ret;
}
-static void write_desc_llp(struct axi_dma_desc *desc, dma_addr_t adr)
+static void write_desc_llp(struct axi_dma_hw_desc *desc, dma_addr_t adr)
{
- desc->lli.llp = cpu_to_le64(adr);
+ desc->lli->llp = cpu_to_le64(adr);
}
static void write_chan_llp(struct axi_dma_chan *chan, dma_addr_t adr)
@@ -295,7 +311,7 @@ static void axi_chan_block_xfer_start(struct axi_dma_chan
*chan,
DWAXIDMAC_HS_SEL_HW << CH_CFG_H_HS_SEL_SRC_POS);
axi_chan_iowrite32(chan, CH_CFG_H, reg);
- write_chan_llp(chan, first->vd.tx.phys | lms);
+ write_chan_llp(chan, first->hw_desc[0].llp | lms);
irq_mask = DWAXIDMAC_IRQ_DMA_TRF | DWAXIDMAC_IRQ_ALL_ERR;
axi_chan_irq_sig_set(chan, irq_mask);
@@ -378,67 +394,78 @@ static void dma_chan_free_chan_resources(struct dma_chan
*dchan)
* transfer and completes the DMA transfer operation at the end of current
* block transfer.
*/
-static void set_desc_last(struct axi_dma_desc *desc)
+static void set_desc_last(struct axi_dma_hw_desc *desc)
{
u32 val;
- val = le32_to_cpu(desc->lli.ctl_hi);
+ val = le32_to_cpu(desc->lli-&g
[PATCH v8 00/16] dmaengine: dw-axi-dmac: support Intel KeemBay AxiDMA
The below patch series are to support AxiDMA running on Intel KeemBay SoC. The base driver is dw-axi-dmac. This driver only support DMA memory copy transfers. Code refactoring is needed so that additional features can be supported. The features added in this patch series are: - Replacing Linked List with virtual descriptor management. - Remove unrelated hw desc stuff from dma memory pool. - Manage dma memory pool alloc/destroy based on channel activity. - Support dmaengine device_sync() callback. - Support dmaengine device_config(). - Support dmaengine device_prep_slave_sg(). - Support dmaengine device_prep_dma_cyclic(). - Support of_dma_controller_register(). - Support burst residue granularity. - Support Intel KeemBay AxiDMA registers. - Support Intel KeemBay AxiDMA device handshake. - Support Intel KeemBay AxiDMA BYTE and HALFWORD device operation. - Add constraint to Max segment size. - Virtually split the linked-list. This patch series are tested on Intel KeemBay platform. v8: - Rebased to kernel v5.11-rc1. - Added reviewed-by tag from Rob. v7: - Added 'allOf' and '$ref:dma-controller.yaml#' in DT binding. - Removed the dma-channels common description in DT binding. - Removed the default fields in DT binding. v6: - Removed 'allOf' cases in DT binding. - Added '>' at the end of the email address. - Removed additional '|' at the start of description. - Fixed space indent. - Added proper constraint in DT binding. - Removed second example in DT binding. v5: - Added comment to the Apb registers used by Intel KeemBay Soc. - Renamed "hs_num" to "handshake_num". - Conditional check for the compatible property and return error instead of printing warning. - Added patch 16th to virtually split the linked-list as per request from ALSA team. v4: - Fixed bot found errors running make_dt_binding_check. - Added minItems: 1 to the YAML schemas DT binding. - Updated "reg" field to the YAML schemas DT binding. v3: - Added additionalProperties: false to the YAML schemas DT binding. - Reordered patch sequence for patch 10th, 11th and 12th so that DT binding come first, follow by adding Intel KeemBay SoC registers and update .compatible field. - Checked txstate NULL condition. - Created helper function dw_axi_dma_set_hw_desc() to handle common code. v2: - Rebased to v5.10-rc1 kernel. - Added support for dmaengine device_config(). - Added support for dmaengine device_prep_slave_sg(). - Added support for dmaengine device_prep_dma_cyclic(). - Added support for of_dma_controller_register(). - Added support for burst residue granularity. - Added support for Intel KeemBay AxiDMA registers. - Added support for Intel KeemBay AxiDMA device handshake. - Added support for Intel KeemBay AxiDMA BYTE and HALFWORD device operation. - Added constraint to Max segment size. v1: - Initial version. Patch on top of dw-axi-dma driver. This version improve the descriptor management by replacing Linked List Item (LLI) with virtual descriptor management, only allocate hardware LLI memories from DMA memory pool, manage DMA memory pool alloc/destroy based on channel activity and to support device_sync callback. Sia Jee Heng (16): dt-bindings: dma: Add YAML schemas for dw-axi-dmac dmaengine: dw-axi-dmac: simplify descriptor management dmaengine: dw-axi-dmac: move dma_pool_create() to alloc_chan_resources() dmaengine: dw-axi-dmac: Add device_synchronize() callback dmaengine: dw-axi-dmac: Add device_config operation dmaengine: dw-axi-dmac: Support device_prep_slave_sg dmaegine: dw-axi-dmac: Support device_prep_dma_cyclic() dmaengine: dw-axi-dmac: Support of_dma_controller_register() dmaengine: dw-axi-dmac: Support burst residue granularity dt-binding: dma: dw-axi-dmac: Add support for Intel KeemBay AxiDMA dmaengine: dw-axi-dmac: Add Intel KeemBay DMA register fields dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA support dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA handshake dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA BYTE and HALFWORD registers dmaengine: dw-axi-dmac: Set constraint to the Max segment size dmaengine: dw-axi-dmac: Virtually split the linked-list .../bindings/dma/snps,dw-axi-dmac.txt | 39 - .../bindings/dma/snps,dw-axi-dmac.yaml| 126 .../dma/dw-axi-dmac/dw-axi-dmac-platform.c| 710 +++--- drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 34 +- 4 files changed, 775 insertions(+), 134 deletions(-) delete mode 100644 Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt create mode 100644 Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml base-commit: dea8dcf2a9fa8cc540136a6cd885c3beece16ec3 -- 2.18.0
[PATCH v7 16/16] dmaengine: dw-axi-dmac: Virtually split the linked-list
AxiDMA driver exposed the dma_set_max_seg_size() to the DMAENGINE.
It shall helps the DMA clients to create size-optimized linked-list
for the controller.
However, there are certain situations where DMA client might not be
abled to benefit from the dma_get_max_seg_size() if the segment size
can't meet the nature of the DMA client's operation.
In the case of ALSA operation, ALSA application and driver expecting
to run in a period of larger than 10ms regardless of the bit depth.
With this large period, there is a strong request to split the linked-list
in the AxiDMA driver.
Signed-off-by: Sia Jee Heng
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c| 111 ++
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 1 +
2 files changed, 92 insertions(+), 20 deletions(-)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 1a218fcdbb16..bf83dea947be 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -576,6 +576,11 @@ static int dw_axi_dma_set_hw_desc(struct axi_dma_chan
*chan,
if (mem_width > DWAXIDMAC_TRANS_WIDTH_32)
mem_width = DWAXIDMAC_TRANS_WIDTH_32;
+ if (!IS_ALIGNED(mem_addr, 4)) {
+ dev_err(chan->chip->dev, "invalid buffer alignment\n");
+ return -EINVAL;
+ }
+
switch (chan->direction) {
case DMA_MEM_TO_DEV:
reg_width = __ffs(chan->config.dst_addr_width);
@@ -637,6 +642,35 @@ static int dw_axi_dma_set_hw_desc(struct axi_dma_chan
*chan,
return 0;
}
+static size_t calculate_block_len(struct axi_dma_chan *chan,
+ dma_addr_t dma_addr, size_t buf_len,
+ enum dma_transfer_direction direction)
+{
+ u32 data_width, reg_width, mem_width;
+ size_t axi_block_ts, block_len;
+
+ axi_block_ts = chan->chip->dw->hdata->block_size[chan->id];
+
+ switch (direction) {
+ case DMA_MEM_TO_DEV:
+ data_width = BIT(chan->chip->dw->hdata->m_data_width);
+ mem_width = __ffs(data_width | dma_addr | buf_len);
+ if (mem_width > DWAXIDMAC_TRANS_WIDTH_32)
+ mem_width = DWAXIDMAC_TRANS_WIDTH_32;
+
+ block_len = axi_block_ts << mem_width;
+ break;
+ case DMA_DEV_TO_MEM:
+ reg_width = __ffs(chan->config.src_addr_width);
+ block_len = axi_block_ts << reg_width;
+ break;
+ default:
+ block_len = 0;
+ }
+
+ return block_len;
+}
+
static struct dma_async_tx_descriptor *
dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan, dma_addr_t dma_addr,
size_t buf_len, size_t period_len,
@@ -647,13 +681,27 @@ dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan,
dma_addr_t dma_addr,
struct axi_dma_hw_desc *hw_desc = NULL;
struct axi_dma_desc *desc = NULL;
dma_addr_t src_addr = dma_addr;
- u32 num_periods = buf_len / period_len;
+ u32 num_periods, num_segments;
+ size_t axi_block_len;
+ u32 total_segments;
+ u32 segment_len;
unsigned int i;
int status;
u64 llp = 0;
u8 lms = 0; /* Select AXI0 master for LLI fetching */
- desc = axi_desc_alloc(num_periods);
+ num_periods = buf_len / period_len;
+
+ axi_block_len = calculate_block_len(chan, dma_addr, buf_len, direction);
+ if (axi_block_len == 0)
+ return NULL;
+
+ num_segments = DIV_ROUND_UP(period_len, axi_block_len);
+ segment_len = DIV_ROUND_UP(period_len, num_segments);
+
+ total_segments = num_periods * num_segments;
+
+ desc = axi_desc_alloc(total_segments);
if (unlikely(!desc))
goto err_desc_get;
@@ -661,12 +709,13 @@ dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan,
dma_addr_t dma_addr,
desc->chan = chan;
chan->cyclic = true;
desc->length = 0;
+ desc->period_len = period_len;
- for (i = 0; i < num_periods; i++) {
+ for (i = 0; i < total_segments; i++) {
hw_desc = >hw_desc[i];
status = dw_axi_dma_set_hw_desc(chan, hw_desc, src_addr,
- period_len);
+ segment_len);
if (status < 0)
goto err_desc_get;
@@ -676,17 +725,17 @@ dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan,
dma_addr_t dma_addr,
*/
set_desc_last(hw_desc);
- src_addr += period_len;
+ src_addr += segment_len;
}
llp = desc->hw_desc[0].llp;
/* Managed transfer list */
do {
- hw_desc = >hw_desc[--num_pe
[PATCH v7 14/16] dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA BYTE and HALFWORD registers
Add support for Intel KeemBay AxiDMA BYTE and HALFWORD registers
programming.
Intel KeemBay AxiDMA supports data transfer between device to memory
and memory to device operations.
This code is needed by I2C, I3C, I2S, SPI and UART which uses FIFO
size of 8bits and 16bits to perform memory to device data transfer
operation. 0-padding functionality is provided to avoid
pre-processing of data on CPU.
Reviewed-by: Andy Shevchenko
Signed-off-by: Sia Jee Heng
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c| 44 ---
1 file changed, 39 insertions(+), 5 deletions(-)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 440f9a8b25da..dc7ddf98fd04 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -312,7 +312,7 @@ static void axi_chan_block_xfer_start(struct axi_dma_chan
*chan,
struct axi_dma_desc *first)
{
u32 priority = chan->chip->dw->hdata->priority[chan->id];
- u32 reg, irq_mask;
+ u32 reg, irq_mask, reg_width, offset, val;
u8 lms = 0; /* Select AXI0 master for LLI fetching */
if (unlikely(axi_chan_is_hw_enable(chan))) {
@@ -334,6 +334,25 @@ static void axi_chan_block_xfer_start(struct axi_dma_chan
*chan,
DWAXIDMAC_HS_SEL_HW << CH_CFG_H_HS_SEL_SRC_POS);
switch (chan->direction) {
case DMA_MEM_TO_DEV:
+ if (chan->chip->apb_regs) {
+ reg_width = __ffs(chan->config.dst_addr_width);
+ /*
+* Configure Byte and Halfword register
+* for MEM_TO_DEV only.
+*/
+ if (reg_width == DWAXIDMAC_TRANS_WIDTH_16) {
+ offset = DMAC_APB_HALFWORD_WR_CH_EN;
+ val = ioread32(chan->chip->apb_regs + offset);
+ val |= BIT(chan->id);
+ iowrite32(val, chan->chip->apb_regs + offset);
+ } else if (reg_width == DWAXIDMAC_TRANS_WIDTH_8) {
+ offset = DMAC_APB_BYTE_WR_CH_EN;
+ val = ioread32(chan->chip->apb_regs + offset);
+ val |= BIT(chan->id);
+ iowrite32(val, chan->chip->apb_regs + offset);
+ }
+ }
+
reg |= (chan->config.device_fc ?
DWAXIDMAC_TT_FC_MEM_TO_PER_DST :
DWAXIDMAC_TT_FC_MEM_TO_PER_DMAC)
@@ -994,8 +1013,9 @@ static int dma_chan_terminate_all(struct dma_chan *dchan)
{
struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
u32 chan_active = BIT(chan->id) << DMAC_CHAN_EN_SHIFT;
+ u32 reg_width = __ffs(chan->config.dst_addr_width);
unsigned long flags;
- u32 val;
+ u32 offset, val;
int ret;
LIST_HEAD(head);
@@ -1007,9 +1027,23 @@ static int dma_chan_terminate_all(struct dma_chan *dchan)
dev_warn(dchan2dev(dchan),
"%s failed to stop\n", axi_chan_name(chan));
- if (chan->direction != DMA_MEM_TO_MEM)
- dw_axi_dma_set_hw_channel(chan->chip,
- chan->hw_handshake_num, false);
+ if (chan->direction != DMA_MEM_TO_MEM) {
+ ret = dw_axi_dma_set_hw_channel(chan->chip,
+ chan->hw_handshake_num, false);
+ if (ret == 0 && chan->direction == DMA_MEM_TO_DEV) {
+ if (reg_width == DWAXIDMAC_TRANS_WIDTH_8) {
+ offset = DMAC_APB_BYTE_WR_CH_EN;
+ val = ioread32(chan->chip->apb_regs + offset);
+ val &= ~BIT(chan->id);
+ iowrite32(val, chan->chip->apb_regs + offset);
+ } else if (reg_width == DWAXIDMAC_TRANS_WIDTH_16) {
+ offset = DMAC_APB_HALFWORD_WR_CH_EN;
+ val = ioread32(chan->chip->apb_regs + offset);
+ val &= ~BIT(chan->id);
+ iowrite32(val, chan->chip->apb_regs + offset);
+ }
+ }
+ }
spin_lock_irqsave(>vc.lock, flags);
--
2.18.0
[PATCH v7 13/16] dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA handshake
Add support for Intel KeemBay AxiDMA device handshake programming.
Device handshake number passed in to the AxiDMA shall be written to
the Intel KeemBay AxiDMA hardware handshake registers before DMA
operations are started.
Reviewed-by: Andy Shevchenko
Signed-off-by: Sia Jee Heng
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c| 52 +++
1 file changed, 52 insertions(+)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 8135b827b47a..440f9a8b25da 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -445,6 +445,48 @@ static void dma_chan_free_chan_resources(struct dma_chan
*dchan)
pm_runtime_put(chan->chip->dev);
}
+static int dw_axi_dma_set_hw_channel(struct axi_dma_chip *chip,
+u32 handshake_num, bool set)
+{
+ unsigned long start = 0;
+ unsigned long reg_value;
+ unsigned long reg_mask;
+ unsigned long reg_set;
+ unsigned long mask;
+ unsigned long val;
+
+ if (!chip->apb_regs)
+ return -ENODEV;
+
+ /*
+* An unused DMA channel has a default value of 0x3F.
+* Lock the DMA channel by assign a handshake number to the channel.
+* Unlock the DMA channel by assign 0x3F to the channel.
+*/
+ if (set) {
+ reg_set = UNUSED_CHANNEL;
+ val = handshake_num;
+ } else {
+ reg_set = handshake_num;
+ val = UNUSED_CHANNEL;
+ }
+
+ reg_value = lo_hi_readq(chip->apb_regs + DMAC_APB_HW_HS_SEL_0);
+
+ for_each_set_clump8(start, reg_mask, _value, 64) {
+ if (reg_mask == reg_set) {
+ mask = GENMASK_ULL(start + 7, start);
+ reg_value &= ~mask;
+ reg_value |= rol64(val, start);
+ lo_hi_writeq(reg_value,
+chip->apb_regs + DMAC_APB_HW_HS_SEL_0);
+ break;
+ }
+ }
+
+ return 0;
+}
+
/*
* If DW_axi_dmac sees CHx_CTL.ShadowReg_Or_LLI_Last bit of the fetched LLI
* as 1, it understands that the current block is the final block in the
@@ -626,6 +668,9 @@ dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan,
dma_addr_t dma_addr,
llp = hw_desc->llp;
} while (num_periods);
+ if (dw_axi_dma_set_hw_channel(chan->chip, chan->hw_handshake_num, true))
+ goto err_desc_get;
+
return vchan_tx_prep(>vc, >vd, flags);
err_desc_get:
@@ -684,6 +729,9 @@ dw_axi_dma_chan_prep_slave_sg(struct dma_chan *dchan,
struct scatterlist *sgl,
llp = hw_desc->llp;
} while (sg_len);
+ if (dw_axi_dma_set_hw_channel(chan->chip, chan->hw_handshake_num, true))
+ goto err_desc_get;
+
return vchan_tx_prep(>vc, >vd, flags);
err_desc_get:
@@ -959,6 +1007,10 @@ static int dma_chan_terminate_all(struct dma_chan *dchan)
dev_warn(dchan2dev(dchan),
"%s failed to stop\n", axi_chan_name(chan));
+ if (chan->direction != DMA_MEM_TO_MEM)
+ dw_axi_dma_set_hw_channel(chan->chip,
+ chan->hw_handshake_num, false);
+
spin_lock_irqsave(>vc.lock, flags);
vchan_get_all_descriptors(>vc, );
--
2.18.0
[PATCH v7 15/16] dmaengine: dw-axi-dmac: Set constraint to the Max segment size
Add support for DMA Scatter-Gather (SG) constraint so that DMA clients can
handle the AxiDMA limitation.
Without supporting DMA constraint the default Max segment size reported by
dmaengine is 64KB, which is not supported by Intel KeemBay AxiDMA.
Reviewed-by: Andy Shevchenko
Signed-off-by: Sia Jee Heng
---
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 8
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 1 +
2 files changed, 9 insertions(+)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index dc7ddf98fd04..1a218fcdbb16 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -1350,6 +1351,13 @@ static int dw_probe(struct platform_device *pdev)
dw->dma.device_prep_slave_sg = dw_axi_dma_chan_prep_slave_sg;
dw->dma.device_prep_dma_cyclic = dw_axi_dma_chan_prep_cyclic;
+ /*
+* Synopsis DesignWare AxiDMA datasheet mentioned Maximum
+* supported blocks is 1024. Device register width is 4 bytes.
+* Therefore, set constraint to 1024 * 4.
+*/
+ dw->dma.dev->dma_parms = >dma_parms;
+ dma_set_max_seg_size(>dev, MAX_BLOCK_SIZE);
platform_set_drvdata(pdev, chip);
pm_runtime_enable(chip->dev);
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
index 3a357f7fda02..1e937ea2a96d 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
@@ -54,6 +54,7 @@ struct axi_dma_chan {
struct dw_axi_dma {
struct dma_device dma;
struct dw_axi_dma_hcfg *hdata;
+ struct device_dma_parametersdma_parms;
/* channels */
struct axi_dma_chan *chan;
--
2.18.0
[PATCH v7 12/16] dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA support
Add support for Intel KeemBay AxiDMA to the .compatible field.
The AxiDMA Apb region will be accessible if the compatible string
matches the "intel,kmb-axi-dma".
Reviewed-by: Andy Shevchenko
Signed-off-by: Sia Jee Heng
---
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 29323e75bc44..8135b827b47a 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -1160,6 +1160,7 @@ static int parse_device_properties(struct axi_dma_chip
*chip)
static int dw_probe(struct platform_device *pdev)
{
+ struct device_node *node = pdev->dev.of_node;
struct axi_dma_chip *chip;
struct resource *mem;
struct dw_axi_dma *dw;
@@ -1192,6 +1193,12 @@ static int dw_probe(struct platform_device *pdev)
if (IS_ERR(chip->regs))
return PTR_ERR(chip->regs);
+ if (of_device_is_compatible(node, "intel,kmb-axi-dma")) {
+ chip->apb_regs = devm_platform_ioremap_resource(pdev, 1);
+ if (IS_ERR(chip->apb_regs))
+ return PTR_ERR(chip->apb_regs);
+ }
+
chip->core_clk = devm_clk_get(chip->dev, "core-clk");
if (IS_ERR(chip->core_clk))
return PTR_ERR(chip->core_clk);
@@ -1336,6 +1343,7 @@ static const struct dev_pm_ops dw_axi_dma_pm_ops = {
static const struct of_device_id dw_dma_of_id_table[] = {
{ .compatible = "snps,axi-dma-1.01a" },
+ { .compatible = "intel,kmb-axi-dma" },
{}
};
MODULE_DEVICE_TABLE(of, dw_dma_of_id_table);
--
2.18.0
[PATCH v7 11/16] dmaengine: dw-axi-dmac: Add Intel KeemBay DMA register fields
Add support for Intel KeemBay DMA registers. These registers are required
to run data transfer between device to memory and memory to device on Intel
KeemBay SoC.
Reviewed-by: Andy Shevchenko
Signed-off-by: Sia Jee Heng
---
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
index 46baf93de617..3a357f7fda02 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
@@ -63,6 +63,7 @@ struct axi_dma_chip {
struct device *dev;
int irq;
void __iomem*regs;
+ void __iomem*apb_regs;
struct clk *core_clk;
struct clk *cfgr_clk;
struct dw_axi_dma *dw;
@@ -169,6 +170,19 @@ static inline struct axi_dma_chan
*dchan_to_axi_dma_chan(struct dma_chan *dchan)
#define CH_INTSIGNAL_ENA 0x090 /* R/W Chan Interrupt Signal Enable */
#define CH_INTCLEAR0x098 /* W Chan Interrupt Clear */
+/* These Apb registers are used by Intel KeemBay SoC */
+#define DMAC_APB_CFG 0x000 /* DMAC Apb Configuration Register */
+#define DMAC_APB_STAT 0x004 /* DMAC Apb Status Register */
+#define DMAC_APB_DEBUG_STAT_0 0x008 /* DMAC Apb Debug Status Register 0 */
+#define DMAC_APB_DEBUG_STAT_1 0x00C /* DMAC Apb Debug Status Register 1 */
+#define DMAC_APB_HW_HS_SEL_0 0x010 /* DMAC Apb HW HS register 0 */
+#define DMAC_APB_HW_HS_SEL_1 0x014 /* DMAC Apb HW HS register 1 */
+#define DMAC_APB_LPI 0x018 /* DMAC Apb Low Power Interface Reg */
+#define DMAC_APB_BYTE_WR_CH_EN 0x01C /* DMAC Apb Byte Write Enable */
+#define DMAC_APB_HALFWORD_WR_CH_EN 0x020 /* DMAC Halfword write enables */
+
+#define UNUSED_CHANNEL 0x3F /* Set unused DMA channel to 0x3F */
+#define MAX_BLOCK_SIZE 0x1000 /* 1024 blocks * 4 bytes data width */
/* DMAC_CFG */
#define DMAC_EN_POS0
--
2.18.0
[PATCH v7 07/16] dmaegine: dw-axi-dmac: Support device_prep_dma_cyclic()
Add support for device_prep_dma_cyclic() callback function to benefit
DMA cyclic client, for example ALSA.
Existing AxiDMA driver only support data transfer between memory to memory.
Data transfer between device to memory and memory to device in cyclic mode
would failed if this interface is not supported by the AxiDMA driver.
Reviewed-by: Andy Shevchenko
Signed-off-by: Sia Jee Heng
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c| 111 --
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 2 +
2 files changed, 106 insertions(+), 7 deletions(-)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 1674dcb6fc5b..b5f92f9cb2bc 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -15,6 +15,8 @@
#include
#include
#include
+#include
+#include
#include
#include
#include
@@ -549,6 +551,64 @@ static int dw_axi_dma_set_hw_desc(struct axi_dma_chan
*chan,
return 0;
}
+static struct dma_async_tx_descriptor *
+dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan, dma_addr_t dma_addr,
+ size_t buf_len, size_t period_len,
+ enum dma_transfer_direction direction,
+ unsigned long flags)
+{
+ struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
+ struct axi_dma_hw_desc *hw_desc = NULL;
+ struct axi_dma_desc *desc = NULL;
+ dma_addr_t src_addr = dma_addr;
+ u32 num_periods = buf_len / period_len;
+ unsigned int i;
+ int status;
+ u64 llp = 0;
+ u8 lms = 0; /* Select AXI0 master for LLI fetching */
+
+ desc = axi_desc_alloc(num_periods);
+ if (unlikely(!desc))
+ goto err_desc_get;
+
+ chan->direction = direction;
+ desc->chan = chan;
+ chan->cyclic = true;
+
+ for (i = 0; i < num_periods; i++) {
+ hw_desc = >hw_desc[i];
+
+ status = dw_axi_dma_set_hw_desc(chan, hw_desc, src_addr,
+ period_len);
+ if (status < 0)
+ goto err_desc_get;
+
+ /* Set end-of-link to the linked descriptor, so that cyclic
+* callback function can be triggered during interrupt.
+*/
+ set_desc_last(hw_desc);
+
+ src_addr += period_len;
+ }
+
+ llp = desc->hw_desc[0].llp;
+
+ /* Managed transfer list */
+ do {
+ hw_desc = >hw_desc[--num_periods];
+ write_desc_llp(hw_desc, llp | lms);
+ llp = hw_desc->llp;
+ } while (num_periods);
+
+ return vchan_tx_prep(>vc, >vd, flags);
+
+err_desc_get:
+ if (desc)
+ axi_desc_put(desc);
+
+ return NULL;
+}
+
static struct dma_async_tx_descriptor *
dw_axi_dma_chan_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl,
unsigned int sg_len,
@@ -773,8 +833,13 @@ static noinline void axi_chan_handle_err(struct
axi_dma_chan *chan, u32 status)
static void axi_chan_block_xfer_complete(struct axi_dma_chan *chan)
{
+ int count = atomic_read(>descs_allocated);
+ struct axi_dma_hw_desc *hw_desc;
+ struct axi_dma_desc *desc;
struct virt_dma_desc *vd;
unsigned long flags;
+ u64 llp;
+ int i;
spin_lock_irqsave(>vc.lock, flags);
if (unlikely(axi_chan_is_hw_enable(chan))) {
@@ -785,12 +850,32 @@ static void axi_chan_block_xfer_complete(struct
axi_dma_chan *chan)
/* The completed descriptor currently is in the head of vc list */
vd = vchan_next_desc(>vc);
- /* Remove the completed descriptor from issued list before completing */
- list_del(>node);
- vchan_cookie_complete(vd);
- /* Submit queued descriptors after processing the completed ones */
- axi_chan_start_first_queued(chan);
+ if (chan->cyclic) {
+ vchan_cyclic_callback(vd);
+ desc = vd_to_axi_desc(vd);
+ if (desc) {
+ llp = lo_hi_readq(chan->chan_regs + CH_LLP);
+ for (i = 0; i < count; i++) {
+ hw_desc = >hw_desc[i];
+ if (hw_desc->llp == llp) {
+ axi_chan_irq_clear(chan,
hw_desc->lli->status_lo);
+ hw_desc->lli->ctl_hi |=
CH_CTL_H_LLI_VALID;
+ desc->completed_blocks = i;
+ break;
+ }
+ }
+
+ axi_chan_enable(chan);
+ }
+ } else {
+ /* Remove the completed descriptor from issued list before
completing *
[PATCH v7 10/16] dt-binding: dma: dw-axi-dmac: Add support for Intel KeemBay AxiDMA
Add support for Intel KeemBay AxiDMA to the dw-axi-dmac Schemas DT binding. Signed-off-by: Sia Jee Heng Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml | 5 + 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml index 3d2515463d56..79e241498e25 100644 --- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml +++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml @@ -8,6 +8,7 @@ title: Synopsys DesignWare AXI DMA Controller maintainers: - Eugeniy Paltsev + - Jee Heng Sia description: Synopsys DesignWare AXI DMA Controller DT Binding @@ -19,14 +20,18 @@ properties: compatible: enum: - snps,axi-dma-1.01a + - intel,kmb-axi-dma reg: +minItems: 1 items: - description: Address range of the DMAC registers + - description: Address range of the DMAC APB registers reg-names: items: - const: axidma_ctrl_regs + - const: axidma_apb_regs interrupts: maxItems: 1 -- 2.18.0
[PATCH v7 06/16] dmaengine: dw-axi-dmac: Support device_prep_slave_sg
Add device_prep_slave_sg() callback function so that DMA_MEM_TO_DEV
and DMA_DEV_TO_MEM operations in single mode can be supported.
Existing AxiDMA driver only support data transfer between
memory to memory. Data transfer between device to memory and
memory to device in single mode would failed if this interface
is not supported by the AxiDMA driver.
Reviewed-by: Andy Shevchenko
Signed-off-by: Sia Jee Heng
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c| 154 ++
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 1 +
2 files changed, 155 insertions(+)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 16e6934ae9a1..1674dcb6fc5b 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -307,6 +307,22 @@ static void axi_chan_block_xfer_start(struct axi_dma_chan
*chan,
priority << CH_CFG_H_PRIORITY_POS |
DWAXIDMAC_HS_SEL_HW << CH_CFG_H_HS_SEL_DST_POS |
DWAXIDMAC_HS_SEL_HW << CH_CFG_H_HS_SEL_SRC_POS);
+ switch (chan->direction) {
+ case DMA_MEM_TO_DEV:
+ reg |= (chan->config.device_fc ?
+ DWAXIDMAC_TT_FC_MEM_TO_PER_DST :
+ DWAXIDMAC_TT_FC_MEM_TO_PER_DMAC)
+ << CH_CFG_H_TT_FC_POS;
+ break;
+ case DMA_DEV_TO_MEM:
+ reg |= (chan->config.device_fc ?
+ DWAXIDMAC_TT_FC_PER_TO_MEM_SRC :
+ DWAXIDMAC_TT_FC_PER_TO_MEM_DMAC)
+ << CH_CFG_H_TT_FC_POS;
+ break;
+ default:
+ break;
+ }
axi_chan_iowrite32(chan, CH_CFG_H, reg);
write_chan_llp(chan, first->hw_desc[0].llp | lms);
@@ -454,6 +470,141 @@ static void set_desc_dest_master(struct axi_dma_hw_desc
*hw_desc,
hw_desc->lli->ctl_lo = cpu_to_le32(val);
}
+static int dw_axi_dma_set_hw_desc(struct axi_dma_chan *chan,
+ struct axi_dma_hw_desc *hw_desc,
+ dma_addr_t mem_addr, size_t len)
+{
+ unsigned int data_width = BIT(chan->chip->dw->hdata->m_data_width);
+ unsigned int reg_width;
+ unsigned int mem_width;
+ dma_addr_t device_addr;
+ size_t axi_block_ts;
+ size_t block_ts;
+ u32 ctllo, ctlhi;
+ u32 burst_len;
+
+ axi_block_ts = chan->chip->dw->hdata->block_size[chan->id];
+
+ mem_width = __ffs(data_width | mem_addr | len);
+ if (mem_width > DWAXIDMAC_TRANS_WIDTH_32)
+ mem_width = DWAXIDMAC_TRANS_WIDTH_32;
+
+ switch (chan->direction) {
+ case DMA_MEM_TO_DEV:
+ reg_width = __ffs(chan->config.dst_addr_width);
+ device_addr = chan->config.dst_addr;
+ ctllo = reg_width << CH_CTL_L_DST_WIDTH_POS |
+ mem_width << CH_CTL_L_SRC_WIDTH_POS |
+ DWAXIDMAC_CH_CTL_L_NOINC << CH_CTL_L_DST_INC_POS |
+ DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_SRC_INC_POS;
+ block_ts = len >> mem_width;
+ break;
+ case DMA_DEV_TO_MEM:
+ reg_width = __ffs(chan->config.src_addr_width);
+ device_addr = chan->config.src_addr;
+ ctllo = reg_width << CH_CTL_L_SRC_WIDTH_POS |
+ mem_width << CH_CTL_L_DST_WIDTH_POS |
+ DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_DST_INC_POS |
+ DWAXIDMAC_CH_CTL_L_NOINC << CH_CTL_L_SRC_INC_POS;
+ block_ts = len >> reg_width;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (block_ts > axi_block_ts)
+ return -EINVAL;
+
+ hw_desc->lli = axi_desc_get(chan, _desc->llp);
+ if (unlikely(!hw_desc->lli))
+ return -ENOMEM;
+
+ ctlhi = CH_CTL_H_LLI_VALID;
+
+ if (chan->chip->dw->hdata->restrict_axi_burst_len) {
+ burst_len = chan->chip->dw->hdata->axi_rw_burst_len;
+ ctlhi |= CH_CTL_H_ARLEN_EN | CH_CTL_H_AWLEN_EN |
+burst_len << CH_CTL_H_ARLEN_POS |
+burst_len << CH_CTL_H_AWLEN_POS;
+ }
+
+ hw_desc->lli->ctl_hi = cpu_to_le32(ctlhi);
+
+ if (chan->direction == DMA_MEM_TO_DEV) {
+ write_desc_sar(hw_desc, mem_addr);
+ write_desc_dar(hw_desc, device_addr);
+ } else {
+ write_desc_sar(hw_desc, device_addr);
+ write_desc_dar(hw_desc, mem_addr);
+ }
+
+ hw_desc->lli->block_ts_lo = cpu_to_le32(block_ts - 1);
+
+ ctllo |= DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CT
[PATCH v7 09/16] dmaengine: dw-axi-dmac: Support burst residue granularity
Add support for DMA_RESIDUE_GRANULARITY_BURST so that AxiDMA can report
DMA residue.
Existing AxiDMA driver only support data transfer between
memory to memory operation, therefore reporting DMA residue
to the DMA clients is not supported.
Reporting DMA residue to the DMA clients is important as DMA clients
shall invoke dmaengine_tx_status() to understand the number of bytes
been transferred so that the buffer pointer can be updated accordingly.
Reviewed-by: Andy Shevchenko
Signed-off-by: Sia Jee Heng
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c| 43 ---
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 2 +
2 files changed, 38 insertions(+), 7 deletions(-)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 40c4af0e0421..29323e75bc44 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -265,14 +265,36 @@ dma_chan_tx_status(struct dma_chan *dchan, dma_cookie_t
cookie,
struct dma_tx_state *txstate)
{
struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
- enum dma_status ret;
+ struct virt_dma_desc *vdesc;
+ enum dma_status status;
+ u32 completed_length;
+ unsigned long flags;
+ u32 completed_blocks;
+ size_t bytes = 0;
+ u32 length;
+ u32 len;
- ret = dma_cookie_status(dchan, cookie, txstate);
+ status = dma_cookie_status(dchan, cookie, txstate);
+ if (status == DMA_COMPLETE || !txstate)
+ return status;
- if (chan->is_paused && ret == DMA_IN_PROGRESS)
- ret = DMA_PAUSED;
+ spin_lock_irqsave(>vc.lock, flags);
- return ret;
+ vdesc = vchan_find_desc(>vc, cookie);
+ if (vdesc) {
+ length = vd_to_axi_desc(vdesc)->length;
+ completed_blocks = vd_to_axi_desc(vdesc)->completed_blocks;
+ len = vd_to_axi_desc(vdesc)->hw_desc[0].len;
+ completed_length = completed_blocks * len;
+ bytes = length - completed_length;
+ } else {
+ bytes = vd_to_axi_desc(vdesc)->length;
+ }
+
+ spin_unlock_irqrestore(>vc.lock, flags);
+ dma_set_residue(txstate, bytes);
+
+ return status;
}
static void write_desc_llp(struct axi_dma_hw_desc *desc, dma_addr_t adr)
@@ -549,6 +571,7 @@ static int dw_axi_dma_set_hw_desc(struct axi_dma_chan *chan,
set_desc_src_master(hw_desc);
+ hw_desc->len = len;
return 0;
}
@@ -575,6 +598,7 @@ dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan,
dma_addr_t dma_addr,
chan->direction = direction;
desc->chan = chan;
chan->cyclic = true;
+ desc->length = 0;
for (i = 0; i < num_periods; i++) {
hw_desc = >hw_desc[i];
@@ -584,6 +608,7 @@ dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan,
dma_addr_t dma_addr,
if (status < 0)
goto err_desc_get;
+ desc->length += hw_desc->len;
/* Set end-of-link to the linked descriptor, so that cyclic
* callback function can be triggered during interrupt.
*/
@@ -636,6 +661,7 @@ dw_axi_dma_chan_prep_slave_sg(struct dma_chan *dchan,
struct scatterlist *sgl,
goto err_desc_get;
desc->chan = chan;
+ desc->length = 0;
for_each_sg(sgl, sg, sg_len, i) {
mem = sg_dma_address(sg);
@@ -645,6 +671,7 @@ dw_axi_dma_chan_prep_slave_sg(struct dma_chan *dchan,
struct scatterlist *sgl,
status = dw_axi_dma_set_hw_desc(chan, hw_desc, mem, len);
if (status < 0)
goto err_desc_get;
+ desc->length += hw_desc->len;
}
/* Set end-of-link to the last link descriptor of list */
@@ -690,6 +717,7 @@ dma_chan_prep_dma_memcpy(struct dma_chan *dchan, dma_addr_t
dst_adr,
desc->chan = chan;
num = 0;
+ desc->length = 0;
while (len) {
xfer_len = len;
@@ -742,7 +770,8 @@ dma_chan_prep_dma_memcpy(struct dma_chan *dchan, dma_addr_t
dst_adr,
set_desc_src_master(hw_desc);
set_desc_dest_master(hw_desc, desc);
-
+ hw_desc->len = xfer_len;
+ desc->length += hw_desc->len;
/* update the length and addresses for the next loop cycle */
len -= xfer_len;
dst_adr += xfer_len;
@@ -1210,7 +1239,7 @@ static int dw_probe(struct platform_device *pdev)
dw->dma.dst_addr_widths = AXI_DMA_BUSWIDTHS;
dw->dma.directions = BIT(DMA_MEM_TO_MEM);
dw->dma.directions |= BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM);
- dw->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
+ dw
