Re: [PATCHv5 1/6] PCI: mobiveil: Refactor Mobiveil PCIe Host Bridge IP driver
ZQ,
On Fri, Apr 12, 2019 at 3:22 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> Refactor the Mobiveil PCIe Host Bridge IP driver to make
> it easier to add support for both RC and EP mode driver.
> This patch moved the Mobiveil driver to an new directory
> 'drivers/pci/controller/mobiveil' and refactor it according
> to the RC and EP abstraction.
>
> Signed-off-by: Hou Zhiqiang
> Reviewed-by: Minghuan Lian
> Reviewed-by: Subrahmanya Lingappa
> ---
> V5:
> - Regenerated this patch on the new base.
> - Retouched the changelog.
> - Updated the Copyright.
>
> MAINTAINERS | 2 +-
> drivers/pci/controller/Kconfig| 11 +-
> drivers/pci/controller/Makefile | 2 +-
> drivers/pci/controller/mobiveil/Kconfig | 24 +
> drivers/pci/controller/mobiveil/Makefile | 4 +
> .../pcie-mobiveil-host.c} | 570 +++---
> .../controller/mobiveil/pcie-mobiveil-plat.c | 56 ++
> .../pci/controller/mobiveil/pcie-mobiveil.c | 248
> .../pci/controller/mobiveil/pcie-mobiveil.h | 211 +++
> 9 files changed, 636 insertions(+), 492 deletions(-)
> create mode 100644 drivers/pci/controller/mobiveil/Kconfig
> create mode 100644 drivers/pci/controller/mobiveil/Makefile
> rename drivers/pci/controller/{pcie-mobiveil.c =>
> mobiveil/pcie-mobiveil-host.c} (53%)
> create mode 100644 drivers/pci/controller/mobiveil/pcie-mobiveil-plat.c
> create mode 100644 drivers/pci/controller/mobiveil/pcie-mobiveil.c
> create mode 100644 drivers/pci/controller/mobiveil/pcie-mobiveil.h
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 1e64279f338a..1013e74b14f2 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -11877,7 +11877,7 @@ M: Subrahmanya Lingappa
>
> L: linux-...@vger.kernel.org
> S: Supported
> F: Documentation/devicetree/bindings/pci/mobiveil-pcie.txt
> -F: drivers/pci/controller/pcie-mobiveil.c
> +F: drivers/pci/controller/mobiveil/pcie-mobiveil*
>
Please add yourself as co-maintainer of the mobiveil driver.
>
> PCI DRIVER FOR MVEBU (Marvell Armada 370 and Armada XP SOC support)
> M: Thomas Petazzoni
> diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
> index 6671946dbf66..0e981ed00a75 100644
> --- a/drivers/pci/controller/Kconfig
> +++ b/drivers/pci/controller/Kconfig
> @@ -241,16 +241,6 @@ config PCIE_MEDIATEK
> Say Y here if you want to enable PCIe controller support on
> MediaTek SoCs.
>
> -config PCIE_MOBIVEIL
> - bool "Mobiveil AXI PCIe controller"
> - depends on ARCH_ZYNQMP || COMPILE_TEST
> - depends on OF
> - depends on PCI_MSI_IRQ_DOMAIN
> - help
> - Say Y here if you want to enable support for the Mobiveil AXI PCIe
> - Soft IP. It has up to 8 outbound and inbound windows
> - for address translation and it is a PCIe Gen4 IP.
> -
> config PCIE_TANGO_SMP8759
> bool "Tango SMP8759 PCIe controller (DANGEROUS)"
> depends on ARCH_TANGO && PCI_MSI && OF
> @@ -281,4 +271,5 @@ config VMD
> module will be called vmd.
>
> source "drivers/pci/controller/dwc/Kconfig"
> +source "drivers/pci/controller/mobiveil/Kconfig"
> endmenu
> diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile
> index d56a507495c5..b79a615041a0 100644
> --- a/drivers/pci/controller/Makefile
> +++ b/drivers/pci/controller/Makefile
> @@ -26,11 +26,11 @@ obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o
> obj-$(CONFIG_PCIE_ROCKCHIP_EP) += pcie-rockchip-ep.o
> obj-$(CONFIG_PCIE_ROCKCHIP_HOST) += pcie-rockchip-host.o
> obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
> -obj-$(CONFIG_PCIE_MOBIVEIL) += pcie-mobiveil.o
> obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
> obj-$(CONFIG_VMD) += vmd.o
> # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW
> obj-y += dwc/
> +obj-y += mobiveil/
>
>
> # The following drivers are for devices that use the generic ACPI
> diff --git a/drivers/pci/controller/mobiveil/Kconfig
> b/drivers/pci/controller/mobiveil/Kconfig
> new file mode 100644
> index ..64343c07bfed
> --- /dev/null
> +++ b/drivers/pci/controller/mobiveil/Kconfig
> @@ -0,0 +1,24 @@
> +# SPDX-License-Identifier: GPL-2.0
> +
> +menu "Mobiveil PCIe Core Support"
> + depends on PCI
> +
> +config PCIE_MOBIVEIL
> + bool
> +
> +config PCIE_MOBIVEIL_HOST
> +bool
> + depends on PCI_MSI_IRQ_DOMAIN
> +select PCIE_MOBIVEIL
> +
> +config PCIE_
Re: [PATCHv4 11/28] PCI: mobiveil: only fix up the Class Code field
Bjorn/ZQ,
On Tue, Mar 12, 2019 at 2:48 PM Z.q. Hou wrote:
>
> Hi Bjorn,
>
> Thanks a lot for your comments!
>
> > -Original Message-
> > From: Bjorn Helgaas [mailto:helg...@kernel.org]
> > Sent: 2019年3月11日 22:14
> > To: Z.q. Hou
> > Cc: linux-...@vger.kernel.org; linux-arm-ker...@lists.infradead.org;
> > devicet...@vger.kernel.org; linux-kernel@vger.kernel.org;
> > robh...@kernel.org; mark.rutl...@arm.com; l.subrahma...@mobiveil.co.in;
> > shawn...@kernel.org; Leo Li ;
> > lorenzo.pieral...@arm.com; catalin.mari...@arm.com;
> > will.dea...@arm.com; Mingkai Hu ; M.h. Lian
> > ; Xiaowei Bao
> > Subject: Re: [PATCHv4 11/28] PCI: mobiveil: only fix up the Class Code field
> >
> > On Mon, Mar 11, 2019 at 09:31:23AM +, Z.q. Hou wrote:
> > > From: Hou Zhiqiang
> > >
> > > Fix up the Class Code to PCI bridge, do not change the Revision ID.
> > > And move the fixup to mobiveil_host_init function.
> >
> > Add parens after function name.
> >
> > Please explain why this change is needed. Does it fix a bug?
> >
> > Does this fix the problem that the PCI core didn't correctly identify the
> > device
> > as a bridge because it identified bridges by class code instead of header
> > type?
> >
> > That problem *should* be fixed by b2fb5cc57469 ("PCI: Rely on config space
> > header type, not class code"), which is now upstream.
> >
> > You might still want this class code change so that lspci shows the correct
> > thing. That's fine, but the changelog should say why we're doing it.
> >
>
> Subrahmanya's original patch is to fixup 'Class Code' field, but it also
> fixed the 'Revision ID' field. This patch is patch is to remove the fixup of
> 'Revision ID' field.
it was introduced during the test with 4.9 and 4.15 linux version,
without this fix driver was not getting loaded.
I belive it should be sufficient to mention in code comment: "Fixing
the class code as hardware is not reflecting the correct class code",
And the changelog for this patch mentioning "avoid changing the
revision ID during the class code fix". Is that OK?
Thanks,
>
> > > Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP
> > > driver")
> >
> > Make this "Fixes:" line a single line again.
> >
> > > Signed-off-by: Hou Zhiqiang
> > > Reviewed-by: Minghuan Lian
> > > Reviewed-by: Subrahmanya Lingappa
> > > ---
> > > V4:
> > > - no change
> > >
> > > drivers/pci/controller/pcie-mobiveil.c | 9 ++---
> > > 1 file changed, 6 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/drivers/pci/controller/pcie-mobiveil.c
> > > b/drivers/pci/controller/pcie-mobiveil.c
> > > index 78e575e71f4d..8eee1ab7ee24 100644
> > > --- a/drivers/pci/controller/pcie-mobiveil.c
> > > +++ b/drivers/pci/controller/pcie-mobiveil.c
> > > @@ -653,6 +653,12 @@ static int mobiveil_host_init(struct mobiveil_pcie
> > *pcie)
> > >type, resource_size(win->res));
> > > }
> > >
> > > + /* fixup for PCIe class register */
> > > + value = csr_readl(pcie, PAB_INTP_AXI_PIO_CLASS);
> > > + value &= 0xff;
> > > + value |= (PCI_CLASS_BRIDGE_PCI << 16);
> > > + csr_writel(pcie, value, PAB_INTP_AXI_PIO_CLASS);
> > > +
> > > /* setup MSI hardware registers */
> > > mobiveil_pcie_enable_msi(pcie);
> > >
> > > @@ -896,9 +902,6 @@ static int mobiveil_pcie_probe(struct
> > platform_device *pdev)
> > > goto error;
> > > }
> > >
> > > - /* fixup for PCIe class register */
> > > - csr_writel(pcie, 0x060402ab, PAB_INTP_AXI_PIO_CLASS);
> > > -
> > > /* initialize the IRQ domains */
> > > ret = mobiveil_pcie_init_irq_domain(pcie);
> > > if (ret) {
> > > --
> > > 2.17.1
> > >
>
> Thanks,
> Zhiqiang
Re: [PATCH 1/6] PCI: mobiveil: Add the EP mode support
* starting offset of INTX bits in status register */
> #define PAB_INTX_START 5
>
> @@ -137,6 +157,7 @@
> ((off >> PAGE_SEL_OFFSET_SHIFT) & PAGE_SEL_MASK)
>
> struct mobiveil_pcie;
> +struct mobiveil_pcie_ep;
>
> struct mobiveil_msi { /* MSI information */
> struct mutex lock; /* protect bitmap variable */
> @@ -169,6 +190,29 @@ struct mobiveil_pab_ops {
> int (*host_init)(struct mobiveil_pcie *pcie);
> };
>
> +struct mobiveil_pcie_ep_ops {
> + void (*ep_init)(struct mobiveil_pcie_ep *ep);
> + int (*raise_irq)(struct mobiveil_pcie_ep *ep, u8 func_no,
> +enum pci_epc_irq_type type, u16 interrupt_num);
> +};
> +
> +struct mobiveil_pcie_ep {
> + struct pci_epc *epc;
> + struct mobiveil_pcie_ep_ops *ops;
> + phys_addr_t phys_base;
> + size_t addr_size;
> + size_t page_size;
> + phys_addr_t *outbound_addr;
> + unsigned long *ob_window_map;
> + u32 num_ob_windows;
> + void __iomem *msi_mem;
> + phys_addr_t msi_mem_phys;
> + u8 msi_cap; /* MSI capability offset */
> + u8 msix_cap;/* MSI-X capability offset */
> + u8 bar_num;
> + u32 pf_num;
> +};
> +
> struct mobiveil_pcie {
> struct platform_device *pdev;
> struct list_head *resources;
> @@ -181,7 +225,10 @@ struct mobiveil_pcie {
> u32 ib_wins_configured; /* configured inbound windows */
> const struct mobiveil_pab_ops *ops;
> struct root_port rp;
> + struct mobiveil_pcie_ep ep;
> };
> +#define to_mobiveil_pcie_from_ep(endpoint) \
> + container_of((endpoint), struct mobiveil_pcie, ep)
>
> int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie);
> int mobiveil_host_init(struct mobiveil_pcie *pcie, bool reinit);
> @@ -226,4 +273,21 @@ static inline void csr_writeb(struct mobiveil_pcie
> *pcie, u32 val, u32 off)
> csr_write(pcie, val, off, 0x1);
> }
>
> +void program_ib_windows_ep(struct mobiveil_pcie *pcie, u8 func_no,
> + int bar, u64 phys);
> +int program_ob_windows_ep(struct mobiveil_pcie *pcie, int win_num, int type,
> + u64 phys, u64 bus_addr, u8 func, u64 size);
> +void mobiveil_pcie_disable_ib_win_ep(struct mobiveil_pcie *pci,
> +u8 func_no, u8 bar);
> +int mobiveil_pcie_ep_init(struct mobiveil_pcie_ep *ep);
> +int mobiveil_pcie_ep_raise_legacy_irq(struct mobiveil_pcie_ep *ep, u8
> func_no);
> +int mobiveil_pcie_ep_raise_msi_irq(struct mobiveil_pcie_ep *ep, u8 func_no,
> +u8 interrupt_num);
> +int mobiveil_pcie_ep_raise_msix_irq(struct mobiveil_pcie_ep *ep, u8 func_no,
> +u16 interrupt_num);
> +void mobiveil_pcie_ep_reset_bar(struct mobiveil_pcie *pci, enum pci_barno
> bar);
> +void mobiveil_pcie_enable_bridge_pio(struct mobiveil_pcie *pci);
> +void mobiveil_pcie_enable_engine_apio(struct mobiveil_pcie *pci);
> +void mobiveil_pcie_enable_engine_ppio(struct mobiveil_pcie *pci);
> +void mobiveil_pcie_enable_msi_ep(struct mobiveil_pcie *pci);
> #endif /* _PCIE_MOBIVEIL_H */
> --
> 1.7.1
>
Please review and fix macro alignments, otherwise looks ok.
Reviewed-by: Subrahmanya Lingappa
Re: [PATCHv3 25/27] PCI: mobiveil: ls_pcie_g4: add Workaround for A-011451
ZQ,
On Tue, Jan 29, 2019 at 1:41 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> When LX2 PCIe controller is sending multiple split completions and
> ACK latency expires indicating that ACK should be send at priority.
> But because of large number of split completions and FC update DLLP,
> the controller does not give priority to ACK transmission. This
> results into ACK latency timer timeout error at the link partner and
> the pending TLPs are replayed by the link partner again.
>
> Workaround:
> 1. Reduce the ACK latency timeout value to a very small value.
> 2. Restrict the number of completions from the LX2 PCIe controller
>to 1, by changing the Max Read Request Size (MRRS) of link partner
>to the same value as Max Packet size (MPS).
>
> This patch implemented part 1, the part 2 can be set by kernel parameter
> 'pci=pcie_bus_perf'
>
> This ERRATA is only for LX2160A Rev1.0, and it will be fixed
> in Rev2.0.
>
> Signed-off-by: Hou Zhiqiang
> ---
> V3:
> - Integrated without change from http://patchwork.ozlabs.org/patch/1006796/
>
> .../pci/controller/mobiveil/pci-layerscape-gen4.c | 15 +++
> drivers/pci/controller/mobiveil/pcie-mobiveil.h | 4
> 2 files changed, 19 insertions(+)
>
> diff --git a/drivers/pci/controller/mobiveil/pci-layerscape-gen4.c
> b/drivers/pci/controller/mobiveil/pci-layerscape-gen4.c
> index d2c5dbbd5e3c..20ce146788ca 100644
> --- a/drivers/pci/controller/mobiveil/pci-layerscape-gen4.c
> +++ b/drivers/pci/controller/mobiveil/pci-layerscape-gen4.c
> @@ -82,12 +82,27 @@ static bool ls_pcie_g4_is_bridge(struct ls_pcie_g4 *pcie)
> return header_type == PCI_HEADER_TYPE_BRIDGE;
> }
>
> +static void workaround_A011451(struct ls_pcie_g4 *pcie)
> +{
> + struct mobiveil_pcie *mv_pci = pcie->pci;
> + u32 val;
> +
> + /* Set ACK latency timeout */
> + val = csr_readl(mv_pci, GPEX_ACK_REPLAY_TO);
> + val &= ~(ACK_LAT_TO_VAL_MASK << ACK_LAT_TO_VAL_SHIFT);
> + val |= (4 << ACK_LAT_TO_VAL_SHIFT);
> + csr_writel(mv_pci, val, GPEX_ACK_REPLAY_TO);
> +}
> +
> static int ls_pcie_g4_host_init(struct mobiveil_pcie *pci)
> {
> struct ls_pcie_g4 *pcie = to_ls_pcie_g4(pci);
>
> pcie->rev = csr_readb(pci, PCI_REVISION_ID);
>
> + if (pcie->rev == REV_1_0)
> + workaround_A011451(pcie);
> +
> return 0;
> }
>
> diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.h
> b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
> index ab43de5e4b2b..f0e2e4ae09b5 100644
> --- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h
> +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
> @@ -85,6 +85,10 @@
> #define PAB_AXI_AMAP_PEX_WIN_H(win)PAB_REG_ADDR(0x0bac, win)
> #define PAB_INTP_AXI_PIO_CLASS 0x474
>
> +#define GPEX_ACK_REPLAY_TO 0x438
> +#define ACK_LAT_TO_VAL_MASK 0x1fff
> +#define ACK_LAT_TO_VAL_SHIFT 0
> +
> #define PAB_PEX_AMAP_CTRL(win) PAB_REG_ADDR(0x4ba0, win)
> #define AMAP_CTRL_EN_SHIFT0
> #define AMAP_CTRL_TYPE_SHIFT 1
> --
> 2.17.1
>
again, can we avoid errata number on patch title and have a brief title instead?
Re: [PATCHv3 24/27] PCI: mobiveil: ls_pcie_g4: add Workaround for A-011577
ZQ,
On Tue, Jan 29, 2019 at 1:41 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> PCIe configuration access to non-existent function triggered
> SERROR interrupt exception.
>
> Workaround:
> Disable error reporting on AXI bus during the Vendor ID read
> transactions in enumeration.
>
> This ERRATA is only for LX2160A Rev1.0, and it will be fixed
> in Rev2.0.
>
> Signed-off-by: Hou Zhiqiang
> ---
> V3:
> - Integrated without change from http://patchwork.ozlabs.org/patch/1006790/
>
> .../controller/mobiveil/pci-layerscape-gen4.c | 37 +++
> .../controller/mobiveil/pcie-mobiveil-host.c | 17 -
> .../pci/controller/mobiveil/pcie-mobiveil.h | 3 ++
> 3 files changed, 56 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/mobiveil/pci-layerscape-gen4.c
> b/drivers/pci/controller/mobiveil/pci-layerscape-gen4.c
> index 174cbcac4059..d2c5dbbd5e3c 100644
> --- a/drivers/pci/controller/mobiveil/pci-layerscape-gen4.c
> +++ b/drivers/pci/controller/mobiveil/pci-layerscape-gen4.c
> @@ -22,8 +22,13 @@
>
> #include "pcie-mobiveil.h"
>
> +#define REV_1_0(0x10)
> +
> /* LUT and PF control registers */
> #define PCIE_LUT_OFF (0x8)
> +#define PCIE_LUT_GCR (0x28)
> +#define PCIE_LUT_GCR_RRE (0)
> +
> #define PCIE_PF_OFF(0xc)
> #define PCIE_PF_INT_STAT (0x18)
> #define PF_INT_STAT_PABRST (31)
> @@ -41,6 +46,7 @@ struct ls_pcie_g4 {
> struct mobiveil_pcie *pci;
> struct delayed_work dwork;
> int irq;
> + u8 rev;
> };
>
> static inline u32 ls_pcie_g4_lut_readl(struct ls_pcie_g4 *pcie, u32 off)
> @@ -76,6 +82,15 @@ static bool ls_pcie_g4_is_bridge(struct ls_pcie_g4 *pcie)
> return header_type == PCI_HEADER_TYPE_BRIDGE;
> }
>
> +static int ls_pcie_g4_host_init(struct mobiveil_pcie *pci)
> +{
> + struct ls_pcie_g4 *pcie = to_ls_pcie_g4(pci);
> +
> + pcie->rev = csr_readb(pci, PCI_REVISION_ID);
> +
> + return 0;
> +}
> +
> static int ls_pcie_g4_link_up(struct mobiveil_pcie *pci)
> {
> struct ls_pcie_g4 *pcie = to_ls_pcie_g4(pci);
> @@ -188,12 +203,34 @@ static void ls_pcie_g4_reset(struct work_struct *work)
> ls_pcie_g4_reinit_hw(pcie);
> }
>
> +static int ls_pcie_g4_read_other_conf(struct pci_bus *bus, unsigned int
> devfn,
> + int where, int size, u32 *val)
> +{
> + struct mobiveil_pcie *pci = bus->sysdata;
> + struct ls_pcie_g4 *pcie = to_ls_pcie_g4(pci);
> + int ret;
> +
> + if (pcie->rev == REV_1_0 && where == PCI_VENDOR_ID)
> + ls_pcie_g4_lut_writel(pcie, PCIE_LUT_GCR,
> + 0 << PCIE_LUT_GCR_RRE);
> +
> + ret = pci_generic_config_read(bus, devfn, where, size, val);
> +
> + if (pcie->rev == REV_1_0 && where == PCI_VENDOR_ID)
> + ls_pcie_g4_lut_writel(pcie, PCIE_LUT_GCR,
> + 1 << PCIE_LUT_GCR_RRE);
> +
> + return ret;
> +}
> +
> static struct mobiveil_rp_ops ls_pcie_g4_rp_ops = {
> .interrupt_init = ls_pcie_g4_interrupt_init,
> + .read_other_conf = ls_pcie_g4_read_other_conf,
> };
>
> static const struct mobiveil_pab_ops ls_pcie_g4_pab_ops = {
> .link_up = ls_pcie_g4_link_up,
> + .host_init = ls_pcie_g4_host_init,
> };
>
> static int __init ls_pcie_g4_probe(struct platform_device *pdev)
> diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
> b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
> index e8d0c4989013..5f51bc2dd6d7 100644
> --- a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
> +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
> @@ -79,9 +79,20 @@ static void __iomem *mobiveil_pcie_map_bus(struct pci_bus
> *bus,
> return pcie->rp.config_axi_slave_base + where;
> }
>
> +static int mobiveil_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
> +int where, int size, u32 *val)
> +{
> + struct mobiveil_pcie *pcie = bus->sysdata;
> + struct root_port *rp = >rp;
> +
> + if (bus->number > rp->root_bus_nr && rp->ops->read_other_conf)
> + return rp->ops->read_other_conf(bus, devfn, where, size, val);
> +
> + return pci_generic_config_read(bus, devfn, where, size, val);
> +}
> static struct pci_ops mobiveil_pcie_ops = {
> .map_bus = mobiveil_pcie_map_bus,
> - .read = pci_generic_config_read,
> + .read = mobiveil_pcie_config_read,
> .write = pci_generic_config_write,
> };
>
> @@ -309,6 +320,10 @@ int mobiveil_host_init(struct mobiveil_pcie *pcie, bool
> reinit)
> value |= (PCI_CLASS_BRIDGE_PCI << 16);
> csr_writel(pcie, value, PAB_INTP_AXI_PIO_CLASS);
>
> + /* Platform specific host init */
> + if (pcie->ops->host_init)
> + return pcie->ops->host_init(pcie);
> +
>
Re: [PATCHv3 23/27] PCI: mobiveil: add PCIe Gen4 RC driver for NXP Layerscape SoCs
ZQ,
On Tue, Jan 29, 2019 at 1:40 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> This PCIe controller is based on the Mobiveil GPEX IP, which is
> compatible with the PCI Express™ Base Specification, Revision 4.0.
>
> Signed-off-by: Hou Zhiqiang
> Reviewed-by: Minghuan Lian
> ---
> V3:
> - No change
>
> drivers/pci/controller/mobiveil/Kconfig | 10 +
> drivers/pci/controller/mobiveil/Makefile | 1 +
> .../controller/mobiveil/pci-layerscape-gen4.c | 254 ++
> .../pci/controller/mobiveil/pcie-mobiveil.h | 16 +-
> 4 files changed, 279 insertions(+), 2 deletions(-)
> create mode 100644 drivers/pci/controller/mobiveil/pci-layerscape-gen4.c
>
> diff --git a/drivers/pci/controller/mobiveil/Kconfig
> b/drivers/pci/controller/mobiveil/Kconfig
> index 64343c07bfed..3ddb7d6163a9 100644
> --- a/drivers/pci/controller/mobiveil/Kconfig
> +++ b/drivers/pci/controller/mobiveil/Kconfig
> @@ -21,4 +21,14 @@ config PCIE_MOBIVEIL_PLAT
> Soft IP. It has up to 8 outbound and inbound windows
> for address translation and it is a PCIe Gen4 IP.
>
> +config PCI_LAYERSCAPE_GEN4
> + bool "Freescale Layerscpe PCIe Gen4 controller"
> + depends on PCI
> + depends on OF && (ARM64 || ARCH_LAYERSCAPE)
> + depends on PCI_MSI_IRQ_DOMAIN
> + select PCIE_MOBIVEIL_HOST
> + help
> + Say Y here if you want PCIe Gen4 controller support on
> + Layerscape SoCs. The PCIe controller can work in RC or
> + EP mode according to RCW[HOST_AGT_PEX] setting.
> endmenu
> diff --git a/drivers/pci/controller/mobiveil/Makefile
> b/drivers/pci/controller/mobiveil/Makefile
> index 9fb6d1c6504d..ff66774ccac4 100644
> --- a/drivers/pci/controller/mobiveil/Makefile
> +++ b/drivers/pci/controller/mobiveil/Makefile
> @@ -2,3 +2,4 @@
> obj-$(CONFIG_PCIE_MOBIVEIL) += pcie-mobiveil.o
> obj-$(CONFIG_PCIE_MOBIVEIL_HOST) += pcie-mobiveil-host.o
> obj-$(CONFIG_PCIE_MOBIVEIL_PLAT) += pcie-mobiveil-plat.o
> +obj-$(CONFIG_PCI_LAYERSCAPE_GEN4) += pci-layerscape-gen4.o
> diff --git a/drivers/pci/controller/mobiveil/pci-layerscape-gen4.c
> b/drivers/pci/controller/mobiveil/pci-layerscape-gen4.c
> new file mode 100644
> index ..174cbcac4059
> --- /dev/null
> +++ b/drivers/pci/controller/mobiveil/pci-layerscape-gen4.c
> @@ -0,0 +1,254 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * PCIe host controller driver for NXP Layerscape SoCs
> + *
> + * Copyright 2018 NXP
> + *
> + * Author: Zhiqiang Hou
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include "pcie-mobiveil.h"
> +
> +/* LUT and PF control registers */
> +#define PCIE_LUT_OFF (0x8)
> +#define PCIE_PF_OFF(0xc)
> +#define PCIE_PF_INT_STAT (0x18)
> +#define PF_INT_STAT_PABRST (31)
> +
> +#define PCIE_PF_DBG(0x7fc)
> +#define PF_DBG_LTSSM_MASK (0x3f)
> +#define PF_DBG_WE (31)
> +#define PF_DBG_PABR(27)
> +
> +#define LS_PCIE_G4_LTSSM_L00x2d /* L0 state */
> +
> +#define to_ls_pcie_g4(x) platform_get_drvdata((x)->pdev)
> +
> +struct ls_pcie_g4 {
> + struct mobiveil_pcie *pci;
> + struct delayed_work dwork;
> + int irq;
> +};
> +
> +static inline u32 ls_pcie_g4_lut_readl(struct ls_pcie_g4 *pcie, u32 off)
> +{
> + return ioread32(pcie->pci->csr_axi_slave_base + PCIE_LUT_OFF + off);
> +}
> +
> +static inline void ls_pcie_g4_lut_writel(struct ls_pcie_g4 *pcie,
> +u32 off, u32 val)
> +{
> + iowrite32(val, pcie->pci->csr_axi_slave_base + PCIE_LUT_OFF + off);
> +}
> +
> +static inline u32 ls_pcie_g4_pf_readl(struct ls_pcie_g4 *pcie, u32 off)
> +{
> + return ioread32(pcie->pci->csr_axi_slave_base + PCIE_PF_OFF + off);
> +}
> +
> +static inline void ls_pcie_g4_pf_writel(struct ls_pcie_g4 *pcie,
> + u32 off, u32 val)
> +{
> + iowrite32(val, pcie->pci->csr_axi_slave_base + PCIE_PF_OFF + off);
> +}
> +
> +static bool ls_pcie_g4_is_bridge(struct ls_pcie_g4 *pcie)
> +{
> + struct mobiveil_pcie *mv_pci = pcie->pci;
> + u32 header_type;
> +
> + header_type = csr_readb(mv_pci, PCI_HEADER_TYPE);
> + header_type &= 0x7f;
> +
> + return header_type == PCI_HEADER_TYPE_BRIDGE;
> +}
> +
> +static int ls_pcie_g4_link_up(struct mobiveil_pcie *pci)
> +{
> + struct ls_pcie_g4 *pcie = to_ls_pcie_g4(pci);
> + u32 state;
> +
> + state = ls_pcie_g4_pf_readl(pcie, PCIE_PF_DBG);
> + state = state & PF_DBG_LTSSM_MASK;
> +
> + if (state == LS_PCIE_G4_LTSSM_L0)
> + return 1;
> +
> + return 0;
> +}
> +
> +static void ls_pcie_g4_reinit_hw(struct ls_pcie_g4 *pcie)
> +{
> + struct mobiveil_pcie *mv_pci = pcie->pci;
> + u32
Re: [PATCHv3 21/27] PCI: mobiveil: make mobiveil_host_init can be used to re-init host
ot_bus_nr;
> @@ -608,7 +612,7 @@ int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie)
> /* setup the kernel resources for the newly added PCIe root bus */
> ret = pci_scan_root_bus_bridge(bridge);
> if (ret)
> - goto error;
> + return ret;
>
> bus = bridge->bus;
>
> @@ -618,7 +622,4 @@ int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie)
> pci_bus_add_devices(bus);
>
> return 0;
> -error:
> - pci_free_resource_list(>resources);
> - return ret;
> }
> diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.h
> b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
> index 933c2f34bc52..0f5303962e88 100644
> --- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h
> +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
> @@ -152,7 +152,7 @@ struct mobiveil_pab_ops {
>
> struct mobiveil_pcie {
> struct platform_device *pdev;
> - struct list_head resources;
> + struct list_head *resources;
> void __iomem *csr_axi_slave_base; /* PAB registers base */
> phys_addr_t pcie_reg_base; /* Physical PCIe Controller Base */
> void __iomem *apb_csr_base; /* MSI register base */
> @@ -165,6 +165,7 @@ struct mobiveil_pcie {
> };
>
> int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie);
> +int mobiveil_host_init(struct mobiveil_pcie *pcie, bool reinit);
> bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie);
> int mobiveil_bringup_link(struct mobiveil_pcie *pcie);
> void program_ob_windows(struct mobiveil_pcie *pcie, int win_num, u64
> cpu_addr,
> --
> 2.17.1
>
Reviewed-by: Subrahmanya Lingappa
Re: [PATCHv3 20/27] PCI: mobiveil: add Byte and Half-Word width register accessors
On Tue, Jan 29, 2019 at 1:40 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> As there are some Byte and Half-Work width registers in PCIe
> configuration space, add Byte and Half-Word width register
> accessors.
>
> Signed-off-by: Hou Zhiqiang
> Reviewed-by: Minghuan Lian
> ---
> V3:
> - No change
>
> .../pci/controller/mobiveil/pcie-mobiveil.h | 20 +++
> 1 file changed, 20 insertions(+)
>
> diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.h
> b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
> index 81685840b378..933c2f34bc52 100644
> --- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h
> +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
> @@ -181,9 +181,29 @@ static inline u32 csr_readl(struct mobiveil_pcie *pcie,
> u32 off)
> return csr_read(pcie, off, 0x4);
> }
>
> +static inline u32 csr_readw(struct mobiveil_pcie *pcie, u32 off)
> +{
> + return csr_read(pcie, off, 0x2);
> +}
> +
> +static inline u32 csr_readb(struct mobiveil_pcie *pcie, u32 off)
> +{
> + return csr_read(pcie, off, 0x1);
> +}
> +
> static inline void csr_writel(struct mobiveil_pcie *pcie, u32 val, u32 off)
> {
> csr_write(pcie, val, off, 0x4);
> }
>
> +static inline void csr_writew(struct mobiveil_pcie *pcie, u32 val, u32 off)
> +{
> + csr_write(pcie, val, off, 0x2);
> +}
> +
> +static inline void csr_writeb(struct mobiveil_pcie *pcie, u32 val, u32 off)
> +{
> + csr_write(pcie, val, off, 0x1);
> +}
> +
> #endif /* _PCIE_MOBIVEIL_H */
> --
> 2.17.1
>
Reviewed-by: Subrahmanya Lingappa
Re: [PATCHv3 18/27] PCI: mobiveil: continue to initialize the host upon no PCIe link
On Tue, Jan 29, 2019 at 1:40 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> Sometimes there is not a PCIe Endpoint in the PCIe slot, so do
> not exit when the PCIe link is not up. And degrade the print
> level of link up info.
>
> Signed-off-by: Hou Zhiqiang
> Reviewed-by: Minghuan Lian
> ---
> V3:
> - No change
>
> drivers/pci/controller/mobiveil/pcie-mobiveil-host.c | 1 -
> drivers/pci/controller/mobiveil/pcie-mobiveil.c | 2 +-
> 2 files changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
> b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
> index 1ae82e790562..d1765d572f44 100644
> --- a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
> +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
> @@ -596,7 +596,6 @@ int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie)
> ret = mobiveil_bringup_link(pcie);
> if (ret) {
> dev_info(dev, "link bring-up failed\n");
> - goto error;
> }
>
> /* setup the kernel resources for the newly added PCIe root bus */
> diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.c
> b/drivers/pci/controller/mobiveil/pcie-mobiveil.c
> index ee678a60825d..370658d6546d 100644
> --- a/drivers/pci/controller/mobiveil/pcie-mobiveil.c
> +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.c
> @@ -222,7 +222,7 @@ int mobiveil_bringup_link(struct mobiveil_pcie *pcie)
> usleep_range(LINK_WAIT_MIN, LINK_WAIT_MAX);
> }
>
> - dev_err(>pdev->dev, "link never came up\n");
> + dev_info(>pdev->dev, "link never came up\n");
>
> return -ETIMEDOUT;
> }
> --
> 2.17.1
>
Reviewed-by: Subrahmanya Lingappa
Re: [PATCHv3 19/27] PCI: mobiveil: disabled IB and OB windows set by bootloader
On Tue, Jan 29, 2019 at 1:40 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> Disabled all inbound and outbound windows before set up the windows
> in kernel, in case transactions match the window set by bootloader.
>
> Signed-off-by: Hou Zhiqiang
> Reviewed-by: Minghuan Lian
> ---
> V3:
> - No change
>
> .../controller/mobiveil/pcie-mobiveil-host.c | 7 +++
> .../pci/controller/mobiveil/pcie-mobiveil.c| 18 ++
> .../pci/controller/mobiveil/pcie-mobiveil.h| 2 ++
> 3 files changed, 27 insertions(+)
>
> diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
> b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
> index d1765d572f44..d028cdf31d0e 100644
> --- a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
> +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
> @@ -221,6 +221,13 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
> {
> u32 value, pab_ctrl, type;
> struct resource_entry *win;
> + int i;
> +
> + /* Disable all inbound/outbound windows */
> + for (i = 0; i < pcie->apio_wins; i++)
> + mobiveil_pcie_disable_ob_win(pcie, i);
> + for (i = 0; i < pcie->ppio_wins; i++)
> + mobiveil_pcie_disable_ib_win(pcie, i);
>
> /* setup bus numbers */
> value = csr_readl(pcie, PCI_PRIMARY_BUS);
> diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.c
> b/drivers/pci/controller/mobiveil/pcie-mobiveil.c
> index 370658d6546d..49d471b75925 100644
> --- a/drivers/pci/controller/mobiveil/pcie-mobiveil.c
> +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.c
> @@ -226,3 +226,21 @@ int mobiveil_bringup_link(struct mobiveil_pcie *pcie)
>
> return -ETIMEDOUT;
> }
> +
> +void mobiveil_pcie_disable_ib_win(struct mobiveil_pcie *pci, int win_num)
> +{
> + u32 val;
> +
> + val = csr_readl(pci, PAB_PEX_AMAP_CTRL(win_num));
> + val &= ~(1 << AMAP_CTRL_EN_SHIFT);
> + csr_writel(pci, val, PAB_PEX_AMAP_CTRL(win_num));
> +}
> +
> +void mobiveil_pcie_disable_ob_win(struct mobiveil_pcie *pci, int win_num)
> +{
> + u32 val;
> +
> + val = csr_readl(pci, PAB_AXI_AMAP_CTRL(win_num));
> + val &= ~(1 << WIN_ENABLE_SHIFT);
> + csr_writel(pci, val, PAB_AXI_AMAP_CTRL(win_num));
> +}
> diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.h
> b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
> index eb4cb61291a8..81685840b378 100644
> --- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h
> +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
> @@ -171,6 +171,8 @@ void program_ob_windows(struct mobiveil_pcie *pcie, int
> win_num, u64 cpu_addr,
> u64 pci_addr, u32 type, u64 size);
> void program_ib_windows(struct mobiveil_pcie *pcie, int win_num, u64
> cpu_addr,
> u64 pci_addr, u32 type, u64 size);
> +void mobiveil_pcie_disable_ob_win(struct mobiveil_pcie *pci, int win_num);
> +void mobiveil_pcie_disable_ib_win(struct mobiveil_pcie *pci, int win_num);
> u32 csr_read(struct mobiveil_pcie *pcie, u32 off, size_t size);
> void csr_write(struct mobiveil_pcie *pcie, u32 val, u32 off, size_t size);
>
> --
> 2.17.1
>
Reviewed-by: Subrahmanya Lingappa
Re: [PATCHv3 17/27] PCI: mobiveil: fix the checking of valid device
ZQ,
On Tue, Jan 29, 2019 at 1:40 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> Avoid to issue CFG transactions to link partner when the PCIe
> link is not up. And allow CFG transactions to all functions of
> Endpoint implemented multiple functions.
>
> Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host
> Bridge IP driver")
> Signed-off-by: Hou Zhiqiang
> Reviewed-by: Minghuan Lian
> ---
> V3:
> - No change
>
> drivers/pci/controller/mobiveil/pcie-mobiveil-host.c | 6 +-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
> b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
> index dc5324d94466..1ae82e790562 100644
> --- a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
> +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
> @@ -29,6 +29,10 @@ static bool mobiveil_pcie_valid_device(struct pci_bus
> *bus, unsigned int devfn)
> {
> struct mobiveil_pcie *pcie = bus->sysdata;
>
> + /* If there is no link, then there is no device */
> + if (bus->number > pcie->rp.root_bus_nr &&
> !mobiveil_pcie_link_up(pcie))
> + return false;
> +
> /* Only one device down on each root port */
> if ((bus->number == pcie->rp.root_bus_nr) && (devfn > 0))
> return false;
> @@ -37,7 +41,7 @@ static bool mobiveil_pcie_valid_device(struct pci_bus *bus,
> unsigned int devfn)
> * Do not read more than one device on the bus directly
> * attached to RC
> */
> - if ((bus->primary == pcie->rp.root_bus_nr) && (devfn > 0))
> + if ((bus->primary == pcie->rp.root_bus_nr) && (PCI_SLOT(devfn) > 0))
here change "primary" to "number", as it's a bug in the original driver too.
> return false;
>
> return true;
> --
> 2.17.1
>
Re: [PATCHv3 16/27] PCI: mobiveil: refactor Mobiveil PCIe Host Bridge IP driver
On Tue, Jan 29, 2019 at 1:40 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> As the Mobiveil PCIe controller support RC DAUL mode, and to
> make platforms which integrated the Mobiveil PCIe IP more easy
> to add their drivers, this patch moved the Mobiveil driver to
> a new directory 'drivers/pci/controller/mobiveil' and refactored
> it according to the abstraction of RC (EP driver will be added
> later).
>
> Signed-off-by: Hou Zhiqiang
> Reviewed-by: Minghuan Lian
> ---
> V3:
> - No change
>
> MAINTAINERS | 2 +-
> drivers/pci/controller/Kconfig| 11 +-
> drivers/pci/controller/Makefile | 2 +-
> drivers/pci/controller/mobiveil/Kconfig | 24 +
> drivers/pci/controller/mobiveil/Makefile | 4 +
> .../pcie-mobiveil-host.c} | 528 +++---
> .../controller/mobiveil/pcie-mobiveil-plat.c | 54 ++
> .../pci/controller/mobiveil/pcie-mobiveil.c | 228
> .../pci/controller/mobiveil/pcie-mobiveil.h | 187 +++
> 9 files changed, 587 insertions(+), 453 deletions(-)
> create mode 100644 drivers/pci/controller/mobiveil/Kconfig
> create mode 100644 drivers/pci/controller/mobiveil/Makefile
> rename drivers/pci/controller/{pcie-mobiveil.c =>
> mobiveil/pcie-mobiveil-host.c} (55%)
> create mode 100644 drivers/pci/controller/mobiveil/pcie-mobiveil-plat.c
> create mode 100644 drivers/pci/controller/mobiveil/pcie-mobiveil.c
> create mode 100644 drivers/pci/controller/mobiveil/pcie-mobiveil.h
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index ddcdc29dfe1f..3bca9642b08b 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -11709,7 +11709,7 @@ M: Subrahmanya Lingappa
>
> L: linux-...@vger.kernel.org
> S: Supported
> F: Documentation/devicetree/bindings/pci/mobiveil-pcie.txt
> -F: drivers/pci/controller/pcie-mobiveil.c
> +F: drivers/pci/controller/mobiveil/pcie-mobiveil*
>
> PCI DRIVER FOR MVEBU (Marvell Armada 370 and Armada XP SOC support)
> M: Thomas Petazzoni
> diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
> index 6671946dbf66..0e981ed00a75 100644
> --- a/drivers/pci/controller/Kconfig
> +++ b/drivers/pci/controller/Kconfig
> @@ -241,16 +241,6 @@ config PCIE_MEDIATEK
> Say Y here if you want to enable PCIe controller support on
> MediaTek SoCs.
>
> -config PCIE_MOBIVEIL
> - bool "Mobiveil AXI PCIe controller"
> - depends on ARCH_ZYNQMP || COMPILE_TEST
> - depends on OF
> - depends on PCI_MSI_IRQ_DOMAIN
> - help
> - Say Y here if you want to enable support for the Mobiveil AXI PCIe
> - Soft IP. It has up to 8 outbound and inbound windows
> - for address translation and it is a PCIe Gen4 IP.
> -
> config PCIE_TANGO_SMP8759
> bool "Tango SMP8759 PCIe controller (DANGEROUS)"
> depends on ARCH_TANGO && PCI_MSI && OF
> @@ -281,4 +271,5 @@ config VMD
> module will be called vmd.
>
> source "drivers/pci/controller/dwc/Kconfig"
> +source "drivers/pci/controller/mobiveil/Kconfig"
> endmenu
> diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile
> index d56a507495c5..b79a615041a0 100644
> --- a/drivers/pci/controller/Makefile
> +++ b/drivers/pci/controller/Makefile
> @@ -26,11 +26,11 @@ obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o
> obj-$(CONFIG_PCIE_ROCKCHIP_EP) += pcie-rockchip-ep.o
> obj-$(CONFIG_PCIE_ROCKCHIP_HOST) += pcie-rockchip-host.o
> obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
> -obj-$(CONFIG_PCIE_MOBIVEIL) += pcie-mobiveil.o
> obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
> obj-$(CONFIG_VMD) += vmd.o
> # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW
> obj-y += dwc/
> +obj-y += mobiveil/
>
>
> # The following drivers are for devices that use the generic ACPI
> diff --git a/drivers/pci/controller/mobiveil/Kconfig
> b/drivers/pci/controller/mobiveil/Kconfig
> new file mode 100644
> index ..64343c07bfed
> --- /dev/null
> +++ b/drivers/pci/controller/mobiveil/Kconfig
> @@ -0,0 +1,24 @@
> +# SPDX-License-Identifier: GPL-2.0
> +
> +menu "Mobiveil PCIe Core Support"
> + depends on PCI
> +
> +config PCIE_MOBIVEIL
> + bool
> +
> +config PCIE_MOBIVEIL_HOST
> +bool
> + depends on PCI_MSI_IRQ_DOMAIN
> +select PCIE_MOBIVEIL
> +
> +config PCIE_MOBIVEIL_PLAT
> + bool "Mobiveil AXI PCIe controller"
> + depends on ARCH_ZYNQMP || COMPILE_TEST
> + depe
Re: [PATCHv3 14/27] PCI: mobiveil: initialize Primary/Secondary/Subordinate bus number
On Tue, Jan 29, 2019 at 1:40 PM Z.q. Hou wrote: > > From: Hou Zhiqiang > > The reset value is all zero, so set a workable value for Primary, > Secondary and Subordinate bus numbers. > > Signed-off-by: Hou Zhiqiang > Reviewed-by: Minghuan Lian > --- > V3: > - No change > > drivers/pci/controller/pcie-mobiveil.c | 6 ++ > 1 file changed, 6 insertions(+) > > diff --git a/drivers/pci/controller/pcie-mobiveil.c > b/drivers/pci/controller/pcie-mobiveil.c > index db7ecb021c63..9210165fe8c0 100644 > --- a/drivers/pci/controller/pcie-mobiveil.c > +++ b/drivers/pci/controller/pcie-mobiveil.c > @@ -582,6 +582,12 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie) > u32 value, pab_ctrl, type; > struct resource_entry *win; > > + /* setup bus numbers */ > + value = csr_readl(pcie, PCI_PRIMARY_BUS); > + value &= 0xff00; > + value |= 0x00ff0100; > + csr_writel(pcie, value, PCI_PRIMARY_BUS); > + > /* > * program Bus Master Enable Bit in Command Register in PAB Config > * Space > -- > 2.17.1 > Reviewed-by: Subrahmanya Lingappa
Re: [PATCHv3 15/27] dt-bindings: pci: mobiveil: change gpio_slave and apb_csr to optional
On Tue, Jan 29, 2019 at 1:40 PM Z.q. Hou wrote: > > From: Hou Zhiqiang > > Change the "gpio_slave" and "apb_csr" to optional, the "gpio_slave" > is not used in current code, and "apb_csr" is not used by some > platforms. > > Signed-off-by: Hou Zhiqiang > Acked-by: Subrahmanya Lingappa > Acked-by: Rob Herring > Reviewed-by: Minghuan Lian > --- > V3: > - No change > > Documentation/devicetree/bindings/pci/mobiveil-pcie.txt | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/mobiveil-pcie.txt > b/Documentation/devicetree/bindings/pci/mobiveil-pcie.txt > index a618d4787dd7..64156993e052 100644 > --- a/Documentation/devicetree/bindings/pci/mobiveil-pcie.txt > +++ b/Documentation/devicetree/bindings/pci/mobiveil-pcie.txt > @@ -10,8 +10,10 @@ Required properties: > interrupt source. The value must be 1. > - compatible: Should contain "mbvl,gpex40-pcie" > - reg: Should contain PCIe registers location and length > + Mandatory: > "config_axi_slave": PCIe controller registers > "csr_axi_slave" : Bridge config registers > + Optional: > "gpio_slave" : GPIO registers to control slot power > "apb_csr" : MSI registers > > -- > 2.17.1 > Reviewed-by: Subrahmanya Lingappa
Re: [PATCHv3 13/27] PCI: mobiveil: move irq chained handler setup out of DT parse
On Tue, Jan 29, 2019 at 1:39 PM Z.q. Hou wrote: > > From: Hou Zhiqiang > > Move irq_set_chained_handler_and_data() out of DT parse function. > > Signed-off-by: Hou Zhiqiang > Reviewed-by: Minghuan Lian > --- > V3: > - No change > > drivers/pci/controller/pcie-mobiveil.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/pci/controller/pcie-mobiveil.c > b/drivers/pci/controller/pcie-mobiveil.c > index c2848c22b466..db7ecb021c63 100644 > --- a/drivers/pci/controller/pcie-mobiveil.c > +++ b/drivers/pci/controller/pcie-mobiveil.c > @@ -460,8 +460,6 @@ static int mobiveil_pcie_parse_dt(struct mobiveil_pcie > *pcie) > return -ENODEV; > } > > - irq_set_chained_handler_and_data(pcie->irq, mobiveil_pcie_isr, pcie); > - > return 0; > } > > @@ -902,6 +900,8 @@ static int mobiveil_pcie_probe(struct platform_device > *pdev) > goto error; > } > > + irq_set_chained_handler_and_data(pcie->irq, mobiveil_pcie_isr, pcie); > + > ret = devm_request_pci_bus_resources(dev, >resources); > if (ret) > goto error; > -- > 2.17.1 > Reviewed-by: Subrahmanya Lingappa
Re: [PATCHv3 01/27] PCI: mobiveil: uniform the register accessors
Lorenzo,
On Tue, Feb 5, 2019 at 11:13 PM Lorenzo Pieralisi
wrote:
>
> On Tue, Feb 05, 2019 at 11:09:19AM +0530, Subrahmanya Lingappa wrote:
> > Reviewed-by: Subrahmanya Lingappa
>
> I have a feeling you do not read what I write.
My apologies, I do read. I am new to reviewing process and trying to learn here.
>
> Please never top-post.
>
I'll make sure not to top-post now on-wards.
>
> Read this, especially the email etiquette section:
>
> https://kernelnewbies.org/PatchCulture
>
I read it.
Thank you.
> >
> >
> >
> > On Tue, Jan 29, 2019 at 1:38 PM Z.q. Hou wrote:
> > >
> > > From: Hou Zhiqiang
> > >
> > > It's confused that R/W some registers by csr_readl()/csr_writel(),
> > > while others by read_paged_register()/write_paged_register().
> > > Actually the low 3KB of 4KB PCIe configure space can be accessed
> > > directly and high 1KB is paging area. So this patch uniformed the
> > > register accessors to csr_readl() and csr_writel() by comparing
> > > the register offset with page access boundary 3KB in the accessor
> > > internal.
> > >
> > > Signed-off-by: Hou Zhiqiang
> > > Reviewed-by: Minghuan Lian
> > > ---
> > > V3:
> > > - No change
> > >
> > > drivers/pci/controller/pcie-mobiveil.c | 179 +
> > > 1 file changed, 124 insertions(+), 55 deletions(-)
> > >
> > > diff --git a/drivers/pci/controller/pcie-mobiveil.c
> > > b/drivers/pci/controller/pcie-mobiveil.c
> > > index 77052a0712d0..d55c7e780c6e 100644
> > > --- a/drivers/pci/controller/pcie-mobiveil.c
> > > +++ b/drivers/pci/controller/pcie-mobiveil.c
> > > @@ -47,7 +47,6 @@
> > > #define PAGE_SEL_SHIFT13
> > > #define PAGE_SEL_MASK 0x3f
> > > #define PAGE_LO_MASK 0x3ff
> > > -#define PAGE_SEL_EN 0xc00
> > > #define PAGE_SEL_OFFSET_SHIFT 10
> > >
> > > #define PAB_AXI_PIO_CTRL 0x0840
> > > @@ -117,6 +116,12 @@
> > > #define LINK_WAIT_MIN 9
> > > #define LINK_WAIT_MAX 10
> > >
> > > +#define PAGED_ADDR_BNDRY 0xc00
> > > +#define OFFSET_TO_PAGE_ADDR(off) \
> > > + ((off & PAGE_LO_MASK) | PAGED_ADDR_BNDRY)
> > > +#define OFFSET_TO_PAGE_IDX(off)\
> > > + ((off >> PAGE_SEL_OFFSET_SHIFT) & PAGE_SEL_MASK)
> > > +
> > > struct mobiveil_msi { /* MSI information */
> > > struct mutex lock; /* protect bitmap variable */
> > > struct irq_domain *msi_domain;
> > > @@ -145,15 +150,119 @@ struct mobiveil_pcie {
> > > struct mobiveil_msi msi;
> > > };
> > >
> > > -static inline void csr_writel(struct mobiveil_pcie *pcie, const u32
> > > value,
> > > - const u32 reg)
> > > +/*
> > > + * mobiveil_pcie_sel_page - routine to access paged register
> > > + *
> > > + * Registers whose address greater than PAGED_ADDR_BNDRY (0xc00) are
> > > paged,
> > > + * for this scheme to work extracted higher 6 bits of the offset will be
> > > + * written to pg_sel field of PAB_CTRL register and rest of the lower 10
> > > + * bits enabled with PAGED_ADDR_BNDRY are used as offset of the register.
> > > + */
> > > +static void mobiveil_pcie_sel_page(struct mobiveil_pcie *pcie, u8 pg_idx)
> > > {
> > > - writel_relaxed(value, pcie->csr_axi_slave_base + reg);
> > > + u32 val;
> > > +
> > > + val = readl(pcie->csr_axi_slave_base + PAB_CTRL);
> > > + val &= ~(PAGE_SEL_MASK << PAGE_SEL_SHIFT);
> > > + val |= (pg_idx & PAGE_SEL_MASK) << PAGE_SEL_SHIFT;
> > > +
> > > + writel(val, pcie->csr_axi_slave_base + PAB_CTRL);
> > > }
> > >
> > > -static inline u32 csr_readl(struct mobiveil_pcie *pcie, const u32 reg)
> > > +static void *mobiveil_pcie_comp_addr(struct mobiveil_pcie *pcie, u32 off)
> > > {
> > > - return readl_relaxed(pcie->csr_axi_slave_base + reg);
> > > + if (off < PAGED_ADDR_BNDRY) {
> > > + /* For directly accessed registers, clear the pg_sel
> > > field */
> > > + mobiveil_pcie_sel_page(pcie, 0);
> > > + return pcie->csr_axi_slave_base + off;
> > > + }
> > > +
> > &g
Re: [PATCHv3 11/27] PCI: mobiveil: only fix up the Class Code field
Reviewed-by: Subrahmanya Lingappa
On Tue, Jan 29, 2019 at 1:39 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> Fix up the Class Code to PCI bridge, do not change the Revision ID.
> And move the fixup to mobiveil_host_init function.
>
> Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge
> IP driver")
> Signed-off-by: Hou Zhiqiang
> Reviewed-by: Minghuan Lian
> ---
> V3:
> - No change
>
> drivers/pci/controller/pcie-mobiveil.c | 9 ++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/pci/controller/pcie-mobiveil.c
> b/drivers/pci/controller/pcie-mobiveil.c
> index 78e575e71f4d..8eee1ab7ee24 100644
> --- a/drivers/pci/controller/pcie-mobiveil.c
> +++ b/drivers/pci/controller/pcie-mobiveil.c
> @@ -653,6 +653,12 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
>type, resource_size(win->res));
> }
>
> + /* fixup for PCIe class register */
> + value = csr_readl(pcie, PAB_INTP_AXI_PIO_CLASS);
> + value &= 0xff;
> + value |= (PCI_CLASS_BRIDGE_PCI << 16);
> + csr_writel(pcie, value, PAB_INTP_AXI_PIO_CLASS);
> +
> /* setup MSI hardware registers */
> mobiveil_pcie_enable_msi(pcie);
>
> @@ -896,9 +902,6 @@ static int mobiveil_pcie_probe(struct platform_device
> *pdev)
> goto error;
> }
>
> - /* fixup for PCIe class register */
> - csr_writel(pcie, 0x060402ab, PAB_INTP_AXI_PIO_CLASS);
> -
> /* initialize the IRQ domains */
> ret = mobiveil_pcie_init_irq_domain(pcie);
> if (ret) {
> --
> 2.17.1
>
Re: [PATCHv3 12/27] PCI: mobiveil: move out the link up waiting from mobiveil_host_init
Reviewed-by: Subrahmanya Lingappa
On Tue, Jan 29, 2019 at 1:39 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> Host initial sequence does not depend on PCIe link up, so move it
> to the place just before the enumeration.
>
> Signed-off-by: Hou Zhiqiang
> Reviewed-by: Minghuan Lian
> ---
> V3:
> - No change
>
> drivers/pci/controller/pcie-mobiveil.c | 15 +++
> 1 file changed, 7 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/pci/controller/pcie-mobiveil.c
> b/drivers/pci/controller/pcie-mobiveil.c
> index 8eee1ab7ee24..c2848c22b466 100644
> --- a/drivers/pci/controller/pcie-mobiveil.c
> +++ b/drivers/pci/controller/pcie-mobiveil.c
> @@ -582,15 +582,8 @@ static void mobiveil_pcie_enable_msi(struct
> mobiveil_pcie *pcie)
> static int mobiveil_host_init(struct mobiveil_pcie *pcie)
> {
> u32 value, pab_ctrl, type;
> - int err;
> struct resource_entry *win;
>
> - err = mobiveil_bringup_link(pcie);
> - if (err) {
> - dev_info(>pdev->dev, "link bring-up failed\n");
> - return err;
> - }
> -
> /*
> * program Bus Master Enable Bit in Command Register in PAB Config
> * Space
> @@ -662,7 +655,7 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
> /* setup MSI hardware registers */
> mobiveil_pcie_enable_msi(pcie);
>
> - return err;
> + return 0;
> }
>
> static void mobiveil_mask_intx_irq(struct irq_data *data)
> @@ -922,6 +915,12 @@ static int mobiveil_pcie_probe(struct platform_device
> *pdev)
> bridge->map_irq = of_irq_parse_and_map_pci;
> bridge->swizzle_irq = pci_common_swizzle;
>
> + ret = mobiveil_bringup_link(pcie);
> + if (ret) {
> + dev_info(dev, "link bring-up failed\n");
> + goto error;
> + }
> +
> /* setup the kernel resources for the newly added PCIe root bus */
> ret = pci_scan_root_bus_bridge(bridge);
> if (ret)
> --
> 2.17.1
>
Re: [PATCHv3 10/27] PCI: mobiveil: fix the INTx process error
Reviewed-by: Subrahmanya Lingappa
On Tue, Jan 29, 2019 at 1:39 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> In the loop block, there is not code change the loop key,
> this patch updated the loop key by re-read the INTx status
> register.
>
> This patch also change to clear the handled INTx status.
>
> Note: Need MV to test this fix.
>
> Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host
> Bridge IP driver")
> Signed-off-by: Hou Zhiqiang
> Reviewed-by: Minghuan Lian
> ---
> V3:
> - No change
>
> drivers/pci/controller/pcie-mobiveil.c | 13 +
> 1 file changed, 9 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/pci/controller/pcie-mobiveil.c
> b/drivers/pci/controller/pcie-mobiveil.c
> index 4ba458474e42..78e575e71f4d 100644
> --- a/drivers/pci/controller/pcie-mobiveil.c
> +++ b/drivers/pci/controller/pcie-mobiveil.c
> @@ -361,6 +361,7 @@ static void mobiveil_pcie_isr(struct irq_desc *desc)
> /* Handle INTx */
> if (intr_status & PAB_INTP_INTX_MASK) {
> shifted_status = csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT);
> + shifted_status &= PAB_INTP_INTX_MASK;
> shifted_status >>= PAB_INTX_START;
> do {
> for_each_set_bit(bit, _status, PCI_NUM_INTX) {
> @@ -372,12 +373,16 @@ static void mobiveil_pcie_isr(struct irq_desc *desc)
> dev_err_ratelimited(dev, "unexpected
> IRQ, INT%d\n",
> bit);
>
> - /* clear interrupt */
> - csr_writel(pcie,
> - shifted_status << PAB_INTX_START,
> + /* clear interrupt handled */
> + csr_writel(pcie, 1 << (PAB_INTX_START + bit),
>PAB_INTP_AMBA_MISC_STAT);
> }
> - } while ((shifted_status >> PAB_INTX_START) != 0);
> +
> + shifted_status = csr_readl(pcie,
> + PAB_INTP_AMBA_MISC_STAT);
> + shifted_status &= PAB_INTP_INTX_MASK;
> + shifted_status >>= PAB_INTX_START;
> + } while (shifted_status != 0);
> }
>
> /* read extra MSI status register */
> --
> 2.17.1
>
Re: [PATCHv3 09/27] PCI: mobiveil: correct inbound/outbound window setup routines
ZQ,
please correct the tab spacing of the macro definitions, otherwise its OK.
Reviewed-by: Subrahmanya Lingappa
On Tue, Jan 29, 2019 at 1:39 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> Outbound window routine:
> - Removed unused var definition and register read operations.
> - Added the upper 32-bit cpu address setup of the window.
> - Instead of blindly write, only change the fields specified.
> - Masked the lower bits of window size in case override the
>control bits.
> - Check if the passing window number is available, instead of
>the total number of the initialized windows.
>
> Inbound window routine:
> - Added parameter 'u64 cpu_addr' to specify the cpu address
>of the window instead of using 'pci_addr'.
> - Changed 'int pci_addr' to 'u64 pci_addr', and added setup
>of the upper 32-bit pci address of the window.
> - Moved the PCIe PIO master enablement to mobiveil_host_init().
> - Instead of blindly write, only change the fields specified.
> - Masked the lower bits of window size in case override the
>control bits.
> - Check if the passing window number is available, instead of
>the total number of the initialized windows.
> - And added the statistic of initialized inbound windows.
>
> Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host
> Bridge IP driver")
> Signed-off-by: Hou Zhiqiang
> Reviewed-by: Minghuan Lian
> ---
> V3:
> - No change
>
> drivers/pci/controller/pcie-mobiveil.c | 70 +++---
> 1 file changed, 42 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/pci/controller/pcie-mobiveil.c
> b/drivers/pci/controller/pcie-mobiveil.c
> index e88afc792a5c..4ba458474e42 100644
> --- a/drivers/pci/controller/pcie-mobiveil.c
> +++ b/drivers/pci/controller/pcie-mobiveil.c
> @@ -65,9 +65,13 @@
> #define PAB_AXI_AMAP_CTRL(win) PAB_REG_ADDR(0x0ba0, win)
> #define WIN_ENABLE_SHIFT 0
> #define WIN_TYPE_SHIFT1
> +#define WIN_TYPE_MASK 0x3
> +#define WIN_SIZE_SHIFT10
> +#define WIN_SIZE_MASK 0x3f
>
> #define PAB_EXT_AXI_AMAP_SIZE(win) PAB_EXT_REG_ADDR(0xbaf0, win)
>
> +#define PAB_EXT_AXI_AMAP_AXI_WIN(win) PAB_EXT_REG_ADDR(0x80a0, win)
> #define PAB_AXI_AMAP_AXI_WIN(win) PAB_REG_ADDR(0x0ba4, win)
> #define AXI_WINDOW_ALIGN_MASK 3
>
> @@ -82,8 +86,10 @@
> #define PAB_PEX_AMAP_CTRL(win) PAB_REG_ADDR(0x4ba0, win)
> #define AMAP_CTRL_EN_SHIFT0
> #define AMAP_CTRL_TYPE_SHIFT 1
> +#define AMAP_CTRL_TYPE_MASK 3
>
> #define PAB_EXT_PEX_AMAP_SIZEN(win)PAB_EXT_REG_ADDR(0xbef0, win)
> +#define PAB_EXT_PEX_AMAP_AXI_WIN(win) PAB_EXT_REG_ADDR(0xb4a0, win)
> #define PAB_PEX_AMAP_AXI_WIN(win) PAB_REG_ADDR(0x4ba4, win)
> #define PAB_PEX_AMAP_PEX_WIN_L(win)PAB_REG_ADDR(0x4ba8, win)
> #define PAB_PEX_AMAP_PEX_WIN_H(win)PAB_REG_ADDR(0x4bac, win)
> @@ -455,49 +461,51 @@ static int mobiveil_pcie_parse_dt(struct mobiveil_pcie
> *pcie)
> }
>
> static void program_ib_windows(struct mobiveil_pcie *pcie, int win_num,
> - int pci_addr, u32 type, u64 size)
> + u64 cpu_addr, u64 pci_addr, u32 type, u64 size)
> {
> - int pio_ctrl_val;
> - int amap_ctrl_dw;
> + u32 value;
> u64 size64 = ~(size - 1);
>
> - if ((pcie->ib_wins_configured + 1) > pcie->ppio_wins) {
> + if (win_num >= pcie->ppio_wins) {
> dev_err(>pdev->dev,
> "ERROR: max inbound windows reached !\n");
> return;
> }
>
> - pio_ctrl_val = csr_readl(pcie, PAB_PEX_PIO_CTRL);
> - pio_ctrl_val |= 1 << PIO_ENABLE_SHIFT;
> - csr_writel(pcie, pio_ctrl_val, PAB_PEX_PIO_CTRL);
> -
> - amap_ctrl_dw = csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num));
> - amap_ctrl_dw |= (type << AMAP_CTRL_TYPE_SHIFT) |
> - (1 << AMAP_CTRL_EN_SHIFT) |
> - lower_32_bits(size64);
> - csr_writel(pcie, amap_ctrl_dw, PAB_PEX_AMAP_CTRL(win_num));
> + value = csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num));
> + value &= ~(AMAP_CTRL_TYPE_MASK << AMAP_CTRL_TYPE_SHIFT |
> +WIN_SIZE_MASK << WIN_SIZE_SHIFT);
> + value |= (type << AMAP_CTRL_TYPE_SHIFT) | (1 << AMAP_CTRL_EN_SHIFT) |
> +(lower_32_bits(size64) & WIN_SIZE_MASK << WIN_SIZE_SHIFT);
> + csr_writel(pcie, value, PAB_PEX_AMAP_CTRL(win_num));
>
> csr_writel(pcie, upper_32_b
Re: [PATCHv3 08/27] PCI: mobiveil: use the 1st inbound window for MEM inbound transactions
Reviewed-by: Subrahmanya Lingappa
On Tue, Jan 29, 2019 at 1:39 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> The inbound windows have different register set with outbound windows.
> This patch change the MEM inbound window to the first one.
>
> Signed-off-by: Hou Zhiqiang
> Reviewed-by: Minghuan Lian
> ---
> V3:
> - No change
>
> drivers/pci/controller/pcie-mobiveil.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/pcie-mobiveil.c
> b/drivers/pci/controller/pcie-mobiveil.c
> index df71c11b4810..e88afc792a5c 100644
> --- a/drivers/pci/controller/pcie-mobiveil.c
> +++ b/drivers/pci/controller/pcie-mobiveil.c
> @@ -616,7 +616,7 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
>CFG_WINDOW_TYPE, resource_size(pcie->ob_io_res));
>
> /* memory inbound translation window */
> - program_ib_windows(pcie, WIN_NUM_1, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE);
> + program_ib_windows(pcie, WIN_NUM_0, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE);
>
> /* Get the I/O and memory ranges from DT */
> resource_list_for_each_entry(win, >resources) {
> --
> 2.17.1
>
Re: [PATCHv3 07/27] PCI: mobiveil: use WIN_NUM_0 explicitly for CFG outbound window
Reviewed-by: Subrahmanya Lingappa On Tue, Jan 29, 2019 at 1:39 PM Z.q. Hou wrote: > > From: Hou Zhiqiang > > As the .map_bus() use the WIN_NUM_0 for CFG transactions, > it's better passing WIN_NUM_0 explicitly when initialize > the CFG outbound window. > > Signed-off-by: Hou Zhiqiang > Reviewed-by: Minghuan Lian > --- > V3: > - No change > > drivers/pci/controller/pcie-mobiveil.c | 5 ++--- > 1 file changed, 2 insertions(+), 3 deletions(-) > > diff --git a/drivers/pci/controller/pcie-mobiveil.c > b/drivers/pci/controller/pcie-mobiveil.c > index b2cc9c097fc9..df71c11b4810 100644 > --- a/drivers/pci/controller/pcie-mobiveil.c > +++ b/drivers/pci/controller/pcie-mobiveil.c > @@ -612,9 +612,8 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie) > */ > > /* config outbound translation window */ > - program_ob_windows(pcie, pcie->ob_wins_configured, > - pcie->ob_io_res->start, 0, CFG_WINDOW_TYPE, > - resource_size(pcie->ob_io_res)); > + program_ob_windows(pcie, WIN_NUM_0, pcie->ob_io_res->start, 0, > + CFG_WINDOW_TYPE, resource_size(pcie->ob_io_res)); > > /* memory inbound translation window */ > program_ib_windows(pcie, WIN_NUM_1, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE); > -- > 2.17.1 >
Re: [PATCHv3 06/27] PCI: mobiveil: replace the resource list iteration function
Reviewed-by: Subrahmanya Lingappa
On Tue, Jan 29, 2019 at 1:39 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> As it won't delete any node in this iteration, replaced
> the function resource_list_for_each_entry_safe() with
> the resource_list_for_each_entry().
>
> Signed-off-by: Hou Zhiqiang
> Reviewed-by: Minghuan Lian
> ---
> V3:
> - No change
>
> drivers/pci/controller/pcie-mobiveil.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pci/controller/pcie-mobiveil.c
> b/drivers/pci/controller/pcie-mobiveil.c
> index 8ff873023b5f..b2cc9c097fc9 100644
> --- a/drivers/pci/controller/pcie-mobiveil.c
> +++ b/drivers/pci/controller/pcie-mobiveil.c
> @@ -569,7 +569,7 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
> {
> u32 value, pab_ctrl, type;
> int err;
> - struct resource_entry *win, *tmp;
> + struct resource_entry *win;
>
> err = mobiveil_bringup_link(pcie);
> if (err) {
> @@ -620,7 +620,7 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
> program_ib_windows(pcie, WIN_NUM_1, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE);
>
> /* Get the I/O and memory ranges from DT */
> - resource_list_for_each_entry_safe(win, tmp, >resources) {
> + resource_list_for_each_entry(win, >resources) {
> if (resource_type(win->res) == IORESOURCE_MEM)
> type = MEM_WINDOW_TYPE;
> else if (resource_type(win->res) == IORESOURCE_IO)
> --
> 2.17.1
>
Re: [PATCHv3 05/27] PCI: mobiveil: correct PCI base address in MEM/IO outbound windows
Reviewed-by: Subrahmanya Lingappa
On Tue, Jan 29, 2019 at 1:39 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> It should get PCI base address from the DT node property 'ranges'
> to setup MEM/IO outbound windows instead of always zero.
>
> Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge
> IP driver")
> Signed-off-by: Hou Zhiqiang
> Reviewed-by: Minghuan Lian
> ---
> V3:
> - No change
>
> drivers/pci/controller/pcie-mobiveil.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pci/controller/pcie-mobiveil.c
> b/drivers/pci/controller/pcie-mobiveil.c
> index a0dd337c6214..8ff873023b5f 100644
> --- a/drivers/pci/controller/pcie-mobiveil.c
> +++ b/drivers/pci/controller/pcie-mobiveil.c
> @@ -630,8 +630,9 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
>
> /* configure outbound translation window */
> program_ob_windows(pcie, pcie->ob_wins_configured,
> - win->res->start, 0, type,
> - resource_size(win->res));
> + win->res->start,
> + win->res->start - win->offset,
> + type, resource_size(win->res));
> }
>
> /* setup MSI hardware registers */
> --
> 2.17.1
>
Re: [PATCHv3 04/27] PCI: mobiveil: remove flag MSI_FLAG_MULTI_PCI_MSI
Zhiqiang,
why are we removing multi-MSI support ?
what functionality this driver is not providing to support it ?
Thanks.
On Tue, Jan 29, 2019 at 1:38 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> The current code does not support multiple MSIs, so remove
> the corresponding flag from the msi_domain_info structure.
>
> Fixes: 1e913e58335f ("PCI: mobiveil: Add MSI support")
> Signed-off-by: Hou Zhiqiang
> Reviewed-by: Minghuan Lian
> ---
> V3:
> - No change
>
> drivers/pci/controller/pcie-mobiveil.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/pcie-mobiveil.c
> b/drivers/pci/controller/pcie-mobiveil.c
> index 563210e731d3..a0dd337c6214 100644
> --- a/drivers/pci/controller/pcie-mobiveil.c
> +++ b/drivers/pci/controller/pcie-mobiveil.c
> @@ -703,7 +703,7 @@ static struct irq_chip mobiveil_msi_irq_chip = {
>
> static struct msi_domain_info mobiveil_msi_domain_info = {
> .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
> - MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX),
> + MSI_FLAG_PCI_MSIX),
> .chip = _msi_irq_chip,
> };
>
> --
> 2.17.1
>
Re: [PATCHv3 03/27] PCI: mobiveil: correct the returned error number
Reviewed-by: Subrahmanya Lingappa
On Tue, Jan 29, 2019 at 1:38 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> This patch corrected the returned error number by convention,
> and removed a unnecessary error check.
>
> Signed-off-by: Hou Zhiqiang
> Reviewed-by: Minghuan Lian
> ---
> V3:
> - No change
>
> drivers/pci/controller/pcie-mobiveil.c | 8 +++-
> 1 file changed, 3 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/pci/controller/pcie-mobiveil.c
> b/drivers/pci/controller/pcie-mobiveil.c
> index b87471f08a40..563210e731d3 100644
> --- a/drivers/pci/controller/pcie-mobiveil.c
> +++ b/drivers/pci/controller/pcie-mobiveil.c
> @@ -819,7 +819,7 @@ static int mobiveil_pcie_init_irq_domain(struct
> mobiveil_pcie *pcie)
>
> if (!pcie->intx_domain) {
> dev_err(dev, "Failed to get a INTx IRQ domain\n");
> - return -ENODEV;
> + return -ENOMEM;
> }
>
> raw_spin_lock_init(>intx_mask_lock);
> @@ -845,11 +845,9 @@ static int mobiveil_pcie_probe(struct platform_device
> *pdev)
> /* allocate the PCIe port */
> bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
> if (!bridge)
> - return -ENODEV;
> + return -ENOMEM;
>
> pcie = pci_host_bridge_priv(bridge);
> - if (!pcie)
> - return -ENOMEM;
>
> pcie->pdev = pdev;
>
> @@ -866,7 +864,7 @@ static int mobiveil_pcie_probe(struct platform_device
> *pdev)
> >resources,
> );
> if (ret) {
> dev_err(dev, "Getting bridge resources failed\n");
> - return -ENOMEM;
> + return ret;
> }
>
> /*
> --
> 2.17.1
>
Re: [PATCHv3 02/27] PCI: mobiveil: format the code without function change
Zhiqiang, On Tue, Jan 29, 2019 at 1:38 PM Z.q. Hou wrote: > > From: Hou Zhiqiang > > Just format the code without functionality change. > > Signed-off-by: Hou Zhiqiang > Reviewed-by: Minghuan Lian > --- > V3: > - No change > > drivers/pci/controller/pcie-mobiveil.c | 261 + > 1 file changed, 137 insertions(+), 124 deletions(-) > > diff --git a/drivers/pci/controller/pcie-mobiveil.c > b/drivers/pci/controller/pcie-mobiveil.c > index d55c7e780c6e..b87471f08a40 100644 > --- a/drivers/pci/controller/pcie-mobiveil.c > +++ b/drivers/pci/controller/pcie-mobiveil.c > @@ -31,38 +31,40 @@ > * translation tables are grouped into windows, each window registers are > * grouped into blocks of 4 or 16 registers each > */ > -#define PAB_REG_BLOCK_SIZE 16 > -#define PAB_EXT_REG_BLOCK_SIZE 4 > +#define PAB_REG_BLOCK_SIZE 16 > +#define PAB_EXT_REG_BLOCK_SIZE 4 > > -#define PAB_REG_ADDR(offset, win) (offset + (win * PAB_REG_BLOCK_SIZE)) > -#define PAB_EXT_REG_ADDR(offset, win) (offset + (win * > PAB_EXT_REG_BLOCK_SIZE)) > +#define PAB_REG_ADDR(offset, win) \ > + (offset + (win * PAB_REG_BLOCK_SIZE)) > +#define PAB_EXT_REG_ADDR(offset, win) \ > + (offset + (win * PAB_EXT_REG_BLOCK_SIZE)) > > -#define LTSSM_STATUS 0x0404 > -#define LTSSM_STATUS_L0_MASK 0x3f > -#define LTSSM_STATUS_L0 0x2d > +#define LTSSM_STATUS 0x0404 > +#define LTSSM_STATUS_L0_MASK 0x3f > +#define LTSSM_STATUS_L0 0x2d > > -#define PAB_CTRL 0x0808 > -#define AMBA_PIO_ENABLE_SHIFT 0 > -#define PEX_PIO_ENABLE_SHIFT 1 > -#define PAGE_SEL_SHIFT13 > -#define PAGE_SEL_MASK 0x3f > -#define PAGE_LO_MASK 0x3ff > -#define PAGE_SEL_OFFSET_SHIFT 10 > +#define PAB_CTRL 0x0808 > +#define AMBA_PIO_ENABLE_SHIFT 0 > +#define PEX_PIO_ENABLE_SHIFT 1 > +#define PAGE_SEL_SHIFT13 above line seems to have an extra tab which makes it not aligned with lines above. > +#define PAGE_SEL_MASK 0x3f > +#define PAGE_LO_MASK 0x3ff > +#define PAGE_SEL_OFFSET_SHIFT 10 > > -#define PAB_AXI_PIO_CTRL 0x0840 > -#define APIO_EN_MASK 0xf > +#define PAB_AXI_PIO_CTRL 0x0840 > +#define APIO_EN_MASK 0xf > > -#define PAB_PEX_PIO_CTRL 0x08c0 > -#define PIO_ENABLE_SHIFT 0 > +#define PAB_PEX_PIO_CTRL 0x08c0 > +#define PIO_ENABLE_SHIFT 0 > > #define PAB_INTP_AMBA_MISC_ENB 0x0b0c > -#define PAB_INTP_AMBA_MISC_STAT0x0b1c > +#define PAB_INTP_AMBA_MISC_STAT0x0b1c > #define PAB_INTP_INTX_MASK0x01e0 > #define PAB_INTP_MSI_MASK 0x8 > > -#define PAB_AXI_AMAP_CTRL(win) PAB_REG_ADDR(0x0ba0, win) > -#define WIN_ENABLE_SHIFT 0 > -#define WIN_TYPE_SHIFT1 > +#define PAB_AXI_AMAP_CTRL(win) PAB_REG_ADDR(0x0ba0, win) > +#define WIN_ENABLE_SHIFT 0 > +#define WIN_TYPE_SHIFT1 please check the extra tab above > > #define PAB_EXT_AXI_AMAP_SIZE(win) PAB_EXT_REG_ADDR(0xbaf0, win) > > @@ -70,16 +72,16 @@ > #define AXI_WINDOW_ALIGN_MASK 3 > > #define PAB_AXI_AMAP_PEX_WIN_L(win)PAB_REG_ADDR(0x0ba8, win) > -#define PAB_BUS_SHIFT 24 > -#define PAB_DEVICE_SHIFT 19 > -#define PAB_FUNCTION_SHIFT16 > +#define PAB_BUS_SHIFT 24 > +#define PAB_DEVICE_SHIFT 19 > +#define PAB_FUNCTION_SHIFT16 > > #define PAB_AXI_AMAP_PEX_WIN_H(win)PAB_REG_ADDR(0x0bac, win) > #define PAB_INTP_AXI_PIO_CLASS 0x474 > > -#define PAB_PEX_AMAP_CTRL(win) PAB_REG_ADDR(0x4ba0, win) > -#define AMAP_CTRL_EN_SHIFT0 > -#define AMAP_CTRL_TYPE_SHIFT 1 > +#define PAB_PEX_AMAP_CTRL(win) PAB_REG_ADDR(0x4ba0, win) > +#define AMAP_CTRL_EN_SHIFT0 > +#define AMAP_CTRL_TYPE_SHIFT 1 > > #define PAB_EXT_PEX_AMAP_SIZEN(win)PAB_EXT_REG_ADDR(0xbef0, win) > #define PAB_PEX_AMAP_AXI_WIN(win) PAB_REG_ADDR(0x4ba4, win) > @@ -87,39 +89,39 @@ > #define PAB_PEX_AMAP_PEX_WIN_H(win)PAB_REG_ADDR(0x4bac, win) > > /* starting offset of INTX bits in status register */ > -#define PAB_INTX_START 5 > +#define PAB_INTX_START 5 > > /* supported number of MSI interrupts */ > -#define PCI_NUM_MSI16 > +#define PCI_NUM_MSI16 > > /* MSI registers */ > -#define MSI_BASE_LO_OFFSET 0x04 > -#define MSI_BASE_HI_OFFSET 0x08 > -#define MSI_SIZE_OFFSET0x0c > -#define MSI_ENABLE_OFFSET 0x14 > -#define MSI_STATUS_OFFSET 0x18 > -#define MSI_DATA_OFFSET0x20 > -#define MSI_ADDR_L_OFFSET 0x24 > -#define MSI_ADDR_H_OFFSET 0x28 > +#define MSI_BASE_LO_OFFSET 0x04 > +#define MSI_BASE_HI_OFFSET 0x08 > +#define MSI_SIZE_OFFSET0x0c > +#define
Re: [PATCHv3 01/27] PCI: mobiveil: uniform the register accessors
Reviewed-by: Subrahmanya Lingappa
On Tue, Jan 29, 2019 at 1:38 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> It's confused that R/W some registers by csr_readl()/csr_writel(),
> while others by read_paged_register()/write_paged_register().
> Actually the low 3KB of 4KB PCIe configure space can be accessed
> directly and high 1KB is paging area. So this patch uniformed the
> register accessors to csr_readl() and csr_writel() by comparing
> the register offset with page access boundary 3KB in the accessor
> internal.
>
> Signed-off-by: Hou Zhiqiang
> Reviewed-by: Minghuan Lian
> ---
> V3:
> - No change
>
> drivers/pci/controller/pcie-mobiveil.c | 179 +
> 1 file changed, 124 insertions(+), 55 deletions(-)
>
> diff --git a/drivers/pci/controller/pcie-mobiveil.c
> b/drivers/pci/controller/pcie-mobiveil.c
> index 77052a0712d0..d55c7e780c6e 100644
> --- a/drivers/pci/controller/pcie-mobiveil.c
> +++ b/drivers/pci/controller/pcie-mobiveil.c
> @@ -47,7 +47,6 @@
> #define PAGE_SEL_SHIFT13
> #define PAGE_SEL_MASK 0x3f
> #define PAGE_LO_MASK 0x3ff
> -#define PAGE_SEL_EN 0xc00
> #define PAGE_SEL_OFFSET_SHIFT 10
>
> #define PAB_AXI_PIO_CTRL 0x0840
> @@ -117,6 +116,12 @@
> #define LINK_WAIT_MIN 9
> #define LINK_WAIT_MAX 10
>
> +#define PAGED_ADDR_BNDRY 0xc00
> +#define OFFSET_TO_PAGE_ADDR(off) \
> + ((off & PAGE_LO_MASK) | PAGED_ADDR_BNDRY)
> +#define OFFSET_TO_PAGE_IDX(off)\
> + ((off >> PAGE_SEL_OFFSET_SHIFT) & PAGE_SEL_MASK)
> +
> struct mobiveil_msi { /* MSI information */
> struct mutex lock; /* protect bitmap variable */
> struct irq_domain *msi_domain;
> @@ -145,15 +150,119 @@ struct mobiveil_pcie {
> struct mobiveil_msi msi;
> };
>
> -static inline void csr_writel(struct mobiveil_pcie *pcie, const u32 value,
> - const u32 reg)
> +/*
> + * mobiveil_pcie_sel_page - routine to access paged register
> + *
> + * Registers whose address greater than PAGED_ADDR_BNDRY (0xc00) are paged,
> + * for this scheme to work extracted higher 6 bits of the offset will be
> + * written to pg_sel field of PAB_CTRL register and rest of the lower 10
> + * bits enabled with PAGED_ADDR_BNDRY are used as offset of the register.
> + */
> +static void mobiveil_pcie_sel_page(struct mobiveil_pcie *pcie, u8 pg_idx)
> {
> - writel_relaxed(value, pcie->csr_axi_slave_base + reg);
> + u32 val;
> +
> + val = readl(pcie->csr_axi_slave_base + PAB_CTRL);
> + val &= ~(PAGE_SEL_MASK << PAGE_SEL_SHIFT);
> + val |= (pg_idx & PAGE_SEL_MASK) << PAGE_SEL_SHIFT;
> +
> + writel(val, pcie->csr_axi_slave_base + PAB_CTRL);
> }
>
> -static inline u32 csr_readl(struct mobiveil_pcie *pcie, const u32 reg)
> +static void *mobiveil_pcie_comp_addr(struct mobiveil_pcie *pcie, u32 off)
> {
> - return readl_relaxed(pcie->csr_axi_slave_base + reg);
> + if (off < PAGED_ADDR_BNDRY) {
> + /* For directly accessed registers, clear the pg_sel field */
> + mobiveil_pcie_sel_page(pcie, 0);
> + return pcie->csr_axi_slave_base + off;
> + }
> +
> + mobiveil_pcie_sel_page(pcie, OFFSET_TO_PAGE_IDX(off));
> + return pcie->csr_axi_slave_base + OFFSET_TO_PAGE_ADDR(off);
> +}
> +
> +static int mobiveil_pcie_read(void __iomem *addr, int size, u32 *val)
> +{
> + if ((uintptr_t)addr & (size - 1)) {
> + *val = 0;
> + return PCIBIOS_BAD_REGISTER_NUMBER;
> + }
> +
> + switch (size) {
> + case 4:
> + *val = readl(addr);
> + break;
> + case 2:
> + *val = readw(addr);
> + break;
> + case 1:
> + *val = readb(addr);
> + break;
> + default:
> + *val = 0;
> + return PCIBIOS_BAD_REGISTER_NUMBER;
> + }
> +
> + return PCIBIOS_SUCCESSFUL;
> +}
> +
> +static int mobiveil_pcie_write(void __iomem *addr, int size, u32 val)
> +{
> + if ((uintptr_t)addr & (size - 1))
> + return PCIBIOS_BAD_REGISTER_NUMBER;
> +
> + switch (size) {
> + case 4:
> + writel(val, addr);
> + break;
> + case 2:
> + writew(val, addr);
> + break;
> + case 1:
> + writeb(val, addr);
> + break;
> + default:
> + return
Re: [PATCHv3 00/27] PCI: refactor Mobiveil driver and add PCIe Gen4 driver for NXP Layerscape SoCs
Lorenzo, My apologies again, I have started looking into these. Thanks, On Mon, Feb 4, 2019 at 9:43 PM Lorenzo Pieralisi wrote: > > On Mon, Feb 04, 2019 at 07:44:25PM +0530, Subrahmanya Lingappa wrote: > >Bjorn, > >My apologies, I was away for a while from this work. > >I am starting to review now. > > Hi, > > I am not Bjorn and as I told you before you should not reply > with html context (ie use plain text, the public lists will > reject your emails otherwise) and top-post. > > You are supposed to maintain this code, if you can't it is fine but I > should know because there are developers who are waiting for your > review, please understand. > > Thanks, > Lorenzo > > >Thanks, > >~subbu > >On Tue, Jan 29, 2019 at 5:09 PM Lorenzo Pieralisi > > wrote: > > > > On Tue, Jan 29, 2019 at 08:08:28AM +, Z.q. Hou wrote: > > > From: Hou Zhiqiang > > > > > > This patch set is aim to refactor the Mobiveil driver and add > > > PCIe support for NXP Layerscape series SoCs integrated Mobiveil's > > > PCIe Gen4 controller. > > > > > > Hou Zhiqiang (27): > > > PCI: mobiveil: uniform the register accessors > > > PCI: mobiveil: format the code without function change > > > PCI: mobiveil: correct the returned error number > > > PCI: mobiveil: remove flag MSI_FLAG_MULTI_PCI_MSI > > > PCI: mobiveil: correct PCI base address in MEM/IO outbound windows > > > PCI: mobiveil: replace the resource list iteration function > > > PCI: mobiveil: use WIN_NUM_0 explicitly for CFG outbound window > > > PCI: mobiveil: use the 1st inbound window for MEM inbound > > transactions > > > PCI: mobiveil: correct inbound/outbound window setup routines > > > PCI: mobiveil: fix the INTx process error > > > PCI: mobiveil: only fix up the Class Code field > > > PCI: mobiveil: move out the link up waiting from mobiveil_host_init > > > PCI: mobiveil: move irq chained handler setup out of DT parse > > > PCI: mobiveil: initialize Primary/Secondary/Subordinate bus number > > > dt-bindings: pci: mobiveil: change gpio_slave and apb_csr to > > optional > > > PCI: mobiveil: refactor Mobiveil PCIe Host Bridge IP driver > > > PCI: mobiveil: fix the checking of valid device > > > PCI: mobiveil: continue to initialize the host upon no PCIe link > > > PCI: mobiveil: disabled IB and OB windows set by bootloader > > > PCI: mobiveil: add Byte and Half-Word width register accessors > > > PCI: mobiveil: make mobiveil_host_init can be used to re-init host > > > dt-bindings: pci: Add NXP Layerscape SoCs PCIe Gen4 controller > > > PCI: mobiveil: add PCIe Gen4 RC driver for NXP Layerscape SoCs > > > PCI: mobiveil: ls_pcie_g4: add Workaround for A-011577 > > > PCI: mobiveil: ls_pcie_g4: add Workaround for A-011451 > > > arm64: dts: freescale: lx2160a: add pcie DT nodes > > > arm64: defconfig: Enable CONFIG_PCI_LAYERSCAPE_GEN4 > > > > Subrahmanya, > > > > Either you review this series or I will have to drop you from > > the MAINTAINERS list for this driver, I am sorry but I asked you > > before to no avail. > > > > Thanks, > > Lorenzo > > > > > .../bindings/pci/layerscape-pci-gen4.txt | 52 ++ > > > .../devicetree/bindings/pci/mobiveil-pcie.txt | 2 + > > > MAINTAINERS | 10 +- > > > .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 163 > > > arch/arm64/configs/defconfig | 1 + > > > drivers/pci/controller/Kconfig| 11 +- > > > drivers/pci/controller/Makefile | 2 +- > > > drivers/pci/controller/mobiveil/Kconfig | 34 + > > > drivers/pci/controller/mobiveil/Makefile | 5 + > > > .../controller/mobiveil/pci-layerscape-gen4.c | 306 +++ > > > .../controller/mobiveil/pcie-mobiveil-host.c | 640 + > > > .../controller/mobiveil/pcie-mobiveil-plat.c | 54 ++ > > > .../pci/controller/mobiveil/pcie-mobiveil.c | 246 + > > > .../pci/controller/mobiveil/pcie-mobiveil.h | 229 + > > > drivers/pci/controller/pcie-mobiveil.c| 861 > > -
Re: [PATCH 00/23] PCI: refactor the Mobiveil driver and add PCIe support for NXP LX SoCs
Lorenzo, You are right, I reviewed few DT files, will need some time to review this train. I will start doing it in a while. Thanks for pitching in. Thanks. On Mon, Dec 3, 2018 at 8:58 AM Lorenzo Pieralisi wrote: > > On Tue, Nov 06, 2018 at 01:19:03PM +, Z.q. Hou wrote: > > From: Hou Zhiqiang > > > > This patch set is aim to refactor the Mobiveil driver and add > > PCIe support for NXP LX series SoCs. > > > > Hou Zhiqiang (23): > > PCI: mobiveil: uniform the register accessors > > PCI: mobiveil: format the code without function change > > PCI: mobiveil: correct the returned error number > > PCI: mobiveil: remove flag MSI_FLAG_MULTI_PCI_MSI > > PCI: mobiveil: correct PCI base address in MEM/IO outbound windows > > PCI: mobiveil: replace the resource list iteration function > > PCI: mobiveil: use WIN_NUM_0 explicitly for CFG outbound window > > PCI: mobiveil: use the 1st inbound window for MEM inbound transactions > > PCI: mobiveil: correct the inbound/outbound window setup routine > > PCI: mobiveil: fix the INTx process error > > PCI: mobiveil: only fixup the Class Code field > > PCI: mobiveil: move out the link up waiting from mobiveil_host_init > > PCI: mobiveil: move irq chained handler setup out of DT parse > > PCI: mobiveil: initialize Primary/Secondary/Subordinate bus number > > dt-bindings: pci: mobiveil: change gpio_slave and apb_csr to optional > > PCI: mobiveil: refactor the Mobiveil driver > > PCI: mobiveil: continue to initialize the host upon no PCIe link > > PCI: mobiveil: disabled IB and OB windows set by bootloader > > PCI: mobiveil: add Byte and Half-Word width register accessors > > PCI: mobiveil: change prototype of function mobiveil_host_init > > dt-bindings: pci: Add NXP LX SoCs PCIe controller > > PCI: mobiveil: add PCIe RC driver for NXP LX series SoCs > > arm64: dts: freescale: lx2160a: add pcie DT nodes > > > > .../devicetree/bindings/pci/lx-pci.txt| 52 ++ > > .../devicetree/bindings/pci/mobiveil-pcie.txt | 2 + > > MAINTAINERS | 10 +- > > .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 157 > > drivers/pci/controller/Kconfig| 11 +- > > drivers/pci/controller/Makefile | 2 +- > > drivers/pci/controller/mobiveil/Kconfig | 34 + > > drivers/pci/controller/mobiveil/Makefile | 5 + > > drivers/pci/controller/mobiveil/pci-lx.c | 222 + > > .../controller/mobiveil/pcie-mobiveil-host.c | 622 + > > .../controller/mobiveil/pcie-mobiveil-plat.c | 54 ++ > > .../pci/controller/mobiveil/pcie-mobiveil.c | 245 + > > .../pci/controller/mobiveil/pcie-mobiveil.h | 221 + > > drivers/pci/controller/pcie-mobiveil.c| 861 -- > > 14 files changed, 1625 insertions(+), 873 deletions(-) > > create mode 100644 Documentation/devicetree/bindings/pci/lx-pci.txt > > create mode 100644 drivers/pci/controller/mobiveil/Kconfig > > create mode 100644 drivers/pci/controller/mobiveil/Makefile > > create mode 100644 drivers/pci/controller/mobiveil/pci-lx.c > > create mode 100644 drivers/pci/controller/mobiveil/pcie-mobiveil-host.c > > create mode 100644 drivers/pci/controller/mobiveil/pcie-mobiveil-plat.c > > create mode 100644 drivers/pci/controller/mobiveil/pcie-mobiveil.c > > create mode 100644 drivers/pci/controller/mobiveil/pcie-mobiveil.h > > delete mode 100644 drivers/pci/controller/pcie-mobiveil.c > > Subrahmanya, > > for the records, this is the driver *you* are maintaining, aren't you ? > > We ask developers to be added to the MAINTAINERS list in order to hold > them accountable, merging a driver upstream means that you need to > actively maintain it, which in turn means reviewing series affecting > its code, like this one. > > I will have a look too but it is your responsibility to review these > patches and ACK them accordingly. > > So I strongly suggest you start doing it please. > > Thanks, > Lorenzo
Re: [PATCH 15/23] dt-bindings: pci: mobiveil: change gpio_slave and apb_csr to optional
Acked-by: Subrahmanya Lingappa On Tue, Nov 6, 2018 at 6:50 PM Z.q. Hou wrote: > > From: Hou Zhiqiang > > Change the "gpio_slave" and "apb_csr" to optional, the "gpio_slave" > is not used in current code, and "apb_csr" is not used by some > platorms. > > Signed-off-by: Hou Zhiqiang > --- > Documentation/devicetree/bindings/pci/mobiveil-pcie.txt | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/mobiveil-pcie.txt > b/Documentation/devicetree/bindings/pci/mobiveil-pcie.txt > index a618d4787dd7..64156993e052 100644 > --- a/Documentation/devicetree/bindings/pci/mobiveil-pcie.txt > +++ b/Documentation/devicetree/bindings/pci/mobiveil-pcie.txt > @@ -10,8 +10,10 @@ Required properties: > interrupt source. The value must be 1. > - compatible: Should contain "mbvl,gpex40-pcie" > - reg: Should contain PCIe registers location and length > + Mandatory: > "config_axi_slave": PCIe controller registers > "csr_axi_slave" : Bridge config registers > + Optional: > "gpio_slave" : GPIO registers to control slot power > "apb_csr" : MSI registers > > -- > 2.17.1 >
Re: [PATCH 15/23] dt-bindings: pci: mobiveil: change gpio_slave and apb_csr to optional
Acked-by: Subrahmanya Lingappa On Tue, Nov 6, 2018 at 6:50 PM Z.q. Hou wrote: > > From: Hou Zhiqiang > > Change the "gpio_slave" and "apb_csr" to optional, the "gpio_slave" > is not used in current code, and "apb_csr" is not used by some > platorms. > > Signed-off-by: Hou Zhiqiang > --- > Documentation/devicetree/bindings/pci/mobiveil-pcie.txt | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/mobiveil-pcie.txt > b/Documentation/devicetree/bindings/pci/mobiveil-pcie.txt > index a618d4787dd7..64156993e052 100644 > --- a/Documentation/devicetree/bindings/pci/mobiveil-pcie.txt > +++ b/Documentation/devicetree/bindings/pci/mobiveil-pcie.txt > @@ -10,8 +10,10 @@ Required properties: > interrupt source. The value must be 1. > - compatible: Should contain "mbvl,gpex40-pcie" > - reg: Should contain PCIe registers location and length > + Mandatory: > "config_axi_slave": PCIe controller registers > "csr_axi_slave" : Bridge config registers > + Optional: > "gpio_slave" : GPIO registers to control slot power > "apb_csr" : MSI registers > > -- > 2.17.1 >
Re: [PATCH] PCI: remove unnecessary check of device_type == pci
Hi,
with regards to : drivers/pci/controller/pcie-mobiveil.c
Acked-by: Subrahmaya Lingappa
Thanks.
On Thu, Aug 30, 2018 at 12:04 AM Rob Herring wrote:
>
> PCI host drivers have already matched on compatible strings, so checking
> device_type is redundant. Also, device_type is considered deprecated for
> FDT though we've still been requiring it for PCI hosts as it is useful
> for finding PCI buses.
>
> Cc: Will Deacon
> Cc: Lorenzo Pieralisi
> Cc: Bjorn Helgaas
> Cc: Alan Douglas
> Cc: Subrahmanya Lingappa
> Cc: Michal Simek
> Cc: linux-...@vger.kernel.org
> Cc: linux-arm-ker...@lists.infradead.org
> Signed-off-by: Rob Herring
> ---
> drivers/pci/controller/pci-host-common.c | 8
> drivers/pci/controller/pcie-cadence-host.c | 7 ---
> drivers/pci/controller/pcie-mobiveil.c | 7 ---
> drivers/pci/controller/pcie-xilinx-nwl.c | 9 -
> drivers/pci/controller/pcie-xilinx.c | 7 ---
> 5 files changed, 38 deletions(-)
>
> diff --git a/drivers/pci/controller/pci-host-common.c
> b/drivers/pci/controller/pci-host-common.c
> index d8f10451f273..c742881b5061 100644
> --- a/drivers/pci/controller/pci-host-common.c
> +++ b/drivers/pci/controller/pci-host-common.c
> @@ -58,9 +58,7 @@ static struct pci_config_window *gen_pci_init(struct device
> *dev,
> int pci_host_common_probe(struct platform_device *pdev,
> struct pci_ecam_ops *ops)
> {
> - const char *type;
> struct device *dev = >dev;
> - struct device_node *np = dev->of_node;
> struct pci_host_bridge *bridge;
> struct pci_config_window *cfg;
> struct list_head resources;
> @@ -70,12 +68,6 @@ int pci_host_common_probe(struct platform_device *pdev,
> if (!bridge)
> return -ENOMEM;
>
> - type = of_get_property(np, "device_type", NULL);
> - if (!type || strcmp(type, "pci")) {
> - dev_err(dev, "invalid \"device_type\" %s\n", type);
> - return -EINVAL;
> - }
> -
> of_pci_check_probe_only();
>
> /* Parse and map our Configuration Space windows */
> diff --git a/drivers/pci/controller/pcie-cadence-host.c
> b/drivers/pci/controller/pcie-cadence-host.c
> index ec394f6a19c8..97e251090b4f 100644
> --- a/drivers/pci/controller/pcie-cadence-host.c
> +++ b/drivers/pci/controller/pcie-cadence-host.c
> @@ -235,7 +235,6 @@ static int cdns_pcie_host_init(struct device *dev,
>
> static int cdns_pcie_host_probe(struct platform_device *pdev)
> {
> - const char *type;
> struct device *dev = >dev;
> struct device_node *np = dev->of_node;
> struct pci_host_bridge *bridge;
> @@ -268,12 +267,6 @@ static int cdns_pcie_host_probe(struct platform_device
> *pdev)
> rc->device_id = 0x;
> of_property_read_u16(np, "device-id", >device_id);
>
> - type = of_get_property(np, "device_type", NULL);
> - if (!type || strcmp(type, "pci")) {
> - dev_err(dev, "invalid \"device_type\" %s\n", type);
> - return -EINVAL;
> - }
> -
> res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg");
> pcie->reg_base = devm_ioremap_resource(dev, res);
> if (IS_ERR(pcie->reg_base)) {
> diff --git a/drivers/pci/controller/pcie-mobiveil.c
> b/drivers/pci/controller/pcie-mobiveil.c
> index a939e8d31735..77052a0712d0 100644
> --- a/drivers/pci/controller/pcie-mobiveil.c
> +++ b/drivers/pci/controller/pcie-mobiveil.c
> @@ -301,13 +301,6 @@ static int mobiveil_pcie_parse_dt(struct mobiveil_pcie
> *pcie)
> struct platform_device *pdev = pcie->pdev;
> struct device_node *node = dev->of_node;
> struct resource *res;
> - const char *type;
> -
> - type = of_get_property(node, "device_type", NULL);
> - if (!type || strcmp(type, "pci")) {
> - dev_err(dev, "invalid \"device_type\" %s\n", type);
> - return -EINVAL;
> - }
>
> /* map config resource */
> res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
> diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c
> b/drivers/pci/controller/pcie-xilinx-nwl.c
> index fb32840ce8e6..81538d77f790 100644
> --- a/drivers/pci/controller/pcie-xilinx-nwl.c
> +++ b/drivers/pci/controller/pcie-xilinx-nwl.c
> @@ -777,16 +777,7 @@ static int nwl_pcie_parse_dt(struct nwl_pcie *pcie,
> struct platform_device *pdev)
> {
> struct device *de
Re: [PATCH] PCI: remove unnecessary check of device_type == pci
Hi,
with regards to : drivers/pci/controller/pcie-mobiveil.c
Acked-by: Subrahmaya Lingappa
Thanks.
On Thu, Aug 30, 2018 at 12:04 AM Rob Herring wrote:
>
> PCI host drivers have already matched on compatible strings, so checking
> device_type is redundant. Also, device_type is considered deprecated for
> FDT though we've still been requiring it for PCI hosts as it is useful
> for finding PCI buses.
>
> Cc: Will Deacon
> Cc: Lorenzo Pieralisi
> Cc: Bjorn Helgaas
> Cc: Alan Douglas
> Cc: Subrahmanya Lingappa
> Cc: Michal Simek
> Cc: linux-...@vger.kernel.org
> Cc: linux-arm-ker...@lists.infradead.org
> Signed-off-by: Rob Herring
> ---
> drivers/pci/controller/pci-host-common.c | 8
> drivers/pci/controller/pcie-cadence-host.c | 7 ---
> drivers/pci/controller/pcie-mobiveil.c | 7 ---
> drivers/pci/controller/pcie-xilinx-nwl.c | 9 -
> drivers/pci/controller/pcie-xilinx.c | 7 ---
> 5 files changed, 38 deletions(-)
>
> diff --git a/drivers/pci/controller/pci-host-common.c
> b/drivers/pci/controller/pci-host-common.c
> index d8f10451f273..c742881b5061 100644
> --- a/drivers/pci/controller/pci-host-common.c
> +++ b/drivers/pci/controller/pci-host-common.c
> @@ -58,9 +58,7 @@ static struct pci_config_window *gen_pci_init(struct device
> *dev,
> int pci_host_common_probe(struct platform_device *pdev,
> struct pci_ecam_ops *ops)
> {
> - const char *type;
> struct device *dev = >dev;
> - struct device_node *np = dev->of_node;
> struct pci_host_bridge *bridge;
> struct pci_config_window *cfg;
> struct list_head resources;
> @@ -70,12 +68,6 @@ int pci_host_common_probe(struct platform_device *pdev,
> if (!bridge)
> return -ENOMEM;
>
> - type = of_get_property(np, "device_type", NULL);
> - if (!type || strcmp(type, "pci")) {
> - dev_err(dev, "invalid \"device_type\" %s\n", type);
> - return -EINVAL;
> - }
> -
> of_pci_check_probe_only();
>
> /* Parse and map our Configuration Space windows */
> diff --git a/drivers/pci/controller/pcie-cadence-host.c
> b/drivers/pci/controller/pcie-cadence-host.c
> index ec394f6a19c8..97e251090b4f 100644
> --- a/drivers/pci/controller/pcie-cadence-host.c
> +++ b/drivers/pci/controller/pcie-cadence-host.c
> @@ -235,7 +235,6 @@ static int cdns_pcie_host_init(struct device *dev,
>
> static int cdns_pcie_host_probe(struct platform_device *pdev)
> {
> - const char *type;
> struct device *dev = >dev;
> struct device_node *np = dev->of_node;
> struct pci_host_bridge *bridge;
> @@ -268,12 +267,6 @@ static int cdns_pcie_host_probe(struct platform_device
> *pdev)
> rc->device_id = 0x;
> of_property_read_u16(np, "device-id", >device_id);
>
> - type = of_get_property(np, "device_type", NULL);
> - if (!type || strcmp(type, "pci")) {
> - dev_err(dev, "invalid \"device_type\" %s\n", type);
> - return -EINVAL;
> - }
> -
> res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg");
> pcie->reg_base = devm_ioremap_resource(dev, res);
> if (IS_ERR(pcie->reg_base)) {
> diff --git a/drivers/pci/controller/pcie-mobiveil.c
> b/drivers/pci/controller/pcie-mobiveil.c
> index a939e8d31735..77052a0712d0 100644
> --- a/drivers/pci/controller/pcie-mobiveil.c
> +++ b/drivers/pci/controller/pcie-mobiveil.c
> @@ -301,13 +301,6 @@ static int mobiveil_pcie_parse_dt(struct mobiveil_pcie
> *pcie)
> struct platform_device *pdev = pcie->pdev;
> struct device_node *node = dev->of_node;
> struct resource *res;
> - const char *type;
> -
> - type = of_get_property(node, "device_type", NULL);
> - if (!type || strcmp(type, "pci")) {
> - dev_err(dev, "invalid \"device_type\" %s\n", type);
> - return -EINVAL;
> - }
>
> /* map config resource */
> res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
> diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c
> b/drivers/pci/controller/pcie-xilinx-nwl.c
> index fb32840ce8e6..81538d77f790 100644
> --- a/drivers/pci/controller/pcie-xilinx-nwl.c
> +++ b/drivers/pci/controller/pcie-xilinx-nwl.c
> @@ -777,16 +777,7 @@ static int nwl_pcie_parse_dt(struct nwl_pcie *pcie,
> struct platform_device *pdev)
> {
> struct device *de
Re: [PATCH AUTOSEL 4.18 068/131] PCI: mobiveil: Add missing ../pci.h include
Acked-by: Subrahmanya Lingappa
Thanks.
On Sun, Sep 2, 2018 at 6:34 PM Sasha Levin
wrote:
>
> From: Lorenzo Pieralisi
>
> [ Upstream commit d3743012230f8dab30d47caba1f2ee9e382385e7 ]
>
> PCI mobiveil host controller driver currently fails to compile
> with the following error:
>
> drivers/pci/controller/pcie-mobiveil.c: In function
> 'mobiveil_pcie_probe':
> drivers/pci/controller/pcie-mobiveil.c:788:8: error: implicit
> declaration of function 'devm_of_pci_get_host_bridge_resources'; did you
> mean 'pci_get_host_bridge_device'?
> [-Werror=implicit-function-declaration]
> ret = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff,
> ^
> pci_get_host_bridge_device
>
> Add the missing include file to pull in the required function declaration.
>
> Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP
> driver")
> Signed-off-by: Lorenzo Pieralisi
> Cc: Bjorn Helgaas
> Cc: Subrahmanya Lingappa
> Signed-off-by: Sasha Levin
> ---
> drivers/pci/controller/pcie-mobiveil.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/pci/controller/pcie-mobiveil.c
> b/drivers/pci/controller/pcie-mobiveil.c
> index cf0aa7cee5b0..2c81be37b010 100644
> --- a/drivers/pci/controller/pcie-mobiveil.c
> +++ b/drivers/pci/controller/pcie-mobiveil.c
> @@ -23,6 +23,8 @@
> #include
> #include
>
> +#include "../pci.h"
> +
> /* register offsets and bit positions */
>
> /*
> --
> 2.17.1
Re: [PATCH AUTOSEL 4.18 068/131] PCI: mobiveil: Add missing ../pci.h include
Acked-by: Subrahmanya Lingappa
Thanks.
On Sun, Sep 2, 2018 at 6:34 PM Sasha Levin
wrote:
>
> From: Lorenzo Pieralisi
>
> [ Upstream commit d3743012230f8dab30d47caba1f2ee9e382385e7 ]
>
> PCI mobiveil host controller driver currently fails to compile
> with the following error:
>
> drivers/pci/controller/pcie-mobiveil.c: In function
> 'mobiveil_pcie_probe':
> drivers/pci/controller/pcie-mobiveil.c:788:8: error: implicit
> declaration of function 'devm_of_pci_get_host_bridge_resources'; did you
> mean 'pci_get_host_bridge_device'?
> [-Werror=implicit-function-declaration]
> ret = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff,
> ^
> pci_get_host_bridge_device
>
> Add the missing include file to pull in the required function declaration.
>
> Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP
> driver")
> Signed-off-by: Lorenzo Pieralisi
> Cc: Bjorn Helgaas
> Cc: Subrahmanya Lingappa
> Signed-off-by: Sasha Levin
> ---
> drivers/pci/controller/pcie-mobiveil.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/pci/controller/pcie-mobiveil.c
> b/drivers/pci/controller/pcie-mobiveil.c
> index cf0aa7cee5b0..2c81be37b010 100644
> --- a/drivers/pci/controller/pcie-mobiveil.c
> +++ b/drivers/pci/controller/pcie-mobiveil.c
> @@ -23,6 +23,8 @@
> #include
> #include
>
> +#include "../pci.h"
> +
> /* register offsets and bit positions */
>
> /*
> --
> 2.17.1
Re: [PATCH AUTOSEL 4.18 069/131] PCI: mobiveil: Fix struct mobiveil_pcie.pcie_reg_base address type
Acked-by: Subrahmanya Lingappa
Thanks.
On Sun, Sep 2, 2018 at 6:34 PM Sasha Levin
wrote:
>
> From: Lorenzo Pieralisi
>
> [ Upstream commit af3f606e0bbb6d811c50b7b90fe324b07fb7cab8 ]
>
> The field pcie_reg_base in struct mobiveil_pcie represents a physical
> address so it should be of phys_addr_t type rather than void __iomem*;
> this results in the following compilation warnings:
>
> drivers/pci/controller/pcie-mobiveil.c: In function
> 'mobiveil_pcie_parse_dt':
> drivers/pci/controller/pcie-mobiveil.c:326:22: warning: assignment makes
> pointer from integer without a cast [-Wint-conversion]
> pcie->pcie_reg_base = res->start;
> ^
> drivers/pci/controller/pcie-mobiveil.c: In function
> 'mobiveil_pcie_enable_msi':
> drivers/pci/controller/pcie-mobiveil.c:485:25: warning: initialization
> makes integer from pointer without a cast [-Wint-conversion]
> phys_addr_t msg_addr = pcie->pcie_reg_base;
> ^~~~
> drivers/pci/controller/pcie-mobiveil.c: In function
> 'mobiveil_compose_msi_msg':
> drivers/pci/controller/pcie-mobiveil.c:640:21: warning: initialization
> makes integer from pointer without a cast [-Wint-conversion]
> phys_addr_t addr = pcie->pcie_reg_base + (data->hwirq * sizeof(int));
>
> Fix the type and with it the compilation warnings.
>
> Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP
> driver")
> Signed-off-by: Lorenzo Pieralisi
> Cc: Bjorn Helgaas
> Cc: Subrahmanya Lingappa
> Signed-off-by: Sasha Levin
> ---
> drivers/pci/controller/pcie-mobiveil.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/pcie-mobiveil.c
> b/drivers/pci/controller/pcie-mobiveil.c
> index 2c81be37b010..a939e8d31735 100644
> --- a/drivers/pci/controller/pcie-mobiveil.c
> +++ b/drivers/pci/controller/pcie-mobiveil.c
> @@ -132,7 +132,7 @@ struct mobiveil_pcie {
> void __iomem *config_axi_slave_base;/* endpoint config base */
> void __iomem *csr_axi_slave_base; /* root port config base */
> void __iomem *apb_csr_base; /* MSI register base */
> - void __iomem *pcie_reg_base;/* Physical PCIe Controller Base */
> + phys_addr_t pcie_reg_base; /* Physical PCIe Controller Base */
> struct irq_domain *intx_domain;
> raw_spinlock_t intx_mask_lock;
> int irq;
> --
> 2.17.1
Re: [PATCH AUTOSEL 4.18 069/131] PCI: mobiveil: Fix struct mobiveil_pcie.pcie_reg_base address type
Acked-by: Subrahmanya Lingappa
Thanks.
On Sun, Sep 2, 2018 at 6:34 PM Sasha Levin
wrote:
>
> From: Lorenzo Pieralisi
>
> [ Upstream commit af3f606e0bbb6d811c50b7b90fe324b07fb7cab8 ]
>
> The field pcie_reg_base in struct mobiveil_pcie represents a physical
> address so it should be of phys_addr_t type rather than void __iomem*;
> this results in the following compilation warnings:
>
> drivers/pci/controller/pcie-mobiveil.c: In function
> 'mobiveil_pcie_parse_dt':
> drivers/pci/controller/pcie-mobiveil.c:326:22: warning: assignment makes
> pointer from integer without a cast [-Wint-conversion]
> pcie->pcie_reg_base = res->start;
> ^
> drivers/pci/controller/pcie-mobiveil.c: In function
> 'mobiveil_pcie_enable_msi':
> drivers/pci/controller/pcie-mobiveil.c:485:25: warning: initialization
> makes integer from pointer without a cast [-Wint-conversion]
> phys_addr_t msg_addr = pcie->pcie_reg_base;
> ^~~~
> drivers/pci/controller/pcie-mobiveil.c: In function
> 'mobiveil_compose_msi_msg':
> drivers/pci/controller/pcie-mobiveil.c:640:21: warning: initialization
> makes integer from pointer without a cast [-Wint-conversion]
> phys_addr_t addr = pcie->pcie_reg_base + (data->hwirq * sizeof(int));
>
> Fix the type and with it the compilation warnings.
>
> Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP
> driver")
> Signed-off-by: Lorenzo Pieralisi
> Cc: Bjorn Helgaas
> Cc: Subrahmanya Lingappa
> Signed-off-by: Sasha Levin
> ---
> drivers/pci/controller/pcie-mobiveil.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/pcie-mobiveil.c
> b/drivers/pci/controller/pcie-mobiveil.c
> index 2c81be37b010..a939e8d31735 100644
> --- a/drivers/pci/controller/pcie-mobiveil.c
> +++ b/drivers/pci/controller/pcie-mobiveil.c
> @@ -132,7 +132,7 @@ struct mobiveil_pcie {
> void __iomem *config_axi_slave_base;/* endpoint config base */
> void __iomem *csr_axi_slave_base; /* root port config base */
> void __iomem *apb_csr_base; /* MSI register base */
> - void __iomem *pcie_reg_base;/* Physical PCIe Controller Base */
> + phys_addr_t pcie_reg_base; /* Physical PCIe Controller Base */
> struct irq_domain *intx_domain;
> raw_spinlock_t intx_mask_lock;
> int irq;
> --
> 2.17.1
