respective configuration accesses just like the way it is
done in DesignWare core sub-system.
This issue is specific to Tegra194 and it would be fixed in the future
generations of Tegra SoCs.
Signed-off-by: Vidya Sagar
---
V4:
* Addressed Bjorn's review comments
* Rebased changes on top of Lorenzo's
On 3/6/2021 3:27 AM, Bjorn Helgaas wrote:
External email: Use caution opening links or attachments
[+cc Krzysztof for .bus_shift below]
This is [2/2] but I don't see a [1/2]. Is there something missing?
On Sat, Jan 11, 2020 at 12:45:00AM +0530, Vidya Sagar wrote:
The PCIe controller
On 4/13/2021 11:43 PM, Rob Herring wrote:
External email: Use caution opening links or attachments
On Mon, Apr 12, 2021 at 12:01 PM Vidya Sagar wrote:
Hi
I'm starting this mail to seek advice on the best approach to be taken
to add support for the driver of the PCIe root port's DMA
On 4/13/2021 3:23 AM, Bjorn Helgaas wrote:
External email: Use caution opening links or attachments
[+cc Matthew for portdrv comment]
On Mon, Apr 12, 2021 at 10:31:02PM +0530, Vidya Sagar wrote:
Hi
I'm starting this mail to seek advice on the best approach to be taken to
add support
as a port service driver as
it makes it cleaner and also in line with the design philosophy (the way
I understood it) of the port service drivers.
Please let me know your thoughts on this.
Thanks,
Vidya Sagar
Ie devices behind bridge after
reset...
But, is save-restore alone going to be enough? I mean what is the state
of the device-driver going to be when the device is going through the
reset process? Isn't remove-rescan the correct thing to do here rather
than save/restore?
- Vidya Sagar
Alex
diff --git
On 3/5/2021 5:49 PM, Bjorn Helgaas wrote:
External email: Use caution opening links or attachments
On Fri, Mar 05, 2021 at 01:42:34PM +0530, Om Prakash Singh wrote:
PCIe EP compliance expect PTM capabilities (ROOT_CAPABLE, RES_CAPABLE,
CLK_GRAN) to be disabled.
I guess this is just
On 1/5/2021 10:27 AM, Jeremy Linton wrote:
External email: Use caution opening links or attachments
Given that most arm64 platform's PCI implementations needs quirks
to deal with problematic config accesses, this is a good place to
apply a firmware abstraction. The ARM PCI SMMCCC spec
Thanks for the patch.
Acked-by: Vidya Sagar
On 12/31/2020 8:55 AM, Wesley Sheng wrote:
External email: Use caution opening links or attachments
In config PCIE_TEGRA194_EP the mode incorrectly referred to
host mode.
Signed-off-by: Wesley Sheng
---
drivers/pci/controller/dwc/Kconfig | 2
DesignWare core has a TLP digest (TD) override bit in one of the control
registers of ATU. This bit also needs to be programmed for proper ECRC
functionality. This is currently identified as an issue with DesignWare
IP version 4.90a.
Signed-off-by: Vidya Sagar
Acked-by: Bjorn Helgaas
---
V3
Ideally Bjorn's patch should have worked.
Could you please collect 'sudo lspci -vv' (please don't forget to give
sudo) with Bjorn's patch before and after hibernate?
Also, is it right to say that with policy set to "performance" there is
no issue during hibernate/resume?
- Vidya Sa
tch. Perhaps I need to spend more
time to debug that part.
In any case, since dw_pcie_setup_rc() is already part of
dw_pcie_host_init(), I think it can be removed from
tegra_pcie_prepare_host() implemention.
Thanks,
Vidya Sagar
On 12/15/2020 3:54 PM, Mian Yousaf Kaukab wrote:
External email:
Hi Lorenzo,
Apologies to bug you, but wondering if you have any further comments on
this patch that I need to take care of?
Thanks,
Vidya Sagar
On 12/3/2020 5:40 PM, Vidya Sagar wrote:
On 11/25/2020 2:32 AM, Bjorn Helgaas wrote:
External email: Use caution opening links or attachments
There is a change already available for it in linux-next
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=4257f7e008ea394fcecc050f1569c3503b8bcc15
Thanks,
Vidya Sagar
On 12/9/2020 3:36 AM, David E. Box wrote:
External email: Use caution opening links
On 12/8/2020 2:07 AM, Bjorn Helgaas wrote:
External email: Use caution opening links or attachments
[+cc Jingoo, Gustavo]
On Thu, Dec 03, 2020 at 07:04:51PM +0530, Vidya Sagar wrote:
PCIe cards like Marvell SATA controller and some of the Samsung NVMe
drives don't support taking the link
On 12/4/2020 1:24 AM, Bjorn Helgaas wrote:
External email: Use caution opening links or attachments
On Fri, Dec 04, 2020 at 12:33:45AM +0530, Vidya Sagar wrote:
On 12/3/2020 11:54 PM, Bjorn Helgaas wrote:
On Tue, Nov 24, 2020 at 04:20:35PM +0530, Vidya Sagar wrote:
There are devices (Ex
On 12/3/2020 11:54 PM, Bjorn Helgaas wrote:
External email: Use caution opening links or attachments
On Tue, Nov 24, 2020 at 04:20:35PM +0530, Vidya Sagar wrote:
There are devices (Ex:- Marvell SATA controller) that don't support
64-bit MSIs and the same is advertised through their MSI
are
returning error. That way, it is more closer to complete uninitialization.
Tested-by: Thierry Reding
Signed-off-by: Vidya Sagar
Acked-by: Thierry Reding
---
V5:
* Added Tested-by and Acked-by from Thierry Reding
V4:
* None
V3:
* Modified subject as per Bjorn's suggestion
* Removed
The return value of tegra_pcie_init_controller() must be checked before
PCIe link up check and registering debugfs entries subsequently as it
doesn't make sense to do these when the controller initialization itself
has failed.
Tested-by: Thierry Reding
Signed-off-by: Vidya Sagar
Acked
Set the DesignWare IP version for Tegra194 to 0x490A. This would be used
by the DesigWare sub-system to do any version specific configuration
(Ex:- TD bit programming for ECRC).
Tested-by: Thierry Reding
Signed-off-by: Vidya Sagar
Acked-by: Thierry Reding
---
V5:
* Added Tested-by and Acked
to disable LTSSM results in the PCIe link not coming up in the
next resume cycle.
Tested-by: Thierry Reding
Signed-off-by: Vidya Sagar
Acked-by: Thierry Reding
---
V5:
* Added Tested-by and Acked-by from Thierry Reding
V4:
* New patch in this series
drivers/pci/controller/dwc/pcie-tegra194.c
with the uninitialization sequence even if some parts fail
- Check return value of tegra_pcie_init_controller() and exit accordingly
V2:
* Addressed Rob's comments. Changed 'Strongly Ordered' to 'nGnRnE'
Vidya Sagar (5):
PCI: tegra: Fix ASPM-L1SS advertisement disable code
PCI: tegra: Set
d Tegra194 PCIe support")
Signed-off-by: Vidya Sagar
---
V5:
* Rebased on top of the tree code
V4:
* None
V3:
* None
V2:
* None
drivers/pci/controller/dwc/pcie-tegra194.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-tegra
-Original Message-
From: Thierry Reding
Sent: Thursday, November 26, 2020 5:04 PM
To: Vidya Sagar
Cc: lorenzo.pieral...@arm.com; robh...@kernel.org; bhelg...@google.com;
Jonathan Hunter ; amanharitsh...@gmail.com;
dinghao@zju.edu.cn; k...@linux.com; linux-...@vger.kernel.org
-Original Message-
From: Thierry Reding
Sent: Thursday, November 26, 2020 5:03 PM
To: Vidya Sagar
Cc: lorenzo.pieral...@arm.com; robh...@kernel.org; bhelg...@google.com;
Jonathan Hunter ; amanharitsh...@gmail.com;
dinghao@zju.edu.cn; k...@linux.com; linux-...@vger.kernel.org
On 11/25/2020 2:32 AM, Bjorn Helgaas wrote:
External email: Use caution opening links or attachments
On Tue, Nov 24, 2020 at 03:50:01PM +0530, Vidya Sagar wrote:
Hi Bjorn,
Please let me know if this patch needs any further modifications
I'm fine with it, but of course Lorenzo will take
Hi,
Could you please review this patch in the context of the following patch?
http://patchwork.ozlabs.org/project/linux-pci/patch/20201124105035.24573-1-vid...@nvidia.com/
Thanks,
Vidya Sagar
On 11/17/2020 10:23 PM, Vidya Sagar wrote:
Set DMA mask to 32-bit while allocating the MSI target
Hi Bjorn,
Do you have any further comments for this patch?
Thanks,
Vidya Sagar
On 11/24/2020 4:20 PM, Vidya Sagar wrote:
There are devices (Ex:- Marvell SATA controller) that don't support
64-bit MSIs and the same is advertised through their MSI capability
register. Set no_64bit_msi flag
-Original Message-
From: Thierry Reding
Sent: Wednesday, November 25, 2020 11:27 PM
To: Vidya Sagar
Cc: lorenzo.pieral...@arm.com; robh...@kernel.org; bhelg...@google.com;
Jonathan Hunter ; amanharitsh...@gmail.com;
dinghao@zju.edu.cn; k...@linux.com; linux-...@vger.kernel.org
registers are accessed. This issue is fixed by explicitly reading the
"dbi" base address from DT node.
Fixes: a0fd361db8e5 ("PCI: dwc: Move "dbi", "dbi2", and "addr_space" resource
setup into common code")
Signed-off-by: Vidya Sagar
---
drivers/pci/co
db8e5 ("PCI: dwc: Move "dbi", "dbi2", and "addr_space" resource
setup into common code")
Signed-off-by: Vidya Sagar
---
drivers/pci/controller/dwc/pcie-tegra194.c | 19 ++-
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/drivers/pci
to use 64-bit MSI.
Signed-off-by: Vidya Sagar
---
V2:
* Addressed Bjorn's comment and changed the error message
drivers/pci/msi.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c
index d52d118979a6..8de5ba6b4a59 100644
Hi Bjorn,
Please let me know if this patch needs any further modifications
Thanks,
Vidya Sagar
On 11/12/2020 10:32 PM, Vidya Sagar wrote:
External email: Use caution opening links or attachments
On 11/12/2020 3:59 AM, Bjorn Helgaas wrote:
External email: Use caution opening links
On 11/21/2020 3:00 AM, Bjorn Helgaas wrote:
External email: Use caution opening links or attachments
On Tue, Nov 17, 2020 at 08:27:28PM +0530, Vidya Sagar wrote:
There are devices (Ex:- Marvell SATA controller) that don't support
64-bit MSIs and the same is advertised through their MSI
Add support to program the ATU to enable translations for >4GB sizes of
the prefetchable memory apertures.
Tested-by: Thierry Reding
Tested-by: Jon Hunter
Signed-off-by: Vidya Sagar
Reviewed-by: Rob Herring
Acked-by: Jingoo
---
V2:
* Added 'Tested-by', 'Reviewed-by' and 'Acked-by'
driv
As per PCIe spec r5.0, sec 7.5.1.3.8 only 32-bit BAR registers are defined
for non-prefetchable memory and hence a warning should be reported when
the size of them go beyond 32-bits.
Tested-by: Thierry Reding
Tested-by: Jon Hunter
Signed-off-by: Vidya Sagar
Reviewed-by: Rob Herring
---
V2
org/project/linux-pci/patch/20201026181652.418729-1-r...@kernel.org/
Vidya Sagar (2):
PCI: of: Warn if non-prefetchable memory aperture size is > 32-bit
PCI: dwc: Add support to program ATU for >4GB memory
drivers/pci/controller/dwc/pcie-designware.c | 12 +++-
drivers/pci/controller
On 11/17/2020 5:40 PM, Lorenzo Pieralisi wrote:
External email: Use caution opening links or attachments
On Tue, Nov 17, 2020 at 10:08:35AM +0530, Vidya Sagar wrote:
Hi Lorenzo & Bjorn,
Sorry to bother you.
Could you please take a look at the patches-1 & 2 from this series?
Set DMA mask to 32-bit while allocating the MSI target address so that
the address is usable for both 32-bit and 64-bit MSI capable devices.
Throw a warning if it fails to set the mask to 32-bit to alert that
devices that are only 32-bit MSI capable may not work properly.
Signed-off-by: Vidya
to use 64-bit MSI.
Signed-off-by: Vidya Sagar
---
drivers/pci/msi.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c
index d52d118979a6..af49da28854e 100644
--- a/drivers/pci/msi.c
+++ b/drivers/pci/msi.c
@@ -581,10 +581,12
Hi Lorenzo & Bjorn,
Sorry to bother you.
Could you please take a look at the patches-1 & 2 from this series?
Thanks,
Vidya Sagar
On 11/4/2020 1:16 PM, Vidya Sagar wrote:
External email: Use caution opening links or attachments
Lorenzo / Bjorn,
Could you please review patch
On 11/12/2020 3:59 AM, Bjorn Helgaas wrote:
External email: Use caution opening links or attachments
On Wed, Nov 11, 2020 at 10:21:46PM +0530, Vidya Sagar wrote:
On 11/11/2020 9:57 PM, Jingoo Han wrote:
External email: Use caution opening links or attachments
On 11/11/20, 7:12 AM
On 11/11/2020 9:57 PM, Jingoo Han wrote:
External email: Use caution opening links or attachments
On 11/11/20, 7:12 AM, Vidya Sagar wrote:
DesignWare core has a TLP digest (TD) override bit in one of the control
registers of ATU. This bit also needs to be programmed for proper ECRC
DesignWare core has a TLP digest (TD) override bit in one of the control
registers of ATU. This bit also needs to be programmed for proper ECRC
functionality. This is currently identified as an issue with DesignWare
IP version 4.90a.
Signed-off-by: Vidya Sagar
Acked-by: Bjorn Helgaas
---
V2
DesignWare core has a TLP digest (TD) override bit in one of the control
registers of ATU. This bit also needs to be programmed for proper ECRC
functionality. This is currently identified as an issue with DesignWare
IP version 4.90a.
Signed-off-by: Vidya Sagar
---
drivers/pci/controller/dwc
to disable LTSSM results in the PCIe link not coming up in the
next resume cycle.
Signed-off-by: Vidya Sagar
---
V4:
* New patch in this series
drivers/pci/controller/dwc/pcie-tegra194.c | 16 +---
1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/drivers/pci/controller/dwc
configuration space.
Signed-off-by: Vidya Sagar
---
V4:
* None
V3:
* None
V2:
* Changed 'Strongly Ordered' to 'nGnRnE'
drivers/pci/controller/dwc/pcie-tegra194.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c
b/drivers/pci/controller/dwc
are
returning error. That way, it is more closer to complete uninitialization.
Signed-off-by: Vidya Sagar
---
V4:
* None
V3:
* Modified subject as per Bjorn's suggestion
* Removed tegra_pcie_init_controller()'s error checking part and pushed
a separate patch for it
V2:
* None
drivers/pci/controller
The return value of tegra_pcie_init_controller() must be checked before
PCIe link up check and registering debugfs entries subsequently as it
doesn't make sense to do these when the controller initialization itself
has failed.
Signed-off-by: Vidya Sagar
---
V4:
* None
V3:
* New patch
d Tegra194 PCIe support")
Signed-off-by: Vidya Sagar
---
V4:
* None
V3:
* None
V2:
* None
drivers/pci/controller/dwc/pcie-tegra194.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c
b/drivers/pci/controller/dwc/p
Set the DesignWare IP version for Tegra194 to 0x490A. This would be used
by the DesigWare sub-system to do any version specific configuration
(Ex:- TD bit programming for ECRC).
Signed-off-by: Vidya Sagar
---
V4:
* None
V3:
* None
V2:
* None
drivers/pci/controller/dwc/pcie-tegra194.c | 1
:
* Addressed Rob's comments. Changed 'Strongly Ordered' to 'nGnRnE'
Vidya Sagar (6):
PCI: tegra: Fix ASPM-L1SS advertisement disable code
PCI: tegra: Map configuration space as nGnRnE
PCI: tegra: Set DesignWare IP version
PCI: tegra: Continue unconfig sequence even if parts fail
PCI: tegra
On 11/4/2020 9:52 PM, Bjorn Helgaas wrote:
External email: Use caution opening links or attachments
On Wed, Nov 04, 2020 at 05:13:07PM +0530, Vidya Sagar wrote:
On 11/4/2020 2:37 AM, Bjorn Helgaas wrote:
On Tue, Nov 03, 2020 at 08:57:01AM +0530, Vidya Sagar wrote:
On 11/3/2020 4:32 AM
On 11/4/2020 2:37 AM, Bjorn Helgaas wrote:
External email: Use caution opening links or attachments
On Tue, Nov 03, 2020 at 08:57:01AM +0530, Vidya Sagar wrote:
On 11/3/2020 4:32 AM, Bjorn Helgaas wrote:
On Thu, Oct 29, 2020 at 11:09:59AM +0530, Vidya Sagar wrote:
DesignWare core has
()
V3:
* Addressed Bjorn's review comments
* Split earlier patch-4 into two
- Continue with the uninitialization sequence even if some parts fail
- Check return value of tegra_pcie_init_controller() and exit accordingly
V2:
* Addressed Rob's comments. Changed 'Strongly Ordered' to 'nGnRnE'
Vidya
are
returning error. That way, it is more closer to complete uninitialization.
Signed-off-by: Vidya Sagar
---
V3:
* Modified subject as per Bjorn's suggestion
* Removed tegra_pcie_init_controller()'s error checking part and pushed
a separate patch for it
V2:
* None
drivers/pci/controller/dwc/pcie
configuration space.
Signed-off-by: Vidya Sagar
---
V3:
* None
V2:
* Changed 'Strongly Ordered' to 'nGnRnE'
drivers/pci/controller/dwc/pcie-tegra194.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c
b/drivers/pci/controller/dwc/pcie
d Tegra194 PCIe support")
Signed-off-by: Vidya Sagar
---
V3:
* None
V2:
* None
drivers/pci/controller/dwc/pcie-tegra194.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c
b/drivers/pci/controller/dwc/pcie-tegra194.
c.
Maybe something like:
PCI: tegra: Continue unconfig sequence even if parts fail
Thanks for reviewing the change.
Sure. I'll go with the above subject line.
PCI: tegra: Return init error (not unconfig error) on init failure
On Thu, Oct 29, 2020 at 10:48:39AM +0530, Vidya Sagar wrote:
Cur
The return value of tegra_pcie_init_controller() must be checked before
PCIe link up check and registering debugfs entries subsequently as it
doesn't make sense to do these when the controller initialization itself
has failed.
Signed-off-by: Vidya Sagar
---
V3:
* New patch in this series
Set the DesignWare IP version for Tegra194 to 0x490A. This would be used
by the DesigWare sub-system to do any version specific configuration
(Ex:- TD bit programming for ECRC).
Signed-off-by: Vidya Sagar
---
V3:
* None
V2:
* None
drivers/pci/controller/dwc/pcie-tegra194.c | 1 +
1 file
Lorenzo / Bjorn,
Could you please review patches-1 & 2 in this series?
For the third patch, we already went with Rob's patch @
http://patchwork.ozlabs.org/project/linux-pci/patch/20201026154852.221483-1-r...@kernel.org/
Thanks,
Vidya Sagar
On 10/26/2020 6:02 PM, Thierry Reding wrote:
On
Bjorn / Lorenzo,
Could you please review this change?
Thanks,
Vidya Sagar
On 10/25/2020 12:34 AM, Vidya Sagar wrote:
Previously ASPM L1-Sub-States control registers (CTL1 and CTL2) weren't
saved and restored during suspend/resume leading to ASPM-L1SS
configuration being lost post resume.
Save
On 11/3/2020 4:32 AM, Bjorn Helgaas wrote:
External email: Use caution opening links or attachments
On Thu, Oct 29, 2020 at 11:09:59AM +0530, Vidya Sagar wrote:
DesignWare core has a TLP digest (TD) override bit in one of the control
registers of ATU. This bit also needs to be programmed
On 11/2/2020 7:45 PM, Rob Herring wrote:
External email: Use caution opening links or attachments
On Thu, Oct 29, 2020 at 12:40 AM Vidya Sagar wrote:
DesignWare core has a TLP digest (TD) override bit in one of the control
registers of ATU. This bit also needs to be programmed for proper
On 10/30/2020 3:33 AM, Jingoo Han wrote:
External email: Use caution opening links or attachments
On 10/29/20, 1:40 AM, Vidya Sagar wrote:
DesignWare core has a TLP digest (TD) override bit in one of the control
registers of ATU. This bit also needs to be programmed for proper ECRC
d Tegra194 PCIe support")
Signed-off-by: Vidya Sagar
---
V2:
* None
drivers/pci/controller/dwc/pcie-tegra194.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c
b/drivers/pci/controller/dwc/pcie-tegra194.c
index aa511e
Set the DesignWare IP version for Tegra194 to 0x490A. This would be used
by the DesigWare sub-system to do any version specific configuration
(Ex:- TD bit programming for ECRC).
Signed-off-by: Vidya Sagar
---
V2:
* None
drivers/pci/controller/dwc/pcie-tegra194.c | 1 +
1 file changed, 1
configuration space.
Signed-off-by: Vidya Sagar
---
V2:
* Changed 'Strongly Ordered' to 'nGnRnE'
drivers/pci/controller/dwc/pcie-tegra194.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c
b/drivers/pci/controller/dwc/pcie-tegra194.c
index
identified as an issue with DesignWare
IP version 4.90a. DWC code queries the PCIe sub-system through the API added
in Patch-1 to find out if ECRC is turned on or not and configures ATU
accordingly.
V3:
* Addressed Ethan Zhao's comments for patch-1
V2:
* Addressed Jingoo's review comments
Vidya
the system policy for ECRC.
Signed-off-by: Vidya Sagar
Reviewed-by: Jingoo Han
---
V3:
* Added 'Reviewed-by: Jingoo Han '
V2:
* Addressed Jingoo's review comment
* Removed saving 'td' bit information in 'dw_pcie' structure
drivers/pci/controller/dwc/pcie-designware.c | 8 ++--
drivers/pci
Adds pcie_is_ecrc_enabled() API to let other sub-systems (like DesignWare)
to query if ECRC policy is enabled and perform any configuration
required in those respective sub-systems.
Signed-off-by: Vidya Sagar
Reviewed-by: Jingoo Han
---
V3:
* Address Ethan Zhao's comments
* Added 'Reviewed
are
returning error. That way, it is more closer to complete uninitialization.
It also adds checking return value for error for a cleaner exit path.
Signed-off-by: Vidya Sagar
---
V2:
* None
drivers/pci/controller/dwc/pcie-tegra194.c | 45 ++
1 file changed, 20 insertions(+), 25
'
Vidya Sagar (4):
PCI: tegra: Fix ASPM-L1SS advertisement disable code
PCI: tegra: Map configuration space as nGnRnE
PCI: tegra: Set DesignWare IP version
PCI: tegra: Handle error conditions properly
drivers/pci/controller/dwc/pcie-tegra194.c | 62 +++---
1 file changed
the system policy for ECRC.
Signed-off-by: Vidya Sagar
---
V2:
* Addressed Jingoo's review comment
* Removed saving 'td' bit information in 'dw_pcie' structure
drivers/pci/controller/dwc/pcie-designware.c | 8 ++--
drivers/pci/controller/dwc/pcie-designware.h | 1 +
2 files changed, 7
Adds pcie_is_ecrc_enabled() API to let other sub-systems (like DesignWare)
to query if ECRC policy is enabled and perform any configuration
required in those respective sub-systems.
Signed-off-by: Vidya Sagar
---
V2:
* None from V1
drivers/pci/pci.h | 2 ++
drivers/pci/pcie/aer.c | 11
identified as an issue with DesignWare
IP version 4.90a. DWC code queries the PCIe sub-system through the API added
in Patch-1 to find out if ECRC is turned on or not and configures ATU
accordingly.
V2:
* Addressed Jingoo's review comments
Vidya Sagar (2):
PCI/AER: Add pcie_is_ecrc_enabled() API
On 10/26/2020 2:19 AM, Jingoo Han wrote:
External email: Use caution opening links or attachments
On 10/25/20, 3:31 AM, Vidya Sagar wrote:
DesignWare core has a TLP digest (TD) override bit in one of the control
registers of ATU. This bit also needs to be programmed for proper ECRC
Set the DesignWare IP version for Tegra194 to 0x490A. This would be used
by the DesigWare sub-system to do any version specific configuration
(Ex:- TD bit programming for ECRC).
Signed-off-by: Vidya Sagar
---
drivers/pci/controller/dwc/pcie-tegra194.c | 1 +
1 file changed, 1 insertion(+)
diff
are
returning error. That way, it is more closer to complete uninitialization.
It also adds checking return value for error for a cleaner exit path.
Signed-off-by: Vidya Sagar
---
drivers/pci/controller/dwc/pcie-tegra194.c | 45 ++
1 file changed, 20 insertions(+), 25 deletions(-)
diff
This series of patches do some enhancements and some bug fixes to the
Tegra194 PCIe platform driver like
- Fixing Vendor-ID corruption
- Mapping DBI space correctly
- Updating DWC IP version
- Handling error conditions properly
Vidya Sagar (4):
PCI: tegra: Fix ASPM-L1SS advertisement disable
d Tegra194 PCIe support")
Signed-off-by: Vidya Sagar
---
drivers/pci/controller/dwc/pcie-tegra194.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c
b/drivers/pci/controller/dwc/pcie-tegra194.c
index aa511ec0d800.
configuration space.
Signed-off-by: Vidya Sagar
---
drivers/pci/controller/dwc/pcie-tegra194.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c
b/drivers/pci/controller/dwc/pcie-tegra194.c
index b172b1d49713..7a0c64436861 100644
Fix the device-tree entry that represents I/O High Voltage property
by replacing 'nvidia,io-high-voltage' with 'nvidia,io-hv' as the former
entry is deprecated.
Fixes: dbb72e2c305b ("arm64: tegra: Add configuration for PCIe C5 sideband
signals")
Signed-off-by: Vidya Sagar
---
arch/
Correct the name of the I/O High Voltage Property from
'nvidia,io-high-voltage' to 'nvidia,io-hv'.
Fixes: 2585a584f844 ("pinctrl: Add Tegra194 pinctrl DT bindings")
Signed-off-by: Vidya Sagar
---
.../devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.txt | 2 +-
1 file changed, 1
identified as an issue with DesignWare
IP version 4.90a. DWC code queries the PCIe sub-system through the API added
in Patch-1 to find out if ECRC is turned on or not and configures ATU
accordingly.
Vidya Sagar (2):
PCI/AER: Add pcie_is_ecrc_enabled() API
PCI: dwc: Add support to configure
Adds pcie_is_ecrc_enabled() API to let other sub-systems (like DesignWare)
to query if ECRC policy is enabled and perform any configuration
required in those respective sub-systems.
Signed-off-by: Vidya Sagar
---
drivers/pci/pci.h | 2 ++
drivers/pci/pcie/aer.c | 11 +++
2 files
the system policy for ECRC.
Signed-off-by: Vidya Sagar
---
drivers/pci/controller/dwc/pcie-designware.c | 8 ++--
drivers/pci/controller/dwc/pcie-designware.h | 2 ++
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware.c
b/drivers/pci
Previously ASPM L1-Sub-States control registers (CTL1 and CTL2) weren't
saved and restored during suspend/resume leading to ASPM-L1SS
configuration being lost post resume.
Save the ASPM-L1SS control registers so that the configuration is retained
post resume.
Signed-off-by: Vidya Sagar
---
v1
As per PCIe spec r5.0, sec 7.5.1.3.8 only 32-bit BAR registers are defined
for non-prefetchable memory and hence a warning should be reported when
the size of them go beyond 32-bits.
Signed-off-by: Vidya Sagar
---
drivers/pci/of.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers
specified and adds support for
mapping prefetchable aperture using ATU region-3 if required.
Fixes: 0f71c60ffd26 ("PCI: dwc: Remove storing of PCI resources")
Link:
http://patchwork.ozlabs.org/project/linux-pci/patch/20200513190855.23318-1-vid...@nvidia.com/
Signed-off-by: Vidya Sagar
---
C
the ATU to handle higher
(i.e. >4GB) sizes and then finally adds support for differentiating
between prefetchable and non-prefetchable regions and configuring one of
the ATU regions for prefetchable memory translations purpose.
Vidya Sagar (3):
PCI: of: Warn if non-prefetchable memory aperture s
Add support to program the ATU to enable translations for >4GB sizes of
the prefetchable memory apertures.
Signed-off-by: Vidya Sagar
---
drivers/pci/controller/dwc/pcie-designware.c | 12 +++-
drivers/pci/controller/dwc/pcie-designware.h | 3 ++-
2 files changed, 9 insertions(+)
On 10/23/2020 9:07 PM, Rob Herring wrote:
External email: Use caution opening links or attachments
On Fri, Oct 23, 2020 at 2:38 AM Vidya Sagar wrote:
On 10/23/2020 12:38 AM, Rob Herring wrote:
External email: Use caution opening links or attachments
On Tue, Oct 20, 2020 at 2:59 PM
On 10/23/2020 12:38 AM, Rob Herring wrote:
External email: Use caution opening links or attachments
On Tue, Oct 20, 2020 at 2:59 PM Vidya Sagar wrote:
DWC sub-system currently doesn't differentiate between prefetchable and
non-prefetchable memory aperture entries in the 'ranges' property
specified and adds support for
mapping prefetchable aperture using ATU region-3 if required.
Fixes: 0f71c60ffd26 ("PCI: dwc: Remove storing of PCI resources")
Link:
http://patchwork.ozlabs.org/project/linux-pci/patch/20200513190855.23318-1-vid...@nvidia.com/
Signed-off-by: Vidya Sagar
---
On 10/20/2020 6:50 PM, Lorenzo Pieralisi wrote:
External email: Use caution opening links or attachments
On Mon, Oct 19, 2020 at 11:21:54AM +0530, Vidya Sagar wrote:
Hi Lorenzo, Rob, Gustavo,
Could you please review this change?
Next cycle - we are in the middle of the merge window and I
Hi Lorenzo, Rob, Gustavo,
Could you please review this change?
Thanks,
Vidya Sagar
On 10/5/2020 5:43 PM, Vidya Sagar wrote:
Use ATU region-3 and region-0 to setup mapping for prefetchable and
non-prefetchable memory regions respectively only if their respective CPU
and bus addresses
for even those legacy PCIe devices with only
32-bit MSI capability?
- Vidya Sagar
If no DWC users have that problem and the current code is working well
enough, then I see little reason not to make this partucular change to
tidy up the implementation, just bear in mind that there's always
On 9/24/2020 4:37 PM, Jisheng Zhang wrote:
External email: Use caution opening links or attachments
Currently, dw_pcie_msi_init() allocates and maps page for msi, then
program the PCIE_MSI_ADDR_LO and PCIE_MSI_ADDR_HI. The Root Complex
may lose power during suspend-to-RAM, so when we
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