On 09/17/2015 06:15 AM, Stephen Boyd wrote:
On 09/16, Vince Hsu wrote:
From: Vince Hsu
The commit e770940218028c6a5927fda45f2ca9db5d9b35e0 ("clk: tegra: dfll:
Properly protect OPP list") added the rcu_read_{lock,unlock} but missed
one in the error path. So add the missing one.
From: Vince Hsu
The commit e770940218028c6a5927fda45f2ca9db5d9b35e0 ("clk: tegra: dfll:
Properly protect OPP list") added the rcu_read_{lock,unlock} but missed
one in the error path. So add the missing one.
Signed-off-by: Vince Hsu
---
Hi,
I noticed the missed unlock because we had
Hi Philipp,
On 03/12/2015 11:01 PM, Philipp Zabel wrote:
Hi Vince,
Am Donnerstag, den 12.03.2015, 20:15 +0800 schrieb Vince Hsu:
Add of_reset_control_get_by_index() to allow the drivers to get reset device
without knowing its name.
I see this is useful in the case of PM domain drivers that
Hi,
On 03/12/2015 08:45 PM, Thierry Reding wrote:
* PGP Signed by an unknown key
On Thu, Mar 12, 2015 at 08:15:18PM +0800, Vince Hsu wrote:
We switch to generic power domain now. So remove the legacy functions.
Signed-off-by: Vince Hsu
---
drivers/soc/tegra/pmc.c | 68
Cc'd Hans.
Thanks,
Vince
On 03/12/2015 08:19 PM, Tejun Heo wrote:
On Thu, Mar 12, 2015 at 08:15:15PM +0800, Vince Hsu wrote:
We have the generic PM domain support for Tegra SoCs now. So remove the
duplicated sequence here.
Signed-off-by: Vince Hsu
Can you please repost this patch w/
This patch adds the hot reset register table and flush related callback
functions for Tegra114.
Signed-off-by: Vince Hsu
---
drivers/memory/tegra/mc.h | 5 ++
drivers/memory/tegra/tegra114.c | 104
2 files changed, 109 insertions(+)
diff --git a
From: Thierry Reding
The PM domains are populated from DT, and the PM domain consumer devices are
also bound to their relevant PM domains by DT.
Signed-off-by: Thierry Reding
[vinceh: make changes based on Thierry and Peter's suggestions]
Signed-off-by: Vince Hsu
---
v2: revise comme
We switch to generic power domain now. So remove the legacy functions.
Signed-off-by: Vince Hsu
---
drivers/soc/tegra/pmc.c | 68 -
include/soc/tegra/pmc.h | 22
2 files changed, 90 deletions(-)
diff --git a/drivers/soc/tegra
We have the generic PM domain support for Tegra SoCs now. So remove the
duplicated power sequence here.
Signed-off-by: Vince Hsu
---
v2: enable pex clock when powering on
drivers/pci/host/pci-tegra.c | 22 +++---
1 file changed, 3 insertions(+), 19 deletions(-)
diff --git a
Add power supply information which is board dependent for GK20A.
Signed-off-by: Vince Hsu
---
arch/arm/boot/dts/tegra124-jetson-tk1.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts
b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
index
We have the generic PM domain support for Tegra SoCs now. So remove the
duplicated power sequence here.
Signed-off-by: Vince Hsu
---
drivers/gpu/drm/tegra/gr3d.c | 32
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/tegra/gr3d.c b
We have added generic power domain support for Tegra SoCs. So now the option
PM_GENERIC_DOMAINS must be enabled by default to have proper power sequence.
Signed-off-by: Vince Hsu
---
arch/arm/mach-tegra/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-tegra/Kconfig b
This patch adds the hot reset register table and flush related callback
functions for Tegra124.
Signed-off-by: Vince Hsu
---
v2: move the drop of tegra124_mc_clients' const to patch #2
move mc flush operations to tegra114
drivers/memory/tegra/tegra124.c
The flush operation of memory clients is needed for various IP blocks in
the Tegra SoCs to perform a clean reset. Also add a mutex in struct tegra_mc
for mc flush operations.
Signed-off-by: Vince Hsu
---
v2: make indentition and name changes according to Alex's comments
add mutex lo
We have the generic PM domain support for Tegra SoCs now. So remove the
duplicated power sequence here.
Signed-off-by: Vince Hsu
---
drivers/gpu/drm/tegra/dc.c | 46 +++---
1 file changed, 11 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm
We have the generic PM domain support for Tegra SoCs now. So remove the
duplicated sequence here.
Signed-off-by: Vince Hsu
---
drivers/ata/ahci_tegra.c | 11 ---
1 file changed, 11 deletions(-)
diff --git a/drivers/ata/ahci_tegra.c b/drivers/ata/ahci_tegra.c
index 3a62eb246d80
alarm, we don't use the lock for PLLD/PLLD2. Just wait 1ms and treat the
clocks as locked.
Signed-off-by: Vince Hsu
---
drivers/clk/tegra/clk-tegra114.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
Also bind the PM domain provider and consumer together.
Signed-off-by: Vince Hsu
---
arch/arm/boot/dts/tegra124.dtsi | 86 -
1 file changed, 85 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
Also bind the PM domain provider and consumer together.
Signed-off-by: Vince Hsu
---
arch/arm/boot/dts/tegra30.dtsi | 45 +-
1 file changed, 44 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
Also bind the PM domain provider and consumer together.
Signed-off-by: Vince Hsu
---
arch/arm/boot/dts/tegra114.dtsi | 43 -
1 file changed, 42 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
This patch adds the hot reset register table and flush related callback
functions for Tegra30.
Signed-off-by: Vince Hsu
---
drivers/memory/tegra/tegra30.c | 78 ++
1 file changed, 78 insertions(+)
diff --git a/drivers/memory/tegra/tegra30.c b/drivers
Add of_reset_control_get_by_index() to allow the drivers to get reset device
without knowing its name.
Signed-off-by: Vince Hsu
---
v2: minor changes according to Alex's comments
drivers/reset/core.c | 44 +---
include/linux/reset.h | 9 +++
perly.
v2:
* Add support for Tegra30/Tegra114
* Address Alex's comments
[1] http://www.spinics.net/lists/linux-tegra/msg21012.html
Thanks,
Vince
Thierry Reding (1):
soc: tegra: pmc: Add generic PM domain support
Vince Hsu (16):
reset: add of_reset_control_get_by_index()
memory: teg
On 01/07/2015 10:48 PM, Thierry Reding wrote:
* PGP Signed by an unknown key
On Wed, Jan 07, 2015 at 10:28:29PM +0800, Vince Hsu wrote:
On 04:08:52PM Jan 07, Peter De Schrijver wrote:
On Wed, Jan 07, 2015 at 02:27:10PM +0100, Thierry Reding wrote:
Yeah. I plan to have the information of
On 01/07/2015 11:12 PM, Thierry Reding wrote:
* PGP Signed by an unknown key
On Wed, Jan 07, 2015 at 10:19:52PM +0800, Vince Hsu wrote:
On 04:12:54PM Jan 07, Peter De Schrijver wrote:
On Wed, Jan 07, 2015 at 06:49:27PM +0800, Vince Hsu wrote:
On 01/07/2015 06:19 PM, Peter De Schrijver wrote
On 04:08:52PM Jan 07, Peter De Schrijver wrote:
> On Wed, Jan 07, 2015 at 02:27:10PM +0100, Thierry Reding wrote:
>
> > > Yeah. I plan to have the information of all the clock client of the
> > > partitions and
> > > the memory clients be defined statically in c source, e.g. pmc-tegra124.c.
> > >
On 04:12:54PM Jan 07, Peter De Schrijver wrote:
> On Wed, Jan 07, 2015 at 06:49:27PM +0800, Vince Hsu wrote:
> >
> > On 01/07/2015 06:19 PM, Peter De Schrijver wrote:
> > >On Mon, Jan 05, 2015 at 04:09:33PM +0100, Thierry Reding wrote:
> > >>* PGP Signed by an
On 01/07/2015 06:19 PM, Peter De Schrijver wrote:
On Mon, Jan 05, 2015 at 04:09:33PM +0100, Thierry Reding wrote:
* PGP Signed by an unknown key
On Thu, Dec 25, 2014 at 10:28:08AM +0800, Vince Hsu wrote:
On 12/24/2014 09:16 PM, Lucas Stach wrote:
Am Dienstag, den 23.12.2014, 18:39 +0800
On 04:27:52PM Jan 06, Thierry Reding wrote:
> * PGP Signed by an unknown key
>
> On Tue, Jan 06, 2015 at 11:07:45PM +0800, Vince Hsu wrote:
> > On 03:30:00PM Jan 06, Thierry Reding wrote:
> > > > Old Signed by an unknown key
> > >
> > > On Tue, Dec
On 03:30:00PM Jan 06, Thierry Reding wrote:
> * PGP Signed by an unknown key
>
> On Tue, Dec 23, 2014 at 06:39:56PM +0800, Vince Hsu wrote:
> > Signed-off-by: Vince Hsu
> > ---
> > drivers/memory/tegra/tegra124.c | 82
> >
On 02:55:52PM Jan 06, Thierry Reding wrote:
> * PGP Signed by an unknown key
>
> On Tue, Jan 06, 2015 at 08:13:01PM +0800, Vince Hsu wrote:
> >
> > On 01/06/2015 07:36 PM, Thierry Reding wrote:
> > >> Old Signed by an unknown key
> > >
> > >
On 02:29:32PM Jan 06, Thierry Reding wrote:
> * PGP Signed by an unknown key
>
> On Tue, Jan 06, 2015 at 08:03:03PM +0800, Vince Hsu wrote:
> > On 01/06/2015 07:15 PM, Thierry Reding wrote:
> > >> Old Signed by an unknown key
> > >
> > >On Tue, Jan
On 01/06/2015 07:49 PM, Thierry Reding wrote:
* PGP Signed by an unknown key
On Mon, Jan 05, 2015 at 08:50:18PM +0100, Alexandre Courbot wrote:
On Mon, Jan 5, 2015 at 4:32 PM, Thierry Reding wrote:
On Tue, Dec 30, 2014 at 11:18:34AM +0800, Vince Hsu wrote:
Hi Emil,
On 12/30/2014 10:34 AM
On 01/06/2015 07:36 PM, Thierry Reding wrote:
* PGP Signed by an unknown key
On Tue, Jan 06, 2015 at 05:34:01PM +0800, Vince Hsu wrote:
On 01/05/2015 11:25 PM, Thierry Reding wrote:
Old Signed by an unknown key
On Thu, Dec 25, 2014 at 10:42:58AM +0800, Vince Hsu wrote:
On 12/24/2014 09:23
On 01/06/2015 07:15 PM, Thierry Reding wrote:
* PGP Signed by an unknown key
On Tue, Jan 06, 2015 at 10:11:41AM +0800, Vince Hsu wrote:
On 01/05/2015 11:09 PM, Thierry Reding wrote:
Old Signed by an unknown key
On Thu, Dec 25, 2014 at 10:28:08AM +0800, Vince Hsu wrote:
On 12/24/2014 09:16
On 01/06/2015 03:50 AM, Alexandre Courbot wrote:
On Mon, Jan 5, 2015 at 4:32 PM, Thierry Reding wrote:
On Tue, Dec 30, 2014 at 11:18:34AM +0800, Vince Hsu wrote:
Hi Emil,
On 12/30/2014 10:34 AM, Emil Velikov wrote:
On 23/12/14 10:40, Vince Hsu wrote:
This patch adds some checks in the
On 01/05/2015 11:25 PM, Thierry Reding wrote:
* PGP Signed by an unknown key
On Thu, Dec 25, 2014 at 10:42:58AM +0800, Vince Hsu wrote:
On 12/24/2014 09:23 PM, Lucas Stach wrote:
Am Dienstag, den 23.12.2014, 18:39 +0800 schrieb Vince Hsu:
This patch adds some missing pieces of the rail
On 01/05/2015 11:09 PM, Thierry Reding wrote:
* PGP Signed by an unknown key
On Thu, Dec 25, 2014 at 10:28:08AM +0800, Vince Hsu wrote:
On 12/24/2014 09:16 PM, Lucas Stach wrote:
Am Dienstag, den 23.12.2014, 18:39 +0800 schrieb Vince Hsu:
The Tegra124 and later Tegra SoCs have a sepatate
On 12/31/2014 12:42 AM, Lucas Stach wrote:
Am Montag, den 29.12.2014, 10:49 +0800 schrieb Vince Hsu:
[...]
That's a read fence to assure the post of the previous writes through
Tegra interconnect. (copy-paster from
https://android.googlesource.com/kernel/tegr
Hi Emil,
On 12/30/2014 10:34 AM, Emil Velikov wrote:
On 23/12/14 10:40, Vince Hsu wrote:
This patch adds some checks in the suspend/resume functions to distinguish
the dGPU and mobile GPU and exports some variables/functions so that the
nouveau platform device can reuse them.
Hi Vince
On 12/26/2014 04:34 AM, Lucas Stach wrote:
Am Donnerstag, den 25.12.2014, 10:28 +0800 schrieb Vince Hsu:
On 12/24/2014 09:16 PM, Lucas Stach wrote:
Am Dienstag, den 23.12.2014, 18:39 +0800 schrieb Vince Hsu:
The Tegra124 and later Tegra SoCs have a sepatate rail gating register
to enable
On 12/24/2014 09:23 PM, Lucas Stach wrote:
Am Dienstag, den 23.12.2014, 18:39 +0800 schrieb Vince Hsu:
This patch adds some missing pieces of the rail gaing/ungating sequence that
can improve the stability in theory.
Signed-off-by: Vince Hsu
---
drm/nouveau_platform.c | 42
On 12/24/2014 09:16 PM, Lucas Stach wrote:
Am Dienstag, den 23.12.2014, 18:39 +0800 schrieb Vince Hsu:
The Tegra124 and later Tegra SoCs have a sepatate rail gating register
to enable/disable the clamp. The original function
tegra_powergate_remove_clamping() is not sufficient for the enable
On 12/24/2014 09:52 PM, Dmitry Osipenko wrote:
I think "ARM: tegra:" is wrong prefix for this patch and "soc: tegra:" should be
used instead to show that it belongs to SoC driver, not arch code.
Indeed. Will fix in v2.
Thanks,
Vince
--
To unsubscribe from this list: send the line "unsubscribe
that explicitly.
Signed-off-by: Vince Hsu
---
Hi,
This fixes a regression found on 3.19-rc1. The USB host can't be probed and
the USB failed on Jetson TK1.
Thanks,
Vince
drivers/usb/host/ehci-tegra.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/host/eh
Hi,
On 12/24/2014 12:39 AM, Ilia Mirkin wrote:
On Tue, Dec 23, 2014 at 5:40 AM, Vince Hsu wrote:
This is a workaround to avoid the instmem backup/restore during the suspend
and resume process in nv50 instemem driver.
Signed-off-by: Vince Hsu
---
drm/Kbuild| 1 +
nvkm
The flush operation of memory clients is needed for various IP blocks in
the Tegra SoCs to perform a clean reset.
Signed-off-by: Vince Hsu
---
drivers/memory/tegra/mc.c | 21 +
include/soc/tegra/mc.h| 23 ++-
2 files changed, 43 insertions(+), 1
Signed-off-by: Vince Hsu
---
drivers/memory/tegra/tegra124.c | 82 +
1 file changed, 82 insertions(+)
diff --git a/drivers/memory/tegra/tegra124.c b/drivers/memory/tegra/tegra124.c
index 278d40b854c1..036935743a0a 100644
--- a/drivers/memory/tegra
Signed-off-by: Vince Hsu
---
drm/nouveau_platform.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drm/nouveau_platform.c b/drm/nouveau_platform.c
index b307bbedd4c4..68788b17a45c 100644
--- a/drm/nouveau_platform.c
+++ b/drm/nouveau_platform.c
@@ -53,7 +53,7 @@ static int
27;s
tree (http://cgit.freedesktop.org/~darktama/nouveau).
Thanks,
Vince
Vince Hsu (4): (linux-next-20141219)
ARM: tegra: add function to control the GPU rail clamp
memory: tegra: add mc flush support
memory: tegra: add flush operation for Tegra124 memory clients
ARM: tegra: add mc node for Tegra124 GPU
ar
rgate ID since the GPU ID makes no
sense here.
Signed-off-by: Vince Hsu
---
drivers/soc/tegra/pmc.c | 34 +++---
include/soc/tegra/pmc.h | 2 ++
2 files changed, 25 insertions(+), 11 deletions(-)
diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
The Tegra124 GPU needs the memory controller for the memory flush operatoin.
So add the node reference of memory controller in device tree.
Signed-off-by: Vince Hsu
---
arch/arm/boot/dts/tegra124.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm
This patch adds some missing pieces of the rail gaing/ungating sequence that
can improve the stability in theory.
Signed-off-by: Vince Hsu
---
drm/nouveau_platform.c | 42 ++
drm/nouveau_platform.h | 3 +++
2 files changed, 45 insertions(+)
diff --git a
This patch adds some checks in the suspend/resume functions to distinguish
the dGPU and mobile GPU and exports some variables/functions so that the
nouveau platform device can reuse them.
Signed-off-by: Vince Hsu
---
drm/nouveau_drm.c | 16 +++-
drm/nouveau_drm.h | 2 ++
2 files
The runtime suspend/resume flow is almost the same as the suspend/resume
except the the arguments passed to nouveau_do_{suspend,resume}.
Signed-off-by: Vince Hsu
---
drm/nouveau_platform.c | 70 ++
1 file changed, 70 insertions(+)
diff --git a
This is a workaround to avoid the instmem backup/restore during the suspend
and resume process in nv50 instemem driver.
Signed-off-by: Vince Hsu
---
drm/Kbuild| 1 +
nvkm/engine/device/nve0.c | 2 +-
nvkm/include/subdev/instmem.h | 1 +
nvkm/subdev/instmem/gk20a.c
We reuse most of the suspend/resume functions of the dGPU for nouveau
platform device. Only the power up/down sequences need to be handled
separately.
Signed-off-by: Vince Hsu
---
drm/nouveau_platform.c | 60 ++
1 file changed, 60 insertions
The GK20A needs to create a dummy instemem subdev to avoid suspend/resume
problem. So make the nv50_instmem_priv non-static for now.
Signed-off-by: Vince Hsu
---
drm/core/subdev/instmem/nv50.h | 1 +
nvkm/subdev/instmem/nv50.c | 9 ++---
nvkm/subdev/instmem/nv50.h | 14
For GK20A we need the GPU speedo value to calculate voltage levels.
Signed-off-by: Vince Hsu
---
drm/nouveau_platform.c | 2 ++
drm/nouveau_platform.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/drm/nouveau_platform.c b/drm/nouveau_platform.c
index 9945c2ec2ca3..8871a21ad8fc 100644
Move the vbios parsing out of init() and call it conditionally if the
platform has a vbios. Non-vbios platforms can use the ctor() to init the
data structures.
Signed-off-by: Vince Hsu
Acked-by: Alexandre Courbot
Acked-by: Martin Peres
---
v3: steal Martin's commit message and add his
The voltage value are calculated by the hardware characterized
result.
Signed-off-by: Vince Hsu
Reviewed-by: Alexandre Courbot
Acked-by: Martin Peres
---
v3: remove the tegra fuse dependency
v2: add Alex's Reviewed-by
drm/Kbuild | 1 +
drm/core/subdev/volt/gk20a.c
Some Tegra drivers might be compiled as kernel modules, and they need the
fuse information for initialization. One example is the GK20A Nouveau
driver. It needs the GPU speedo value to calculate frequency-voltage
table. So export the tegra_sku_info.
Signed-off-by: Vince Hsu
Acked-by: Alexandre
Signed-off-by: Vince Hsu
Acked-by: Alexandre Courbot
---
v2: add Alex's Acked-by
nvkm/subdev/volt/base.c | 67 -
1 file changed, 38 insertions(+), 29 deletions(-)
diff --git a/nvkm/subdev/volt/base.c b/nvkm/subdev/volt/base.c
index 32794a9
The voltage value are calculated by the hardware characterized
result.
Signed-off-by: Vince Hsu
Reviewed-by: Alexandre Courbot
---
v2: add Alex's Reviewed-by
drm/Kbuild | 1 +
drm/core/subdev/volt/gk20a.c | 1 +
nvkm/engine/device/nve0.c| 1 +
nvkm/include/s
Some Tegra drivers might be compiled as kernel modules, and they need the
fuse information for initialization. One example is the GK20A Nouveau
driver. It needs the GPU speedo value to calculate frequency-voltage
table. So export the tegra_sku_info.
Signed-off-by: Vince Hsu
Acked-by: Alexandre
Signed-off-by: Vince Hsu
---
Resend this patch with the fuse change and proper patch prefix
per Thierry's request.
nvkm/subdev/volt/base.c | 67 -
1 file changed, 38 insertions(+), 29 deletions(-)
diff --git a/nvkm/subdev/volt/base.c b
Some Tegra drivers might be complied as kernel modules, and
they need the fuse information for initialization. One
example is the GK20A Nouveau driver. It needs the GPU speedo
value to calculate frequency-voltage table. So export
the tegra_sku_info.
Signed-off-by: Vince Hsu
---
v2: add more
The voltage value are calculated by the hardware characterized
result.
Signed-off-by: Vince Hsu
---
Resend this patch with the fuse change and proper patch prefix
per Thierry's request.
drm/Kbuild | 1 +
drm/core/subdev/volt/gk20a.c | 1 +
nvkm/engine/device/n
Some Tegra drivers might be complied as kernel modules, and
they need the fuse information for initialization. One
example is the GK20A Nouveau driver. It needs the GPU speedo
value to calculate frequency-voltage table. So export
the tegra_sku_info.
Signed-off-by: Vince Hsu
---
v2: add more
Signed-off-by: Vince Hsu
---
drivers/soc/tegra/fuse/fuse-tegra.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/soc/tegra/fuse/fuse-tegra.c
b/drivers/soc/tegra/fuse/fuse-tegra.c
index 11a5043959dc..011a3363c265 100644
--- a/drivers/soc/tegra/fuse/fuse-tegra.c
+++ b/drivers/soc
Hi Viresh,
Just sent v2 with your ACK. :)
Hi Rafael,
Could you please apply the v2? Thanks!
Vince
On 11/10/2014 01:09 PM, Viresh Kumar wrote:
On 28 October 2014 08:55, Vince Hsu wrote:
Hi Viresh,
Could you remind me where can I find this patch upstream? It seems this was
missed?
Rafael
vers' status.
Signed-off-by: Vince Hsu
Acked-by: Viresh Kumar
---
v2: added Viresh's Acked-by
drivers/cpufreq/cpufreq.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/cpufreq/cpufreq.c b/drivers/cpufreq/cpufreq.c
index 644b54e1e7d1..0721ab352e
Hi Viresh,
Could you remind me where can I find this patch upstream? It seems this
was missed?
Thanks,
Vince
On 10/06/2014 12:50 PM, Vince Hsu wrote:
Hi Viresh,
On 10/06/2014 12:45 PM, Viresh Kumar wrote:
On 2 October 2014 12:25, Vince Hsu wrote:
When the user space tries to set
Hi Viresh,
On 10/06/2014 12:45 PM, Viresh Kumar wrote:
On 2 October 2014 12:25, Vince Hsu wrote:
When the user space tries to set scaling_(max|min)_freq through
sysfs, the cpufreq_set_policy() asks other driver's opinions
for the max/min frequencies. Some device drivers, like Tegra
CP
vers' status.
Signed-off-by: Vince Hsu
---
Hi,
I'm not sure if any platform that is supported mainlin might have this
issue, and this patch is complie tested only. We hit the problem when
the laptop_mode tool configures the scaling_max_freq and the Tegra
CPU EDP driver is limiting the C
Hi,
On 08/19/2014 11:33 AM, Tuomas Tynkkynen wrote:
From: Tuomas Tynkkynen
With closed loop support, the clock rate of the DFLL can be adjusted.
The oscillator itself in the DFLL is a free-running oscillator whose
rate is directly determined the supply voltage. However, the DFLL
module contai
ually it's pretty easy to misuse
the dfll read/write/wmb functions. We might want to have some generic
functions for these, and let the generic functions handle the offset to
different register blocks.
commit 4a1fdd54141b4f8f9425d54cdad13c42763e6186
Author: Vince Hsu
Date: Thu Aug 14
Hi,
On 07/21/2014 11:38 PM, Tuomas Tynkkynen wrote:
With closed loop support, the clock rate of the DFLL can be adjusted.
The oscillator itself in the DFLL is a free-running oscillator whose
rate is directly determined the supply voltage. However, the DFLL
module contains logic to compare the D
Hi,
On 07/21/2014 11:38 PM, Tuomas Tynkkynen wrote:
Add shared code to support the Tegra DFLL clocksource in open-loop
mode. This root clocksource is present on the Tegra124 SoCs. The
DFLL is the intended primary clock source for the fast CPU cluster.
This code is very closely based on a patch
Hi,
On 07/21/2014 11:38 PM, Tuomas Tynkkynen wrote:
Add basic platform driver support for the fast CPU cluster DFLL
clocksource found on Tegra124 SoCs. This small driver selects the
appropriate Tegra124-specific characterization data and integration
code. It relies on the DFLL common code to do
Simple fix to set the correct current limit for SD0/1/6.
Signed-off-by: Vince Hsu
---
drivers/regulator/as3722-regulator.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/regulator/as3722-regulator.c
b/drivers/regulator/as3722-regulator.c
index 5917fe3dc983
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