[PATCH v3 6/9] misc: xilinx-ai-engine: add request and release tiles
Add request/release and related clock gating functions to AI engine
driver:
* scanning when the partition is being requested to know which tiles
are in use.
* check if a tile is gated or not
* tiles requesting and releasing ioctl so that user application can
enable/disable tiles at runtime.
Signed-off-by: Wendy Liang
Reviewed-by: Hyun Kwon
---
drivers/misc/xilinx-ai-engine/Makefile | 1 +
drivers/misc/xilinx-ai-engine/ai-engine-aie.c | 225 +++
drivers/misc/xilinx-ai-engine/ai-engine-clock.c| 245 +
drivers/misc/xilinx-ai-engine/ai-engine-dev.c | 19 +-
drivers/misc/xilinx-ai-engine/ai-engine-internal.h | 34 +++
drivers/misc/xilinx-ai-engine/ai-engine-part.c | 32 +++
drivers/misc/xilinx-ai-engine/ai-engine-res.c | 51 +
include/uapi/linux/xlnx-ai-engine.h| 31 +++
8 files changed, 631 insertions(+), 7 deletions(-)
create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-clock.c
diff --git a/drivers/misc/xilinx-ai-engine/Makefile
b/drivers/misc/xilinx-ai-engine/Makefile
index 1b743fa..2e67b25 100644
--- a/drivers/misc/xilinx-ai-engine/Makefile
+++ b/drivers/misc/xilinx-ai-engine/Makefile
@@ -6,6 +6,7 @@
obj-$(CONFIG_XILINX_AIE) += xilinx-aie.o
xilinx-aie-$(CONFIG_XILINX_AIE) := ai-engine-aie.o \
+ ai-engine-clock.o \
ai-engine-dev.o \
ai-engine-dma.o \
ai-engine-mem.o \
diff --git a/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
b/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
index ac95aff..ff721b3 100644
--- a/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
+++ b/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
@@ -41,6 +41,9 @@
#define AIE_SHIMPL_SHIMRST_MASK0x1U
#define AIE_SHIMPL_COLRST_MASK 0x1U
#define AIE_SHIMPL_CLKCNTR_COLBUF_MASK 0x1U
+#define AIE_SHIMPL_CLKCNTR_NEXTCLK_MASKBIT(1)
+#define AIE_TILE_CLKCNTR_COLBUF_MASK BIT(0)
+#define AIE_TILE_CLKCNTR_NEXTCLK_MASK BIT(1)
/*
* AI engine SHIM reset ID.
@@ -221,10 +224,232 @@ static int aie_reset_shim(struct aie_device *adev,
struct aie_range *range)
return 0;
}
+static int aie_init_part_clk_state(struct aie_partition *apart)
+{
+ int ret, num_tiles;
+
+ num_tiles = apart->range.size.col * (apart->range.size.row - 1);
+
+ ret = aie_resource_initialize(>cores_clk_state, num_tiles);
+ if (ret) {
+ dev_err(>dev,
+ "failed to initialize cores clock state resource.\n");
+ return ret;
+ }
+
+ ret = aie_resource_initialize(>tiles_inuse, num_tiles);
+ if (ret) {
+ dev_err(>dev,
+ "failed to initialize tiles in use resource.\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int aie_scan_part_clocks(struct aie_partition *apart)
+{
+ struct aie_device *adev = apart->adev;
+ struct aie_range *range = >range;
+ struct aie_location loc;
+
+ /* Clear the bitmap of cores and memories clock state */
+ aie_resource_put_region(>cores_clk_state, 0,
+ apart->cores_clk_state.total);
+
+ for (loc.col = range->start.col;
+loc.col < range->start.col + range->size.col;
+loc.col++) {
+ for (loc.row = range->start.row;
+loc.row < range->start.row + range->size.row - 1;
+loc.row++) {
+ void __iomem *va;
+ u32 val, nbitpos;
+
+ /*
+* Reading registers of the current tile to see the next
+* tile is clock gated.
+*/
+ nbitpos = loc.col * (range->size.row - 1) + loc.row;
+
+ if (aie_get_tile_type() != AIE_TILE_TYPE_TILE) {
+ /* Checks shim tile for next core tile */
+ va = adev->base +
+aie_cal_regoff(adev, loc,
+ AIE_SHIMPL_CLKCNTR_REGOFF);
+ val = ioread32(va);
+
+ /*
+* check if the clock buffer and the next clock
+* tile is set, if one of them is not set, the
+* tiles of the column are clock gated.
+*/
+ if (!(val & AIE_SHIMPL_CLKCNTR_COLBUF_MASK) ||
+ !(val & AIE_SHIMPL_CLKCNTR_NEXTCLK_MASK))
+ break;
+
+ /* Set
[PATCH v3 9/9] misc: xilinx-ai-engine: Add support for servicing error interrupts
From: Nishad Saraf
AI engine errors events can be routed to generate interrupt. The
errors events routing will be done during AI engine configuration.
At runtime, Linux kernel AI engine driver monitors the interrupt and
backtracks errors events.
As error events from 400 AIE tiles and 50 shim tiles are channeled on
a single interrupt line, backtracking the source the interrupt to an
AIE module is required. To keep the top-half interrupt short,
backtracking is deferred to bottom half by scheduling a task in shared
workqueue.
Signed-off-by: Nishad Saraf
Signed-off-by: Wendy Liang
---
drivers/misc/xilinx-ai-engine/Makefile | 1 +
drivers/misc/xilinx-ai-engine/ai-engine-aie.c | 121
drivers/misc/xilinx-ai-engine/ai-engine-dev.c | 14 +
drivers/misc/xilinx-ai-engine/ai-engine-internal.h | 144 +
.../misc/xilinx-ai-engine/ai-engine-interrupt.c| 659 +
drivers/misc/xilinx-ai-engine/ai-engine-part.c | 44 ++
drivers/misc/xilinx-ai-engine/ai-engine-res.c | 54 ++
7 files changed, 1037 insertions(+)
create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-interrupt.c
diff --git a/drivers/misc/xilinx-ai-engine/Makefile
b/drivers/misc/xilinx-ai-engine/Makefile
index 2e67b25..9607ecb 100644
--- a/drivers/misc/xilinx-ai-engine/Makefile
+++ b/drivers/misc/xilinx-ai-engine/Makefile
@@ -9,6 +9,7 @@ xilinx-aie-$(CONFIG_XILINX_AIE) := ai-engine-aie.o \
ai-engine-clock.o \
ai-engine-dev.o \
ai-engine-dma.o \
+ ai-engine-interrupt.o \
ai-engine-mem.o \
ai-engine-part.o \
ai-engine-res.o \
diff --git a/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
b/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
index ff721b3..af0f997 100644
--- a/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
+++ b/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
@@ -33,7 +33,10 @@
#define AIE_SHIMPL_CLKCNTR_REGOFF 0x00036040U
#define AIE_SHIMPL_COLRESET_REGOFF 0x00036048U
#define AIE_SHIMPL_RESET_REGOFF0x0003604cU
+#define AIE_SHIMPL_GROUP_ERROR_REGOFF 0x0003450cU
#define AIE_TILE_CORE_CLKCNTR_REGOFF 0x00036040U
+#define AIE_TILE_CORE_GROUP_ERROR_REGOFF 0x00034510U
+#define AIE_TILE_MEM_GROUP_ERROR_REGOFF0x00014514U
/*
* Register masks
@@ -93,11 +96,27 @@ static const struct aie_tile_regs aie_kernel_regs[] = {
.soff = AIE_SHIMPL_CLKCNTR_REGOFF,
.eoff = AIE_SHIMPL_CLKCNTR_REGOFF,
},
+ /* SHIM group error enable */
+ {.attribute = (AIE_TILE_TYPE_SHIMPL | AIE_TILE_TYPE_SHIMNOC) <<
+ AIE_REGS_ATTR_TILE_TYPE_SHIFT,
+.soff = AIE_SHIMPL_GROUP_ERROR_REGOFF,
+.eoff = AIE_SHIMPL_GROUP_ERROR_REGOFF,
+ },
/* Tile clock control */
{.attribute = AIE_TILE_TYPE_TILE << AIE_REGS_ATTR_TILE_TYPE_SHIFT,
.soff = AIE_TILE_CORE_CLKCNTR_REGOFF,
.eoff = AIE_TILE_CORE_CLKCNTR_REGOFF,
},
+ /* Tile group error for core module */
+ {.attribute = AIE_TILE_TYPE_TILE << AIE_REGS_ATTR_TILE_TYPE_SHIFT,
+.soff = AIE_TILE_CORE_GROUP_ERROR_REGOFF,
+.eoff = AIE_TILE_CORE_GROUP_ERROR_REGOFF,
+ },
+ /* Tile group error for memory module */
+ {.attribute = AIE_TILE_TYPE_TILE << AIE_REGS_ATTR_TILE_TYPE_SHIFT,
+.soff = AIE_TILE_MEM_GROUP_ERROR_REGOFF,
+.eoff = AIE_TILE_MEM_GROUP_ERROR_REGOFF,
+ },
};
static const struct aie_single_reg_field aie_col_rst = {
@@ -128,6 +147,103 @@ static const struct aie_dma_attr aie_shimdma = {
.bd_len = 0x14U,
};
+static const struct aie_event_attr aie_pl_event = {
+ .bc_event = {
+ .mask = GENMASK(6, 0),
+ .regoff = 0x0U,
+ },
+ .group_error = {
+ .mask = GENMASK(10, 0),
+ .regoff = 0xcU,
+ },
+ .bc_regoff = 0x34010U,
+ .status_regoff = 0x34200U,
+ .group_regoff = 0x34500U,
+ .base_error_event = 62U,
+ .num_broadcasts = 16U,
+ .base_bc_event = 107U,
+ .num_events = 128U,
+};
+
+static const struct aie_event_attr aie_mem_event = {
+ .bc_event = {
+ .mask = GENMASK(6, 0),
+ .regoff = 0x0U,
+ },
+ .group_error = {
+ .mask = GENMASK(13, 0),
+ .regoff = 0x14U,
+ },
+ .bc_regoff = 0x14010U,
+ .status_regoff = 0x14200U,
+ .group_regoff = 0x14500U,
+ .base_error_event = 87U,
+ .num_broadcasts = 16U,
+ .base_bc_event = 107U,
+ .num_events = 128U,
+};
+
+static const struct aie_event_attr aie_core_event = {
+ .bc_event = {
+ .mask = GENMASK(6, 0),
+
[PATCH v3 4/9] misc: xilinx-ai-engine: expose AI engine tile memories to userspace
There is no concern to have userspace to directly access AI engine
program and data memories. It will be much faster to directly copy
data to and from these memories from userspace.
We choose to use DMA buf for the data and program memory because of the
DMA buf features. DMA buf can share the DMA memory between applications
and different devices, which can benefit on how to share data with AI
engine device in future.
There is one DMA buf per type of memory in an AI engine partition. e.g.
There is one DMA buf for all the tile core program memories in an AI
engine partition. There is another DMA buf for all the tile data
memories in an AI engine partition.
Signed-off-by: Wendy Liang
Reviewed-by: Hyun Kwon
---
drivers/misc/xilinx-ai-engine/Makefile | 1 +
drivers/misc/xilinx-ai-engine/ai-engine-aie.c | 36 +++
drivers/misc/xilinx-ai-engine/ai-engine-internal.h | 30 +++
drivers/misc/xilinx-ai-engine/ai-engine-mem.c | 275 +
drivers/misc/xilinx-ai-engine/ai-engine-part.c | 47
drivers/misc/xilinx-ai-engine/ai-engine-reset.c| 38 +++
include/uapi/linux/xlnx-ai-engine.h| 50
7 files changed, 477 insertions(+)
create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-mem.c
diff --git a/drivers/misc/xilinx-ai-engine/Makefile
b/drivers/misc/xilinx-ai-engine/Makefile
index 39bec61..2dbed42 100644
--- a/drivers/misc/xilinx-ai-engine/Makefile
+++ b/drivers/misc/xilinx-ai-engine/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_XILINX_AIE)+= xilinx-aie.o
xilinx-aie-$(CONFIG_XILINX_AIE) := ai-engine-aie.o \
ai-engine-dev.o \
+ ai-engine-mem.o \
ai-engine-part.o \
ai-engine-res.o \
ai-engine-reset.o
diff --git a/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
b/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
index 36127f0..7fce2f00 100644
--- a/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
+++ b/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
@@ -12,10 +12,14 @@
#include "ai-engine-internal.h"
+#define KBYTES(n) ((n) * 1024)
+
#define AIE_ARRAY_SHIFT30U
#define AIE_COL_SHIFT 23U
#define AIE_ROW_SHIFT 18U
+#define NUM_MEMS_PER_TILE 2U
+
/*
* Registers offsets
*/
@@ -114,6 +118,37 @@ static u32 aie_get_tile_type(struct aie_location *loc)
return AIE_TILE_TYPE_SHIMNOC;
}
+static unsigned int aie_get_mem_info(struct aie_range *range,
+struct aie_part_mem *pmem)
+{
+ unsigned int i;
+
+ if (range->start.row + range->size.row <= 1) {
+ /* SHIM row only, no memories in this range */
+ return 0;
+ }
+ if (!pmem)
+ return NUM_MEMS_PER_TILE;
+
+ for (i = 0; i < NUM_MEMS_PER_TILE; i++) {
+ struct aie_mem *mem = [i].mem;
+
+ memcpy(>range, range, sizeof(*range));
+ if (!mem->range.start.row) {
+ mem->range.start.row = 1;
+ mem->range.size.row--;
+ }
+ }
+ /* Setup tile data memory information */
+ pmem[0].mem.offset = 0;
+ pmem[0].mem.size = KBYTES(32);
+ /* Setup program memory information */
+ pmem[1].mem.offset = 0x2;
+ pmem[1].mem.size = KBYTES(16);
+
+ return NUM_MEMS_PER_TILE;
+}
+
/**
* aie_set_shim_reset() - Set AI engine SHIM reset
* @adev: AI engine device
@@ -170,6 +205,7 @@ static int aie_reset_shim(struct aie_device *adev, struct
aie_range *range)
static const struct aie_tile_operations aie_ops = {
.get_tile_type = aie_get_tile_type,
+ .get_mem_info = aie_get_mem_info,
.reset_shim = aie_reset_shim,
};
diff --git a/drivers/misc/xilinx-ai-engine/ai-engine-internal.h
b/drivers/misc/xilinx-ai-engine/ai-engine-internal.h
index 2acd34f..e84610b 100644
--- a/drivers/misc/xilinx-ai-engine/ai-engine-internal.h
+++ b/drivers/misc/xilinx-ai-engine/ai-engine-internal.h
@@ -12,6 +12,8 @@
#include
#include
#include
+#include
+#include
#include
#include
#include
@@ -67,8 +69,30 @@ struct aie_device;
struct aie_partition;
/**
+ * struct aie_part_mem - AI engine partition memory information structure
+ * @apart: AI engine partition
+ * @dbuf: dmabuf pointer associated with the memory
+ * @mem: memory information of a type of memory
+ * @size: size of the total memories in the partition
+ *
+ * This structure is to keep the information of a type of memory in a
+ * partition. The memory information will be stored in @mem property.
+ * The following information will be keep:
+ * * memory start address offset within a tile
+ * * memory size
+ * * what tiles contain this type of memory
+ */
+struct aie_part_mem {
+ struct aie_partition *apart;
+ struct dma_buf
[PATCH v3 2/9] misc: Add Xilinx AI engine device driver
Create AI engine device/partition hierarchical structure. Each AI engine device can have multiple logical partitions(groups of AI engine tiles). Each partition is column based and has its own node ID in the system. AI engine device driver manages its partitions. Applications can access AI engine partition through the AI engine partition driver instance. AI engine registers write is moved to kernel as there are registers in the AI engine array needs privilege permission. Signed-off-by: Wendy Liang Signed-off-by: Hyun Kwon --- MAINTAINERS| 8 + drivers/misc/Kconfig | 12 + drivers/misc/Makefile | 1 + drivers/misc/xilinx-ai-engine/Makefile | 11 + drivers/misc/xilinx-ai-engine/ai-engine-aie.c | 115 + drivers/misc/xilinx-ai-engine/ai-engine-dev.c | 452 +++ drivers/misc/xilinx-ai-engine/ai-engine-internal.h | 226 ++ drivers/misc/xilinx-ai-engine/ai-engine-part.c | 498 + drivers/misc/xilinx-ai-engine/ai-engine-res.c | 114 + include/uapi/linux/xlnx-ai-engine.h| 107 + 10 files changed, 1544 insertions(+) create mode 100644 drivers/misc/xilinx-ai-engine/Makefile create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-aie.c create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-dev.c create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-internal.h create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-part.c create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-res.c create mode 100644 include/uapi/linux/xlnx-ai-engine.h diff --git a/MAINTAINERS b/MAINTAINERS index 2daa6ee..1e36294 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19287,6 +19287,14 @@ T: git https://github.com/Xilinx/linux-xlnx.git F: Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.yaml F: drivers/phy/xilinx/phy-zynqmp.c +XILINX AI ENGINE DRIVER +M: Wendy Liang +S: Supported +F: Documentation/devicetree/bindings/soc/xilinx/xlnx,ai-engine.yaml +F: drivers/misc/xilinx-ai-engine/ +F: include/linux/xlnx-ai-engine.h +F: include/uapi/linux/xlnx-ai-engine.h + XILLYBUS DRIVER M: Eli Billauer L: linux-kernel@vger.kernel.org diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index fafa8b0..0b8ce4d 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -444,6 +444,18 @@ config XILINX_SDFEC If unsure, say N. +config XILINX_AIE + tristate "Xilinx AI engine" + depends on ARM64 || COMPILE_TEST + help + This option enables support for the Xilinx AI engine driver. + One Xilinx AI engine device can have multiple partitions (groups of + AI engine tiles). Xilinx AI engine device driver instance manages + AI engine partitions. User application access its partitions through + AI engine partition instance file operations. + + If unsure, say N + config MISC_RTSX tristate default MISC_RTSX_PCI || MISC_RTSX_USB diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index d23231e..2176b18 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -57,3 +57,4 @@ obj-$(CONFIG_HABANA_AI) += habanalabs/ obj-$(CONFIG_UACCE)+= uacce/ obj-$(CONFIG_XILINX_SDFEC) += xilinx_sdfec.o obj-$(CONFIG_HISI_HIKEY_USB) += hisi_hikey_usb.o +obj-$(CONFIG_XILINX_AIE) += xilinx-ai-engine/ diff --git a/drivers/misc/xilinx-ai-engine/Makefile b/drivers/misc/xilinx-ai-engine/Makefile new file mode 100644 index 000..7827a0a --- /dev/null +++ b/drivers/misc/xilinx-ai-engine/Makefile @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Makefile for Xilinx AI engine device driver +# + +obj-$(CONFIG_XILINX_AIE) += xilinx-aie.o + +xilinx-aie-$(CONFIG_XILINX_AIE) := ai-engine-aie.o \ + ai-engine-dev.o \ + ai-engine-part.o \ + ai-engine-res.o diff --git a/drivers/misc/xilinx-ai-engine/ai-engine-aie.c b/drivers/misc/xilinx-ai-engine/ai-engine-aie.c new file mode 100644 index 000..319260f --- /dev/null +++ b/drivers/misc/xilinx-ai-engine/ai-engine-aie.c @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx AI Engine driver AIE device specific implementation + * + * Copyright (C) 2020 Xilinx, Inc. + */ + +#include + +#include "ai-engine-internal.h" + +#define AIE_ARRAY_SHIFT30U +#define AIE_COL_SHIFT 23U +#define AIE_ROW_SHIFT 18U + +/* + * Registers offsets + */ +#define AIE_SHIMNOC_L2INTR_MASK_REGOFF 0x00015000U +#define AIE_SHIMNOC_L2INTR_INTR_REGOFF 0x00015010U +#define AIE_SHIMNOC_DMA_BD0_ADDRLOW_REGOFF 0x0001d000U +#define AIE_SHIMNOC_DMA_BD15_PACKET_REGOFF 0x0001d13cU +#define AIE_SHIMNOC_AXIMM_REGOFF
[PATCH v3 7/9] misc: xilinx-ai-engine: Add support to request device management services
From: Nishad Saraf
Platform management services like device control, resets, power
management, etc. are provided by Platform, Loader and Manager(PLM)
through firmware driver APIs. For requesting some of these services,
this change reads AI Engine platform management node ID from DT node.
Some other features like clearing interrupts in the NoC interconnect
might only be valid for particular silicon revisions. For supporting
such silicon specific features, AI Engine driver will query and store
this information in device instance. While at it, this change makes
EEMI operations accessible to all the other source files in the
driver.
Signed-off-by: Nishad Saraf
Signed-off-by: Wendy Liang
---
drivers/misc/xilinx-ai-engine/ai-engine-dev.c | 25 +-
drivers/misc/xilinx-ai-engine/ai-engine-internal.h | 6 ++
2 files changed, 30 insertions(+), 1 deletion(-)
diff --git a/drivers/misc/xilinx-ai-engine/ai-engine-dev.c
b/drivers/misc/xilinx-ai-engine/ai-engine-dev.c
index 43f4933..51c3a4f 100644
--- a/drivers/misc/xilinx-ai-engine/ai-engine-dev.c
+++ b/drivers/misc/xilinx-ai-engine/ai-engine-dev.c
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -26,7 +27,8 @@
#include "ai-engine-internal.h"
-#define AIE_DEV_MAX(MINORMASK + 1)
+#define AIE_DEV_MAX(MINORMASK + 1)
+#define VERSAL_SILICON_REV_MASKGENMASK(31, 28)
static dev_t aie_major;
struct class *aie_class;
@@ -322,6 +324,7 @@ static int xilinx_ai_engine_probe(struct platform_device
*pdev)
{
struct aie_device *adev;
struct device *dev;
+ u32 idcode, version, pm_reg[2];
int ret;
adev = devm_kzalloc(>dev, sizeof(*adev), GFP_KERNEL);
@@ -349,6 +352,26 @@ static int xilinx_ai_engine_probe(struct platform_device
*pdev)
return ret;
}
+ /*
+* AI Engine platform management node ID is required for requesting
+* services from firmware driver.
+*/
+ ret = of_property_read_u32_array(pdev->dev.of_node, "power-domains",
+pm_reg, ARRAY_SIZE(pm_reg));
+ if (ret < 0) {
+ dev_err(>dev,
+ "Failed to read power management information\n");
+ return ret;
+ }
+ adev->pm_node_id = pm_reg[1];
+
+ ret = zynqmp_pm_get_chipid(, );
+ if (ret < 0) {
+ dev_err(>dev, "Failed to get chip ID\n");
+ return ret;
+ }
+ adev->version = FIELD_GET(VERSAL_SILICON_REV_MASK, idcode);
+
dev = >dev;
device_initialize(dev);
dev->class = aie_class;
diff --git a/drivers/misc/xilinx-ai-engine/ai-engine-internal.h
b/drivers/misc/xilinx-ai-engine/ai-engine-internal.h
index 131d22a..b21b7025 100644
--- a/drivers/misc/xilinx-ai-engine/ai-engine-internal.h
+++ b/drivers/misc/xilinx-ai-engine/ai-engine-internal.h
@@ -41,6 +41,10 @@
#define AIE_REGS_ATTR_PERM_MASKGENMASK(15, \
AIE_REGS_ATTR_PERM_SHIFT)
+/* Silicon Engineering Sample(ES) revision ID */
+#define VERSAL_ES1_REV_ID 0x0
+#define VERSAL_ES2_REV_ID 0x1
+
/**
* struct aie_tile_regs - contiguous range of AI engine register
* within an AI engine tile
@@ -173,6 +177,7 @@ struct aie_resource {
* while columns are occupied by partitions.
* @num_kernel_regs: number of kernel only registers range
* @version: AI engine device version
+ * @pm_node_id: AI Engine platform management node ID
*/
struct aie_device {
struct list_head partitions;
@@ -193,6 +198,7 @@ struct aie_device {
u32 row_shift;
u32 num_kernel_regs;
int version;
+ u32 pm_node_id;
};
/**
--
2.7.4
[PATCH v3 5/9] misc: xilinx-ai-engine: add setting shim dma bd operation
Add operation to set SHIM DMA buffer descriptor.
The following operations are added to set the buffer descriptors:
* attach DMA buffer which enables AI engine device to access the DMA
buffer memory
* detach DMA buffer which disables AI engine device to access the DMA
buffer memory
* set DMA buffer descriptor, which takes buffer descriptor contents
pointer, the dmabuf fd, and the offset to the start of dmabuf as
as argument. It validates the dmabuf and the offset and size of the
buffer. And then it calculates the DMA address of the buffer and set
the buffer descriptor content to the hardware DMA buffer descriptor.
The main logic to control what's go into the buffer descriptor and which
buffer descriptor to use is in the userspace AI engine library.
Signed-off-by: Wendy Liang
Reviewed-by: Hyun Kwon
---
drivers/misc/xilinx-ai-engine/Makefile | 1 +
drivers/misc/xilinx-ai-engine/ai-engine-aie.c | 19 +
drivers/misc/xilinx-ai-engine/ai-engine-dma.c | 481 +
drivers/misc/xilinx-ai-engine/ai-engine-internal.h | 45 ++
drivers/misc/xilinx-ai-engine/ai-engine-part.c | 17 +
include/uapi/linux/xlnx-ai-engine.h| 44 ++
6 files changed, 607 insertions(+)
create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-dma.c
diff --git a/drivers/misc/xilinx-ai-engine/Makefile
b/drivers/misc/xilinx-ai-engine/Makefile
index 2dbed42..1b743fa 100644
--- a/drivers/misc/xilinx-ai-engine/Makefile
+++ b/drivers/misc/xilinx-ai-engine/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_XILINX_AIE)+= xilinx-aie.o
xilinx-aie-$(CONFIG_XILINX_AIE) := ai-engine-aie.o \
ai-engine-dev.o \
+ ai-engine-dma.o \
ai-engine-mem.o \
ai-engine-part.o \
ai-engine-res.o \
diff --git a/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
b/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
index 7fce2f00..ac95aff 100644
--- a/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
+++ b/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
@@ -107,6 +107,24 @@ static const struct aie_single_reg_field aie_col_clkbuf = {
.regoff = AIE_SHIMPL_CLKCNTR_REGOFF,
};
+static const struct aie_dma_attr aie_shimdma = {
+ .laddr = {
+ .mask = 0xU,
+ .regoff = 0U,
+ },
+ .haddr = {
+ .mask = 0xU,
+ .regoff = 0x8U,
+ },
+ .buflen = {
+ .mask = 0xU,
+ .regoff = 0x4U,
+ },
+ .bd_regoff = 0x0001d000U,
+ .num_bds = 16,
+ .bd_len = 0x14U,
+};
+
static u32 aie_get_tile_type(struct aie_location *loc)
{
if (loc->row)
@@ -232,6 +250,7 @@ int aie_device_init(struct aie_device *adev)
adev->kernel_regs = aie_kernel_regs;
adev->col_rst = _col_rst;
adev->col_clkbuf = _col_clkbuf;
+ adev->shim_dma = _shimdma;
/* Get the columns resource */
/* Get number of columns from AI engine memory resource */
diff --git a/drivers/misc/xilinx-ai-engine/ai-engine-dma.c
b/drivers/misc/xilinx-ai-engine/ai-engine-dma.c
new file mode 100644
index 000..863790b
--- /dev/null
+++ b/drivers/misc/xilinx-ai-engine/ai-engine-dma.c
@@ -0,0 +1,481 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx AI Engine driver DMA implementation
+ *
+ * Copyright (C) 2020 Xilinx, Inc.
+ */
+
+#include "ai-engine-internal.h"
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/**
+ * struct aie_dmabuf - AI engine dmabuf information
+ * @attach: dmabuf attachment pointer
+ * @sgt: scatter/gather table
+ * @refs: refcount of the attached aie_dmabuf
+ * @node: list node
+ */
+struct aie_dmabuf {
+ struct dma_buf_attachment *attach;
+ struct sg_table *sgt;
+ refcount_t refs;
+ struct list_head node;
+};
+
+/**
+ * aie_part_find_dmabuf() - find a attached dmabuf
+ * @apart: AI engine partition
+ * @dmabuf: pointer to dmabuf
+ * @return: pointer to AI engine dmabuf struct of the found dmabuf, if dmabuf
+ * is not found, returns NULL.
+ *
+ * This function scans all the attached dmabufs to see the input dmabuf is
+ * in the list. if it is attached, return the corresponding struct aie_dmabuf
+ * pointer.
+ */
+static struct aie_dmabuf *
+aie_part_find_dmabuf(struct aie_partition *apart, struct dma_buf *dmabuf)
+{
+ struct aie_dmabuf *adbuf;
+
+ list_for_each_entry(adbuf, >dbufs, node) {
+ if (dmabuf == adbuf->attach->dmabuf)
+ return adbuf;
+ }
+
+ return NULL;
+}
+
+/**
+ * aie_part_get_dmabuf_da_from_off() - get DMA address from offset to a dmabuf
+ * @apart: AI engine partition
+ * @dmabuf_fd: dmabuf file descriptor
+ * @off: offset to the start of a dmabuf
+ * @len: memory length
+ * @return: dma addres
[PATCH v3 8/9] firmware: xilinx: Add IOCTL support for AIE ISR Clear
From: Izhar Ameer Shaikh
Latching of AIE NPI Interrupts is present in Versal ES1 Silicon Rev,
however it has been removed from ES2 rev.
As a result on ES1, in order to use the interrupt, a client needs to
request PMC to clear/ack the interrupt.
Provide an EEMI IOCTL to serve the same purpose. Note that, this will
only be applicable for ES1 rev. For ES2 and other non-silicon platforms,
this call will essentially be a NOP in the firmware.
Signed-off-by: Izhar Ameer Shaikh
Signed-off-by: Wendy Liang
---
drivers/firmware/xilinx/zynqmp.c | 14 ++
include/linux/firmware/xlnx-zynqmp.h | 8
2 files changed, 22 insertions(+)
diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
index d08ac82..23e58cc 100644
--- a/drivers/firmware/xilinx/zynqmp.c
+++ b/drivers/firmware/xilinx/zynqmp.c
@@ -729,6 +729,20 @@ int zynqmp_pm_set_boot_health_status(u32 value)
}
/**
+ * zynqmp_pm_clear_aie_npi_isr - Clear AI engine NPI interrupt status register
+ * @node: AI engine node id
+ * @irq_mask: Mask of AI engine NPI interrupt bit to clear
+ *
+ * Return: Returns status, either success or error+reason
+ */
+int zynqmp_pm_clear_aie_npi_isr(u32 node, u32 irq_mask)
+{
+ return zynqmp_pm_invoke_fn(PM_IOCTL, node, IOCTL_AIE_ISR_CLEAR,
+ irq_mask, 0, NULL);
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_clear_aie_npi_isr);
+
+/**
* zynqmp_pm_reset_assert - Request setting of reset (1 - assert, 0 - release)
* @reset: Reset to be configured
* @assert_flag: Flag stating should reset be asserted (1) or
diff --git a/include/linux/firmware/xlnx-zynqmp.h
b/include/linux/firmware/xlnx-zynqmp.h
index 83ac9ec..defa4ea 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -114,6 +114,8 @@ enum pm_ioctl_id {
IOCTL_READ_PGGS = 15,
/* Set healthy bit value */
IOCTL_SET_BOOT_HEALTH_STATUS = 17,
+ /* AI engine NPI ISR clear */
+ IOCTL_AIE_ISR_CLEAR = 24,
};
enum pm_query_id {
@@ -355,6 +357,7 @@ int zynqmp_pm_write_pggs(u32 index, u32 value);
int zynqmp_pm_read_pggs(u32 index, u32 *value);
int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype);
int zynqmp_pm_set_boot_health_status(u32 value);
+int zynqmp_pm_clear_aie_npi_isr(u32 node, u32 irq_mask);
#else
static inline struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void)
{
@@ -505,6 +508,11 @@ static inline int zynqmp_pm_set_boot_health_status(u32
value)
{
return -ENODEV;
}
+
+static inline int zynqmp_pm_clear_aie_npi_isr(u32 node, u32 irq_mask)
+{
+ return -ENODEV;
+}
#endif
#endif /* __FIRMWARE_ZYNQMP_H__ */
--
2.7.4
[PATCH v3 1/9] dt-binding: soc: xilinx: ai-engine: Add AI engine binding
Xilinx AI engine array can be partitioned statically for different
applications. In the device tree, there will be device node for the AI
engine device, and device nodes for the statically configured AI engine
partitions. Each of the statically configured partition has a partition
ID in the system.
Signed-off-by: Wendy Liang
---
.../bindings/soc/xilinx/xlnx,ai-engine.yaml| 126 +
1 file changed, 126 insertions(+)
create mode 100644
Documentation/devicetree/bindings/soc/xilinx/xlnx,ai-engine.yaml
diff --git a/Documentation/devicetree/bindings/soc/xilinx/xlnx,ai-engine.yaml
b/Documentation/devicetree/bindings/soc/xilinx/xlnx,ai-engine.yaml
new file mode 100644
index 000..1de5623
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/xilinx/xlnx,ai-engine.yaml
@@ -0,0 +1,126 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/xilinx/xlnx,ai-engine.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx AI Engine
+
+maintainers:
+ - Wendy Liang
+
+description: |+
+ The Xilinx AI Engine is a tile processor with many cores (up to 400) that
+ can run in parallel. The data routing between cores is configured through
+ internal switches, and shim tiles interface with external interconnect, such
+ as memory or PL.
+
+properties:
+ compatible:
+const: xlnx,ai-engine-v1.0
+
+ reg:
+description: |
+ Physical base address and length of the device registers.
+ The AI engine address space assigned to Linux is defined by Xilinx
+ platform design tool.
+
+ '#address-cells':
+enum: [2]
+description: |
+ size of cell to describe AI engine range of tiles address.
+ It is the location of the starting tile of the range.
+ As the AI engine tiles are 2D array, the location of a tile
+ is presented as (column, row), the address cell is 2.
+
+ '#size-cells':
+enum: [2]
+description: |
+ size of cell to describe AI engine range of tiles size.
+ As the AI engine tiles are 2D array, the size cell is 2.
+
+ power-domains:
+maxItems: 1
+description: phandle to the associated power domain
+
+ interrupts:
+maxItems: 3
+
+ interrupt-names:
+description: |
+ Should be "interrupt1", "interrupt2" or "interrupt3".
+
+required:
+ - compatible
+ - reg
+ - '#address-cells'
+ - '#size-cells'
+ - power-domains
+ - interrupt-parent
+ - interrupts
+ - interrupt-names
+
+patternProperties:
+ "^aie_partition@[0-9]+$":
+type: object
+description: |
+ AI engine partition which is a group of column based tiles of the AI
+ engine device. Each AI engine partition is isolated from the other
+ AI engine partitions. An AI engine partition is defined by Xilinx
+ platform design tools. Each partition has a SHIM row and core tiles rows.
+ A SHIM row contains SHIM tiles which are the interface to external
+ components. AXI master can access AI engine registers, push data to and
+ fetch data from AI engine through the SHIM tiles. Core tiles are the
+ compute tiles.
+
+properties:
+ reg:
+description: |
+ It describes the group of tiles of the AI engine partition. It needs
+ to include the SHIM row. The format is defined by the parent AI
engine
+ device node's '#address-cells' and '#size-cells' properties. e.g. a
v1
+ AI engine device has 2D tiles array, the first row is SHIM row. A
+ partition which has 50 columns and 8 rows of core tiles and 1 row of
+ SHIM tiles will be presented as <0 0 50 9>.
+
+ label:
+maxItems: 1
+
+ xlnx,partition-id:
+$ref: /schemas/types.yaml#/definitions/uint32
+description: |
+ AI engine partition ID, which is defined by Xilinx platform design
+ tool to identify the AI engine partition in the system.
+
+required:
+ - reg
+ - xlnx,partition-id
+additionalProperties: false
+
+additionalProperties: false
+
+examples:
+ - |
+bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ ai_engine: ai-engine@200 {
+compatible = "xlnx,ai-engine-v1.0";
+reg = <0x200 0x0 0x1 0x0>;
+#address-cells = <2>;
+#size-cells = <2>;
+power-domains = <_firmware 0x18224072>;
+interrupt-parent = <>;
+interrupts = <0x0 0x94 0x4>,
+ <0x0 0x95 0x4>,
+ <0x0 0x96 0x4>;
+interrupt-names = "interrupt1", "interrupt2", "interrupt3";
+
+aie_partition0: aie_partition@0 {
+/* 50 columns and 8 core tile rows + 1 SHIM row */
+reg = <0 0 50 9>;
+xlnx,partition-id = <1>;
+};
+ };
+};
--
2.7.4
[PATCH v3 0/9] Xilinx AI engine kernel driver
AI engine is the acceleration engine provided by Xilinx. These engines provide high compute density for vector-based algorithms, and flexible custom compute and data movement. It has core tiles for compute and shim tiles to interface the FPGA fabric. You can check the AI engine architecture document for more hardware details: https://www.xilinx.com/support/documentation/architecture-manuals/am009-versal-ai-engine.pdf This patch series adds a Linux kernel driver to manage the Xilinx AI engine array device and AI engine partitions (groups of AI engine tiles dedicated to an application). v3: * unlock AIE dev mutex after failed to gain the partition lock in errors handing * replace pointer with __u64 and enum with __u32 in ioctl v2: * Fix dtschema check errors * Fix test bot warning on interrupt implementation. Removed set but unused varaible. * Fix compilation unused function warning of firmware change in case ZynqMP firmware is not configured * There are other warning on ZynqMP firmware reported from testbot which is not introduced by this patch set. "[PATCH] firmware: xlnx-zynqmp: fix compilation warning" is submitted for those fixes. Izhar Ameer Shaikh (1): firmware: xilinx: Add IOCTL support for AIE ISR Clear Nishad Saraf (2): misc: xilinx-ai-engine: Add support to request device management services misc: xilinx-ai-engine: Add support for servicing error interrupts Wendy Liang (6): dt-binding: soc: xilinx: ai-engine: Add AI engine binding misc: Add Xilinx AI engine device driver misc: xilinx-ai-engine: Implement AI engine cleanup sequence misc: xilinx-ai-engine: expose AI engine tile memories to userspace misc: xilinx-ai-engine: add setting shim dma bd operation misc: xilinx-ai-engine: add request and release tiles .../bindings/soc/xilinx/xlnx,ai-engine.yaml| 126 MAINTAINERS| 8 + drivers/firmware/xilinx/zynqmp.c | 14 + drivers/misc/Kconfig | 12 + drivers/misc/Makefile | 1 + drivers/misc/xilinx-ai-engine/Makefile | 16 + drivers/misc/xilinx-ai-engine/ai-engine-aie.c | 608 +++ drivers/misc/xilinx-ai-engine/ai-engine-clock.c| 245 drivers/misc/xilinx-ai-engine/ai-engine-dev.c | 496 drivers/misc/xilinx-ai-engine/ai-engine-dma.c | 481 +++ drivers/misc/xilinx-ai-engine/ai-engine-internal.h | 519 .../misc/xilinx-ai-engine/ai-engine-interrupt.c| 659 + drivers/misc/xilinx-ai-engine/ai-engine-mem.c | 275 + drivers/misc/xilinx-ai-engine/ai-engine-part.c | 635 drivers/misc/xilinx-ai-engine/ai-engine-res.c | 219 +++ drivers/misc/xilinx-ai-engine/ai-engine-reset.c| 159 + include/linux/firmware/xlnx-zynqmp.h | 8 + include/uapi/linux/xlnx-ai-engine.h| 238 18 files changed, 4719 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/xilinx/xlnx,ai-engine.yaml create mode 100644 drivers/misc/xilinx-ai-engine/Makefile create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-aie.c create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-clock.c create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-dev.c create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-dma.c create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-internal.h create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-interrupt.c create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-mem.c create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-part.c create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-res.c create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-reset.c create mode 100644 include/uapi/linux/xlnx-ai-engine.h -- 2.7.4
[PATCH v3 3/9] misc: xilinx-ai-engine: Implement AI engine cleanup sequence
When AI engine partition is released, that is if no one is using the AI
engine partition, by default, it will cleanup the partition by doing the
following:
* reset the columns
* reset the SHIMs
* clear data and program memory
* gate all the tiles
If user doesn't want the partition is reset when the partition is
released, user can set the control flag to indicate not to reset the
partition when the user requests the partition.
If partition the not to reset partition control flag is set, it will
not execute the above cleanup sequence when the partition is released.
Signed-off-by: Wendy Liang
Reviewed-by: Hyun Kwon
---
drivers/misc/xilinx-ai-engine/Makefile | 3 +-
drivers/misc/xilinx-ai-engine/ai-engine-aie.c | 92
drivers/misc/xilinx-ai-engine/ai-engine-dev.c | 2 +
drivers/misc/xilinx-ai-engine/ai-engine-internal.h | 34 ++
drivers/misc/xilinx-ai-engine/ai-engine-part.c | 7 +-
drivers/misc/xilinx-ai-engine/ai-engine-reset.c| 121 +
include/uapi/linux/xlnx-ai-engine.h| 6 +
7 files changed, 259 insertions(+), 6 deletions(-)
create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-reset.c
diff --git a/drivers/misc/xilinx-ai-engine/Makefile
b/drivers/misc/xilinx-ai-engine/Makefile
index 7827a0a..39bec61 100644
--- a/drivers/misc/xilinx-ai-engine/Makefile
+++ b/drivers/misc/xilinx-ai-engine/Makefile
@@ -8,4 +8,5 @@ obj-$(CONFIG_XILINX_AIE)+= xilinx-aie.o
xilinx-aie-$(CONFIG_XILINX_AIE) := ai-engine-aie.o \
ai-engine-dev.o \
ai-engine-part.o \
- ai-engine-res.o
+ ai-engine-res.o \
+ ai-engine-reset.o
diff --git a/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
b/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
index 319260f..36127f0 100644
--- a/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
+++ b/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
@@ -5,6 +5,9 @@
* Copyright (C) 2020 Xilinx, Inc.
*/
+#include
+#include
+#include
#include
#include "ai-engine-internal.h"
@@ -24,9 +27,25 @@
#define AIE_SHIMPL_L1INTR_MASK_A_REGOFF0x00035000U
#define AIE_SHIMPL_L1INTR_BLOCK_NORTH_B_REGOFF 0x00035050U
#define AIE_SHIMPL_CLKCNTR_REGOFF 0x00036040U
+#define AIE_SHIMPL_COLRESET_REGOFF 0x00036048U
#define AIE_SHIMPL_RESET_REGOFF0x0003604cU
#define AIE_TILE_CORE_CLKCNTR_REGOFF 0x00036040U
+/*
+ * Register masks
+ */
+#define AIE_SHIMPL_SHIMRST_MASK0x1U
+#define AIE_SHIMPL_COLRST_MASK 0x1U
+#define AIE_SHIMPL_CLKCNTR_COLBUF_MASK 0x1U
+
+/*
+ * AI engine SHIM reset ID.
+ * TODO: it should follow the Linux reset framework. The ID should be in the
+ * device tree. However, as versal resets is not ready, we hardcode it in the
+ * driver.
+ */
+#define VERSAL_PM_RST_AIE_SHIM_ID 0xc10405fU
+
static const struct aie_tile_regs aie_kernel_regs[] = {
/* SHIM AXI MM Config */
{.attribute = AIE_TILE_TYPE_SHIMNOC << AIE_REGS_ATTR_TILE_TYPE_SHIFT,
@@ -49,6 +68,12 @@ static const struct aie_tile_regs aie_kernel_regs[] = {
.soff = AIE_SHIMPL_L1INTR_MASK_A_REGOFF,
.eoff = AIE_SHIMPL_L1INTR_BLOCK_NORTH_B_REGOFF,
},
+ /* SHIM column reset */
+ {.attribute = (AIE_TILE_TYPE_SHIMPL | AIE_TILE_TYPE_SHIMNOC) <<
+ AIE_REGS_ATTR_TILE_TYPE_SHIFT,
+.soff = AIE_SHIMPL_COLRESET_REGOFF,
+.eoff = AIE_SHIMPL_COLRESET_REGOFF,
+ },
/* SHIM reset Enable */
{.attribute = (AIE_TILE_TYPE_SHIMPL | AIE_TILE_TYPE_SHIMNOC) <<
AIE_REGS_ATTR_TILE_TYPE_SHIFT,
@@ -68,6 +93,16 @@ static const struct aie_tile_regs aie_kernel_regs[] = {
},
};
+static const struct aie_single_reg_field aie_col_rst = {
+ .mask = AIE_SHIMPL_COLRST_MASK,
+ .regoff = AIE_SHIMPL_COLRESET_REGOFF,
+};
+
+static const struct aie_single_reg_field aie_col_clkbuf = {
+ .mask = AIE_SHIMPL_CLKCNTR_COLBUF_MASK,
+ .regoff = AIE_SHIMPL_CLKCNTR_REGOFF,
+};
+
static u32 aie_get_tile_type(struct aie_location *loc)
{
if (loc->row)
@@ -79,8 +114,63 @@ static u32 aie_get_tile_type(struct aie_location *loc)
return AIE_TILE_TYPE_SHIMNOC;
}
+/**
+ * aie_set_shim_reset() - Set AI engine SHIM reset
+ * @adev: AI engine device
+ * @range: range of AI engine tiles
+ * @assert: true to set reset, false to unset reset
+ */
+static void aie_set_shim_reset(struct aie_device *adev,
+ struct aie_range *range, bool assert)
+{
+ u32 c;
+ u32 val;
+ struct aie_location loc;
+
+ val = FIELD_PREP(AIE_SHIMPL_SHIMRST_MASK, (assert ? 1 : 0));
+ loc.row = 0;
+ for (c = range->start.col; c < range->sta
[PATCH v2] firmware: xlnx-zynqmp: fix compilation warning
Fix compilation warning when ZYNQMP_FIRMWARE is not defined. include/linux/firmware/xlnx-zynqmp.h: In function 'zynqmp_pm_get_eemi_ops': include/linux/firmware/xlnx-zynqmp.h:363:9: error: implicit declaration of function 'ERR_PTR' [-Werror=implicit-function-declaration] 363 | return ERR_PTR(-ENODEV); include/linux/firmware/xlnx-zynqmp.h:363:18: note: each undeclared identifier is reported only once for each function it appears in include/linux/firmware/xlnx-zynqmp.h: In function 'zynqmp_pm_get_api_version': include/linux/firmware/xlnx-zynqmp.h:367:10: error: 'ENODEV' undeclared (first use in this function) 367 | return -ENODEV; | ^~ Signed-off-by: Wendy Liang --- v2: * Always include linux/err.h --- include/linux/firmware/xlnx-zynqmp.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h index 5968df8..f84244e 100644 --- a/include/linux/firmware/xlnx-zynqmp.h +++ b/include/linux/firmware/xlnx-zynqmp.h @@ -13,6 +13,8 @@ #ifndef __FIRMWARE_ZYNQMP_H__ #define __FIRMWARE_ZYNQMP_H__ +#include + #define ZYNQMP_PM_VERSION_MAJOR1 #define ZYNQMP_PM_VERSION_MINOR0 -- 2.7.4
Re: [PATCH v2 9/9] misc: xilinx-ai-engine: Add support for servicing error interrupts
On 11/19/20 12:36 AM, Hillf Danton wrote:
On Wed, 18 Nov 2020 15:48:09 -0800 Wendy Liang wrote:
+/**
+ * aie_interrupt() - interrupt handler for AIE.
+ * @irq: Interrupt number.
+ * @data: AI engine device structure.
+ * @return: IRQ_HANDLED.
+ *
+ * This thread function disables level 2 interrupt controllers and schedules a
+ * task in workqueue to backtrack the source of error interrupt. Disabled
+ * interrupts are re-enabled after successful completion of bottom half.
+ */
+irqreturn_t aie_interrupt(int irq, void *data)
+{
+ struct aie_device *adev = data;
+ struct aie_partition *apart;
+ int ret;
+ bool sched_work = false;
+
+ ret = mutex_lock_interruptible(>mlock);
+ if (ret) {
+ dev_err(>dev,
+ "Failed to acquire lock. Process was interrupted by fatal
signals\n");
+ return IRQ_NONE;
+ }
+
+ list_for_each_entry(apart, >partitions, node) {
+ struct aie_location loc;
+ u32 ttype, l2_mask, l2_status, l2_bitmap_offset = 0;
+
+ ret = mutex_lock_interruptible(>mlock);
+ if (ret) {
+ dev_err(>dev,
+ "Failed to acquire lock. Process was interrupted by
fatal signals\n");
+ return IRQ_NONE;
Though quite unlikely, you need to release adev->mlock before
going home.
Thanks to point it out, I will change in next version
Thanks,
Wendy
+ }
+
+ for (loc.col = apart->range.start.col, loc.row = 0;
+loc.col < apart->range.start.col + apart->range.size.col;
+loc.col++) {
+ ttype = apart->adev->ops->get_tile_type();
+ if (ttype != AIE_TILE_TYPE_SHIMNOC)
+ continue;
+
+ l2_mask = aie_get_l2_mask(apart, );
+ if (l2_mask) {
+ aie_resource_cpy_from_arr32(>l2_mask,
+ l2_bitmap_offset *
+ 32, _mask, 32);
+ aie_disable_l2_ctrl(apart, , l2_mask);
+ }
+ l2_bitmap_offset++;
+
+ l2_status = aie_get_l2_status(apart, );
+ if (l2_status) {
+ aie_clear_l2_intr(apart, , l2_status);
+ sched_work = true;
+ } else {
+ aie_enable_l2_ctrl(apart, , l2_mask);
+ }
+ }
+ mutex_unlock(>mlock);
+ }
+
+ /* For ES1 silicon, interrupts are latched in NPI */
+ if (adev->version == VERSAL_ES1_REV_ID) {
+ ret = zynqmp_pm_clear_aie_npi_isr(adev->pm_node_id,
+ AIE_NPI_ERROR_ID);
+ if (ret < 0)
+ dev_err(>dev, "Failed to clear NPI ISR\n");
+ }
+
+ mutex_unlock(>mlock);
+
+ if (sched_work)
+ schedule_work(>backtrack);
+
+ return IRQ_HANDLED;
+}
[PATCH v2 6/9] misc: xilinx-ai-engine: add request and release tiles
Add request/release and related clock gating functions to AI engine
driver:
* scanning when the partition is being requested to know which tiles
are in use.
* check if a tile is gated or not
* tiles requesting and releasing ioctl so that user application can
enable/disable tiles at runtime.
Signed-off-by: Wendy Liang
Reviewed-by: Hyun Kwon
---
drivers/misc/xilinx-ai-engine/Makefile | 1 +
drivers/misc/xilinx-ai-engine/ai-engine-aie.c | 227 ++-
drivers/misc/xilinx-ai-engine/ai-engine-clock.c| 244 +
drivers/misc/xilinx-ai-engine/ai-engine-dev.c | 19 +-
drivers/misc/xilinx-ai-engine/ai-engine-internal.h | 34 +++
drivers/misc/xilinx-ai-engine/ai-engine-part.c | 32 +++
drivers/misc/xilinx-ai-engine/ai-engine-res.c | 51 +
include/uapi/linux/xlnx-ai-engine.h| 31 +++
8 files changed, 631 insertions(+), 8 deletions(-)
create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-clock.c
diff --git a/drivers/misc/xilinx-ai-engine/Makefile
b/drivers/misc/xilinx-ai-engine/Makefile
index 1b743fa..2e67b25 100644
--- a/drivers/misc/xilinx-ai-engine/Makefile
+++ b/drivers/misc/xilinx-ai-engine/Makefile
@@ -6,6 +6,7 @@
obj-$(CONFIG_XILINX_AIE) += xilinx-aie.o
xilinx-aie-$(CONFIG_XILINX_AIE) := ai-engine-aie.o \
+ ai-engine-clock.o \
ai-engine-dev.o \
ai-engine-dma.o \
ai-engine-mem.o \
diff --git a/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
b/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
index 19c262d..ff721b3 100644
--- a/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
+++ b/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
@@ -41,6 +41,9 @@
#define AIE_SHIMPL_SHIMRST_MASK0x1U
#define AIE_SHIMPL_COLRST_MASK 0x1U
#define AIE_SHIMPL_CLKCNTR_COLBUF_MASK 0x1U
+#define AIE_SHIMPL_CLKCNTR_NEXTCLK_MASKBIT(1)
+#define AIE_TILE_CLKCNTR_COLBUF_MASK BIT(0)
+#define AIE_TILE_CLKCNTR_NEXTCLK_MASK BIT(1)
/*
* AI engine SHIM reset ID.
@@ -221,10 +224,232 @@ static int aie_reset_shim(struct aie_device *adev,
struct aie_range *range)
return 0;
}
+static int aie_init_part_clk_state(struct aie_partition *apart)
+{
+ int ret, num_tiles;
+
+ num_tiles = apart->range.size.col * (apart->range.size.row - 1);
+
+ ret = aie_resource_initialize(>cores_clk_state, num_tiles);
+ if (ret) {
+ dev_err(>dev,
+ "failed to initialize cores clock state resource.\n");
+ return ret;
+ }
+
+ ret = aie_resource_initialize(>tiles_inuse, num_tiles);
+ if (ret) {
+ dev_err(>dev,
+ "failed to initialize tiles in use resource.\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int aie_scan_part_clocks(struct aie_partition *apart)
+{
+ struct aie_device *adev = apart->adev;
+ struct aie_range *range = >range;
+ struct aie_location loc;
+
+ /* Clear the bitmap of cores and memories clock state */
+ aie_resource_put_region(>cores_clk_state, 0,
+ apart->cores_clk_state.total);
+
+ for (loc.col = range->start.col;
+loc.col < range->start.col + range->size.col;
+loc.col++) {
+ for (loc.row = range->start.row;
+loc.row < range->start.row + range->size.row - 1;
+loc.row++) {
+ void __iomem *va;
+ u32 val, nbitpos;
+
+ /*
+* Reading registers of the current tile to see the next
+* tile is clock gated.
+*/
+ nbitpos = loc.col * (range->size.row - 1) + loc.row;
+
+ if (aie_get_tile_type() != AIE_TILE_TYPE_TILE) {
+ /* Checks shim tile for next core tile */
+ va = adev->base +
+aie_cal_regoff(adev, loc,
+ AIE_SHIMPL_CLKCNTR_REGOFF);
+ val = ioread32(va);
+
+ /*
+* check if the clock buffer and the next clock
+* tile is set, if one of them is not set, the
+* tiles of the column are clock gated.
+*/
+ if (!(val & AIE_SHIMPL_CLKCNTR_COLBUF_MASK) ||
+ !(val & AIE_SHIMPL_CLKCNTR_NEXTCLK_MASK))
+ break;
+
+ /* Set
[PATCH v2 2/9] misc: Add Xilinx AI engine device driver
Create AI engine device/partition hierarchical structure. Each AI engine device can have multiple logical partitions(groups of AI engine tiles). Each partition is column based and has its own node ID in the system. AI engine device driver manages its partitions. Applications can access AI engine partition through the AI engine partition driver instance. AI engine registers write is moved to kernel as there are registers in the AI engine array needs privilege permission. Signed-off-by: Wendy Liang Signed-off-by: Hyun Kwon --- MAINTAINERS| 8 + drivers/misc/Kconfig | 12 + drivers/misc/Makefile | 1 + drivers/misc/xilinx-ai-engine/Makefile | 11 + drivers/misc/xilinx-ai-engine/ai-engine-aie.c | 115 + drivers/misc/xilinx-ai-engine/ai-engine-dev.c | 448 ++ drivers/misc/xilinx-ai-engine/ai-engine-internal.h | 226 ++ drivers/misc/xilinx-ai-engine/ai-engine-part.c | 498 + drivers/misc/xilinx-ai-engine/ai-engine-res.c | 114 + include/uapi/linux/xlnx-ai-engine.h| 107 + 10 files changed, 1540 insertions(+) create mode 100644 drivers/misc/xilinx-ai-engine/Makefile create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-aie.c create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-dev.c create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-internal.h create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-part.c create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-res.c create mode 100644 include/uapi/linux/xlnx-ai-engine.h diff --git a/MAINTAINERS b/MAINTAINERS index 5cc595a..40e3351 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19283,6 +19283,14 @@ T: git https://github.com/Xilinx/linux-xlnx.git F: Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.yaml F: drivers/phy/xilinx/phy-zynqmp.c +XILINX AI ENGINE DRIVER +M: Wendy Liang +S: Supported +F: Documentation/devicetree/bindings/soc/xilinx/xlnx,ai-engine.yaml +F: drivers/misc/xilinx-ai-engine/ +F: include/linux/xlnx-ai-engine.h +F: include/uapi/linux/xlnx-ai-engine.h + XILLYBUS DRIVER M: Eli Billauer L: linux-kernel@vger.kernel.org diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index fafa8b0..0b8ce4d 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -444,6 +444,18 @@ config XILINX_SDFEC If unsure, say N. +config XILINX_AIE + tristate "Xilinx AI engine" + depends on ARM64 || COMPILE_TEST + help + This option enables support for the Xilinx AI engine driver. + One Xilinx AI engine device can have multiple partitions (groups of + AI engine tiles). Xilinx AI engine device driver instance manages + AI engine partitions. User application access its partitions through + AI engine partition instance file operations. + + If unsure, say N + config MISC_RTSX tristate default MISC_RTSX_PCI || MISC_RTSX_USB diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index d23231e..2176b18 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -57,3 +57,4 @@ obj-$(CONFIG_HABANA_AI) += habanalabs/ obj-$(CONFIG_UACCE)+= uacce/ obj-$(CONFIG_XILINX_SDFEC) += xilinx_sdfec.o obj-$(CONFIG_HISI_HIKEY_USB) += hisi_hikey_usb.o +obj-$(CONFIG_XILINX_AIE) += xilinx-ai-engine/ diff --git a/drivers/misc/xilinx-ai-engine/Makefile b/drivers/misc/xilinx-ai-engine/Makefile new file mode 100644 index 000..7827a0a --- /dev/null +++ b/drivers/misc/xilinx-ai-engine/Makefile @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Makefile for Xilinx AI engine device driver +# + +obj-$(CONFIG_XILINX_AIE) += xilinx-aie.o + +xilinx-aie-$(CONFIG_XILINX_AIE) := ai-engine-aie.o \ + ai-engine-dev.o \ + ai-engine-part.o \ + ai-engine-res.o diff --git a/drivers/misc/xilinx-ai-engine/ai-engine-aie.c b/drivers/misc/xilinx-ai-engine/ai-engine-aie.c new file mode 100644 index 000..319260f --- /dev/null +++ b/drivers/misc/xilinx-ai-engine/ai-engine-aie.c @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx AI Engine driver AIE device specific implementation + * + * Copyright (C) 2020 Xilinx, Inc. + */ + +#include + +#include "ai-engine-internal.h" + +#define AIE_ARRAY_SHIFT30U +#define AIE_COL_SHIFT 23U +#define AIE_ROW_SHIFT 18U + +/* + * Registers offsets + */ +#define AIE_SHIMNOC_L2INTR_MASK_REGOFF 0x00015000U +#define AIE_SHIMNOC_L2INTR_INTR_REGOFF 0x00015010U +#define AIE_SHIMNOC_DMA_BD0_ADDRLOW_REGOFF 0x0001d000U +#define AIE_SHIMNOC_DMA_BD15_PACKET_REGOFF 0x0001d13cU +#define AIE_SHIMNOC_AXIMM_REGOFF
[PATCH v2 4/9] misc: xilinx-ai-engine: expose AI engine tile memories to userspace
There is no concern to have userspace to directly access AI engine
program and data memories. It will be much faster to directly copy
data to and from these memories from userspace.
We choose to use DMA buf for the data and program memory because of the
DMA buf features. DMA buf can share the DMA memory between applications
and different devices, which can benefit on how to share data with AI
engine device in future.
There is one DMA buf per type of memory in an AI engine partition. e.g.
There is one DMA buf for all the tile core program memories in an AI
engine partition. There is another DMA buf for all the tile data
memories in an AI engine partition.
Signed-off-by: Wendy Liang
Reviewed-by: Hyun Kwon
---
drivers/misc/xilinx-ai-engine/Makefile | 1 +
drivers/misc/xilinx-ai-engine/ai-engine-aie.c | 36 +++
drivers/misc/xilinx-ai-engine/ai-engine-internal.h | 30 +++
drivers/misc/xilinx-ai-engine/ai-engine-mem.c | 274 +
drivers/misc/xilinx-ai-engine/ai-engine-part.c | 47
drivers/misc/xilinx-ai-engine/ai-engine-reset.c| 38 +++
include/uapi/linux/xlnx-ai-engine.h| 49
7 files changed, 475 insertions(+)
create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-mem.c
diff --git a/drivers/misc/xilinx-ai-engine/Makefile
b/drivers/misc/xilinx-ai-engine/Makefile
index 39bec61..2dbed42 100644
--- a/drivers/misc/xilinx-ai-engine/Makefile
+++ b/drivers/misc/xilinx-ai-engine/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_XILINX_AIE)+= xilinx-aie.o
xilinx-aie-$(CONFIG_XILINX_AIE) := ai-engine-aie.o \
ai-engine-dev.o \
+ ai-engine-mem.o \
ai-engine-part.o \
ai-engine-res.o \
ai-engine-reset.o
diff --git a/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
b/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
index 36127f0..7fce2f00 100644
--- a/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
+++ b/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
@@ -12,10 +12,14 @@
#include "ai-engine-internal.h"
+#define KBYTES(n) ((n) * 1024)
+
#define AIE_ARRAY_SHIFT30U
#define AIE_COL_SHIFT 23U
#define AIE_ROW_SHIFT 18U
+#define NUM_MEMS_PER_TILE 2U
+
/*
* Registers offsets
*/
@@ -114,6 +118,37 @@ static u32 aie_get_tile_type(struct aie_location *loc)
return AIE_TILE_TYPE_SHIMNOC;
}
+static unsigned int aie_get_mem_info(struct aie_range *range,
+struct aie_part_mem *pmem)
+{
+ unsigned int i;
+
+ if (range->start.row + range->size.row <= 1) {
+ /* SHIM row only, no memories in this range */
+ return 0;
+ }
+ if (!pmem)
+ return NUM_MEMS_PER_TILE;
+
+ for (i = 0; i < NUM_MEMS_PER_TILE; i++) {
+ struct aie_mem *mem = [i].mem;
+
+ memcpy(>range, range, sizeof(*range));
+ if (!mem->range.start.row) {
+ mem->range.start.row = 1;
+ mem->range.size.row--;
+ }
+ }
+ /* Setup tile data memory information */
+ pmem[0].mem.offset = 0;
+ pmem[0].mem.size = KBYTES(32);
+ /* Setup program memory information */
+ pmem[1].mem.offset = 0x2;
+ pmem[1].mem.size = KBYTES(16);
+
+ return NUM_MEMS_PER_TILE;
+}
+
/**
* aie_set_shim_reset() - Set AI engine SHIM reset
* @adev: AI engine device
@@ -170,6 +205,7 @@ static int aie_reset_shim(struct aie_device *adev, struct
aie_range *range)
static const struct aie_tile_operations aie_ops = {
.get_tile_type = aie_get_tile_type,
+ .get_mem_info = aie_get_mem_info,
.reset_shim = aie_reset_shim,
};
diff --git a/drivers/misc/xilinx-ai-engine/ai-engine-internal.h
b/drivers/misc/xilinx-ai-engine/ai-engine-internal.h
index 2acd34f..e84610b 100644
--- a/drivers/misc/xilinx-ai-engine/ai-engine-internal.h
+++ b/drivers/misc/xilinx-ai-engine/ai-engine-internal.h
@@ -12,6 +12,8 @@
#include
#include
#include
+#include
+#include
#include
#include
#include
@@ -67,8 +69,30 @@ struct aie_device;
struct aie_partition;
/**
+ * struct aie_part_mem - AI engine partition memory information structure
+ * @apart: AI engine partition
+ * @dbuf: dmabuf pointer associated with the memory
+ * @mem: memory information of a type of memory
+ * @size: size of the total memories in the partition
+ *
+ * This structure is to keep the information of a type of memory in a
+ * partition. The memory information will be stored in @mem property.
+ * The following information will be keep:
+ * * memory start address offset within a tile
+ * * memory size
+ * * what tiles contain this type of memory
+ */
+struct aie_part_mem {
+ struct aie_partition *apart;
+ struct dma_buf
[PATCH v2 5/9] misc: xilinx-ai-engine: add setting shim dma bd operation
Add operation to set SHIM DMA buffer descriptor.
The following operations are added to set the buffer descriptors:
* attach DMA buffer which enables AI engine device to access the DMA
buffer memory
* detach DMA buffer which disables AI engine device to access the DMA
buffer memory
* set DMA buffer descriptor, which takes buffer descriptor contents
pointer, the dmabuf fd, and the offset to the start of dmabuf as
as argument. It validates the dmabuf and the offset and size of the
buffer. And then it calculates the DMA address of the buffer and set
the buffer descriptor content to the hardware DMA buffer descriptor.
The main logic to control what's go into the buffer descriptor and which
buffer descriptor to use is in the userspace AI engine library.
Signed-off-by: Wendy Liang
Reviewed-by: Hyun Kwon
---
drivers/misc/xilinx-ai-engine/Makefile | 1 +
drivers/misc/xilinx-ai-engine/ai-engine-aie.c | 19 +
drivers/misc/xilinx-ai-engine/ai-engine-dma.c | 481 +
drivers/misc/xilinx-ai-engine/ai-engine-internal.h | 45 ++
drivers/misc/xilinx-ai-engine/ai-engine-part.c | 17 +
include/uapi/linux/xlnx-ai-engine.h| 43 ++
6 files changed, 606 insertions(+)
create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-dma.c
diff --git a/drivers/misc/xilinx-ai-engine/Makefile
b/drivers/misc/xilinx-ai-engine/Makefile
index 2dbed42..1b743fa 100644
--- a/drivers/misc/xilinx-ai-engine/Makefile
+++ b/drivers/misc/xilinx-ai-engine/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_XILINX_AIE)+= xilinx-aie.o
xilinx-aie-$(CONFIG_XILINX_AIE) := ai-engine-aie.o \
ai-engine-dev.o \
+ ai-engine-dma.o \
ai-engine-mem.o \
ai-engine-part.o \
ai-engine-res.o \
diff --git a/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
b/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
index 7fce2f00..19c262d 100644
--- a/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
+++ b/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
@@ -107,6 +107,24 @@ static const struct aie_single_reg_field aie_col_clkbuf = {
.regoff = AIE_SHIMPL_CLKCNTR_REGOFF,
};
+static const struct aie_dma_attr aie_shimdma = {
+ .laddr = {
+ .mask = 0xU,
+ .regoff = 0U,
+ },
+ .haddr = {
+ .mask = 0xU,
+ .regoff = 0x8U,
+ },
+ .buflen = {
+ .mask = 0xU,
+ .regoff = 0x4U,
+ },
+ .bd_regoff = 0x0001d000U,
+ .num_bds = 16,
+ .bd_len = 0x14U,
+};
+
static u32 aie_get_tile_type(struct aie_location *loc)
{
if (loc->row)
@@ -232,6 +250,7 @@ int aie_device_init(struct aie_device *adev)
adev->kernel_regs = aie_kernel_regs;
adev->col_rst = _col_rst;
adev->col_clkbuf = _col_clkbuf;
+ adev->shim_dma = _shimdma;
/* Get the columns resource */
/* Get number of columns from AI engine memory resource */
diff --git a/drivers/misc/xilinx-ai-engine/ai-engine-dma.c
b/drivers/misc/xilinx-ai-engine/ai-engine-dma.c
new file mode 100644
index 000..007bec4
--- /dev/null
+++ b/drivers/misc/xilinx-ai-engine/ai-engine-dma.c
@@ -0,0 +1,481 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx AI Engine driver DMA implementation
+ *
+ * Copyright (C) 2020 Xilinx, Inc.
+ */
+
+#include "ai-engine-internal.h"
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/**
+ * struct aie_dmabuf - AI engine dmabuf information
+ * @attach: dmabuf attachment pointer
+ * @sgt: scatter/gather table
+ * @refs: refcount of the attached aie_dmabuf
+ * @node: list node
+ */
+struct aie_dmabuf {
+ struct dma_buf_attachment *attach;
+ struct sg_table *sgt;
+ refcount_t refs;
+ struct list_head node;
+};
+
+/**
+ * aie_part_find_dmabuf() - find a attached dmabuf
+ * @apart: AI engine partition
+ * @dmabuf: pointer to dmabuf
+ * @return: pointer to AI engine dmabuf struct of the found dmabuf, if dmabuf
+ * is not found, returns NULL.
+ *
+ * This function scans all the attached dmabufs to see the input dmabuf is
+ * in the list. if it is attached, return the corresponding struct aie_dmabuf
+ * pointer.
+ */
+static struct aie_dmabuf *
+aie_part_find_dmabuf(struct aie_partition *apart, struct dma_buf *dmabuf)
+{
+ struct aie_dmabuf *adbuf;
+
+ list_for_each_entry(adbuf, >dbufs, node) {
+ if (dmabuf == adbuf->attach->dmabuf)
+ return adbuf;
+ }
+
+ return NULL;
+}
+
+/**
+ * aie_part_get_dmabuf_da_from_off() - get DMA address from offset to a dmabuf
+ * @apart: AI engine partition
+ * @dmabuf_fd: dmabuf file descriptor
+ * @off: offset to the start of a dmabuf
+ * @len: memory length
+ * @return: dma addres
[PATCH v2 8/9] firmware: xilinx: Add IOCTL support for AIE ISR Clear
From: Izhar Ameer Shaikh
Latching of AIE NPI Interrupts is present in Versal ES1 Silicon Rev,
however it has been removed from ES2 rev.
As a result on ES1, in order to use the interrupt, a client needs to
request PMC to clear/ack the interrupt.
Provide an EEMI IOCTL to serve the same purpose. Note that, this will
only be applicable for ES1 rev. For ES2 and other non-silicon platforms,
this call will essentially be a NOP in the firmware.
Signed-off-by: Izhar Ameer Shaikh
Signed-off-by: Wendy Liang
---
drivers/firmware/xilinx/zynqmp.c | 14 ++
include/linux/firmware/xlnx-zynqmp.h | 8
2 files changed, 22 insertions(+)
diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
index efb8a66..7a0c6a3 100644
--- a/drivers/firmware/xilinx/zynqmp.c
+++ b/drivers/firmware/xilinx/zynqmp.c
@@ -702,6 +702,20 @@ int zynqmp_pm_set_boot_health_status(u32 value)
}
/**
+ * zynqmp_pm_clear_aie_npi_isr - Clear AI engine NPI interrupt status register
+ * @node: AI engine node id
+ * @irq_mask: Mask of AI engine NPI interrupt bit to clear
+ *
+ * Return: Returns status, either success or error+reason
+ */
+int zynqmp_pm_clear_aie_npi_isr(u32 node, u32 irq_mask)
+{
+ return zynqmp_pm_invoke_fn(PM_IOCTL, node, IOCTL_AIE_ISR_CLEAR,
+ irq_mask, 0, NULL);
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_clear_aie_npi_isr);
+
+/**
* zynqmp_pm_reset_assert - Request setting of reset (1 - assert, 0 - release)
* @reset: Reset to be configured
* @assert_flag: Flag stating should reset be asserted (1) or
diff --git a/include/linux/firmware/xlnx-zynqmp.h
b/include/linux/firmware/xlnx-zynqmp.h
index 7b6f9fc..cdc0867 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -120,6 +120,8 @@ enum pm_ioctl_id {
IOCTL_READ_PGGS = 15,
/* Set healthy bit value */
IOCTL_SET_BOOT_HEALTH_STATUS = 17,
+ /* AI engine NPI ISR clear */
+ IOCTL_AIE_ISR_CLEAR = 24,
};
enum pm_query_id {
@@ -361,6 +363,7 @@ int zynqmp_pm_write_pggs(u32 index, u32 value);
int zynqmp_pm_read_pggs(u32 index, u32 *value);
int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype);
int zynqmp_pm_set_boot_health_status(u32 value);
+int zynqmp_pm_clear_aie_npi_isr(u32 node, u32 irq_mask);
#else
static inline struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void)
{
@@ -511,6 +514,11 @@ static inline int zynqmp_pm_set_boot_health_status(u32
value)
{
return -ENODEV;
}
+
+static inline int zynqmp_pm_clear_aie_npi_isr(u32 node, u32 irq_mask)
+{
+ return -ENODEV;
+}
#endif
#endif /* __FIRMWARE_ZYNQMP_H__ */
--
2.7.4
[PATCH v2 9/9] misc: xilinx-ai-engine: Add support for servicing error interrupts
From: Nishad Saraf
AI engine errors events can be routed to generate interrupt. The
errors events routing will be done during AI engine configuration.
At runtime, Linux kernel AI engine driver monitors the interrupt and
backtracks errors events.
As error events from 400 AIE tiles and 50 shim tiles are channeled on
a single interrupt line, backtracking the source the interrupt to an
AIE module is required. To keep the top-half interrupt short,
backtracking is deferred to bottom half by scheduling a task in shared
workqueue.
Signed-off-by: Nishad Saraf
Signed-off-by: Wendy Liang
---
drivers/misc/xilinx-ai-engine/Makefile | 1 +
drivers/misc/xilinx-ai-engine/ai-engine-aie.c | 121
drivers/misc/xilinx-ai-engine/ai-engine-dev.c | 14 +
drivers/misc/xilinx-ai-engine/ai-engine-internal.h | 144 +
.../misc/xilinx-ai-engine/ai-engine-interrupt.c| 659 +
drivers/misc/xilinx-ai-engine/ai-engine-part.c | 44 ++
drivers/misc/xilinx-ai-engine/ai-engine-res.c | 54 ++
7 files changed, 1037 insertions(+)
create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-interrupt.c
diff --git a/drivers/misc/xilinx-ai-engine/Makefile
b/drivers/misc/xilinx-ai-engine/Makefile
index 2e67b25..9607ecb 100644
--- a/drivers/misc/xilinx-ai-engine/Makefile
+++ b/drivers/misc/xilinx-ai-engine/Makefile
@@ -9,6 +9,7 @@ xilinx-aie-$(CONFIG_XILINX_AIE) := ai-engine-aie.o \
ai-engine-clock.o \
ai-engine-dev.o \
ai-engine-dma.o \
+ ai-engine-interrupt.o \
ai-engine-mem.o \
ai-engine-part.o \
ai-engine-res.o \
diff --git a/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
b/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
index ff721b3..af0f997 100644
--- a/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
+++ b/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
@@ -33,7 +33,10 @@
#define AIE_SHIMPL_CLKCNTR_REGOFF 0x00036040U
#define AIE_SHIMPL_COLRESET_REGOFF 0x00036048U
#define AIE_SHIMPL_RESET_REGOFF0x0003604cU
+#define AIE_SHIMPL_GROUP_ERROR_REGOFF 0x0003450cU
#define AIE_TILE_CORE_CLKCNTR_REGOFF 0x00036040U
+#define AIE_TILE_CORE_GROUP_ERROR_REGOFF 0x00034510U
+#define AIE_TILE_MEM_GROUP_ERROR_REGOFF0x00014514U
/*
* Register masks
@@ -93,11 +96,27 @@ static const struct aie_tile_regs aie_kernel_regs[] = {
.soff = AIE_SHIMPL_CLKCNTR_REGOFF,
.eoff = AIE_SHIMPL_CLKCNTR_REGOFF,
},
+ /* SHIM group error enable */
+ {.attribute = (AIE_TILE_TYPE_SHIMPL | AIE_TILE_TYPE_SHIMNOC) <<
+ AIE_REGS_ATTR_TILE_TYPE_SHIFT,
+.soff = AIE_SHIMPL_GROUP_ERROR_REGOFF,
+.eoff = AIE_SHIMPL_GROUP_ERROR_REGOFF,
+ },
/* Tile clock control */
{.attribute = AIE_TILE_TYPE_TILE << AIE_REGS_ATTR_TILE_TYPE_SHIFT,
.soff = AIE_TILE_CORE_CLKCNTR_REGOFF,
.eoff = AIE_TILE_CORE_CLKCNTR_REGOFF,
},
+ /* Tile group error for core module */
+ {.attribute = AIE_TILE_TYPE_TILE << AIE_REGS_ATTR_TILE_TYPE_SHIFT,
+.soff = AIE_TILE_CORE_GROUP_ERROR_REGOFF,
+.eoff = AIE_TILE_CORE_GROUP_ERROR_REGOFF,
+ },
+ /* Tile group error for memory module */
+ {.attribute = AIE_TILE_TYPE_TILE << AIE_REGS_ATTR_TILE_TYPE_SHIFT,
+.soff = AIE_TILE_MEM_GROUP_ERROR_REGOFF,
+.eoff = AIE_TILE_MEM_GROUP_ERROR_REGOFF,
+ },
};
static const struct aie_single_reg_field aie_col_rst = {
@@ -128,6 +147,103 @@ static const struct aie_dma_attr aie_shimdma = {
.bd_len = 0x14U,
};
+static const struct aie_event_attr aie_pl_event = {
+ .bc_event = {
+ .mask = GENMASK(6, 0),
+ .regoff = 0x0U,
+ },
+ .group_error = {
+ .mask = GENMASK(10, 0),
+ .regoff = 0xcU,
+ },
+ .bc_regoff = 0x34010U,
+ .status_regoff = 0x34200U,
+ .group_regoff = 0x34500U,
+ .base_error_event = 62U,
+ .num_broadcasts = 16U,
+ .base_bc_event = 107U,
+ .num_events = 128U,
+};
+
+static const struct aie_event_attr aie_mem_event = {
+ .bc_event = {
+ .mask = GENMASK(6, 0),
+ .regoff = 0x0U,
+ },
+ .group_error = {
+ .mask = GENMASK(13, 0),
+ .regoff = 0x14U,
+ },
+ .bc_regoff = 0x14010U,
+ .status_regoff = 0x14200U,
+ .group_regoff = 0x14500U,
+ .base_error_event = 87U,
+ .num_broadcasts = 16U,
+ .base_bc_event = 107U,
+ .num_events = 128U,
+};
+
+static const struct aie_event_attr aie_core_event = {
+ .bc_event = {
+ .mask = GENMASK(6, 0),
+
[PATCH v2 3/9] misc: xilinx-ai-engine: Implement AI engine cleanup sequence
When AI engine partition is released, that is if no one is using the AI
engine partition, by default, it will cleanup the partition by doing the
following:
* reset the columns
* reset the SHIMs
* clear data and program memory
* gate all the tiles
If user doesn't want the partition is reset when the partition is
released, user can set the control flag to indicate not to reset the
partition when the user requests the partition.
If partition the not to reset partition control flag is set, it will
not execute the above cleanup sequence when the partition is released.
Signed-off-by: Wendy Liang
Reviewed-by: Hyun Kwon
---
drivers/misc/xilinx-ai-engine/Makefile | 3 +-
drivers/misc/xilinx-ai-engine/ai-engine-aie.c | 92
drivers/misc/xilinx-ai-engine/ai-engine-dev.c | 2 +
drivers/misc/xilinx-ai-engine/ai-engine-internal.h | 34 ++
drivers/misc/xilinx-ai-engine/ai-engine-part.c | 7 +-
drivers/misc/xilinx-ai-engine/ai-engine-reset.c| 121 +
include/uapi/linux/xlnx-ai-engine.h| 6 +
7 files changed, 259 insertions(+), 6 deletions(-)
create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-reset.c
diff --git a/drivers/misc/xilinx-ai-engine/Makefile
b/drivers/misc/xilinx-ai-engine/Makefile
index 7827a0a..39bec61 100644
--- a/drivers/misc/xilinx-ai-engine/Makefile
+++ b/drivers/misc/xilinx-ai-engine/Makefile
@@ -8,4 +8,5 @@ obj-$(CONFIG_XILINX_AIE)+= xilinx-aie.o
xilinx-aie-$(CONFIG_XILINX_AIE) := ai-engine-aie.o \
ai-engine-dev.o \
ai-engine-part.o \
- ai-engine-res.o
+ ai-engine-res.o \
+ ai-engine-reset.o
diff --git a/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
b/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
index 319260f..36127f0 100644
--- a/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
+++ b/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
@@ -5,6 +5,9 @@
* Copyright (C) 2020 Xilinx, Inc.
*/
+#include
+#include
+#include
#include
#include "ai-engine-internal.h"
@@ -24,9 +27,25 @@
#define AIE_SHIMPL_L1INTR_MASK_A_REGOFF0x00035000U
#define AIE_SHIMPL_L1INTR_BLOCK_NORTH_B_REGOFF 0x00035050U
#define AIE_SHIMPL_CLKCNTR_REGOFF 0x00036040U
+#define AIE_SHIMPL_COLRESET_REGOFF 0x00036048U
#define AIE_SHIMPL_RESET_REGOFF0x0003604cU
#define AIE_TILE_CORE_CLKCNTR_REGOFF 0x00036040U
+/*
+ * Register masks
+ */
+#define AIE_SHIMPL_SHIMRST_MASK0x1U
+#define AIE_SHIMPL_COLRST_MASK 0x1U
+#define AIE_SHIMPL_CLKCNTR_COLBUF_MASK 0x1U
+
+/*
+ * AI engine SHIM reset ID.
+ * TODO: it should follow the Linux reset framework. The ID should be in the
+ * device tree. However, as versal resets is not ready, we hardcode it in the
+ * driver.
+ */
+#define VERSAL_PM_RST_AIE_SHIM_ID 0xc10405fU
+
static const struct aie_tile_regs aie_kernel_regs[] = {
/* SHIM AXI MM Config */
{.attribute = AIE_TILE_TYPE_SHIMNOC << AIE_REGS_ATTR_TILE_TYPE_SHIFT,
@@ -49,6 +68,12 @@ static const struct aie_tile_regs aie_kernel_regs[] = {
.soff = AIE_SHIMPL_L1INTR_MASK_A_REGOFF,
.eoff = AIE_SHIMPL_L1INTR_BLOCK_NORTH_B_REGOFF,
},
+ /* SHIM column reset */
+ {.attribute = (AIE_TILE_TYPE_SHIMPL | AIE_TILE_TYPE_SHIMNOC) <<
+ AIE_REGS_ATTR_TILE_TYPE_SHIFT,
+.soff = AIE_SHIMPL_COLRESET_REGOFF,
+.eoff = AIE_SHIMPL_COLRESET_REGOFF,
+ },
/* SHIM reset Enable */
{.attribute = (AIE_TILE_TYPE_SHIMPL | AIE_TILE_TYPE_SHIMNOC) <<
AIE_REGS_ATTR_TILE_TYPE_SHIFT,
@@ -68,6 +93,16 @@ static const struct aie_tile_regs aie_kernel_regs[] = {
},
};
+static const struct aie_single_reg_field aie_col_rst = {
+ .mask = AIE_SHIMPL_COLRST_MASK,
+ .regoff = AIE_SHIMPL_COLRESET_REGOFF,
+};
+
+static const struct aie_single_reg_field aie_col_clkbuf = {
+ .mask = AIE_SHIMPL_CLKCNTR_COLBUF_MASK,
+ .regoff = AIE_SHIMPL_CLKCNTR_REGOFF,
+};
+
static u32 aie_get_tile_type(struct aie_location *loc)
{
if (loc->row)
@@ -79,8 +114,63 @@ static u32 aie_get_tile_type(struct aie_location *loc)
return AIE_TILE_TYPE_SHIMNOC;
}
+/**
+ * aie_set_shim_reset() - Set AI engine SHIM reset
+ * @adev: AI engine device
+ * @range: range of AI engine tiles
+ * @assert: true to set reset, false to unset reset
+ */
+static void aie_set_shim_reset(struct aie_device *adev,
+ struct aie_range *range, bool assert)
+{
+ u32 c;
+ u32 val;
+ struct aie_location loc;
+
+ val = FIELD_PREP(AIE_SHIMPL_SHIMRST_MASK, (assert ? 1 : 0));
+ loc.row = 0;
+ for (c = range->start.col; c < range->sta
[PATCH v2 7/9] misc: xilinx-ai-engine: Add support to request device management services
From: Nishad Saraf
Platform management services like device control, resets, power
management, etc. are provided by Platform, Loader and Manager(PLM)
through firmware driver APIs. For requesting some of these services,
this change reads AI Engine platform management node ID from DT node.
Some other features like clearing interrupts in the NoC interconnect
might only be valid for particular silicon revisions. For supporting
such silicon specific features, AI Engine driver will query and store
this information in device instance. While at it, this change makes
EEMI operations accessible to all the other source files in the
driver.
Signed-off-by: Nishad Saraf
Signed-off-by: Wendy Liang
---
drivers/misc/xilinx-ai-engine/ai-engine-dev.c | 25 +-
drivers/misc/xilinx-ai-engine/ai-engine-internal.h | 6 ++
2 files changed, 30 insertions(+), 1 deletion(-)
diff --git a/drivers/misc/xilinx-ai-engine/ai-engine-dev.c
b/drivers/misc/xilinx-ai-engine/ai-engine-dev.c
index 7e69ff4..78eae90 100644
--- a/drivers/misc/xilinx-ai-engine/ai-engine-dev.c
+++ b/drivers/misc/xilinx-ai-engine/ai-engine-dev.c
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -25,7 +26,8 @@
#include "ai-engine-internal.h"
-#define AIE_DEV_MAX(MINORMASK + 1)
+#define AIE_DEV_MAX(MINORMASK + 1)
+#define VERSAL_SILICON_REV_MASKGENMASK(31, 28)
static dev_t aie_major;
struct class *aie_class;
@@ -318,6 +320,7 @@ static int xilinx_ai_engine_probe(struct platform_device
*pdev)
{
struct aie_device *adev;
struct device *dev;
+ u32 idcode, version, pm_reg[2];
int ret;
adev = devm_kzalloc(>dev, sizeof(*adev), GFP_KERNEL);
@@ -345,6 +348,26 @@ static int xilinx_ai_engine_probe(struct platform_device
*pdev)
return ret;
}
+ /*
+* AI Engine platform management node ID is required for requesting
+* services from firmware driver.
+*/
+ ret = of_property_read_u32_array(pdev->dev.of_node, "power-domains",
+pm_reg, ARRAY_SIZE(pm_reg));
+ if (ret < 0) {
+ dev_err(>dev,
+ "Failed to read power management information\n");
+ return ret;
+ }
+ adev->pm_node_id = pm_reg[1];
+
+ ret = zynqmp_pm_get_chipid(, );
+ if (ret < 0) {
+ dev_err(>dev, "Failed to get chip ID\n");
+ return ret;
+ }
+ adev->version = FIELD_GET(VERSAL_SILICON_REV_MASK, idcode);
+
dev = >dev;
device_initialize(dev);
dev->class = aie_class;
diff --git a/drivers/misc/xilinx-ai-engine/ai-engine-internal.h
b/drivers/misc/xilinx-ai-engine/ai-engine-internal.h
index 131d22a..b21b7025 100644
--- a/drivers/misc/xilinx-ai-engine/ai-engine-internal.h
+++ b/drivers/misc/xilinx-ai-engine/ai-engine-internal.h
@@ -41,6 +41,10 @@
#define AIE_REGS_ATTR_PERM_MASKGENMASK(15, \
AIE_REGS_ATTR_PERM_SHIFT)
+/* Silicon Engineering Sample(ES) revision ID */
+#define VERSAL_ES1_REV_ID 0x0
+#define VERSAL_ES2_REV_ID 0x1
+
/**
* struct aie_tile_regs - contiguous range of AI engine register
* within an AI engine tile
@@ -173,6 +177,7 @@ struct aie_resource {
* while columns are occupied by partitions.
* @num_kernel_regs: number of kernel only registers range
* @version: AI engine device version
+ * @pm_node_id: AI Engine platform management node ID
*/
struct aie_device {
struct list_head partitions;
@@ -193,6 +198,7 @@ struct aie_device {
u32 row_shift;
u32 num_kernel_regs;
int version;
+ u32 pm_node_id;
};
/**
--
2.7.4
[PATCH v2 0/9] Xilinx AI engine kernel driver
AI engine is the acceleration engine provided by Xilinx. These engines provide high compute density for vector-based algorithms, and flexible custom compute and data movement. It has core tiles for compute and shim tiles to interface the FPGA fabric. You can check the AI engine architecture document for more hardware details: https://www.xilinx.com/support/documentation/architecture-manuals/am009-versal-ai-engine.pdf This patch series adds a Linux kernel driver to manage the Xilinx AI engine array device and AI engine partitions (groups of AI engine tiles dedicated to an application). v2: * Fix dtschema check errors * Fix test bot warning on interrupt implementation. Removed set but unused varaible. * Fix compilation unused function warning of firmware change in case ZynqMP firmware is not configured * There are other warning on ZynqMP firmware reported from testbot which is not introduced by this patch set. "[PATCH] firmware: xlnx-zynqmp: fix compilation warning" is submitted for those fixes. Izhar Ameer Shaikh (1): firmware: xilinx: Add IOCTL support for AIE ISR Clear Nishad Saraf (2): misc: xilinx-ai-engine: Add support to request device management services misc: xilinx-ai-engine: Add support for servicing error interrupts Wendy Liang (6): dt-binding: soc: xilinx: ai-engine: Add AI engine binding misc: Add Xilinx AI engine device driver misc: xilinx-ai-engine: Implement AI engine cleanup sequence misc: xilinx-ai-engine: expose AI engine tile memories to userspace misc: xilinx-ai-engine: add setting shim dma bd operation misc: xilinx-ai-engine: add request and release tiles .../bindings/soc/xilinx/xlnx,ai-engine.yaml| 126 MAINTAINERS| 8 + drivers/firmware/xilinx/zynqmp.c | 14 + drivers/misc/Kconfig | 12 + drivers/misc/Makefile | 1 + drivers/misc/xilinx-ai-engine/Makefile | 16 + drivers/misc/xilinx-ai-engine/ai-engine-aie.c | 608 +++ drivers/misc/xilinx-ai-engine/ai-engine-clock.c| 244 drivers/misc/xilinx-ai-engine/ai-engine-dev.c | 492 +++ drivers/misc/xilinx-ai-engine/ai-engine-dma.c | 481 +++ drivers/misc/xilinx-ai-engine/ai-engine-internal.h | 519 .../misc/xilinx-ai-engine/ai-engine-interrupt.c| 659 + drivers/misc/xilinx-ai-engine/ai-engine-mem.c | 274 + drivers/misc/xilinx-ai-engine/ai-engine-part.c | 635 drivers/misc/xilinx-ai-engine/ai-engine-res.c | 219 +++ drivers/misc/xilinx-ai-engine/ai-engine-reset.c| 159 + include/linux/firmware/xlnx-zynqmp.h | 8 + include/uapi/linux/xlnx-ai-engine.h| 236 18 files changed, 4711 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/xilinx/xlnx,ai-engine.yaml create mode 100644 drivers/misc/xilinx-ai-engine/Makefile create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-aie.c create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-clock.c create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-dev.c create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-dma.c create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-internal.h create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-interrupt.c create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-mem.c create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-part.c create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-res.c create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-reset.c create mode 100644 include/uapi/linux/xlnx-ai-engine.h -- 2.7.4
[PATCH v2 1/9] dt-binding: soc: xilinx: ai-engine: Add AI engine binding
Xilinx AI engine array can be partitioned statically for different
applications. In the device tree, there will be device node for the AI
engine device, and device nodes for the statically configured AI engine
partitions. Each of the statically configured partition has a partition
ID in the system.
Signed-off-by: Wendy Liang
---
.../bindings/soc/xilinx/xlnx,ai-engine.yaml| 126 +
1 file changed, 126 insertions(+)
create mode 100644
Documentation/devicetree/bindings/soc/xilinx/xlnx,ai-engine.yaml
diff --git a/Documentation/devicetree/bindings/soc/xilinx/xlnx,ai-engine.yaml
b/Documentation/devicetree/bindings/soc/xilinx/xlnx,ai-engine.yaml
new file mode 100644
index 000..1de5623
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/xilinx/xlnx,ai-engine.yaml
@@ -0,0 +1,126 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/xilinx/xlnx,ai-engine.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx AI Engine
+
+maintainers:
+ - Wendy Liang
+
+description: |+
+ The Xilinx AI Engine is a tile processor with many cores (up to 400) that
+ can run in parallel. The data routing between cores is configured through
+ internal switches, and shim tiles interface with external interconnect, such
+ as memory or PL.
+
+properties:
+ compatible:
+const: xlnx,ai-engine-v1.0
+
+ reg:
+description: |
+ Physical base address and length of the device registers.
+ The AI engine address space assigned to Linux is defined by Xilinx
+ platform design tool.
+
+ '#address-cells':
+enum: [2]
+description: |
+ size of cell to describe AI engine range of tiles address.
+ It is the location of the starting tile of the range.
+ As the AI engine tiles are 2D array, the location of a tile
+ is presented as (column, row), the address cell is 2.
+
+ '#size-cells':
+enum: [2]
+description: |
+ size of cell to describe AI engine range of tiles size.
+ As the AI engine tiles are 2D array, the size cell is 2.
+
+ power-domains:
+maxItems: 1
+description: phandle to the associated power domain
+
+ interrupts:
+maxItems: 3
+
+ interrupt-names:
+description: |
+ Should be "interrupt1", "interrupt2" or "interrupt3".
+
+required:
+ - compatible
+ - reg
+ - '#address-cells'
+ - '#size-cells'
+ - power-domains
+ - interrupt-parent
+ - interrupts
+ - interrupt-names
+
+patternProperties:
+ "^aie_partition@[0-9]+$":
+type: object
+description: |
+ AI engine partition which is a group of column based tiles of the AI
+ engine device. Each AI engine partition is isolated from the other
+ AI engine partitions. An AI engine partition is defined by Xilinx
+ platform design tools. Each partition has a SHIM row and core tiles rows.
+ A SHIM row contains SHIM tiles which are the interface to external
+ components. AXI master can access AI engine registers, push data to and
+ fetch data from AI engine through the SHIM tiles. Core tiles are the
+ compute tiles.
+
+properties:
+ reg:
+description: |
+ It describes the group of tiles of the AI engine partition. It needs
+ to include the SHIM row. The format is defined by the parent AI
engine
+ device node's '#address-cells' and '#size-cells' properties. e.g. a
v1
+ AI engine device has 2D tiles array, the first row is SHIM row. A
+ partition which has 50 columns and 8 rows of core tiles and 1 row of
+ SHIM tiles will be presented as <0 0 50 9>.
+
+ label:
+maxItems: 1
+
+ xlnx,partition-id:
+$ref: /schemas/types.yaml#/definitions/uint32
+description: |
+ AI engine partition ID, which is defined by Xilinx platform design
+ tool to identify the AI engine partition in the system.
+
+required:
+ - reg
+ - xlnx,partition-id
+additionalProperties: false
+
+additionalProperties: false
+
+examples:
+ - |
+bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ ai_engine: ai-engine@200 {
+compatible = "xlnx,ai-engine-v1.0";
+reg = <0x200 0x0 0x1 0x0>;
+#address-cells = <2>;
+#size-cells = <2>;
+power-domains = <_firmware 0x18224072>;
+interrupt-parent = <>;
+interrupts = <0x0 0x94 0x4>,
+ <0x0 0x95 0x4>,
+ <0x0 0x96 0x4>;
+interrupt-names = "interrupt1", "interrupt2", "interrupt3";
+
+aie_partition0: aie_partition@0 {
+/* 50 columns and 8 core tile rows + 1 SHIM row */
+reg = <0 0 50 9>;
+xlnx,partition-id = <1>;
+};
+ };
+};
--
2.7.4
[PATCH] firmware: xlnx-zynqmp: fix compilation warning
Fix compilation warning when ZYNQMP_FIRMWARE is not defined. include/linux/firmware/xlnx-zynqmp.h: In function 'zynqmp_pm_get_eemi_ops': include/linux/firmware/xlnx-zynqmp.h:363:9: error: implicit declaration of function 'ERR_PTR' [-Werror=implicit-function-declaration] 363 | return ERR_PTR(-ENODEV); include/linux/firmware/xlnx-zynqmp.h:363:18: note: each undeclared identifier is reported only once for each function it appears in include/linux/firmware/xlnx-zynqmp.h: In function 'zynqmp_pm_get_api_version': include/linux/firmware/xlnx-zynqmp.h:367:10: error: 'ENODEV' undeclared (first use in this function) 367 | return -ENODEV; | ^~ Signed-off-by: Wendy Liang --- include/linux/firmware/xlnx-zynqmp.h | 4 1 file changed, 4 insertions(+) diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h index 5968df8..7b6f9fc 100644 --- a/include/linux/firmware/xlnx-zynqmp.h +++ b/include/linux/firmware/xlnx-zynqmp.h @@ -13,6 +13,10 @@ #ifndef __FIRMWARE_ZYNQMP_H__ #define __FIRMWARE_ZYNQMP_H__ +#if !IS_REACHABLE(CONFIG_ZYNQMP_FIRMWARE) +#include +#endif + #define ZYNQMP_PM_VERSION_MAJOR1 #define ZYNQMP_PM_VERSION_MINOR0 -- 2.7.4
[PATCH 9/9] misc: xilinx-ai-engine: Add support for servicing error interrupts
From: Nishad Saraf
AI engine errors events can be routed to generate interrupt. The
errors events routing will be done during AI engine configuration.
At runtime, Linux kernel AI engine driver monitors the interrupt and
backtracks errors events.
As error events from 400 AIE tiles and 50 shim tiles are channeled on
a single interrupt line, backtracking the source the interrupt to an
AIE module is required. To keep the top-half interrupt short,
backtracking is deferred to bottom half by scheduling a task in shared
workqueue.
Signed-off-by: Nishad Saraf
Signed-off-by: Wendy Liang
---
drivers/misc/xilinx-ai-engine/Makefile | 1 +
drivers/misc/xilinx-ai-engine/ai-engine-aie.c | 121
drivers/misc/xilinx-ai-engine/ai-engine-dev.c | 14 +
drivers/misc/xilinx-ai-engine/ai-engine-internal.h | 144 +
.../misc/xilinx-ai-engine/ai-engine-interrupt.c| 661 +
drivers/misc/xilinx-ai-engine/ai-engine-part.c | 44 ++
drivers/misc/xilinx-ai-engine/ai-engine-res.c | 54 ++
7 files changed, 1039 insertions(+)
create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-interrupt.c
diff --git a/drivers/misc/xilinx-ai-engine/Makefile
b/drivers/misc/xilinx-ai-engine/Makefile
index 2e67b25..9607ecb 100644
--- a/drivers/misc/xilinx-ai-engine/Makefile
+++ b/drivers/misc/xilinx-ai-engine/Makefile
@@ -9,6 +9,7 @@ xilinx-aie-$(CONFIG_XILINX_AIE) := ai-engine-aie.o \
ai-engine-clock.o \
ai-engine-dev.o \
ai-engine-dma.o \
+ ai-engine-interrupt.o \
ai-engine-mem.o \
ai-engine-part.o \
ai-engine-res.o \
diff --git a/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
b/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
index ff721b3..af0f997 100644
--- a/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
+++ b/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
@@ -33,7 +33,10 @@
#define AIE_SHIMPL_CLKCNTR_REGOFF 0x00036040U
#define AIE_SHIMPL_COLRESET_REGOFF 0x00036048U
#define AIE_SHIMPL_RESET_REGOFF0x0003604cU
+#define AIE_SHIMPL_GROUP_ERROR_REGOFF 0x0003450cU
#define AIE_TILE_CORE_CLKCNTR_REGOFF 0x00036040U
+#define AIE_TILE_CORE_GROUP_ERROR_REGOFF 0x00034510U
+#define AIE_TILE_MEM_GROUP_ERROR_REGOFF0x00014514U
/*
* Register masks
@@ -93,11 +96,27 @@ static const struct aie_tile_regs aie_kernel_regs[] = {
.soff = AIE_SHIMPL_CLKCNTR_REGOFF,
.eoff = AIE_SHIMPL_CLKCNTR_REGOFF,
},
+ /* SHIM group error enable */
+ {.attribute = (AIE_TILE_TYPE_SHIMPL | AIE_TILE_TYPE_SHIMNOC) <<
+ AIE_REGS_ATTR_TILE_TYPE_SHIFT,
+.soff = AIE_SHIMPL_GROUP_ERROR_REGOFF,
+.eoff = AIE_SHIMPL_GROUP_ERROR_REGOFF,
+ },
/* Tile clock control */
{.attribute = AIE_TILE_TYPE_TILE << AIE_REGS_ATTR_TILE_TYPE_SHIFT,
.soff = AIE_TILE_CORE_CLKCNTR_REGOFF,
.eoff = AIE_TILE_CORE_CLKCNTR_REGOFF,
},
+ /* Tile group error for core module */
+ {.attribute = AIE_TILE_TYPE_TILE << AIE_REGS_ATTR_TILE_TYPE_SHIFT,
+.soff = AIE_TILE_CORE_GROUP_ERROR_REGOFF,
+.eoff = AIE_TILE_CORE_GROUP_ERROR_REGOFF,
+ },
+ /* Tile group error for memory module */
+ {.attribute = AIE_TILE_TYPE_TILE << AIE_REGS_ATTR_TILE_TYPE_SHIFT,
+.soff = AIE_TILE_MEM_GROUP_ERROR_REGOFF,
+.eoff = AIE_TILE_MEM_GROUP_ERROR_REGOFF,
+ },
};
static const struct aie_single_reg_field aie_col_rst = {
@@ -128,6 +147,103 @@ static const struct aie_dma_attr aie_shimdma = {
.bd_len = 0x14U,
};
+static const struct aie_event_attr aie_pl_event = {
+ .bc_event = {
+ .mask = GENMASK(6, 0),
+ .regoff = 0x0U,
+ },
+ .group_error = {
+ .mask = GENMASK(10, 0),
+ .regoff = 0xcU,
+ },
+ .bc_regoff = 0x34010U,
+ .status_regoff = 0x34200U,
+ .group_regoff = 0x34500U,
+ .base_error_event = 62U,
+ .num_broadcasts = 16U,
+ .base_bc_event = 107U,
+ .num_events = 128U,
+};
+
+static const struct aie_event_attr aie_mem_event = {
+ .bc_event = {
+ .mask = GENMASK(6, 0),
+ .regoff = 0x0U,
+ },
+ .group_error = {
+ .mask = GENMASK(13, 0),
+ .regoff = 0x14U,
+ },
+ .bc_regoff = 0x14010U,
+ .status_regoff = 0x14200U,
+ .group_regoff = 0x14500U,
+ .base_error_event = 87U,
+ .num_broadcasts = 16U,
+ .base_bc_event = 107U,
+ .num_events = 128U,
+};
+
+static const struct aie_event_attr aie_core_event = {
+ .bc_event = {
+ .mask = GENMASK(6, 0),
+
[PATCH 2/9] misc: Add Xilinx AI engine device driver
Create AI engine device/partition hierarchical structure. Each AI engine device can have multiple logical partitions(groups of AI engine tiles). Each partition is column based and has its own node ID in the system. AI engine device driver manages its partitions. Applications can access AI engine partition through the AI engine partition driver instance. AI engine registers write is moved to kernel as there are registers in the AI engine array needs privilege permission. Signed-off-by: Wendy Liang Signed-off-by: Hyun Kwon --- MAINTAINERS| 8 + drivers/misc/Kconfig | 12 + drivers/misc/Makefile | 1 + drivers/misc/xilinx-ai-engine/Makefile | 11 + drivers/misc/xilinx-ai-engine/ai-engine-aie.c | 115 + drivers/misc/xilinx-ai-engine/ai-engine-dev.c | 448 ++ drivers/misc/xilinx-ai-engine/ai-engine-internal.h | 226 ++ drivers/misc/xilinx-ai-engine/ai-engine-part.c | 498 + drivers/misc/xilinx-ai-engine/ai-engine-res.c | 114 + include/uapi/linux/xlnx-ai-engine.h| 107 + 10 files changed, 1540 insertions(+) create mode 100644 drivers/misc/xilinx-ai-engine/Makefile create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-aie.c create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-dev.c create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-internal.h create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-part.c create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-res.c create mode 100644 include/uapi/linux/xlnx-ai-engine.h diff --git a/MAINTAINERS b/MAINTAINERS index 5cc595a..40e3351 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19283,6 +19283,14 @@ T: git https://github.com/Xilinx/linux-xlnx.git F: Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.yaml F: drivers/phy/xilinx/phy-zynqmp.c +XILINX AI ENGINE DRIVER +M: Wendy Liang +S: Supported +F: Documentation/devicetree/bindings/soc/xilinx/xlnx,ai-engine.yaml +F: drivers/misc/xilinx-ai-engine/ +F: include/linux/xlnx-ai-engine.h +F: include/uapi/linux/xlnx-ai-engine.h + XILLYBUS DRIVER M: Eli Billauer L: linux-kernel@vger.kernel.org diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index fafa8b0..0b8ce4d 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -444,6 +444,18 @@ config XILINX_SDFEC If unsure, say N. +config XILINX_AIE + tristate "Xilinx AI engine" + depends on ARM64 || COMPILE_TEST + help + This option enables support for the Xilinx AI engine driver. + One Xilinx AI engine device can have multiple partitions (groups of + AI engine tiles). Xilinx AI engine device driver instance manages + AI engine partitions. User application access its partitions through + AI engine partition instance file operations. + + If unsure, say N + config MISC_RTSX tristate default MISC_RTSX_PCI || MISC_RTSX_USB diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index d23231e..2176b18 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -57,3 +57,4 @@ obj-$(CONFIG_HABANA_AI) += habanalabs/ obj-$(CONFIG_UACCE)+= uacce/ obj-$(CONFIG_XILINX_SDFEC) += xilinx_sdfec.o obj-$(CONFIG_HISI_HIKEY_USB) += hisi_hikey_usb.o +obj-$(CONFIG_XILINX_AIE) += xilinx-ai-engine/ diff --git a/drivers/misc/xilinx-ai-engine/Makefile b/drivers/misc/xilinx-ai-engine/Makefile new file mode 100644 index 000..7827a0a --- /dev/null +++ b/drivers/misc/xilinx-ai-engine/Makefile @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Makefile for Xilinx AI engine device driver +# + +obj-$(CONFIG_XILINX_AIE) += xilinx-aie.o + +xilinx-aie-$(CONFIG_XILINX_AIE) := ai-engine-aie.o \ + ai-engine-dev.o \ + ai-engine-part.o \ + ai-engine-res.o diff --git a/drivers/misc/xilinx-ai-engine/ai-engine-aie.c b/drivers/misc/xilinx-ai-engine/ai-engine-aie.c new file mode 100644 index 000..319260f --- /dev/null +++ b/drivers/misc/xilinx-ai-engine/ai-engine-aie.c @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx AI Engine driver AIE device specific implementation + * + * Copyright (C) 2020 Xilinx, Inc. + */ + +#include + +#include "ai-engine-internal.h" + +#define AIE_ARRAY_SHIFT30U +#define AIE_COL_SHIFT 23U +#define AIE_ROW_SHIFT 18U + +/* + * Registers offsets + */ +#define AIE_SHIMNOC_L2INTR_MASK_REGOFF 0x00015000U +#define AIE_SHIMNOC_L2INTR_INTR_REGOFF 0x00015010U +#define AIE_SHIMNOC_DMA_BD0_ADDRLOW_REGOFF 0x0001d000U +#define AIE_SHIMNOC_DMA_BD15_PACKET_REGOFF 0x0001d13cU +#define AIE_SHIMNOC_AXIMM_REGOFF
[PATCH 6/9] misc: xilinx-ai-engine: add request and release tiles
Add request/release and related clock gating functions to AI engine
driver:
* scanning when the partition is being requested to know which tiles
are in use.
* check if a tile is gated or not
* tiles requesting and releasing ioctl so that user application can
enable/disable tiles at runtime.
Signed-off-by: Wendy Liang
Reviewed-by: Hyun Kwon
---
drivers/misc/xilinx-ai-engine/Makefile | 1 +
drivers/misc/xilinx-ai-engine/ai-engine-aie.c | 227 ++-
drivers/misc/xilinx-ai-engine/ai-engine-clock.c| 244 +
drivers/misc/xilinx-ai-engine/ai-engine-dev.c | 19 +-
drivers/misc/xilinx-ai-engine/ai-engine-internal.h | 34 +++
drivers/misc/xilinx-ai-engine/ai-engine-part.c | 32 +++
drivers/misc/xilinx-ai-engine/ai-engine-res.c | 51 +
include/uapi/linux/xlnx-ai-engine.h| 31 +++
8 files changed, 631 insertions(+), 8 deletions(-)
create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-clock.c
diff --git a/drivers/misc/xilinx-ai-engine/Makefile
b/drivers/misc/xilinx-ai-engine/Makefile
index 1b743fa..2e67b25 100644
--- a/drivers/misc/xilinx-ai-engine/Makefile
+++ b/drivers/misc/xilinx-ai-engine/Makefile
@@ -6,6 +6,7 @@
obj-$(CONFIG_XILINX_AIE) += xilinx-aie.o
xilinx-aie-$(CONFIG_XILINX_AIE) := ai-engine-aie.o \
+ ai-engine-clock.o \
ai-engine-dev.o \
ai-engine-dma.o \
ai-engine-mem.o \
diff --git a/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
b/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
index 19c262d..ff721b3 100644
--- a/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
+++ b/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
@@ -41,6 +41,9 @@
#define AIE_SHIMPL_SHIMRST_MASK0x1U
#define AIE_SHIMPL_COLRST_MASK 0x1U
#define AIE_SHIMPL_CLKCNTR_COLBUF_MASK 0x1U
+#define AIE_SHIMPL_CLKCNTR_NEXTCLK_MASKBIT(1)
+#define AIE_TILE_CLKCNTR_COLBUF_MASK BIT(0)
+#define AIE_TILE_CLKCNTR_NEXTCLK_MASK BIT(1)
/*
* AI engine SHIM reset ID.
@@ -221,10 +224,232 @@ static int aie_reset_shim(struct aie_device *adev,
struct aie_range *range)
return 0;
}
+static int aie_init_part_clk_state(struct aie_partition *apart)
+{
+ int ret, num_tiles;
+
+ num_tiles = apart->range.size.col * (apart->range.size.row - 1);
+
+ ret = aie_resource_initialize(>cores_clk_state, num_tiles);
+ if (ret) {
+ dev_err(>dev,
+ "failed to initialize cores clock state resource.\n");
+ return ret;
+ }
+
+ ret = aie_resource_initialize(>tiles_inuse, num_tiles);
+ if (ret) {
+ dev_err(>dev,
+ "failed to initialize tiles in use resource.\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int aie_scan_part_clocks(struct aie_partition *apart)
+{
+ struct aie_device *adev = apart->adev;
+ struct aie_range *range = >range;
+ struct aie_location loc;
+
+ /* Clear the bitmap of cores and memories clock state */
+ aie_resource_put_region(>cores_clk_state, 0,
+ apart->cores_clk_state.total);
+
+ for (loc.col = range->start.col;
+loc.col < range->start.col + range->size.col;
+loc.col++) {
+ for (loc.row = range->start.row;
+loc.row < range->start.row + range->size.row - 1;
+loc.row++) {
+ void __iomem *va;
+ u32 val, nbitpos;
+
+ /*
+* Reading registers of the current tile to see the next
+* tile is clock gated.
+*/
+ nbitpos = loc.col * (range->size.row - 1) + loc.row;
+
+ if (aie_get_tile_type() != AIE_TILE_TYPE_TILE) {
+ /* Checks shim tile for next core tile */
+ va = adev->base +
+aie_cal_regoff(adev, loc,
+ AIE_SHIMPL_CLKCNTR_REGOFF);
+ val = ioread32(va);
+
+ /*
+* check if the clock buffer and the next clock
+* tile is set, if one of them is not set, the
+* tiles of the column are clock gated.
+*/
+ if (!(val & AIE_SHIMPL_CLKCNTR_COLBUF_MASK) ||
+ !(val & AIE_SHIMPL_CLKCNTR_NEXTCLK_MASK))
+ break;
+
+ /* Set
[PATCH 4/9] misc: xilinx-ai-engine: expose AI engine tile memories to userspace
There is no concern to have userspace to directly access AI engine
program and data memories. It will be much faster to directly copy
data to and from these memories from userspace.
We choose to use DMA buf for the data and program memory because of the
DMA buf features. DMA buf can share the DMA memory between applications
and different devices, which can benefit on how to share data with AI
engine device in future.
There is one DMA buf per type of memory in an AI engine partition. e.g.
There is one DMA buf for all the tile core program memories in an AI
engine partition. There is another DMA buf for all the tile data
memories in an AI engine partition.
Signed-off-by: Wendy Liang
Reviewed-by: Hyun Kwon
---
drivers/misc/xilinx-ai-engine/Makefile | 1 +
drivers/misc/xilinx-ai-engine/ai-engine-aie.c | 36 +++
drivers/misc/xilinx-ai-engine/ai-engine-internal.h | 30 +++
drivers/misc/xilinx-ai-engine/ai-engine-mem.c | 274 +
drivers/misc/xilinx-ai-engine/ai-engine-part.c | 47
drivers/misc/xilinx-ai-engine/ai-engine-reset.c| 38 +++
include/uapi/linux/xlnx-ai-engine.h| 49
7 files changed, 475 insertions(+)
create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-mem.c
diff --git a/drivers/misc/xilinx-ai-engine/Makefile
b/drivers/misc/xilinx-ai-engine/Makefile
index 39bec61..2dbed42 100644
--- a/drivers/misc/xilinx-ai-engine/Makefile
+++ b/drivers/misc/xilinx-ai-engine/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_XILINX_AIE)+= xilinx-aie.o
xilinx-aie-$(CONFIG_XILINX_AIE) := ai-engine-aie.o \
ai-engine-dev.o \
+ ai-engine-mem.o \
ai-engine-part.o \
ai-engine-res.o \
ai-engine-reset.o
diff --git a/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
b/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
index 36127f0..7fce2f00 100644
--- a/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
+++ b/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
@@ -12,10 +12,14 @@
#include "ai-engine-internal.h"
+#define KBYTES(n) ((n) * 1024)
+
#define AIE_ARRAY_SHIFT30U
#define AIE_COL_SHIFT 23U
#define AIE_ROW_SHIFT 18U
+#define NUM_MEMS_PER_TILE 2U
+
/*
* Registers offsets
*/
@@ -114,6 +118,37 @@ static u32 aie_get_tile_type(struct aie_location *loc)
return AIE_TILE_TYPE_SHIMNOC;
}
+static unsigned int aie_get_mem_info(struct aie_range *range,
+struct aie_part_mem *pmem)
+{
+ unsigned int i;
+
+ if (range->start.row + range->size.row <= 1) {
+ /* SHIM row only, no memories in this range */
+ return 0;
+ }
+ if (!pmem)
+ return NUM_MEMS_PER_TILE;
+
+ for (i = 0; i < NUM_MEMS_PER_TILE; i++) {
+ struct aie_mem *mem = [i].mem;
+
+ memcpy(>range, range, sizeof(*range));
+ if (!mem->range.start.row) {
+ mem->range.start.row = 1;
+ mem->range.size.row--;
+ }
+ }
+ /* Setup tile data memory information */
+ pmem[0].mem.offset = 0;
+ pmem[0].mem.size = KBYTES(32);
+ /* Setup program memory information */
+ pmem[1].mem.offset = 0x2;
+ pmem[1].mem.size = KBYTES(16);
+
+ return NUM_MEMS_PER_TILE;
+}
+
/**
* aie_set_shim_reset() - Set AI engine SHIM reset
* @adev: AI engine device
@@ -170,6 +205,7 @@ static int aie_reset_shim(struct aie_device *adev, struct
aie_range *range)
static const struct aie_tile_operations aie_ops = {
.get_tile_type = aie_get_tile_type,
+ .get_mem_info = aie_get_mem_info,
.reset_shim = aie_reset_shim,
};
diff --git a/drivers/misc/xilinx-ai-engine/ai-engine-internal.h
b/drivers/misc/xilinx-ai-engine/ai-engine-internal.h
index 2acd34f..e84610b 100644
--- a/drivers/misc/xilinx-ai-engine/ai-engine-internal.h
+++ b/drivers/misc/xilinx-ai-engine/ai-engine-internal.h
@@ -12,6 +12,8 @@
#include
#include
#include
+#include
+#include
#include
#include
#include
@@ -67,8 +69,30 @@ struct aie_device;
struct aie_partition;
/**
+ * struct aie_part_mem - AI engine partition memory information structure
+ * @apart: AI engine partition
+ * @dbuf: dmabuf pointer associated with the memory
+ * @mem: memory information of a type of memory
+ * @size: size of the total memories in the partition
+ *
+ * This structure is to keep the information of a type of memory in a
+ * partition. The memory information will be stored in @mem property.
+ * The following information will be keep:
+ * * memory start address offset within a tile
+ * * memory size
+ * * what tiles contain this type of memory
+ */
+struct aie_part_mem {
+ struct aie_partition *apart;
+ struct dma_buf
[PATCH 8/9] firmware: xilinx: Add IOCTL support for AIE ISR Clear
From: Izhar Ameer Shaikh
Latching of AIE NPI Interrupts is present in Versal ES1 Silicon Rev,
however it has been removed from ES2 rev.
As a result on ES1, in order to use the interrupt, a client needs to
request PMC to clear/ack the interrupt.
Provide an EEMI IOCTL to serve the same purpose. Note that, this will
only be applicable for ES1 rev. For ES2 and other non-silicon platforms,
this call will essentially be a NOP in the firmware.
Signed-off-by: Izhar Ameer Shaikh
Signed-off-by: Wendy Liang
---
drivers/firmware/xilinx/zynqmp.c | 14 ++
include/linux/firmware/xlnx-zynqmp.h | 8
2 files changed, 22 insertions(+)
diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
index efb8a66..7a0c6a3 100644
--- a/drivers/firmware/xilinx/zynqmp.c
+++ b/drivers/firmware/xilinx/zynqmp.c
@@ -702,6 +702,20 @@ int zynqmp_pm_set_boot_health_status(u32 value)
}
/**
+ * zynqmp_pm_clear_aie_npi_isr - Clear AI engine NPI interrupt status register
+ * @node: AI engine node id
+ * @irq_mask: Mask of AI engine NPI interrupt bit to clear
+ *
+ * Return: Returns status, either success or error+reason
+ */
+int zynqmp_pm_clear_aie_npi_isr(u32 node, u32 irq_mask)
+{
+ return zynqmp_pm_invoke_fn(PM_IOCTL, node, IOCTL_AIE_ISR_CLEAR,
+ irq_mask, 0, NULL);
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_clear_aie_npi_isr);
+
+/**
* zynqmp_pm_reset_assert - Request setting of reset (1 - assert, 0 - release)
* @reset: Reset to be configured
* @assert_flag: Flag stating should reset be asserted (1) or
diff --git a/include/linux/firmware/xlnx-zynqmp.h
b/include/linux/firmware/xlnx-zynqmp.h
index 5968df8..b929d57 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -116,6 +116,8 @@ enum pm_ioctl_id {
IOCTL_READ_PGGS = 15,
/* Set healthy bit value */
IOCTL_SET_BOOT_HEALTH_STATUS = 17,
+ /* AI engine NPI ISR clear */
+ IOCTL_AIE_ISR_CLEAR = 24,
};
enum pm_query_id {
@@ -357,6 +359,7 @@ int zynqmp_pm_write_pggs(u32 index, u32 value);
int zynqmp_pm_read_pggs(u32 index, u32 *value);
int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype);
int zynqmp_pm_set_boot_health_status(u32 value);
+int zynqmp_pm_clear_aie_npi_isr(u32 node, u32 irq_mask);
#else
static inline struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void)
{
@@ -507,6 +510,11 @@ static inline int zynqmp_pm_set_boot_health_status(u32
value)
{
return -ENODEV;
}
+
+static int zynqmp_pm_clear_aie_npi_isr(u32 node, u32 irq_mask)
+{
+ return -ENODEV;
+}
#endif
#endif /* __FIRMWARE_ZYNQMP_H__ */
--
2.7.4
[PATCH 5/9] misc: xilinx-ai-engine: add setting shim dma bd operation
Add operation to set SHIM DMA buffer descriptor.
The following operations are added to set the buffer descriptors:
* attach DMA buffer which enables AI engine device to access the DMA
buffer memory
* detach DMA buffer which disables AI engine device to access the DMA
buffer memory
* set DMA buffer descriptor, which takes buffer descriptor contents
pointer, the dmabuf fd, and the offset to the start of dmabuf as
as argument. It validates the dmabuf and the offset and size of the
buffer. And then it calculates the DMA address of the buffer and set
the buffer descriptor content to the hardware DMA buffer descriptor.
The main logic to control what's go into the buffer descriptor and which
buffer descriptor to use is in the userspace AI engine library.
Signed-off-by: Wendy Liang
Reviewed-by: Hyun Kwon
---
drivers/misc/xilinx-ai-engine/Makefile | 1 +
drivers/misc/xilinx-ai-engine/ai-engine-aie.c | 19 +
drivers/misc/xilinx-ai-engine/ai-engine-dma.c | 481 +
drivers/misc/xilinx-ai-engine/ai-engine-internal.h | 45 ++
drivers/misc/xilinx-ai-engine/ai-engine-part.c | 17 +
include/uapi/linux/xlnx-ai-engine.h| 43 ++
6 files changed, 606 insertions(+)
create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-dma.c
diff --git a/drivers/misc/xilinx-ai-engine/Makefile
b/drivers/misc/xilinx-ai-engine/Makefile
index 2dbed42..1b743fa 100644
--- a/drivers/misc/xilinx-ai-engine/Makefile
+++ b/drivers/misc/xilinx-ai-engine/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_XILINX_AIE)+= xilinx-aie.o
xilinx-aie-$(CONFIG_XILINX_AIE) := ai-engine-aie.o \
ai-engine-dev.o \
+ ai-engine-dma.o \
ai-engine-mem.o \
ai-engine-part.o \
ai-engine-res.o \
diff --git a/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
b/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
index 7fce2f00..19c262d 100644
--- a/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
+++ b/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
@@ -107,6 +107,24 @@ static const struct aie_single_reg_field aie_col_clkbuf = {
.regoff = AIE_SHIMPL_CLKCNTR_REGOFF,
};
+static const struct aie_dma_attr aie_shimdma = {
+ .laddr = {
+ .mask = 0xU,
+ .regoff = 0U,
+ },
+ .haddr = {
+ .mask = 0xU,
+ .regoff = 0x8U,
+ },
+ .buflen = {
+ .mask = 0xU,
+ .regoff = 0x4U,
+ },
+ .bd_regoff = 0x0001d000U,
+ .num_bds = 16,
+ .bd_len = 0x14U,
+};
+
static u32 aie_get_tile_type(struct aie_location *loc)
{
if (loc->row)
@@ -232,6 +250,7 @@ int aie_device_init(struct aie_device *adev)
adev->kernel_regs = aie_kernel_regs;
adev->col_rst = _col_rst;
adev->col_clkbuf = _col_clkbuf;
+ adev->shim_dma = _shimdma;
/* Get the columns resource */
/* Get number of columns from AI engine memory resource */
diff --git a/drivers/misc/xilinx-ai-engine/ai-engine-dma.c
b/drivers/misc/xilinx-ai-engine/ai-engine-dma.c
new file mode 100644
index 000..007bec4
--- /dev/null
+++ b/drivers/misc/xilinx-ai-engine/ai-engine-dma.c
@@ -0,0 +1,481 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx AI Engine driver DMA implementation
+ *
+ * Copyright (C) 2020 Xilinx, Inc.
+ */
+
+#include "ai-engine-internal.h"
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/**
+ * struct aie_dmabuf - AI engine dmabuf information
+ * @attach: dmabuf attachment pointer
+ * @sgt: scatter/gather table
+ * @refs: refcount of the attached aie_dmabuf
+ * @node: list node
+ */
+struct aie_dmabuf {
+ struct dma_buf_attachment *attach;
+ struct sg_table *sgt;
+ refcount_t refs;
+ struct list_head node;
+};
+
+/**
+ * aie_part_find_dmabuf() - find a attached dmabuf
+ * @apart: AI engine partition
+ * @dmabuf: pointer to dmabuf
+ * @return: pointer to AI engine dmabuf struct of the found dmabuf, if dmabuf
+ * is not found, returns NULL.
+ *
+ * This function scans all the attached dmabufs to see the input dmabuf is
+ * in the list. if it is attached, return the corresponding struct aie_dmabuf
+ * pointer.
+ */
+static struct aie_dmabuf *
+aie_part_find_dmabuf(struct aie_partition *apart, struct dma_buf *dmabuf)
+{
+ struct aie_dmabuf *adbuf;
+
+ list_for_each_entry(adbuf, >dbufs, node) {
+ if (dmabuf == adbuf->attach->dmabuf)
+ return adbuf;
+ }
+
+ return NULL;
+}
+
+/**
+ * aie_part_get_dmabuf_da_from_off() - get DMA address from offset to a dmabuf
+ * @apart: AI engine partition
+ * @dmabuf_fd: dmabuf file descriptor
+ * @off: offset to the start of a dmabuf
+ * @len: memory length
+ * @return: dma addres
[PATCH 7/9] misc: xilinx-ai-engine: Add support to request device management services
From: Nishad Saraf
Platform management services like device control, resets, power
management, etc. are provided by Platform, Loader and Manager(PLM)
through firmware driver APIs. For requesting some of these services,
this change reads AI Engine platform management node ID from DT node.
Some other features like clearing interrupts in the NoC interconnect
might only be valid for particular silicon revisions. For supporting
such silicon specific features, AI Engine driver will query and store
this information in device instance. While at it, this change makes
EEMI operations accessible to all the other source files in the
driver.
Signed-off-by: Nishad Saraf
Signed-off-by: Wendy Liang
---
drivers/misc/xilinx-ai-engine/ai-engine-dev.c | 25 +-
drivers/misc/xilinx-ai-engine/ai-engine-internal.h | 6 ++
2 files changed, 30 insertions(+), 1 deletion(-)
diff --git a/drivers/misc/xilinx-ai-engine/ai-engine-dev.c
b/drivers/misc/xilinx-ai-engine/ai-engine-dev.c
index 7e69ff4..78eae90 100644
--- a/drivers/misc/xilinx-ai-engine/ai-engine-dev.c
+++ b/drivers/misc/xilinx-ai-engine/ai-engine-dev.c
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -25,7 +26,8 @@
#include "ai-engine-internal.h"
-#define AIE_DEV_MAX(MINORMASK + 1)
+#define AIE_DEV_MAX(MINORMASK + 1)
+#define VERSAL_SILICON_REV_MASKGENMASK(31, 28)
static dev_t aie_major;
struct class *aie_class;
@@ -318,6 +320,7 @@ static int xilinx_ai_engine_probe(struct platform_device
*pdev)
{
struct aie_device *adev;
struct device *dev;
+ u32 idcode, version, pm_reg[2];
int ret;
adev = devm_kzalloc(>dev, sizeof(*adev), GFP_KERNEL);
@@ -345,6 +348,26 @@ static int xilinx_ai_engine_probe(struct platform_device
*pdev)
return ret;
}
+ /*
+* AI Engine platform management node ID is required for requesting
+* services from firmware driver.
+*/
+ ret = of_property_read_u32_array(pdev->dev.of_node, "power-domains",
+pm_reg, ARRAY_SIZE(pm_reg));
+ if (ret < 0) {
+ dev_err(>dev,
+ "Failed to read power management information\n");
+ return ret;
+ }
+ adev->pm_node_id = pm_reg[1];
+
+ ret = zynqmp_pm_get_chipid(, );
+ if (ret < 0) {
+ dev_err(>dev, "Failed to get chip ID\n");
+ return ret;
+ }
+ adev->version = FIELD_GET(VERSAL_SILICON_REV_MASK, idcode);
+
dev = >dev;
device_initialize(dev);
dev->class = aie_class;
diff --git a/drivers/misc/xilinx-ai-engine/ai-engine-internal.h
b/drivers/misc/xilinx-ai-engine/ai-engine-internal.h
index 131d22a..b21b7025 100644
--- a/drivers/misc/xilinx-ai-engine/ai-engine-internal.h
+++ b/drivers/misc/xilinx-ai-engine/ai-engine-internal.h
@@ -41,6 +41,10 @@
#define AIE_REGS_ATTR_PERM_MASKGENMASK(15, \
AIE_REGS_ATTR_PERM_SHIFT)
+/* Silicon Engineering Sample(ES) revision ID */
+#define VERSAL_ES1_REV_ID 0x0
+#define VERSAL_ES2_REV_ID 0x1
+
/**
* struct aie_tile_regs - contiguous range of AI engine register
* within an AI engine tile
@@ -173,6 +177,7 @@ struct aie_resource {
* while columns are occupied by partitions.
* @num_kernel_regs: number of kernel only registers range
* @version: AI engine device version
+ * @pm_node_id: AI Engine platform management node ID
*/
struct aie_device {
struct list_head partitions;
@@ -193,6 +198,7 @@ struct aie_device {
u32 row_shift;
u32 num_kernel_regs;
int version;
+ u32 pm_node_id;
};
/**
--
2.7.4
[PATCH 1/9] dt-binding: soc: xilinx: ai-engine: Add AI engine binding
Xilinx AI engine array can be partitioned statically for different
applications. In the device tree, there will be device node for the AI
engine device, and device nodes for the statically configured AI engine
partitions. Each of the statically configured partition has a partition
ID in the system.
Signed-off-by: Wendy Liang
---
.../bindings/soc/xilinx/xlnx,ai-engine.yaml| 119 +
1 file changed, 119 insertions(+)
create mode 100644
Documentation/devicetree/bindings/soc/xilinx/xlnx,ai-engine.yaml
diff --git a/Documentation/devicetree/bindings/soc/xilinx/xlnx,ai-engine.yaml
b/Documentation/devicetree/bindings/soc/xilinx/xlnx,ai-engine.yaml
new file mode 100644
index 000..67e64f5
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/xilinx/xlnx,ai-engine.yaml
@@ -0,0 +1,119 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/xilinx/xlnx,ai-engine.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx AI Engine
+
+maintainers:
+ - Wendy Liang
+
+description: |+
+ The Xilinx AI Engine is a tile processor with many cores (up to 400) that
+ can run in parallel. The data routing between cores is configured through
+ internal switches, and shim tiles interface with external interconnect, such
+ as memory or PL.
+
+properties:
+ compatible:
+const: xlnx,ai-engine-v1.0
+
+ reg:
+description: |
+ Physical base address and length of the device registers.
+ The AI engine address space assigned to Linux is defined by Xilinx
+ platform design tool.
+
+ '#address-cells':
+enum: [2]
+description: |
+ size of cell to describe AI engine range of tiles address.
+ It is the location of the starting tile of the range.
+ As the AI engine tiles are 2D array, the location of a tile
+ is presented as (column, row), the address cell is 2.
+
+ '#size-cells':
+enum: [2]
+description: |
+ size of cell to describe AI engine range of tiles size.
+ As the AI engine tiles are 2D array, the size cell is 2.
+
+ interrupts:
+maxItems: 3
+
+ interrupt-names:
+description: |
+ Should be "interrupt1", "interrupt2" or "interrupt3".
+
+required:
+ - compatible
+ - reg
+ - '#address-cells'
+ - '#size-cells'
+ - power-domains
+ - interrupt-parent
+ - interrupts
+ - interrupt-names
+
+patternProperties:
+ "^partition[0-9]@[0-9]+$":
+type: object
+description: |
+ AI engine partition which is a group of column based tiles of the AI
+ engine device. Each AI engine partition is isolated from the other
+ AI engine partitions. An AI engine partition is defined by Xilinx
+ platform design tools. Each partition has a SHIM row and core tiles rows.
+ A SHIM row contains SHIM tiles which are the interface to external
+ components. AXI master can access AI engine registers, push data to and
+ fetch data from AI engine through the SHIM tiles. Core tiles are the
+ compute tiles.
+
+properties:
+ reg:
+description: |
+ It describes the group of tiles of the AI engine partition. It needs
+ to include the SHIM row. The format is defined by the parent AI
engine
+ device node's '#address-cells' and '#size-cells' properties. e.g. a
v1
+ AI engine device has 2D tiles array, the first row is SHIM row. A
+ partition which has 50 columns and 8 rows of core tiles and 1 row of
+ SHIM tiles will be presented as <0 0 50 9>.
+
+ label:
+maxItems: 1
+
+ xlnx,partition-id:
+$ref: /schemas/types.yaml#/definitions/uint32
+description: |
+ AI engine partition ID, which is defined by Xilinx platform design
+ tool to identify the AI engine partition in the system.
+
+required:
+ - reg
+ - xlnx,partition-id
+
+examples:
+ - |
+bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ ai_engine: ai-engine@200 {
+compatible = "xlnx,ai-engine-v1.0";
+reg = <0x200 0x0 0x1 0x0>;
+#address-cells = <2>;
+#size-cells = <2>;
+power-domains = <_firmware 0x18224072>;
+interrupt-parent = <>;
+interrupts = <0x0 0x94 0x4>,
+ <0x0 0x95 0x4>,
+ <0x0 0x96 0x4>;
+interrupt-names = "interrupt1", "interrupt2", "interrupt3";
+
+aie_partition0: aie-partition@0 {
+/* 50 columns and 8 core tile rows + 1 SHIM row */
+reg = <0 0 50 9>;
+xlnx,partition-id = <1>;
+};
+ };
+};
--
2.7.4
[PATCH 3/9] misc: xilinx-ai-engine: Implement AI engine cleanup sequence
When AI engine partition is released, that is if no one is using the AI
engine partition, by default, it will cleanup the partition by doing the
following:
* reset the columns
* reset the SHIMs
* clear data and program memory
* gate all the tiles
If user doesn't want the partition is reset when the partition is
released, user can set the control flag to indicate not to reset the
partition when the user requests the partition.
If partition the not to reset partition control flag is set, it will
not execute the above cleanup sequence when the partition is released.
Signed-off-by: Wendy Liang
Reviewed-by: Hyun Kwon
---
drivers/misc/xilinx-ai-engine/Makefile | 3 +-
drivers/misc/xilinx-ai-engine/ai-engine-aie.c | 92
drivers/misc/xilinx-ai-engine/ai-engine-dev.c | 2 +
drivers/misc/xilinx-ai-engine/ai-engine-internal.h | 34 ++
drivers/misc/xilinx-ai-engine/ai-engine-part.c | 7 +-
drivers/misc/xilinx-ai-engine/ai-engine-reset.c| 121 +
include/uapi/linux/xlnx-ai-engine.h| 6 +
7 files changed, 259 insertions(+), 6 deletions(-)
create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-reset.c
diff --git a/drivers/misc/xilinx-ai-engine/Makefile
b/drivers/misc/xilinx-ai-engine/Makefile
index 7827a0a..39bec61 100644
--- a/drivers/misc/xilinx-ai-engine/Makefile
+++ b/drivers/misc/xilinx-ai-engine/Makefile
@@ -8,4 +8,5 @@ obj-$(CONFIG_XILINX_AIE)+= xilinx-aie.o
xilinx-aie-$(CONFIG_XILINX_AIE) := ai-engine-aie.o \
ai-engine-dev.o \
ai-engine-part.o \
- ai-engine-res.o
+ ai-engine-res.o \
+ ai-engine-reset.o
diff --git a/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
b/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
index 319260f..36127f0 100644
--- a/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
+++ b/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
@@ -5,6 +5,9 @@
* Copyright (C) 2020 Xilinx, Inc.
*/
+#include
+#include
+#include
#include
#include "ai-engine-internal.h"
@@ -24,9 +27,25 @@
#define AIE_SHIMPL_L1INTR_MASK_A_REGOFF0x00035000U
#define AIE_SHIMPL_L1INTR_BLOCK_NORTH_B_REGOFF 0x00035050U
#define AIE_SHIMPL_CLKCNTR_REGOFF 0x00036040U
+#define AIE_SHIMPL_COLRESET_REGOFF 0x00036048U
#define AIE_SHIMPL_RESET_REGOFF0x0003604cU
#define AIE_TILE_CORE_CLKCNTR_REGOFF 0x00036040U
+/*
+ * Register masks
+ */
+#define AIE_SHIMPL_SHIMRST_MASK0x1U
+#define AIE_SHIMPL_COLRST_MASK 0x1U
+#define AIE_SHIMPL_CLKCNTR_COLBUF_MASK 0x1U
+
+/*
+ * AI engine SHIM reset ID.
+ * TODO: it should follow the Linux reset framework. The ID should be in the
+ * device tree. However, as versal resets is not ready, we hardcode it in the
+ * driver.
+ */
+#define VERSAL_PM_RST_AIE_SHIM_ID 0xc10405fU
+
static const struct aie_tile_regs aie_kernel_regs[] = {
/* SHIM AXI MM Config */
{.attribute = AIE_TILE_TYPE_SHIMNOC << AIE_REGS_ATTR_TILE_TYPE_SHIFT,
@@ -49,6 +68,12 @@ static const struct aie_tile_regs aie_kernel_regs[] = {
.soff = AIE_SHIMPL_L1INTR_MASK_A_REGOFF,
.eoff = AIE_SHIMPL_L1INTR_BLOCK_NORTH_B_REGOFF,
},
+ /* SHIM column reset */
+ {.attribute = (AIE_TILE_TYPE_SHIMPL | AIE_TILE_TYPE_SHIMNOC) <<
+ AIE_REGS_ATTR_TILE_TYPE_SHIFT,
+.soff = AIE_SHIMPL_COLRESET_REGOFF,
+.eoff = AIE_SHIMPL_COLRESET_REGOFF,
+ },
/* SHIM reset Enable */
{.attribute = (AIE_TILE_TYPE_SHIMPL | AIE_TILE_TYPE_SHIMNOC) <<
AIE_REGS_ATTR_TILE_TYPE_SHIFT,
@@ -68,6 +93,16 @@ static const struct aie_tile_regs aie_kernel_regs[] = {
},
};
+static const struct aie_single_reg_field aie_col_rst = {
+ .mask = AIE_SHIMPL_COLRST_MASK,
+ .regoff = AIE_SHIMPL_COLRESET_REGOFF,
+};
+
+static const struct aie_single_reg_field aie_col_clkbuf = {
+ .mask = AIE_SHIMPL_CLKCNTR_COLBUF_MASK,
+ .regoff = AIE_SHIMPL_CLKCNTR_REGOFF,
+};
+
static u32 aie_get_tile_type(struct aie_location *loc)
{
if (loc->row)
@@ -79,8 +114,63 @@ static u32 aie_get_tile_type(struct aie_location *loc)
return AIE_TILE_TYPE_SHIMNOC;
}
+/**
+ * aie_set_shim_reset() - Set AI engine SHIM reset
+ * @adev: AI engine device
+ * @range: range of AI engine tiles
+ * @assert: true to set reset, false to unset reset
+ */
+static void aie_set_shim_reset(struct aie_device *adev,
+ struct aie_range *range, bool assert)
+{
+ u32 c;
+ u32 val;
+ struct aie_location loc;
+
+ val = FIELD_PREP(AIE_SHIMPL_SHIMRST_MASK, (assert ? 1 : 0));
+ loc.row = 0;
+ for (c = range->start.col; c < range->sta
[PATCH 0/9] Xilinx AI engine kernel driver
AI engine is the acceleration engine provided by Xilinx. These engines provide high compute density for vector-based algorithms, and flexible custom compute and data movement. It has core tiles for compute and shim tiles to interface the FPGA fabric. You can check the AI engine architecture document for more hardware details: https://www.xilinx.com/support/documentation/architecture-manuals/am009-versal-ai-engine.pdf This patch series adds a Linux kernel driver to manage the Xilinx AI engine array device and AI engine partitions (groups of AI engine tiles dedicated to an application). Izhar Ameer Shaikh (1): firmware: xilinx: Add IOCTL support for AIE ISR Clear Nishad Saraf (2): misc: xilinx-ai-engine: Add support to request device management services misc: xilinx-ai-engine: Add support for servicing error interrupts Wendy Liang (6): dt-binding: soc: xilinx: ai-engine: Add AI engine binding misc: Add Xilinx AI engine device driver misc: xilinx-ai-engine: Implement AI engine cleanup sequence misc: xilinx-ai-engine: expose AI engine tile memories to userspace misc: xilinx-ai-engine: add setting shim dma bd operation misc: xilinx-ai-engine: add request and release tiles .../bindings/soc/xilinx/xlnx,ai-engine.yaml| 119 MAINTAINERS| 8 + drivers/firmware/xilinx/zynqmp.c | 14 + drivers/misc/Kconfig | 12 + drivers/misc/Makefile | 1 + drivers/misc/xilinx-ai-engine/Makefile | 16 + drivers/misc/xilinx-ai-engine/ai-engine-aie.c | 608 +++ drivers/misc/xilinx-ai-engine/ai-engine-clock.c| 244 drivers/misc/xilinx-ai-engine/ai-engine-dev.c | 492 +++ drivers/misc/xilinx-ai-engine/ai-engine-dma.c | 481 +++ drivers/misc/xilinx-ai-engine/ai-engine-internal.h | 519 .../misc/xilinx-ai-engine/ai-engine-interrupt.c| 661 + drivers/misc/xilinx-ai-engine/ai-engine-mem.c | 274 + drivers/misc/xilinx-ai-engine/ai-engine-part.c | 635 drivers/misc/xilinx-ai-engine/ai-engine-res.c | 219 +++ drivers/misc/xilinx-ai-engine/ai-engine-reset.c| 159 + include/linux/firmware/xlnx-zynqmp.h | 8 + include/uapi/linux/xlnx-ai-engine.h| 236 18 files changed, 4706 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/xilinx/xlnx,ai-engine.yaml create mode 100644 drivers/misc/xilinx-ai-engine/Makefile create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-aie.c create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-clock.c create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-dev.c create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-dma.c create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-internal.h create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-interrupt.c create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-mem.c create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-part.c create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-res.c create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-reset.c create mode 100644 include/uapi/linux/xlnx-ai-engine.h -- 2.7.4
Re: RE: RE: [PATCH v14 5/5] remoteproc: Add initial zynqmp R5 remoteproc driver
Hi Ben On Sun, Sep 20, 2020 at 4:16 PM Ben Levinsky wrote: > > Hi All, > > > -Original Message- > > From: Wendy Liang > > Sent: Friday, September 18, 2020 6:53 PM > > To: Michael Auchter > > Cc: Ben Levinsky ; punit1.agra...@toshiba.co.jp; > > devicet...@vger.kernel.org; linux-remotep...@vger.kernel.org; linux- > > ker...@vger.kernel.org; linux-arm-ker...@lists.infradead.org > > Subject: Re: RE: RE: [PATCH v14 5/5] remoteproc: Add initial zynqmp R5 > > remoteproc driver > > > > HI Michael, Ben, Punit, > > > > On Fri, Sep 18, 2020 at 12:08 PM Michael Auchter > > wrote: > > > > > > Hey Ben, > > > > > > On Fri, Sep 18, 2020 at 06:01:19PM +, Ben Levinsky wrote: > > > > Hi Michael, Punit, > > > > > > > > > -Original Message- > > > > > From: Michael Auchter > > > > > Sent: Friday, September 18, 2020 9:07 AM > > > > > To: Ben Levinsky > > > > > Cc: devicet...@vger.kernel.org; linux-remotep...@vger.kernel.org; > > linux- > > > > > ker...@vger.kernel.org; linux-arm-ker...@lists.infradead.org > > > > > Subject: Re: RE: [PATCH v14 5/5] remoteproc: Add initial zynqmp R5 > > > > > remoteproc driver > > > > > > > > > > On Thu, Sep 17, 2020 at 10:50:42PM +, Ben Levinsky wrote: > > > > > > In addition to device tree, is there particular linker script you > > > > > > use > > > > > > for your R5 application? For example with OCM? As presently this > > > > > > driver only has DDR and TCM as supported regions to load into > > > > > > > > > > The firmware is being loaded to TCM. > > > > > > > > > > I'm able to use this driver to load and run my firmware on both R5 > > > > > cores, but only after I change the incorrect: > > > > > > > > > > rpu_mode = lockstep_mode > > > > > > > > > > assignment to: > > > > > > > > > > rpu_mode = lockstep_mode ? PM_RPU_MODE_LOCKSTEP > > > > > : PM_RPU_MODE_SPLIT; > > > > There was a point raised by Punit that as "it is possible to set R5 to > > > > operatore in split or lock-step mode dynamically" which is true and > > > > can be done via sysfs and the Xilinx firmware kernel code. > > > > > > I'm not familiar with this, and don't see an obvious way to do this > > > (from looking at drivers/firmware/xilinx/). Can you point me to this > > > code? > > > > [Ben Levinsky] A way to do this, though it seems later comments show it is > not an implementation to pursue, is use the RPU configuration API and present > it via sysfs interface a la > https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842232/Zynq+UltraScale+MPSoC+Power+Management+-+Linux+Kernel#ZynqUltraScale%EF%BC%8BMPSoCPowerManagement-LinuxKernel-EnableClock > > > > A suggestion that might clean up the driver so that the whole > > > > rpu_mode, tcm_mode configuration can be simplified and pulled out of > > > > the driver: > > > > - as Punit suggested, remove the lockstep-mode property > > > > - the zynqmp_remoteproc_r5 driver ONLY loads firmware and does > > start/stop. > > > > - the zynqmp_remoteproc_r5 driver does not configure and memory > > regions or the RPU. Let the Xilinx firmware sysfs interface handle this. > > > > > > I don't think this is a good approach. > [Ben Levinsky] ok, noted. Can keep the configuration but still as wendy said > just have lockstep property to denote lockstep mode in RPU and otherwise be > split, for simplicity? > > [Wendy] The TCMs are presented differently in the system depending on > > if RPU is in > > lockstep or split mode. > > > > Not sure if it is allowed to list TCMs registers properties for both > > split mode and lockstep > > mode in the same device node. > > > > Even though, driver can have this information in the code, but I feel > > the device tree is a > > better place for this information. > > And also for predefined shared memories, you will need to know the RPU > > op mode ahead, > > so that you can specify which shared memories belong to which RPU. > > > > To dynamic setup the RPU mode, besides sysfs, setup, if remoteproc can > > support > > device tree overlay, the RPUs can be described with dtbo and loaded at > > runtime. > > &
Re: RE: RE: [PATCH v14 5/5] remoteproc: Add initial zynqmp R5 remoteproc driver
Hi Ben, On Sun, Sep 20, 2020 at 4:16 PM Ben Levinsky wrote: > > Hi All, > > > -Original Message- > > From: Wendy Liang > > Sent: Friday, September 18, 2020 6:53 PM > > To: Michael Auchter > > Cc: Ben Levinsky ; punit1.agra...@toshiba.co.jp; > > devicet...@vger.kernel.org; linux-remotep...@vger.kernel.org; linux- > > ker...@vger.kernel.org; linux-arm-ker...@lists.infradead.org > > Subject: Re: RE: RE: [PATCH v14 5/5] remoteproc: Add initial zynqmp R5 > > remoteproc driver > > > > HI Michael, Ben, Punit, > > > > On Fri, Sep 18, 2020 at 12:08 PM Michael Auchter > > wrote: > > > > > > Hey Ben, > > > > > > On Fri, Sep 18, 2020 at 06:01:19PM +, Ben Levinsky wrote: > > > > Hi Michael, Punit, > > > > > > > > > -Original Message- > > > > > From: Michael Auchter > > > > > Sent: Friday, September 18, 2020 9:07 AM > > > > > To: Ben Levinsky > > > > > Cc: devicet...@vger.kernel.org; linux-remotep...@vger.kernel.org; > > linux- > > > > > ker...@vger.kernel.org; linux-arm-ker...@lists.infradead.org > > > > > Subject: Re: RE: [PATCH v14 5/5] remoteproc: Add initial zynqmp R5 > > > > > remoteproc driver > > > > > > > > > > On Thu, Sep 17, 2020 at 10:50:42PM +, Ben Levinsky wrote: > > > > > > In addition to device tree, is there particular linker script you > > > > > > use > > > > > > for your R5 application? For example with OCM? As presently this > > > > > > driver only has DDR and TCM as supported regions to load into > > > > > > > > > > The firmware is being loaded to TCM. > > > > > > > > > > I'm able to use this driver to load and run my firmware on both R5 > > > > > cores, but only after I change the incorrect: > > > > > > > > > > rpu_mode = lockstep_mode > > > > > > > > > > assignment to: > > > > > > > > > > rpu_mode = lockstep_mode ? PM_RPU_MODE_LOCKSTEP > > > > > : PM_RPU_MODE_SPLIT; > > > > There was a point raised by Punit that as "it is possible to set R5 to > > > > operatore in split or lock-step mode dynamically" which is true and > > > > can be done via sysfs and the Xilinx firmware kernel code. > > > > > > I'm not familiar with this, and don't see an obvious way to do this > > > (from looking at drivers/firmware/xilinx/). Can you point me to this > > > code? > > > > [Ben Levinsky] A way to do this, though it seems later comments show it is > not an implementation to pursue, is use the RPU configuration API and present > it via sysfs interface a la > https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842232/Zynq+UltraScale+MPSoC+Power+Management+-+Linux+Kernel#ZynqUltraScale%EF%BC%8BMPSoCPowerManagement-LinuxKernel-EnableClock > > > > A suggestion that might clean up the driver so that the whole > > > > rpu_mode, tcm_mode configuration can be simplified and pulled out of > > > > the driver: > > > > - as Punit suggested, remove the lockstep-mode property > > > > - the zynqmp_remoteproc_r5 driver ONLY loads firmware and does > > start/stop. > > > > - the zynqmp_remoteproc_r5 driver does not configure and memory > > regions or the RPU. Let the Xilinx firmware sysfs interface handle this. > > > > > > I don't think this is a good approach. > [Ben Levinsky] ok, noted. Can keep the configuration but still as wendy said > just have lockstep property to denote lockstep mode in RPU and otherwise be > split, for simplicity? > > [Wendy] The TCMs are presented differently in the system depending on > > if RPU is in > > lockstep or split mode. > > > > Not sure if it is allowed to list TCMs registers properties for both > > split mode and lockstep > > mode in the same device node. > > > > Even though, driver can have this information in the code, but I feel > > the device tree is a > > better place for this information. > > And also for predefined shared memories, you will need to know the RPU > > op mode ahead, > > so that you can specify which shared memories belong to which RPU. > > > > To dynamic setup the RPU mode, besides sysfs, setup, if remoteproc can > > support > > device tree overlay, the RPUs can be described with dtbo and loaded at > > runtime. > > >
Re: RE: RE: [PATCH v14 5/5] remoteproc: Add initial zynqmp R5 remoteproc driver
HI Michael, Ben, Punit, On Fri, Sep 18, 2020 at 12:08 PM Michael Auchter wrote: > > Hey Ben, > > On Fri, Sep 18, 2020 at 06:01:19PM +, Ben Levinsky wrote: > > Hi Michael, Punit, > > > > > -Original Message- > > > From: Michael Auchter > > > Sent: Friday, September 18, 2020 9:07 AM > > > To: Ben Levinsky > > > Cc: devicet...@vger.kernel.org; linux-remotep...@vger.kernel.org; linux- > > > ker...@vger.kernel.org; linux-arm-ker...@lists.infradead.org > > > Subject: Re: RE: [PATCH v14 5/5] remoteproc: Add initial zynqmp R5 > > > remoteproc driver > > > > > > On Thu, Sep 17, 2020 at 10:50:42PM +, Ben Levinsky wrote: > > > > In addition to device tree, is there particular linker script you use > > > > for your R5 application? For example with OCM? As presently this > > > > driver only has DDR and TCM as supported regions to load into > > > > > > The firmware is being loaded to TCM. > > > > > > I'm able to use this driver to load and run my firmware on both R5 > > > cores, but only after I change the incorrect: > > > > > > rpu_mode = lockstep_mode > > > > > > assignment to: > > > > > > rpu_mode = lockstep_mode ? PM_RPU_MODE_LOCKSTEP > > > : PM_RPU_MODE_SPLIT; > > There was a point raised by Punit that as "it is possible to set R5 to > > operatore in split or lock-step mode dynamically" which is true and > > can be done via sysfs and the Xilinx firmware kernel code. > > I'm not familiar with this, and don't see an obvious way to do this > (from looking at drivers/firmware/xilinx/). Can you point me to this > code? > > > A suggestion that might clean up the driver so that the whole > > rpu_mode, tcm_mode configuration can be simplified and pulled out of > > the driver: > > - as Punit suggested, remove the lockstep-mode property > > - the zynqmp_remoteproc_r5 driver ONLY loads firmware and does start/stop. > > - the zynqmp_remoteproc_r5 driver does not configure and memory regions or > > the RPU. Let the Xilinx firmware sysfs interface handle this. > > I don't think this is a good approach. [Wendy] The TCMs are presented differently in the system depending on if RPU is in lockstep or split mode. Not sure if it is allowed to list TCMs registers properties for both split mode and lockstep mode in the same device node. Even though, driver can have this information in the code, but I feel the device tree is a better place for this information. And also for predefined shared memories, you will need to know the RPU op mode ahead, so that you can specify which shared memories belong to which RPU. To dynamic setup the RPU mode, besides sysfs, setup, if remoteproc can support device tree overlay, the RPUs can be described with dtbo and loaded at runtime. Just want to understand the case which needs to set RPU mode at runtime? I think testing can be one case. Best Regards, Wendy > - How will someone know to configure the RPU mode and TCM mode via sysfs? > - What happens when someone changes the RPU mode after remoteproc has > already booted some firmware on it? > - What if the kernel is the one booting the R5, not the user? > > Split vs. lockstep, IMO, needs to be specified as part of the device > tree, and this driver needs to handle configuring the RPU mode and TCM > modes appropriately. > > Split vs. lockstep already necessitates different entries in the device > tree: > - In the binding, each core references its TCMs via the > meta-memory-regions phandles, and the referenced nodes necessarily > encode this size. In split mode, each core has access to 64K of > TCMA/TCMB, while in lockstep R5 0 has access to 128K of TCMA/TCMB. So, > the "xlnx,tcm" nodes' reg entries need to differ between lockstep and > split. > - In lockstep mode, it does not make sense to have both r5@0 and r5@1 > child nodes: only r5@0 makes sense. Though, I just realized that I > think this driver will currently permit that, and register two > remoteprocs even in lockstep mode... What happens if someone tries to > load firmware on to r5_1 when they're in lockstep mode? This should > probably be prevented. > > Thanks, > Michael
[PATCH v8 2/2] dt-bindings: mailbox: Add Xilinx IPI Mailbox
Xilinx ZynqMP IPI(Inter Processor Interrupt) is a hardware block
in ZynqMP SoC used for the communication between various processor
systems.
Signed-off-by: Wendy Liang
Reviewed-by: Rob Herring
---
.../bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt | 127 +
1 file changed, 127 insertions(+)
create mode 100644
Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt
diff --git
a/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt
b/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt
new file mode 100644
index 000..4438432
--- /dev/null
+++ b/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt
@@ -0,0 +1,127 @@
+Xilinx IPI Mailbox Controller
+
+
+The Xilinx IPI(Inter Processor Interrupt) mailbox controller is to manage
+messaging between two Xilinx Zynq UltraScale+ MPSoC IPI agents. Each IPI
+agent owns registers used for notification and buffers for message.
+
+ +-+
+ | Xilinx ZynqMP IPI Controller|
+ +-+
++--+
+ATF| |
+ | |
+ | |
++--+ |
+ | |
+ | |
++--+
++--+
+| ++ ++ |
+Hardware| | IPI Agent | | IPI Buffers | |
+| | Registers | || |
+| || || |
+| ++ ++ |
+| |
+| Xilinx IPI Agent Block |
++--+
+
+
+Controller Device Node:
+===
+Required properties:
+
+IPI agent node:
+- compatible: Shall be: "xlnx,zynqmp-ipi-mailbox"
+- interrupt-parent:Phandle for the interrupt controller
+- interrupts: Interrupt information corresponding to the
+ interrupt-names property.
+- xlnx,ipi-id: local Xilinx IPI agent ID
+- #address-cells: number of address cells of internal IPI mailbox nodes
+- #size-cells: number of size cells of internal IPI mailbox nodes
+
+Internal IPI mailbox node:
+- reg: IPI buffers address ranges
+- reg-names: Names of the reg resources. It should have:
+ * local_request_region
+ - IPI request msg buffer written by local and read
+ by remote
+ * local_response_region
+ - IPI response msg buffer written by local and read
+ by remote
+ * remote_request_region
+ - IPI request msg buffer written by remote and read
+ by local
+ * remote_response_region
+ - IPI response msg buffer written by remote and read
+ by local
+- #mbox-cells: Shall be 1. It contains:
+ * tx(0) or rx(1) channel
+- xlnx,ipi-id: remote Xilinx IPI agent ID of which the mailbox is
+ connected to.
+
+Optional properties:
+
+- method: The method of accessing the IPI agent registers.
+ Permitted values are: "smc" and "hvc". Default is
+ "smc".
+
+Client Device Node:
+===
+Required properties:
+
+- mboxes: Standard property to specify a mailbox
+ (See ./mailbox.txt)
+- mbox-names: List of identifier strings for each mailbox
+ channel.
+
+Example:
+===
+ zynqmp_ipi {
+ compatible = "xlnx,zynqmp-ipi-mailbox";
+ interrupt-parent = <>;
+ interrupts = <0 29 4>;
+ xlnx,ipi-id = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ /* APU<->RPU0 IPI mailbox controller */
+ ipi_mailbox_rpu0: mailbox@ff90400 {
+ reg = <0xff990400 0x20>,
+ <0xff990420 0x20>,
+ <0xff990080 0x20>,
+ <0xff9900a0 0x20>;
+
[PATCH v8 0/2] Xilinx ZynqMP IPI Mailbox Controller Driver
Introduce mailbox controller driver for ZynqMP IPI(Inter-processor interrupt) IP core. v8: - Remove unused macros - Remove polling sending status from send_data - Remove calling receive callback from last_tx_done() - Use devm_mbox_controller_register() - Use of_get_child_count() to get the number of mailboxes. v7: - Fix sparse warning, and documentation check. - Add emply block to the end of of_device_id. v6: - dts-binding, remove compatible property from IPI subnode v5: - fix check patch warning on write a paragraph to describe the kconfig symbol. v4: - make IPI mailboxes as subnodes to the IPI agent device node to properly describe the hardware. v3: - add NULL entry to of_device_id of IPI controller v2: - change SPDX-License-Identifier license text style in .c file - replace xlnx-ipi-ids with xlnx,ipi-ids Wendy Liang (2): mailbox: ZynqMP IPI mailbox controller dt-bindings: mailbox: Add Xilinx IPI Mailbox .../bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt | 127 drivers/mailbox/Kconfig| 11 + drivers/mailbox/Makefile | 2 + drivers/mailbox/zynqmp-ipi-mailbox.c | 725 + include/linux/mailbox/zynqmp-ipi-message.h | 20 + 5 files changed, 885 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt create mode 100644 drivers/mailbox/zynqmp-ipi-mailbox.c create mode 100644 include/linux/mailbox/zynqmp-ipi-message.h -- 2.7.4
[PATCH v8 1/2] mailbox: ZynqMP IPI mailbox controller
This patch is to introduce ZynqMP IPI mailbox controller driver
to use the ZynqMP IPI block as mailboxes.
Signed-off-by: Wendy Liang
---
drivers/mailbox/Kconfig| 11 +
drivers/mailbox/Makefile | 2 +
drivers/mailbox/zynqmp-ipi-mailbox.c | 725 +
include/linux/mailbox/zynqmp-ipi-message.h | 20 +
4 files changed, 758 insertions(+)
create mode 100644 drivers/mailbox/zynqmp-ipi-mailbox.c
create mode 100644 include/linux/mailbox/zynqmp-ipi-message.h
diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig
index 3eeb12e9..d86e7a4 100644
--- a/drivers/mailbox/Kconfig
+++ b/drivers/mailbox/Kconfig
@@ -205,4 +205,15 @@ config MTK_CMDQ_MBOX
mailbox driver. The CMDQ is used to help read/write registers with
critical time limitation, such as updating display configuration
during the vblank.
+
+config ZYNQMP_IPI_MBOX
+ bool "Xilinx ZynqMP IPI Mailbox"
+ depends on ARCH_ZYNQMP && OF
+ help
+ Say yes here to add support for Xilinx IPI mailbox driver.
+ This mailbox driver is used to send notification or short message
+ between processors with Xilinx ZynqMP IPI. It will place the
+ message to the IPI buffer and will access the IPI control
+ registers to kick the other processor or enquire status.
+
endif
diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile
index c818b5d..8be3bcb 100644
--- a/drivers/mailbox/Makefile
+++ b/drivers/mailbox/Makefile
@@ -44,3 +44,5 @@ obj-$(CONFIG_TEGRA_HSP_MBOX) += tegra-hsp.o
obj-$(CONFIG_STM32_IPCC) += stm32-ipcc.o
obj-$(CONFIG_MTK_CMDQ_MBOX)+= mtk-cmdq-mailbox.o
+
+obj-$(CONFIG_ZYNQMP_IPI_MBOX) += zynqmp-ipi-mailbox.o
diff --git a/drivers/mailbox/zynqmp-ipi-mailbox.c
b/drivers/mailbox/zynqmp-ipi-mailbox.c
new file mode 100644
index 000..86887c9
--- /dev/null
+++ b/drivers/mailbox/zynqmp-ipi-mailbox.c
@@ -0,0 +1,725 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Inter Processor Interrupt(IPI) Mailbox Driver
+ *
+ * Copyright (C) 2018 Xilinx, Inc.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* IPI agent ID any */
+#define IPI_ID_ANY 0xFFUL
+
+/* indicate if ZynqMP IPI mailbox driver uses SMC calls or HVC calls */
+#define USE_SMC 0
+#define USE_HVC 1
+
+/* Default IPI SMC function IDs */
+#define SMC_IPI_MAILBOX_OPEN 0x82001000U
+#define SMC_IPI_MAILBOX_RELEASE0x82001001U
+#define SMC_IPI_MAILBOX_STATUS_ENQUIRY 0x82001002U
+#define SMC_IPI_MAILBOX_NOTIFY 0x82001003U
+#define SMC_IPI_MAILBOX_ACK0x82001004U
+#define SMC_IPI_MAILBOX_ENABLE_IRQ 0x82001005U
+#define SMC_IPI_MAILBOX_DISABLE_IRQ0x82001006U
+
+/* IPI SMC Macros */
+#define IPI_SMC_ENQUIRY_DIRQ_MASK 0x0001UL /* Flag to indicate if
+ * notification interrupt
+ * to be disabled.
+ */
+#define IPI_SMC_ACK_EIRQ_MASK 0x0001UL /* Flag to indicate if
+ * notification interrupt
+ * to be enabled.
+ */
+
+/* IPI mailbox status */
+#define IPI_MB_STATUS_IDLE 0
+#define IPI_MB_STATUS_SEND_PENDING 1
+#define IPI_MB_STATUS_RECV_PENDING 2
+
+#define IPI_MB_CHNL_TX 0 /* IPI mailbox TX channel */
+#define IPI_MB_CHNL_RX 1 /* IPI mailbox RX channel */
+
+/**
+ * struct zynqmp_ipi_mchan - Description of a Xilinx ZynqMP IPI mailbox channel
+ * @is_opened: indicate if the IPI channel is opened
+ * @req_buf: local to remote request buffer start address
+ * @resp_buf: local to remote response buffer start address
+ * @req_buf_size: request buffer size
+ * @resp_buf_size: response buffer size
+ * @rx_buf: receive buffer to pass received message to client
+ * @chan_type: channel type
+ */
+struct zynqmp_ipi_mchan {
+ int is_opened;
+ void __iomem *req_buf;
+ void __iomem *resp_buf;
+ void *rx_buf;
+ size_t req_buf_size;
+ size_t resp_buf_size;
+ unsigned int chan_type;
+};
+
+/**
+ * struct zynqmp_ipi_mbox - Description of a ZynqMP IPI mailbox
+ * platform data.
+ * @pdata: pointer to the IPI private data
+ * @dev: device pointer corresponding to the Xilinx ZynqMP
+ *IPI mailbox
+ * @remote_id:remote IPI agent ID
+ * @mbox: mailbox Controller
+ * @mchans: array for channels, tx channel and rx channel.
+ * @irq: IPI agent interrupt ID
+ */
+struct zynqmp_ipi_mbox {
+ struct zynqmp_ipi_pdata *pdata;
+ struct devic
[PATH v7 1/2] mailbox: ZynqMP IPI mailbox controller
This patch is to introduce ZynqMP IPI mailbox controller driver
to use the ZynqMP IPI block as mailboxes.
Signed-off-by: Wendy Liang
---
drivers/mailbox/Kconfig | 11 +
drivers/mailbox/Makefile | 2 +
drivers/mailbox/zynqmp-ipi-mailbox.c | 764 +++
3 files changed, 777 insertions(+)
create mode 100644 drivers/mailbox/zynqmp-ipi-mailbox.c
diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig
index 3eeb12e9..d86e7a4 100644
--- a/drivers/mailbox/Kconfig
+++ b/drivers/mailbox/Kconfig
@@ -205,4 +205,15 @@ config MTK_CMDQ_MBOX
mailbox driver. The CMDQ is used to help read/write registers with
critical time limitation, such as updating display configuration
during the vblank.
+
+config ZYNQMP_IPI_MBOX
+ bool "Xilinx ZynqMP IPI Mailbox"
+ depends on ARCH_ZYNQMP && OF
+ help
+ Say yes here to add support for Xilinx IPI mailbox driver.
+ This mailbox driver is used to send notification or short message
+ between processors with Xilinx ZynqMP IPI. It will place the
+ message to the IPI buffer and will access the IPI control
+ registers to kick the other processor or enquire status.
+
endif
diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile
index c818b5d..8be3bcb 100644
--- a/drivers/mailbox/Makefile
+++ b/drivers/mailbox/Makefile
@@ -44,3 +44,5 @@ obj-$(CONFIG_TEGRA_HSP_MBOX) += tegra-hsp.o
obj-$(CONFIG_STM32_IPCC) += stm32-ipcc.o
obj-$(CONFIG_MTK_CMDQ_MBOX)+= mtk-cmdq-mailbox.o
+
+obj-$(CONFIG_ZYNQMP_IPI_MBOX) += zynqmp-ipi-mailbox.o
diff --git a/drivers/mailbox/zynqmp-ipi-mailbox.c
b/drivers/mailbox/zynqmp-ipi-mailbox.c
new file mode 100644
index 000..bbddfd5
--- /dev/null
+++ b/drivers/mailbox/zynqmp-ipi-mailbox.c
@@ -0,0 +1,764 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Inter Processor Interrupt(IPI) Mailbox Driver
+ *
+ * Copyright (C) 2018 Xilinx, Inc.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* IPI agent ID any */
+#define IPI_ID_ANY 0xFFUL
+
+/* indicate if ZynqMP IPI mailbox driver uses SMC calls or HVC calls */
+#define USE_SMC 0
+#define USE_HVC 1
+
+/* Default IPI SMC function IDs */
+#define SMC_IPI_MAILBOX_OPEN 0x82001000U
+#define SMC_IPI_MAILBOX_RELEASE0x82001001U
+#define SMC_IPI_MAILBOX_STATUS_ENQUIRY 0x82001002U
+#define SMC_IPI_MAILBOX_NOTIFY 0x82001003U
+#define SMC_IPI_MAILBOX_ACK0x82001004U
+#define SMC_IPI_MAILBOX_ENABLE_IRQ 0x82001005U
+#define SMC_IPI_MAILBOX_DISABLE_IRQ0x82001006U
+
+/* IPI SMC Macros */
+#define IPI_SMC_OPEN_IRQ_MASK 0x0001UL /* IRQ enable bit in IPI
+ * open SMC call
+ */
+#define IPI_SMC_NOTIFY_BLOCK_MASK 0x0001UL /* Flag to indicate if
+ * IPI notification needs
+ * to be blocking.
+ */
+#define IPI_SMC_ENQUIRY_DIRQ_MASK 0x0001UL /* Flag to indicate if
+ * notification interrupt
+ * to be disabled.
+ */
+#define IPI_SMC_ACK_EIRQ_MASK 0x0001UL /* Flag to indicate if
+ * notification interrupt
+ * to be enabled.
+ */
+
+/* IPI mailbox status */
+#define IPI_MB_STATUS_IDLE 0
+#define IPI_MB_STATUS_SEND_PENDING 1
+#define IPI_MB_STATUS_RECV_PENDING 2
+
+#define IPI_MB_CHNL_TX 0 /* IPI mailbox TX channel */
+#define IPI_MB_CHNL_RX 1 /* IPI mailbox RX channel */
+
+/**
+ * struct zynqmp_ipi_mchan - Description of a Xilinx ZynqMP IPI mailbox channel
+ * @is_opened: indicate if the IPI channel is opened
+ * @req_buf: local to remote request buffer start address
+ * @resp_buf: local to remote response buffer start address
+ * @req_buf_size: request buffer size
+ * @resp_buf_size: response buffer size
+ * @rx_buf: receive buffer to pass received message to client
+ * @chan_type: channel type
+ */
+struct zynqmp_ipi_mchan {
+ int is_opened;
+ void __iomem *req_buf;
+ void __iomem *resp_buf;
+ void *rx_buf;
+ size_t req_buf_size;
+ size_t resp_buf_size;
+ unsigned int chan_type;
+};
+
+/**
+ * struct zynqmp_ipi_mbox - Description of a ZynqMP IPI mailbox
+ * platform data.
+ * @pdata: pointer to the IPI private data
+ * @dev: device pointer corresponding to
[PATH v7 2/2] dt-bindings: mailbox: Add Xilinx IPI Mailbox
Xilinx ZynqMP IPI(Inter Processor Interrupt) is a hardware block
in ZynqMP SoC used for the communication between various processor
systems.
Signed-off-by: Wendy Liang
Reviewed-by: Rob Herring
---
.../bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt | 127 +
1 file changed, 127 insertions(+)
create mode 100644
Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt
diff --git
a/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt
b/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt
new file mode 100644
index 000..4438432
--- /dev/null
+++ b/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt
@@ -0,0 +1,127 @@
+Xilinx IPI Mailbox Controller
+
+
+The Xilinx IPI(Inter Processor Interrupt) mailbox controller is to manage
+messaging between two Xilinx Zynq UltraScale+ MPSoC IPI agents. Each IPI
+agent owns registers used for notification and buffers for message.
+
+ +-+
+ | Xilinx ZynqMP IPI Controller|
+ +-+
++--+
+ATF| |
+ | |
+ | |
++--+ |
+ | |
+ | |
++--+
++--+
+| ++ ++ |
+Hardware| | IPI Agent | | IPI Buffers | |
+| | Registers | || |
+| || || |
+| ++ ++ |
+| |
+| Xilinx IPI Agent Block |
++--+
+
+
+Controller Device Node:
+===
+Required properties:
+
+IPI agent node:
+- compatible: Shall be: "xlnx,zynqmp-ipi-mailbox"
+- interrupt-parent:Phandle for the interrupt controller
+- interrupts: Interrupt information corresponding to the
+ interrupt-names property.
+- xlnx,ipi-id: local Xilinx IPI agent ID
+- #address-cells: number of address cells of internal IPI mailbox nodes
+- #size-cells: number of size cells of internal IPI mailbox nodes
+
+Internal IPI mailbox node:
+- reg: IPI buffers address ranges
+- reg-names: Names of the reg resources. It should have:
+ * local_request_region
+ - IPI request msg buffer written by local and read
+ by remote
+ * local_response_region
+ - IPI response msg buffer written by local and read
+ by remote
+ * remote_request_region
+ - IPI request msg buffer written by remote and read
+ by local
+ * remote_response_region
+ - IPI response msg buffer written by remote and read
+ by local
+- #mbox-cells: Shall be 1. It contains:
+ * tx(0) or rx(1) channel
+- xlnx,ipi-id: remote Xilinx IPI agent ID of which the mailbox is
+ connected to.
+
+Optional properties:
+
+- method: The method of accessing the IPI agent registers.
+ Permitted values are: "smc" and "hvc". Default is
+ "smc".
+
+Client Device Node:
+===
+Required properties:
+
+- mboxes: Standard property to specify a mailbox
+ (See ./mailbox.txt)
+- mbox-names: List of identifier strings for each mailbox
+ channel.
+
+Example:
+===
+ zynqmp_ipi {
+ compatible = "xlnx,zynqmp-ipi-mailbox";
+ interrupt-parent = <>;
+ interrupts = <0 29 4>;
+ xlnx,ipi-id = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ /* APU<->RPU0 IPI mailbox controller */
+ ipi_mailbox_rpu0: mailbox@ff90400 {
+ reg = <0xff990400 0x20>,
+ <0xff990420 0x20>,
+ <0xff990080 0x20>,
+ <0xff9900a0 0x20>;
+
[PATH v7 0/2] Xilinx ZynqMP IPI Mailbox Controller Driver
Introduce mailbox controller driver for ZynqMP IPI(Inter-processor interrupt) IP core. As the device tree bindings have been updated. Do not have "Reviewed-by" nor "Acked-by" in the dt-bindings commit. v7: - Fix sparse warning, and documentation check. - Add emply block to the end of of_device_id. v6: - dts-binding, remove compatible property from IPI subnode v5: - fix check patch warning on write a paragraph to describe the kconfig symbol. v4: - make IPI mailboxes as subnodes to the IPI agent device node to properly describe the hardware. v3: - add NULL entry to of_device_id of IPI controller v2: - change SPDX-License-Identifier license text style in .c file - replace xlnx-ipi-ids with xlnx,ipi-ids Wendy Liang (2): mailbox: ZynqMP IPI mailbox controller dt-bindings: mailbox: Add Xilinx IPI Mailbox .../bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt | 127 drivers/mailbox/Kconfig| 11 + drivers/mailbox/Makefile | 2 + drivers/mailbox/zynqmp-ipi-mailbox.c | 764 + 4 files changed, 904 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt create mode 100644 drivers/mailbox/zynqmp-ipi-mailbox.c -- 2.7.4
Re: [PATCH v4 12/17] remoteproc: modify vring allocation to rely on centralized carveout allocator
On Tue, Dec 4, 2018 at 11:57 AM Loic PALLARDY wrote: > > > > > -Original Message- > > From: Wendy Liang > > Sent: mardi 4 décembre 2018 19:58 > > To: Loic PALLARDY > > Cc: Suman Anna ; Bjorn Andersson > > ; Ohad Ben-Cohen ; > > linux-remotep...@vger.kernel.org; Linux Kernel Mailing List > ker...@vger.kernel.org>; Arnaud POULIQUEN ; > > Benjamin Gaignard > > Subject: Re: [PATCH v4 12/17] remoteproc: modify vring allocation to rely on > > centralized carveout allocator > > > > On Tue, Dec 4, 2018 at 10:04 AM Loic PALLARDY > > wrote: > > > > > > > > > > > > > -Original Message- > > > > From: Wendy Liang > > > > Sent: mardi 4 décembre 2018 18:57 > > > > To: Suman Anna > > > > Cc: Loic PALLARDY ; Bjorn Andersson > > > > ; Ohad Ben-Cohen ; > > > > linux-remotep...@vger.kernel.org; Linux Kernel Mailing List > > > ker...@vger.kernel.org>; Arnaud POULIQUEN > > ; > > > > Benjamin Gaignard > > > > Subject: Re: [PATCH v4 12/17] remoteproc: modify vring allocation to > > > > rely > > on > > > > centralized carveout allocator > > > > > > > > On Mon, Oct 29, 2018 at 1:19 PM Suman Anna wrote: > > > > > > > > > > Hi Loic, > > > > > > > > > > On 10/24/18 10:14 AM, Loic PALLARDY wrote: > > > > > > Hi Suman, > > > > > > > > > > > >> -Original Message- > > > > > >> From: Suman Anna > > > > > >> Sent: mercredi 24 octobre 2018 02:14 > > > > > >> To: Loic PALLARDY ; > > bjorn.anders...@linaro.org; > > > > > >> o...@wizery.com > > > > > >> Cc: linux-remotep...@vger.kernel.org; linux- > > ker...@vger.kernel.org; > > > > > >> Arnaud POULIQUEN ; > > > > > >> benjamin.gaign...@linaro.org > > > > > >> Subject: Re: [PATCH v4 12/17] remoteproc: modify vring allocation > > > > > >> to > > > > rely on > > > > > >> centralized carveout allocator > > > > > >> > > > > > >> On 7/27/18 8:14 AM, Loic Pallardy wrote: > > > > > >>> Current version of rproc_alloc_vring function supports only > > dynamic > > > > vring > > > > > >>> allocation. > > > > > >>> > > > > > >>> This patch allows to allocate vrings based on memory region > > > > declatation. > > > > > >>> Vrings are now manage like memory carveouts, to communize > > > > memory > > > > > >> management > > > > > >>> code in rproc_alloc_registered_carveouts(). > > > > > >>> > > > > > >>> Allocated buffer is retrieved in rp_find_vq() thanks to > > > > > >>> rproc_find_carveout_by_name() functions for. > > > > > >>> > > > > > >>> This patch sets vrings names to vdev"x"vring"y" with x vdev index > > in > > > > > >>> resource table and y vring index in vdev. This will be updated > > > > > >>> when > > > > > >>> name will be associated to vdev in firmware resource table. > > > > > >>> > > > > > >>> Signed-off-by: Loic Pallardy > > > > > >>> --- > > > > > >>> drivers/remoteproc/remoteproc_core.c | 61 > > +- > > > > - > > > > > >> - > > > > > >>> drivers/remoteproc/remoteproc_internal.h | 2 ++ > > > > > >>> drivers/remoteproc/remoteproc_virtio.c | 14 +++- > > > > > >>> include/linux/remoteproc.h | 6 ++-- > > > > > >>> 4 files changed, 51 insertions(+), 32 deletions(-) > > > > > >>> > > > > > >>> diff --git a/drivers/remoteproc/remoteproc_core.c > > > > > >> b/drivers/remoteproc/remoteproc_core.c > > > > > >>> index c543d04..4edc6f0 100644 > > > > > >>> --- a/drivers/remoteproc/remoteproc_core.c > > > > > >>> +++ b/drivers/remoteproc/remoteproc_core.c > > > > > >>> @@ -53,6 +53,11 @@ typedef int > &g
Re: [PATCH v4 12/17] remoteproc: modify vring allocation to rely on centralized carveout allocator
On Tue, Dec 4, 2018 at 11:57 AM Loic PALLARDY wrote: > > > > > -Original Message- > > From: Wendy Liang > > Sent: mardi 4 décembre 2018 19:58 > > To: Loic PALLARDY > > Cc: Suman Anna ; Bjorn Andersson > > ; Ohad Ben-Cohen ; > > linux-remotep...@vger.kernel.org; Linux Kernel Mailing List > ker...@vger.kernel.org>; Arnaud POULIQUEN ; > > Benjamin Gaignard > > Subject: Re: [PATCH v4 12/17] remoteproc: modify vring allocation to rely on > > centralized carveout allocator > > > > On Tue, Dec 4, 2018 at 10:04 AM Loic PALLARDY > > wrote: > > > > > > > > > > > > > -Original Message- > > > > From: Wendy Liang > > > > Sent: mardi 4 décembre 2018 18:57 > > > > To: Suman Anna > > > > Cc: Loic PALLARDY ; Bjorn Andersson > > > > ; Ohad Ben-Cohen ; > > > > linux-remotep...@vger.kernel.org; Linux Kernel Mailing List > > > ker...@vger.kernel.org>; Arnaud POULIQUEN > > ; > > > > Benjamin Gaignard > > > > Subject: Re: [PATCH v4 12/17] remoteproc: modify vring allocation to > > > > rely > > on > > > > centralized carveout allocator > > > > > > > > On Mon, Oct 29, 2018 at 1:19 PM Suman Anna wrote: > > > > > > > > > > Hi Loic, > > > > > > > > > > On 10/24/18 10:14 AM, Loic PALLARDY wrote: > > > > > > Hi Suman, > > > > > > > > > > > >> -Original Message- > > > > > >> From: Suman Anna > > > > > >> Sent: mercredi 24 octobre 2018 02:14 > > > > > >> To: Loic PALLARDY ; > > bjorn.anders...@linaro.org; > > > > > >> o...@wizery.com > > > > > >> Cc: linux-remotep...@vger.kernel.org; linux- > > ker...@vger.kernel.org; > > > > > >> Arnaud POULIQUEN ; > > > > > >> benjamin.gaign...@linaro.org > > > > > >> Subject: Re: [PATCH v4 12/17] remoteproc: modify vring allocation > > > > > >> to > > > > rely on > > > > > >> centralized carveout allocator > > > > > >> > > > > > >> On 7/27/18 8:14 AM, Loic Pallardy wrote: > > > > > >>> Current version of rproc_alloc_vring function supports only > > dynamic > > > > vring > > > > > >>> allocation. > > > > > >>> > > > > > >>> This patch allows to allocate vrings based on memory region > > > > declatation. > > > > > >>> Vrings are now manage like memory carveouts, to communize > > > > memory > > > > > >> management > > > > > >>> code in rproc_alloc_registered_carveouts(). > > > > > >>> > > > > > >>> Allocated buffer is retrieved in rp_find_vq() thanks to > > > > > >>> rproc_find_carveout_by_name() functions for. > > > > > >>> > > > > > >>> This patch sets vrings names to vdev"x"vring"y" with x vdev index > > in > > > > > >>> resource table and y vring index in vdev. This will be updated > > > > > >>> when > > > > > >>> name will be associated to vdev in firmware resource table. > > > > > >>> > > > > > >>> Signed-off-by: Loic Pallardy > > > > > >>> --- > > > > > >>> drivers/remoteproc/remoteproc_core.c | 61 > > +- > > > > - > > > > > >> - > > > > > >>> drivers/remoteproc/remoteproc_internal.h | 2 ++ > > > > > >>> drivers/remoteproc/remoteproc_virtio.c | 14 +++- > > > > > >>> include/linux/remoteproc.h | 6 ++-- > > > > > >>> 4 files changed, 51 insertions(+), 32 deletions(-) > > > > > >>> > > > > > >>> diff --git a/drivers/remoteproc/remoteproc_core.c > > > > > >> b/drivers/remoteproc/remoteproc_core.c > > > > > >>> index c543d04..4edc6f0 100644 > > > > > >>> --- a/drivers/remoteproc/remoteproc_core.c > > > > > >>> +++ b/drivers/remoteproc/remoteproc_core.c > > > > > >>> @@ -53,6 +53,11 @@ typedef int > &g
Re: [PATCH v4 12/17] remoteproc: modify vring allocation to rely on centralized carveout allocator
On Tue, Dec 4, 2018 at 10:04 AM Loic PALLARDY wrote: > > > > > -Original Message- > > From: Wendy Liang > > Sent: mardi 4 décembre 2018 18:57 > > To: Suman Anna > > Cc: Loic PALLARDY ; Bjorn Andersson > > ; Ohad Ben-Cohen ; > > linux-remotep...@vger.kernel.org; Linux Kernel Mailing List > ker...@vger.kernel.org>; Arnaud POULIQUEN ; > > Benjamin Gaignard > > Subject: Re: [PATCH v4 12/17] remoteproc: modify vring allocation to rely on > > centralized carveout allocator > > > > On Mon, Oct 29, 2018 at 1:19 PM Suman Anna wrote: > > > > > > Hi Loic, > > > > > > On 10/24/18 10:14 AM, Loic PALLARDY wrote: > > > > Hi Suman, > > > > > > > >> -Original Message- > > > >> From: Suman Anna > > > >> Sent: mercredi 24 octobre 2018 02:14 > > > >> To: Loic PALLARDY ; bjorn.anders...@linaro.org; > > > >> o...@wizery.com > > > >> Cc: linux-remotep...@vger.kernel.org; linux-kernel@vger.kernel.org; > > > >> Arnaud POULIQUEN ; > > > >> benjamin.gaign...@linaro.org > > > >> Subject: Re: [PATCH v4 12/17] remoteproc: modify vring allocation to > > rely on > > > >> centralized carveout allocator > > > >> > > > >> On 7/27/18 8:14 AM, Loic Pallardy wrote: > > > >>> Current version of rproc_alloc_vring function supports only dynamic > > vring > > > >>> allocation. > > > >>> > > > >>> This patch allows to allocate vrings based on memory region > > declatation. > > > >>> Vrings are now manage like memory carveouts, to communize > > memory > > > >> management > > > >>> code in rproc_alloc_registered_carveouts(). > > > >>> > > > >>> Allocated buffer is retrieved in rp_find_vq() thanks to > > > >>> rproc_find_carveout_by_name() functions for. > > > >>> > > > >>> This patch sets vrings names to vdev"x"vring"y" with x vdev index in > > > >>> resource table and y vring index in vdev. This will be updated when > > > >>> name will be associated to vdev in firmware resource table. > > > >>> > > > >>> Signed-off-by: Loic Pallardy > > > >>> --- > > > >>> drivers/remoteproc/remoteproc_core.c | 61 +- > > - > > > >> - > > > >>> drivers/remoteproc/remoteproc_internal.h | 2 ++ > > > >>> drivers/remoteproc/remoteproc_virtio.c | 14 +++- > > > >>> include/linux/remoteproc.h | 6 ++-- > > > >>> 4 files changed, 51 insertions(+), 32 deletions(-) > > > >>> > > > >>> diff --git a/drivers/remoteproc/remoteproc_core.c > > > >> b/drivers/remoteproc/remoteproc_core.c > > > >>> index c543d04..4edc6f0 100644 > > > >>> --- a/drivers/remoteproc/remoteproc_core.c > > > >>> +++ b/drivers/remoteproc/remoteproc_core.c > > > >>> @@ -53,6 +53,11 @@ typedef int (*rproc_handle_resources_t)(struct > > > >> rproc *rproc, > > > >>> typedef int (*rproc_handle_resource_t)(struct rproc *rproc, > > > >>> void *, int offset, int avail); > > > >>> > > > >>> +static int rproc_alloc_carveout(struct rproc *rproc, > > > >>> + struct rproc_mem_entry *mem); > > > >>> +static int rproc_release_carveout(struct rproc *rproc, > > > >>> + struct rproc_mem_entry *mem); > > > >>> + > > > >>> /* Unique indices for remoteproc devices */ > > > >>> static DEFINE_IDA(rproc_dev_index); > > > >>> > > > >>> @@ -312,21 +317,33 @@ int rproc_alloc_vring(struct rproc_vdev > > *rvdev, > > > >> int i) > > > >>> struct device *dev = >dev; > > > >>> struct rproc_vring *rvring = >vring[i]; > > > >>> struct fw_rsc_vdev *rsc; > > > >>> - dma_addr_t dma; > > > >>> - void *va; > > > >>> int ret, size, notifyid; > > > >>> + struct rproc_mem_entry *mem; > > > >>> > > > >>> /* act
Re: [PATCH v4 12/17] remoteproc: modify vring allocation to rely on centralized carveout allocator
On Tue, Dec 4, 2018 at 10:04 AM Loic PALLARDY wrote: > > > > > -Original Message- > > From: Wendy Liang > > Sent: mardi 4 décembre 2018 18:57 > > To: Suman Anna > > Cc: Loic PALLARDY ; Bjorn Andersson > > ; Ohad Ben-Cohen ; > > linux-remotep...@vger.kernel.org; Linux Kernel Mailing List > ker...@vger.kernel.org>; Arnaud POULIQUEN ; > > Benjamin Gaignard > > Subject: Re: [PATCH v4 12/17] remoteproc: modify vring allocation to rely on > > centralized carveout allocator > > > > On Mon, Oct 29, 2018 at 1:19 PM Suman Anna wrote: > > > > > > Hi Loic, > > > > > > On 10/24/18 10:14 AM, Loic PALLARDY wrote: > > > > Hi Suman, > > > > > > > >> -Original Message- > > > >> From: Suman Anna > > > >> Sent: mercredi 24 octobre 2018 02:14 > > > >> To: Loic PALLARDY ; bjorn.anders...@linaro.org; > > > >> o...@wizery.com > > > >> Cc: linux-remotep...@vger.kernel.org; linux-kernel@vger.kernel.org; > > > >> Arnaud POULIQUEN ; > > > >> benjamin.gaign...@linaro.org > > > >> Subject: Re: [PATCH v4 12/17] remoteproc: modify vring allocation to > > rely on > > > >> centralized carveout allocator > > > >> > > > >> On 7/27/18 8:14 AM, Loic Pallardy wrote: > > > >>> Current version of rproc_alloc_vring function supports only dynamic > > vring > > > >>> allocation. > > > >>> > > > >>> This patch allows to allocate vrings based on memory region > > declatation. > > > >>> Vrings are now manage like memory carveouts, to communize > > memory > > > >> management > > > >>> code in rproc_alloc_registered_carveouts(). > > > >>> > > > >>> Allocated buffer is retrieved in rp_find_vq() thanks to > > > >>> rproc_find_carveout_by_name() functions for. > > > >>> > > > >>> This patch sets vrings names to vdev"x"vring"y" with x vdev index in > > > >>> resource table and y vring index in vdev. This will be updated when > > > >>> name will be associated to vdev in firmware resource table. > > > >>> > > > >>> Signed-off-by: Loic Pallardy > > > >>> --- > > > >>> drivers/remoteproc/remoteproc_core.c | 61 +- > > - > > > >> - > > > >>> drivers/remoteproc/remoteproc_internal.h | 2 ++ > > > >>> drivers/remoteproc/remoteproc_virtio.c | 14 +++- > > > >>> include/linux/remoteproc.h | 6 ++-- > > > >>> 4 files changed, 51 insertions(+), 32 deletions(-) > > > >>> > > > >>> diff --git a/drivers/remoteproc/remoteproc_core.c > > > >> b/drivers/remoteproc/remoteproc_core.c > > > >>> index c543d04..4edc6f0 100644 > > > >>> --- a/drivers/remoteproc/remoteproc_core.c > > > >>> +++ b/drivers/remoteproc/remoteproc_core.c > > > >>> @@ -53,6 +53,11 @@ typedef int (*rproc_handle_resources_t)(struct > > > >> rproc *rproc, > > > >>> typedef int (*rproc_handle_resource_t)(struct rproc *rproc, > > > >>> void *, int offset, int avail); > > > >>> > > > >>> +static int rproc_alloc_carveout(struct rproc *rproc, > > > >>> + struct rproc_mem_entry *mem); > > > >>> +static int rproc_release_carveout(struct rproc *rproc, > > > >>> + struct rproc_mem_entry *mem); > > > >>> + > > > >>> /* Unique indices for remoteproc devices */ > > > >>> static DEFINE_IDA(rproc_dev_index); > > > >>> > > > >>> @@ -312,21 +317,33 @@ int rproc_alloc_vring(struct rproc_vdev > > *rvdev, > > > >> int i) > > > >>> struct device *dev = >dev; > > > >>> struct rproc_vring *rvring = >vring[i]; > > > >>> struct fw_rsc_vdev *rsc; > > > >>> - dma_addr_t dma; > > > >>> - void *va; > > > >>> int ret, size, notifyid; > > > >>> + struct rproc_mem_entry *mem; > > > >>> > > > >>> /* act
Re: [PATCH v4 12/17] remoteproc: modify vring allocation to rely on centralized carveout allocator
On Mon, Oct 29, 2018 at 1:19 PM Suman Anna wrote:
>
> Hi Loic,
>
> On 10/24/18 10:14 AM, Loic PALLARDY wrote:
> > Hi Suman,
> >
> >> -Original Message-
> >> From: Suman Anna
> >> Sent: mercredi 24 octobre 2018 02:14
> >> To: Loic PALLARDY ; bjorn.anders...@linaro.org;
> >> o...@wizery.com
> >> Cc: linux-remotep...@vger.kernel.org; linux-kernel@vger.kernel.org;
> >> Arnaud POULIQUEN ;
> >> benjamin.gaign...@linaro.org
> >> Subject: Re: [PATCH v4 12/17] remoteproc: modify vring allocation to rely
> >> on
> >> centralized carveout allocator
> >>
> >> On 7/27/18 8:14 AM, Loic Pallardy wrote:
> >>> Current version of rproc_alloc_vring function supports only dynamic vring
> >>> allocation.
> >>>
> >>> This patch allows to allocate vrings based on memory region declatation.
> >>> Vrings are now manage like memory carveouts, to communize memory
> >> management
> >>> code in rproc_alloc_registered_carveouts().
> >>>
> >>> Allocated buffer is retrieved in rp_find_vq() thanks to
> >>> rproc_find_carveout_by_name() functions for.
> >>>
> >>> This patch sets vrings names to vdev"x"vring"y" with x vdev index in
> >>> resource table and y vring index in vdev. This will be updated when
> >>> name will be associated to vdev in firmware resource table.
> >>>
> >>> Signed-off-by: Loic Pallardy
> >>> ---
> >>> drivers/remoteproc/remoteproc_core.c | 61 +--
> >> -
> >>> drivers/remoteproc/remoteproc_internal.h | 2 ++
> >>> drivers/remoteproc/remoteproc_virtio.c | 14 +++-
> >>> include/linux/remoteproc.h | 6 ++--
> >>> 4 files changed, 51 insertions(+), 32 deletions(-)
> >>>
> >>> diff --git a/drivers/remoteproc/remoteproc_core.c
> >> b/drivers/remoteproc/remoteproc_core.c
> >>> index c543d04..4edc6f0 100644
> >>> --- a/drivers/remoteproc/remoteproc_core.c
> >>> +++ b/drivers/remoteproc/remoteproc_core.c
> >>> @@ -53,6 +53,11 @@ typedef int (*rproc_handle_resources_t)(struct
> >> rproc *rproc,
> >>> typedef int (*rproc_handle_resource_t)(struct rproc *rproc,
> >>> void *, int offset, int avail);
> >>>
> >>> +static int rproc_alloc_carveout(struct rproc *rproc,
> >>> + struct rproc_mem_entry *mem);
> >>> +static int rproc_release_carveout(struct rproc *rproc,
> >>> + struct rproc_mem_entry *mem);
> >>> +
> >>> /* Unique indices for remoteproc devices */
> >>> static DEFINE_IDA(rproc_dev_index);
> >>>
> >>> @@ -312,21 +317,33 @@ int rproc_alloc_vring(struct rproc_vdev *rvdev,
> >> int i)
> >>> struct device *dev = >dev;
> >>> struct rproc_vring *rvring = >vring[i];
> >>> struct fw_rsc_vdev *rsc;
> >>> - dma_addr_t dma;
> >>> - void *va;
> >>> int ret, size, notifyid;
> >>> + struct rproc_mem_entry *mem;
> >>>
> >>> /* actual size of vring (in bytes) */
> >>> size = PAGE_ALIGN(vring_size(rvring->len, rvring->align));
> >>>
> >>> - /*
> >>> -* Allocate non-cacheable memory for the vring. In the future
> >>> -* this call will also configure the IOMMU for us
> >>> -*/
> >>> - va = dma_alloc_coherent(dev->parent, size, , GFP_KERNEL);
> >>> - if (!va) {
> >>> - dev_err(dev->parent, "dma_alloc_coherent failed\n");
> >>> - return -EINVAL;
> >>> + rsc = (void *)rproc->table_ptr + rvdev->rsc_offset;
> >>> +
> >>> + /* Search for pre-registered carveout */
> >>> + mem = rproc_find_carveout_by_name(rproc, "vdev%dvring%d",
> >> rvdev->index,
> >>> + i);
> >>> + if (mem) {
> >>> + if (rproc_check_carveout_da(rproc, mem, rsc->vring[i].da,
> >> size))
> >>> + return -ENOMEM;
> >>> + } else {
> >>> + /* Register carveout in in list */
> >>> + mem = rproc_mem_entry_init(dev, 0, 0, size, rsc-
> >>> vring[i].da,
> >>> + rproc_alloc_carveout,
> >>> + rproc_release_carveout,
> >>> + "vdev%dvring%d",
> >>> + rvdev->index, i);
> >>> + if (!mem) {
> >>> + dev_err(dev, "Can't allocate memory entry
> >> structure\n");
> >>> + return -ENOMEM;
> >>> + }
> >>> +
> >>> + rproc_add_carveout(rproc, mem);
> >>> }
> >>>
> >>> /*
> >>> @@ -337,7 +354,6 @@ int rproc_alloc_vring(struct rproc_vdev *rvdev, int i)
> >>> ret = idr_alloc(>notifyids, rvring, 0, 0, GFP_KERNEL);
> >>> if (ret < 0) {
> >>> dev_err(dev, "idr_alloc failed: %d\n", ret);
> >>> - dma_free_coherent(dev->parent, size, va, dma);
> >>> return ret;
> >>> }
> >>> notifyid = ret;
> >>> @@ -346,21 +362,9 @@ int rproc_alloc_vring(struct rproc_vdev *rvdev, int
> >> i)
> >>> if (notifyid > rproc->max_notifyid)
> >>> rproc->max_notifyid = notifyid;
> >>>
> >>> - dev_dbg(dev, "vring%d: va %pK dma %pad size 0x%x
Re: [PATCH v4 12/17] remoteproc: modify vring allocation to rely on centralized carveout allocator
On Mon, Oct 29, 2018 at 1:19 PM Suman Anna wrote:
>
> Hi Loic,
>
> On 10/24/18 10:14 AM, Loic PALLARDY wrote:
> > Hi Suman,
> >
> >> -Original Message-
> >> From: Suman Anna
> >> Sent: mercredi 24 octobre 2018 02:14
> >> To: Loic PALLARDY ; bjorn.anders...@linaro.org;
> >> o...@wizery.com
> >> Cc: linux-remotep...@vger.kernel.org; linux-kernel@vger.kernel.org;
> >> Arnaud POULIQUEN ;
> >> benjamin.gaign...@linaro.org
> >> Subject: Re: [PATCH v4 12/17] remoteproc: modify vring allocation to rely
> >> on
> >> centralized carveout allocator
> >>
> >> On 7/27/18 8:14 AM, Loic Pallardy wrote:
> >>> Current version of rproc_alloc_vring function supports only dynamic vring
> >>> allocation.
> >>>
> >>> This patch allows to allocate vrings based on memory region declatation.
> >>> Vrings are now manage like memory carveouts, to communize memory
> >> management
> >>> code in rproc_alloc_registered_carveouts().
> >>>
> >>> Allocated buffer is retrieved in rp_find_vq() thanks to
> >>> rproc_find_carveout_by_name() functions for.
> >>>
> >>> This patch sets vrings names to vdev"x"vring"y" with x vdev index in
> >>> resource table and y vring index in vdev. This will be updated when
> >>> name will be associated to vdev in firmware resource table.
> >>>
> >>> Signed-off-by: Loic Pallardy
> >>> ---
> >>> drivers/remoteproc/remoteproc_core.c | 61 +--
> >> -
> >>> drivers/remoteproc/remoteproc_internal.h | 2 ++
> >>> drivers/remoteproc/remoteproc_virtio.c | 14 +++-
> >>> include/linux/remoteproc.h | 6 ++--
> >>> 4 files changed, 51 insertions(+), 32 deletions(-)
> >>>
> >>> diff --git a/drivers/remoteproc/remoteproc_core.c
> >> b/drivers/remoteproc/remoteproc_core.c
> >>> index c543d04..4edc6f0 100644
> >>> --- a/drivers/remoteproc/remoteproc_core.c
> >>> +++ b/drivers/remoteproc/remoteproc_core.c
> >>> @@ -53,6 +53,11 @@ typedef int (*rproc_handle_resources_t)(struct
> >> rproc *rproc,
> >>> typedef int (*rproc_handle_resource_t)(struct rproc *rproc,
> >>> void *, int offset, int avail);
> >>>
> >>> +static int rproc_alloc_carveout(struct rproc *rproc,
> >>> + struct rproc_mem_entry *mem);
> >>> +static int rproc_release_carveout(struct rproc *rproc,
> >>> + struct rproc_mem_entry *mem);
> >>> +
> >>> /* Unique indices for remoteproc devices */
> >>> static DEFINE_IDA(rproc_dev_index);
> >>>
> >>> @@ -312,21 +317,33 @@ int rproc_alloc_vring(struct rproc_vdev *rvdev,
> >> int i)
> >>> struct device *dev = >dev;
> >>> struct rproc_vring *rvring = >vring[i];
> >>> struct fw_rsc_vdev *rsc;
> >>> - dma_addr_t dma;
> >>> - void *va;
> >>> int ret, size, notifyid;
> >>> + struct rproc_mem_entry *mem;
> >>>
> >>> /* actual size of vring (in bytes) */
> >>> size = PAGE_ALIGN(vring_size(rvring->len, rvring->align));
> >>>
> >>> - /*
> >>> -* Allocate non-cacheable memory for the vring. In the future
> >>> -* this call will also configure the IOMMU for us
> >>> -*/
> >>> - va = dma_alloc_coherent(dev->parent, size, , GFP_KERNEL);
> >>> - if (!va) {
> >>> - dev_err(dev->parent, "dma_alloc_coherent failed\n");
> >>> - return -EINVAL;
> >>> + rsc = (void *)rproc->table_ptr + rvdev->rsc_offset;
> >>> +
> >>> + /* Search for pre-registered carveout */
> >>> + mem = rproc_find_carveout_by_name(rproc, "vdev%dvring%d",
> >> rvdev->index,
> >>> + i);
> >>> + if (mem) {
> >>> + if (rproc_check_carveout_da(rproc, mem, rsc->vring[i].da,
> >> size))
> >>> + return -ENOMEM;
> >>> + } else {
> >>> + /* Register carveout in in list */
> >>> + mem = rproc_mem_entry_init(dev, 0, 0, size, rsc-
> >>> vring[i].da,
> >>> + rproc_alloc_carveout,
> >>> + rproc_release_carveout,
> >>> + "vdev%dvring%d",
> >>> + rvdev->index, i);
> >>> + if (!mem) {
> >>> + dev_err(dev, "Can't allocate memory entry
> >> structure\n");
> >>> + return -ENOMEM;
> >>> + }
> >>> +
> >>> + rproc_add_carveout(rproc, mem);
> >>> }
> >>>
> >>> /*
> >>> @@ -337,7 +354,6 @@ int rproc_alloc_vring(struct rproc_vdev *rvdev, int i)
> >>> ret = idr_alloc(>notifyids, rvring, 0, 0, GFP_KERNEL);
> >>> if (ret < 0) {
> >>> dev_err(dev, "idr_alloc failed: %d\n", ret);
> >>> - dma_free_coherent(dev->parent, size, va, dma);
> >>> return ret;
> >>> }
> >>> notifyid = ret;
> >>> @@ -346,21 +362,9 @@ int rproc_alloc_vring(struct rproc_vdev *rvdev, int
> >> i)
> >>> if (notifyid > rproc->max_notifyid)
> >>> rproc->max_notifyid = notifyid;
> >>>
> >>> - dev_dbg(dev, "vring%d: va %pK dma %pad size 0x%x
[PATCH v6 0/2] Xilinx ZynqMP IPI Mailbox Controller Driver
Introduce mailbox controller driver for ZynqMP IPI(Inter-processor interrupt) IP core. As the device tree bindings have been updated. Do not have "Reviewed-by" nor "Acked-by" in the dt-bindings commit. v6: - dts-binding, remove compatible property from IPI subnode v5: - fix check patch warning on write a paragraph to describe the kconfig symbol. v4: - make IPI mailboxes as subnodes to the IPI agent device node to properly describe the hardware. v3: - add NULL entry to of_device_id of IPI controller v2: - change SPDX-License-Identifier license text style in .c file - replace xlnx-ipi-ids with xlnx,ipi-ids Wendy Liang (2): mailbox: ZynqMP IPI mailbox controller dt-bindings: mailbox: Add Xilinx IPI Mailbox .../bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt | 127 drivers/mailbox/Kconfig| 9 + drivers/mailbox/Makefile | 2 + drivers/mailbox/zynqmp-ipi-mailbox.c | 762 + include/linux/mailbox/zynqmp-ipi-message.h | 24 + 5 files changed, 924 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt create mode 100644 drivers/mailbox/zynqmp-ipi-mailbox.c create mode 100644 include/linux/mailbox/zynqmp-ipi-message.h -- 2.7.4
[PATCH v6 0/2] Xilinx ZynqMP IPI Mailbox Controller Driver
Introduce mailbox controller driver for ZynqMP IPI(Inter-processor interrupt) IP core. As the device tree bindings have been updated. Do not have "Reviewed-by" nor "Acked-by" in the dt-bindings commit. v6: - dts-binding, remove compatible property from IPI subnode v5: - fix check patch warning on write a paragraph to describe the kconfig symbol. v4: - make IPI mailboxes as subnodes to the IPI agent device node to properly describe the hardware. v3: - add NULL entry to of_device_id of IPI controller v2: - change SPDX-License-Identifier license text style in .c file - replace xlnx-ipi-ids with xlnx,ipi-ids Wendy Liang (2): mailbox: ZynqMP IPI mailbox controller dt-bindings: mailbox: Add Xilinx IPI Mailbox .../bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt | 127 drivers/mailbox/Kconfig| 9 + drivers/mailbox/Makefile | 2 + drivers/mailbox/zynqmp-ipi-mailbox.c | 762 + include/linux/mailbox/zynqmp-ipi-message.h | 24 + 5 files changed, 924 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt create mode 100644 drivers/mailbox/zynqmp-ipi-mailbox.c create mode 100644 include/linux/mailbox/zynqmp-ipi-message.h -- 2.7.4
[PATCH v6 2/2] dt-bindings: mailbox: Add Xilinx IPI Mailbox
Xilinx ZynqMP IPI(Inter Processor Interrupt) is a hardware block
in ZynqMP SoC used for the communication between various processor
systems.
Signed-off-by: Wendy Liang
---
.../bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt | 127 +
1 file changed, 127 insertions(+)
create mode 100644
Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt
diff --git
a/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt
b/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt
new file mode 100644
index 000..4438432
--- /dev/null
+++ b/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt
@@ -0,0 +1,127 @@
+Xilinx IPI Mailbox Controller
+
+
+The Xilinx IPI(Inter Processor Interrupt) mailbox controller is to manage
+messaging between two Xilinx Zynq UltraScale+ MPSoC IPI agents. Each IPI
+agent owns registers used for notification and buffers for message.
+
+ +-+
+ | Xilinx ZynqMP IPI Controller|
+ +-+
++--+
+ATF| |
+ | |
+ | |
++--+ |
+ | |
+ | |
++--+
++--+
+| ++ ++ |
+Hardware| | IPI Agent | | IPI Buffers | |
+| | Registers | || |
+| || || |
+| ++ ++ |
+| |
+| Xilinx IPI Agent Block |
++--+
+
+
+Controller Device Node:
+===
+Required properties:
+
+IPI agent node:
+- compatible: Shall be: "xlnx,zynqmp-ipi-mailbox"
+- interrupt-parent:Phandle for the interrupt controller
+- interrupts: Interrupt information corresponding to the
+ interrupt-names property.
+- xlnx,ipi-id: local Xilinx IPI agent ID
+- #address-cells: number of address cells of internal IPI mailbox nodes
+- #size-cells: number of size cells of internal IPI mailbox nodes
+
+Internal IPI mailbox node:
+- reg: IPI buffers address ranges
+- reg-names: Names of the reg resources. It should have:
+ * local_request_region
+ - IPI request msg buffer written by local and read
+ by remote
+ * local_response_region
+ - IPI response msg buffer written by local and read
+ by remote
+ * remote_request_region
+ - IPI request msg buffer written by remote and read
+ by local
+ * remote_response_region
+ - IPI response msg buffer written by remote and read
+ by local
+- #mbox-cells: Shall be 1. It contains:
+ * tx(0) or rx(1) channel
+- xlnx,ipi-id: remote Xilinx IPI agent ID of which the mailbox is
+ connected to.
+
+Optional properties:
+
+- method: The method of accessing the IPI agent registers.
+ Permitted values are: "smc" and "hvc". Default is
+ "smc".
+
+Client Device Node:
+===
+Required properties:
+
+- mboxes: Standard property to specify a mailbox
+ (See ./mailbox.txt)
+- mbox-names: List of identifier strings for each mailbox
+ channel.
+
+Example:
+===
+ zynqmp_ipi {
+ compatible = "xlnx,zynqmp-ipi-mailbox";
+ interrupt-parent = <>;
+ interrupts = <0 29 4>;
+ xlnx,ipi-id = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ /* APU<->RPU0 IPI mailbox controller */
+ ipi_mailbox_rpu0: mailbox@ff90400 {
+ reg = <0xff990400 0x20>,
+ <0xff990420 0x20>,
+ <0xff990080 0x20>,
+ <0xff9900a0 0x20>;
+ reg-names = "local_request_region",
[PATCH v6 2/2] dt-bindings: mailbox: Add Xilinx IPI Mailbox
Xilinx ZynqMP IPI(Inter Processor Interrupt) is a hardware block
in ZynqMP SoC used for the communication between various processor
systems.
Signed-off-by: Wendy Liang
---
.../bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt | 127 +
1 file changed, 127 insertions(+)
create mode 100644
Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt
diff --git
a/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt
b/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt
new file mode 100644
index 000..4438432
--- /dev/null
+++ b/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt
@@ -0,0 +1,127 @@
+Xilinx IPI Mailbox Controller
+
+
+The Xilinx IPI(Inter Processor Interrupt) mailbox controller is to manage
+messaging between two Xilinx Zynq UltraScale+ MPSoC IPI agents. Each IPI
+agent owns registers used for notification and buffers for message.
+
+ +-+
+ | Xilinx ZynqMP IPI Controller|
+ +-+
++--+
+ATF| |
+ | |
+ | |
++--+ |
+ | |
+ | |
++--+
++--+
+| ++ ++ |
+Hardware| | IPI Agent | | IPI Buffers | |
+| | Registers | || |
+| || || |
+| ++ ++ |
+| |
+| Xilinx IPI Agent Block |
++--+
+
+
+Controller Device Node:
+===
+Required properties:
+
+IPI agent node:
+- compatible: Shall be: "xlnx,zynqmp-ipi-mailbox"
+- interrupt-parent:Phandle for the interrupt controller
+- interrupts: Interrupt information corresponding to the
+ interrupt-names property.
+- xlnx,ipi-id: local Xilinx IPI agent ID
+- #address-cells: number of address cells of internal IPI mailbox nodes
+- #size-cells: number of size cells of internal IPI mailbox nodes
+
+Internal IPI mailbox node:
+- reg: IPI buffers address ranges
+- reg-names: Names of the reg resources. It should have:
+ * local_request_region
+ - IPI request msg buffer written by local and read
+ by remote
+ * local_response_region
+ - IPI response msg buffer written by local and read
+ by remote
+ * remote_request_region
+ - IPI request msg buffer written by remote and read
+ by local
+ * remote_response_region
+ - IPI response msg buffer written by remote and read
+ by local
+- #mbox-cells: Shall be 1. It contains:
+ * tx(0) or rx(1) channel
+- xlnx,ipi-id: remote Xilinx IPI agent ID of which the mailbox is
+ connected to.
+
+Optional properties:
+
+- method: The method of accessing the IPI agent registers.
+ Permitted values are: "smc" and "hvc". Default is
+ "smc".
+
+Client Device Node:
+===
+Required properties:
+
+- mboxes: Standard property to specify a mailbox
+ (See ./mailbox.txt)
+- mbox-names: List of identifier strings for each mailbox
+ channel.
+
+Example:
+===
+ zynqmp_ipi {
+ compatible = "xlnx,zynqmp-ipi-mailbox";
+ interrupt-parent = <>;
+ interrupts = <0 29 4>;
+ xlnx,ipi-id = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ /* APU<->RPU0 IPI mailbox controller */
+ ipi_mailbox_rpu0: mailbox@ff90400 {
+ reg = <0xff990400 0x20>,
+ <0xff990420 0x20>,
+ <0xff990080 0x20>,
+ <0xff9900a0 0x20>;
+ reg-names = "local_request_region",
[PATCH v6 1/2] mailbox: ZynqMP IPI mailbox controller
This patch is to introduce ZynqMP IPI mailbox controller driver
to use the ZynqMP IPI block as mailboxes.
Signed-off-by: Wendy Liang
---
drivers/mailbox/Kconfig| 9 +
drivers/mailbox/Makefile | 2 +
drivers/mailbox/zynqmp-ipi-mailbox.c | 762 +
include/linux/mailbox/zynqmp-ipi-message.h | 24 +
4 files changed, 797 insertions(+)
create mode 100644 drivers/mailbox/zynqmp-ipi-mailbox.c
create mode 100644 include/linux/mailbox/zynqmp-ipi-message.h
diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig
index 3eeb12e9..10bfe3f 100644
--- a/drivers/mailbox/Kconfig
+++ b/drivers/mailbox/Kconfig
@@ -205,4 +205,13 @@ config MTK_CMDQ_MBOX
mailbox driver. The CMDQ is used to help read/write registers with
critical time limitation, such as updating display configuration
during the vblank.
+
+config ZYNQMP_IPI_MBOX
+ tristate "Xilinx ZynqMP IPI Mailbox"
+ depends on ARCH_ZYNQMP && OF
+ help
+ Mailbox implementation for Xilinx ZynqMP IPI controller. It is used
+ to send notification or short message between processors on Xilinx
+ UltraScale+ MPSoC platforms. Say Y here if you want to have this
+ support.
endif
diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile
index c818b5d..bb3d604 100644
--- a/drivers/mailbox/Makefile
+++ b/drivers/mailbox/Makefile
@@ -44,3 +44,5 @@ obj-$(CONFIG_TEGRA_HSP_MBOX) += tegra-hsp.o
obj-$(CONFIG_STM32_IPCC) += stm32-ipcc.o
obj-$(CONFIG_MTK_CMDQ_MBOX)+= mtk-cmdq-mailbox.o
+
+obj-$(CONFIG_ZYNQMP_IPI_MBOX) += zynqmp-ipi-mailbox.o
diff --git a/drivers/mailbox/zynqmp-ipi-mailbox.c
b/drivers/mailbox/zynqmp-ipi-mailbox.c
new file mode 100644
index 000..bc02864
--- /dev/null
+++ b/drivers/mailbox/zynqmp-ipi-mailbox.c
@@ -0,0 +1,762 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Inter Processor Interrupt(IPI) Mailbox Driver
+ *
+ * Copyright (C) 2018 Xilinx Inc.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* IPI agent ID any */
+#define IPI_ID_ANY 0xFFUL
+
+/* indicate if ZynqMP IPI mailbox driver uses SMC calls or HVC calls */
+#define USE_SMC 0
+#define USE_HVC 1
+
+/* Default IPI SMC function IDs */
+#define SMC_IPI_MAILBOX_OPEN0x82001000U
+#define SMC_IPI_MAILBOX_RELEASE 0x82001001U
+#define SMC_IPI_MAILBOX_STATUS_ENQUIRY 0x82001002U
+#define SMC_IPI_MAILBOX_NOTIFY 0x82001003U
+#define SMC_IPI_MAILBOX_ACK 0x82001004U
+#define SMC_IPI_MAILBOX_ENABLE_IRQ 0x82001005U
+#define SMC_IPI_MAILBOX_DISABLE_IRQ 0x82001006U
+
+/* IPI SMC Macros */
+#define IPI_SMC_OPEN_IRQ_MASK 0x0001UL /* IRQ enable bit in IPI
+ * open SMC call
+ */
+#define IPI_SMC_NOTIFY_BLOCK_MASK 0x0001UL /* Flag to indicate if
+ * IPI notification needs
+ * to be blocking.
+ */
+#define IPI_SMC_ENQUIRY_DIRQ_MASK 0x0001UL /* Flag to indicate if
+ * notification interrupt
+ * to be disabled.
+ */
+#define IPI_SMC_ACK_EIRQ_MASK 0x0001UL /* Flag to indicate if
+ * notification interrupt
+ * to be enabled.
+ */
+
+/* IPI mailbox status */
+#define IPI_MB_STATUS_IDLE 0
+#define IPI_MB_STATUS_SEND_PENDING 1
+#define IPI_MB_STATUS_RECV_PENDING 2
+
+#define IPI_MB_CHNL_TX 0 /* IPI mailbox TX channel */
+#define IPI_MB_CHNL_RX 1 /* IPI mailbox RX channel */
+
+/**
+ * struct zynqmp_ipi_mchan - Description of a Xilinx ZynqMP IPI mailbox channel
+ * @is_opened: indicate if the IPI channel is opened
+ * @req_buf: local to remote request buffer start address
+ * @resp_buf: local to remote response buffer start address
+ * @req_buf_size: request buffer size
+ * @resp_buf_size: response buffer size
+ * @rx_buf: receive buffer to pass received message to client
+ * @chan_type: channel type
+ */
+struct zynqmp_ipi_mchan {
+ int is_opened;
+ void __iomem *req_buf;
+ void __iomem *resp_buf;
+ void *rx_buf;
+ size_t req_buf_size;
+ size_t resp_buf_size;
+ unsigned int chan_type;
+};
+
+/**
+ * struct zynqmp_ipi_mbox - Description of a ZynqMP IPI mailbox
+ * platform data.
+ * @pdata: pointer to the IPI private data
+ * @dev:
[PATCH v6 1/2] mailbox: ZynqMP IPI mailbox controller
This patch is to introduce ZynqMP IPI mailbox controller driver
to use the ZynqMP IPI block as mailboxes.
Signed-off-by: Wendy Liang
---
drivers/mailbox/Kconfig| 9 +
drivers/mailbox/Makefile | 2 +
drivers/mailbox/zynqmp-ipi-mailbox.c | 762 +
include/linux/mailbox/zynqmp-ipi-message.h | 24 +
4 files changed, 797 insertions(+)
create mode 100644 drivers/mailbox/zynqmp-ipi-mailbox.c
create mode 100644 include/linux/mailbox/zynqmp-ipi-message.h
diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig
index 3eeb12e9..10bfe3f 100644
--- a/drivers/mailbox/Kconfig
+++ b/drivers/mailbox/Kconfig
@@ -205,4 +205,13 @@ config MTK_CMDQ_MBOX
mailbox driver. The CMDQ is used to help read/write registers with
critical time limitation, such as updating display configuration
during the vblank.
+
+config ZYNQMP_IPI_MBOX
+ tristate "Xilinx ZynqMP IPI Mailbox"
+ depends on ARCH_ZYNQMP && OF
+ help
+ Mailbox implementation for Xilinx ZynqMP IPI controller. It is used
+ to send notification or short message between processors on Xilinx
+ UltraScale+ MPSoC platforms. Say Y here if you want to have this
+ support.
endif
diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile
index c818b5d..bb3d604 100644
--- a/drivers/mailbox/Makefile
+++ b/drivers/mailbox/Makefile
@@ -44,3 +44,5 @@ obj-$(CONFIG_TEGRA_HSP_MBOX) += tegra-hsp.o
obj-$(CONFIG_STM32_IPCC) += stm32-ipcc.o
obj-$(CONFIG_MTK_CMDQ_MBOX)+= mtk-cmdq-mailbox.o
+
+obj-$(CONFIG_ZYNQMP_IPI_MBOX) += zynqmp-ipi-mailbox.o
diff --git a/drivers/mailbox/zynqmp-ipi-mailbox.c
b/drivers/mailbox/zynqmp-ipi-mailbox.c
new file mode 100644
index 000..bc02864
--- /dev/null
+++ b/drivers/mailbox/zynqmp-ipi-mailbox.c
@@ -0,0 +1,762 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Inter Processor Interrupt(IPI) Mailbox Driver
+ *
+ * Copyright (C) 2018 Xilinx Inc.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* IPI agent ID any */
+#define IPI_ID_ANY 0xFFUL
+
+/* indicate if ZynqMP IPI mailbox driver uses SMC calls or HVC calls */
+#define USE_SMC 0
+#define USE_HVC 1
+
+/* Default IPI SMC function IDs */
+#define SMC_IPI_MAILBOX_OPEN0x82001000U
+#define SMC_IPI_MAILBOX_RELEASE 0x82001001U
+#define SMC_IPI_MAILBOX_STATUS_ENQUIRY 0x82001002U
+#define SMC_IPI_MAILBOX_NOTIFY 0x82001003U
+#define SMC_IPI_MAILBOX_ACK 0x82001004U
+#define SMC_IPI_MAILBOX_ENABLE_IRQ 0x82001005U
+#define SMC_IPI_MAILBOX_DISABLE_IRQ 0x82001006U
+
+/* IPI SMC Macros */
+#define IPI_SMC_OPEN_IRQ_MASK 0x0001UL /* IRQ enable bit in IPI
+ * open SMC call
+ */
+#define IPI_SMC_NOTIFY_BLOCK_MASK 0x0001UL /* Flag to indicate if
+ * IPI notification needs
+ * to be blocking.
+ */
+#define IPI_SMC_ENQUIRY_DIRQ_MASK 0x0001UL /* Flag to indicate if
+ * notification interrupt
+ * to be disabled.
+ */
+#define IPI_SMC_ACK_EIRQ_MASK 0x0001UL /* Flag to indicate if
+ * notification interrupt
+ * to be enabled.
+ */
+
+/* IPI mailbox status */
+#define IPI_MB_STATUS_IDLE 0
+#define IPI_MB_STATUS_SEND_PENDING 1
+#define IPI_MB_STATUS_RECV_PENDING 2
+
+#define IPI_MB_CHNL_TX 0 /* IPI mailbox TX channel */
+#define IPI_MB_CHNL_RX 1 /* IPI mailbox RX channel */
+
+/**
+ * struct zynqmp_ipi_mchan - Description of a Xilinx ZynqMP IPI mailbox channel
+ * @is_opened: indicate if the IPI channel is opened
+ * @req_buf: local to remote request buffer start address
+ * @resp_buf: local to remote response buffer start address
+ * @req_buf_size: request buffer size
+ * @resp_buf_size: response buffer size
+ * @rx_buf: receive buffer to pass received message to client
+ * @chan_type: channel type
+ */
+struct zynqmp_ipi_mchan {
+ int is_opened;
+ void __iomem *req_buf;
+ void __iomem *resp_buf;
+ void *rx_buf;
+ size_t req_buf_size;
+ size_t resp_buf_size;
+ unsigned int chan_type;
+};
+
+/**
+ * struct zynqmp_ipi_mbox - Description of a ZynqMP IPI mailbox
+ * platform data.
+ * @pdata: pointer to the IPI private data
+ * @dev:
[PATCH v5 1/2] mailbox: ZynqMP IPI mailbox controller
This patch is to introduce ZynqMP IPI mailbox controller driver
to use the ZynqMP IPI block as mailboxes.
Signed-off-by: Wendy Liang
---
drivers/mailbox/Kconfig| 9 +
drivers/mailbox/Makefile | 2 +
drivers/mailbox/zynqmp-ipi-mailbox.c | 762 +
include/linux/mailbox/zynqmp-ipi-message.h | 24 +
4 files changed, 797 insertions(+)
create mode 100644 drivers/mailbox/zynqmp-ipi-mailbox.c
create mode 100644 include/linux/mailbox/zynqmp-ipi-message.h
diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig
index 3eeb12e9..10bfe3f 100644
--- a/drivers/mailbox/Kconfig
+++ b/drivers/mailbox/Kconfig
@@ -205,4 +205,13 @@ config MTK_CMDQ_MBOX
mailbox driver. The CMDQ is used to help read/write registers with
critical time limitation, such as updating display configuration
during the vblank.
+
+config ZYNQMP_IPI_MBOX
+ tristate "Xilinx ZynqMP IPI Mailbox"
+ depends on ARCH_ZYNQMP && OF
+ help
+ Mailbox implementation for Xilinx ZynqMP IPI controller. It is used
+ to send notification or short message between processors on Xilinx
+ UltraScale+ MPSoC platforms. Say Y here if you want to have this
+ support.
endif
diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile
index c818b5d..bb3d604 100644
--- a/drivers/mailbox/Makefile
+++ b/drivers/mailbox/Makefile
@@ -44,3 +44,5 @@ obj-$(CONFIG_TEGRA_HSP_MBOX) += tegra-hsp.o
obj-$(CONFIG_STM32_IPCC) += stm32-ipcc.o
obj-$(CONFIG_MTK_CMDQ_MBOX)+= mtk-cmdq-mailbox.o
+
+obj-$(CONFIG_ZYNQMP_IPI_MBOX) += zynqmp-ipi-mailbox.o
diff --git a/drivers/mailbox/zynqmp-ipi-mailbox.c
b/drivers/mailbox/zynqmp-ipi-mailbox.c
new file mode 100644
index 000..6a2e0fc
--- /dev/null
+++ b/drivers/mailbox/zynqmp-ipi-mailbox.c
@@ -0,0 +1,762 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Inter Processor Interrupt(IPI) Mailbox Driver
+ *
+ * Copyright (C) 2018 Xilinx Inc.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* IPI agent ID any */
+#define IPI_ID_ANY 0xFFUL
+
+/* indicate if ZynqMP IPI mailbox driver uses SMC calls or HVC calls */
+#define USE_SMC 0
+#define USE_HVC 1
+
+/* Default IPI SMC function IDs */
+#define SMC_IPI_MAILBOX_OPEN0x82001000U
+#define SMC_IPI_MAILBOX_RELEASE 0x82001001U
+#define SMC_IPI_MAILBOX_STATUS_ENQUIRY 0x82001002U
+#define SMC_IPI_MAILBOX_NOTIFY 0x82001003U
+#define SMC_IPI_MAILBOX_ACK 0x82001004U
+#define SMC_IPI_MAILBOX_ENABLE_IRQ 0x82001005U
+#define SMC_IPI_MAILBOX_DISABLE_IRQ 0x82001006U
+
+/* IPI SMC Macros */
+#define IPI_SMC_OPEN_IRQ_MASK 0x0001UL /* IRQ enable bit in IPI
+ * open SMC call
+ */
+#define IPI_SMC_NOTIFY_BLOCK_MASK 0x0001UL /* Flag to indicate if
+ * IPI notification needs
+ * to be blocking.
+ */
+#define IPI_SMC_ENQUIRY_DIRQ_MASK 0x0001UL /* Flag to indicate if
+ * notification interrupt
+ * to be disabled.
+ */
+#define IPI_SMC_ACK_EIRQ_MASK 0x0001UL /* Flag to indicate if
+ * notification interrupt
+ * to be enabled.
+ */
+
+/* IPI mailbox status */
+#define IPI_MB_STATUS_IDLE 0
+#define IPI_MB_STATUS_SEND_PENDING 1
+#define IPI_MB_STATUS_RECV_PENDING 2
+
+#define IPI_MB_CHNL_TX 0 /* IPI mailbox TX channel */
+#define IPI_MB_CHNL_RX 1 /* IPI mailbox RX channel */
+
+/**
+ * struct zynqmp_ipi_mchan - Description of a Xilinx ZynqMP IPI mailbox channel
+ * @is_opened: indicate if the IPI channel is opened
+ * @req_buf: local to remote request buffer start address
+ * @resp_buf: local to remote response buffer start address
+ * @req_buf_size: request buffer size
+ * @resp_buf_size: response buffer size
+ * @rx_buf: receive buffer to pass received message to client
+ * @chan_type: channel type
+ */
+struct zynqmp_ipi_mchan {
+ int is_opened;
+ void __iomem *req_buf;
+ void __iomem *resp_buf;
+ void *rx_buf;
+ size_t req_buf_size;
+ size_t resp_buf_size;
+ unsigned int chan_type;
+};
+
+/**
+ * struct zynqmp_ipi_mbox - Description of a ZynqMP IPI mailbox
+ * platform data.
+ * @pdata: pointer to the IPI private data
+ * @dev:
[PATCH v5 1/2] mailbox: ZynqMP IPI mailbox controller
This patch is to introduce ZynqMP IPI mailbox controller driver
to use the ZynqMP IPI block as mailboxes.
Signed-off-by: Wendy Liang
---
drivers/mailbox/Kconfig| 9 +
drivers/mailbox/Makefile | 2 +
drivers/mailbox/zynqmp-ipi-mailbox.c | 762 +
include/linux/mailbox/zynqmp-ipi-message.h | 24 +
4 files changed, 797 insertions(+)
create mode 100644 drivers/mailbox/zynqmp-ipi-mailbox.c
create mode 100644 include/linux/mailbox/zynqmp-ipi-message.h
diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig
index 3eeb12e9..10bfe3f 100644
--- a/drivers/mailbox/Kconfig
+++ b/drivers/mailbox/Kconfig
@@ -205,4 +205,13 @@ config MTK_CMDQ_MBOX
mailbox driver. The CMDQ is used to help read/write registers with
critical time limitation, such as updating display configuration
during the vblank.
+
+config ZYNQMP_IPI_MBOX
+ tristate "Xilinx ZynqMP IPI Mailbox"
+ depends on ARCH_ZYNQMP && OF
+ help
+ Mailbox implementation for Xilinx ZynqMP IPI controller. It is used
+ to send notification or short message between processors on Xilinx
+ UltraScale+ MPSoC platforms. Say Y here if you want to have this
+ support.
endif
diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile
index c818b5d..bb3d604 100644
--- a/drivers/mailbox/Makefile
+++ b/drivers/mailbox/Makefile
@@ -44,3 +44,5 @@ obj-$(CONFIG_TEGRA_HSP_MBOX) += tegra-hsp.o
obj-$(CONFIG_STM32_IPCC) += stm32-ipcc.o
obj-$(CONFIG_MTK_CMDQ_MBOX)+= mtk-cmdq-mailbox.o
+
+obj-$(CONFIG_ZYNQMP_IPI_MBOX) += zynqmp-ipi-mailbox.o
diff --git a/drivers/mailbox/zynqmp-ipi-mailbox.c
b/drivers/mailbox/zynqmp-ipi-mailbox.c
new file mode 100644
index 000..6a2e0fc
--- /dev/null
+++ b/drivers/mailbox/zynqmp-ipi-mailbox.c
@@ -0,0 +1,762 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Inter Processor Interrupt(IPI) Mailbox Driver
+ *
+ * Copyright (C) 2018 Xilinx Inc.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* IPI agent ID any */
+#define IPI_ID_ANY 0xFFUL
+
+/* indicate if ZynqMP IPI mailbox driver uses SMC calls or HVC calls */
+#define USE_SMC 0
+#define USE_HVC 1
+
+/* Default IPI SMC function IDs */
+#define SMC_IPI_MAILBOX_OPEN0x82001000U
+#define SMC_IPI_MAILBOX_RELEASE 0x82001001U
+#define SMC_IPI_MAILBOX_STATUS_ENQUIRY 0x82001002U
+#define SMC_IPI_MAILBOX_NOTIFY 0x82001003U
+#define SMC_IPI_MAILBOX_ACK 0x82001004U
+#define SMC_IPI_MAILBOX_ENABLE_IRQ 0x82001005U
+#define SMC_IPI_MAILBOX_DISABLE_IRQ 0x82001006U
+
+/* IPI SMC Macros */
+#define IPI_SMC_OPEN_IRQ_MASK 0x0001UL /* IRQ enable bit in IPI
+ * open SMC call
+ */
+#define IPI_SMC_NOTIFY_BLOCK_MASK 0x0001UL /* Flag to indicate if
+ * IPI notification needs
+ * to be blocking.
+ */
+#define IPI_SMC_ENQUIRY_DIRQ_MASK 0x0001UL /* Flag to indicate if
+ * notification interrupt
+ * to be disabled.
+ */
+#define IPI_SMC_ACK_EIRQ_MASK 0x0001UL /* Flag to indicate if
+ * notification interrupt
+ * to be enabled.
+ */
+
+/* IPI mailbox status */
+#define IPI_MB_STATUS_IDLE 0
+#define IPI_MB_STATUS_SEND_PENDING 1
+#define IPI_MB_STATUS_RECV_PENDING 2
+
+#define IPI_MB_CHNL_TX 0 /* IPI mailbox TX channel */
+#define IPI_MB_CHNL_RX 1 /* IPI mailbox RX channel */
+
+/**
+ * struct zynqmp_ipi_mchan - Description of a Xilinx ZynqMP IPI mailbox channel
+ * @is_opened: indicate if the IPI channel is opened
+ * @req_buf: local to remote request buffer start address
+ * @resp_buf: local to remote response buffer start address
+ * @req_buf_size: request buffer size
+ * @resp_buf_size: response buffer size
+ * @rx_buf: receive buffer to pass received message to client
+ * @chan_type: channel type
+ */
+struct zynqmp_ipi_mchan {
+ int is_opened;
+ void __iomem *req_buf;
+ void __iomem *resp_buf;
+ void *rx_buf;
+ size_t req_buf_size;
+ size_t resp_buf_size;
+ unsigned int chan_type;
+};
+
+/**
+ * struct zynqmp_ipi_mbox - Description of a ZynqMP IPI mailbox
+ * platform data.
+ * @pdata: pointer to the IPI private data
+ * @dev:
[PATCH v5 0/2] Xilinx ZynqMP IPI Mailbox Controller Driver
Introduce mailbox controller driver for ZynqMP IPI(Inter-processor interrupt) IP core. As the device tree bindings have been updated. Do not have "Reviewed-by" nor "Acked-by" in the dt-bindings commit. v5: - fix check patch warning on write a paragraph to describe the kconfig symbol. v4: - make IPI mailboxes as subnodes to the IPI agent device node to properly describe the hardware. v3: - add NULL entry to of_device_id of IPI controller v2: - change SPDX-License-Identifier license text style in .c file - replace xlnx-ipi-ids with xlnx,ipi-ids Wendy Liang (2): mailbox: ZynqMP IPI mailbox controller dt-bindings: mailbox: Add Xilinx IPI Mailbox .../bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt | 128 drivers/mailbox/Kconfig| 9 + drivers/mailbox/Makefile | 2 + drivers/mailbox/zynqmp-ipi-mailbox.c | 762 + include/linux/mailbox/zynqmp-ipi-message.h | 24 + 5 files changed, 925 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt create mode 100644 drivers/mailbox/zynqmp-ipi-mailbox.c create mode 100644 include/linux/mailbox/zynqmp-ipi-message.h -- 2.7.4
[PATCH v5 2/2] dt-bindings: mailbox: Add Xilinx IPI Mailbox
Xilinx ZynqMP IPI(Inter Processor Interrupt) is a hardware block
in ZynqMP SoC used for the communication between various processor
systems.
Signed-off-by: Wendy Liang
---
.../bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt | 128 +
1 file changed, 128 insertions(+)
create mode 100644
Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt
diff --git
a/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt
b/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt
new file mode 100644
index 000..18fd7b4
--- /dev/null
+++ b/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt
@@ -0,0 +1,128 @@
+Xilinx IPI Mailbox Controller
+
+
+The Xilinx IPI(Inter Processor Interrupt) mailbox controller is to manage
+messaging between two Xilinx Zynq UltraScale+ MPSoC IPI agents. Each IPI
+agent owns registers used for notification and buffers for message.
+
+ +-+
+ | Xilinx ZynqMP IPI Controller|
+ +-+
++--+
+ATF| |
+ | |
+ | |
++--+ |
+ | |
+ | |
++--+
++--+
+| ++ ++ |
+Hardware| | IPI Agent | | IPI Buffers | |
+| | Registers | || |
+| || || |
+| ++ ++ |
+| |
+| Xilinx IPI Agent Block |
++--+
+
+
+Controller Device Node:
+===
+Required properties:
+
+IPI agent node:
+- compatible: Shall be: "xlnx,zynqmp-ipi-mailbox"
+- interrupt-parent:Phandle for the interrupt controller
+- interrupts: Interrupt information corresponding to the
+ interrupt-names property.
+- xlnx,ipi-id: local Xilinx IPI agent ID
+- #address-cells: number of address cells of internal IPI mailbox nodes
+- #size-cells: number of size cells of internal IPI mailbox nodes
+
+Internal IPI mailbox node:
+- reg: IPI buffers address ranges
+- reg-names: Names of the reg resources. It should have:
+ * local_request_region
+ - IPI request msg buffer written by local and read
+ by remote
+ * local_response_region
+ - IPI response msg buffer written by local and read
+ by remote
+ * remote_request_region
+ - IPI request msg buffer written by remote and read
+ by local
+ * remote_response_region
+ - IPI response msg buffer written by remote and read
+ by local
+- #mbox-cells: Shall be 1. It contains:
+ * tx(0) or rx(1) channel
+- xlnx,ipi-id: remote Xilinx IPI agent ID of which the mailbox is
+ connected to.
+
+Optional properties:
+
+- method: The method of accessing the IPI agent registers.
+ Permitted values are: "smc" and "hvc". Default is
+ "smc".
+
+Client Device Node:
+===
+Required properties:
+
+- mboxes: Standard property to specify a mailbox
+ (See ./mailbox.txt)
+- mbox-names: List of identifier strings for each mailbox
+ channel.
+
+Example:
+===
+ zynqmp_ipi {
+ compatible = "xlnx,zynqmp-ipi-mailbox";
+ interrupt-parent = <>;
+ interrupts = <0 29 4>;
+ xlnx,ipi-id = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* APU<->RPU0 IPI mailbox controller */
+ ipi_mailbox_rpu0: mailbox@ff90400 {
+ compatible = "xlnx,zynqmp-ipi-mailbox";
+ reg = <0xff990400 0x20>,
+ <0xff990420 0x20>,
+ <0xff990080 0x20>,
+ <0xff9900a0 0x20>
[PATCH v5 0/2] Xilinx ZynqMP IPI Mailbox Controller Driver
Introduce mailbox controller driver for ZynqMP IPI(Inter-processor interrupt) IP core. As the device tree bindings have been updated. Do not have "Reviewed-by" nor "Acked-by" in the dt-bindings commit. v5: - fix check patch warning on write a paragraph to describe the kconfig symbol. v4: - make IPI mailboxes as subnodes to the IPI agent device node to properly describe the hardware. v3: - add NULL entry to of_device_id of IPI controller v2: - change SPDX-License-Identifier license text style in .c file - replace xlnx-ipi-ids with xlnx,ipi-ids Wendy Liang (2): mailbox: ZynqMP IPI mailbox controller dt-bindings: mailbox: Add Xilinx IPI Mailbox .../bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt | 128 drivers/mailbox/Kconfig| 9 + drivers/mailbox/Makefile | 2 + drivers/mailbox/zynqmp-ipi-mailbox.c | 762 + include/linux/mailbox/zynqmp-ipi-message.h | 24 + 5 files changed, 925 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt create mode 100644 drivers/mailbox/zynqmp-ipi-mailbox.c create mode 100644 include/linux/mailbox/zynqmp-ipi-message.h -- 2.7.4
[PATCH v5 2/2] dt-bindings: mailbox: Add Xilinx IPI Mailbox
Xilinx ZynqMP IPI(Inter Processor Interrupt) is a hardware block
in ZynqMP SoC used for the communication between various processor
systems.
Signed-off-by: Wendy Liang
---
.../bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt | 128 +
1 file changed, 128 insertions(+)
create mode 100644
Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt
diff --git
a/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt
b/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt
new file mode 100644
index 000..18fd7b4
--- /dev/null
+++ b/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt
@@ -0,0 +1,128 @@
+Xilinx IPI Mailbox Controller
+
+
+The Xilinx IPI(Inter Processor Interrupt) mailbox controller is to manage
+messaging between two Xilinx Zynq UltraScale+ MPSoC IPI agents. Each IPI
+agent owns registers used for notification and buffers for message.
+
+ +-+
+ | Xilinx ZynqMP IPI Controller|
+ +-+
++--+
+ATF| |
+ | |
+ | |
++--+ |
+ | |
+ | |
++--+
++--+
+| ++ ++ |
+Hardware| | IPI Agent | | IPI Buffers | |
+| | Registers | || |
+| || || |
+| ++ ++ |
+| |
+| Xilinx IPI Agent Block |
++--+
+
+
+Controller Device Node:
+===
+Required properties:
+
+IPI agent node:
+- compatible: Shall be: "xlnx,zynqmp-ipi-mailbox"
+- interrupt-parent:Phandle for the interrupt controller
+- interrupts: Interrupt information corresponding to the
+ interrupt-names property.
+- xlnx,ipi-id: local Xilinx IPI agent ID
+- #address-cells: number of address cells of internal IPI mailbox nodes
+- #size-cells: number of size cells of internal IPI mailbox nodes
+
+Internal IPI mailbox node:
+- reg: IPI buffers address ranges
+- reg-names: Names of the reg resources. It should have:
+ * local_request_region
+ - IPI request msg buffer written by local and read
+ by remote
+ * local_response_region
+ - IPI response msg buffer written by local and read
+ by remote
+ * remote_request_region
+ - IPI request msg buffer written by remote and read
+ by local
+ * remote_response_region
+ - IPI response msg buffer written by remote and read
+ by local
+- #mbox-cells: Shall be 1. It contains:
+ * tx(0) or rx(1) channel
+- xlnx,ipi-id: remote Xilinx IPI agent ID of which the mailbox is
+ connected to.
+
+Optional properties:
+
+- method: The method of accessing the IPI agent registers.
+ Permitted values are: "smc" and "hvc". Default is
+ "smc".
+
+Client Device Node:
+===
+Required properties:
+
+- mboxes: Standard property to specify a mailbox
+ (See ./mailbox.txt)
+- mbox-names: List of identifier strings for each mailbox
+ channel.
+
+Example:
+===
+ zynqmp_ipi {
+ compatible = "xlnx,zynqmp-ipi-mailbox";
+ interrupt-parent = <>;
+ interrupts = <0 29 4>;
+ xlnx,ipi-id = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* APU<->RPU0 IPI mailbox controller */
+ ipi_mailbox_rpu0: mailbox@ff90400 {
+ compatible = "xlnx,zynqmp-ipi-mailbox";
+ reg = <0xff990400 0x20>,
+ <0xff990420 0x20>,
+ <0xff990080 0x20>,
+ <0xff9900a0 0x20>
Re: [PATCH v4 2/2] dt-bindings: mailbox: Add Xilinx IPI Mailbox
On Wed, Oct 10, 2018 at 2:59 AM Sudeep Holla wrote: > > On Wed, Oct 10, 2018 at 12:18:32AM -0700, Wendy Liang wrote: > > Xilinx ZynqMP IPI(Inter Processor Interrupt) is a hardware block > > in ZynqMP SoC used for the communication between various processor > > systems. > > > > Signed-off-by: Wendy Liang > > [...] > > > +Optional properties: > > + > > +- method: The method of accessing the IPI agent registers. > > + Permitted values are: "smc" and "hvc". Default is > > + "smc". > > You are mixing the hardware messaging based mailbox and the software > "smc/hvc" based mailbox together here. Please keep them separated. > IIUC smc/hvc based mailcox is used for "tx" or too keep it simple in > one direction and hardware based is used for "rx" or the other direction > for communication. > Hi Sudeep, Thanks for your comments. The IPI hardware block has both buffers and registers. The hardware block has dedicated buffers for each mailboxes, and thus, in the implementation, we directly access the buffers from IPI driver. However, the controller registers are shared between mailboxes in the hardware, as the ATF will also access the registers, we need to use SMC/HVC to access the registers (control or ISR). And the SMC/HVC here is for the register access. I am not clear on smc/hvc based mailbox is used for tx, and hardware based is used for "rx". As for both TX and RX, we need to write/read the registers (through SMC) and write/read the buffers provided by the IPI hardware block directly. Thanks, Wendy > You *should not* mix them as single unit. Also lots of other vendor need > SMC/HVC based mailbox. So make it generic and keep it separate. > > -- > Regards, > Sudeep
Re: [PATCH v4 2/2] dt-bindings: mailbox: Add Xilinx IPI Mailbox
On Wed, Oct 10, 2018 at 2:59 AM Sudeep Holla wrote: > > On Wed, Oct 10, 2018 at 12:18:32AM -0700, Wendy Liang wrote: > > Xilinx ZynqMP IPI(Inter Processor Interrupt) is a hardware block > > in ZynqMP SoC used for the communication between various processor > > systems. > > > > Signed-off-by: Wendy Liang > > [...] > > > +Optional properties: > > + > > +- method: The method of accessing the IPI agent registers. > > + Permitted values are: "smc" and "hvc". Default is > > + "smc". > > You are mixing the hardware messaging based mailbox and the software > "smc/hvc" based mailbox together here. Please keep them separated. > IIUC smc/hvc based mailcox is used for "tx" or too keep it simple in > one direction and hardware based is used for "rx" or the other direction > for communication. > Hi Sudeep, Thanks for your comments. The IPI hardware block has both buffers and registers. The hardware block has dedicated buffers for each mailboxes, and thus, in the implementation, we directly access the buffers from IPI driver. However, the controller registers are shared between mailboxes in the hardware, as the ATF will also access the registers, we need to use SMC/HVC to access the registers (control or ISR). And the SMC/HVC here is for the register access. I am not clear on smc/hvc based mailbox is used for tx, and hardware based is used for "rx". As for both TX and RX, we need to write/read the registers (through SMC) and write/read the buffers provided by the IPI hardware block directly. Thanks, Wendy > You *should not* mix them as single unit. Also lots of other vendor need > SMC/HVC based mailbox. So make it generic and keep it separate. > > -- > Regards, > Sudeep
[PATCH v4 2/2] dt-bindings: mailbox: Add Xilinx IPI Mailbox
Xilinx ZynqMP IPI(Inter Processor Interrupt) is a hardware block
in ZynqMP SoC used for the communication between various processor
systems.
Signed-off-by: Wendy Liang
---
Not put "Reviewed-by" as bindings have been updated since last review.
---
.../bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt | 128 +
1 file changed, 128 insertions(+)
create mode 100644
Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt
diff --git
a/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt
b/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt
new file mode 100644
index 000..146f2fb
--- /dev/null
+++ b/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt
@@ -0,0 +1,128 @@
+Xilinx IPI Mailbox Controller
+
+
+The Xilinx IPI(Inter Processor Interrupt) mailbox controller is to manage
+messaging between two Xilinx Zynq UltraScale+ MPSoC IPI agents. Each IPI
+agent owns registers used for notification and buffers for message.
+
+ +-+
+ | Xilinx ZynqMP IPI Controller|
+ +-+
++--+
+ATF| |
+ | |
+ | |
++--+ |
+ | |
+ | |
++--+
++--+
+| ++ ++ |
+Hardware| | IPI Agent | | IPI Buffers | |
+| | Registers | || |
+| || || |
+| ++ ++ |
+| |
+| Xilinx IPI Agent Block |
++--+
+
+
+Controller Device Node:
+===
+Required properties:
+
+IPI agent node:
+- compatible: Shall be: "xlnx,zynqmp-ipi-mailbox"
+- interrupt-parent:Phandle for the interrupt controller
+- interrupts: Interrupt information corresponding to the
+ interrupt-names property.
+- xlnx,ipi-id: local Xilinx IPI agent ID
+- #address-cells: number of address cells of internal IPI mailbox nodes
+- #size-cells: number of size cells of internal IPI mailbox nodes
+
+Internal IPI mailbox node:
+- reg: IPI buffers address ranges
+- reg-names: Names of the reg resources. It should have:
+ * local_request_region
+ - IPI request msg buffer written by local and read
+ by remote
+ * local_response_region
+ - IPI response msg buffer written by local and read
+ by remote
+ * remote_request_region
+ - IPI request msg buffer written by remote and read
+ by local
+ * remote_response_region
+ - IPI response msg buffer written by remote and read
+ by local
+- #mbox-cells: Shall be 1. It contains:
+ * tx(0) or rx(1) channel
+- xlnx,ipi-id: remote Xilinx IPI agent ID of which the mailbox is
+ connected to.
+
+Optional properties:
+
+- method: The method of accessing the IPI agent registers.
+ Permitted values are: "smc" and "hvc". Default is
+ "smc".
+
+Client Device Node:
+===
+Required properties:
+
+- mboxes: Standard property to specify a mailbox
+ (See ./mailbox.txt)
+- mbox-names: List of identifier strings for each mailbox
+ channel.
+
+Example:
+===
+ zynqmp_ipi {
+ compatible = "xlnx,zynqmp-ipi-mailbox";
+ interrupt-parent = <>;
+ interrupts = <0 29 4>;
+ xlnx,ipi-id = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* APU<->RPU0 IPI mailbox controller */
+ ipi_mailbox_rpu0: mailbox@ff90400 {
+ compatible = "xlnx,zynqmp-ipi-mailbox";
+ reg = <0xff990400 0x20>,
+ <0xff990420 0x20>,
+ <0xf
[PATCH v4 2/2] dt-bindings: mailbox: Add Xilinx IPI Mailbox
Xilinx ZynqMP IPI(Inter Processor Interrupt) is a hardware block
in ZynqMP SoC used for the communication between various processor
systems.
Signed-off-by: Wendy Liang
---
Not put "Reviewed-by" as bindings have been updated since last review.
---
.../bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt | 128 +
1 file changed, 128 insertions(+)
create mode 100644
Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt
diff --git
a/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt
b/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt
new file mode 100644
index 000..146f2fb
--- /dev/null
+++ b/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt
@@ -0,0 +1,128 @@
+Xilinx IPI Mailbox Controller
+
+
+The Xilinx IPI(Inter Processor Interrupt) mailbox controller is to manage
+messaging between two Xilinx Zynq UltraScale+ MPSoC IPI agents. Each IPI
+agent owns registers used for notification and buffers for message.
+
+ +-+
+ | Xilinx ZynqMP IPI Controller|
+ +-+
++--+
+ATF| |
+ | |
+ | |
++--+ |
+ | |
+ | |
++--+
++--+
+| ++ ++ |
+Hardware| | IPI Agent | | IPI Buffers | |
+| | Registers | || |
+| || || |
+| ++ ++ |
+| |
+| Xilinx IPI Agent Block |
++--+
+
+
+Controller Device Node:
+===
+Required properties:
+
+IPI agent node:
+- compatible: Shall be: "xlnx,zynqmp-ipi-mailbox"
+- interrupt-parent:Phandle for the interrupt controller
+- interrupts: Interrupt information corresponding to the
+ interrupt-names property.
+- xlnx,ipi-id: local Xilinx IPI agent ID
+- #address-cells: number of address cells of internal IPI mailbox nodes
+- #size-cells: number of size cells of internal IPI mailbox nodes
+
+Internal IPI mailbox node:
+- reg: IPI buffers address ranges
+- reg-names: Names of the reg resources. It should have:
+ * local_request_region
+ - IPI request msg buffer written by local and read
+ by remote
+ * local_response_region
+ - IPI response msg buffer written by local and read
+ by remote
+ * remote_request_region
+ - IPI request msg buffer written by remote and read
+ by local
+ * remote_response_region
+ - IPI response msg buffer written by remote and read
+ by local
+- #mbox-cells: Shall be 1. It contains:
+ * tx(0) or rx(1) channel
+- xlnx,ipi-id: remote Xilinx IPI agent ID of which the mailbox is
+ connected to.
+
+Optional properties:
+
+- method: The method of accessing the IPI agent registers.
+ Permitted values are: "smc" and "hvc". Default is
+ "smc".
+
+Client Device Node:
+===
+Required properties:
+
+- mboxes: Standard property to specify a mailbox
+ (See ./mailbox.txt)
+- mbox-names: List of identifier strings for each mailbox
+ channel.
+
+Example:
+===
+ zynqmp_ipi {
+ compatible = "xlnx,zynqmp-ipi-mailbox";
+ interrupt-parent = <>;
+ interrupts = <0 29 4>;
+ xlnx,ipi-id = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* APU<->RPU0 IPI mailbox controller */
+ ipi_mailbox_rpu0: mailbox@ff90400 {
+ compatible = "xlnx,zynqmp-ipi-mailbox";
+ reg = <0xff990400 0x20>,
+ <0xff990420 0x20>,
+ <0xf
[PATCH v4 1/2] mailbox: ZynqMP IPI mailbox controller
This patch is to introduce ZynqMP IPI mailbox controller driver
to use the ZynqMP IPI block as mailboxes.
Signed-off-by: Wendy Liang
---
drivers/mailbox/Kconfig| 8 +
drivers/mailbox/Makefile | 2 +
drivers/mailbox/zynqmp-ipi-mailbox.c | 762 +
include/linux/mailbox/zynqmp-ipi-message.h | 24 +
4 files changed, 796 insertions(+)
create mode 100644 drivers/mailbox/zynqmp-ipi-mailbox.c
create mode 100644 include/linux/mailbox/zynqmp-ipi-message.h
diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig
index 841c005..b1a006b 100644
--- a/drivers/mailbox/Kconfig
+++ b/drivers/mailbox/Kconfig
@@ -205,4 +205,12 @@ config MTK_CMDQ_MBOX
mailbox driver. The CMDQ is used to help read/write registers with
critical time limitation, such as updating display configuration
during the vblank.
+
+config ZYNQMP_IPI_MBOX
+ tristate "Xilinx ZynqMP IPI Mailbox"
+ depends on ARCH_ZYNQMP && OF
+ help
+ Mailbox implementation for Xilinx ZynqMP IPI. It is used to send
+ notification or short message between processors with Xilinx
+ ZynqMP IPI.
endif
diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile
index c818b5d..bb3d604 100644
--- a/drivers/mailbox/Makefile
+++ b/drivers/mailbox/Makefile
@@ -44,3 +44,5 @@ obj-$(CONFIG_TEGRA_HSP_MBOX) += tegra-hsp.o
obj-$(CONFIG_STM32_IPCC) += stm32-ipcc.o
obj-$(CONFIG_MTK_CMDQ_MBOX)+= mtk-cmdq-mailbox.o
+
+obj-$(CONFIG_ZYNQMP_IPI_MBOX) += zynqmp-ipi-mailbox.o
diff --git a/drivers/mailbox/zynqmp-ipi-mailbox.c
b/drivers/mailbox/zynqmp-ipi-mailbox.c
new file mode 100644
index 000..6a2e0fc
--- /dev/null
+++ b/drivers/mailbox/zynqmp-ipi-mailbox.c
@@ -0,0 +1,762 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Inter Processor Interrupt(IPI) Mailbox Driver
+ *
+ * Copyright (C) 2018 Xilinx Inc.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* IPI agent ID any */
+#define IPI_ID_ANY 0xFFUL
+
+/* indicate if ZynqMP IPI mailbox driver uses SMC calls or HVC calls */
+#define USE_SMC 0
+#define USE_HVC 1
+
+/* Default IPI SMC function IDs */
+#define SMC_IPI_MAILBOX_OPEN0x82001000U
+#define SMC_IPI_MAILBOX_RELEASE 0x82001001U
+#define SMC_IPI_MAILBOX_STATUS_ENQUIRY 0x82001002U
+#define SMC_IPI_MAILBOX_NOTIFY 0x82001003U
+#define SMC_IPI_MAILBOX_ACK 0x82001004U
+#define SMC_IPI_MAILBOX_ENABLE_IRQ 0x82001005U
+#define SMC_IPI_MAILBOX_DISABLE_IRQ 0x82001006U
+
+/* IPI SMC Macros */
+#define IPI_SMC_OPEN_IRQ_MASK 0x0001UL /* IRQ enable bit in IPI
+ * open SMC call
+ */
+#define IPI_SMC_NOTIFY_BLOCK_MASK 0x0001UL /* Flag to indicate if
+ * IPI notification needs
+ * to be blocking.
+ */
+#define IPI_SMC_ENQUIRY_DIRQ_MASK 0x0001UL /* Flag to indicate if
+ * notification interrupt
+ * to be disabled.
+ */
+#define IPI_SMC_ACK_EIRQ_MASK 0x0001UL /* Flag to indicate if
+ * notification interrupt
+ * to be enabled.
+ */
+
+/* IPI mailbox status */
+#define IPI_MB_STATUS_IDLE 0
+#define IPI_MB_STATUS_SEND_PENDING 1
+#define IPI_MB_STATUS_RECV_PENDING 2
+
+#define IPI_MB_CHNL_TX 0 /* IPI mailbox TX channel */
+#define IPI_MB_CHNL_RX 1 /* IPI mailbox RX channel */
+
+/**
+ * struct zynqmp_ipi_mchan - Description of a Xilinx ZynqMP IPI mailbox channel
+ * @is_opened: indicate if the IPI channel is opened
+ * @req_buf: local to remote request buffer start address
+ * @resp_buf: local to remote response buffer start address
+ * @req_buf_size: request buffer size
+ * @resp_buf_size: response buffer size
+ * @rx_buf: receive buffer to pass received message to client
+ * @chan_type: channel type
+ */
+struct zynqmp_ipi_mchan {
+ int is_opened;
+ void __iomem *req_buf;
+ void __iomem *resp_buf;
+ void *rx_buf;
+ size_t req_buf_size;
+ size_t resp_buf_size;
+ unsigned int chan_type;
+};
+
+/**
+ * struct zynqmp_ipi_mbox - Description of a ZynqMP IPI mailbox
+ * platform data.
+ * @pdata: pointer to the IPI private data
+ * @dev: device pointer corresponding to the Xilinx ZynqMP
+ *IPI mail
[PATCH v4 1/2] mailbox: ZynqMP IPI mailbox controller
This patch is to introduce ZynqMP IPI mailbox controller driver
to use the ZynqMP IPI block as mailboxes.
Signed-off-by: Wendy Liang
---
drivers/mailbox/Kconfig| 8 +
drivers/mailbox/Makefile | 2 +
drivers/mailbox/zynqmp-ipi-mailbox.c | 762 +
include/linux/mailbox/zynqmp-ipi-message.h | 24 +
4 files changed, 796 insertions(+)
create mode 100644 drivers/mailbox/zynqmp-ipi-mailbox.c
create mode 100644 include/linux/mailbox/zynqmp-ipi-message.h
diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig
index 841c005..b1a006b 100644
--- a/drivers/mailbox/Kconfig
+++ b/drivers/mailbox/Kconfig
@@ -205,4 +205,12 @@ config MTK_CMDQ_MBOX
mailbox driver. The CMDQ is used to help read/write registers with
critical time limitation, such as updating display configuration
during the vblank.
+
+config ZYNQMP_IPI_MBOX
+ tristate "Xilinx ZynqMP IPI Mailbox"
+ depends on ARCH_ZYNQMP && OF
+ help
+ Mailbox implementation for Xilinx ZynqMP IPI. It is used to send
+ notification or short message between processors with Xilinx
+ ZynqMP IPI.
endif
diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile
index c818b5d..bb3d604 100644
--- a/drivers/mailbox/Makefile
+++ b/drivers/mailbox/Makefile
@@ -44,3 +44,5 @@ obj-$(CONFIG_TEGRA_HSP_MBOX) += tegra-hsp.o
obj-$(CONFIG_STM32_IPCC) += stm32-ipcc.o
obj-$(CONFIG_MTK_CMDQ_MBOX)+= mtk-cmdq-mailbox.o
+
+obj-$(CONFIG_ZYNQMP_IPI_MBOX) += zynqmp-ipi-mailbox.o
diff --git a/drivers/mailbox/zynqmp-ipi-mailbox.c
b/drivers/mailbox/zynqmp-ipi-mailbox.c
new file mode 100644
index 000..6a2e0fc
--- /dev/null
+++ b/drivers/mailbox/zynqmp-ipi-mailbox.c
@@ -0,0 +1,762 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Inter Processor Interrupt(IPI) Mailbox Driver
+ *
+ * Copyright (C) 2018 Xilinx Inc.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* IPI agent ID any */
+#define IPI_ID_ANY 0xFFUL
+
+/* indicate if ZynqMP IPI mailbox driver uses SMC calls or HVC calls */
+#define USE_SMC 0
+#define USE_HVC 1
+
+/* Default IPI SMC function IDs */
+#define SMC_IPI_MAILBOX_OPEN0x82001000U
+#define SMC_IPI_MAILBOX_RELEASE 0x82001001U
+#define SMC_IPI_MAILBOX_STATUS_ENQUIRY 0x82001002U
+#define SMC_IPI_MAILBOX_NOTIFY 0x82001003U
+#define SMC_IPI_MAILBOX_ACK 0x82001004U
+#define SMC_IPI_MAILBOX_ENABLE_IRQ 0x82001005U
+#define SMC_IPI_MAILBOX_DISABLE_IRQ 0x82001006U
+
+/* IPI SMC Macros */
+#define IPI_SMC_OPEN_IRQ_MASK 0x0001UL /* IRQ enable bit in IPI
+ * open SMC call
+ */
+#define IPI_SMC_NOTIFY_BLOCK_MASK 0x0001UL /* Flag to indicate if
+ * IPI notification needs
+ * to be blocking.
+ */
+#define IPI_SMC_ENQUIRY_DIRQ_MASK 0x0001UL /* Flag to indicate if
+ * notification interrupt
+ * to be disabled.
+ */
+#define IPI_SMC_ACK_EIRQ_MASK 0x0001UL /* Flag to indicate if
+ * notification interrupt
+ * to be enabled.
+ */
+
+/* IPI mailbox status */
+#define IPI_MB_STATUS_IDLE 0
+#define IPI_MB_STATUS_SEND_PENDING 1
+#define IPI_MB_STATUS_RECV_PENDING 2
+
+#define IPI_MB_CHNL_TX 0 /* IPI mailbox TX channel */
+#define IPI_MB_CHNL_RX 1 /* IPI mailbox RX channel */
+
+/**
+ * struct zynqmp_ipi_mchan - Description of a Xilinx ZynqMP IPI mailbox channel
+ * @is_opened: indicate if the IPI channel is opened
+ * @req_buf: local to remote request buffer start address
+ * @resp_buf: local to remote response buffer start address
+ * @req_buf_size: request buffer size
+ * @resp_buf_size: response buffer size
+ * @rx_buf: receive buffer to pass received message to client
+ * @chan_type: channel type
+ */
+struct zynqmp_ipi_mchan {
+ int is_opened;
+ void __iomem *req_buf;
+ void __iomem *resp_buf;
+ void *rx_buf;
+ size_t req_buf_size;
+ size_t resp_buf_size;
+ unsigned int chan_type;
+};
+
+/**
+ * struct zynqmp_ipi_mbox - Description of a ZynqMP IPI mailbox
+ * platform data.
+ * @pdata: pointer to the IPI private data
+ * @dev: device pointer corresponding to the Xilinx ZynqMP
+ *IPI mail
[PATCH v4 0/2] Xilinx ZynqMP IPI Mailbox Controller Driver
Introduce mailbox controller driver for ZynqMP IPI(Inter-processor interrupt) IP core. As the device tree bindings have been updated. Do not have "Reviewed-by" nor "Acked-by" in the dt-bindings commit. v4: - make IPI mailboxes as subnodes to the IPI agent device node to properly describe the hardware. v3: - add NULL entry to of_device_id of IPI controller v2: - change SPDX-License-Identifier license text style in .c file - replace xlnx-ipi-ids with xlnx,ipi-ids Wendy Liang (2): mailbox: ZynqMP IPI mailbox controller dt-bindings: mailbox: Add Xilinx IPI Mailbox .../bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt | 128 drivers/mailbox/Kconfig| 8 + drivers/mailbox/Makefile | 2 + drivers/mailbox/zynqmp-ipi-mailbox.c | 762 + include/linux/mailbox/zynqmp-ipi-message.h | 24 + 5 files changed, 924 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt create mode 100644 drivers/mailbox/zynqmp-ipi-mailbox.c create mode 100644 include/linux/mailbox/zynqmp-ipi-message.h -- 2.7.4
[PATCH v4 0/2] Xilinx ZynqMP IPI Mailbox Controller Driver
Introduce mailbox controller driver for ZynqMP IPI(Inter-processor interrupt) IP core. As the device tree bindings have been updated. Do not have "Reviewed-by" nor "Acked-by" in the dt-bindings commit. v4: - make IPI mailboxes as subnodes to the IPI agent device node to properly describe the hardware. v3: - add NULL entry to of_device_id of IPI controller v2: - change SPDX-License-Identifier license text style in .c file - replace xlnx-ipi-ids with xlnx,ipi-ids Wendy Liang (2): mailbox: ZynqMP IPI mailbox controller dt-bindings: mailbox: Add Xilinx IPI Mailbox .../bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt | 128 drivers/mailbox/Kconfig| 8 + drivers/mailbox/Makefile | 2 + drivers/mailbox/zynqmp-ipi-mailbox.c | 762 + include/linux/mailbox/zynqmp-ipi-message.h | 24 + 5 files changed, 924 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt create mode 100644 drivers/mailbox/zynqmp-ipi-mailbox.c create mode 100644 include/linux/mailbox/zynqmp-ipi-message.h -- 2.7.4
Re: [PATCH v3 2/2] dt-bindings: mailbox: Add Xilinx IPI Mailbox
On Thu, Jan 4, 2018 at 3:53 PM Wendy Liang wrote:
>
> Xilinx ZynqMP IPI(Inter Processor Interrupt) is a hardware block
> in ZynqMP SoC used for the communication between various processor
> systems.
>
> Signed-off-by: Wendy Liang
> ---
> .../bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt | 104
> +
> 1 file changed, 104 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt
>
> diff --git
> a/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt
> b/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt
> new file mode 100644
> index 000..5e270a3
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt
> @@ -0,0 +1,104 @@
> +Xilinx IPI Mailbox Controller
> +
> +
> +The Xilinx IPI(Inter Processor Interrupt) mailbox controller is to manage
> +messaging between two Xilinx Zynq UltraScale+ MPSoC IPI agents. Each IPI
> +agent owns registers used for notification and buffers for message.
> +
> + +-+
> + | Xilinx ZynqMP IPI Controller|
> + +-+
> ++--+
> +ATF| |
> + | |
> + | |
> ++--+ |
> + | |
> + | |
> ++--+
> ++--+
> +| ++ ++ |
> +Hardware| | IPI Agent | | IPI Buffers | |
> +| | Registers | || |
> +| || || |
> +| ++ ++ |
> +| |
> +| Xilinx IPI Agent Block |
> ++--+
> +
> +
> +Controller Device Node:
> +===
> +Required properties:
> +
> +- compatible: Shall be: "xlnx,zynqmp-ipi-mailbox"
> +- reg: IPI buffers address ranges
> +- reg-names: Names of the reg resources. It should have:
> + * local_request_region
> + - IPI request msg buffer written by local and read
> + by remote
> + * local_response_region
> + - IPI response msg buffer written by local and read
> + by remote
> + * remote_request_region
> + - IPI request msg buffer written by remote and read
> + by local
> + * remote_response_region
> + - IPI response msg buffer written by remote and read
> + by local
> +- #mbox-cells: Shall be 1. It contains:
> + * tx(0) or rx(1) channel
> +- xlnx,ipi-ids:Xilinx IPI agent IDs of the two peers of the
> + Xilinx IPI communication channel.
> +- interrupt-parent:Phandle for the interrupt controller
> +- interrupts: Interrupt information corresponding to the
> + interrupt-names property.
> +
> +Optional properties:
> +
> +- method: The method of accessing the IPI agent registers.
> + Permitted values are: "smc" and "hvc". Default is
> + "smc".
> +
> +Example:
> +===
> + /* APU<->RPU0 IPI mailbox controller */
> + ipi_mailbox_rpu0: mailbox@ff90400 {
> + compatible = "xlnx,zynqmp-ipi-mailbox";
> + reg = <0x0 0xff990400 0x0 0x20>,
> + <0x0 0xff990420 0x0 0x20>,
> + <0x0 0xff990080 0x0 0x20>,
> + <0x0 0xff9900a0 0x0 0x20>;
> + reg-names = "local_request_region", "local_response_region",
> + "remote_request_region", "remote_response_region";
> + #mbox-cells = <1>;
> + xlnx-ipi-ids = <0 1>;
> + interrupt-parent = <>;
> +
Re: [PATCH v3 2/2] dt-bindings: mailbox: Add Xilinx IPI Mailbox
On Thu, Jan 4, 2018 at 3:53 PM Wendy Liang wrote:
>
> Xilinx ZynqMP IPI(Inter Processor Interrupt) is a hardware block
> in ZynqMP SoC used for the communication between various processor
> systems.
>
> Signed-off-by: Wendy Liang
> ---
> .../bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt | 104
> +
> 1 file changed, 104 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt
>
> diff --git
> a/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt
> b/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt
> new file mode 100644
> index 000..5e270a3
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt
> @@ -0,0 +1,104 @@
> +Xilinx IPI Mailbox Controller
> +
> +
> +The Xilinx IPI(Inter Processor Interrupt) mailbox controller is to manage
> +messaging between two Xilinx Zynq UltraScale+ MPSoC IPI agents. Each IPI
> +agent owns registers used for notification and buffers for message.
> +
> + +-+
> + | Xilinx ZynqMP IPI Controller|
> + +-+
> ++--+
> +ATF| |
> + | |
> + | |
> ++--+ |
> + | |
> + | |
> ++--+
> ++--+
> +| ++ ++ |
> +Hardware| | IPI Agent | | IPI Buffers | |
> +| | Registers | || |
> +| || || |
> +| ++ ++ |
> +| |
> +| Xilinx IPI Agent Block |
> ++--+
> +
> +
> +Controller Device Node:
> +===
> +Required properties:
> +
> +- compatible: Shall be: "xlnx,zynqmp-ipi-mailbox"
> +- reg: IPI buffers address ranges
> +- reg-names: Names of the reg resources. It should have:
> + * local_request_region
> + - IPI request msg buffer written by local and read
> + by remote
> + * local_response_region
> + - IPI response msg buffer written by local and read
> + by remote
> + * remote_request_region
> + - IPI request msg buffer written by remote and read
> + by local
> + * remote_response_region
> + - IPI response msg buffer written by remote and read
> + by local
> +- #mbox-cells: Shall be 1. It contains:
> + * tx(0) or rx(1) channel
> +- xlnx,ipi-ids:Xilinx IPI agent IDs of the two peers of the
> + Xilinx IPI communication channel.
> +- interrupt-parent:Phandle for the interrupt controller
> +- interrupts: Interrupt information corresponding to the
> + interrupt-names property.
> +
> +Optional properties:
> +
> +- method: The method of accessing the IPI agent registers.
> + Permitted values are: "smc" and "hvc". Default is
> + "smc".
> +
> +Example:
> +===
> + /* APU<->RPU0 IPI mailbox controller */
> + ipi_mailbox_rpu0: mailbox@ff90400 {
> + compatible = "xlnx,zynqmp-ipi-mailbox";
> + reg = <0x0 0xff990400 0x0 0x20>,
> + <0x0 0xff990420 0x0 0x20>,
> + <0x0 0xff990080 0x0 0x20>,
> + <0x0 0xff9900a0 0x0 0x20>;
> + reg-names = "local_request_region", "local_response_region",
> + "remote_request_region", "remote_response_region";
> + #mbox-cells = <1>;
> + xlnx-ipi-ids = <0 1>;
> + interrupt-parent = <>;
> +
Re: [PATCH v4 13/17] remoteproc: create vdev subdevice with specific dma memory pool
Hi Loic,
On Thu, Sep 27, 2018 at 12:22 PM Loic PALLARDY wrote:
>
> Hi Wendy
>
> > -Original Message-
> > From: Wendy Liang
> > Sent: Thursday, September 27, 2018 7:17 PM
> > To: Loic PALLARDY
> > Cc: Bjorn Andersson ; Ohad Ben-Cohen
> > ; linux-remotep...@vger.kernel.org; Linux Kernel
> > Mailing List ; Arnaud POULIQUEN
> > ; benjamin.gaign...@linaro.org; Suman Anna
> >
> > Subject: Re: [PATCH v4 13/17] remoteproc: create vdev subdevice with
> > specific dma memory pool
> >
> > On Fri, Jul 27, 2018 at 6:16 AM Loic Pallardy wrote:
> > >
> > > This patch creates a dedicated vdev subdevice for each vdev declared
> > > in firmware resource table and associates carveout named "vdev%dbuffer"
> > > (with %d vdev index in resource table) if any as dma coherent memory
> > pool.
> > >
> > > Then vdev subdevice is used as parent for virtio device.
> > >
> > > Signed-off-by: Loic Pallardy
> > > ---
> > > drivers/remoteproc/remoteproc_core.c | 35
> > +++---
> > > drivers/remoteproc/remoteproc_internal.h | 1 +
> > > drivers/remoteproc/remoteproc_virtio.c | 42
> > +++-
> > > include/linux/remoteproc.h | 1 +
> > > 4 files changed, 75 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/drivers/remoteproc/remoteproc_core.c
> > b/drivers/remoteproc/remoteproc_core.c
> > > index 4edc6f0..adcc66e 100644
> > > --- a/drivers/remoteproc/remoteproc_core.c
> > > +++ b/drivers/remoteproc/remoteproc_core.c
> > > @@ -39,6 +39,7 @@
> > > #include
> > > #include
> > > #include
> > > +#include
> > > #include
> > > #include
> > > #include
> > > @@ -145,7 +146,7 @@ static void rproc_disable_iommu(struct rproc
> > *rproc)
> > > iommu_domain_free(domain);
> > > }
> > >
> > > -static phys_addr_t rproc_va_to_pa(void *cpu_addr)
> > > +phys_addr_t rproc_va_to_pa(void *cpu_addr)
> > > {
> > > /*
> > > * Return physical address according to virtual address location
> > > @@ -160,6 +161,7 @@ static phys_addr_t rproc_va_to_pa(void
> > *cpu_addr)
> > > WARN_ON(!virt_addr_valid(cpu_addr));
> > > return virt_to_phys(cpu_addr);
> > > }
> > > +EXPORT_SYMBOL(rproc_va_to_pa);
> > >
> > > /**
> > > * rproc_da_to_va() - lookup the kernel virtual address for a remoteproc
> > address
> > > @@ -423,6 +425,20 @@ static void rproc_vdev_do_stop(struct
> > rproc_subdev *subdev, bool crashed)
> > > }
> > >
> > > /**
> > > + * rproc_rvdev_release() - release the existence of a rvdev
> > > + *
> > > + * @dev: the subdevice's dev
> > > + */
> > > +static void rproc_rvdev_release(struct device *dev)
> > > +{
> > > + struct rproc_vdev *rvdev = container_of(dev, struct rproc_vdev,
> > > dev);
> > > +
> > > + of_reserved_mem_device_release(dev);
> > > +
> > > + kfree(rvdev);
> > > +}
> > > +
> > > +/**
> > > * rproc_handle_vdev() - handle a vdev fw resource
> > > * @rproc: the remote processor
> > > * @rsc: the vring resource descriptor
> > > @@ -455,6 +471,7 @@ static int rproc_handle_vdev(struct rproc *rproc,
> > struct fw_rsc_vdev *rsc,
> > > struct device *dev = >dev;
> > > struct rproc_vdev *rvdev;
> > > int i, ret;
> > > + char name[16];
> > >
> > > /* make sure resource isn't truncated */
> > > if (sizeof(*rsc) + rsc->num_of_vrings * sizeof(struct
> > fw_rsc_vdev_vring)
> > > @@ -488,6 +505,18 @@ static int rproc_handle_vdev(struct rproc *rproc,
> > struct fw_rsc_vdev *rsc,
> > > rvdev->rproc = rproc;
> > > rvdev->index = rproc->nb_vdev++;
> > >
> > > + /* Initialise vdev subdevice */
> > > + snprintf(name, sizeof(name), "vdev%dbuffer", rvdev->index);
> > > + rvdev->dev.parent = rproc->dev.parent;
> > > + rvdev->dev.release = rproc_rvdev_release;
> > > + dev_set_name(>dev, "%s#%s", dev_name(rvdev-
> > >dev.parent), name);
> > > + dev_set_drvdata(>dev, rvdev);
> > > + dma_set_coherent_mask(>dev, DMA_BIT_M
Re: [PATCH v4 13/17] remoteproc: create vdev subdevice with specific dma memory pool
Hi Loic,
On Thu, Sep 27, 2018 at 12:22 PM Loic PALLARDY wrote:
>
> Hi Wendy
>
> > -Original Message-
> > From: Wendy Liang
> > Sent: Thursday, September 27, 2018 7:17 PM
> > To: Loic PALLARDY
> > Cc: Bjorn Andersson ; Ohad Ben-Cohen
> > ; linux-remotep...@vger.kernel.org; Linux Kernel
> > Mailing List ; Arnaud POULIQUEN
> > ; benjamin.gaign...@linaro.org; Suman Anna
> >
> > Subject: Re: [PATCH v4 13/17] remoteproc: create vdev subdevice with
> > specific dma memory pool
> >
> > On Fri, Jul 27, 2018 at 6:16 AM Loic Pallardy wrote:
> > >
> > > This patch creates a dedicated vdev subdevice for each vdev declared
> > > in firmware resource table and associates carveout named "vdev%dbuffer"
> > > (with %d vdev index in resource table) if any as dma coherent memory
> > pool.
> > >
> > > Then vdev subdevice is used as parent for virtio device.
> > >
> > > Signed-off-by: Loic Pallardy
> > > ---
> > > drivers/remoteproc/remoteproc_core.c | 35
> > +++---
> > > drivers/remoteproc/remoteproc_internal.h | 1 +
> > > drivers/remoteproc/remoteproc_virtio.c | 42
> > +++-
> > > include/linux/remoteproc.h | 1 +
> > > 4 files changed, 75 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/drivers/remoteproc/remoteproc_core.c
> > b/drivers/remoteproc/remoteproc_core.c
> > > index 4edc6f0..adcc66e 100644
> > > --- a/drivers/remoteproc/remoteproc_core.c
> > > +++ b/drivers/remoteproc/remoteproc_core.c
> > > @@ -39,6 +39,7 @@
> > > #include
> > > #include
> > > #include
> > > +#include
> > > #include
> > > #include
> > > #include
> > > @@ -145,7 +146,7 @@ static void rproc_disable_iommu(struct rproc
> > *rproc)
> > > iommu_domain_free(domain);
> > > }
> > >
> > > -static phys_addr_t rproc_va_to_pa(void *cpu_addr)
> > > +phys_addr_t rproc_va_to_pa(void *cpu_addr)
> > > {
> > > /*
> > > * Return physical address according to virtual address location
> > > @@ -160,6 +161,7 @@ static phys_addr_t rproc_va_to_pa(void
> > *cpu_addr)
> > > WARN_ON(!virt_addr_valid(cpu_addr));
> > > return virt_to_phys(cpu_addr);
> > > }
> > > +EXPORT_SYMBOL(rproc_va_to_pa);
> > >
> > > /**
> > > * rproc_da_to_va() - lookup the kernel virtual address for a remoteproc
> > address
> > > @@ -423,6 +425,20 @@ static void rproc_vdev_do_stop(struct
> > rproc_subdev *subdev, bool crashed)
> > > }
> > >
> > > /**
> > > + * rproc_rvdev_release() - release the existence of a rvdev
> > > + *
> > > + * @dev: the subdevice's dev
> > > + */
> > > +static void rproc_rvdev_release(struct device *dev)
> > > +{
> > > + struct rproc_vdev *rvdev = container_of(dev, struct rproc_vdev,
> > > dev);
> > > +
> > > + of_reserved_mem_device_release(dev);
> > > +
> > > + kfree(rvdev);
> > > +}
> > > +
> > > +/**
> > > * rproc_handle_vdev() - handle a vdev fw resource
> > > * @rproc: the remote processor
> > > * @rsc: the vring resource descriptor
> > > @@ -455,6 +471,7 @@ static int rproc_handle_vdev(struct rproc *rproc,
> > struct fw_rsc_vdev *rsc,
> > > struct device *dev = >dev;
> > > struct rproc_vdev *rvdev;
> > > int i, ret;
> > > + char name[16];
> > >
> > > /* make sure resource isn't truncated */
> > > if (sizeof(*rsc) + rsc->num_of_vrings * sizeof(struct
> > fw_rsc_vdev_vring)
> > > @@ -488,6 +505,18 @@ static int rproc_handle_vdev(struct rproc *rproc,
> > struct fw_rsc_vdev *rsc,
> > > rvdev->rproc = rproc;
> > > rvdev->index = rproc->nb_vdev++;
> > >
> > > + /* Initialise vdev subdevice */
> > > + snprintf(name, sizeof(name), "vdev%dbuffer", rvdev->index);
> > > + rvdev->dev.parent = rproc->dev.parent;
> > > + rvdev->dev.release = rproc_rvdev_release;
> > > + dev_set_name(>dev, "%s#%s", dev_name(rvdev-
> > >dev.parent), name);
> > > + dev_set_drvdata(>dev, rvdev);
> > > + dma_set_coherent_mask(>dev, DMA_BIT_M
Re: [PATCH v4 13/17] remoteproc: create vdev subdevice with specific dma memory pool
On Fri, Jul 27, 2018 at 6:16 AM Loic Pallardy wrote:
>
> This patch creates a dedicated vdev subdevice for each vdev declared
> in firmware resource table and associates carveout named "vdev%dbuffer"
> (with %d vdev index in resource table) if any as dma coherent memory pool.
>
> Then vdev subdevice is used as parent for virtio device.
>
> Signed-off-by: Loic Pallardy
> ---
> drivers/remoteproc/remoteproc_core.c | 35 +++---
> drivers/remoteproc/remoteproc_internal.h | 1 +
> drivers/remoteproc/remoteproc_virtio.c | 42
> +++-
> include/linux/remoteproc.h | 1 +
> 4 files changed, 75 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/remoteproc/remoteproc_core.c
> b/drivers/remoteproc/remoteproc_core.c
> index 4edc6f0..adcc66e 100644
> --- a/drivers/remoteproc/remoteproc_core.c
> +++ b/drivers/remoteproc/remoteproc_core.c
> @@ -39,6 +39,7 @@
> #include
> #include
> #include
> +#include
> #include
> #include
> #include
> @@ -145,7 +146,7 @@ static void rproc_disable_iommu(struct rproc *rproc)
> iommu_domain_free(domain);
> }
>
> -static phys_addr_t rproc_va_to_pa(void *cpu_addr)
> +phys_addr_t rproc_va_to_pa(void *cpu_addr)
> {
> /*
> * Return physical address according to virtual address location
> @@ -160,6 +161,7 @@ static phys_addr_t rproc_va_to_pa(void *cpu_addr)
> WARN_ON(!virt_addr_valid(cpu_addr));
> return virt_to_phys(cpu_addr);
> }
> +EXPORT_SYMBOL(rproc_va_to_pa);
>
> /**
> * rproc_da_to_va() - lookup the kernel virtual address for a remoteproc
> address
> @@ -423,6 +425,20 @@ static void rproc_vdev_do_stop(struct rproc_subdev
> *subdev, bool crashed)
> }
>
> /**
> + * rproc_rvdev_release() - release the existence of a rvdev
> + *
> + * @dev: the subdevice's dev
> + */
> +static void rproc_rvdev_release(struct device *dev)
> +{
> + struct rproc_vdev *rvdev = container_of(dev, struct rproc_vdev, dev);
> +
> + of_reserved_mem_device_release(dev);
> +
> + kfree(rvdev);
> +}
> +
> +/**
> * rproc_handle_vdev() - handle a vdev fw resource
> * @rproc: the remote processor
> * @rsc: the vring resource descriptor
> @@ -455,6 +471,7 @@ static int rproc_handle_vdev(struct rproc *rproc, struct
> fw_rsc_vdev *rsc,
> struct device *dev = >dev;
> struct rproc_vdev *rvdev;
> int i, ret;
> + char name[16];
>
> /* make sure resource isn't truncated */
> if (sizeof(*rsc) + rsc->num_of_vrings * sizeof(struct
> fw_rsc_vdev_vring)
> @@ -488,6 +505,18 @@ static int rproc_handle_vdev(struct rproc *rproc, struct
> fw_rsc_vdev *rsc,
> rvdev->rproc = rproc;
> rvdev->index = rproc->nb_vdev++;
>
> + /* Initialise vdev subdevice */
> + snprintf(name, sizeof(name), "vdev%dbuffer", rvdev->index);
> + rvdev->dev.parent = rproc->dev.parent;
> + rvdev->dev.release = rproc_rvdev_release;
> + dev_set_name(>dev, "%s#%s", dev_name(rvdev->dev.parent), name);
> + dev_set_drvdata(>dev, rvdev);
> + dma_set_coherent_mask(>dev, DMA_BIT_MASK(32));
I tried the latest kernel, this function will not set the DMA coherent mask as
dma_supported() of the >dev will return false.
As this is a device created at run time, should it be force to support DMA?
should it directly set the dma_coherent_mask?
> +
> + ret = device_register(>dev);
> + if (ret)
> + goto free_rvdev;
> +
> /* parse the vrings */
> for (i = 0; i < rsc->num_of_vrings; i++) {
> ret = rproc_parse_vring(rvdev, rsc, i);
> @@ -518,7 +547,7 @@ static int rproc_handle_vdev(struct rproc *rproc, struct
> fw_rsc_vdev *rsc,
> for (i--; i >= 0; i--)
> rproc_free_vring(>vring[i]);
> free_rvdev:
> - kfree(rvdev);
> + device_unregister(>dev);
> return ret;
> }
>
> @@ -536,7 +565,7 @@ void rproc_vdev_release(struct kref *ref)
>
> rproc_remove_subdev(rproc, >subdev);
> list_del(>node);
> - kfree(rvdev);
> + device_unregister(>dev);
> }
>
> /**
> diff --git a/drivers/remoteproc/remoteproc_internal.h
> b/drivers/remoteproc/remoteproc_internal.h
> index f6cad24..bfeacfd 100644
> --- a/drivers/remoteproc/remoteproc_internal.h
> +++ b/drivers/remoteproc/remoteproc_internal.h
> @@ -52,6 +52,7 @@ struct dentry *rproc_create_trace_file(const char *name,
> struct rproc *rproc,
> int rproc_alloc_vring(struct rproc_vdev *rvdev, int i);
>
> void *rproc_da_to_va(struct rproc *rproc, u64 da, int len);
> +phys_addr_t rproc_va_to_pa(void *cpu_addr);
> int rproc_trigger_recovery(struct rproc *rproc);
>
> int rproc_elf_sanity_check(struct rproc *rproc, const struct firmware *fw);
> diff --git a/drivers/remoteproc/remoteproc_virtio.c
> b/drivers/remoteproc/remoteproc_virtio.c
> index de21f62..9ee63c0 100644
> --- a/drivers/remoteproc/remoteproc_virtio.c
> +++ b/drivers/remoteproc/remoteproc_virtio.c
> @@
Re: [PATCH v4 13/17] remoteproc: create vdev subdevice with specific dma memory pool
On Fri, Jul 27, 2018 at 6:16 AM Loic Pallardy wrote:
>
> This patch creates a dedicated vdev subdevice for each vdev declared
> in firmware resource table and associates carveout named "vdev%dbuffer"
> (with %d vdev index in resource table) if any as dma coherent memory pool.
>
> Then vdev subdevice is used as parent for virtio device.
>
> Signed-off-by: Loic Pallardy
> ---
> drivers/remoteproc/remoteproc_core.c | 35 +++---
> drivers/remoteproc/remoteproc_internal.h | 1 +
> drivers/remoteproc/remoteproc_virtio.c | 42
> +++-
> include/linux/remoteproc.h | 1 +
> 4 files changed, 75 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/remoteproc/remoteproc_core.c
> b/drivers/remoteproc/remoteproc_core.c
> index 4edc6f0..adcc66e 100644
> --- a/drivers/remoteproc/remoteproc_core.c
> +++ b/drivers/remoteproc/remoteproc_core.c
> @@ -39,6 +39,7 @@
> #include
> #include
> #include
> +#include
> #include
> #include
> #include
> @@ -145,7 +146,7 @@ static void rproc_disable_iommu(struct rproc *rproc)
> iommu_domain_free(domain);
> }
>
> -static phys_addr_t rproc_va_to_pa(void *cpu_addr)
> +phys_addr_t rproc_va_to_pa(void *cpu_addr)
> {
> /*
> * Return physical address according to virtual address location
> @@ -160,6 +161,7 @@ static phys_addr_t rproc_va_to_pa(void *cpu_addr)
> WARN_ON(!virt_addr_valid(cpu_addr));
> return virt_to_phys(cpu_addr);
> }
> +EXPORT_SYMBOL(rproc_va_to_pa);
>
> /**
> * rproc_da_to_va() - lookup the kernel virtual address for a remoteproc
> address
> @@ -423,6 +425,20 @@ static void rproc_vdev_do_stop(struct rproc_subdev
> *subdev, bool crashed)
> }
>
> /**
> + * rproc_rvdev_release() - release the existence of a rvdev
> + *
> + * @dev: the subdevice's dev
> + */
> +static void rproc_rvdev_release(struct device *dev)
> +{
> + struct rproc_vdev *rvdev = container_of(dev, struct rproc_vdev, dev);
> +
> + of_reserved_mem_device_release(dev);
> +
> + kfree(rvdev);
> +}
> +
> +/**
> * rproc_handle_vdev() - handle a vdev fw resource
> * @rproc: the remote processor
> * @rsc: the vring resource descriptor
> @@ -455,6 +471,7 @@ static int rproc_handle_vdev(struct rproc *rproc, struct
> fw_rsc_vdev *rsc,
> struct device *dev = >dev;
> struct rproc_vdev *rvdev;
> int i, ret;
> + char name[16];
>
> /* make sure resource isn't truncated */
> if (sizeof(*rsc) + rsc->num_of_vrings * sizeof(struct
> fw_rsc_vdev_vring)
> @@ -488,6 +505,18 @@ static int rproc_handle_vdev(struct rproc *rproc, struct
> fw_rsc_vdev *rsc,
> rvdev->rproc = rproc;
> rvdev->index = rproc->nb_vdev++;
>
> + /* Initialise vdev subdevice */
> + snprintf(name, sizeof(name), "vdev%dbuffer", rvdev->index);
> + rvdev->dev.parent = rproc->dev.parent;
> + rvdev->dev.release = rproc_rvdev_release;
> + dev_set_name(>dev, "%s#%s", dev_name(rvdev->dev.parent), name);
> + dev_set_drvdata(>dev, rvdev);
> + dma_set_coherent_mask(>dev, DMA_BIT_MASK(32));
I tried the latest kernel, this function will not set the DMA coherent mask as
dma_supported() of the >dev will return false.
As this is a device created at run time, should it be force to support DMA?
should it directly set the dma_coherent_mask?
> +
> + ret = device_register(>dev);
> + if (ret)
> + goto free_rvdev;
> +
> /* parse the vrings */
> for (i = 0; i < rsc->num_of_vrings; i++) {
> ret = rproc_parse_vring(rvdev, rsc, i);
> @@ -518,7 +547,7 @@ static int rproc_handle_vdev(struct rproc *rproc, struct
> fw_rsc_vdev *rsc,
> for (i--; i >= 0; i--)
> rproc_free_vring(>vring[i]);
> free_rvdev:
> - kfree(rvdev);
> + device_unregister(>dev);
> return ret;
> }
>
> @@ -536,7 +565,7 @@ void rproc_vdev_release(struct kref *ref)
>
> rproc_remove_subdev(rproc, >subdev);
> list_del(>node);
> - kfree(rvdev);
> + device_unregister(>dev);
> }
>
> /**
> diff --git a/drivers/remoteproc/remoteproc_internal.h
> b/drivers/remoteproc/remoteproc_internal.h
> index f6cad24..bfeacfd 100644
> --- a/drivers/remoteproc/remoteproc_internal.h
> +++ b/drivers/remoteproc/remoteproc_internal.h
> @@ -52,6 +52,7 @@ struct dentry *rproc_create_trace_file(const char *name,
> struct rproc *rproc,
> int rproc_alloc_vring(struct rproc_vdev *rvdev, int i);
>
> void *rproc_da_to_va(struct rproc *rproc, u64 da, int len);
> +phys_addr_t rproc_va_to_pa(void *cpu_addr);
> int rproc_trigger_recovery(struct rproc *rproc);
>
> int rproc_elf_sanity_check(struct rproc *rproc, const struct firmware *fw);
> diff --git a/drivers/remoteproc/remoteproc_virtio.c
> b/drivers/remoteproc/remoteproc_virtio.c
> index de21f62..9ee63c0 100644
> --- a/drivers/remoteproc/remoteproc_virtio.c
> +++ b/drivers/remoteproc/remoteproc_virtio.c
> @@
Re: [PATCH 6/7] remoteproc: Add Xilinx ZynqMP R5 remoteproc
On Fri, Aug 24, 2018 at 9:26 AM Wendy Liang wrote: > > Ping, any comments to the driver? Any comments to this driver? Thanks, Wendy > On Thu, Aug 16, 2018 at 3:17 AM Wendy Liang wrote: > > > > There are cortex-r5 processors in Xilinx Zynq UltraScale+ > > MPSoC platforms. This remoteproc driver is to manage the > > R5 processors. > > > > Signed-off-by: Wendy Liang > > --- > > drivers/remoteproc/Kconfig| 9 + > > drivers/remoteproc/Makefile | 1 + > > drivers/remoteproc/zynqmp_r5_remoteproc.c | 692 > > ++ > > 3 files changed, 702 insertions(+) > > create mode 100644 drivers/remoteproc/zynqmp_r5_remoteproc.c > > > > diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig > > index cd1c168..83aac63 100644 > > --- a/drivers/remoteproc/Kconfig > > +++ b/drivers/remoteproc/Kconfig > > @@ -158,6 +158,15 @@ config ST_REMOTEPROC > > config ST_SLIM_REMOTEPROC > > tristate > > > > +config ZYNQMP_R5_REMOTEPROC > > + tristate "ZynqMP_r5 remoteproc support" > > + depends on ARM64 && PM && ARCH_ZYNQMP > > + select RPMSG_VIRTIO > > + select ZYNQMP_FIRMWARE > > + help > > + Say y here to support ZynqMP R5 remote processors via the remote > > + processor framework. > > + > > endif # REMOTEPROC > > > > endmenu > > diff --git a/drivers/remoteproc/Makefile b/drivers/remoteproc/Makefile > > index 02627ed..147923c 100644 > > --- a/drivers/remoteproc/Makefile > > +++ b/drivers/remoteproc/Makefile > > @@ -23,3 +23,4 @@ qcom_wcnss_pil-y += qcom_wcnss.o > > qcom_wcnss_pil-y += qcom_wcnss_iris.o > > obj-$(CONFIG_ST_REMOTEPROC)+= st_remoteproc.o > > obj-$(CONFIG_ST_SLIM_REMOTEPROC) += st_slim_rproc.o > > +obj-$(CONFIG_ZYNQMP_R5_REMOTEPROC) += zynqmp_r5_remoteproc.o > > diff --git a/drivers/remoteproc/zynqmp_r5_remoteproc.c > > b/drivers/remoteproc/zynqmp_r5_remoteproc.c > > new file mode 100644 > > index 000..7fc3718 > > --- /dev/null > > +++ b/drivers/remoteproc/zynqmp_r5_remoteproc.c > > @@ -0,0 +1,692 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * Zynq R5 Remote Processor driver > > + * > > + * Copyright (C) 2015 Xilinx, Inc. > > + * > > + */ > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +#include "remoteproc_internal.h" > > + > > +/* IPI reg offsets */ > > +#define TRIG_OFFSET0x > > +#define OBS_OFFSET 0x0004 > > +#define ISR_OFFSET 0x0010 > > +#define IMR_OFFSET 0x0014 > > +#define IER_OFFSET 0x0018 > > +#define IDR_OFFSET 0x001C > > +#define IPI_ALL_MASK 0x0F0F0301 > > + > > +/* RPU IPI mask */ > > +#define RPU_IPI_INIT_MASK 0x0100 > > +#define RPU_IPI_MASK(n)(RPU_IPI_INIT_MASK << (n)) > > +#define RPU_0_IPI_MASK RPU_IPI_MASK(0) > > +#define RPU_1_IPI_MASK RPU_IPI_MASK(1) > > + > > +/* PM proc states */ > > +#define PM_PROC_STATE_ACTIVE 1u > > + > > +/* Maximum TCM power nodes IDs */ > > +#define MAX_TCM_PNODES 4 > > + > > +/* Register access macros */ > > +#define reg_read(base, reg) \ > > + readl(((void __iomem *)(base)) + (reg)) > > +#define reg_write(base, reg, val) \ > > + writel((val), ((void __iomem *)(base)) + (reg)) > > + > > +#define DEFAULT_FIRMWARE_NAME "rproc-rpu-fw" > > + > > +static bool autoboot __read_mostly; > > + > > +struct zynqmp_r5_rproc_pdata; > > + > > +/** > > + * struct zynqmp_r5_rproc_pdata - zynqmp rpu remote processor instance > > state > > + * @rproc: rproc handle > > + * @workqueue: workqueue for the RPU remoteproc > > + * @ipi_base: virt ptr to IPI channel address registers for APU > > + * @rpu_mode: RPU core configuration > > + * @rpu_id: RPU CPU id > > + * @rpu_pnode_id: RPU CPU power domain id > > + * @mem_pools: list of gen_pool for firmware mmio_sram memory and their >
Re: [PATCH 6/7] remoteproc: Add Xilinx ZynqMP R5 remoteproc
On Fri, Aug 24, 2018 at 9:26 AM Wendy Liang wrote: > > Ping, any comments to the driver? Any comments to this driver? Thanks, Wendy > On Thu, Aug 16, 2018 at 3:17 AM Wendy Liang wrote: > > > > There are cortex-r5 processors in Xilinx Zynq UltraScale+ > > MPSoC platforms. This remoteproc driver is to manage the > > R5 processors. > > > > Signed-off-by: Wendy Liang > > --- > > drivers/remoteproc/Kconfig| 9 + > > drivers/remoteproc/Makefile | 1 + > > drivers/remoteproc/zynqmp_r5_remoteproc.c | 692 > > ++ > > 3 files changed, 702 insertions(+) > > create mode 100644 drivers/remoteproc/zynqmp_r5_remoteproc.c > > > > diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig > > index cd1c168..83aac63 100644 > > --- a/drivers/remoteproc/Kconfig > > +++ b/drivers/remoteproc/Kconfig > > @@ -158,6 +158,15 @@ config ST_REMOTEPROC > > config ST_SLIM_REMOTEPROC > > tristate > > > > +config ZYNQMP_R5_REMOTEPROC > > + tristate "ZynqMP_r5 remoteproc support" > > + depends on ARM64 && PM && ARCH_ZYNQMP > > + select RPMSG_VIRTIO > > + select ZYNQMP_FIRMWARE > > + help > > + Say y here to support ZynqMP R5 remote processors via the remote > > + processor framework. > > + > > endif # REMOTEPROC > > > > endmenu > > diff --git a/drivers/remoteproc/Makefile b/drivers/remoteproc/Makefile > > index 02627ed..147923c 100644 > > --- a/drivers/remoteproc/Makefile > > +++ b/drivers/remoteproc/Makefile > > @@ -23,3 +23,4 @@ qcom_wcnss_pil-y += qcom_wcnss.o > > qcom_wcnss_pil-y += qcom_wcnss_iris.o > > obj-$(CONFIG_ST_REMOTEPROC)+= st_remoteproc.o > > obj-$(CONFIG_ST_SLIM_REMOTEPROC) += st_slim_rproc.o > > +obj-$(CONFIG_ZYNQMP_R5_REMOTEPROC) += zynqmp_r5_remoteproc.o > > diff --git a/drivers/remoteproc/zynqmp_r5_remoteproc.c > > b/drivers/remoteproc/zynqmp_r5_remoteproc.c > > new file mode 100644 > > index 000..7fc3718 > > --- /dev/null > > +++ b/drivers/remoteproc/zynqmp_r5_remoteproc.c > > @@ -0,0 +1,692 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * Zynq R5 Remote Processor driver > > + * > > + * Copyright (C) 2015 Xilinx, Inc. > > + * > > + */ > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +#include "remoteproc_internal.h" > > + > > +/* IPI reg offsets */ > > +#define TRIG_OFFSET0x > > +#define OBS_OFFSET 0x0004 > > +#define ISR_OFFSET 0x0010 > > +#define IMR_OFFSET 0x0014 > > +#define IER_OFFSET 0x0018 > > +#define IDR_OFFSET 0x001C > > +#define IPI_ALL_MASK 0x0F0F0301 > > + > > +/* RPU IPI mask */ > > +#define RPU_IPI_INIT_MASK 0x0100 > > +#define RPU_IPI_MASK(n)(RPU_IPI_INIT_MASK << (n)) > > +#define RPU_0_IPI_MASK RPU_IPI_MASK(0) > > +#define RPU_1_IPI_MASK RPU_IPI_MASK(1) > > + > > +/* PM proc states */ > > +#define PM_PROC_STATE_ACTIVE 1u > > + > > +/* Maximum TCM power nodes IDs */ > > +#define MAX_TCM_PNODES 4 > > + > > +/* Register access macros */ > > +#define reg_read(base, reg) \ > > + readl(((void __iomem *)(base)) + (reg)) > > +#define reg_write(base, reg, val) \ > > + writel((val), ((void __iomem *)(base)) + (reg)) > > + > > +#define DEFAULT_FIRMWARE_NAME "rproc-rpu-fw" > > + > > +static bool autoboot __read_mostly; > > + > > +struct zynqmp_r5_rproc_pdata; > > + > > +/** > > + * struct zynqmp_r5_rproc_pdata - zynqmp rpu remote processor instance > > state > > + * @rproc: rproc handle > > + * @workqueue: workqueue for the RPU remoteproc > > + * @ipi_base: virt ptr to IPI channel address registers for APU > > + * @rpu_mode: RPU core configuration > > + * @rpu_id: RPU CPU id > > + * @rpu_pnode_id: RPU CPU power domain id > > + * @mem_pools: list of gen_pool for firmware mmio_sram memory and their >
Re: [PATCH v3 2/2] dt-bindings: mailbox: Add Xilinx IPI Mailbox
On Thu, Jul 26, 2018 at 2:31 PM Wendy Liang wrote: > > On Tue, Jan 9, 2018 at 8:42 PM, Jassi Brar wrote: > > On Wed, Jan 10, 2018 at 6:52 AM, Jiaying Liang wrote: > >>> From: Jassi Brar [mailto:jassisinghb...@gmail.com] > > > >>> > + > >>> > +Controller Device Node: > >>> > +=== > >>> > +Required properties: > >>> > + > >>> > +- compatible: Shall be: "xlnx,zynqmp-ipi-mailbox" > >>> > +- reg: IPI buffers address ranges > >>> > +- reg-names: Names of the reg resources. It should have: > >>> > + * local_request_region > >>> > + - IPI request msg buffer written by local and > >>> > read > >>> > + by remote > >>> > + * local_response_region > >>> > + - IPI response msg buffer written by local > >>> > and read > >>> > + by remote > >>> > + * remote_request_region > >>> > + - IPI request msg buffer written by remote > >>> > and read > >>> > + by local > >>> > + * remote_response_region > >>> > + - IPI response msg buffer written by remote > >>> > and read > >>> > + by local > >>> > > >>> shmem is option and external to the controller. It should be passed via > >>> client's binding. > >>> Please have a look at Sudeep's proposed patch > >>> https://www.spinics.net/lists/arm-kernel/msg626120.html > >> [Wendy] thanks for the link, but those 'buffers" are registers in the > >> hardware > >> but not memory. > >> > > No, that is for memory, not registers. > > Please have a more careful look at the patch. > > Sorry for very late response. > > Those are not the normal memory but device memories, > they are 32bytes fixed request buffers and response buffers per > channel. They come > from the IPI hardware block. > > The mailbox framework API "mbox_send_message()" allows users to send message > to the mailbox. in this case, just not clear on why we cannot have the > buffer in the > controller? These memories are not for sharing data, but just for > short notification > messages. > > > > >>> > >>> > +- #mbox-cells: Shall be 1. It contains: > >>> > + * tx(0) or rx(1) channel > >>> > +- xlnx,ipi-ids:Xilinx IPI agent IDs of the two peers > >>> > of the > >>> > + Xilinx IPI communication channel. > >>> > +- interrupt-parent:Phandle for the interrupt controller > >>> > +- interrupts: Interrupt information corresponding to the > >>> > + interrupt-names property. > >>> > + > >>> > +Optional properties: > >>> > + > >>> > +- method: The method of accessing the IPI agent registers. > >>> > + Permitted values are: "smc" and "hvc". Default > >>> > is > >>> > + "smc". > >>> > + > >>> Andre almost implemented the generic driver. Can you please have a look at > >>> https://www.spinics.net/lists/arm-kernel/msg595416.html > >>> and see if you can just finish it off? > >> [Wendy] This mailbox controller is about to use Xilinx IPI hardware as > >> mailbox. > >> > > I couldn't find anything specific to Xilinx h/w > > zynqmp_ipi_fw_call() is same as arm_smc_send_data() in Andre's driver > > (though it needs to pass on [R2,R7] as I suggested in reply to him). > > > >> We use it to send notification/short request to firmware (usually running > >> on > >> another core on SoC), > >> > > So does Andre's driver. Which is precise and generic, so I much prefer that. > > > >> and also to receive notification/short request from firmware. > >> Interrupt is used in the receiving direction. It looks different to the > >> usage of > >> mailbox driver from the link. > >> > > Yes,
Re: [PATCH v3 2/2] dt-bindings: mailbox: Add Xilinx IPI Mailbox
On Thu, Jul 26, 2018 at 2:31 PM Wendy Liang wrote: > > On Tue, Jan 9, 2018 at 8:42 PM, Jassi Brar wrote: > > On Wed, Jan 10, 2018 at 6:52 AM, Jiaying Liang wrote: > >>> From: Jassi Brar [mailto:jassisinghb...@gmail.com] > > > >>> > + > >>> > +Controller Device Node: > >>> > +=== > >>> > +Required properties: > >>> > + > >>> > +- compatible: Shall be: "xlnx,zynqmp-ipi-mailbox" > >>> > +- reg: IPI buffers address ranges > >>> > +- reg-names: Names of the reg resources. It should have: > >>> > + * local_request_region > >>> > + - IPI request msg buffer written by local and > >>> > read > >>> > + by remote > >>> > + * local_response_region > >>> > + - IPI response msg buffer written by local > >>> > and read > >>> > + by remote > >>> > + * remote_request_region > >>> > + - IPI request msg buffer written by remote > >>> > and read > >>> > + by local > >>> > + * remote_response_region > >>> > + - IPI response msg buffer written by remote > >>> > and read > >>> > + by local > >>> > > >>> shmem is option and external to the controller. It should be passed via > >>> client's binding. > >>> Please have a look at Sudeep's proposed patch > >>> https://www.spinics.net/lists/arm-kernel/msg626120.html > >> [Wendy] thanks for the link, but those 'buffers" are registers in the > >> hardware > >> but not memory. > >> > > No, that is for memory, not registers. > > Please have a more careful look at the patch. > > Sorry for very late response. > > Those are not the normal memory but device memories, > they are 32bytes fixed request buffers and response buffers per > channel. They come > from the IPI hardware block. > > The mailbox framework API "mbox_send_message()" allows users to send message > to the mailbox. in this case, just not clear on why we cannot have the > buffer in the > controller? These memories are not for sharing data, but just for > short notification > messages. > > > > >>> > >>> > +- #mbox-cells: Shall be 1. It contains: > >>> > + * tx(0) or rx(1) channel > >>> > +- xlnx,ipi-ids:Xilinx IPI agent IDs of the two peers > >>> > of the > >>> > + Xilinx IPI communication channel. > >>> > +- interrupt-parent:Phandle for the interrupt controller > >>> > +- interrupts: Interrupt information corresponding to the > >>> > + interrupt-names property. > >>> > + > >>> > +Optional properties: > >>> > + > >>> > +- method: The method of accessing the IPI agent registers. > >>> > + Permitted values are: "smc" and "hvc". Default > >>> > is > >>> > + "smc". > >>> > + > >>> Andre almost implemented the generic driver. Can you please have a look at > >>> https://www.spinics.net/lists/arm-kernel/msg595416.html > >>> and see if you can just finish it off? > >> [Wendy] This mailbox controller is about to use Xilinx IPI hardware as > >> mailbox. > >> > > I couldn't find anything specific to Xilinx h/w > > zynqmp_ipi_fw_call() is same as arm_smc_send_data() in Andre's driver > > (though it needs to pass on [R2,R7] as I suggested in reply to him). > > > >> We use it to send notification/short request to firmware (usually running > >> on > >> another core on SoC), > >> > > So does Andre's driver. Which is precise and generic, so I much prefer that. > > > >> and also to receive notification/short request from firmware. > >> Interrupt is used in the receiving direction. It looks different to the > >> usage of > >> mailbox driver from the link. > >> > > Yes,
Re: [PATCH 6/7] remoteproc: Add Xilinx ZynqMP R5 remoteproc
Ping, any comments to the driver?
On Thu, Aug 16, 2018 at 3:17 AM Wendy Liang wrote:
>
> There are cortex-r5 processors in Xilinx Zynq UltraScale+
> MPSoC platforms. This remoteproc driver is to manage the
> R5 processors.
>
> Signed-off-by: Wendy Liang
> ---
> drivers/remoteproc/Kconfig| 9 +
> drivers/remoteproc/Makefile | 1 +
> drivers/remoteproc/zynqmp_r5_remoteproc.c | 692
> ++
> 3 files changed, 702 insertions(+)
> create mode 100644 drivers/remoteproc/zynqmp_r5_remoteproc.c
>
> diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig
> index cd1c168..83aac63 100644
> --- a/drivers/remoteproc/Kconfig
> +++ b/drivers/remoteproc/Kconfig
> @@ -158,6 +158,15 @@ config ST_REMOTEPROC
> config ST_SLIM_REMOTEPROC
> tristate
>
> +config ZYNQMP_R5_REMOTEPROC
> + tristate "ZynqMP_r5 remoteproc support"
> + depends on ARM64 && PM && ARCH_ZYNQMP
> + select RPMSG_VIRTIO
> + select ZYNQMP_FIRMWARE
> + help
> + Say y here to support ZynqMP R5 remote processors via the remote
> + processor framework.
> +
> endif # REMOTEPROC
>
> endmenu
> diff --git a/drivers/remoteproc/Makefile b/drivers/remoteproc/Makefile
> index 02627ed..147923c 100644
> --- a/drivers/remoteproc/Makefile
> +++ b/drivers/remoteproc/Makefile
> @@ -23,3 +23,4 @@ qcom_wcnss_pil-y += qcom_wcnss.o
> qcom_wcnss_pil-y += qcom_wcnss_iris.o
> obj-$(CONFIG_ST_REMOTEPROC)+= st_remoteproc.o
> obj-$(CONFIG_ST_SLIM_REMOTEPROC) += st_slim_rproc.o
> +obj-$(CONFIG_ZYNQMP_R5_REMOTEPROC) += zynqmp_r5_remoteproc.o
> diff --git a/drivers/remoteproc/zynqmp_r5_remoteproc.c
> b/drivers/remoteproc/zynqmp_r5_remoteproc.c
> new file mode 100644
> index 000..7fc3718
> --- /dev/null
> +++ b/drivers/remoteproc/zynqmp_r5_remoteproc.c
> @@ -0,0 +1,692 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Zynq R5 Remote Processor driver
> + *
> + * Copyright (C) 2015 Xilinx, Inc.
> + *
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include "remoteproc_internal.h"
> +
> +/* IPI reg offsets */
> +#define TRIG_OFFSET0x
> +#define OBS_OFFSET 0x0004
> +#define ISR_OFFSET 0x0010
> +#define IMR_OFFSET 0x0014
> +#define IER_OFFSET 0x0018
> +#define IDR_OFFSET 0x001C
> +#define IPI_ALL_MASK 0x0F0F0301
> +
> +/* RPU IPI mask */
> +#define RPU_IPI_INIT_MASK 0x0100
> +#define RPU_IPI_MASK(n)(RPU_IPI_INIT_MASK << (n))
> +#define RPU_0_IPI_MASK RPU_IPI_MASK(0)
> +#define RPU_1_IPI_MASK RPU_IPI_MASK(1)
> +
> +/* PM proc states */
> +#define PM_PROC_STATE_ACTIVE 1u
> +
> +/* Maximum TCM power nodes IDs */
> +#define MAX_TCM_PNODES 4
> +
> +/* Register access macros */
> +#define reg_read(base, reg) \
> + readl(((void __iomem *)(base)) + (reg))
> +#define reg_write(base, reg, val) \
> + writel((val), ((void __iomem *)(base)) + (reg))
> +
> +#define DEFAULT_FIRMWARE_NAME "rproc-rpu-fw"
> +
> +static bool autoboot __read_mostly;
> +
> +struct zynqmp_r5_rproc_pdata;
> +
> +/**
> + * struct zynqmp_r5_rproc_pdata - zynqmp rpu remote processor instance state
> + * @rproc: rproc handle
> + * @workqueue: workqueue for the RPU remoteproc
> + * @ipi_base: virt ptr to IPI channel address registers for APU
> + * @rpu_mode: RPU core configuration
> + * @rpu_id: RPU CPU id
> + * @rpu_pnode_id: RPU CPU power domain id
> + * @mem_pools: list of gen_pool for firmware mmio_sram memory and their
> + * power domain IDs
> + * @mems: list of rproc_mem_entries for firmware
> + * @irq: IRQ number
> + * @ipi_dest_mask: IPI destination mask for the IPI channel
> + */
> +struct zynqmp_r5_rproc_pdata {
> + struct rproc *rproc;
> + struct work_struct workqueue;
> + void __iomem *ipi_base;
> + enum rpu_oper_mode rpu_mode;
> + struct list_head mems;
> + u32 ipi_dest_mask;
> + u32 rpu_id;
> + u32 rpu_pnode_id;
> + int irq;
> + u32 tcm_pnode_id[MAX_TCM_PNODES];
> +};
> +
> +/**
> + * r5_boot_addr_config - configure the boot address of R5
> + * @pdata: platform data
> + * @bootmem: boot from
Re: [PATCH 6/7] remoteproc: Add Xilinx ZynqMP R5 remoteproc
Ping, any comments to the driver?
On Thu, Aug 16, 2018 at 3:17 AM Wendy Liang wrote:
>
> There are cortex-r5 processors in Xilinx Zynq UltraScale+
> MPSoC platforms. This remoteproc driver is to manage the
> R5 processors.
>
> Signed-off-by: Wendy Liang
> ---
> drivers/remoteproc/Kconfig| 9 +
> drivers/remoteproc/Makefile | 1 +
> drivers/remoteproc/zynqmp_r5_remoteproc.c | 692
> ++
> 3 files changed, 702 insertions(+)
> create mode 100644 drivers/remoteproc/zynqmp_r5_remoteproc.c
>
> diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig
> index cd1c168..83aac63 100644
> --- a/drivers/remoteproc/Kconfig
> +++ b/drivers/remoteproc/Kconfig
> @@ -158,6 +158,15 @@ config ST_REMOTEPROC
> config ST_SLIM_REMOTEPROC
> tristate
>
> +config ZYNQMP_R5_REMOTEPROC
> + tristate "ZynqMP_r5 remoteproc support"
> + depends on ARM64 && PM && ARCH_ZYNQMP
> + select RPMSG_VIRTIO
> + select ZYNQMP_FIRMWARE
> + help
> + Say y here to support ZynqMP R5 remote processors via the remote
> + processor framework.
> +
> endif # REMOTEPROC
>
> endmenu
> diff --git a/drivers/remoteproc/Makefile b/drivers/remoteproc/Makefile
> index 02627ed..147923c 100644
> --- a/drivers/remoteproc/Makefile
> +++ b/drivers/remoteproc/Makefile
> @@ -23,3 +23,4 @@ qcom_wcnss_pil-y += qcom_wcnss.o
> qcom_wcnss_pil-y += qcom_wcnss_iris.o
> obj-$(CONFIG_ST_REMOTEPROC)+= st_remoteproc.o
> obj-$(CONFIG_ST_SLIM_REMOTEPROC) += st_slim_rproc.o
> +obj-$(CONFIG_ZYNQMP_R5_REMOTEPROC) += zynqmp_r5_remoteproc.o
> diff --git a/drivers/remoteproc/zynqmp_r5_remoteproc.c
> b/drivers/remoteproc/zynqmp_r5_remoteproc.c
> new file mode 100644
> index 000..7fc3718
> --- /dev/null
> +++ b/drivers/remoteproc/zynqmp_r5_remoteproc.c
> @@ -0,0 +1,692 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Zynq R5 Remote Processor driver
> + *
> + * Copyright (C) 2015 Xilinx, Inc.
> + *
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include "remoteproc_internal.h"
> +
> +/* IPI reg offsets */
> +#define TRIG_OFFSET0x
> +#define OBS_OFFSET 0x0004
> +#define ISR_OFFSET 0x0010
> +#define IMR_OFFSET 0x0014
> +#define IER_OFFSET 0x0018
> +#define IDR_OFFSET 0x001C
> +#define IPI_ALL_MASK 0x0F0F0301
> +
> +/* RPU IPI mask */
> +#define RPU_IPI_INIT_MASK 0x0100
> +#define RPU_IPI_MASK(n)(RPU_IPI_INIT_MASK << (n))
> +#define RPU_0_IPI_MASK RPU_IPI_MASK(0)
> +#define RPU_1_IPI_MASK RPU_IPI_MASK(1)
> +
> +/* PM proc states */
> +#define PM_PROC_STATE_ACTIVE 1u
> +
> +/* Maximum TCM power nodes IDs */
> +#define MAX_TCM_PNODES 4
> +
> +/* Register access macros */
> +#define reg_read(base, reg) \
> + readl(((void __iomem *)(base)) + (reg))
> +#define reg_write(base, reg, val) \
> + writel((val), ((void __iomem *)(base)) + (reg))
> +
> +#define DEFAULT_FIRMWARE_NAME "rproc-rpu-fw"
> +
> +static bool autoboot __read_mostly;
> +
> +struct zynqmp_r5_rproc_pdata;
> +
> +/**
> + * struct zynqmp_r5_rproc_pdata - zynqmp rpu remote processor instance state
> + * @rproc: rproc handle
> + * @workqueue: workqueue for the RPU remoteproc
> + * @ipi_base: virt ptr to IPI channel address registers for APU
> + * @rpu_mode: RPU core configuration
> + * @rpu_id: RPU CPU id
> + * @rpu_pnode_id: RPU CPU power domain id
> + * @mem_pools: list of gen_pool for firmware mmio_sram memory and their
> + * power domain IDs
> + * @mems: list of rproc_mem_entries for firmware
> + * @irq: IRQ number
> + * @ipi_dest_mask: IPI destination mask for the IPI channel
> + */
> +struct zynqmp_r5_rproc_pdata {
> + struct rproc *rproc;
> + struct work_struct workqueue;
> + void __iomem *ipi_base;
> + enum rpu_oper_mode rpu_mode;
> + struct list_head mems;
> + u32 ipi_dest_mask;
> + u32 rpu_id;
> + u32 rpu_pnode_id;
> + int irq;
> + u32 tcm_pnode_id[MAX_TCM_PNODES];
> +};
> +
> +/**
> + * r5_boot_addr_config - configure the boot address of R5
> + * @pdata: platform data
> + * @bootmem: boot from
Re: [PATCH 7/7] Documentation: devicetree: Add Xilinx R5 rproc binding
On Fri, Aug 17, 2018 at 9:31 AM, Moritz Fischer
wrote:
> Hi Wendy,
>
> couple of minor stuff inline.
>
> On Thu, Aug 16, 2018 at 12:06 AM, Wendy Liang wrote:
>> Add device tree binding for Xilinx Cortex-r5 remoteproc.
>>
>> Signed-off-by: Wendy Liang
>> ---
>> .../remoteproc/xlnx,zynqmp-r5-remoteproc.txt | 81
>> ++
>> 1 file changed, 81 insertions(+)
>> create mode 100644
>> Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5-remoteproc.txt
>>
>> diff --git
>> a/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5-remoteproc.txt
>> b/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5-remoteproc.txt
>> new file mode 100644
>> index 000..3940019
>> --- /dev/null
>> +++
>> b/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5-remoteproc.txt
>> @@ -0,0 +1,81 @@
>> +Xilinx ARM Cortex A53-R5 remoteproc driver
>> +==
>> +
>> +ZynqMP family of devices use two Cortex R5 processors to help with various
>> +low power / real time tasks.
>
> The ZynqMP family [..] uses [..]
Will update in next version
>> +
>> +This driver requires specific ZynqMP hardware design.
>
> *a* specific ZynqMP hardware design. What does that mean?
>> +
>> +ZynqMP R5 RemoteProc Device Node:
>> +=
>> +A zynqmp_r5_remoteproc device node is used to represent a R5 IP instance
>> +within ZynqMP SoC.
>> +
>> +Required properties:
>> +
>> + - compatible : Should be "xlnx,zynqmp-r5-remoteproc-1.0"
>> + - reg : Address and length of the register set for the device. It
>> +contains in the same order as described reg-names
>
> ?
>> + - reg-names: Contain the register set names.
>
> Contains
Will update in next version
>
>> + "tcm_a" and "tcm_b" for TCM memories.
>> + If the user uses the remoteproc driver with the RPMsg kernel
>> + driver,"ipi" for the IPI register used to communicate with RPU
>> + is also required.
>> + Otherwise, if user only uses the remoteproc driver to boot RPU
>> + firmware, "ipi" is not required.
>> + - tcm-pnode-id: TCM resources power nodes IDs which are used to request TCM
>> + resources for the remoteproc driver to access.
>> + - rpu-pnode-id : RPU power node id which is used by the remoteproc driver
>> + to start RPU or shut it down.
>> +
>> +Optional properties:
>> +
>> + - core_conf : R5 core configuration (valid string - split0 or split1 or
>> + lock-step), default is lock-step.
>> + - memory-region: memories regions for RPU executable and DMA memory.
>> + - interrupts : Interrupt mapping for remoteproc IPI. It is required if the
>> +user uses the remoteproc driver with the RPMsg kernel
>> driver.
>> + - interrupt-parent : Phandle for the interrupt controller. It is required
>> if
>> + the user uses the remoteproc driver with the RPMsg
>> kernel
>> + kernel driver.
>> +
>> +Example:
>> +
>> + reserved-memory {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> + rproc_0_fw_reserved: rproc@3ed00 {
>> + compatible = "rproc-prog-memory";
>> + no-map;
>> + reg = <0x0 0x3ed0 0x0 0x4>;
>> + };
>> + rproc_0_dma_reserved: rproc@3ed40 {
>> + compatible = "shared-dma-pool";
>> + no-map;
>> + reg = <0x0 0x3ed4 0x0 0x8>;
>> + };
>> + };
>> +
>> + firmware {
>> + zynqmp_firmware: zynqmp-firmware {
>> + compatible = "xlnx,zynqmp-firmware";
>> + method = "smc";
>> + };
>> + };
>> +
>> + zynqmp-r5-remoteproc@0 {
>> + compatible = "xlnx,zynqmp-r5-remoteproc-1.0";
>> + reg = <0x0 0xFFE0 0x0 0x1>,
>> + <0x0 0xFFE2 0x0 0x1>,
>> + <0x0 0xff34 0x0 0x100>;
>> + reg-names = "tcm_a", "tcm_b", "ipi";
>> + dma-ranges;
>> + core_conf = "split0";
>> + memory-region = <_0_fw_reserved>,
>> + <_0_dma_reserved>;
>> + tcm-pnode-id = <0xf>, <0x10>;
>> + rpu-pnode-id = <0x7>;
>> + interrupt-parent = <>;
>> + interrupts = <0 29 4>;
>> + } ;
>> --
>> 2.7.4
>>
>
> Cheers,
> Moritz
Re: [PATCH 7/7] Documentation: devicetree: Add Xilinx R5 rproc binding
On Fri, Aug 17, 2018 at 9:31 AM, Moritz Fischer
wrote:
> Hi Wendy,
>
> couple of minor stuff inline.
>
> On Thu, Aug 16, 2018 at 12:06 AM, Wendy Liang wrote:
>> Add device tree binding for Xilinx Cortex-r5 remoteproc.
>>
>> Signed-off-by: Wendy Liang
>> ---
>> .../remoteproc/xlnx,zynqmp-r5-remoteproc.txt | 81
>> ++
>> 1 file changed, 81 insertions(+)
>> create mode 100644
>> Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5-remoteproc.txt
>>
>> diff --git
>> a/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5-remoteproc.txt
>> b/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5-remoteproc.txt
>> new file mode 100644
>> index 000..3940019
>> --- /dev/null
>> +++
>> b/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5-remoteproc.txt
>> @@ -0,0 +1,81 @@
>> +Xilinx ARM Cortex A53-R5 remoteproc driver
>> +==
>> +
>> +ZynqMP family of devices use two Cortex R5 processors to help with various
>> +low power / real time tasks.
>
> The ZynqMP family [..] uses [..]
Will update in next version
>> +
>> +This driver requires specific ZynqMP hardware design.
>
> *a* specific ZynqMP hardware design. What does that mean?
>> +
>> +ZynqMP R5 RemoteProc Device Node:
>> +=
>> +A zynqmp_r5_remoteproc device node is used to represent a R5 IP instance
>> +within ZynqMP SoC.
>> +
>> +Required properties:
>> +
>> + - compatible : Should be "xlnx,zynqmp-r5-remoteproc-1.0"
>> + - reg : Address and length of the register set for the device. It
>> +contains in the same order as described reg-names
>
> ?
>> + - reg-names: Contain the register set names.
>
> Contains
Will update in next version
>
>> + "tcm_a" and "tcm_b" for TCM memories.
>> + If the user uses the remoteproc driver with the RPMsg kernel
>> + driver,"ipi" for the IPI register used to communicate with RPU
>> + is also required.
>> + Otherwise, if user only uses the remoteproc driver to boot RPU
>> + firmware, "ipi" is not required.
>> + - tcm-pnode-id: TCM resources power nodes IDs which are used to request TCM
>> + resources for the remoteproc driver to access.
>> + - rpu-pnode-id : RPU power node id which is used by the remoteproc driver
>> + to start RPU or shut it down.
>> +
>> +Optional properties:
>> +
>> + - core_conf : R5 core configuration (valid string - split0 or split1 or
>> + lock-step), default is lock-step.
>> + - memory-region: memories regions for RPU executable and DMA memory.
>> + - interrupts : Interrupt mapping for remoteproc IPI. It is required if the
>> +user uses the remoteproc driver with the RPMsg kernel
>> driver.
>> + - interrupt-parent : Phandle for the interrupt controller. It is required
>> if
>> + the user uses the remoteproc driver with the RPMsg
>> kernel
>> + kernel driver.
>> +
>> +Example:
>> +
>> + reserved-memory {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> + rproc_0_fw_reserved: rproc@3ed00 {
>> + compatible = "rproc-prog-memory";
>> + no-map;
>> + reg = <0x0 0x3ed0 0x0 0x4>;
>> + };
>> + rproc_0_dma_reserved: rproc@3ed40 {
>> + compatible = "shared-dma-pool";
>> + no-map;
>> + reg = <0x0 0x3ed4 0x0 0x8>;
>> + };
>> + };
>> +
>> + firmware {
>> + zynqmp_firmware: zynqmp-firmware {
>> + compatible = "xlnx,zynqmp-firmware";
>> + method = "smc";
>> + };
>> + };
>> +
>> + zynqmp-r5-remoteproc@0 {
>> + compatible = "xlnx,zynqmp-r5-remoteproc-1.0";
>> + reg = <0x0 0xFFE0 0x0 0x1>,
>> + <0x0 0xFFE2 0x0 0x1>,
>> + <0x0 0xff34 0x0 0x100>;
>> + reg-names = "tcm_a", "tcm_b", "ipi";
>> + dma-ranges;
>> + core_conf = "split0";
>> + memory-region = <_0_fw_reserved>,
>> + <_0_dma_reserved>;
>> + tcm-pnode-id = <0xf>, <0x10>;
>> + rpu-pnode-id = <0x7>;
>> + interrupt-parent = <>;
>> + interrupts = <0 29 4>;
>> + } ;
>> --
>> 2.7.4
>>
>
> Cheers,
> Moritz
Re: [PATCH 7/7] Documentation: devicetree: Add Xilinx R5 rproc binding
On Fri, Aug 17, 2018 at 8:09 AM, Rob Herring wrote: > Hi, this email is from Rob's (experimental) review bot. I found a couple > of common problems with your patch. Please see below. > > On Thu, 16 Aug 2018 00:06:30 -0700, Wendy Liang wrote: >> Add device tree binding for Xilinx Cortex-r5 remoteproc. >> >> Signed-off-by: Wendy Liang > > The preferred subject prefix is "dt-bindings: : ...". Will updated in the next release > >> --- >> .../remoteproc/xlnx,zynqmp-r5-remoteproc.txt | 81 >> ++ >> 1 file changed, 81 insertions(+) >> create mode 100644 >> Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5-remoteproc.txt >>
Re: [PATCH 7/7] Documentation: devicetree: Add Xilinx R5 rproc binding
On Fri, Aug 17, 2018 at 8:09 AM, Rob Herring wrote: > Hi, this email is from Rob's (experimental) review bot. I found a couple > of common problems with your patch. Please see below. > > On Thu, 16 Aug 2018 00:06:30 -0700, Wendy Liang wrote: >> Add device tree binding for Xilinx Cortex-r5 remoteproc. >> >> Signed-off-by: Wendy Liang > > The preferred subject prefix is "dt-bindings: : ...". Will updated in the next release > >> --- >> .../remoteproc/xlnx,zynqmp-r5-remoteproc.txt | 81 >> ++ >> 1 file changed, 81 insertions(+) >> create mode 100644 >> Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5-remoteproc.txt >>
[PATCH 5/7] firmware: xlnx-zynqmp: Add shutdown/wakeup request
Add shutdown/wakeup a resource eemi operations to shutdown
or bringup a resource.
Signed-off-by: Wendy Liang
---
drivers/firmware/xilinx/zynqmp.c | 35 +++
include/linux/firmware/xlnx-zynqmp.h | 8
2 files changed, 43 insertions(+)
diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
index 2e97f60..aa83262 100644
--- a/drivers/firmware/xilinx/zynqmp.c
+++ b/drivers/firmware/xilinx/zynqmp.c
@@ -475,6 +475,39 @@ static int zynqmp_pm_release_node(const u32 node)
return zynqmp_pm_invoke_fn(PM_RELEASE_NODE, node, 0, 0, 0, NULL);
}
+/**
+ * zynqmp_pm_force_powerdown - PM call to request for another PU or subsystem
to
+ * be powered down forcefully
+ * @target:Node ID of the targeted PU or subsystem
+ * @ack: Flag to specify whether acknowledge is requested
+ *
+ * Return: Returns status, either success or error+reason
+ */
+static int zynqmp_pm_force_powerdown(const u32 target,
+const enum zynqmp_pm_request_ack ack)
+{
+ return zynqmp_pm_invoke_fn(PM_FORCE_POWERDOWN, target, ack, 0, 0, NULL);
+}
+
+/**
+ * zynqmp_pm_request_wakeup - PM call to wake up selected master or subsystem
+ * @node: Node ID of the master or subsystem
+ * @set_addr: Specifies whether the address argument is relevant
+ * @address: Address from which to resume when woken up
+ * @ack: Flag to specify whether acknowledge requested
+ *
+ * Return: Returns status, either success or error+reason
+ */
+static int zynqmp_pm_request_wakeup(const u32 node,
+ const bool set_addr,
+ const u64 address,
+ const enum zynqmp_pm_request_ack ack)
+{
+ /* set_addr flag is encoded into 1st bit of address */
+ return zynqmp_pm_invoke_fn(PM_REQUEST_WAKEUP, node, address | set_addr,
+ address >> 32, ack, NULL);
+}
+
static const struct zynqmp_eemi_ops eemi_ops = {
.get_api_version = zynqmp_pm_get_api_version,
.ioctl = zynqmp_pm_ioctl,
@@ -490,6 +523,8 @@ static const struct zynqmp_eemi_ops eemi_ops = {
.clock_getparent = zynqmp_pm_clock_getparent,
.request_node = zynqmp_pm_request_node,
.release_node = zynqmp_pm_release_node,
+ .force_powerdown = zynqmp_pm_force_powerdown,
+ .request_wakeup = zynqmp_pm_request_wakeup,
};
/**
diff --git a/include/linux/firmware/xlnx-zynqmp.h
b/include/linux/firmware/xlnx-zynqmp.h
index 02067a3..efc73bc 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -54,6 +54,8 @@ enum pm_api_id {
PM_CLOCK_GETRATE,
PM_CLOCK_SETPARENT,
PM_CLOCK_GETPARENT,
+ PM_FORCE_POWERDOWN = 8,
+ PM_REQUEST_WAKEUP = 10,
PM_REQUEST_NODE = 13,
PM_RELEASE_NODE = 14,
};
@@ -137,6 +139,12 @@ struct zynqmp_eemi_ops {
const u32 qos,
const enum zynqmp_pm_request_ack ack);
int (*release_node)(const u32 node);
+ int (*force_powerdown)(const u32 target,
+ const enum zynqmp_pm_request_ack ack);
+ int (*request_wakeup)(const u32 node,
+ const bool set_addr,
+ const u64 address,
+ const enum zynqmp_pm_request_ack ack);
};
#if IS_REACHABLE(CONFIG_ARCH_ZYNQMP)
--
2.7.4
[PATCH 3/7] firmware: xilinx-zynqmp: Add request access capability macro
Add request access capability macro which will be used to
request access to a device node from Xilinx firmware.
Signed-off-by: Wendy Liang
---
include/linux/firmware/xlnx-zynqmp.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/linux/firmware/xlnx-zynqmp.h
b/include/linux/firmware/xlnx-zynqmp.h
index e3b7292..83ebadf 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -32,6 +32,9 @@
/* Number of 32bits values in payload */
#define PAYLOAD_ARG_CNT4U
+/* Request capability of a device node */
+#defineZYNQMP_PM_CAPABILITY_ACCESS 0x1U
+
enum zynqmp_pm_request_ack {
ZYNQMP_PM_REQUEST_ACK_NO = 1,
ZYNQMP_PM_REQUEST_ACK_BLOCKING,
--
2.7.4
[PATCH 6/7] remoteproc: Add Xilinx ZynqMP R5 remoteproc
There are cortex-r5 processors in Xilinx Zynq UltraScale+
MPSoC platforms. This remoteproc driver is to manage the
R5 processors.
Signed-off-by: Wendy Liang
---
drivers/remoteproc/Kconfig| 9 +
drivers/remoteproc/Makefile | 1 +
drivers/remoteproc/zynqmp_r5_remoteproc.c | 692 ++
3 files changed, 702 insertions(+)
create mode 100644 drivers/remoteproc/zynqmp_r5_remoteproc.c
diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig
index cd1c168..83aac63 100644
--- a/drivers/remoteproc/Kconfig
+++ b/drivers/remoteproc/Kconfig
@@ -158,6 +158,15 @@ config ST_REMOTEPROC
config ST_SLIM_REMOTEPROC
tristate
+config ZYNQMP_R5_REMOTEPROC
+ tristate "ZynqMP_r5 remoteproc support"
+ depends on ARM64 && PM && ARCH_ZYNQMP
+ select RPMSG_VIRTIO
+ select ZYNQMP_FIRMWARE
+ help
+ Say y here to support ZynqMP R5 remote processors via the remote
+ processor framework.
+
endif # REMOTEPROC
endmenu
diff --git a/drivers/remoteproc/Makefile b/drivers/remoteproc/Makefile
index 02627ed..147923c 100644
--- a/drivers/remoteproc/Makefile
+++ b/drivers/remoteproc/Makefile
@@ -23,3 +23,4 @@ qcom_wcnss_pil-y += qcom_wcnss.o
qcom_wcnss_pil-y += qcom_wcnss_iris.o
obj-$(CONFIG_ST_REMOTEPROC)+= st_remoteproc.o
obj-$(CONFIG_ST_SLIM_REMOTEPROC) += st_slim_rproc.o
+obj-$(CONFIG_ZYNQMP_R5_REMOTEPROC) += zynqmp_r5_remoteproc.o
diff --git a/drivers/remoteproc/zynqmp_r5_remoteproc.c
b/drivers/remoteproc/zynqmp_r5_remoteproc.c
new file mode 100644
index 000..7fc3718
--- /dev/null
+++ b/drivers/remoteproc/zynqmp_r5_remoteproc.c
@@ -0,0 +1,692 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Zynq R5 Remote Processor driver
+ *
+ * Copyright (C) 2015 Xilinx, Inc.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "remoteproc_internal.h"
+
+/* IPI reg offsets */
+#define TRIG_OFFSET0x
+#define OBS_OFFSET 0x0004
+#define ISR_OFFSET 0x0010
+#define IMR_OFFSET 0x0014
+#define IER_OFFSET 0x0018
+#define IDR_OFFSET 0x001C
+#define IPI_ALL_MASK 0x0F0F0301
+
+/* RPU IPI mask */
+#define RPU_IPI_INIT_MASK 0x0100
+#define RPU_IPI_MASK(n)(RPU_IPI_INIT_MASK << (n))
+#define RPU_0_IPI_MASK RPU_IPI_MASK(0)
+#define RPU_1_IPI_MASK RPU_IPI_MASK(1)
+
+/* PM proc states */
+#define PM_PROC_STATE_ACTIVE 1u
+
+/* Maximum TCM power nodes IDs */
+#define MAX_TCM_PNODES 4
+
+/* Register access macros */
+#define reg_read(base, reg) \
+ readl(((void __iomem *)(base)) + (reg))
+#define reg_write(base, reg, val) \
+ writel((val), ((void __iomem *)(base)) + (reg))
+
+#define DEFAULT_FIRMWARE_NAME "rproc-rpu-fw"
+
+static bool autoboot __read_mostly;
+
+struct zynqmp_r5_rproc_pdata;
+
+/**
+ * struct zynqmp_r5_rproc_pdata - zynqmp rpu remote processor instance state
+ * @rproc: rproc handle
+ * @workqueue: workqueue for the RPU remoteproc
+ * @ipi_base: virt ptr to IPI channel address registers for APU
+ * @rpu_mode: RPU core configuration
+ * @rpu_id: RPU CPU id
+ * @rpu_pnode_id: RPU CPU power domain id
+ * @mem_pools: list of gen_pool for firmware mmio_sram memory and their
+ * power domain IDs
+ * @mems: list of rproc_mem_entries for firmware
+ * @irq: IRQ number
+ * @ipi_dest_mask: IPI destination mask for the IPI channel
+ */
+struct zynqmp_r5_rproc_pdata {
+ struct rproc *rproc;
+ struct work_struct workqueue;
+ void __iomem *ipi_base;
+ enum rpu_oper_mode rpu_mode;
+ struct list_head mems;
+ u32 ipi_dest_mask;
+ u32 rpu_id;
+ u32 rpu_pnode_id;
+ int irq;
+ u32 tcm_pnode_id[MAX_TCM_PNODES];
+};
+
+/**
+ * r5_boot_addr_config - configure the boot address of R5
+ * @pdata: platform data
+ * @bootmem: boot from LOVEC or HIVEC
+ *
+ * This function will set the RPU boot address
+ */
+static void r5_boot_addr_config(struct zynqmp_r5_rproc_pdata *pdata,
+ enum rpu_boot_mem bootmem)
+{
+ const struct zynqmp_eemi_ops *eemi = zynqmp_pm_get_eemi_ops();
+
+ pr_debug("%s: R5 ID: %d, boot_dev %d\n",
+__func__, pdata->rpu_id, bootmem);
+
+ if (!eemi || !eemi->ioctl) {
+ pr_err("%s: no eemi ioctl operation.\n", __func__);
+ return;
+ }
+ eemi->ioctl(pdata->rpu_pnode_id, IOCTL_RPU_BOOT_ADDR_CONFIG,
+ bootmem, 0, NULL);
+}
+
+/**
+ * r5_mode_config - configure R5 operation mode
+ * @pdata: platform data
+ *
+ * configure R5 to split mode or lockstep mode
+ * based
[PATCH 4/7] firmware: xlnx-zynqmp: Add request/release node
Add request/release resource node EEMI operations.
Signed-off-by: Wendy Liang
---
drivers/firmware/xilinx/zynqmp.c | 30 ++
include/linux/firmware/xlnx-zynqmp.h | 7 +++
2 files changed, 37 insertions(+)
diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
index ce6c746..2e97f60 100644
--- a/drivers/firmware/xilinx/zynqmp.c
+++ b/drivers/firmware/xilinx/zynqmp.c
@@ -447,6 +447,34 @@ static int zynqmp_pm_clock_getparent(u32 clock_id, u32
*parent_id)
return ret;
}
+/**
+ * zynqmp_pm_request_node - PM call to request a node with specific
capabilities
+ * @node: Node ID of the slave
+ * @capabilities: Requested capabilities of the slave
+ * @qos: Quality of service (not supported)
+ * @ack: Flag to specify whether acknowledge is requested
+ *
+ * Return: Returns status, either success or error+reason
+ */
+static int zynqmp_pm_request_node(const u32 node, const u32 capabilities,
+ const u32 qos,
+ const enum zynqmp_pm_request_ack ack)
+{
+ return zynqmp_pm_invoke_fn(PM_REQUEST_NODE, node, capabilities,
+ qos, ack, NULL);
+}
+
+/**
+ * zynqmp_pm_release_node - PM call to release a node
+ * @node: Node ID of the slave
+ *
+ * Return: Returns status, either success or error+reason
+ */
+static int zynqmp_pm_release_node(const u32 node)
+{
+ return zynqmp_pm_invoke_fn(PM_RELEASE_NODE, node, 0, 0, 0, NULL);
+}
+
static const struct zynqmp_eemi_ops eemi_ops = {
.get_api_version = zynqmp_pm_get_api_version,
.ioctl = zynqmp_pm_ioctl,
@@ -460,6 +488,8 @@ static const struct zynqmp_eemi_ops eemi_ops = {
.clock_getrate = zynqmp_pm_clock_getrate,
.clock_setparent = zynqmp_pm_clock_setparent,
.clock_getparent = zynqmp_pm_clock_getparent,
+ .request_node = zynqmp_pm_request_node,
+ .release_node = zynqmp_pm_release_node,
};
/**
diff --git a/include/linux/firmware/xlnx-zynqmp.h
b/include/linux/firmware/xlnx-zynqmp.h
index 83ebadf..02067a3 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -54,6 +54,8 @@ enum pm_api_id {
PM_CLOCK_GETRATE,
PM_CLOCK_SETPARENT,
PM_CLOCK_GETPARENT,
+ PM_REQUEST_NODE = 13,
+ PM_RELEASE_NODE = 14,
};
/* PMU-FW return status codes */
@@ -130,6 +132,11 @@ struct zynqmp_eemi_ops {
int (*clock_getrate)(u32 clock_id, u64 *rate);
int (*clock_setparent)(u32 clock_id, u32 parent_id);
int (*clock_getparent)(u32 clock_id, u32 *parent_id);
+ int (*request_node)(const u32 node,
+ const u32 capabilities,
+ const u32 qos,
+ const enum zynqmp_pm_request_ack ack);
+ int (*release_node)(const u32 node);
};
#if IS_REACHABLE(CONFIG_ARCH_ZYNQMP)
--
2.7.4
[PATCH 5/7] firmware: xlnx-zynqmp: Add shutdown/wakeup request
Add shutdown/wakeup a resource eemi operations to shutdown
or bringup a resource.
Signed-off-by: Wendy Liang
---
drivers/firmware/xilinx/zynqmp.c | 35 +++
include/linux/firmware/xlnx-zynqmp.h | 8
2 files changed, 43 insertions(+)
diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
index 2e97f60..aa83262 100644
--- a/drivers/firmware/xilinx/zynqmp.c
+++ b/drivers/firmware/xilinx/zynqmp.c
@@ -475,6 +475,39 @@ static int zynqmp_pm_release_node(const u32 node)
return zynqmp_pm_invoke_fn(PM_RELEASE_NODE, node, 0, 0, 0, NULL);
}
+/**
+ * zynqmp_pm_force_powerdown - PM call to request for another PU or subsystem
to
+ * be powered down forcefully
+ * @target:Node ID of the targeted PU or subsystem
+ * @ack: Flag to specify whether acknowledge is requested
+ *
+ * Return: Returns status, either success or error+reason
+ */
+static int zynqmp_pm_force_powerdown(const u32 target,
+const enum zynqmp_pm_request_ack ack)
+{
+ return zynqmp_pm_invoke_fn(PM_FORCE_POWERDOWN, target, ack, 0, 0, NULL);
+}
+
+/**
+ * zynqmp_pm_request_wakeup - PM call to wake up selected master or subsystem
+ * @node: Node ID of the master or subsystem
+ * @set_addr: Specifies whether the address argument is relevant
+ * @address: Address from which to resume when woken up
+ * @ack: Flag to specify whether acknowledge requested
+ *
+ * Return: Returns status, either success or error+reason
+ */
+static int zynqmp_pm_request_wakeup(const u32 node,
+ const bool set_addr,
+ const u64 address,
+ const enum zynqmp_pm_request_ack ack)
+{
+ /* set_addr flag is encoded into 1st bit of address */
+ return zynqmp_pm_invoke_fn(PM_REQUEST_WAKEUP, node, address | set_addr,
+ address >> 32, ack, NULL);
+}
+
static const struct zynqmp_eemi_ops eemi_ops = {
.get_api_version = zynqmp_pm_get_api_version,
.ioctl = zynqmp_pm_ioctl,
@@ -490,6 +523,8 @@ static const struct zynqmp_eemi_ops eemi_ops = {
.clock_getparent = zynqmp_pm_clock_getparent,
.request_node = zynqmp_pm_request_node,
.release_node = zynqmp_pm_release_node,
+ .force_powerdown = zynqmp_pm_force_powerdown,
+ .request_wakeup = zynqmp_pm_request_wakeup,
};
/**
diff --git a/include/linux/firmware/xlnx-zynqmp.h
b/include/linux/firmware/xlnx-zynqmp.h
index 02067a3..efc73bc 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -54,6 +54,8 @@ enum pm_api_id {
PM_CLOCK_GETRATE,
PM_CLOCK_SETPARENT,
PM_CLOCK_GETPARENT,
+ PM_FORCE_POWERDOWN = 8,
+ PM_REQUEST_WAKEUP = 10,
PM_REQUEST_NODE = 13,
PM_RELEASE_NODE = 14,
};
@@ -137,6 +139,12 @@ struct zynqmp_eemi_ops {
const u32 qos,
const enum zynqmp_pm_request_ack ack);
int (*release_node)(const u32 node);
+ int (*force_powerdown)(const u32 target,
+ const enum zynqmp_pm_request_ack ack);
+ int (*request_wakeup)(const u32 node,
+ const bool set_addr,
+ const u64 address,
+ const enum zynqmp_pm_request_ack ack);
};
#if IS_REACHABLE(CONFIG_ARCH_ZYNQMP)
--
2.7.4
[PATCH 3/7] firmware: xilinx-zynqmp: Add request access capability macro
Add request access capability macro which will be used to
request access to a device node from Xilinx firmware.
Signed-off-by: Wendy Liang
---
include/linux/firmware/xlnx-zynqmp.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/linux/firmware/xlnx-zynqmp.h
b/include/linux/firmware/xlnx-zynqmp.h
index e3b7292..83ebadf 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -32,6 +32,9 @@
/* Number of 32bits values in payload */
#define PAYLOAD_ARG_CNT4U
+/* Request capability of a device node */
+#defineZYNQMP_PM_CAPABILITY_ACCESS 0x1U
+
enum zynqmp_pm_request_ack {
ZYNQMP_PM_REQUEST_ACK_NO = 1,
ZYNQMP_PM_REQUEST_ACK_BLOCKING,
--
2.7.4
[PATCH 6/7] remoteproc: Add Xilinx ZynqMP R5 remoteproc
There are cortex-r5 processors in Xilinx Zynq UltraScale+
MPSoC platforms. This remoteproc driver is to manage the
R5 processors.
Signed-off-by: Wendy Liang
---
drivers/remoteproc/Kconfig| 9 +
drivers/remoteproc/Makefile | 1 +
drivers/remoteproc/zynqmp_r5_remoteproc.c | 692 ++
3 files changed, 702 insertions(+)
create mode 100644 drivers/remoteproc/zynqmp_r5_remoteproc.c
diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig
index cd1c168..83aac63 100644
--- a/drivers/remoteproc/Kconfig
+++ b/drivers/remoteproc/Kconfig
@@ -158,6 +158,15 @@ config ST_REMOTEPROC
config ST_SLIM_REMOTEPROC
tristate
+config ZYNQMP_R5_REMOTEPROC
+ tristate "ZynqMP_r5 remoteproc support"
+ depends on ARM64 && PM && ARCH_ZYNQMP
+ select RPMSG_VIRTIO
+ select ZYNQMP_FIRMWARE
+ help
+ Say y here to support ZynqMP R5 remote processors via the remote
+ processor framework.
+
endif # REMOTEPROC
endmenu
diff --git a/drivers/remoteproc/Makefile b/drivers/remoteproc/Makefile
index 02627ed..147923c 100644
--- a/drivers/remoteproc/Makefile
+++ b/drivers/remoteproc/Makefile
@@ -23,3 +23,4 @@ qcom_wcnss_pil-y += qcom_wcnss.o
qcom_wcnss_pil-y += qcom_wcnss_iris.o
obj-$(CONFIG_ST_REMOTEPROC)+= st_remoteproc.o
obj-$(CONFIG_ST_SLIM_REMOTEPROC) += st_slim_rproc.o
+obj-$(CONFIG_ZYNQMP_R5_REMOTEPROC) += zynqmp_r5_remoteproc.o
diff --git a/drivers/remoteproc/zynqmp_r5_remoteproc.c
b/drivers/remoteproc/zynqmp_r5_remoteproc.c
new file mode 100644
index 000..7fc3718
--- /dev/null
+++ b/drivers/remoteproc/zynqmp_r5_remoteproc.c
@@ -0,0 +1,692 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Zynq R5 Remote Processor driver
+ *
+ * Copyright (C) 2015 Xilinx, Inc.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "remoteproc_internal.h"
+
+/* IPI reg offsets */
+#define TRIG_OFFSET0x
+#define OBS_OFFSET 0x0004
+#define ISR_OFFSET 0x0010
+#define IMR_OFFSET 0x0014
+#define IER_OFFSET 0x0018
+#define IDR_OFFSET 0x001C
+#define IPI_ALL_MASK 0x0F0F0301
+
+/* RPU IPI mask */
+#define RPU_IPI_INIT_MASK 0x0100
+#define RPU_IPI_MASK(n)(RPU_IPI_INIT_MASK << (n))
+#define RPU_0_IPI_MASK RPU_IPI_MASK(0)
+#define RPU_1_IPI_MASK RPU_IPI_MASK(1)
+
+/* PM proc states */
+#define PM_PROC_STATE_ACTIVE 1u
+
+/* Maximum TCM power nodes IDs */
+#define MAX_TCM_PNODES 4
+
+/* Register access macros */
+#define reg_read(base, reg) \
+ readl(((void __iomem *)(base)) + (reg))
+#define reg_write(base, reg, val) \
+ writel((val), ((void __iomem *)(base)) + (reg))
+
+#define DEFAULT_FIRMWARE_NAME "rproc-rpu-fw"
+
+static bool autoboot __read_mostly;
+
+struct zynqmp_r5_rproc_pdata;
+
+/**
+ * struct zynqmp_r5_rproc_pdata - zynqmp rpu remote processor instance state
+ * @rproc: rproc handle
+ * @workqueue: workqueue for the RPU remoteproc
+ * @ipi_base: virt ptr to IPI channel address registers for APU
+ * @rpu_mode: RPU core configuration
+ * @rpu_id: RPU CPU id
+ * @rpu_pnode_id: RPU CPU power domain id
+ * @mem_pools: list of gen_pool for firmware mmio_sram memory and their
+ * power domain IDs
+ * @mems: list of rproc_mem_entries for firmware
+ * @irq: IRQ number
+ * @ipi_dest_mask: IPI destination mask for the IPI channel
+ */
+struct zynqmp_r5_rproc_pdata {
+ struct rproc *rproc;
+ struct work_struct workqueue;
+ void __iomem *ipi_base;
+ enum rpu_oper_mode rpu_mode;
+ struct list_head mems;
+ u32 ipi_dest_mask;
+ u32 rpu_id;
+ u32 rpu_pnode_id;
+ int irq;
+ u32 tcm_pnode_id[MAX_TCM_PNODES];
+};
+
+/**
+ * r5_boot_addr_config - configure the boot address of R5
+ * @pdata: platform data
+ * @bootmem: boot from LOVEC or HIVEC
+ *
+ * This function will set the RPU boot address
+ */
+static void r5_boot_addr_config(struct zynqmp_r5_rproc_pdata *pdata,
+ enum rpu_boot_mem bootmem)
+{
+ const struct zynqmp_eemi_ops *eemi = zynqmp_pm_get_eemi_ops();
+
+ pr_debug("%s: R5 ID: %d, boot_dev %d\n",
+__func__, pdata->rpu_id, bootmem);
+
+ if (!eemi || !eemi->ioctl) {
+ pr_err("%s: no eemi ioctl operation.\n", __func__);
+ return;
+ }
+ eemi->ioctl(pdata->rpu_pnode_id, IOCTL_RPU_BOOT_ADDR_CONFIG,
+ bootmem, 0, NULL);
+}
+
+/**
+ * r5_mode_config - configure R5 operation mode
+ * @pdata: platform data
+ *
+ * configure R5 to split mode or lockstep mode
+ * based
[PATCH 4/7] firmware: xlnx-zynqmp: Add request/release node
Add request/release resource node EEMI operations.
Signed-off-by: Wendy Liang
---
drivers/firmware/xilinx/zynqmp.c | 30 ++
include/linux/firmware/xlnx-zynqmp.h | 7 +++
2 files changed, 37 insertions(+)
diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
index ce6c746..2e97f60 100644
--- a/drivers/firmware/xilinx/zynqmp.c
+++ b/drivers/firmware/xilinx/zynqmp.c
@@ -447,6 +447,34 @@ static int zynqmp_pm_clock_getparent(u32 clock_id, u32
*parent_id)
return ret;
}
+/**
+ * zynqmp_pm_request_node - PM call to request a node with specific
capabilities
+ * @node: Node ID of the slave
+ * @capabilities: Requested capabilities of the slave
+ * @qos: Quality of service (not supported)
+ * @ack: Flag to specify whether acknowledge is requested
+ *
+ * Return: Returns status, either success or error+reason
+ */
+static int zynqmp_pm_request_node(const u32 node, const u32 capabilities,
+ const u32 qos,
+ const enum zynqmp_pm_request_ack ack)
+{
+ return zynqmp_pm_invoke_fn(PM_REQUEST_NODE, node, capabilities,
+ qos, ack, NULL);
+}
+
+/**
+ * zynqmp_pm_release_node - PM call to release a node
+ * @node: Node ID of the slave
+ *
+ * Return: Returns status, either success or error+reason
+ */
+static int zynqmp_pm_release_node(const u32 node)
+{
+ return zynqmp_pm_invoke_fn(PM_RELEASE_NODE, node, 0, 0, 0, NULL);
+}
+
static const struct zynqmp_eemi_ops eemi_ops = {
.get_api_version = zynqmp_pm_get_api_version,
.ioctl = zynqmp_pm_ioctl,
@@ -460,6 +488,8 @@ static const struct zynqmp_eemi_ops eemi_ops = {
.clock_getrate = zynqmp_pm_clock_getrate,
.clock_setparent = zynqmp_pm_clock_setparent,
.clock_getparent = zynqmp_pm_clock_getparent,
+ .request_node = zynqmp_pm_request_node,
+ .release_node = zynqmp_pm_release_node,
};
/**
diff --git a/include/linux/firmware/xlnx-zynqmp.h
b/include/linux/firmware/xlnx-zynqmp.h
index 83ebadf..02067a3 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -54,6 +54,8 @@ enum pm_api_id {
PM_CLOCK_GETRATE,
PM_CLOCK_SETPARENT,
PM_CLOCK_GETPARENT,
+ PM_REQUEST_NODE = 13,
+ PM_RELEASE_NODE = 14,
};
/* PMU-FW return status codes */
@@ -130,6 +132,11 @@ struct zynqmp_eemi_ops {
int (*clock_getrate)(u32 clock_id, u64 *rate);
int (*clock_setparent)(u32 clock_id, u32 parent_id);
int (*clock_getparent)(u32 clock_id, u32 *parent_id);
+ int (*request_node)(const u32 node,
+ const u32 capabilities,
+ const u32 qos,
+ const enum zynqmp_pm_request_ack ack);
+ int (*release_node)(const u32 node);
};
#if IS_REACHABLE(CONFIG_ARCH_ZYNQMP)
--
2.7.4
[PATCH 7/7] Documentation: devicetree: Add Xilinx R5 rproc binding
Add device tree binding for Xilinx Cortex-r5 remoteproc.
Signed-off-by: Wendy Liang
---
.../remoteproc/xlnx,zynqmp-r5-remoteproc.txt | 81 ++
1 file changed, 81 insertions(+)
create mode 100644
Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5-remoteproc.txt
diff --git
a/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5-remoteproc.txt
b/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5-remoteproc.txt
new file mode 100644
index 000..3940019
--- /dev/null
+++ b/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5-remoteproc.txt
@@ -0,0 +1,81 @@
+Xilinx ARM Cortex A53-R5 remoteproc driver
+==
+
+ZynqMP family of devices use two Cortex R5 processors to help with various
+low power / real time tasks.
+
+This driver requires specific ZynqMP hardware design.
+
+ZynqMP R5 RemoteProc Device Node:
+=
+A zynqmp_r5_remoteproc device node is used to represent a R5 IP instance
+within ZynqMP SoC.
+
+Required properties:
+
+ - compatible : Should be "xlnx,zynqmp-r5-remoteproc-1.0"
+ - reg : Address and length of the register set for the device. It
+contains in the same order as described reg-names
+ - reg-names: Contain the register set names.
+ "tcm_a" and "tcm_b" for TCM memories.
+ If the user uses the remoteproc driver with the RPMsg kernel
+ driver,"ipi" for the IPI register used to communicate with RPU
+ is also required.
+ Otherwise, if user only uses the remoteproc driver to boot RPU
+ firmware, "ipi" is not required.
+ - tcm-pnode-id: TCM resources power nodes IDs which are used to request TCM
+ resources for the remoteproc driver to access.
+ - rpu-pnode-id : RPU power node id which is used by the remoteproc driver
+ to start RPU or shut it down.
+
+Optional properties:
+
+ - core_conf : R5 core configuration (valid string - split0 or split1 or
+ lock-step), default is lock-step.
+ - memory-region: memories regions for RPU executable and DMA memory.
+ - interrupts : Interrupt mapping for remoteproc IPI. It is required if the
+user uses the remoteproc driver with the RPMsg kernel driver.
+ - interrupt-parent : Phandle for the interrupt controller. It is required if
+ the user uses the remoteproc driver with the RPMsg kernel
+ kernel driver.
+
+Example:
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ rproc_0_fw_reserved: rproc@3ed00 {
+ compatible = "rproc-prog-memory";
+ no-map;
+ reg = <0x0 0x3ed0 0x0 0x4>;
+ };
+ rproc_0_dma_reserved: rproc@3ed40 {
+ compatible = "shared-dma-pool";
+ no-map;
+ reg = <0x0 0x3ed4 0x0 0x8>;
+ };
+ };
+
+ firmware {
+ zynqmp_firmware: zynqmp-firmware {
+ compatible = "xlnx,zynqmp-firmware";
+ method = "smc";
+ };
+ };
+
+ zynqmp-r5-remoteproc@0 {
+ compatible = "xlnx,zynqmp-r5-remoteproc-1.0";
+ reg = <0x0 0xFFE0 0x0 0x1>,
+ <0x0 0xFFE2 0x0 0x1>,
+ <0x0 0xff34 0x0 0x100>;
+ reg-names = "tcm_a", "tcm_b", "ipi";
+ dma-ranges;
+ core_conf = "split0";
+ memory-region = <_0_fw_reserved>,
+ <_0_dma_reserved>;
+ tcm-pnode-id = <0xf>, <0x10>;
+ rpu-pnode-id = <0x7>;
+ interrupt-parent = <>;
+ interrupts = <0 29 4>;
+ } ;
--
2.7.4
[PATCH 1/7] firmware: xlnx-zynqmp: Add RPU ioctl enums
Add ZynqMP firmware ioctl enums for RPU configuration.
Signed-off-by: Wendy Liang
---
include/linux/firmware/xlnx-zynqmp.h | 19 +++
1 file changed, 19 insertions(+)
diff --git a/include/linux/firmware/xlnx-zynqmp.h
b/include/linux/firmware/xlnx-zynqmp.h
index a3ef7d6..9c4258f 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -59,6 +59,10 @@ enum pm_ret_status {
};
enum pm_ioctl_id {
+ IOCTL_GET_RPU_OPER_MODE = 0,
+ IOCTL_SET_RPU_OPER_MODE,
+ IOCTL_RPU_BOOT_ADDR_CONFIG,
+ IOCTL_TCM_COMB_CONFIG,
IOCTL_SET_PLL_FRAC_MODE = 8,
IOCTL_GET_PLL_FRAC_MODE,
IOCTL_SET_PLL_FRAC_DATA,
@@ -75,6 +79,21 @@ enum pm_query_id {
PM_QID_CLOCK_GET_NUM_CLOCKS = 12,
};
+enum rpu_oper_mode {
+ PM_RPU_MODE_LOCKSTEP,
+ PM_RPU_MODE_SPLIT,
+};
+
+enum rpu_boot_mem {
+ PM_RPU_BOOTMEM_LOVEC,
+ PM_RPU_BOOTMEM_HIVEC,
+};
+
+enum rpu_tcm_comb {
+ PM_RPU_TCM_SPLIT,
+ PM_RPU_TCM_COMB,
+};
+
/**
* struct zynqmp_pm_query_data - PM query data
* @qid: query ID
--
2.7.4
[PATCH 7/7] Documentation: devicetree: Add Xilinx R5 rproc binding
Add device tree binding for Xilinx Cortex-r5 remoteproc.
Signed-off-by: Wendy Liang
---
.../remoteproc/xlnx,zynqmp-r5-remoteproc.txt | 81 ++
1 file changed, 81 insertions(+)
create mode 100644
Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5-remoteproc.txt
diff --git
a/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5-remoteproc.txt
b/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5-remoteproc.txt
new file mode 100644
index 000..3940019
--- /dev/null
+++ b/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5-remoteproc.txt
@@ -0,0 +1,81 @@
+Xilinx ARM Cortex A53-R5 remoteproc driver
+==
+
+ZynqMP family of devices use two Cortex R5 processors to help with various
+low power / real time tasks.
+
+This driver requires specific ZynqMP hardware design.
+
+ZynqMP R5 RemoteProc Device Node:
+=
+A zynqmp_r5_remoteproc device node is used to represent a R5 IP instance
+within ZynqMP SoC.
+
+Required properties:
+
+ - compatible : Should be "xlnx,zynqmp-r5-remoteproc-1.0"
+ - reg : Address and length of the register set for the device. It
+contains in the same order as described reg-names
+ - reg-names: Contain the register set names.
+ "tcm_a" and "tcm_b" for TCM memories.
+ If the user uses the remoteproc driver with the RPMsg kernel
+ driver,"ipi" for the IPI register used to communicate with RPU
+ is also required.
+ Otherwise, if user only uses the remoteproc driver to boot RPU
+ firmware, "ipi" is not required.
+ - tcm-pnode-id: TCM resources power nodes IDs which are used to request TCM
+ resources for the remoteproc driver to access.
+ - rpu-pnode-id : RPU power node id which is used by the remoteproc driver
+ to start RPU or shut it down.
+
+Optional properties:
+
+ - core_conf : R5 core configuration (valid string - split0 or split1 or
+ lock-step), default is lock-step.
+ - memory-region: memories regions for RPU executable and DMA memory.
+ - interrupts : Interrupt mapping for remoteproc IPI. It is required if the
+user uses the remoteproc driver with the RPMsg kernel driver.
+ - interrupt-parent : Phandle for the interrupt controller. It is required if
+ the user uses the remoteproc driver with the RPMsg kernel
+ kernel driver.
+
+Example:
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ rproc_0_fw_reserved: rproc@3ed00 {
+ compatible = "rproc-prog-memory";
+ no-map;
+ reg = <0x0 0x3ed0 0x0 0x4>;
+ };
+ rproc_0_dma_reserved: rproc@3ed40 {
+ compatible = "shared-dma-pool";
+ no-map;
+ reg = <0x0 0x3ed4 0x0 0x8>;
+ };
+ };
+
+ firmware {
+ zynqmp_firmware: zynqmp-firmware {
+ compatible = "xlnx,zynqmp-firmware";
+ method = "smc";
+ };
+ };
+
+ zynqmp-r5-remoteproc@0 {
+ compatible = "xlnx,zynqmp-r5-remoteproc-1.0";
+ reg = <0x0 0xFFE0 0x0 0x1>,
+ <0x0 0xFFE2 0x0 0x1>,
+ <0x0 0xff34 0x0 0x100>;
+ reg-names = "tcm_a", "tcm_b", "ipi";
+ dma-ranges;
+ core_conf = "split0";
+ memory-region = <_0_fw_reserved>,
+ <_0_dma_reserved>;
+ tcm-pnode-id = <0xf>, <0x10>;
+ rpu-pnode-id = <0x7>;
+ interrupt-parent = <>;
+ interrupts = <0 29 4>;
+ } ;
--
2.7.4
[PATCH 1/7] firmware: xlnx-zynqmp: Add RPU ioctl enums
Add ZynqMP firmware ioctl enums for RPU configuration.
Signed-off-by: Wendy Liang
---
include/linux/firmware/xlnx-zynqmp.h | 19 +++
1 file changed, 19 insertions(+)
diff --git a/include/linux/firmware/xlnx-zynqmp.h
b/include/linux/firmware/xlnx-zynqmp.h
index a3ef7d6..9c4258f 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -59,6 +59,10 @@ enum pm_ret_status {
};
enum pm_ioctl_id {
+ IOCTL_GET_RPU_OPER_MODE = 0,
+ IOCTL_SET_RPU_OPER_MODE,
+ IOCTL_RPU_BOOT_ADDR_CONFIG,
+ IOCTL_TCM_COMB_CONFIG,
IOCTL_SET_PLL_FRAC_MODE = 8,
IOCTL_GET_PLL_FRAC_MODE,
IOCTL_SET_PLL_FRAC_DATA,
@@ -75,6 +79,21 @@ enum pm_query_id {
PM_QID_CLOCK_GET_NUM_CLOCKS = 12,
};
+enum rpu_oper_mode {
+ PM_RPU_MODE_LOCKSTEP,
+ PM_RPU_MODE_SPLIT,
+};
+
+enum rpu_boot_mem {
+ PM_RPU_BOOTMEM_LOVEC,
+ PM_RPU_BOOTMEM_HIVEC,
+};
+
+enum rpu_tcm_comb {
+ PM_RPU_TCM_SPLIT,
+ PM_RPU_TCM_COMB,
+};
+
/**
* struct zynqmp_pm_query_data - PM query data
* @qid: query ID
--
2.7.4
[PATCH 2/7] firmware: xlnx-zynqmp: Add request ack enums
Add firmware request ack enums which will be used in firmware
request calls.
Signed-off-by: Wendy Liang
---
include/linux/firmware/xlnx-zynqmp.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/include/linux/firmware/xlnx-zynqmp.h
b/include/linux/firmware/xlnx-zynqmp.h
index 9c4258f..e3b7292 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -32,6 +32,12 @@
/* Number of 32bits values in payload */
#define PAYLOAD_ARG_CNT4U
+enum zynqmp_pm_request_ack {
+ ZYNQMP_PM_REQUEST_ACK_NO = 1,
+ ZYNQMP_PM_REQUEST_ACK_BLOCKING,
+ ZYNQMP_PM_REQUEST_ACK_NON_BLOCKING,
+};
+
enum pm_api_id {
PM_GET_API_VERSION = 1,
PM_IOCTL = 34,
--
2.7.4
[PATCH 2/7] firmware: xlnx-zynqmp: Add request ack enums
Add firmware request ack enums which will be used in firmware
request calls.
Signed-off-by: Wendy Liang
---
include/linux/firmware/xlnx-zynqmp.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/include/linux/firmware/xlnx-zynqmp.h
b/include/linux/firmware/xlnx-zynqmp.h
index 9c4258f..e3b7292 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -32,6 +32,12 @@
/* Number of 32bits values in payload */
#define PAYLOAD_ARG_CNT4U
+enum zynqmp_pm_request_ack {
+ ZYNQMP_PM_REQUEST_ACK_NO = 1,
+ ZYNQMP_PM_REQUEST_ACK_BLOCKING,
+ ZYNQMP_PM_REQUEST_ACK_NON_BLOCKING,
+};
+
enum pm_api_id {
PM_GET_API_VERSION = 1,
PM_IOCTL = 34,
--
2.7.4
[PATCH 0/7] Add Xilinx ZynqMP R5 remoteproc driver
There are Cortex-R5 processors on Xilinx ZynqMP UltraScale+ MPSoC. This patch is to add an Xilinx ZynqMP R5 remoteproc driver to enable Linux kernel to bringup R5, and enable communication between Linux kernel and R5. This patch series is based on top of Xilinx firmware patch set: https://patchwork.kernel.org/cover/10555405/ Wendy Liang (7): firmware: xlnx-zynqmp: Add RPU ioctl enums firmware: xlnx-zynqmp: Add request ack enums firmware: xilinx-zynqmp: Add request access capability macro firmware: xlnx-zynqmp: Add request/release node firmware: xlnx-zynqmp: Add shutdown/wakeup request remoteproc: Add Xilinx ZynqMP R5 remoteproc Documentation: devicetree: Add Xilinx R5 rproc binding .../remoteproc/xlnx,zynqmp-r5-remoteproc.txt | 81 +++ drivers/firmware/xilinx/zynqmp.c | 65 ++ drivers/remoteproc/Kconfig | 9 + drivers/remoteproc/Makefile| 1 + drivers/remoteproc/zynqmp_r5_remoteproc.c | 692 + include/linux/firmware/xlnx-zynqmp.h | 43 ++ 6 files changed, 891 insertions(+) create mode 100644 Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5-remoteproc.txt create mode 100644 drivers/remoteproc/zynqmp_r5_remoteproc.c -- 2.7.4
[PATCH 0/7] Add Xilinx ZynqMP R5 remoteproc driver
There are Cortex-R5 processors on Xilinx ZynqMP UltraScale+ MPSoC. This patch is to add an Xilinx ZynqMP R5 remoteproc driver to enable Linux kernel to bringup R5, and enable communication between Linux kernel and R5. This patch series is based on top of Xilinx firmware patch set: https://patchwork.kernel.org/cover/10555405/ Wendy Liang (7): firmware: xlnx-zynqmp: Add RPU ioctl enums firmware: xlnx-zynqmp: Add request ack enums firmware: xilinx-zynqmp: Add request access capability macro firmware: xlnx-zynqmp: Add request/release node firmware: xlnx-zynqmp: Add shutdown/wakeup request remoteproc: Add Xilinx ZynqMP R5 remoteproc Documentation: devicetree: Add Xilinx R5 rproc binding .../remoteproc/xlnx,zynqmp-r5-remoteproc.txt | 81 +++ drivers/firmware/xilinx/zynqmp.c | 65 ++ drivers/remoteproc/Kconfig | 9 + drivers/remoteproc/Makefile| 1 + drivers/remoteproc/zynqmp_r5_remoteproc.c | 692 + include/linux/firmware/xlnx-zynqmp.h | 43 ++ 6 files changed, 891 insertions(+) create mode 100644 Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5-remoteproc.txt create mode 100644 drivers/remoteproc/zynqmp_r5_remoteproc.c -- 2.7.4
