s/exceution/execution/
s/possibe/possible/
s/manupulations/manipulations/
Signed-off-by: Xie XiuQi
---
kernel/sched/psi.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/kernel/sched/psi.c b/kernel/sched/psi.c
index 967732c0766c..7c800be47c6f 100644
--- a/kernel/sched
(not in a function); did you mean ‘tegra_ivc’?
{ .compatible = "nvidia,tegra186-bpmp", .data = _soc },
^~~~
tegra_ivc
Xie XiuQi (2):
soc/tegra: fuse: Fix build with Tegra234 con
pport on Tegra234")
Signed-off-by: Xie XiuQi
---
drivers/firmware/tegra/Makefile | 1 +
drivers/firmware/tegra/bpmp-private.h | 3 ++-
drivers/firmware/tegra/bpmp.c | 3 ++-
3 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/firmware/tegra/Makefile b/driver
: Add Tegra234 support")
Signed-off-by: Xie XiuQi
---
drivers/soc/tegra/fuse/fuse-tegra30.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/soc/tegra/fuse/fuse-tegra30.c
b/drivers/soc/tegra/fuse/fuse-tegra30.c
index 9ea7f0168457..c1aa7815bd6e 100644
--- a/drivers
uctrl and udev are unused after commit 9632a6b4b747
("scsi: qedi: Move LL2 producer index processing in BH.")
Remove them.
Signed-off-by: Xie XiuQi
---
drivers/scsi/qedi/qedi_main.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/drivers/scsi/qedi/qedi_main.c b/drivers
byte_offset is unsigned integer, it's always >= 0, so remove this
meaningless checking.
Signed-off-by: Xie XiuQi
---
drivers/input/touchscreen/atmel_mxt_ts.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/input/touchscreen/atmel_mxt_ts.c
b/drivers/input/touchscr
/0x590 [ixgbe]
ixgbe_service_task+0xc20/0x1f78 [ixgbe]
process_one_work+0x8f0/0xf18
worker_thread+0x430/0x6d0
kthread+0x218/0x238
ret_from_fork+0x10/0x18
Reported-by: Hulk Robot
Signed-off-by: Xie XiuQi
---
drivers/net/ethernet/intel/ixgbe/ixgbe_common.c | 2 +-
1 file changed, 1 insertion
The following commit has been merged into the sched/core branch of tip:
Commit-ID: f080d93e1d419099a99d7473ed532289ca8dc717
Gitweb:
https://git.kernel.org/tip/f080d93e1d419099a99d7473ed532289ca8dc717
Author:Xie XiuQi
AuthorDate:Tue, 14 Apr 2020 20:57:21 +08:00
Committer
Hi James,
Sorry for reply late.
On 2020/4/14 22:53, James Morse wrote:
> Hi Xie,
>
> On 14/04/2020 13:39, Xie XiuQi wrote:
>> On 2020/4/14 20:16, James Morse wrote:
>>> On 14/04/2020 11:59, Mark Rutland wrote:
>>>> On Fri, Apr 10, 2020 at 09:52:45AM +0800, Xi
+ mutex_unlock();
> }
> - mutex_unlock();
> }
>
> static int ep_alloc(struct eventpoll **pep)
> @@ -1030,6 +1106,8 @@ static int ep_alloc(struct eventpoll **pep)
> ep->rbr = RB_ROOT_CACHED;
> ep->ovflist = EP_UNACTIVE_PTR;
> ep->user = user;
> + INIT_LIST_HEAD(>visited_list_link);
> + refcount_set(>ref, 1);
>
> *pep = ep;
>
> @@ -2018,7 +2096,7 @@ static int ep_loop_check(struct eventpoll *ep, struct
> file *file)
> list_for_each_entry_safe(ep_cur, ep_next, _list,
> visited_list_link) {
> ep_cur->visited = 0;
> - list_del(_cur->visited_list_link);
> + list_del_init(_cur->visited_list_link);
> }
> return ret;
> }
>
--
Thanks,
Xie XiuQi
Commit-ID: a860fa7b96e1a1c974556327aa1aee852d434c21
Gitweb: https://git.kernel.org/tip/a860fa7b96e1a1c974556327aa1aee852d434c21
Author: Xie XiuQi
AuthorDate: Sat, 20 Apr 2019 16:34:16 +0800
Committer: Ingo Molnar
CommitDate: Thu, 25 Apr 2019 19:58:54 +0200
sched/numa: Fix a possible
Commit-ID: 993efef2483bde15fd33ec5fba5464597c2d8124
Gitweb: https://git.kernel.org/tip/993efef2483bde15fd33ec5fba5464597c2d8124
Author: Xie XiuQi
AuthorDate: Sat, 20 Apr 2019 16:34:16 +0800
Committer: Ingo Molnar
CommitDate: Thu, 25 Apr 2019 19:58:35 +0200
sched/numa: Fix a possible
Hi Peter,
On 2019/4/25 16:00, Peter Zijlstra wrote:
> On Thu, Apr 25, 2019 at 11:52:28AM +0800, Xie XiuQi wrote:
>> On 2019/4/24 2:44, Peter Zijlstra wrote:
>
>>> I'll try and come up with a better Changelog tomorrow.
>
> I actually did, but forgot to send ou
Hi Peter,
Thanks for your comments.
On 2019/4/24 2:44, Peter Zijlstra wrote:
> On Sat, Apr 20, 2019 at 04:34:16PM +0800, Xie XiuQi wrote:
>> We meet a divide error on 3.10.0 kernel, the error message is bellow:
>
> That is a _realll_ old kernel. I would urge you
ror was triggerred at the div operation:
task_numa_placement:
runtime = numa_get_avg_runtime(p, );
f_weight = div64_u64(runtime << 16, period + 1); // divide error here
In this patch, we make sure period is not less than 0 to avoid this
divide error.
Signed-off-by: Xie XiuQi
Cc
k: https://syzkaller.appspot.com/bug?extid=a24c397a29ad22d86c98
>> compiler: gcc (GCC) 8.0.1 20180413 (experimental)
>>
>> Unfortunately, I don't have any reproducer for this crash yet.
>
> Is there a chance of getti
_decayed(cfs_rq) &&
> + rq->tmp_alone_branch == >leaf_cfs_rq_list)
> list_del_leaf_cfs_rq(cfs_rq);
>
> /* Don't need periodic decay once load/util_avg are null */
>
> .
>
--
Thanks,
Xie XiuQi
fore delete it
from list.
Reported-by: Zhipeng Xie
Cc: Bin Li
Cc: [4.10+]
Fixes: 9c2791f936ef (sched/fair: Fix hierarchical order in rq->leaf_cfs_rq_list)
Signed-off-by: Xie XiuQi
Tested-by: Zhipeng Xie
---
kernel/sched/fair.c | 5 +
1 file changed, 5 insertions(+)
diff --git a
ust because it is safer for an -rc
> cycle even though if the patch below would do delaying the fix for a
> couple of -rc (to get it tested across ACPI ARM64 NUMA platforms) is
> not a disaster.
I tested this patch on my arm board, it works.
--
Thanks,
Xie XiuQi
>
> Lorenzo
>
&
ust because it is safer for an -rc
> cycle even though if the patch below would do delaying the fix for a
> couple of -rc (to get it tested across ACPI ARM64 NUMA platforms) is
> not a disaster.
I tested this patch on my arm board, it works.
--
Thanks,
Xie XiuQi
>
> Lorenzo
>
&
Hi Michal,
On 2018/6/19 20:07, Michal Hocko wrote:
> On Tue 19-06-18 20:03:07, Xie XiuQi wrote:
> [...]
>> I tested on a arm board with 128 cores 4 numa nodes, but I set
>> CONFIG_NR_CPUS=72.
>> Then node 3 is not be created, because node 3 has no memory, and no cpu.
&g
Hi Michal,
On 2018/6/19 20:07, Michal Hocko wrote:
> On Tue 19-06-18 20:03:07, Xie XiuQi wrote:
> [...]
>> I tested on a arm board with 128 cores 4 numa nodes, but I set
>> CONFIG_NR_CPUS=72.
>> Then node 3 is not be created, because node 3 has no memory, and no cpu.
&g
oot_ops = kzalloc_node(sizeof(*root_ops), GFP_KERNEL, node);
182 if (!root_ops) {
183 kfree(ri);
184 return NULL;
185 }
186
187 ri->cfg = pci_acpi_setup_ecam_mapping(root);
188 if (!ri->cfg) {
189 kfree(ri);
190
oot_ops = kzalloc_node(sizeof(*root_ops), GFP_KERNEL, node);
182 if (!root_ops) {
183 kfree(ri);
184 return NULL;
185 }
186
187 ri->cfg = pci_acpi_setup_ecam_mapping(root);
188 if (!ri->cfg) {
189 kfree(ri);
190
Hi Michal,
On 2018/6/11 16:52, Michal Hocko wrote:
> On Mon 11-06-18 11:23:18, Xie XiuQi wrote:
>> Hi Michal,
>>
>> On 2018/6/7 20:21, Michal Hocko wrote:
>>> On Thu 07-06-18 19:55:53, Hanjun Guo wrote:
>>>> On 2018/6/7 18:55, Michal Hocko wrote:
>
Hi Michal,
On 2018/6/11 16:52, Michal Hocko wrote:
> On Mon 11-06-18 11:23:18, Xie XiuQi wrote:
>> Hi Michal,
>>
>> On 2018/6/7 20:21, Michal Hocko wrote:
>>> On Thu 07-06-18 19:55:53, Hanjun Guo wrote:
>>>> On 2018/6/7 18:55, Michal Hocko wrote:
>
SP: 881196947a90
[ 120.776780] CR2: 2088
[ 120.780116] ---[ end trace 89f801c36550734f ]---
[ 120.978922] Kernel panic - not syncing: Fatal exception
[ 120.984186] Kernel Offset: 0x3380 from 0xffff8100 (relocation
range: 0x8000-0xbfff)
[ 121.209501] ---[ end Kernel panic - not syncing: Fatal exception ]---
--
Thanks,
Xie XiuQi
SP: 881196947a90
[ 120.776780] CR2: 2088
[ 120.780116] ---[ end trace 89f801c36550734f ]---
[ 120.978922] Kernel panic - not syncing: Fatal exception
[ 120.984186] Kernel Offset: 0x3380 from 0xffff8100 (relocation
range: 0x8000-0xbfff)
[ 121.209501] ---[ end Kernel panic - not syncing: Fatal exception ]---
--
Thanks,
Xie XiuQi
340
[ 28.093577] kernel_init+0x18/0x118
[ 28.097052] ret_from_fork+0x10/0x1c
[ 28.100614] Code: 7100047f 321902a4 1a950095 b5000602 (b9400803)
[ 28.106740] ---[ end trace e32df44e6e1c3a4b ]---
Signed-off-by: Xie XiuQi
Tested-by: Huiqiang Wang
Cc: Hanjun Guo
Cc: Tomasz Nowicki
Cc: Xishi
)
[ 25.980162] ---[ end trace 64f0893eb21ec283 ]---
[ 25.984765] Kernel panic - not syncing: Fatal exception
Xie XiuQi (2):
arm64: avoid alloc memory on offline node
drivers: check numa node's online status in dev_to_node
arch/arm64/kernel/pci.c | 3 +++
include/linux/device.h | 7
)
[ 25.980162] ---[ end trace 64f0893eb21ec283 ]---
[ 25.984765] Kernel panic - not syncing: Fatal exception
Xie XiuQi (2):
arm64: avoid alloc memory on offline node
drivers: check numa node's online status in dev_to_node
arch/arm64/kernel/pci.c | 3 +++
include/linux/device.h | 7
340
[ 28.093577] kernel_init+0x18/0x118
[ 28.097052] ret_from_fork+0x10/0x1c
[ 28.100614] Code: 7100047f 321902a4 1a950095 b5000602 (b9400803)
[ 28.106740] ---[ end trace e32df44e6e1c3a4b ]---
Signed-off-by: Xie XiuQi
Tested-by: Huiqiang Wang
Cc: Hanjun Guo
Cc: Tomasz Nowicki
Cc: Xishi
)
[ 25.980162] ---[ end trace 64f0893eb21ec283 ]---
[ 25.984765] Kernel panic - not syncing: Fatal exception
Signed-off-by: Xie XiuQi
Tested-by: Huiqiang Wang
Cc: Hanjun Guo
Cc: Tomasz Nowicki
Cc: Xishi Qiu
---
arch/arm64/kernel/pci.c | 3 +++
1 file changed, 3 insertions(+)
diff --git
)
[ 25.980162] ---[ end trace 64f0893eb21ec283 ]---
[ 25.984765] Kernel panic - not syncing: Fatal exception
Signed-off-by: Xie XiuQi
Tested-by: Huiqiang Wang
Cc: Hanjun Guo
Cc: Tomasz Nowicki
Cc: Xishi Qiu
---
arch/arm64/kernel/pci.c | 3 +++
1 file changed, 3 insertions(+)
diff --git
Hi Boris,
Thanks for your comments.
On 2018/2/7 18:31, Borislav Petkov wrote:
> On Fri, Jan 26, 2018 at 08:31:24PM +0800, Xie XiuQi wrote:
>> Add a notify chain for process memory section, with
>> which other modules might do error recovery.
>>
>> Signed-off-by: Xie
Hi Boris,
Thanks for your comments.
On 2018/2/7 18:31, Borislav Petkov wrote:
> On Fri, Jan 26, 2018 at 08:31:24PM +0800, Xie XiuQi wrote:
>> Add a notify chain for process memory section, with
>> which other modules might do error recovery.
>>
>> Signed-off-by: Xi
Hi James,
Sorry for reply late.
On 2018/2/8 3:03, James Morse wrote:
> Hi Xie XiuQi,
>
> On 30/01/18 19:19, James Morse wrote:
>> On 26/01/18 12:31, Xie XiuQi wrote:
>>> With ARM v8.2 RAS Extension, SEA are usually triggered when memory errors
>>> are consumed.
Hi James,
Sorry for reply late.
On 2018/2/8 3:03, James Morse wrote:
> Hi Xie XiuQi,
>
> On 30/01/18 19:19, James Morse wrote:
>> On 26/01/18 12:31, Xie XiuQi wrote:
>>> With ARM v8.2 RAS Extension, SEA are usually triggered when memory errors
>>> are consumed.
or recoery support
+ *
+ * Copyright 2017 Huawei Technologies Co., Ltd.
+ * Author: Xie XiuQi <xiexi...@huawei.com>
+ * Author: Wang Xiongfeng <wangxiongfe...@huawei.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU
.f0f18da
--- /dev/null
+++ b/arch/arm64/include/asm/ras.h
@@ -0,0 +1,23 @@
+/*
+ * ARM64 SEA error recoery support
+ *
+ * Copyright 2017 Huawei Technologies Co., Ltd.
+ * Author: Xie XiuQi
+ * Author: Wang Xiongfeng
+ *
+ * This program is free software; you can redistribute it and/or
+
Add a notify chain for process memory section, with
which other modules might do error recovery.
Signed-off-by: Xie XiuQi <xiexi...@huawei.com>
Tested-by: Wang Xiongfeng <wangxiongfe...@huawei.com>
Tested-by: Tyler Baicar <tbai...@codeaurora.org>
---
drivers/acp
Add a notify chain for process memory section, with
which other modules might do error recovery.
Signed-off-by: Xie XiuQi
Tested-by: Wang Xiongfeng
Tested-by: Tyler Baicar
---
drivers/acpi/apei/ghes.c | 10 ++
include/acpi/ghes.h | 8
2 files changed, 18 insertions
ctly
https://lkml.org/lkml/2017/9/1/189
Xie XiuQi (3):
arm64/ras: support sea error recovery
GHES: add a notify chain for process memory section
arm64/ras: save error address from memory section for recovery
arch/arm64/Kconfig | 11 +++
arch/arm64/include/asm/ras.h |
In some platform, when SEA triggerred, physical address might be
reported by memory section, so we save it for error recovery later.
Signed-off-by: Xie XiuQi <xiexi...@huawei.com>
Tested-by: Wang Xiongfeng <wangxiongfe...@huawei.com>
Tested-by: Tyler Baicar <tbai...@codeaurora
ctly
https://lkml.org/lkml/2017/9/1/189
Xie XiuQi (3):
arm64/ras: support sea error recovery
GHES: add a notify chain for process memory section
arm64/ras: save error address from memory section for recovery
arch/arm64/Kconfig | 11 +++
arch/arm64/include/asm/ras.h |
In some platform, when SEA triggerred, physical address might be
reported by memory section, so we save it for error recovery later.
Signed-off-by: Xie XiuQi
Tested-by: Wang Xiongfeng
Tested-by: Tyler Baicar
---
arch/arm64/kernel/ras.c | 31 +++
1 file changed, 31
1
> +#define CPER_ARM_BUS_ERROR2
> +#define CPER_ARM_VENDOR_ERROR3
--
Thanks,
Xie XiuQi
R_ARM_BUS_ERROR2
> +#define CPER_ARM_VENDOR_ERROR3
--
Thanks,
Xie XiuQi
dr;
> arm64_notify_die("", regs, , esr);
>
> - return ret;
> + return 0;
It looks good to me. do_sea() has done all necessary action for SEA, so it
should always return 0,
no matter ghes_notify_sea() return true or false.
Reviewed-by: Xie XiuQi <xiexi...@huawei.com>
> }
>
> static const struct fault_info fault_info[] = {
> --
> 2.10.1
>
--
Thanks,
Xie XiuQi
fy_die("", regs, , esr);
>
> - return ret;
> + return 0;
It looks good to me. do_sea() has done all necessary action for SEA, so it
should always return 0,
no matter ghes_notify_sea() return true or false.
Reviewed-by: Xie XiuQi
> }
>
> static const struct fault_info fault_info[] = {
> --
> 2.10.1
>
--
Thanks,
Xie XiuQi
Commit-ID: e085ac7a6ddbd746966083c5e13aa290c3e9a253
Gitweb: https://git.kernel.org/tip/e085ac7a6ddbd746966083c5e13aa290c3e9a253
Author: Xie XiuQi <xiexi...@huawei.com>
AuthorDate: Mon, 4 Dec 2017 17:54:37 +0100
Committer: Thomas Gleixner <t...@linutronix.de>
CommitDate: Mon
Commit-ID: e085ac7a6ddbd746966083c5e13aa290c3e9a253
Gitweb: https://git.kernel.org/tip/e085ac7a6ddbd746966083c5e13aa290c3e9a253
Author: Xie XiuQi
AuthorDate: Mon, 4 Dec 2017 17:54:37 +0100
Committer: Thomas Gleixner
CommitDate: Mon, 4 Dec 2017 20:38:44 +0100
x86/MCE: Extend table
ment")
Signed-off-by: Xie XiuQi <xiexi...@huawei.com>
Acked-by: Jesper Dangaard Brouer <bro...@redhat.com>
Acked-by: Steven Rostedt (VMware) <rost...@goodmis.org>
---
include/trace/events/xdp.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/trace/events/xdp.h b/
) \
^~
./include/linux/tracepoint.h:354:4: note: in expansion of macro ‘PARAMS’
PARAMS(void *__data, proto), \
^~
Reported-by: Huang Daode
Cc: Hanjun Guo
Fixes: 8d3b778ff544 ("xdp: tracepoint xdp_redirect also need a map argument")
Signed-off-by: Xie XiuQi
Acked-by: Jesper Danga
'll resend soon.
>> Fixes: 8d3b778ff544 ("xdp: tracepoint xdp_redirect also need a map argument")
>>
>> Acked-by: Jesper Dangaard Brouer <bro...@redhat.com>
> Thanks,
> Daniel
--
Thanks,
Xie XiuQi
'll resend soon.
>> Fixes: 8d3b778ff544 ("xdp: tracepoint xdp_redirect also need a map argument")
>>
>> Acked-by: Jesper Dangaard Brouer
> Thanks,
> Daniel
--
Thanks,
Xie XiuQi
) \
^~
./include/linux/tracepoint.h:354:4: note: in expansion of macro ‘PARAMS’
PARAMS(void *__data, proto), \
^~
Reported-by: Huang Daode <huangda...@hisilicon.com>
Cc: Hanjun Guo <guohan...@huawei.com>
Signed-off-by: Xie XiuQi <xiexi...@huawei.com>
---
include/trace/eve
) \
^~
./include/linux/tracepoint.h:354:4: note: in expansion of macro ‘PARAMS’
PARAMS(void *__data, proto), \
^~
Reported-by: Huang Daode
Cc: Hanjun Guo
Signed-off-by: Xie XiuQi
---
include/trace/events/xdp.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/trace/events/xdp.h b
was reported
as a corrected machine check (CMC).
So we could merge this two case, and just remove the S=0 check for SRAO
in mce_severity().
---
v2: add OVER=0 check and merge MCE and CMC case.
Signed-off-by: Xie XiuQi <xiexi...@huawei.com>
Tested-by: Chen Wei <chenwe...@huawei.com>
Revie
was reported
as a corrected machine check (CMC).
So we could merge this two case, and just remove the S=0 check for SRAO
in mce_severity().
---
v2: add OVER=0 check and merge MCE and CMC case.
Signed-off-by: Xie XiuQi
Tested-by: Chen Wei
Reviewed-by: Tony Luck
---
arch/x86/kernel/cpu/mcheck/mce
ected machine check (CMC).
As the description in SDM, I think this flag could be used to determine whether
MCE or CMC was triggered. So we could merge this two case in one and just
remove the S=0 check for SRAO.
How about this patch?
>From a06b2a781a86e3b1fe241591b53f7a6d33d63331 Mon Sep 17 00:00:00
ected machine check (CMC).
As the description in SDM, I think this flag could be used to determine whether
MCE or CMC was triggered. So we could merge this two case in one and just
remove the S=0 check for SRAO.
How about this patch?
>From a06b2a781a86e3b1fe241591b53f7a6d33d63331 Mon Sep 17 00:00:00 2001
From: X
.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
>
--
Thanks,
Xie XiuQi
.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
>
--
Thanks,
Xie XiuQi
Hi Tony,
On 2017/11/15 2:51, Luck, Tony wrote:
> On Tue, Nov 14, 2017 at 01:55:11PM +0800, Xie XiuQi wrote:
>> +/* known AO MCACODs reported via CMC: */
>> +MCESEV(
>> +AO, "Action optional: memory scrubbing error",
>> +
Hi Tony,
On 2017/11/15 2:51, Luck, Tony wrote:
> On Tue, Nov 14, 2017 at 01:55:11PM +0800, Xie XiuQi wrote:
>> +/* known AO MCACODs reported via CMC: */
>> +MCESEV(
>> +AO, "Action optional: memory scrubbing error",
>> +
In Intel SDM Volume 3B (253669-063US, July 2017), SRAO could be
reported via CMC:
In cases when SRAO is signaled via CMCI the error signature is
indicated via UC=1, PCC=0, S=0.
So we add those known AO MCACODs check in mce_severity().
Signed-off-by: Xie XiuQi <xiexi...@huawei.com>
In Intel SDM Volume 3B (253669-063US, July 2017), SRAO could be
reported via CMC:
In cases when SRAO is signaled via CMCI the error signature is
indicated via UC=1, PCC=0, S=0.
So we add those known AO MCACODs check in mce_severity().
Signed-off-by: Xie XiuQi
Tested-by: Chen Wei
---
arch
is not selected
- use a notify chain instead of call arch_apei_report_mem_error directly
https://lkml.org/lkml/2017/9/1/189
Xie XiuQi (4):
ACPI, CPER: add arm error info type definition
arm64/ras: support sea error recovery
GHES: add a notify chain for process memory section
arm64/ras: save error
In some platform, when SEA triggerred, physical address might be
reported by memory section, so we save it for error recovery later.
Signed-off-by: Xie XiuQi <xiexi...@huawei.com>
---
arch/arm64/kernel/ras.c | 31 +++
1 file changed, 31 insertions(+)
diff
Hi James,
I'll send v4 to fix some small issue, for same one who interested
with this feature could test it. For the question you mentioned,
I will study in depth.
Any comments is welcome.
On 2017/9/16 2:33, James Morse wrote:
> Hi Xie XiuQi,
>
> On 11/09/17 15:11, Xie XiuQi wrote:
&
is not selected
- use a notify chain instead of call arch_apei_report_mem_error directly
https://lkml.org/lkml/2017/9/1/189
Xie XiuQi (4):
ACPI, CPER: add arm error info type definition
arm64/ras: support sea error recovery
GHES: add a notify chain for process memory section
arm64/ras: save error
In some platform, when SEA triggerred, physical address might be
reported by memory section, so we save it for error recovery later.
Signed-off-by: Xie XiuQi
---
arch/arm64/kernel/ras.c | 31 +++
1 file changed, 31 insertions(+)
diff --git a/arch/arm64/kernel/ras.c
Hi James,
I'll send v4 to fix some small issue, for same one who interested
with this feature could test it. For the question you mentioned,
I will study in depth.
Any comments is welcome.
On 2017/9/16 2:33, James Morse wrote:
> Hi Xie XiuQi,
>
> On 11/09/17 15:11, Xie XiuQi wrote:
&
Add arm error info type definition according to ACPI6.1
Table 261. ARM Processor Error Information Structure,
which is used for error recovery in the following patches.
Signed-off-by: Xie XiuQi <xiexi...@huawei.com>
---
include/linux/cper.h | 5 +
1 file changed, 5 insertions(+)
diff
and Scheduler Support"
diff --git a/arch/arm64/include/asm/ras.h b/arch/arm64/include/asm/ras.h
new file mode 100644
index 000..f0f18da
--- /dev/null
+++ b/arch/arm64/include/asm/ras.h
@@ -0,0 +1,23 @@
+/*
+ * ARM64 SEA error recoery support
+ *
+ * Copyright 2017 Huawei Technologies Co.,
Add a notify chain for process memory section, with
which other modules might do error recovery.
Signed-off-by: Xie XiuQi <xiexi...@huawei.com>
---
drivers/acpi/apei/ghes.c | 10 ++
include/acpi/ghes.h | 8
2 files changed, 18 insertions(+)
diff --git a/drivers/acp
Add arm error info type definition according to ACPI6.1
Table 261. ARM Processor Error Information Structure,
which is used for error recovery in the following patches.
Signed-off-by: Xie XiuQi
---
include/linux/cper.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/linux
arch/arm64/include/asm/ras.h
@@ -0,0 +1,23 @@
+/*
+ * ARM64 SEA error recoery support
+ *
+ * Copyright 2017 Huawei Technologies Co., Ltd.
+ * Author: Xie XiuQi
+ * Author: Wang Xiongfeng
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of th
Add a notify chain for process memory section, with
which other modules might do error recovery.
Signed-off-by: Xie XiuQi
---
drivers/acpi/apei/ghes.c | 10 ++
include/acpi/ghes.h | 8
2 files changed, 18 insertions(+)
diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi
Hi James,
I try to explain some of following questions.
On 2017/9/16 2:33, James Morse wrote:
> Hi Xie XiuQi,
>
> On 11/09/17 15:11, Xie XiuQi wrote:
>> I first describe the approach of this patchset:
>>
>> A memory access error on the execution path usually
Hi James,
I try to explain some of following questions.
On 2017/9/16 2:33, James Morse wrote:
> Hi Xie XiuQi,
>
> On 11/09/17 15:11, Xie XiuQi wrote:
>> I first describe the approach of this patchset:
>>
>> A memory access error on the execution path usually
v4 0/5] x86: Rework IST interrupts
https://lkml.org/lkml/2014/11/21/632
On 2017/9/9 2:15, James Morse wrote:
> Hi Xie XiuQi,
>
> (Sorry a few versions of this went past before I caught up with it)
>
> On 07/09/17 08:45, Xie XiuQi wrote:
>> With ARM v8.2 RAS Extension, SEA are usual
v4 0/5] x86: Rework IST interrupts
https://lkml.org/lkml/2014/11/21/632
On 2017/9/9 2:15, James Morse wrote:
> Hi Xie XiuQi,
>
> (Sorry a few versions of this went past before I caught up with it)
>
> On 07/09/17 08:45, Xie XiuQi wrote:
>> With ARM v8.2 RAS Extension, SEA are usual
In some platform, when SEA triggerred, physical address might be
reported by memory section, so we save it for error recovery later.
Signed-off-by: Xie XiuQi <xiexi...@huawei.com>
---
arch/arm64/kernel/ras.c | 31 +++
1 file changed, 31 insertions(+)
diff
In some platform, when SEA triggerred, physical address might be
reported by memory section, so we save it for error recovery later.
Signed-off-by: Xie XiuQi
---
arch/arm64/kernel/ras.c | 31 +++
1 file changed, 31 insertions(+)
diff --git a/arch/arm64/kernel/ras.c
running, we could check it and call memory_failure() to do
recovery. It's safe, because we are in process context.
Signed-off-by: Xie XiuQi <xiexi...@huawei.com>
Signed-off-by: Wang Xiongfeng <wangxiongfe...@huawei.com>
---
arch/arm64/Kconfig | 11 +++
arch/arm64/inclu
running, we could check it and call memory_failure() to do
recovery. It's safe, because we are in process context.
Signed-off-by: Xie XiuQi
Signed-off-by: Wang Xiongfeng
---
arch/arm64/Kconfig | 11 +++
arch/arm64/include/asm/ras.h | 36 +
arch/arm64/include/asm
Add a notify chain for process memory section, with
which other modules might do error recovery.
Signed-off-by: Xie XiuQi <xiexi...@huawei.com>
---
drivers/acpi/apei/ghes.c | 10 ++
include/acpi/ghes.h | 8
2 files changed, 18 insertions(+)
diff --git a/drivers/acp
://lkml.org/lkml/2017/9/1/189
Xie XiuQi (3):
arm64/ras: support sea error recovery
GHES: add a notify chain for process memory section
arm64/ras: save error address from memory section for recovery
arch/arm64/Kconfig | 11 +++
arch/arm64/include/asm/ras.h | 36
Add a notify chain for process memory section, with
which other modules might do error recovery.
Signed-off-by: Xie XiuQi
---
drivers/acpi/apei/ghes.c | 10 ++
include/acpi/ghes.h | 8
2 files changed, 18 insertions(+)
diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi
://lkml.org/lkml/2017/9/1/189
Xie XiuQi (3):
arm64/ras: support sea error recovery
GHES: add a notify chain for process memory section
arm64/ras: save error address from memory section for recovery
arch/arm64/Kconfig | 11 +++
arch/arm64/include/asm/ras.h | 36
Hi Borislav,
On 2017/9/6 18:12, Borislav Petkov wrote:
> On Tue, Sep 05, 2017 at 07:06:04PM +0800, Xie XiuQi wrote:
>> With ARM v8.2 RAS Extension, SEA are usually triggered when memory errors
>> are consumed. In some cases, if the error address is in a clean page or a
&g
Hi Borislav,
On 2017/9/6 18:12, Borislav Petkov wrote:
> On Tue, Sep 05, 2017 at 07:06:04PM +0800, Xie XiuQi wrote:
>> With ARM v8.2 RAS Extension, SEA are usually triggered when memory errors
>> are consumed. In some cases, if the error address is in a clean page or a
&g
running, we could check it
and call memory_failure() to do recovery. It's safe, because we are in process
context.
Signed-off-by: Xie XiuQi <xiexi...@huawei.com>
Signed-off-by: Wang Xiongfeng <wangxiongfe...@huawei.com>
---
arch/arm64/Kconfig | 11 +++
arch/arm64/inclu
running, we could check it
and call memory_failure() to do recovery. It's safe, because we are in process
context.
Signed-off-by: Xie XiuQi
Signed-off-by: Wang Xiongfeng
---
arch/arm64/Kconfig | 11 +++
arch/arm64/include/asm/ras.h | 36 +
arch/arm64/include/asm
Add a notify chain for process memory section, with
which other modules might do error recovery.
Signed-off-by: Xie XiuQi <xiexi...@huawei.com>
Tested-by: Wang Xiongfeng <wangxiongfe...@huawei.com>
---
drivers/acpi/apei/ghes.c | 10 ++
include/acpi/ghes.h | 8 +
In some platform, when SEA triggerred, physical address might be
reported by memory section, so we save it for error recovery later.
Signed-off-by: Xie XiuQi <xiexi...@huawei.com>
Tested-by: Wang Xiongfeng <wangxiongfe...@huawei.com>
---
arch/arm64/kerne
Add a notify chain for process memory section, with
which other modules might do error recovery.
Signed-off-by: Xie XiuQi
Tested-by: Wang Xiongfeng
---
drivers/acpi/apei/ghes.c | 10 ++
include/acpi/ghes.h | 8
2 files changed, 18 insertions(+)
diff --git a/drivers/acpi
In some platform, when SEA triggerred, physical address might be
reported by memory section, so we save it for error recovery later.
Signed-off-by: Xie XiuQi
Tested-by: Wang Xiongfeng
---
arch/arm64/kernel/ras.c | 31 +++
1 file changed, 31 insertions(+)
diff --git
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