The range of the pclk_edp_div_con is [13:8] and 6 bits, not 5.
Reported-by: Lin Huang
Signed-off-by: Xing Zheng
---
drivers/clk/rockchip/clk-rk3399.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk-rk3399.c
b/drivers/clk/rockchip/clk-rk3399.c
. Right now I only see pclkin_isp1_wrapper describing such a mux,
but it would be cool if you could check again.
OK, we will check these. :)
Thanks.
--
- Xing Zheng
Hi Doug,
On 2017年01月11日 02:45, Doug Anderson wrote:
Hi,
On Mon, Jan 9, 2017 at 10:15 PM, Xing Zheng wrote:
The structure rockchip_clk_provider needs to refer the GRF regmap
in somewhere, if the CRU node has not "rockchip,grf" property,
calling syscon_regmap_lookup_by_phandle will
Add support for rockchip,grf property which is used for GRF muxes
on RK3399.
Signed-off-by: Xing Zheng
---
Changes in v4:
- update the decription for rockchip,grf property
Changes in v3: None
Changes in v2: None
Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt | 6 ++
1
o add them.
Thanks.
Changes in v4:
- separte the binding patch
- update the decription for rockchip,grf property
Changes in v3:
- add optional roperty rockchip,grf in rockchip,rk3399-cru.txt
Changes in v2:
- referring pmugrf for PMUGRU
- fix the typo "invaild" in COMMIT message
Xing Zhe
Signed-off-by: Xing Zheng
---
Changes in v4:
- separte the binding patch
Changes in v3:
- add optional roperty rockchip,grf in rockchip,rk3399-cru.txt
Changes in v2:
- referring pmugrf for PMUGRU
- fix the typo "invaild" in COMMIT message
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 +
Hi, Doug
On 2017年01月10日 11:06, Doug Anderson wrote:
Hi,
On Mon, Jan 9, 2017 at 5:27 PM, Xing Zheng wrote:
The structure rockchip_clk_provider needs to refer the GRF regmap
in somewhere, if the CRU node has not "rockchip,grf" property,
calling syscon_regmap_lookup_by_phandle will
Signed-off-by: Xing Zheng
---
Changes in v3:
- add optional roperty rockchip,grf in rockchip,rk3399-cru.txt
Changes in v2:
- referring pmugrf for PMUGRU
- fix the typo "invaild" in COMMIT message
Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt | 5 +
arch/arm64/boot
that actually uses this new functionality.
Sorry to miss it. Thanks for your reminding me.
--
- Xing Zheng
Signed-off-by: Xing Zheng
---
Changes in v2:
- referring pmugrf for PMUGRU
- fix the typo "invaild" in COMMIT message
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
b/arch/arm64/boot/dts/rockch
Signed-off-by: Xing Zheng
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 92b731f..7790634 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/
Hi Doug,
在 2016年12月22日 08:47, Doug Anderson 写道:
Hi,
On Wed, Dec 21, 2016 at 2:41 AM, Xing Zheng wrote:
From: William wu
We found that the suspend process was blocked when it run into
ehci/ohci module due to clk-480m of usb2-phy was disabled.
The root cause is that usb2-phy suspended
Hi Heiko, Doug
在 2016年12月17日 01:28, Doug Anderson 写道:
Hi,
On Thu, Dec 15, 2016 at 10:57 PM, Xing Zheng wrote:
Hi Heiko, Doug,
On 2016年12月16日 02:18, Heiko Stuebner wrote:
Am Donnerstag, 15. Dezember 2016, 08:34:09 CET schrieb Doug Anderson:
I still need to digest all of the things that
CLK -> | EHCI |
OSC_24M ---|---> PHY_PLL||
|^___||-> 480M_CLK ---|G|---> | USBPHY_480M_SRC|
> USBPHY_480M for SoC
|
|
GRF
===
Signed-off-by: William wu
Signed-off-by: Xing Zheng
---
Chang
SBPHY_480M for SoC
|
|
GRF
---
Signed-off-by: William wu
Signed-off-by: Xing Zheng
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 28
1 file changed, 20 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
b/a
.
I think Frank and William will help us to continue checking these.
Thanks
在 2016年12月15日 08:10, Doug Anderson 写道:
Hi,
On Wed, Dec 14, 2016 at 2:11 AM, Xing Zheng wrote:
From: William wu
We found that the suspend process was blocked when it run into
ehci/ohci module due to clk-480m of usb2
Hi,
This patches would like to fix the USB suspend block without
the clk-480m clock. Let's add and export them to control them.
Thanks.
William wu (1):
arm64: dts: rockchip: add clk-480m for ehci and ohci of rk3399
Xing Zheng (2):
clk: rockchip: rk3399: add USBPHYx_480M_SRC cloc
was disabled if no module used. However,
some suspend process related ehci/ohci are base on this clock,
so we should refer it into ehci/ohci driver to prevent this case.
Signed-off-by: William wu
Signed-off-by: Xing Zheng
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 28
This patch add two clock IDs for the usb phy 480m source clocks.
Signed-off-by: Xing Zheng
---
include/dt-bindings/clock/rk3399-cru.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/dt-bindings/clock/rk3399-cru.h
b/include/dt-bindings/clock/rk3399-cru.h
index 220a60f..224daf7
This patch exports USBPHYx_480M_SRC clocks for usbphy.
Signed-off-by: Xing Zheng
---
drivers/clk/rockchip/clk-rk3399.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3399.c
b/drivers/clk/rockchip/clk-rk3399.c
index 3490887..cf2af4c 100644
r are lower:
800 MHz:
- FVCO == 2.4 GHz, revdiv == 1.
1 GHz:
- FVCO == 3 GHz, revdiv == 1.
Signed-off-by: Xing Zheng
---
drivers/clk/rockchip/clk-rk3399.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3399.c
b/drivers/clk/rockchip/clk-rk3399.c
We need to get the accurate 533.25MHz for the DP display.
Signed-off-by: Xing Zheng
---
drivers/clk/rockchip/clk-rk3399.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/rockchip/clk-rk3399.c
b/drivers/clk/rockchip/clk-rk3399.c
index 2c7cba7..a87cb49 100644
--- a/drivers/clk
Hi Mark,
On 2016年09月19日 22:44, Mark Rutland wrote:
On Mon, Sep 19, 2016 at 10:29:39PM +0800, Xing Zheng wrote:
From: Wonjoon Lee
Pop happens when mclk applied but dmic's own boot-time
Specify dmic delay times in dt to make sure
clocks are ready earlier than dmic working
Signed-o
From: Wonjoon Lee
Pop happens when mclk applied but dmic's own boot-time
Specify dmic delay times in dt to make sure
clocks are ready earlier than dmic working
Signed-off-by: Wonjoon Lee
Signed-off-by: Xing Zheng
---
Changes in v2:
- rename dmic-delay to dmic-wakeup-delay-ms
.../bin
From: Wonjoon Lee
Pop happens when mclk applied but dmic's own boot-time
Specify dmic delay times in dt to make sure
clocks are ready earlier than dmic working
Signed-off-by: Wonjoon Lee
Signed-off-by: Xing Zheng
---
.../bindings/sound/rockchip,rk3399-gru-sound.txt |6 ++
From: Hsin-Yu Chao
Da7219 does not trigger interrupt to report jack status
when system boots from warm reset because its power
remains on during warm reset.
Doing software reset at probe to handle this.
Signed-off-by: Hsin-Yu Chao
Signed-off-by: Xing Zheng
---
Changes in v2:
- change the
From: Hsin-Yu Chao
On some platform da7219 codec has persistent power across reboot
so it doesn't reset and cause abnormal jack detection.
Workaround this issue by doing software reset at probe.
Signed-off-by: Hsin-Yu Chao
Signed-off-by: Xing Zheng
---
sound/soc/codecs/da7219.
We need to ensure the master bias and jack detection to be enabled
before reporting event at the da7219_aad_irq_thread. Otherwise, we
may acquire the incorrect the unplug event when the DUT startup
with a plugged headphone.
Signed-off-by: Xing Zheng
---
sound/soc/codecs/da7219-aad.c | 7
),
RK3399_CPUCLKB_RATE(18, 1, 8, 8),
It looks good to me.
Reviewed-by: Xing Zheng
Thanks.
--
- Xing Zheng
"
- depends on SND_SOC_ROCKCHIP&& I2C&& GPIOLIB&& CLKDEV_LOOKUP
+ depends on SND_SOC_ROCKCHIP&& I2C&& GPIOLIB&& CLKDEV_LOOKUP&& SPI
select SND_SOC_ROCKCHIP_I2S
select SND_SOC_MAX98357A
select SND_SOC_RT5514
So sorry to miss it... Thanks to help us to fix it. :-)
Tested-by: Xing Zheng
Thanks.
--
- Xing Zheng
ll update the TRM to fix it.
Signed-off-by: Xing Zheng
---
Changes in v2:
- rename node name "watchdog" to "watchdog0" explicitly
arch/arm64/boot/dts/rockchip/rk3399.dtsi |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/roc
Hi Shawn,
On 2016年08月26日 17:41, Shawn Lin wrote:
On 2016/8/26 14:22, Xing Zheng wrote:
Dues to incorrect description in the TRM, the WDTs base address
should be fixed and swap them like this:
WDT0 - 0xff848000
WDT1 - 0xff84
And, it is right that only WDT0 can generate global software
Dues to incorrect description in the TRM, the WDTs base address
should be fixed and swap them like this:
WDT0 - 0xff848000
WDT1 - 0xff84
And, it is right that only WDT0 can generate global software reset.
We will update the TRM to fix it.
Signed-off-by: Xing Zheng
---
arch/arm64/boot/dts
This patch can attach automaticlly rt5514 spi DAI with driver name "rt5514"
in the snd_soc_find_dai process. Turn this feature on, we can enable the
voice wake up via rt5514 dsp for RK3399 Gru Boards.
Signed-off-by: Xing Zheng
---
sound/soc/rockchip/Kconfig|1 +
incorrect bit.
Reviewed-by: Xing Zheng
Thanks.
COMPOSITE_NOMUX(PCLK_VIO, "pclk_vio", "aclk_vio", 0,
RK3399_CLKSEL_CON(43), 0, 5, DFLAGS,
RK3399_CLKGATE_CON(11), 1, GFLAGS),
@@ -1470,6 +1470,9 @@ static const char
TPB 12
f004102e:DMAFLUSHP 12
f0041030:DMALPENDA_1 bjmpto_7
f0041032:DMASEV 0
f0041034:DMAEND
Signed-off-by: Shawn Lin
Tested-by: Xing Zheng
Thanks.
--
- Xing Zheng
mprovement
significantly when tesing SPI transfer etc.
default single mode
[ 88.292550] spi write 65536*1 cost 32402us speed:2022KB/S
After applied with burst mode(len 16)
[ 17.625296] spi write 65536*1 cost 17830us speed:3675KB/S
Cc: Huibin Hong
Cc: Xing Zheng
Signed-off-by: Shawn Lin
---
Hi Heiko,
On 2016年08月05日 16:48, Heiko Stübner wrote:
Hi Xing,
Am Freitag, 5. August 2016, 10:26:57 schrieb Xing Zheng:
On 2016年08月05日 03:19, Heiko Stübner wrote:
Am Dienstag, 2. August 2016, 15:22:59 schrieb Xing Zheng:
We need to support various display resolutions for external
display
Hi Heiko,
On 2016年08月05日 03:19, Heiko Stübner wrote:
Hi Xing,
Am Dienstag, 2. August 2016, 15:22:59 schrieb Xing Zheng:
We need to support various display resolutions for external
display devices like HDMI/DP, the frac mode can help us to
acquire almost any frequencies, and need higher VCOs
Because we need to support the multiple codecs (MAX98357A/RT5514/DA7219)
on the RK3399 GRU boards, this patch can help us to support these codecs.
Signed-off-by: Xing Zheng
Acked-by: Rob Herring
---
Changes in v7:
- add default MCLK and PLL settings for the da7219_init() so that the
Hi Doug,
On 2016年08月03日 08:49, Doug Anderson wrote:
Xing,
On Tue, Aug 2, 2016 at 6:13 AM, Xing Zheng wrote:
From: Elaine Zhang
The suggestion that is from IC designer, the correct pll sequence setting
should be like these:
set pll to slow mode or other plls
set pll down
set
From: Elaine Zhang
The goal is that we can configure the most suitable pll params automatically.
If setting freq is not supported in rockchip_pll_rate_table rk3399_pll_rates[],
we can set pll params automatically.
Signed-off-by: Elaine Zhang
Signed-off-by: Xing Zheng
---
drivers/clk
need to fix:
rockchip_rk3399_wait_pll_lock - timeout waiting for pll to lock
rockchip_rk3399_pll_set_params - pll update unsucessful, trying to restore old
params
Signed-off-by: Elaine Zhang
Signed-off-by: Xing Zheng
---
drivers/clk/rockchip/clk-pll.c | 10 ++
1 file changed, 10
We need to support various display resolutions for external
display devices like HDMI/DP, the frac mode can help us to
acquire almost any frequencies, and need higher VCOs to reduce
clock jitters.
Signed-off-by: Xing Zheng
---
Changes in v3: None
Changes in v2: None
drivers/clk/rockchip/clk
4
0x03e1
plug/unplug, the DUT is crashed
Summary:
bit 1 - shows aclk_perihp_cpll_src_en
bit 0 - shows aclk_perihp_gpll_src_en
Fixes: 3bd14ae9da91 ("clk: rockchip: fix incorrect parent for rk3399's
{c,g}pll_aclk_perihp_src")
Signed-off-by: Xing Zheng
---
Changes in v3:
- list
e patchset
Elaine Zhang (1):
clk: rockchip: rk3399: delete the CLK_IGNORE_UNUSED for aclk_pcie
Xing Zheng (6):
clk: rockchip: rk3399: export USBPHYx_480M_SRC clock IDs
clk: rockchip: rk3399: export 480M_SRC clock id for usbphy0/usbphy1
clk: rockchip: rk3399: fix incorrect GATE bits for
We need to add more clocks for supporting more display resolution
for HDMI.
Signed-off-by: Xing Zheng
---
Changes in v3: None
Changes in v2: None
drivers/clk/rockchip/clk-rk3399.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/rockchip/clk-rk3399.c
b/drivers/clk
From: Elaine Zhang
allow aclk_pcie and aclk_perf_pcie disabled when unused.
Signed-off-by: Elaine Zhang
Signed-off-by: Xing Zheng
---
Changes in v3: None
Changes in v2: None
drivers/clk/rockchip/clk-rk3399.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a
Dues to incorrect diagram, we need to fix incorrect bits for
(c/g)pll_aclk_emmc_src:
cpll_aclk_emmc_src --> G6[13]
gpll_aclk_emmc_src --> G6[12]
Signed-off-by: Xing Zheng
Reviewed-by: Shawn Lin
---
Changes in v3:
- add "Reviewed-by: Shawn Lin "
Changes in v2: None
drivers/
We export some clock IDs for the usb phy 480m source clocks.
Signed-off-by: Xing Zheng
---
Changes in v3: None
Changes in v2: None
include/dt-bindings/clock/rk3399-cru.h |2 ++
1 file changed, 2 insertions(+)
diff --git a/include/dt-bindings/clock/rk3399-cru.h
b/include/dt-bindings
Export these source clocks for usbphy.
Signed-off-by: Xing Zheng
---
Changes in v3: None
Changes in v2: None
drivers/clk/rockchip/clk-rk3399.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3399.c
b/drivers/clk/rockchip/clk-rk3399.c
Hi Brain,
On 2016年08月02日 04:13, Brian Norris wrote:
On Mon, Aug 01, 2016 at 05:53:38PM +0800, Xing Zheng wrote:
There was a typo, swapping 'c' <--> 'g'.
(This patch is updated and am from https://patchwork.kernel.org/patch/9254067/)
Signed-off-by: Xing Zheng
S
From: Elaine Zhang
allow aclk_pcie and aclk_perf_pcie disabled when unused.
Signed-off-by: Elaine Zhang
Signed-off-by: Xing Zheng
---
Changes in v2: None
drivers/clk/rockchip/clk-rk3399.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/rockchip/clk
We need to support various display resolutions for external
display devices like HDMI/DP, the frac mode can help us to
acquire almost any frequencies, and need higher VCOs to reduce
clock jitters.
Signed-off-by: Xing Zheng
---
Changes in v2:
- add the patch "fix incorrect parent for rk3399
We need to add more clocks for supporting more display resolution
for HDMI.
Signed-off-by: Xing Zheng
---
Changes in v2: None
drivers/clk/rockchip/clk-rk3399.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/rockchip/clk-rk3399.c
b/drivers/clk/rockchip/clk-rk3399.c
index
Dues to incorrect diagram, we need to fix incorrect bits for
(c/g)pll_aclk_emmc_src:
cpll_aclk_emmc_src --> G6[13]
gpll_aclk_emmc_src --> G6[12]
Signed-off-by: Xing Zheng
---
Changes in v2: None
drivers/clk/rockchip/clk-rk3399.c |4 ++--
1 file changed, 2 insertions(+), 2 del
.
On 2016年05月16日 23:49, Doug Anderson wrote:
Hi,
On Fri, May 13, 2016 at 8:36 PM, Xing Zheng wrote:
Hi Doug,
On 2016年05月14日 04:10, Doug Anderson wrote:
Hi,
On Fri, May 13, 2016 at 11:42 AM, Brian Norris
wrote:
From: Xing Zheng
There was a typo, swapping 'c' <--> 'g&#
Sorry to refer incorrect clock diagram, we double check it that the
bits configuration of the Xpll_aclk_perihp_src need to be fixed:
bit 1 - shows aclk_perihp_cpll_src_en
bit 0 - shows aclk_perihp_gpll_src_en
Signed-off-by: Xing Zheng
---
Changes in v2: None
drivers/clk/rockchip/clk-rk3399.c
There was a typo, swapping 'c' <--> 'g'.
(This patch is updated and am from https://patchwork.kernel.org/patch/9254067/)
Signed-off-by: Xing Zheng
Signed-off-by: Brian Norris
Reviewed-by: Douglas Anderson
---
Changes in v2: None
drivers/clk/rockchip/clk-rk3399.c |
We export some clock IDs for the usb phy 480m source clocks.
Signed-off-by: Xing Zheng
---
Changes in v2: None
include/dt-bindings/clock/rk3399-cru.h |2 ++
1 file changed, 2 insertions(+)
diff --git a/include/dt-bindings/clock/rk3399-cru.h
b/include/dt-bindings/clock/rk3399-cru.h
GATE bits for {c, g}pll_aclk_perihp_src"
Elaine Zhang (1):
clk: rockchip: rk3399: delete the CLK_IGNORE_UNUSED for aclk_pcie
Xing Zheng (7):
clk: rockchip: rk3399: export USBPHYx_480M_SRC clock IDs
clk: rockchip: rk3399: export 480M_SRC clock id for usbphy0/usbphy1
clk: rockchip: rk3
Export these source clocks for usbphy.
Signed-off-by: Xing Zheng
---
Changes in v2: None
drivers/clk/rockchip/clk-rk3399.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3399.c
b/drivers/clk/rockchip/clk-rk3399.c
index 78e51cb..f55f967f
We need to support various display resolutions for external
display devices like HDMI/DP, the frac mode can help us to
acquire almost any frequencies, and need higher VCOs to reduce
clock jitters.
Signed-off-by: Xing Zheng
---
Changes in v2:
- add the patch "fix incorrect parent for rk3399
We need to add more clocks for supporting more display resolution
for HDMI.
Signed-off-by: Xing Zheng
---
Changes in v2: None
drivers/clk/rockchip/clk-rk3399.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/rockchip/clk-rk3399.c
b/drivers/clk/rockchip/clk-rk3399.c
index
From: Elaine Zhang
allow aclk_pcie and aclk_perf_pcie disabled when unused.
Signed-off-by: Elaine Zhang
Signed-off-by: Xing Zheng
---
Changes in v2: None
drivers/clk/rockchip/clk-rk3399.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/rockchip/clk
We export some clock IDs for the usb phy 480m source clocks.
Signed-off-by: Xing Zheng
---
Changes in v2: None
include/dt-bindings/clock/rk3399-cru.h |2 ++
1 file changed, 2 insertions(+)
diff --git a/include/dt-bindings/clock/rk3399-cru.h
b/include/dt-bindings/clock/rk3399-cru.h
rk3399: delete the CLK_IGNORE_UNUSED for aclk_pcie
Xing Zheng (6):
clk: rockchip: rk3399: export USBPHYx_480M_SRC clock IDs
clk: rockchip: rk3399: export 480M_SRC clock id for usbphy0/usbphy1
clk: rockchip: rk3399: fix incorrect parent for rk3399's {c,
g}pll_aclk_perihp_src
clk: r
There was a typo, swapping 'c' <--> 'g'.
And sorry to refer incorrect clock diagram, we double check it that
the bits configuration of the Xpll_aclk_perihp_src need to be fixed:
bit 1 - shows aclk_perihp_cpll_src_en
bit 0 - shows aclk_perihp_gpll_src_en
Signed-off-by:
Export these source clocks for usbphy.
Signed-off-by: Xing Zheng
---
Changes in v2: None
drivers/clk/rockchip/clk-rk3399.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3399.c
b/drivers/clk/rockchip/clk-rk3399.c
index 78e51cb..f55f967f
Dues to incorrect diagram, we need to fix incorrect bits for
(c/g)pll_aclk_emmc_src:
cpll_aclk_emmc_src --> G6[13]
gpll_aclk_emmc_src --> G6[12]
Signed-off-by: Xing Zheng
---
Changes in v2: None
drivers/clk/rockchip/clk-rk3399.c |4 ++--
1 file changed, 2 insertions(+), 2 del
Hi:
In the development work, we found that some of the previous
incorrect clock configuration on the RK3399 platform, we should
fix and optimize them.
Elaine Zhang (1):
clk: rockchip: rk3399: delete the CLK_IGNORE_UNUSED for aclk_pcie
Xing Zheng (5):
clk: rockchip: rk3399: export
We need to support various display resolutions for external
display devices like HDMI/DP, the frac mode can help us to
acquire almost any frequencies, and need higher VCOs to reduce
clock jitters.
Signed-off-by: Xing Zheng
---
drivers/clk/rockchip/clk-rk3399.c | 21 -
1
We export some clock IDs for the usb phy 480m source clocks.
Signed-off-by: Xing Zheng
---
include/dt-bindings/clock/rk3399-cru.h |2 ++
1 file changed, 2 insertions(+)
diff --git a/include/dt-bindings/clock/rk3399-cru.h
b/include/dt-bindings/clock/rk3399-cru.h
index 50a44cf..c4d8311
Dues to incorrect diagram, we need to fix incorrect bits for
(c/g)pll_aclk_emmc_src:
cpll_aclk_emmc_src --> G6[13]
gpll_aclk_emmc_src --> G6[12]
Signed-off-by: Xing Zheng
---
drivers/clk/rockchip/clk-rk3399.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/d
Export these source clocks for usbphy.
Signed-off-by: Xing Zheng
---
drivers/clk/rockchip/clk-rk3399.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3399.c
b/drivers/clk/rockchip/clk-rk3399.c
index 78e51cb..f55f967f 100644
--- a/drivers
From: Elaine Zhang
allow aclk_pcie and aclk_perf_pcie disabled when unused.
Signed-off-by: Elaine Zhang
Signed-off-by: Xing Zheng
---
drivers/clk/rockchip/clk-rk3399.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3399.c
b/drivers
We need to add more clocks for supporting more display resolution
for HDMI.
Signed-off-by: Xing Zheng
---
drivers/clk/rockchip/clk-rk3399.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/rockchip/clk-rk3399.c
b/drivers/clk/rockchip/clk-rk3399.c
index ad3860a..74afec0
From: Elaine Zhang
allow aclk_pcie and aclk_perf_pcie disabled when unused.
Signed-off-by: Elaine Zhang
Signed-off-by: Xing Zheng
---
drivers/clk/rockchip/clk-rk3399.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3399.c
b/drivers
Dues to incorrect diagram, we need to fix incorrect bits for
(c/g)pll_aclk_emmc_src:
cpll_aclk_emmc_src --> G6[13]
gpll_aclk_emmc_src --> G6[12]
Signed-off-by: Xing Zheng
---
drivers/clk/rockchip/clk-rk3399.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/d
Hi:
In the development work, we found that some of the previous
incorrect clock configuration on the RK3399 platform, we should
fix and optimize them.
Elaine Zhang (1):
clk: rockchip: rk3399: delete the CLK_IGNORE_UNUSED for aclk_pcie
Xing Zheng (5):
clk: rockchip: rk3399: export
We export some clock IDs for the usb phy 480m source clocks.
Signed-off-by: Xing Zheng
---
include/dt-bindings/clock/rk3399-cru.h |2 ++
1 file changed, 2 insertions(+)
diff --git a/include/dt-bindings/clock/rk3399-cru.h
b/include/dt-bindings/clock/rk3399-cru.h
index 50a44cf..c4d8311
Export these source clocks for usbphy.
Signed-off-by: Xing Zheng
---
drivers/clk/rockchip/clk-rk3399.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3399.c
b/drivers/clk/rockchip/clk-rk3399.c
index 78e51cb..f55f967f 100644
--- a/drivers
We need to support various display resolutions for external
display devices like HDMI/DP, the frac mode can help us to
acquire almost any frequencies, and need higher VCOs to reduce
clock jitters.
Signed-off-by: Xing Zheng
---
drivers/clk/rockchip/clk-rk3399.c | 21 -
1
We need to add more clocks for supporting more display resolution
for HDMI.
Signed-off-by: Xing Zheng
---
drivers/clk/rockchip/clk-rk3399.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/rockchip/clk-rk3399.c
b/drivers/clk/rockchip/clk-rk3399.c
index ad3860a..74afec0
Hi Mark,
In your opinion, is there anything needs to be optimized in this patch?
Thanks.
On 2016年06月20日 21:08, Rob Herring wrote:
On Thu, Jun 16, 2016 at 08:40:58PM +0800, Xing Zheng wrote:
Because we need to support the multiple codecs (MAX98357A/RT5514/DA7219)
on the RK3399 GRU boards
This adds support for RK3288-Fennec boards. Currently supported
are serial console, wired networking, hdmi output and USB.
Signed-off-by: Xing Zheng
---
Documentation/devicetree/bindings/arm/rockchip.txt |4 +
arch/arm/boot/dts/Makefile |1 +
arch/arm/boot/dts
The CLKSEL_CON32 bit_0 is controlled for spdif_8ch, not spdif_rec_dptx,
it should be bit_8, let's fix it.
Reported-by: Chris Zhong
Tested-by: Chris Zhong
Signed-off-by: Xing Zheng
---
drivers/clk/rockchip/clk-rk3399.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --
Thanks Heiko. :-)
On 2016年06月28日 03:43, Heiko Stuebner wrote:
Am Mittwoch, 22. Juni 2016, 11:16:49 schrieb Xing Zheng:
Hi,
We have the brother chipset product that RK3228 and RK3229,
They have many common configuration, but there are a number
of different features. In order to develop the
This patch add the GMAC dt nodes for rk322x SoCs.
Signed-off-by: Xing Zheng
---
Changes in v2: None
arch/arm/boot/dts/rk322x.dtsi | 64 +
1 file changed, 64 insertions(+)
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
We have the brother chipset that RK3228 and RK3229, they share most
of dts configuration, but there are a number of different features.
In order to develop the future when they are easy to distinguish,
we need them to be independent.
Signed-off-by: Xing Zheng
---
Changes in v2: None
arch/arm
Initial release for rk3229 evb board, and turn the GMAC on.
Signed-off-by: Xing Zheng
---
Changes in v2:
- rename rk3228.dtsi to rk322x.dtsi
arch/arm/boot/dts/Makefile |1 +
arch/arm/boot/dts/rk3229-evb.dts | 90 ++
arch/arm/boot/dts/rk3229
RK322x SoCs,
and add the new dts file of the rk3229 evb board.
Thanks.
Changes in v2:
- rename rk3228.dtsi to rk322x.dtsi
Xing Zheng (4):
ARM: dts: rockchip: rename rk3228.dtsi to rk322x.dtsi
ARM: dts: rockchip: add i2s nodes for RK322x SoCs
ARM: dts: rockchip: add GMAC nodes for RK322x SoCs
This patch add the i2s dt nodes for rk322x SoCs.
Signed-off-by: Xing Zheng
---
Changes in v2: None
arch/arm/boot/dts/rk322x.dtsi | 55 +
1 file changed, 55 insertions(+)
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
index
RK322x SoCs,
and add the new dts file of the rk3229 evb board.
Thanks.
Changes in v2:
- rename rk3228.dtsi to rk322x.dtsi
Xing Zheng (4):
ARM: dts: rockchip: rename rk3228.dtsi to rk322x.dtsi
ARM: dts: rockchip: add i2s nodes for RK322x SoCs
ARM: dts: rockchip: add GMAC nodes for RK322x SoCs
Initial release for rk3229 evb board, and turn the GMAC on.
Signed-off-by: Xing Zheng
---
Changes in v2:
- rename rk3228.dtsi to rk322x.dtsi
arch/arm/boot/dts/Makefile |1 +
arch/arm/boot/dts/rk3229-evb.dts | 90 ++
arch/arm/boot/dts/rk3229
This patch add the GMAC dt nodes for rk322x SoCs.
Signed-off-by: Xing Zheng
---
Changes in v2: None
arch/arm/boot/dts/rk322x.dtsi | 64 +
1 file changed, 64 insertions(+)
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
This patch add the i2s dt nodes for rk322x SoCs.
Signed-off-by: Xing Zheng
---
Changes in v2: None
arch/arm/boot/dts/rk322x.dtsi | 55 +
1 file changed, 55 insertions(+)
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
index
We have the brother chipset that RK3228 and RK3229, they share most
of dts configuration, but there are a number of different features.
In order to develop the future when they are easy to distinguish,
we need them to be independent.
Signed-off-by: Xing Zheng
---
Changes in v2: None
arch/arm
Hi Heiko,
On 2016年06月22日 07:07, Heiko Stuebner wrote:
Am Dienstag, 21. Juni 2016, 12:53:26 schrieb Xing Zheng:
Hi,
These patchset fix some clocks bugs, and improve clock configuration
for i2s/spdif/MAC on RK322x SoCs.
applied to my clock-branch with the following changes:
- fixed the
Add constants and callback functions for the dwmac on rk3228/rk3229 socs.
As can be seen, the base structure is the same, only registers and the
bits in them moved slightly.
Signed-off-by: Xing Zheng
---
Changes in v2:
- the "rk322x" is not clear to SoC decription, rename it
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