[PATCH] ARM: hisi: Fix typo in comment
Fix the rc vs. pc typo. There is no a register named rc, I felt confused when I read this assembler command in comment. Signed-off-by: Yunzhi Li <yunzhi...@deephi.tech> --- arch/arm/mach-hisi/platsmp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-hisi/platsmp.c b/arch/arm/mach-hisi/platsmp.c index 91bb02dec20f..da5689ababf7 100644 --- a/arch/arm/mach-hisi/platsmp.c +++ b/arch/arm/mach-hisi/platsmp.c @@ -109,7 +109,7 @@ static void hix5hd2_set_scu_boot_addr(phys_addr_t start_addr, phys_addr_t jump_a virt = ioremap(start_addr, PAGE_SIZE); - writel_relaxed(0xe51ff004, virt); /* ldr pc, [rc, #-4] */ + writel_relaxed(0xe51ff004, virt); /* ldr pc, [pc, #-4] */ writel_relaxed(jump_addr, virt + 4);/* pc jump phy address */ iounmap(virt); } -- 2.11.0
[PATCH] ARM: hisi: Fix typo in comment
Fix the rc vs. pc typo. There is no a register named rc, I felt confused when I read this assembler command in comment. Signed-off-by: Yunzhi Li --- arch/arm/mach-hisi/platsmp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-hisi/platsmp.c b/arch/arm/mach-hisi/platsmp.c index 91bb02dec20f..da5689ababf7 100644 --- a/arch/arm/mach-hisi/platsmp.c +++ b/arch/arm/mach-hisi/platsmp.c @@ -109,7 +109,7 @@ static void hix5hd2_set_scu_boot_addr(phys_addr_t start_addr, phys_addr_t jump_a virt = ioremap(start_addr, PAGE_SIZE); - writel_relaxed(0xe51ff004, virt); /* ldr pc, [rc, #-4] */ + writel_relaxed(0xe51ff004, virt); /* ldr pc, [pc, #-4] */ writel_relaxed(jump_addr, virt + 4);/* pc jump phy address */ iounmap(virt); } -- 2.11.0
[PATCH] ARM: hisi: Fix typo in comment
Fix the rc vs. pc typo. There is no a register named rc, I felt confused when I read this assembler command in comment. Signed-off-by: Yunzhi Li <yunzhi...@deephi.tech> --- arch/arm/mach-hisi/platsmp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-hisi/platsmp.c b/arch/arm/mach-hisi/platsmp.c index 91bb02dec20f..da5689ababf7 100644 --- a/arch/arm/mach-hisi/platsmp.c +++ b/arch/arm/mach-hisi/platsmp.c @@ -109,7 +109,7 @@ static void hix5hd2_set_scu_boot_addr(phys_addr_t start_addr, phys_addr_t jump_a virt = ioremap(start_addr, PAGE_SIZE); - writel_relaxed(0xe51ff004, virt); /* ldr pc, [rc, #-4] */ + writel_relaxed(0xe51ff004, virt); /* ldr pc, [pc, #-4] */ writel_relaxed(jump_addr, virt + 4);/* pc jump phy address */ iounmap(virt); } -- 2.11.0
[PATCH] ARM: hisi: Fix typo in comment
Fix the rc vs. pc typo. There is no a register named rc, I felt confused when I read this assembler command in comment. Signed-off-by: Yunzhi Li --- arch/arm/mach-hisi/platsmp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-hisi/platsmp.c b/arch/arm/mach-hisi/platsmp.c index 91bb02dec20f..da5689ababf7 100644 --- a/arch/arm/mach-hisi/platsmp.c +++ b/arch/arm/mach-hisi/platsmp.c @@ -109,7 +109,7 @@ static void hix5hd2_set_scu_boot_addr(phys_addr_t start_addr, phys_addr_t jump_a virt = ioremap(start_addr, PAGE_SIZE); - writel_relaxed(0xe51ff004, virt); /* ldr pc, [rc, #-4] */ + writel_relaxed(0xe51ff004, virt); /* ldr pc, [pc, #-4] */ writel_relaxed(jump_addr, virt + 4);/* pc jump phy address */ iounmap(virt); } -- 2.11.0
[PATCH] usb: dwc2: hcd: fix periodic transfer schedule sequence
When checking dwc2 host channel interrupts, handle qh in
periodic_sched_queued list at first, then we could make sure CSPLIT
packets scheduled in the same order as SSPLIT packets.
Signed-off-by: Yunzhi Li
---
drivers/usb/dwc2/hcd_intr.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/drivers/usb/dwc2/hcd_intr.c b/drivers/usb/dwc2/hcd_intr.c
index bda0b21..e8e8970 100644
--- a/drivers/usb/dwc2/hcd_intr.c
+++ b/drivers/usb/dwc2/hcd_intr.c
@@ -2115,6 +2115,8 @@ static void dwc2_hc_intr(struct dwc2_hsotg *hsotg)
{
u32 haint;
int i;
+ int hc_num;
+ struct dwc2_qh *qh, *qh_tmp;
haint = dwc2_readl(hsotg->regs + HAINT);
if (dbg_perio()) {
@@ -2123,6 +2125,26 @@ static void dwc2_hc_intr(struct dwc2_hsotg *hsotg)
dev_vdbg(hsotg->dev, "HAINT=%08x\n", haint);
}
+ /*
+* According to USB 2.0 spec section 11.18.8, a host must
+* issue complete-split transactions in a microframe for a
+* set of full-/low-speed endpoints in the same relative
+* order as the start-splits were issued in a microframe for.
+* So here we should at first picking up host channels
+* from periodic_sched_queued list and checking if there is
+* any start-split have already finished then schedule
+* complete-split in the same order.
+*/
+ list_for_each_entry_safe(qh, qh_tmp,
+>periodic_sched_queued,
+qh_list_entry) {
+ hc_num = qh->channel->hc_num;
+ if (haint & (1 << hc_num)) {
+ dwc2_hc_n_intr(hsotg, hc_num);
+ haint &= ~(1 << hc_num);
+ }
+ }
+
for (i = 0; i < hsotg->core_params->host_channels; i++) {
if (haint & (1 << i))
dwc2_hc_n_intr(hsotg, i);
--
1.9.1
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[PATCH] usb: dwc2: hcd: fix periodic transfer schedule sequence
When checking dwc2 host channel interrupts, handle qh in
periodic_sched_queued list at first, then we could make sure CSPLIT
packets scheduled in the same order as SSPLIT packets.
Signed-off-by: Yunzhi Li <l...@rock-chips.com>
---
drivers/usb/dwc2/hcd_intr.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/drivers/usb/dwc2/hcd_intr.c b/drivers/usb/dwc2/hcd_intr.c
index bda0b21..e8e8970 100644
--- a/drivers/usb/dwc2/hcd_intr.c
+++ b/drivers/usb/dwc2/hcd_intr.c
@@ -2115,6 +2115,8 @@ static void dwc2_hc_intr(struct dwc2_hsotg *hsotg)
{
u32 haint;
int i;
+ int hc_num;
+ struct dwc2_qh *qh, *qh_tmp;
haint = dwc2_readl(hsotg->regs + HAINT);
if (dbg_perio()) {
@@ -2123,6 +2125,26 @@ static void dwc2_hc_intr(struct dwc2_hsotg *hsotg)
dev_vdbg(hsotg->dev, "HAINT=%08x\n", haint);
}
+ /*
+* According to USB 2.0 spec section 11.18.8, a host must
+* issue complete-split transactions in a microframe for a
+* set of full-/low-speed endpoints in the same relative
+* order as the start-splits were issued in a microframe for.
+* So here we should at first picking up host channels
+* from periodic_sched_queued list and checking if there is
+* any start-split have already finished then schedule
+* complete-split in the same order.
+*/
+ list_for_each_entry_safe(qh, qh_tmp,
+>periodic_sched_queued,
+qh_list_entry) {
+ hc_num = qh->channel->hc_num;
+ if (haint & (1 << hc_num)) {
+ dwc2_hc_n_intr(hsotg, hc_num);
+ haint &= ~(1 << hc_num);
+ }
+ }
+
for (i = 0; i < hsotg->core_params->host_channels; i++) {
if (haint & (1 << i))
dwc2_hc_n_intr(hsotg, i);
--
1.9.1
--
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Re: [RFC] usb: dwc2: hcd: fix split schedule issue
Hi John 在 2015/11/12 12:29, John Youn 写道: On 11/11/2015 4:22 PM, Doug Anderson wrote: John, On Fri, Nov 6, 2015 at 2:04 AM, Yunzhi Li wrote: hi John , As we talked yesterday, I tried to fix the split schedule sequence. This patch will avoid scheduling SSPLIT-IN packet for another device between SSPLIT-OUT-begin and SSPLIT-OUT-end, now the keyboard and Jebra audio speaker could work together well, but I'm not sure if this is exactly the right way to schedule split transfers and if there is any dide effect with this patch. Please help review this patch. Thanks. Fix dwc2 split schedule sequence issue. Not schedule a SSPLIT_IN packet between SSPLIT-begin and SSPLIT-end. Signed-off-by: Yunzhi Li --- drivers/usb/dwc2/hcd.c | 4 1 file changed, 4 insertions(+) Did you have any thoughts on this patch? Although this patch didn't fix the problems I was seeing with the Microsoft Wireless Keyboard (see the patch I sent out earlier which does seem to fix it), I can confirm that in a different setup (HUB goes to USB audio + mouse) that this patch does fix some problems. That being said, it feels to me like a band-aid rather than an actual fix (I'm talking out of my rear end, though, since my USB experience is lacking at best). It feels like perhaps we're just not keeping track the xact_pos correctly, but of course I don't know that for sure... Anyway, just fishing... ;) -Doug Hi Doug, I also feel it is not quite right as the SSPLIT should be able to happen during the SSPLIT of another device. I tried to reproduce and see the same scheduling but don't see any hang due to it. Yunzhi, any details on what kind of hub and keyboard you are using? I have the same Jabra 410 speaker. You could use a single tt hub and any stander keyboard or mouse to reproduce this issue 1. connect hub keyboard and audio speaker 2. play any sound 3. then the keyboard stop working -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [RFC] usb: dwc2: hcd: fix split schedule issue
Hi John 在 2015/11/12 12:29, John Youn 写道: On 11/11/2015 4:22 PM, Doug Anderson wrote: John, On Fri, Nov 6, 2015 at 2:04 AM, Yunzhi Li <l...@rock-chips.com> wrote: hi John , As we talked yesterday, I tried to fix the split schedule sequence. This patch will avoid scheduling SSPLIT-IN packet for another device between SSPLIT-OUT-begin and SSPLIT-OUT-end, now the keyboard and Jebra audio speaker could work together well, but I'm not sure if this is exactly the right way to schedule split transfers and if there is any dide effect with this patch. Please help review this patch. Thanks. Fix dwc2 split schedule sequence issue. Not schedule a SSPLIT_IN packet between SSPLIT-begin and SSPLIT-end. Signed-off-by: Yunzhi Li <l...@rock-chips.com> --- drivers/usb/dwc2/hcd.c | 4 1 file changed, 4 insertions(+) Did you have any thoughts on this patch? Although this patch didn't fix the problems I was seeing with the Microsoft Wireless Keyboard (see the patch I sent out earlier which does seem to fix it), I can confirm that in a different setup (HUB goes to USB audio + mouse) that this patch does fix some problems. That being said, it feels to me like a band-aid rather than an actual fix (I'm talking out of my rear end, though, since my USB experience is lacking at best). It feels like perhaps we're just not keeping track the xact_pos correctly, but of course I don't know that for sure... Anyway, just fishing... ;) -Doug Hi Doug, I also feel it is not quite right as the SSPLIT should be able to happen during the SSPLIT of another device. I tried to reproduce and see the same scheduling but don't see any hang due to it. Yunzhi, any details on what kind of hub and keyboard you are using? I have the same Jabra 410 speaker. You could use a single tt hub and any stander keyboard or mouse to reproduce this issue 1. connect hub keyboard and audio speaker 2. play any sound 3. then the keyboard stop working -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [RFC] usb: dwc2: hcd: fix split schedule issue
hi Doug 在 2015/11/7 7:56, Doug Anderson 写道: lyz@, On Fri, Nov 6, 2015 at 1:36 AM, Yunzhi Li wrote: Fix dwc2 split schedule sequence issue. Not schedule a SSPLIT_IN packet between SSPLIT-begin and SSPLIT-end. Signed-off-by: Yunzhi Li --- drivers/usb/dwc2/hcd.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c index e79baf7..a32ed01 100644 --- a/drivers/usb/dwc2/hcd.c +++ b/drivers/usb/dwc2/hcd.c @@ -1122,6 +1122,10 @@ static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg) break; } + if (qh->channel->xact_pos == DWC2_HCSPLT_XACTPOS_BEGIN || + qh->channel->xact_pos == DWC2_HCSPLT_XACTPOS_MID) + break; + /* * In Slave mode, stay on the current transfer until there is * nothing more to do or the high-bandwidth request count is Just a quite note to say that this doesn't seem to resolve the weird errors I'm seeing with the "Microsoft Wireless Keyboard 2000" that I have. I see split transaction errors in a USB analyzer with just that hooked up behind a hub (don't even need any other USB devices). ...it is possible that there are two unrelated problems here, but it's also possible that there's some bigger root cause that will fix both of our problems. I've been poking at things a bit too, but so far no luck... -Doug It seems that we are debugging two different issues, your new patch which rewrite the microframe scheduler doesn't resolve my problem. My patch fix chrome-os issue #46547 not related to the particular Microsoft keyboard any keyboard could be used to reproduce the issue. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [RFC] usb: dwc2: hcd: fix split schedule issue
hi Doug 在 2015/11/7 7:56, Doug Anderson 写道: lyz@, On Fri, Nov 6, 2015 at 1:36 AM, Yunzhi Li <l...@rock-chips.com> wrote: Fix dwc2 split schedule sequence issue. Not schedule a SSPLIT_IN packet between SSPLIT-begin and SSPLIT-end. Signed-off-by: Yunzhi Li <l...@rock-chips.com> --- drivers/usb/dwc2/hcd.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c index e79baf7..a32ed01 100644 --- a/drivers/usb/dwc2/hcd.c +++ b/drivers/usb/dwc2/hcd.c @@ -1122,6 +1122,10 @@ static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg) break; } + if (qh->channel->xact_pos == DWC2_HCSPLT_XACTPOS_BEGIN || + qh->channel->xact_pos == DWC2_HCSPLT_XACTPOS_MID) + break; + /* * In Slave mode, stay on the current transfer until there is * nothing more to do or the high-bandwidth request count is Just a quite note to say that this doesn't seem to resolve the weird errors I'm seeing with the "Microsoft Wireless Keyboard 2000" that I have. I see split transaction errors in a USB analyzer with just that hooked up behind a hub (don't even need any other USB devices). ...it is possible that there are two unrelated problems here, but it's also possible that there's some bigger root cause that will fix both of our problems. I've been poking at things a bit too, but so far no luck... -Doug It seems that we are debugging two different issues, your new patch which rewrite the microframe scheduler doesn't resolve my problem. My patch fix chrome-os issue #46547 not related to the particular Microsoft keyboard any keyboard could be used to reproduce the issue. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [RFC] usb: dwc2: hcd: fix split schedule issue
hi John , As we talked yesterday, I tried to fix the split schedule sequence. This patch will avoid scheduling SSPLIT-IN packet for another device between SSPLIT-OUT-begin and SSPLIT-OUT-end, now the keyboard and Jebra audio speaker could work together well, but I'm not sure if this is exactly the right way to schedule split transfers and if there is any dide effect with this patch. Please help review this patch. Thanks. Fix dwc2 split schedule sequence issue. Not schedule a SSPLIT_IN packet between SSPLIT-begin and SSPLIT-end. Signed-off-by: Yunzhi Li --- drivers/usb/dwc2/hcd.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c index e79baf7..a32ed01 100644 --- a/drivers/usb/dwc2/hcd.c +++ b/drivers/usb/dwc2/hcd.c @@ -1122,6 +1122,10 @@ static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg) break; } + if (qh->channel->xact_pos == DWC2_HCSPLT_XACTPOS_BEGIN || + qh->channel->xact_pos == DWC2_HCSPLT_XACTPOS_MID) + break; + /* * In Slave mode, stay on the current transfer until there is * nothing more to do or the high-bandwidth request count is On 11/5/2015 2:13 AM, l...@rock-chips.com wrote: Hi John : We found some problem when we tested usb audio speaker on rk3288 platform which use dwc2 IP v3.10a as usb controller Steps to reproduce the problem: 1. Plug in USB2.0 hub to rk3288 platform board. 2. Plug in USB keyboard to the hub. 3. Plug in USB audio speaker speaker(Jabra 410 or 510) to the hub (These audio speakers support full speed data packet length 192 byte and it will be split into 2 SSPLIT-OUT packets (188B + 4B) in high speed bus other usb audio devices which has FS data packets length smaller then 188B not has this issue ) 4. Play music via usb speaker then USB keyboard stop working I do some debug work and try to figure out the root cause of this issue : Use the usb protocol analyzer to catch usb traffic in high speed bus I see something weired that dwc2 send SSPLIT IN for dev 5 between two SSPLIT OUT transaction for dev 6 then hub respond a NYET for dev 5 CSPLIT and keyboard not working any more. It seems some problem with split scheduling sequence and it let the hub confused, but I'm not sure which rule in usb20 spec chapters 11 is broken and how to fix it. DWC2 traffic I alsocatch the usb traffic between an EHCI controller in pc and the hub connected with audio speaker and keyboard both keyboard and audio speaker work well with EHCI. EHCI schedules the SSPLIT IN for keyboard in the next microframe after OUT SSPLIT OUT for audio data packets and the hub can respond NAK . EHCI traffic I will keep on debugging for this issue and try to fix the scheduling sequence , does anyone have any ideas could be help with this issue ? l...@rock-chips.com Thanks for this report. I'll try to reproduce and forward it along to some of our experts. Regards, John -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[RFC] usb: dwc2: hcd: fix split schedule issue
Fix dwc2 split schedule sequence issue. Not schedule a SSPLIT_IN packet between SSPLIT-begin and SSPLIT-end. Signed-off-by: Yunzhi Li --- drivers/usb/dwc2/hcd.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c index e79baf7..a32ed01 100644 --- a/drivers/usb/dwc2/hcd.c +++ b/drivers/usb/dwc2/hcd.c @@ -1122,6 +1122,10 @@ static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg) break; } + if (qh->channel->xact_pos == DWC2_HCSPLT_XACTPOS_BEGIN || + qh->channel->xact_pos == DWC2_HCSPLT_XACTPOS_MID) + break; + /* * In Slave mode, stay on the current transfer until there is * nothing more to do or the high-bandwidth request count is -- 2.0.0 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [RFC] usb: dwc2: hcd: fix split schedule issue
hi John , As we talked yesterday, I tried to fix the split schedule sequence. This patch will avoid scheduling SSPLIT-IN packet for another device between SSPLIT-OUT-begin and SSPLIT-OUT-end, now the keyboard and Jebra audio speaker could work together well, but I'm not sure if this is exactly the right way to schedule split transfers and if there is any dide effect with this patch. Please help review this patch. Thanks. Fix dwc2 split schedule sequence issue. Not schedule a SSPLIT_IN packet between SSPLIT-begin and SSPLIT-end. Signed-off-by: Yunzhi Li <l...@rock-chips.com> --- drivers/usb/dwc2/hcd.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c index e79baf7..a32ed01 100644 --- a/drivers/usb/dwc2/hcd.c +++ b/drivers/usb/dwc2/hcd.c @@ -1122,6 +1122,10 @@ static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg) break; } + if (qh->channel->xact_pos == DWC2_HCSPLT_XACTPOS_BEGIN || + qh->channel->xact_pos == DWC2_HCSPLT_XACTPOS_MID) + break; + /* * In Slave mode, stay on the current transfer until there is * nothing more to do or the high-bandwidth request count is On 11/5/2015 2:13 AM, l...@rock-chips.com wrote: Hi John : We found some problem when we tested usb audio speaker on rk3288 platform which use dwc2 IP v3.10a as usb controller Steps to reproduce the problem: 1. Plug in USB2.0 hub to rk3288 platform board. 2. Plug in USB keyboard to the hub. 3. Plug in USB audio speaker speaker(Jabra 410 or 510) to the hub (These audio speakers support full speed data packet length 192 byte and it will be split into 2 SSPLIT-OUT packets (188B + 4B) in high speed bus other usb audio devices which has FS data packets length smaller then 188B not has this issue ) 4. Play music via usb speaker then USB keyboard stop working I do some debug work and try to figure out the root cause of this issue : Use the usb protocol analyzer to catch usb traffic in high speed bus I see something weired that dwc2 send SSPLIT IN for dev 5 between two SSPLIT OUT transaction for dev 6 then hub respond a NYET for dev 5 CSPLIT and keyboard not working any more. It seems some problem with split scheduling sequence and it let the hub confused, but I'm not sure which rule in usb20 spec chapters 11 is broken and how to fix it. DWC2 traffic I alsocatch the usb traffic between an EHCI controller in pc and the hub connected with audio speaker and keyboard both keyboard and audio speaker work well with EHCI. EHCI schedules the SSPLIT IN for keyboard in the next microframe after OUT SSPLIT OUT for audio data packets and the hub can respond NAK . EHCI traffic I will keep on debugging for this issue and try to fix the scheduling sequence , does anyone have any ideas could be help with this issue ? l...@rock-chips.com Thanks for this report. I'll try to reproduce and forward it along to some of our experts. Regards, John -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[RFC] usb: dwc2: hcd: fix split schedule issue
Fix dwc2 split schedule sequence issue. Not schedule a SSPLIT_IN packet between SSPLIT-begin and SSPLIT-end. Signed-off-by: Yunzhi Li <l...@rock-chips.com> --- drivers/usb/dwc2/hcd.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c index e79baf7..a32ed01 100644 --- a/drivers/usb/dwc2/hcd.c +++ b/drivers/usb/dwc2/hcd.c @@ -1122,6 +1122,10 @@ static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg) break; } + if (qh->channel->xact_pos == DWC2_HCSPLT_XACTPOS_BEGIN || + qh->channel->xact_pos == DWC2_HCSPLT_XACTPOS_MID) + break; + /* * In Slave mode, stay on the current transfer until there is * nothing more to do or the high-bandwidth request count is -- 2.0.0 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v3] usb: dwc2: reset dwc2 core before dwc2_get_hwparams()
We initiate dwc2 usb controller in BIOS, dwc2_core_reset() should
be called before dwc2_get_hwparams() to reset core registers to
default value. Without this the FIFO setting might be incorrect
because calculating FIFO size need power-on value of
GRXFSIZ/GNPTXFSIZ/HPTXFSIZ registers.
This patch could avoid warnning massage like in rk3288 platform:
[2.074764] dwc2 ff58.usb: 256 invalid for
host_perio_tx_fifo_size. Check HW configuration.
Signed-off-by: Yunzhi Li
---
drivers/usb/dwc2/core.c | 2 +-
drivers/usb/dwc2/core.h | 1 +
drivers/usb/dwc2/platform.c | 21 -
3 files changed, 22 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/dwc2/core.c b/drivers/usb/dwc2/core.c
index c3cc1a7..86d1d65 100644
--- a/drivers/usb/dwc2/core.c
+++ b/drivers/usb/dwc2/core.c
@@ -474,7 +474,7 @@ static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg
*hsotg)
* Do core a soft reset of the core. Be careful with this because it
* resets all the internal state machines of the core.
*/
-static int dwc2_core_reset(struct dwc2_hsotg *hsotg)
+int dwc2_core_reset(struct dwc2_hsotg *hsotg)
{
u32 greset;
int count = 0;
diff --git a/drivers/usb/dwc2/core.h b/drivers/usb/dwc2/core.h
index 0ed87620..5d95aec 100644
--- a/drivers/usb/dwc2/core.h
+++ b/drivers/usb/dwc2/core.h
@@ -846,6 +846,7 @@ enum dwc2_halt_status {
* The following functions support initialization of the core driver component
* and the DWC_otg controller
*/
+extern int dwc2_core_reset(struct dwc2_hsotg *hsotg);
extern void dwc2_core_host_init(struct dwc2_hsotg *hsotg);
extern int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg);
extern int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore);
diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c
index 9093530..55d378a 100644
--- a/drivers/usb/dwc2/platform.c
+++ b/drivers/usb/dwc2/platform.c
@@ -166,7 +166,8 @@ static int dwc2_driver_probe(struct platform_device *dev)
struct phy *phy;
struct usb_phy *uphy;
int retval;
- int irq;
+ int irq, count = 0;
+ u32 greset;
match = of_match_device(dwc2_of_match_table, >dev);
if (match && match->data) {
@@ -243,6 +244,24 @@ static int dwc2_driver_probe(struct platform_device *dev)
spin_lock_init(>lock);
mutex_init(>init_mutex);
+ /*
+* Reset before dwc2_get_hwparams() then it could get power-on real
+* reset value form registers.
+*/
+ count = 0;
+ greset |= GRSTCTL_CSFTRST;
+ writel(greset, hsotg->regs + GRSTCTL);
+ do {
+ usleep_range(2, 4);
+ greset = readl(hsotg->regs + GRSTCTL);
+ if (++count > 50) {
+ dev_warn(hsotg->dev,
+"%s() HANG! Soft Reset GRSTCTL=%0x\n",
+__func__, greset);
+ return -EBUSY;
+ }
+ } while (greset & GRSTCTL_CSFTRST);
+
/* Detect config values from hardware */
retval = dwc2_get_hwparams(hsotg);
if (retval)
--
2.0.0
--
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[PATCH v3] usb: dwc2: reset dwc2 core before dwc2_get_hwparams()
We initiate dwc2 usb controller in BIOS, dwc2_core_reset() should
be called before dwc2_get_hwparams() to reset core registers to
default value. Without this the FIFO setting might be incorrect
because calculating FIFO size need power-on value of
GRXFSIZ/GNPTXFSIZ/HPTXFSIZ registers.
This patch could avoid warnning massage like in rk3288 platform:
[2.074764] dwc2 ff58.usb: 256 invalid for
host_perio_tx_fifo_size. Check HW configuration.
Signed-off-by: Yunzhi Li l...@rock-chips.com
---
drivers/usb/dwc2/core.c | 2 +-
drivers/usb/dwc2/core.h | 1 +
drivers/usb/dwc2/platform.c | 21 -
3 files changed, 22 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/dwc2/core.c b/drivers/usb/dwc2/core.c
index c3cc1a7..86d1d65 100644
--- a/drivers/usb/dwc2/core.c
+++ b/drivers/usb/dwc2/core.c
@@ -474,7 +474,7 @@ static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg
*hsotg)
* Do core a soft reset of the core. Be careful with this because it
* resets all the internal state machines of the core.
*/
-static int dwc2_core_reset(struct dwc2_hsotg *hsotg)
+int dwc2_core_reset(struct dwc2_hsotg *hsotg)
{
u32 greset;
int count = 0;
diff --git a/drivers/usb/dwc2/core.h b/drivers/usb/dwc2/core.h
index 0ed87620..5d95aec 100644
--- a/drivers/usb/dwc2/core.h
+++ b/drivers/usb/dwc2/core.h
@@ -846,6 +846,7 @@ enum dwc2_halt_status {
* The following functions support initialization of the core driver component
* and the DWC_otg controller
*/
+extern int dwc2_core_reset(struct dwc2_hsotg *hsotg);
extern void dwc2_core_host_init(struct dwc2_hsotg *hsotg);
extern int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg);
extern int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore);
diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c
index 9093530..55d378a 100644
--- a/drivers/usb/dwc2/platform.c
+++ b/drivers/usb/dwc2/platform.c
@@ -166,7 +166,8 @@ static int dwc2_driver_probe(struct platform_device *dev)
struct phy *phy;
struct usb_phy *uphy;
int retval;
- int irq;
+ int irq, count = 0;
+ u32 greset;
match = of_match_device(dwc2_of_match_table, dev-dev);
if (match match-data) {
@@ -243,6 +244,24 @@ static int dwc2_driver_probe(struct platform_device *dev)
spin_lock_init(hsotg-lock);
mutex_init(hsotg-init_mutex);
+ /*
+* Reset before dwc2_get_hwparams() then it could get power-on real
+* reset value form registers.
+*/
+ count = 0;
+ greset |= GRSTCTL_CSFTRST;
+ writel(greset, hsotg-regs + GRSTCTL);
+ do {
+ usleep_range(2, 4);
+ greset = readl(hsotg-regs + GRSTCTL);
+ if (++count 50) {
+ dev_warn(hsotg-dev,
+%s() HANG! Soft Reset GRSTCTL=%0x\n,
+__func__, greset);
+ return -EBUSY;
+ }
+ } while (greset GRSTCTL_CSFTRST);
+
/* Detect config values from hardware */
retval = dwc2_get_hwparams(hsotg);
if (retval)
--
2.0.0
--
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the body of a message to majord...@vger.kernel.org
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Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v1 1/3] usb: dwc2: reset AHB hclk domain before init
Hi John, 在 2015/8/15 3:41, John Youn 写道: > On 8/13/2015 8:29 PM, Yunzhi Li wrote: >> >> 在 2015/8/14 8:09, John Youn 写道: >>> On 8/11/2015 12:57 AM, Yunzhi Li wrote: >>>> We initiate dwc2 usb controller in BIOS, when kernel driver >>>> start-up we should reset AHB hclk domain to reset all AHB >>>> interface registers to default. Without this the FIFO value >>>> setting might be incorrect because calculating FIFO size need the >>>> power-on value of GRXFSIZ/GNPTXFSIZ/HPTXFSIZ registers. >>>> >>>> This patch could avoid warnning massage like in rk3288 platform: >>>> [2.074764] dwc2 ff58.usb: 256 invalid for >>>> host_perio_tx_fifo_size. Check HW configuration. >>>> >>>> .. >>> I didn't receive the other two patches in this series so I was >>> confused about where the "ahb_reset" was coming from when I >>> replied to your other patch. >>> >>> I see you changed the name and documented the DT so never mind. >>> >>> Another thing is that there probably shouldn't be a debug >>> message on the IS_ERR condition since that is the common case >>> and of no interest to other platforms. >>> >>> The other two resets you added aren't used by the driver >>> anywhere right? Maybe those should be left out until they are. >>> >>> John >>> >> Hi John , >> >>Here is the other two patches : >> https://patchwork.kernel.org/patch/6989541/ >> https://patchwork.kernel.org/patch/6989531/ >> >>ahb_reset is hreset_n signal of dwc2 IP. Our rk3288 SoC implement >> connect this signal to a special >> register in clock ang reset unit (CRU) module, set this register will >> reset dwc2 control and status registers(CSR) >> to default value. You could find more info in <> Hi Speed On-TheGo (OTG) Databook 3.10a>> >> 4.4.1 System Clock and Reset Signals. >> >>Our problem is that dwc2_get_hwparams() reads fifo size registers and >> reguards it as the power-on reset value, >> then dwc2_set_param_host_perio_tx_fifo_size() will check this value and >> make sure the new fifo size value is no bigger >> than the power-on reset value. But we init and set these fifo registers >> in BIOS, so here hw->xxx_fifo_size is not the >> real power-on reset vaule. So we hope to reset CSR before >> dwc2_get_hwparams(). >> >> I have another ideal: we might use GRSTCTL.CSftRst instead of hreset_n >> to reset dwc2 CSR. > > Yes, please try doing that before calling dwc2_get_hwparams(). > Maybe by calling dwc2_core_reset(). If that works for you, I think > it would be better. > > John > > It works and please help review the new patch. Thanks. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v2] usb: dwc2: reset dwc2 core before dwc2_get_hwparams()
We initiate dwc2 usb controller in BIOS, dwc2_core_reset() should
be called before dwc2_get_hwparams() to reset core registers to
default value. Without this the FIFO setting might be incorrect
because calculating FIFO size need power-on value of
GRXFSIZ/GNPTXFSIZ/HPTXFSIZ registers.
This patch could avoid warnning massage like in rk3288 platform:
[2.074764] dwc2 ff58.usb: 256 invalid for
host_perio_tx_fifo_size. Check HW configuration.
Signed-off-by: Yunzhi Li
---
drivers/usb/dwc2/core.c | 2 +-
drivers/usb/dwc2/core.h | 1 +
drivers/usb/dwc2/platform.c | 6 ++
3 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/dwc2/core.c b/drivers/usb/dwc2/core.c
index c3cc1a7..86d1d65 100644
--- a/drivers/usb/dwc2/core.c
+++ b/drivers/usb/dwc2/core.c
@@ -474,7 +474,7 @@ static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg
*hsotg)
* Do core a soft reset of the core. Be careful with this because it
* resets all the internal state machines of the core.
*/
-static int dwc2_core_reset(struct dwc2_hsotg *hsotg)
+int dwc2_core_reset(struct dwc2_hsotg *hsotg)
{
u32 greset;
int count = 0;
diff --git a/drivers/usb/dwc2/core.h b/drivers/usb/dwc2/core.h
index 0ed87620..5d95aec 100644
--- a/drivers/usb/dwc2/core.h
+++ b/drivers/usb/dwc2/core.h
@@ -846,6 +846,7 @@ enum dwc2_halt_status {
* The following functions support initialization of the core driver component
* and the DWC_otg controller
*/
+extern int dwc2_core_reset(struct dwc2_hsotg *hsotg);
extern void dwc2_core_host_init(struct dwc2_hsotg *hsotg);
extern int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg);
extern int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore);
diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c
index 9093530..8d3be4a 100644
--- a/drivers/usb/dwc2/platform.c
+++ b/drivers/usb/dwc2/platform.c
@@ -243,6 +243,12 @@ static int dwc2_driver_probe(struct platform_device *dev)
spin_lock_init(>lock);
mutex_init(>init_mutex);
+ /*
+* Reset before dwc2_get_hwparams() then it could get power-on real
+* reset value form registers.
+*/
+ dwc2_core_reset(hsotg);
+
/* Detect config values from hardware */
retval = dwc2_get_hwparams(hsotg);
if (retval)
--
2.0.0
--
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the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v1 1/3] usb: dwc2: reset AHB hclk domain before init
Hi John, 在 2015/8/15 3:41, John Youn 写道: On 8/13/2015 8:29 PM, Yunzhi Li wrote: 在 2015/8/14 8:09, John Youn 写道: On 8/11/2015 12:57 AM, Yunzhi Li wrote: We initiate dwc2 usb controller in BIOS, when kernel driver start-up we should reset AHB hclk domain to reset all AHB interface registers to default. Without this the FIFO value setting might be incorrect because calculating FIFO size need the power-on value of GRXFSIZ/GNPTXFSIZ/HPTXFSIZ registers. This patch could avoid warnning massage like in rk3288 platform: [2.074764] dwc2 ff58.usb: 256 invalid for host_perio_tx_fifo_size. Check HW configuration. .. I didn't receive the other two patches in this series so I was confused about where the ahb_reset was coming from when I replied to your other patch. I see you changed the name and documented the DT so never mind. Another thing is that there probably shouldn't be a debug message on the IS_ERR condition since that is the common case and of no interest to other platforms. The other two resets you added aren't used by the driver anywhere right? Maybe those should be left out until they are. John Hi John , Here is the other two patches : https://patchwork.kernel.org/patch/6989541/ https://patchwork.kernel.org/patch/6989531/ ahb_reset is hreset_n signal of dwc2 IP. Our rk3288 SoC implement connect this signal to a special register in clock ang reset unit (CRU) module, set this register will reset dwc2 control and status registers(CSR) to default value. You could find more info in DesignWare Cores USB 2.0 Hi Speed On-TheGo (OTG) Databook 3.10a 4.4.1 System Clock and Reset Signals. Our problem is that dwc2_get_hwparams() reads fifo size registers and reguards it as the power-on reset value, then dwc2_set_param_host_perio_tx_fifo_size() will check this value and make sure the new fifo size value is no bigger than the power-on reset value. But we init and set these fifo registers in BIOS, so here hw-xxx_fifo_size is not the real power-on reset vaule. So we hope to reset CSR before dwc2_get_hwparams(). I have another ideal: we might use GRSTCTL.CSftRst instead of hreset_n to reset dwc2 CSR. Yes, please try doing that before calling dwc2_get_hwparams(). Maybe by calling dwc2_core_reset(). If that works for you, I think it would be better. John It works and please help review the new patch. Thanks. -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v2] usb: dwc2: reset dwc2 core before dwc2_get_hwparams()
We initiate dwc2 usb controller in BIOS, dwc2_core_reset() should
be called before dwc2_get_hwparams() to reset core registers to
default value. Without this the FIFO setting might be incorrect
because calculating FIFO size need power-on value of
GRXFSIZ/GNPTXFSIZ/HPTXFSIZ registers.
This patch could avoid warnning massage like in rk3288 platform:
[2.074764] dwc2 ff58.usb: 256 invalid for
host_perio_tx_fifo_size. Check HW configuration.
Signed-off-by: Yunzhi Li l...@rock-chips.com
---
drivers/usb/dwc2/core.c | 2 +-
drivers/usb/dwc2/core.h | 1 +
drivers/usb/dwc2/platform.c | 6 ++
3 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/dwc2/core.c b/drivers/usb/dwc2/core.c
index c3cc1a7..86d1d65 100644
--- a/drivers/usb/dwc2/core.c
+++ b/drivers/usb/dwc2/core.c
@@ -474,7 +474,7 @@ static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg
*hsotg)
* Do core a soft reset of the core. Be careful with this because it
* resets all the internal state machines of the core.
*/
-static int dwc2_core_reset(struct dwc2_hsotg *hsotg)
+int dwc2_core_reset(struct dwc2_hsotg *hsotg)
{
u32 greset;
int count = 0;
diff --git a/drivers/usb/dwc2/core.h b/drivers/usb/dwc2/core.h
index 0ed87620..5d95aec 100644
--- a/drivers/usb/dwc2/core.h
+++ b/drivers/usb/dwc2/core.h
@@ -846,6 +846,7 @@ enum dwc2_halt_status {
* The following functions support initialization of the core driver component
* and the DWC_otg controller
*/
+extern int dwc2_core_reset(struct dwc2_hsotg *hsotg);
extern void dwc2_core_host_init(struct dwc2_hsotg *hsotg);
extern int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg);
extern int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore);
diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c
index 9093530..8d3be4a 100644
--- a/drivers/usb/dwc2/platform.c
+++ b/drivers/usb/dwc2/platform.c
@@ -243,6 +243,12 @@ static int dwc2_driver_probe(struct platform_device *dev)
spin_lock_init(hsotg-lock);
mutex_init(hsotg-init_mutex);
+ /*
+* Reset before dwc2_get_hwparams() then it could get power-on real
+* reset value form registers.
+*/
+ dwc2_core_reset(hsotg);
+
/* Detect config values from hardware */
retval = dwc2_get_hwparams(hsotg);
if (retval)
--
2.0.0
--
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the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v1 1/3] usb: dwc2: reset AHB hclk domain before init
在 2015/8/14 8:09, John Youn 写道: On 8/11/2015 12:57 AM, Yunzhi Li wrote: We initiate dwc2 usb controller in BIOS, when kernel driver start-up we should reset AHB hclk domain to reset all AHB interface registers to default. Without this the FIFO value setting might be incorrect because calculating FIFO size need the power-on value of GRXFSIZ/GNPTXFSIZ/HPTXFSIZ registers. This patch could avoid warnning massage like in rk3288 platform: [2.074764] dwc2 ff58.usb: 256 invalid for host_perio_tx_fifo_size. Check HW configuration. .. I didn't receive the other two patches in this series so I was confused about where the "ahb_reset" was coming from when I replied to your other patch. I see you changed the name and documented the DT so never mind. Another thing is that there probably shouldn't be a debug message on the IS_ERR condition since that is the common case and of no interest to other platforms. The other two resets you added aren't used by the driver anywhere right? Maybe those should be left out until they are. John Hi John , Here is the other two patches : https://patchwork.kernel.org/patch/6989541/ https://patchwork.kernel.org/patch/6989531/ ahb_reset is hreset_n signal of dwc2 IP. Our rk3288 SoC implement connect this signal to a special register in clock ang reset unit (CRU) module, set this register will reset dwc2 control and status registers(CSR) to default value. You could find more info in <Hi Speed On-TheGo (OTG) Databook 3.10a>> 4.4.1 System Clock and Reset Signals. Our problem is that dwc2_get_hwparams() reads fifo size registers and reguards it as the power-on reset value, then dwc2_set_param_host_perio_tx_fifo_size() will check this value and make sure the new fifo size value is no bigger than the power-on reset value. But we init and set these fifo registers in BIOS, so here hw->xxx_fifo_size is not the real power-on reset vaule. So we hope to reset CSR before dwc2_get_hwparams(). I have another ideal: we might use GRSTCTL.CSftRst instead of hreset_n to reset dwc2 CSR. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v1 1/3] usb: dwc2: reset AHB hclk domain before init
在 2015/8/14 8:09, John Youn 写道: On 8/11/2015 12:57 AM, Yunzhi Li wrote: We initiate dwc2 usb controller in BIOS, when kernel driver start-up we should reset AHB hclk domain to reset all AHB interface registers to default. Without this the FIFO value setting might be incorrect because calculating FIFO size need the power-on value of GRXFSIZ/GNPTXFSIZ/HPTXFSIZ registers. This patch could avoid warnning massage like in rk3288 platform: [2.074764] dwc2 ff58.usb: 256 invalid for host_perio_tx_fifo_size. Check HW configuration. .. I didn't receive the other two patches in this series so I was confused about where the ahb_reset was coming from when I replied to your other patch. I see you changed the name and documented the DT so never mind. Another thing is that there probably shouldn't be a debug message on the IS_ERR condition since that is the common case and of no interest to other platforms. The other two resets you added aren't used by the driver anywhere right? Maybe those should be left out until they are. John Hi John , Here is the other two patches : https://patchwork.kernel.org/patch/6989541/ https://patchwork.kernel.org/patch/6989531/ ahb_reset is hreset_n signal of dwc2 IP. Our rk3288 SoC implement connect this signal to a special register in clock ang reset unit (CRU) module, set this register will reset dwc2 control and status registers(CSR) to default value. You could find more info in DesignWare Cores USB 2.0 Hi Speed On-TheGo (OTG) Databook 3.10a 4.4.1 System Clock and Reset Signals. Our problem is that dwc2_get_hwparams() reads fifo size registers and reguards it as the power-on reset value, then dwc2_set_param_host_perio_tx_fifo_size() will check this value and make sure the new fifo size value is no bigger than the power-on reset value. But we init and set these fifo registers in BIOS, so here hw-xxx_fifo_size is not the real power-on reset vaule. So we hope to reset CSR before dwc2_get_hwparams(). I have another ideal: we might use GRSTCTL.CSftRst instead of hreset_n to reset dwc2 CSR. -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v1] usb: dwc2: reset AHB hclk domain before init
Hi , 在 2015/8/11 22:12, Felipe Balbi 写道: Hi, On Tue, Aug 11, 2015 at 10:27:42AM +0800, Yunzhi Li wrote: We initiate dwc2 usb controller in BIOS, when kernel driver start-up we should reset AHB hclk domain to reset all AHB interface registers to default. Without this the FIFO value setting might be incorrect because calculating FIFO size need the power-on value of GRXFSIZ/GNPTXFSIZ/HPTXFSIZ registers. This patch could avoid warnning massage like in rk3288 platform: [2.074764] dwc2 ff58.usb: 256 invalid for host_perio_tx_fifo_size. Check HW configuration. Signed-off-by: Yunzhi Li --- drivers/usb/dwc2/platform.c | 12 1 file changed, 12 insertions(+) diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c index 9093530..3da21ab 100644 --- a/drivers/usb/dwc2/platform.c +++ b/drivers/usb/dwc2/platform.c @@ -42,6 +42,7 @@ #include #include #include +#include #include @@ -165,6 +166,7 @@ static int dwc2_driver_probe(struct platform_device *dev) struct resource *res; struct phy *phy; struct usb_phy *uphy; + struct reset_control *rst; int retval; int irq; @@ -189,6 +191,16 @@ static int dwc2_driver_probe(struct platform_device *dev) hsotg->dev = >dev; + /* AHB hclk domain reset, set all AHB interface registers to default */ + rst = devm_reset_control_get_optional(>dev, "ahb_reset"); why isn't this done in core so PCI systems can also make use of it ? I have no ides about how to reset a PCI interface dwc2 controller, John could you please give some infomation about it ? Is it also needed for PCI interface dwc2 IP ? -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v1] usb: dwc2: reset AHB hclk domain before init
Hi , 在 2015/8/11 22:12, Felipe Balbi 写道: Hi, On Tue, Aug 11, 2015 at 10:27:42AM +0800, Yunzhi Li wrote: We initiate dwc2 usb controller in BIOS, when kernel driver start-up we should reset AHB hclk domain to reset all AHB interface registers to default. Without this the FIFO value setting might be incorrect because calculating FIFO size need the power-on value of GRXFSIZ/GNPTXFSIZ/HPTXFSIZ registers. This patch could avoid warnning massage like in rk3288 platform: [2.074764] dwc2 ff58.usb: 256 invalid for host_perio_tx_fifo_size. Check HW configuration. Signed-off-by: Yunzhi Li l...@rock-chips.com --- drivers/usb/dwc2/platform.c | 12 1 file changed, 12 insertions(+) diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c index 9093530..3da21ab 100644 --- a/drivers/usb/dwc2/platform.c +++ b/drivers/usb/dwc2/platform.c @@ -42,6 +42,7 @@ #include linux/of_device.h #include linux/mutex.h #include linux/platform_device.h +#include linux/reset.h #include linux/usb/of.h @@ -165,6 +166,7 @@ static int dwc2_driver_probe(struct platform_device *dev) struct resource *res; struct phy *phy; struct usb_phy *uphy; + struct reset_control *rst; int retval; int irq; @@ -189,6 +191,16 @@ static int dwc2_driver_probe(struct platform_device *dev) hsotg-dev = dev-dev; + /* AHB hclk domain reset, set all AHB interface registers to default */ + rst = devm_reset_control_get_optional(dev-dev, ahb_reset); why isn't this done in core so PCI systems can also make use of it ? I have no ides about how to reset a PCI interface dwc2 controller, John could you please give some infomation about it ? Is it also needed for PCI interface dwc2 IP ? -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v1 2/3] Documentation: dt-bindings: add dt binding info for dwc2 reset control
Signed-off-by: Yunzhi Li --- Documentation/devicetree/bindings/usb/dwc2.txt | 6 ++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/dwc2.txt b/Documentation/devicetree/bindings/usb/dwc2.txt index fd132cb..6a84099 100644 --- a/Documentation/devicetree/bindings/usb/dwc2.txt +++ b/Documentation/devicetree/bindings/usb/dwc2.txt @@ -24,6 +24,12 @@ Refer to phy/phy-bindings.txt for generic phy consumer properties - g-rx-fifo-size: size of rx fifo size in gadget mode. - g-np-tx-fifo-size: size of non-periodic tx fifo size in gadget mode. - g-tx-fifo-size: size of periodic tx fifo per endpoint (except ep0) in gadget mode. +- resets: A list of phandle + reset-specifier pairs for the resets listed in + reset-names +- reset-names: Should contain the following: + "ahb": AHB interface reset + "phy": PHY reset + "con": controller reset Example: -- 2.0.0 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v1 3/3] ARM: dts: rockchip: add dwc2 ahb reset property for rk3288
This patch adds dwc2 reset property for rk3288 dwc2 usb controller to fix FIFO setting bug Signed-off-by: Yunzhi Li --- arch/arm/boot/dts/rk3288.dtsi | 8 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 22316d0..440aa42 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -473,6 +473,10 @@ dr_mode = "host"; phys = <>; phy-names = "usb2-phy"; + resets = < SRST_USBHOST1_AHB>, +< SRST_USBHOST1_PHY>, +< SRST_USBHOST1_CON>; + reset-names = "ahb", "phy", "con"; status = "disabled"; }; @@ -490,6 +494,10 @@ g-use-dma; phys = <>; phy-names = "usb2-phy"; + resets = < SRST_USBOTG_AHB>, +< SRST_USBOTG_PHY>, +< SRST_USBOTG_CON>; + reset-names = "ahb", "phy", "con"; status = "disabled"; }; -- 2.0.0 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v1 1/3] usb: dwc2: reset AHB hclk domain before init
We initiate dwc2 usb controller in BIOS, when kernel driver
start-up we should reset AHB hclk domain to reset all AHB
interface registers to default. Without this the FIFO value
setting might be incorrect because calculating FIFO size need the
power-on value of GRXFSIZ/GNPTXFSIZ/HPTXFSIZ registers.
This patch could avoid warnning massage like in rk3288 platform:
[2.074764] dwc2 ff58.usb: 256 invalid for
host_perio_tx_fifo_size. Check HW configuration.
Signed-off-by: Yunzhi Li
---
drivers/usb/dwc2/platform.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c
index 9093530..ec6bf6b 100644
--- a/drivers/usb/dwc2/platform.c
+++ b/drivers/usb/dwc2/platform.c
@@ -42,6 +42,7 @@
#include
#include
#include
+#include
#include
@@ -165,6 +166,7 @@ static int dwc2_driver_probe(struct platform_device *dev)
struct resource *res;
struct phy *phy;
struct usb_phy *uphy;
+ struct reset_control *rst;
int retval;
int irq;
@@ -189,6 +191,16 @@ static int dwc2_driver_probe(struct platform_device *dev)
hsotg->dev = >dev;
+ /* AHB hclk domain reset, set all AHB interface registers to default */
+ rst = devm_reset_control_get_optional(>dev, "ahb");
+ if (IS_ERR(rst)) {
+ dev_dbg(>dev, "Can't get dwc2 AHB reset\n");
+ } else {
+ reset_control_assert(rst);
+ udelay(5);
+ reset_control_deassert(rst);
+ }
+
/*
* Use reasonable defaults so platforms don't have to provide these.
*/
--
2.0.0
--
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the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[PATCH v1 1/3] usb: dwc2: reset AHB hclk domain before init
We initiate dwc2 usb controller in BIOS, when kernel driver
start-up we should reset AHB hclk domain to reset all AHB
interface registers to default. Without this the FIFO value
setting might be incorrect because calculating FIFO size need the
power-on value of GRXFSIZ/GNPTXFSIZ/HPTXFSIZ registers.
This patch could avoid warnning massage like in rk3288 platform:
[2.074764] dwc2 ff58.usb: 256 invalid for
host_perio_tx_fifo_size. Check HW configuration.
Signed-off-by: Yunzhi Li l...@rock-chips.com
---
drivers/usb/dwc2/platform.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c
index 9093530..ec6bf6b 100644
--- a/drivers/usb/dwc2/platform.c
+++ b/drivers/usb/dwc2/platform.c
@@ -42,6 +42,7 @@
#include linux/of_device.h
#include linux/mutex.h
#include linux/platform_device.h
+#include linux/reset.h
#include linux/usb/of.h
@@ -165,6 +166,7 @@ static int dwc2_driver_probe(struct platform_device *dev)
struct resource *res;
struct phy *phy;
struct usb_phy *uphy;
+ struct reset_control *rst;
int retval;
int irq;
@@ -189,6 +191,16 @@ static int dwc2_driver_probe(struct platform_device *dev)
hsotg-dev = dev-dev;
+ /* AHB hclk domain reset, set all AHB interface registers to default */
+ rst = devm_reset_control_get_optional(dev-dev, ahb);
+ if (IS_ERR(rst)) {
+ dev_dbg(dev-dev, Can't get dwc2 AHB reset\n);
+ } else {
+ reset_control_assert(rst);
+ udelay(5);
+ reset_control_deassert(rst);
+ }
+
/*
* Use reasonable defaults so platforms don't have to provide these.
*/
--
2.0.0
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[PATCH v1 2/3] Documentation: dt-bindings: add dt binding info for dwc2 reset control
Signed-off-by: Yunzhi Li l...@rock-chips.com --- Documentation/devicetree/bindings/usb/dwc2.txt | 6 ++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/dwc2.txt b/Documentation/devicetree/bindings/usb/dwc2.txt index fd132cb..6a84099 100644 --- a/Documentation/devicetree/bindings/usb/dwc2.txt +++ b/Documentation/devicetree/bindings/usb/dwc2.txt @@ -24,6 +24,12 @@ Refer to phy/phy-bindings.txt for generic phy consumer properties - g-rx-fifo-size: size of rx fifo size in gadget mode. - g-np-tx-fifo-size: size of non-periodic tx fifo size in gadget mode. - g-tx-fifo-size: size of periodic tx fifo per endpoint (except ep0) in gadget mode. +- resets: A list of phandle + reset-specifier pairs for the resets listed in + reset-names +- reset-names: Should contain the following: + ahb: AHB interface reset + phy: PHY reset + con: controller reset Example: -- 2.0.0 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v1 3/3] ARM: dts: rockchip: add dwc2 ahb reset property for rk3288
This patch adds dwc2 reset property for rk3288 dwc2 usb controller to fix FIFO setting bug Signed-off-by: Yunzhi Li l...@rock-chips.com --- arch/arm/boot/dts/rk3288.dtsi | 8 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 22316d0..440aa42 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -473,6 +473,10 @@ dr_mode = host; phys = usbphy2; phy-names = usb2-phy; + resets = cru SRST_USBHOST1_AHB, +cru SRST_USBHOST1_PHY, +cru SRST_USBHOST1_CON; + reset-names = ahb, phy, con; status = disabled; }; @@ -490,6 +494,10 @@ g-use-dma; phys = usbphy0; phy-names = usb2-phy; + resets = cru SRST_USBOTG_AHB, +cru SRST_USBOTG_PHY, +cru SRST_USBOTG_CON; + reset-names = ahb, phy, con; status = disabled; }; -- 2.0.0 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v1] usb: dwc2: reset AHB hclk domain before init
We initiate dwc2 usb controller in BIOS, when kernel driver
start-up we should reset AHB hclk domain to reset all AHB
interface registers to default. Without this the FIFO value
setting might be incorrect because calculating FIFO size need the
power-on value of GRXFSIZ/GNPTXFSIZ/HPTXFSIZ registers.
This patch could avoid warnning massage like in rk3288 platform:
[2.074764] dwc2 ff58.usb: 256 invalid for
host_perio_tx_fifo_size. Check HW configuration.
Signed-off-by: Yunzhi Li
---
drivers/usb/dwc2/platform.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c
index 9093530..3da21ab 100644
--- a/drivers/usb/dwc2/platform.c
+++ b/drivers/usb/dwc2/platform.c
@@ -42,6 +42,7 @@
#include
#include
#include
+#include
#include
@@ -165,6 +166,7 @@ static int dwc2_driver_probe(struct platform_device *dev)
struct resource *res;
struct phy *phy;
struct usb_phy *uphy;
+ struct reset_control *rst;
int retval;
int irq;
@@ -189,6 +191,16 @@ static int dwc2_driver_probe(struct platform_device *dev)
hsotg->dev = >dev;
+ /* AHB hclk domain reset, set all AHB interface registers to default */
+ rst = devm_reset_control_get_optional(>dev, "ahb_reset");
+ if (IS_ERR(rst)) {
+ dev_dbg(>dev, "Can't get dwc2 AHB reset\n");
+ } else {
+ reset_control_assert(rst);
+ udelay(5);
+ reset_control_deassert(rst);
+ }
+
/*
* Use reasonable defaults so platforms don't have to provide these.
*/
--
2.0.0
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[PATCH v1] usb: dwc2: reset AHB hclk domain before init
We initiate dwc2 usb controller in BIOS, when kernel driver
start-up we should reset AHB hclk domain to reset all AHB
interface registers to default. Without this the FIFO value
setting might be incorrect because calculating FIFO size need the
power-on value of GRXFSIZ/GNPTXFSIZ/HPTXFSIZ registers.
This patch could avoid warnning massage like in rk3288 platform:
[2.074764] dwc2 ff58.usb: 256 invalid for
host_perio_tx_fifo_size. Check HW configuration.
Signed-off-by: Yunzhi Li l...@rock-chips.com
---
drivers/usb/dwc2/platform.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c
index 9093530..3da21ab 100644
--- a/drivers/usb/dwc2/platform.c
+++ b/drivers/usb/dwc2/platform.c
@@ -42,6 +42,7 @@
#include linux/of_device.h
#include linux/mutex.h
#include linux/platform_device.h
+#include linux/reset.h
#include linux/usb/of.h
@@ -165,6 +166,7 @@ static int dwc2_driver_probe(struct platform_device *dev)
struct resource *res;
struct phy *phy;
struct usb_phy *uphy;
+ struct reset_control *rst;
int retval;
int irq;
@@ -189,6 +191,16 @@ static int dwc2_driver_probe(struct platform_device *dev)
hsotg-dev = dev-dev;
+ /* AHB hclk domain reset, set all AHB interface registers to default */
+ rst = devm_reset_control_get_optional(dev-dev, ahb_reset);
+ if (IS_ERR(rst)) {
+ dev_dbg(dev-dev, Can't get dwc2 AHB reset\n);
+ } else {
+ reset_control_assert(rst);
+ udelay(5);
+ reset_control_deassert(rst);
+ }
+
/*
* Use reasonable defaults so platforms don't have to provide these.
*/
--
2.0.0
--
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the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[PATCH v1] usb: dwc2: gadget: fix a memory use-after-free bug
When s3c_hsotg_handle_unaligned_buf_complete() hs_req->req.buf already destroyed, in s3c_hsotg_unmap_dma(), it touches hs_req->req.dma again, so s3c_hsotg_unmap_dma() should be called before s3c_hsotg_handle_unaligned_buf_complete(). Otherwise, it will cause a bad_page BUG, when allocate this memory page next time. This bug led to the following crash: BUG: Bad page state in process swapper/0 pfn:2bdbc [ 26.820440] page:eed76780 count:0 mapcount:0 mapping: (null) index:0x0 [ 26.854710] page flags: 0x200(arch_1) [ 26.885836] page dumped because: PAGE_FLAGS_CHECK_AT_PREP flag set [ 26.919179] bad because of flags: [ 26.948917] page flags: 0x200(arch_1) [ 26.979100] Modules linked in: [ 27.008401] CPU: 0 PID: 0 Comm: swapper/0 Tainted: G W3.14.0 #17 [ 27.041816] [] (unwind_backtrace) from [] (show_stack+0x20/0x24) [ 27.076108] [] (show_stack) from [] (dump_stack+0x70/0x8c) [ 27.110246] [] (dump_stack) from [] (bad_page+0xfc/0x12c) [ 27.143958] [] (bad_page) from [] (get_page_from_freelist+0x3e4/0x50c) [ 27.179298] [] (get_page_from_freelist) from [] (__alloc_pages_nodemask) [ 27.216296] [] (__alloc_pages_nodemask) from [] (__get_free_pages+0x20/) [ 27.252326] [] (__get_free_pages) from [] (kmalloc_order_trace+0x34/0xa) [ 27.288295] [] (kmalloc_order_trace) from [] (__kmalloc+0x40/0x1ac) [ 27.323751] [] (__kmalloc) from [] (s3c_hsotg_ep_queue.isra.12+0x7c/0x1) [ 27.359937] [] (s3c_hsotg_ep_queue.isra.12) from [] (s3c_hsotg_ep_queue) [ 27.397478] [] (s3c_hsotg_ep_queue_lock) from [] (rx_submit+0xfc/0x164) [ 27.433619] [] (rx_submit) from [] (rx_complete+0x22c/0x230) [ 27.468872] [] (rx_complete) from [] (s3c_hsotg_complete_request+0xfc/0) [ 27.506240] [] (s3c_hsotg_complete_request) from [] (s3c_hsotg_handle_o) [ 27.545401] [] (s3c_hsotg_handle_outdone) from [] (s3c_hsotg_epint+0x2c) [ 27.583689] [] (s3c_hsotg_epint) from [] (s3c_hsotg_irq+0x1dc/0x4ac) [ 27.621041] [] (s3c_hsotg_irq) from [] (handle_irq_event_percpu+0x70/0x) [ 27.659066] [] (handle_irq_event_percpu) from [] (handle_irq_event+0x4c) [ 27.697322] [] (handle_irq_event) from [] (handle_fasteoi_irq+0xc8/0x11) [ 27.735451] [] (handle_fasteoi_irq) from [] (generic_handle_irq+0x30/0x) [ 27.773918] [] (generic_handle_irq) from [] (__handle_domain_irq+0x84/0) [ 27.812018] [] (__handle_domain_irq) from [] (gic_handle_irq+0x48/0x6c) [ 27.849695] [] (gic_handle_irq) from [] (__irq_svc+0x40/0x50) [ 27.886907] Exception stack(0xc0d01ee0 to 0xc0d01f28) Signed-off-by: Yunzhi Li --- drivers/usb/dwc2/gadget.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c index 6a30887..8070602 100644 --- a/drivers/usb/dwc2/gadget.c +++ b/drivers/usb/dwc2/gadget.c @@ -1389,14 +1389,14 @@ static void s3c_hsotg_complete_request(struct dwc2_hsotg *hsotg, if (hs_req->req.status == -EINPROGRESS) hs_req->req.status = result; + if (using_dma(hsotg)) + s3c_hsotg_unmap_dma(hsotg, hs_ep, hs_req); + s3c_hsotg_handle_unaligned_buf_complete(hsotg, hs_ep, hs_req); hs_ep->req = NULL; list_del_init(_req->queue); - if (using_dma(hsotg)) - s3c_hsotg_unmap_dma(hsotg, hs_ep, hs_req); - /* * call the complete request with the locks off, just in case the * request tries to queue more work for this endpoint. -- 2.0.0 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v1] usb: dwc2: gadget: fix a memory use-after-free bug
When s3c_hsotg_handle_unaligned_buf_complete() hs_req-req.buf already destroyed, in s3c_hsotg_unmap_dma(), it touches hs_req-req.dma again, so s3c_hsotg_unmap_dma() should be called before s3c_hsotg_handle_unaligned_buf_complete(). Otherwise, it will cause a bad_page BUG, when allocate this memory page next time. This bug led to the following crash: BUG: Bad page state in process swapper/0 pfn:2bdbc [ 26.820440] page:eed76780 count:0 mapcount:0 mapping: (null) index:0x0 [ 26.854710] page flags: 0x200(arch_1) [ 26.885836] page dumped because: PAGE_FLAGS_CHECK_AT_PREP flag set [ 26.919179] bad because of flags: [ 26.948917] page flags: 0x200(arch_1) [ 26.979100] Modules linked in: [ 27.008401] CPU: 0 PID: 0 Comm: swapper/0 Tainted: G W3.14.0 #17 [ 27.041816] [c010e1f8] (unwind_backtrace) from [c010a704] (show_stack+0x20/0x24) [ 27.076108] [c010a704] (show_stack) from [c087eea8] (dump_stack+0x70/0x8c) [ 27.110246] [c087eea8] (dump_stack) from [c01ce0b8] (bad_page+0xfc/0x12c) [ 27.143958] [c01ce0b8] (bad_page) from [c01ce65c] (get_page_from_freelist+0x3e4/0x50c) [ 27.179298] [c01ce65c] (get_page_from_freelist) from [c01ce9a0] (__alloc_pages_nodemask) [ 27.216296] [c01ce9a0] (__alloc_pages_nodemask) from [c01cf00c] (__get_free_pages+0x20/) [ 27.252326] [c01cf00c] (__get_free_pages) from [c01e5bec] (kmalloc_order_trace+0x34/0xa) [ 27.288295] [c01e5bec] (kmalloc_order_trace) from [c0203304] (__kmalloc+0x40/0x1ac) [ 27.323751] [c0203304] (__kmalloc) from [c052abc0] (s3c_hsotg_ep_queue.isra.12+0x7c/0x1) [ 27.359937] [c052abc0] (s3c_hsotg_ep_queue.isra.12) from [c052af88] (s3c_hsotg_ep_queue) [ 27.397478] [c052af88] (s3c_hsotg_ep_queue_lock) from [c0554110] (rx_submit+0xfc/0x164) [ 27.433619] [c0554110] (rx_submit) from [c05546e8] (rx_complete+0x22c/0x230) [ 27.468872] [c05546e8] (rx_complete) from [c052b528] (s3c_hsotg_complete_request+0xfc/0) [ 27.506240] [c052b528] (s3c_hsotg_complete_request) from [c052bba0] (s3c_hsotg_handle_o) [ 27.545401] [c052bba0] (s3c_hsotg_handle_outdone) from [c052be70] (s3c_hsotg_epint+0x2c) [ 27.583689] [c052be70] (s3c_hsotg_epint) from [c052c750] (s3c_hsotg_irq+0x1dc/0x4ac) [ 27.621041] [c052c750] (s3c_hsotg_irq) from [c01682e0] (handle_irq_event_percpu+0x70/0x) [ 27.659066] [c01682e0] (handle_irq_event_percpu) from [c01684ec] (handle_irq_event+0x4c) [ 27.697322] [c01684ec] (handle_irq_event) from [c016bae0] (handle_fasteoi_irq+0xc8/0x11) [ 27.735451] [c016bae0] (handle_fasteoi_irq) from [c0167b8c] (generic_handle_irq+0x30/0x) [ 27.773918] [c0167b8c] (generic_handle_irq) from [c0167ca4] (__handle_domain_irq+0x84/0) [ 27.812018] [c0167ca4] (__handle_domain_irq) from [c01003b0] (gic_handle_irq+0x48/0x6c) [ 27.849695] [c01003b0] (gic_handle_irq) from [c010b340] (__irq_svc+0x40/0x50) [ 27.886907] Exception stack(0xc0d01ee0 to 0xc0d01f28) Signed-off-by: Yunzhi Li l...@rock-chips.com --- drivers/usb/dwc2/gadget.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c index 6a30887..8070602 100644 --- a/drivers/usb/dwc2/gadget.c +++ b/drivers/usb/dwc2/gadget.c @@ -1389,14 +1389,14 @@ static void s3c_hsotg_complete_request(struct dwc2_hsotg *hsotg, if (hs_req-req.status == -EINPROGRESS) hs_req-req.status = result; + if (using_dma(hsotg)) + s3c_hsotg_unmap_dma(hsotg, hs_ep, hs_req); + s3c_hsotg_handle_unaligned_buf_complete(hsotg, hs_ep, hs_req); hs_ep-req = NULL; list_del_init(hs_req-queue); - if (using_dma(hsotg)) - s3c_hsotg_unmap_dma(hsotg, hs_ep, hs_req); - /* * call the complete request with the locks off, just in case the * request tries to queue more work for this endpoint. -- 2.0.0 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v1 1/2] ARM: dts: rockchip: add properties for dwc2 usb otg controller
Add properties for dwc2 usb device controller according to Documentation/devicetree/bindings/usb/dwc2.txt Signed-off-by: Yunzhi Li --- arch/arm/boot/dts/rk3288.dtsi | 6 ++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index eccc78d..2b55b07 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -432,6 +432,7 @@ interrupts = ; clocks = < HCLK_USBHOST1>; clock-names = "otg"; + dr_mode = "host"; status = "disabled"; }; @@ -442,6 +443,11 @@ interrupts = ; clocks = < HCLK_OTG0>; clock-names = "otg"; + dr_mode = "otg"; + g-np-tx-fifo-size = <16>; + g-rx-fifo-size = <275>; + g-tx-fifo-size = <256 128 128 64 64 32>; + g-use-dma; status = "disabled"; }; -- 2.0.0 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v1 2/2] ARM: dts: rockchip: set dr_mode property for rk3288-firefly board
rk3288-firefly board use the dwc2 usb otg controller as a host
controller and the device mode not used, so the dr_mode should be
"host" then the dwc2 usb otg controller will work at host only
mode
Signed-off-by: Yunzhi Li
---
arch/arm/boot/dts/rk3288-firefly.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/rk3288-firefly.dtsi
b/arch/arm/boot/dts/rk3288-firefly.dtsi
index e6f873a..a861776 100644
--- a/arch/arm/boot/dts/rk3288-firefly.dtsi
+++ b/arch/arm/boot/dts/rk3288-firefly.dtsi
@@ -466,6 +466,7 @@
};
_otg {
+ dr_modr = "host";
status = "okay";
};
--
2.0.0
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[PATCH] usb: dwc2: gadget: cleanup useless code
dwc2 gadget driver s3c_hsotg_of_probe() run twice in dwc2_gadget_init() and the first one is useless, so remove it. Signed-off-by: Yunzhi Li --- drivers/usb/dwc2/gadget.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c index 6a30887..2ae74f2 100644 --- a/drivers/usb/dwc2/gadget.c +++ b/drivers/usb/dwc2/gadget.c @@ -3851,8 +3851,6 @@ int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq) /* Set default UTMI width */ hsotg->phyif = GUSBCFG_PHYIF16; - s3c_hsotg_of_probe(hsotg); - /* Initialize to legacy fifo configuration values */ hsotg->g_rx_fifo_sz = 2048; hsotg->g_np_g_tx_fifo_sz = 1024; -- 2.0.0 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH] usb: dwc2: gadget: cleanup useless code
dwc2 gadget driver s3c_hsotg_of_probe() run twice in dwc2_gadget_init() and the first one is useless, so remove it. Signed-off-by: Yunzhi Li l...@rock-chips.com --- drivers/usb/dwc2/gadget.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c index 6a30887..2ae74f2 100644 --- a/drivers/usb/dwc2/gadget.c +++ b/drivers/usb/dwc2/gadget.c @@ -3851,8 +3851,6 @@ int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq) /* Set default UTMI width */ hsotg-phyif = GUSBCFG_PHYIF16; - s3c_hsotg_of_probe(hsotg); - /* Initialize to legacy fifo configuration values */ hsotg-g_rx_fifo_sz = 2048; hsotg-g_np_g_tx_fifo_sz = 1024; -- 2.0.0 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v1 2/2] ARM: dts: rockchip: set dr_mode property for rk3288-firefly board
rk3288-firefly board use the dwc2 usb otg controller as a host
controller and the device mode not used, so the dr_mode should be
host then the dwc2 usb otg controller will work at host only
mode
Signed-off-by: Yunzhi Li l...@rock-chips.com
---
arch/arm/boot/dts/rk3288-firefly.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/rk3288-firefly.dtsi
b/arch/arm/boot/dts/rk3288-firefly.dtsi
index e6f873a..a861776 100644
--- a/arch/arm/boot/dts/rk3288-firefly.dtsi
+++ b/arch/arm/boot/dts/rk3288-firefly.dtsi
@@ -466,6 +466,7 @@
};
usb_otg {
+ dr_modr = host;
status = okay;
};
--
2.0.0
--
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[PATCH v1 1/2] ARM: dts: rockchip: add properties for dwc2 usb otg controller
Add properties for dwc2 usb device controller according to Documentation/devicetree/bindings/usb/dwc2.txt Signed-off-by: Yunzhi Li l...@rock-chips.com --- arch/arm/boot/dts/rk3288.dtsi | 6 ++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index eccc78d..2b55b07 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -432,6 +432,7 @@ interrupts = GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH; clocks = cru HCLK_USBHOST1; clock-names = otg; + dr_mode = host; status = disabled; }; @@ -442,6 +443,11 @@ interrupts = GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH; clocks = cru HCLK_OTG0; clock-names = otg; + dr_mode = otg; + g-np-tx-fifo-size = 16; + g-rx-fifo-size = 275; + g-tx-fifo-size = 256 128 128 64 64 32; + g-use-dma; status = disabled; }; -- 2.0.0 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH RESEND] usb: dwc2: avoid leaking DMA channels on disconnection
Hi
When the HCD is disconnected, the DMA transfers still in-flight were cleaned-up
but the count of available DMA channels (e.g. available_host_channels) was not
reset.
The pool of DMA channels can be depleted when doing unclean
disconnection of USB peripherals, and reaches the point where no
transfer was possible until the next reboot/reload of the driver.
Tested by putting a programmable USB mux on the port and randomly
plugging/unpluging a USB HUB with USB mass-storage key, USB-audio and
USB-ethernet dongle connected to its downstream ports, and also doing the
disconnection early while the devices are still enumerating to get more URBs
in-flight.
After the patch, the devices are still enumerating after thousands of cycles,
while the port was totally dead before.
Signed-off-by: Vincent Palatin
---
I'm re-sending it, it seems the previous email did not show up.
drivers/usb/dwc2/hcd.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c
index c78c874..559b55e 100644
--- a/drivers/usb/dwc2/hcd.c
+++ b/drivers/usb/dwc2/hcd.c
@@ -257,6 +257,14 @@ static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg
*hsotg)
*/
channel->qh = NULL;
}
+ /* All channels have been freed, mark them available */
+ if (hsotg->core_params->uframe_sched > 0) {
+ hsotg->available_host_channels =
+ hsotg->core_params->host_channels;
+ } else {
+ hsotg->non_periodic_channels = 0;
+ hsotg->periodic_channels = 0;
+ }
}
/**
I have reviewed this patch. Obviously,it makes sense.
Reviewed-by: Yunzhi Li
--
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Re: [PATCH RESEND] usb: dwc2: avoid leaking DMA channels on disconnection
Hi
When the HCD is disconnected, the DMA transfers still in-flight were cleaned-up
but the count of available DMA channels (e.g. available_host_channels) was not
reset.
The pool of DMA channels can be depleted when doing unclean
disconnection of USB peripherals, and reaches the point where no
transfer was possible until the next reboot/reload of the driver.
Tested by putting a programmable USB mux on the port and randomly
plugging/unpluging a USB HUB with USB mass-storage key, USB-audio and
USB-ethernet dongle connected to its downstream ports, and also doing the
disconnection early while the devices are still enumerating to get more URBs
in-flight.
After the patch, the devices are still enumerating after thousands of cycles,
while the port was totally dead before.
Signed-off-by: Vincent Palatin vpala...@chromium.org
---
I'm re-sending it, it seems the previous email did not show up.
drivers/usb/dwc2/hcd.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c
index c78c874..559b55e 100644
--- a/drivers/usb/dwc2/hcd.c
+++ b/drivers/usb/dwc2/hcd.c
@@ -257,6 +257,14 @@ static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg
*hsotg)
*/
channel-qh = NULL;
}
+ /* All channels have been freed, mark them available */
+ if (hsotg-core_params-uframe_sched 0) {
+ hsotg-available_host_channels =
+ hsotg-core_params-host_channels;
+ } else {
+ hsotg-non_periodic_channels = 0;
+ hsotg-periodic_channels = 0;
+ }
}
/**
I have reviewed this patch. Obviously,it makes sense.
Reviewed-by: Yunzhi Li l...@rock-chips.com
--
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[RFC PATCH v1] usb: dwc2: reduce dwc2 driver probe time
I found that the probe function of dwc2 driver takes much time
when kernel boot up. There are many long delays in the probe
function these take almost 1 second.
This patch trying to reduce unnecessary delay time.
In dwc2_core_reset() I see it use two at least 20ms delays to
wait AHB idle and core soft reset, but dwc2 data book said that
dwc2 core soft reset and AHB idle just need a few clocks (I think
it refers to AHB clock, and AHB clock run at 150MHz in my RK3288
board), so 20ms is too long, delay 1us for wait AHB idle and soft
reset is enough.
And in dwc2_get_hwparams() it takes 150ms to wait ForceHostMode
and ForceDeviceMode vaild but in data book it said software must
wait at least 25ms before the change to take effect, so I reduce
this time to 25ms~50ms. By the way, is there any state bit show
that the force mode take effect ? Could we poll curmod bit for
figuring out if the change take effect ?
It seems that usleep_range() at boot time will pick the longest
value in the range. In dwc2_core_reset() there is a very long
delay takes 200ms, and this function run twice when probe, could
any one tell me is this delay time resonable ?
I have tried this patch in my RK3288-evb board. It works well.
Signed-off-by: Yunzhi Li
---
drivers/usb/dwc2/core.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/usb/dwc2/core.c b/drivers/usb/dwc2/core.c
index d5197d4..bdafb9d 100644
--- a/drivers/usb/dwc2/core.c
+++ b/drivers/usb/dwc2/core.c
@@ -124,7 +124,7 @@ static int dwc2_core_reset(struct dwc2_hsotg *hsotg)
/* Wait for AHB master IDLE state */
do {
- usleep_range(2, 4);
+ udelay(1);
greset = readl(hsotg->regs + GRSTCTL);
if (++count > 50) {
dev_warn(hsotg->dev,
@@ -139,7 +139,7 @@ static int dwc2_core_reset(struct dwc2_hsotg *hsotg)
greset |= GRSTCTL_CSFTRST;
writel(greset, hsotg->regs + GRSTCTL);
do {
- usleep_range(2, 4);
+ udelay(1);
greset = readl(hsotg->regs + GRSTCTL);
if (++count > 50) {
dev_warn(hsotg->dev,
@@ -170,7 +170,7 @@ static int dwc2_core_reset(struct dwc2_hsotg *hsotg)
* NOTE: This long sleep is _very_ important, otherwise the core will
* not stay in host mode after a connector ID change!
*/
- usleep_range(15, 20);
+ usleep_range(15, 16);
return 0;
}
@@ -2694,7 +2694,7 @@ int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
gusbcfg = readl(hsotg->regs + GUSBCFG);
gusbcfg |= GUSBCFG_FORCEHOSTMODE;
writel(gusbcfg, hsotg->regs + GUSBCFG);
- usleep_range(10, 15);
+ usleep_range(25000, 5);
gnptxfsiz = readl(hsotg->regs + GNPTXFSIZ);
hptxfsiz = readl(hsotg->regs + HPTXFSIZ);
@@ -2703,7 +2703,7 @@ int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
gusbcfg = readl(hsotg->regs + GUSBCFG);
gusbcfg &= ~GUSBCFG_FORCEHOSTMODE;
writel(gusbcfg, hsotg->regs + GUSBCFG);
- usleep_range(10, 15);
+ usleep_range(25000, 5);
/* hwcfg2 */
hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >>
--
2.0.0
--
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[RFC PATCH v1] usb: dwc2: reduce dwc2 driver probe time
I found that the probe function of dwc2 driver takes much time
when kernel boot up. There are many long delays in the probe
function these take almost 1 second.
This patch trying to reduce unnecessary delay time.
In dwc2_core_reset() I see it use two at least 20ms delays to
wait AHB idle and core soft reset, but dwc2 data book said that
dwc2 core soft reset and AHB idle just need a few clocks (I think
it refers to AHB clock, and AHB clock run at 150MHz in my RK3288
board), so 20ms is too long, delay 1us for wait AHB idle and soft
reset is enough.
And in dwc2_get_hwparams() it takes 150ms to wait ForceHostMode
and ForceDeviceMode vaild but in data book it said software must
wait at least 25ms before the change to take effect, so I reduce
this time to 25ms~50ms. By the way, is there any state bit show
that the force mode take effect ? Could we poll curmod bit for
figuring out if the change take effect ?
It seems that usleep_range() at boot time will pick the longest
value in the range. In dwc2_core_reset() there is a very long
delay takes 200ms, and this function run twice when probe, could
any one tell me is this delay time resonable ?
I have tried this patch in my RK3288-evb board. It works well.
Signed-off-by: Yunzhi Li l...@rock-chips.com
---
drivers/usb/dwc2/core.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/usb/dwc2/core.c b/drivers/usb/dwc2/core.c
index d5197d4..bdafb9d 100644
--- a/drivers/usb/dwc2/core.c
+++ b/drivers/usb/dwc2/core.c
@@ -124,7 +124,7 @@ static int dwc2_core_reset(struct dwc2_hsotg *hsotg)
/* Wait for AHB master IDLE state */
do {
- usleep_range(2, 4);
+ udelay(1);
greset = readl(hsotg-regs + GRSTCTL);
if (++count 50) {
dev_warn(hsotg-dev,
@@ -139,7 +139,7 @@ static int dwc2_core_reset(struct dwc2_hsotg *hsotg)
greset |= GRSTCTL_CSFTRST;
writel(greset, hsotg-regs + GRSTCTL);
do {
- usleep_range(2, 4);
+ udelay(1);
greset = readl(hsotg-regs + GRSTCTL);
if (++count 50) {
dev_warn(hsotg-dev,
@@ -170,7 +170,7 @@ static int dwc2_core_reset(struct dwc2_hsotg *hsotg)
* NOTE: This long sleep is _very_ important, otherwise the core will
* not stay in host mode after a connector ID change!
*/
- usleep_range(15, 20);
+ usleep_range(15, 16);
return 0;
}
@@ -2694,7 +2694,7 @@ int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
gusbcfg = readl(hsotg-regs + GUSBCFG);
gusbcfg |= GUSBCFG_FORCEHOSTMODE;
writel(gusbcfg, hsotg-regs + GUSBCFG);
- usleep_range(10, 15);
+ usleep_range(25000, 5);
gnptxfsiz = readl(hsotg-regs + GNPTXFSIZ);
hptxfsiz = readl(hsotg-regs + HPTXFSIZ);
@@ -2703,7 +2703,7 @@ int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
gusbcfg = readl(hsotg-regs + GUSBCFG);
gusbcfg = ~GUSBCFG_FORCEHOSTMODE;
writel(gusbcfg, hsotg-regs + GUSBCFG);
- usleep_range(10, 15);
+ usleep_range(25000, 5);
/* hwcfg2 */
hw-op_mode = (hwcfg2 GHWCFG2_OP_MODE_MASK)
--
2.0.0
--
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Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v7 2/5] phy: add a driver for the Rockchip SoC internal USB2.0 PHY
Hi Kishon :
Hi,
On Wednesday 21 January 2015 03:36 PM, Yunzhi Li wrote:
Hi Kishon :
Hi,
On Friday 12 December 2014 08:37 PM, Yunzhi Li wrote:
This patch to add a generic PHY driver for ROCKCHIP usb PHYs,
currently this driver can support RK3288. The RK3288 SoC have
three independent USB PHY IPs which are all configured through a
set of registers located in the GRF (general register files)
module.
Signed-off-by: Yunzhi Li
---
Changes in v7:
- Accept Kishon's comments to use phandle args to find a phy
struct directly and get rid of using a custom of_xlate
function.
Changes in v6:
- Rename SIDDQ_MSK to SIDDQ_WRITE_ENA.
Changes in v5: None
Changes in v4:
- Get number of PHYs from device tree.
- Model each PHY as subnode of the phy provider node.
Changes in v3:
- Use BIT macro instead of bit shift ops.
- Rename the config entry to PHY_ROCKCHIP_USB.
drivers/phy/Kconfig| 7 ++
drivers/phy/Makefile | 1 +
drivers/phy/phy-rockchip-usb.c | 158
+
3 files changed, 166 insertions(+)
create mode 100644 drivers/phy/phy-rockchip-usb.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index ccad880..b24500a 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -239,6 +239,13 @@ config PHY_QCOM_IPQ806X_SATA
depends on OF
select GENERIC_PHY
+config PHY_ROCKCHIP_USB
+tristate "Rockchip USB2 PHY Driver"
+depends on ARCH_ROCKCHIP && OF
+select GENERIC_PHY
+help
+ Enable this to support the Rockchip USB 2.0 PHY.
+
config PHY_ST_SPEAR1310_MIPHY
tristate "ST SPEAR1310-MIPHY driver"
select GENERIC_PHY
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index aa74f96..48bf5a1 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -28,6 +28,7 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2)+=
phy-exynos5250-usb2.o
phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2)+= phy-s5pv210-usb2.o
obj-$(CONFIG_PHY_EXYNOS5_USBDRD)+= phy-exynos5-usbdrd.o
obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)+= phy-qcom-apq8064-sata.o
+obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)+= phy-qcom-ipq806x-sata.o
obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY)+= phy-spear1310-miphy.o
obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY)+= phy-spear1340-miphy.o
diff --git a/drivers/phy/phy-rockchip-usb.c b/drivers/phy/phy-rockchip-usb.c
new file mode 100644
index 000..22011c3
--- /dev/null
+++ b/drivers/phy/phy-rockchip-usb.c
@@ -0,0 +1,158 @@
+/*
+ * Rockchip usb PHY driver
+ *
+ * Copyright (C) 2014 Yunzhi Li
+ * Copyright (C) 2014 ROCKCHIP, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/*
+ * The higher 16-bit of this register is used for write protection
+ * only if BIT(13 + 16) set to 1 the BIT(13) can be written.
+ */
+#define SIDDQ_WRITE_ENABIT(29)
+#define SIDDQ_ONBIT(13)
+#define SIDDQ_OFF(0 << 13)
+
+struct rockchip_usb_phy {
+unsigned intreg_offset;
+struct regmap*reg_base;
+struct clk*clk;
+struct phy*phy;
+};
+
+static int rockchip_usb_phy_power(struct rockchip_usb_phy *phy,
+ bool siddq)
+{
+return regmap_write(phy->reg_base, phy->reg_offset,
+SIDDQ_WRITE_ENA | (siddq ? SIDDQ_ON : SIDDQ_OFF));
+}
+
+static int rockchip_usb_phy_power_off(struct phy *_phy)
+{
+struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
+int ret = 0;
+
+/* Power down usb phy analog blocks by set siddq 1 */
+ret = rockchip_usb_phy_power(phy, 1);
+if (ret)
+return ret;
+
+clk_disable_unprepare(phy->clk);
+if (ret)
+return ret;
+
+return 0;
+}
+
+static int rockchip_usb_phy_power_on(struct phy *_phy)
+{
+struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
+int ret = 0;
+
+ret = clk_prepare_enable(phy->clk);
+if (ret)
+return ret;
+
+/* Power up usb phy analog blocks by set siddq 0 */
+ret = rockchip_usb_phy_power(phy, 0);
+if (ret)
+return ret;
+
+return 0;
+}
+
+static struct phy_ops ops = {
+.power_on= rockchip_usb_phy_power_on,
+.power_off= rockchip_usb_phy_power_off,
+.owner= THIS_MODULE,
+};
+
+static int rockchip_usb_phy_probe(struct platform_device *pdev)
+{
+struct device *dev = >dev;
+struct r
Re: [PATCH v7 2/5] phy: add a driver for the Rockchip SoC internal USB2.0 PHY
Hi Kishon :
Hi,
On Friday 12 December 2014 08:37 PM, Yunzhi Li wrote:
This patch to add a generic PHY driver for ROCKCHIP usb PHYs,
currently this driver can support RK3288. The RK3288 SoC have
three independent USB PHY IPs which are all configured through a
set of registers located in the GRF (general register files)
module.
Signed-off-by: Yunzhi Li
---
Changes in v7:
- Accept Kishon's comments to use phandle args to find a phy
struct directly and get rid of using a custom of_xlate
function.
Changes in v6:
- Rename SIDDQ_MSK to SIDDQ_WRITE_ENA.
Changes in v5: None
Changes in v4:
- Get number of PHYs from device tree.
- Model each PHY as subnode of the phy provider node.
Changes in v3:
- Use BIT macro instead of bit shift ops.
- Rename the config entry to PHY_ROCKCHIP_USB.
drivers/phy/Kconfig| 7 ++
drivers/phy/Makefile | 1 +
drivers/phy/phy-rockchip-usb.c | 158 +
3 files changed, 166 insertions(+)
create mode 100644 drivers/phy/phy-rockchip-usb.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index ccad880..b24500a 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -239,6 +239,13 @@ config PHY_QCOM_IPQ806X_SATA
depends on OF
select GENERIC_PHY
+config PHY_ROCKCHIP_USB
+ tristate "Rockchip USB2 PHY Driver"
+ depends on ARCH_ROCKCHIP && OF
+ select GENERIC_PHY
+ help
+ Enable this to support the Rockchip USB 2.0 PHY.
+
config PHY_ST_SPEAR1310_MIPHY
tristate "ST SPEAR1310-MIPHY driver"
select GENERIC_PHY
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index aa74f96..48bf5a1 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -28,6 +28,7 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2) +=
phy-exynos5250-usb2.o
phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2)+= phy-s5pv210-usb2.o
obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o
obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o
+obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o
obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY) += phy-spear1310-miphy.o
obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) += phy-spear1340-miphy.o
diff --git a/drivers/phy/phy-rockchip-usb.c b/drivers/phy/phy-rockchip-usb.c
new file mode 100644
index 000..22011c3
--- /dev/null
+++ b/drivers/phy/phy-rockchip-usb.c
@@ -0,0 +1,158 @@
+/*
+ * Rockchip usb PHY driver
+ *
+ * Copyright (C) 2014 Yunzhi Li
+ * Copyright (C) 2014 ROCKCHIP, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/*
+ * The higher 16-bit of this register is used for write protection
+ * only if BIT(13 + 16) set to 1 the BIT(13) can be written.
+ */
+#define SIDDQ_WRITE_ENABIT(29)
+#define SIDDQ_ON BIT(13)
+#define SIDDQ_OFF (0 << 13)
+
+struct rockchip_usb_phy {
+ unsigned intreg_offset;
+ struct regmap *reg_base;
+ struct clk *clk;
+ struct phy *phy;
+};
+
+static int rockchip_usb_phy_power(struct rockchip_usb_phy *phy,
+ bool siddq)
+{
+ return regmap_write(phy->reg_base, phy->reg_offset,
+ SIDDQ_WRITE_ENA | (siddq ? SIDDQ_ON : SIDDQ_OFF));
+}
+
+static int rockchip_usb_phy_power_off(struct phy *_phy)
+{
+ struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
+ int ret = 0;
+
+ /* Power down usb phy analog blocks by set siddq 1 */
+ ret = rockchip_usb_phy_power(phy, 1);
+ if (ret)
+ return ret;
+
+ clk_disable_unprepare(phy->clk);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int rockchip_usb_phy_power_on(struct phy *_phy)
+{
+ struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
+ int ret = 0;
+
+ ret = clk_prepare_enable(phy->clk);
+ if (ret)
+ return ret;
+
+ /* Power up usb phy analog blocks by set siddq 0 */
+ ret = rockchip_usb_phy_power(phy, 0);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static struct phy_ops ops = {
+ .power_on = rockchip_usb_phy_power_on,
+ .power_off = rockchip_usb_phy_power_off,
+ .owner = THIS_MODULE,
+};
+
+static int rockchip_usb_phy_probe(s
Re: [PATCH v7 2/5] phy: add a driver for the Rockchip SoC internal USB2.0 PHY
Hi Kishon :
Hi,
On Wednesday 21 January 2015 03:36 PM, Yunzhi Li wrote:
Hi Kishon :
Hi,
On Friday 12 December 2014 08:37 PM, Yunzhi Li wrote:
This patch to add a generic PHY driver for ROCKCHIP usb PHYs,
currently this driver can support RK3288. The RK3288 SoC have
three independent USB PHY IPs which are all configured through a
set of registers located in the GRF (general register files)
module.
Signed-off-by: Yunzhi Li l...@rock-chips.com
---
Changes in v7:
- Accept Kishon's comments to use phandle args to find a phy
struct directly and get rid of using a custom of_xlate
function.
Changes in v6:
- Rename SIDDQ_MSK to SIDDQ_WRITE_ENA.
Changes in v5: None
Changes in v4:
- Get number of PHYs from device tree.
- Model each PHY as subnode of the phy provider node.
Changes in v3:
- Use BIT macro instead of bit shift ops.
- Rename the config entry to PHY_ROCKCHIP_USB.
drivers/phy/Kconfig| 7 ++
drivers/phy/Makefile | 1 +
drivers/phy/phy-rockchip-usb.c | 158
+
3 files changed, 166 insertions(+)
create mode 100644 drivers/phy/phy-rockchip-usb.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index ccad880..b24500a 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -239,6 +239,13 @@ config PHY_QCOM_IPQ806X_SATA
depends on OF
select GENERIC_PHY
+config PHY_ROCKCHIP_USB
+tristate Rockchip USB2 PHY Driver
+depends on ARCH_ROCKCHIP OF
+select GENERIC_PHY
+help
+ Enable this to support the Rockchip USB 2.0 PHY.
+
config PHY_ST_SPEAR1310_MIPHY
tristate ST SPEAR1310-MIPHY driver
select GENERIC_PHY
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index aa74f96..48bf5a1 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -28,6 +28,7 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2)+=
phy-exynos5250-usb2.o
phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2)+= phy-s5pv210-usb2.o
obj-$(CONFIG_PHY_EXYNOS5_USBDRD)+= phy-exynos5-usbdrd.o
obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)+= phy-qcom-apq8064-sata.o
+obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)+= phy-qcom-ipq806x-sata.o
obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY)+= phy-spear1310-miphy.o
obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY)+= phy-spear1340-miphy.o
diff --git a/drivers/phy/phy-rockchip-usb.c b/drivers/phy/phy-rockchip-usb.c
new file mode 100644
index 000..22011c3
--- /dev/null
+++ b/drivers/phy/phy-rockchip-usb.c
@@ -0,0 +1,158 @@
+/*
+ * Rockchip usb PHY driver
+ *
+ * Copyright (C) 2014 Yunzhi Li l...@rock-chips.com
+ * Copyright (C) 2014 ROCKCHIP, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/clk.h
+#include linux/io.h
+#include linux/kernel.h
+#include linux/module.h
+#include linux/mutex.h
+#include linux/of.h
+#include linux/of_address.h
+#include linux/phy/phy.h
+#include linux/platform_device.h
+#include linux/regulator/consumer.h
+#include linux/reset.h
+#include linux/regmap.h
+#include linux/mfd/syscon.h
+
+/*
+ * The higher 16-bit of this register is used for write protection
+ * only if BIT(13 + 16) set to 1 the BIT(13) can be written.
+ */
+#define SIDDQ_WRITE_ENABIT(29)
+#define SIDDQ_ONBIT(13)
+#define SIDDQ_OFF(0 13)
+
+struct rockchip_usb_phy {
+unsigned intreg_offset;
+struct regmap*reg_base;
+struct clk*clk;
+struct phy*phy;
+};
+
+static int rockchip_usb_phy_power(struct rockchip_usb_phy *phy,
+ bool siddq)
+{
+return regmap_write(phy-reg_base, phy-reg_offset,
+SIDDQ_WRITE_ENA | (siddq ? SIDDQ_ON : SIDDQ_OFF));
+}
+
+static int rockchip_usb_phy_power_off(struct phy *_phy)
+{
+struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
+int ret = 0;
+
+/* Power down usb phy analog blocks by set siddq 1 */
+ret = rockchip_usb_phy_power(phy, 1);
+if (ret)
+return ret;
+
+clk_disable_unprepare(phy-clk);
+if (ret)
+return ret;
+
+return 0;
+}
+
+static int rockchip_usb_phy_power_on(struct phy *_phy)
+{
+struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
+int ret = 0;
+
+ret = clk_prepare_enable(phy-clk);
+if (ret)
+return ret;
+
+/* Power up usb phy analog blocks by set siddq 0 */
+ret = rockchip_usb_phy_power(phy, 0);
+if (ret)
+return ret;
+
+return 0;
+}
+
+static struct phy_ops ops = {
+.power_on= rockchip_usb_phy_power_on,
+.power_off
Re: [PATCH v7 2/5] phy: add a driver for the Rockchip SoC internal USB2.0 PHY
Hi Kishon :
Hi,
On Friday 12 December 2014 08:37 PM, Yunzhi Li wrote:
This patch to add a generic PHY driver for ROCKCHIP usb PHYs,
currently this driver can support RK3288. The RK3288 SoC have
three independent USB PHY IPs which are all configured through a
set of registers located in the GRF (general register files)
module.
Signed-off-by: Yunzhi Li l...@rock-chips.com
---
Changes in v7:
- Accept Kishon's comments to use phandle args to find a phy
struct directly and get rid of using a custom of_xlate
function.
Changes in v6:
- Rename SIDDQ_MSK to SIDDQ_WRITE_ENA.
Changes in v5: None
Changes in v4:
- Get number of PHYs from device tree.
- Model each PHY as subnode of the phy provider node.
Changes in v3:
- Use BIT macro instead of bit shift ops.
- Rename the config entry to PHY_ROCKCHIP_USB.
drivers/phy/Kconfig| 7 ++
drivers/phy/Makefile | 1 +
drivers/phy/phy-rockchip-usb.c | 158 +
3 files changed, 166 insertions(+)
create mode 100644 drivers/phy/phy-rockchip-usb.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index ccad880..b24500a 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -239,6 +239,13 @@ config PHY_QCOM_IPQ806X_SATA
depends on OF
select GENERIC_PHY
+config PHY_ROCKCHIP_USB
+ tristate Rockchip USB2 PHY Driver
+ depends on ARCH_ROCKCHIP OF
+ select GENERIC_PHY
+ help
+ Enable this to support the Rockchip USB 2.0 PHY.
+
config PHY_ST_SPEAR1310_MIPHY
tristate ST SPEAR1310-MIPHY driver
select GENERIC_PHY
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index aa74f96..48bf5a1 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -28,6 +28,7 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2) +=
phy-exynos5250-usb2.o
phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2)+= phy-s5pv210-usb2.o
obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o
obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o
+obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o
obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY) += phy-spear1310-miphy.o
obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) += phy-spear1340-miphy.o
diff --git a/drivers/phy/phy-rockchip-usb.c b/drivers/phy/phy-rockchip-usb.c
new file mode 100644
index 000..22011c3
--- /dev/null
+++ b/drivers/phy/phy-rockchip-usb.c
@@ -0,0 +1,158 @@
+/*
+ * Rockchip usb PHY driver
+ *
+ * Copyright (C) 2014 Yunzhi Li l...@rock-chips.com
+ * Copyright (C) 2014 ROCKCHIP, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/clk.h
+#include linux/io.h
+#include linux/kernel.h
+#include linux/module.h
+#include linux/mutex.h
+#include linux/of.h
+#include linux/of_address.h
+#include linux/phy/phy.h
+#include linux/platform_device.h
+#include linux/regulator/consumer.h
+#include linux/reset.h
+#include linux/regmap.h
+#include linux/mfd/syscon.h
+
+/*
+ * The higher 16-bit of this register is used for write protection
+ * only if BIT(13 + 16) set to 1 the BIT(13) can be written.
+ */
+#define SIDDQ_WRITE_ENABIT(29)
+#define SIDDQ_ON BIT(13)
+#define SIDDQ_OFF (0 13)
+
+struct rockchip_usb_phy {
+ unsigned intreg_offset;
+ struct regmap *reg_base;
+ struct clk *clk;
+ struct phy *phy;
+};
+
+static int rockchip_usb_phy_power(struct rockchip_usb_phy *phy,
+ bool siddq)
+{
+ return regmap_write(phy-reg_base, phy-reg_offset,
+ SIDDQ_WRITE_ENA | (siddq ? SIDDQ_ON : SIDDQ_OFF));
+}
+
+static int rockchip_usb_phy_power_off(struct phy *_phy)
+{
+ struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
+ int ret = 0;
+
+ /* Power down usb phy analog blocks by set siddq 1 */
+ ret = rockchip_usb_phy_power(phy, 1);
+ if (ret)
+ return ret;
+
+ clk_disable_unprepare(phy-clk);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int rockchip_usb_phy_power_on(struct phy *_phy)
+{
+ struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
+ int ret = 0;
+
+ ret = clk_prepare_enable(phy-clk);
+ if (ret)
+ return ret;
+
+ /* Power up usb phy analog blocks by set siddq 0 */
+ ret = rockchip_usb_phy_power(phy, 0);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static struct phy_ops ops
Re: [PATCH v7 3/5] usb: dwc2: add generic PHY framework support for dwc2 usb controler platform driver.
Hi paul:
在 2015/1/9 10:15, Paul Zimmerman 写道:
[...]
/*
-* Attempt to find a generic PHY, then look for an old style
-* USB PHY, finally fall back to pdata
+* If platform probe couldn't find a generic PHY or an old style
+* USB PHY, fall back to pdata
*/
- phy = devm_phy_get(dev, "usb2-phy");
- if (IS_ERR(phy)) {
- uphy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
- if (IS_ERR(uphy)) {
- /* Fallback for pdata */
- plat = dev_get_platdata(dev);
- if (!plat) {
- dev_err(dev,
- "no platform data or transceiver defined\n");
- return -EPROBE_DEFER;
- }
- hsotg->plat = plat;
- } else
- hsotg->uphy = uphy;
- } else {
- hsotg->phy = phy;
+ if (IS_ERR_OR_NULL(hsotg->phy) && IS_ERR_OR_NULL(hsotg->uphy)) {
+ plat = dev_get_platdata(dev);
+ if (!plat) {
+ dev_err(dev,
+ "no platform data or transceiver defined\n");
+ return -EPROBE_DEFER;
Hi Yunzhi,
Testing Felipe's testing/next branch on an Altera SOCFPGA platform,
the driver never loads because it always returns -EPROBE_DEFER here.
Apparently the SOCFPGA platform does not have any platform data
defined, because dev_get_platdata() always returns NULL.
If I remove the -EPROBE_DEFER return and have it continue on, the
driver works. Reverting the patch also makes it work.
When I debug this problem, I checked socfpga.dtsi, there is a
usbphy node defined for each
dwc2 controller, so I think when running dwc2_driver_probe() uphy =
devm_usb_get_phy()
should get a valid usbphy pointer and hsotg->uphy will not be NULL or
ERROR, then in dwc2_gadget_init()
it will not return -EPROBE_DEFER. I have no idea about why you meet
-EPROBE_DEFER, could you please tell
me what's the return value of devm_usb_get_phy() on your socfpga board ?
I am testing with the driver built-in. I haven't tried it as a module
yet.
Any ideas? Is the -EPROBE_DEFER return really needed here?
--
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Re: [PATCH v7 3/5] usb: dwc2: add generic PHY framework support for dwc2 usb controler platform driver.
Hi Paul:
On 2015/1/9 10:15, Paul Zimmerman wrote:
/*
-* Attempt to find a generic PHY, then look for an old style
-* USB PHY, finally fall back to pdata
+* If platform probe couldn't find a generic PHY or an old style
+* USB PHY, fall back to pdata
*/
- phy = devm_phy_get(dev, "usb2-phy");
- if (IS_ERR(phy)) {
- uphy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
- if (IS_ERR(uphy)) {
- /* Fallback for pdata */
- plat = dev_get_platdata(dev);
- if (!plat) {
- dev_err(dev,
- "no platform data or transceiver defined\n");
- return -EPROBE_DEFER;
- }
- hsotg->plat = plat;
- } else
- hsotg->uphy = uphy;
- } else {
- hsotg->phy = phy;
+ if (IS_ERR_OR_NULL(hsotg->phy) && IS_ERR_OR_NULL(hsotg->uphy)) {
+ plat = dev_get_platdata(dev);
+ if (!plat) {
+ dev_err(dev,
+ "no platform data or transceiver defined\n");
+ return -EPROBE_DEFER;
Hi Yunzhi,
Testing Felipe's testing/next branch on an Altera SOCFPGA platform,
the driver never loads because it always returns -EPROBE_DEFER here.
Apparently the SOCFPGA platform does not have any platform data
defined, because dev_get_platdata() always returns NULL.
If I remove the -EPROBE_DEFER return and have it continue on, the
driver works. Reverting the patch also makes it work.
I am testing with the driver built-in. I haven't tried it as a module
yet.
Any ideas? Is the -EPROBE_DEFER return really needed here?
Yeah, I agree -EPROBE_DEFER is no need here, because the phy driver
is optional, it shouldn't
break the usb controller driver probe procedure. I will fix it then
resend this patch. Thank you
for testing .
--
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the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v7 3/5] usb: dwc2: add generic PHY framework support for dwc2 usb controler platform driver.
Hi paul:
在 2015/1/9 10:15, Paul Zimmerman 写道:
[...]
/*
-* Attempt to find a generic PHY, then look for an old style
-* USB PHY, finally fall back to pdata
+* If platform probe couldn't find a generic PHY or an old style
+* USB PHY, fall back to pdata
*/
- phy = devm_phy_get(dev, usb2-phy);
- if (IS_ERR(phy)) {
- uphy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
- if (IS_ERR(uphy)) {
- /* Fallback for pdata */
- plat = dev_get_platdata(dev);
- if (!plat) {
- dev_err(dev,
- no platform data or transceiver defined\n);
- return -EPROBE_DEFER;
- }
- hsotg-plat = plat;
- } else
- hsotg-uphy = uphy;
- } else {
- hsotg-phy = phy;
+ if (IS_ERR_OR_NULL(hsotg-phy) IS_ERR_OR_NULL(hsotg-uphy)) {
+ plat = dev_get_platdata(dev);
+ if (!plat) {
+ dev_err(dev,
+ no platform data or transceiver defined\n);
+ return -EPROBE_DEFER;
Hi Yunzhi,
Testing Felipe's testing/next branch on an Altera SOCFPGA platform,
the driver never loads because it always returns -EPROBE_DEFER here.
Apparently the SOCFPGA platform does not have any platform data
defined, because dev_get_platdata() always returns NULL.
If I remove the -EPROBE_DEFER return and have it continue on, the
driver works. Reverting the patch also makes it work.
When I debug this problem, I checked socfpga.dtsi, there is a
usbphy node defined for each
dwc2 controller, so I think when running dwc2_driver_probe() uphy =
devm_usb_get_phy()
should get a valid usbphy pointer and hsotg-uphy will not be NULL or
ERROR, then in dwc2_gadget_init()
it will not return -EPROBE_DEFER. I have no idea about why you meet
-EPROBE_DEFER, could you please tell
me what's the return value of devm_usb_get_phy() on your socfpga board ?
I am testing with the driver built-in. I haven't tried it as a module
yet.
Any ideas? Is the -EPROBE_DEFER return really needed here?
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v7 3/5] usb: dwc2: add generic PHY framework support for dwc2 usb controler platform driver.
Hi Paul:
On 2015/1/9 10:15, Paul Zimmerman wrote:
/*
-* Attempt to find a generic PHY, then look for an old style
-* USB PHY, finally fall back to pdata
+* If platform probe couldn't find a generic PHY or an old style
+* USB PHY, fall back to pdata
*/
- phy = devm_phy_get(dev, usb2-phy);
- if (IS_ERR(phy)) {
- uphy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
- if (IS_ERR(uphy)) {
- /* Fallback for pdata */
- plat = dev_get_platdata(dev);
- if (!plat) {
- dev_err(dev,
- no platform data or transceiver defined\n);
- return -EPROBE_DEFER;
- }
- hsotg-plat = plat;
- } else
- hsotg-uphy = uphy;
- } else {
- hsotg-phy = phy;
+ if (IS_ERR_OR_NULL(hsotg-phy) IS_ERR_OR_NULL(hsotg-uphy)) {
+ plat = dev_get_platdata(dev);
+ if (!plat) {
+ dev_err(dev,
+ no platform data or transceiver defined\n);
+ return -EPROBE_DEFER;
Hi Yunzhi,
Testing Felipe's testing/next branch on an Altera SOCFPGA platform,
the driver never loads because it always returns -EPROBE_DEFER here.
Apparently the SOCFPGA platform does not have any platform data
defined, because dev_get_platdata() always returns NULL.
If I remove the -EPROBE_DEFER return and have it continue on, the
driver works. Reverting the patch also makes it work.
I am testing with the driver built-in. I haven't tried it as a module
yet.
Any ideas? Is the -EPROBE_DEFER return really needed here?
Yeah, I agree -EPROBE_DEFER is no need here, because the phy driver
is optional, it shouldn't
break the usb controller driver probe procedure. I will fix it then
resend this patch. Thank you
for testing .
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[PATCH v7 5/5] ARM: dts: rockchip: Enable usb PHY on rk3288-evb board
Enable usb PHY for all usb ports on rk3288-evb.
Signed-off-by: Yunzhi Li
---
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
arch/arm/boot/dts/rk3288-evb.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi
b/arch/arm/boot/dts/rk3288-evb.dtsi
index cb83cea..992f323 100644
--- a/arch/arm/boot/dts/rk3288-evb.dtsi
+++ b/arch/arm/boot/dts/rk3288-evb.dtsi
@@ -174,6 +174,10 @@
};
};
+ {
+ status = "okay";
+};
+
_host0_ehci {
status = "okay";
};
--
2.0.0
--
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[PATCH v7 4/5] ARM: dts: rockchip: add rk3288 usb PHY
This patch adds a device_node for RK3288 SoC usb phy. It also
defines the phy to be used by three usb controllers: usb_host0/1
and usb_otg.
Signed-off-by: Yunzhi Li
---
Changes in v7:
- Update dtsi for new usb phy driver.
Changes in v6: None
Changes in v5:
- reorder the phy dt node to a correct position.
Changes in v4:
- Add phy subnodes.
Changes in v3: None
arch/arm/boot/dts/rk3288.dtsi | 35 +++
1 file changed, 35 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 874e66d..2a9a029 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -335,6 +335,8 @@
interrupts = ;
clocks = < HCLK_USBHOST0>;
clock-names = "usbhost";
+ phys = <>;
+ phy-names = "usb";
status = "disabled";
};
@@ -347,6 +349,8 @@
interrupts = ;
clocks = < HCLK_USBHOST1>;
clock-names = "otg";
+ phys = <>;
+ phy-names = "usb2-phy";
status = "disabled";
};
@@ -357,6 +361,8 @@
interrupts = ;
clocks = < HCLK_OTG0>;
clock-names = "otg";
+ phys = <>;
+ phy-names = "usb2-phy";
status = "disabled";
};
@@ -497,6 +503,35 @@
interrupts = ;
};
+ usbphy: phy {
+ compatible = "rockchip,rk3288-usb-phy";
+ rockchip,grf = <>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ usbphy0: usb-phy0 {
+ #phy-cells = <0>;
+ reg = <0x320>;
+ clocks = < SCLK_OTGPHY0>;
+ clock-names = "phyclk";
+ };
+
+ usbphy1: usb-phy1 {
+ #phy-cells = <0>;
+ reg = <0x334>;
+ clocks = < SCLK_OTGPHY1>;
+ clock-names = "phyclk";
+ };
+
+ usbphy2: usb-phy2 {
+ #phy-cells = <0>;
+ reg = <0x348>;
+ clocks = < SCLK_OTGPHY2>;
+ clock-names = "phyclk";
+ };
+ };
+
pinctrl: pinctrl {
compatible = "rockchip,rk3288-pinctrl";
rockchip,grf = <>;
--
2.0.0
--
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[PATCH v7 3/5] usb: dwc2: add generic PHY framework support for dwc2 usb controler platform driver.
Get PHY parameters from devicetree and power off usb PHY during
system suspend.
Signed-off-by: Yunzhi Li
Acked-by: Paul Zimmerman
---
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3:
- Fix coding style: both branches of the if() which only one
branch of the conditional statement is a single statement
should have braces.
- No need to test dwc2->phy for NULL before calling generic phy
APIs.
drivers/usb/dwc2/gadget.c | 33 -
drivers/usb/dwc2/platform.c | 36 ++--
2 files changed, 46 insertions(+), 23 deletions(-)
diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c
index 200168e..2601c61 100644
--- a/drivers/usb/dwc2/gadget.c
+++ b/drivers/usb/dwc2/gadget.c
@@ -3410,8 +3410,6 @@ int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq)
{
struct device *dev = hsotg->dev;
struct s3c_hsotg_plat *plat = dev->platform_data;
- struct phy *phy;
- struct usb_phy *uphy;
struct s3c_hsotg_ep *eps;
int epnum;
int ret;
@@ -3421,30 +3419,23 @@ int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq)
hsotg->phyif = GUSBCFG_PHYIF16;
/*
-* Attempt to find a generic PHY, then look for an old style
-* USB PHY, finally fall back to pdata
+* If platform probe couldn't find a generic PHY or an old style
+* USB PHY, fall back to pdata
*/
- phy = devm_phy_get(dev, "usb2-phy");
- if (IS_ERR(phy)) {
- uphy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
- if (IS_ERR(uphy)) {
- /* Fallback for pdata */
- plat = dev_get_platdata(dev);
- if (!plat) {
- dev_err(dev,
- "no platform data or transceiver defined\n");
- return -EPROBE_DEFER;
- }
- hsotg->plat = plat;
- } else
- hsotg->uphy = uphy;
- } else {
- hsotg->phy = phy;
+ if (IS_ERR_OR_NULL(hsotg->phy) && IS_ERR_OR_NULL(hsotg->uphy)) {
+ plat = dev_get_platdata(dev);
+ if (!plat) {
+ dev_err(dev,
+ "no platform data or transceiver defined\n");
+ return -EPROBE_DEFER;
+ }
+ hsotg->plat = plat;
+ } else if (hsotg->phy) {
/*
* If using the generic PHY framework, check if the PHY bus
* width is 8-bit and set the phyif appropriately.
*/
- if (phy_get_bus_width(phy) == 8)
+ if (phy_get_bus_width(hsotg->phy) == 8)
hsotg->phyif = GUSBCFG_PHYIF8;
}
diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c
index 6a795aa..ae095f0 100644
--- a/drivers/usb/dwc2/platform.c
+++ b/drivers/usb/dwc2/platform.c
@@ -155,6 +155,8 @@ static int dwc2_driver_probe(struct platform_device *dev)
struct dwc2_core_params defparams;
struct dwc2_hsotg *hsotg;
struct resource *res;
+ struct phy *phy;
+ struct usb_phy *uphy;
int retval;
int irq;
@@ -212,6 +214,24 @@ static int dwc2_driver_probe(struct platform_device *dev)
hsotg->dr_mode = of_usb_get_dr_mode(dev->dev.of_node);
+ /*
+* Attempt to find a generic PHY, then look for an old style
+* USB PHY
+*/
+ phy = devm_phy_get(>dev, "usb2-phy");
+ if (IS_ERR(phy)) {
+ hsotg->phy = NULL;
+ uphy = devm_usb_get_phy(>dev, USB_PHY_TYPE_USB2);
+ if (IS_ERR(uphy))
+ hsotg->uphy = NULL;
+ else
+ hsotg->uphy = uphy;
+ } else {
+ hsotg->phy = phy;
+ phy_power_on(hsotg->phy);
+ phy_init(hsotg->phy);
+ }
+
spin_lock_init(>lock);
mutex_init(>init_mutex);
retval = dwc2_gadget_init(hsotg, irq);
@@ -231,8 +251,15 @@ static int __maybe_unused dwc2_suspend(struct device *dev)
struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
int ret = 0;
- if (dwc2_is_device_mode(dwc2))
+ if (dwc2_is_device_mode(dwc2)) {
ret = s3c_hsotg_suspend(dwc2);
+ } else {
+ if (dwc2->lx_state == DWC2_L0)
+ return 0;
+ phy_exit(dwc2->phy);
+ phy_power_off(dwc2->phy);
+
+ }
return ret;
}
@@ -241,8 +268,13 @@ static int __maybe_unused dwc2_resume(struct device *dev)
struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
int ret = 0;
-
[PATCH v7 2/5] phy: add a driver for the Rockchip SoC internal USB2.0 PHY
This patch to add a generic PHY driver for ROCKCHIP usb PHYs,
currently this driver can support RK3288. The RK3288 SoC have
three independent USB PHY IPs which are all configured through a
set of registers located in the GRF (general register files)
module.
Signed-off-by: Yunzhi Li
---
Changes in v7:
- Accept Kishon's comments to use phandle args to find a phy
struct directly and get rid of using a custom of_xlate
function.
Changes in v6:
- Rename SIDDQ_MSK to SIDDQ_WRITE_ENA.
Changes in v5: None
Changes in v4:
- Get number of PHYs from device tree.
- Model each PHY as subnode of the phy provider node.
Changes in v3:
- Use BIT macro instead of bit shift ops.
- Rename the config entry to PHY_ROCKCHIP_USB.
drivers/phy/Kconfig| 7 ++
drivers/phy/Makefile | 1 +
drivers/phy/phy-rockchip-usb.c | 158 +
3 files changed, 166 insertions(+)
create mode 100644 drivers/phy/phy-rockchip-usb.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index ccad880..b24500a 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -239,6 +239,13 @@ config PHY_QCOM_IPQ806X_SATA
depends on OF
select GENERIC_PHY
+config PHY_ROCKCHIP_USB
+ tristate "Rockchip USB2 PHY Driver"
+ depends on ARCH_ROCKCHIP && OF
+ select GENERIC_PHY
+ help
+ Enable this to support the Rockchip USB 2.0 PHY.
+
config PHY_ST_SPEAR1310_MIPHY
tristate "ST SPEAR1310-MIPHY driver"
select GENERIC_PHY
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index aa74f96..48bf5a1 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -28,6 +28,7 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2) +=
phy-exynos5250-usb2.o
phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2) += phy-s5pv210-usb2.o
obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o
obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)+= phy-qcom-apq8064-sata.o
+obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)+= phy-qcom-ipq806x-sata.o
obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY) += phy-spear1310-miphy.o
obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) += phy-spear1340-miphy.o
diff --git a/drivers/phy/phy-rockchip-usb.c b/drivers/phy/phy-rockchip-usb.c
new file mode 100644
index 000..22011c3
--- /dev/null
+++ b/drivers/phy/phy-rockchip-usb.c
@@ -0,0 +1,158 @@
+/*
+ * Rockchip usb PHY driver
+ *
+ * Copyright (C) 2014 Yunzhi Li
+ * Copyright (C) 2014 ROCKCHIP, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/*
+ * The higher 16-bit of this register is used for write protection
+ * only if BIT(13 + 16) set to 1 the BIT(13) can be written.
+ */
+#define SIDDQ_WRITE_ENABIT(29)
+#define SIDDQ_ON BIT(13)
+#define SIDDQ_OFF (0 << 13)
+
+struct rockchip_usb_phy {
+ unsigned intreg_offset;
+ struct regmap *reg_base;
+ struct clk *clk;
+ struct phy *phy;
+};
+
+static int rockchip_usb_phy_power(struct rockchip_usb_phy *phy,
+ bool siddq)
+{
+ return regmap_write(phy->reg_base, phy->reg_offset,
+ SIDDQ_WRITE_ENA | (siddq ? SIDDQ_ON : SIDDQ_OFF));
+}
+
+static int rockchip_usb_phy_power_off(struct phy *_phy)
+{
+ struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
+ int ret = 0;
+
+ /* Power down usb phy analog blocks by set siddq 1 */
+ ret = rockchip_usb_phy_power(phy, 1);
+ if (ret)
+ return ret;
+
+ clk_disable_unprepare(phy->clk);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int rockchip_usb_phy_power_on(struct phy *_phy)
+{
+ struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
+ int ret = 0;
+
+ ret = clk_prepare_enable(phy->clk);
+ if (ret)
+ return ret;
+
+ /* Power up usb phy analog blocks by set siddq 0 */
+ ret = rockchip_usb_phy_power(phy, 0);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static struct phy_ops ops = {
+ .power_on = rockchip_usb_phy_power_on,
+ .power_off = rockchip_usb_phy_power_off,
+ .owner = THIS_MODULE,
+};
+
+static int rockchip_usb_phy_probe(struct platform_device *pdev)
+{
+ struct device *dev = >dev;
+
[PATCH v7 1/5] Documentation: bindings: add dt documentation for Rockchip usb PHY
This patch adds a binding that describes the Rockchip usb PHYs
found on Rockchip SoCs usb interface.
Signed-off-by: Yunzhi Li
---
Changes in v7:
- Update bindings doc
Changes in v6: None
Changes in v5:
- Adjust entry order of example devicetree node in document.
Changes in v4:
- Updata description for phy device tree subnode.
Changes in v3: None
.../devicetree/bindings/phy/rockchip-usb-phy.txt | 37 ++
1 file changed, 37 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
diff --git a/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
b/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
new file mode 100644
index 000..826454a
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
@@ -0,0 +1,37 @@
+ROCKCHIP USB2 PHY
+
+Required properties:
+ - compatible: rockchip,rk3288-usb-phy
+ - rockchip,grf : phandle to the syscon managing the "general
+ register files"
+ - #address-cells: should be 1
+ - #size-cells: should be 0
+
+Sub-nodes:
+Each PHY should be represented as a sub-node.
+
+Sub-nodes
+required properties:
+- #phy-cells: should be 0
+- reg: PHY configure reg address offset in GRF
+ "0x320" - for PHY attach to OTG controller
+ "0x334" - for PHY attach to HOST0 controller
+ "0x348" - for PHY attach to HOST1 controller
+
+Optional Properties:
+- clocks : phandle + clock specifier for the phy clocks
+- clock-names: string, clock name, must be "phyclk"
+
+Example:
+
+usbphy: phy {
+ compatible = "rockchip,rk3288-usb-phy";
+ rockchip,grf = <>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usbphy0: usb-phy0 {
+ #phy-cells = <0>;
+ reg = <0x320>;
+ };
+};
--
2.0.0
--
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Please read the FAQ at http://www.tux.org/lkml/
[PATCH v7 0/5] Patches to add support for Rockchip usb PHYs.
Patches to add support for Rockchip usb phys.Add a new Rockchip usb phy driver and modify dwc2 controller driver to make dwc2 platform devices support a generic PHY framework driver. This patch set has been tested on my rk3288-evb and power off the usb phys would reduce about 60mW power budget in total during sustem suspend. Changes in v7: - Update bindings doc - Accept Kishon's comments to use phandle args to find a phy struct directly and get rid of using a custom of_xlate function. - Update dtsi for new usb phy driver. Changes in v6: - Rename SIDDQ_MSK to SIDDQ_WRITE_ENA. Changes in v5: - Adjust entry order of example devicetree node in document. - reorder the phy dt node to a correct position. Changes in v4: - Updata description for phy device tree subnode. - Get number of PHYs from device tree. - Model each PHY as subnode of the phy provider node. - Add phy subnodes. Changes in v3: - Use BIT macro instead of bit shift ops. - Rename the config entry to PHY_ROCKCHIP_USB. - Fix coding style: both branches of the if() which only one branch of the conditional statement is a single statement should have braces. - No need to test dwc2->phy for NULL before calling generic phy APIs. Yunzhi Li (5): Documentation: bindings: add dt documentation for Rockchip usb PHY phy: add a driver for the Rockchip SoC internal USB2.0 PHY usb: dwc2: add generic PHY framework support for dwc2 usb controler platform driver. ARM: dts: rockchip: add rk3288 usb PHY ARM: dts: rockchip: Enable usb PHY on rk3288-evb board .../devicetree/bindings/phy/rockchip-usb-phy.txt | 37 + arch/arm/boot/dts/rk3288-evb.dtsi | 4 + arch/arm/boot/dts/rk3288.dtsi | 35 + drivers/phy/Kconfig| 7 + drivers/phy/Makefile | 1 + drivers/phy/phy-rockchip-usb.c | 158 + drivers/usb/dwc2/gadget.c | 33 ++--- drivers/usb/dwc2/platform.c| 36 - 8 files changed, 288 insertions(+), 23 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt create mode 100644 drivers/phy/phy-rockchip-usb.c -- 2.0.0 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v7 0/5] Patches to add support for Rockchip usb PHYs.
Patches to add support for Rockchip usb phys.Add a new Rockchip usb phy driver and modify dwc2 controller driver to make dwc2 platform devices support a generic PHY framework driver. This patch set has been tested on my rk3288-evb and power off the usb phys would reduce about 60mW power budget in total during sustem suspend. Changes in v7: - Update bindings doc - Accept Kishon's comments to use phandle args to find a phy struct directly and get rid of using a custom of_xlate function. - Update dtsi for new usb phy driver. Changes in v6: - Rename SIDDQ_MSK to SIDDQ_WRITE_ENA. Changes in v5: - Adjust entry order of example devicetree node in document. - reorder the phy dt node to a correct position. Changes in v4: - Updata description for phy device tree subnode. - Get number of PHYs from device tree. - Model each PHY as subnode of the phy provider node. - Add phy subnodes. Changes in v3: - Use BIT macro instead of bit shift ops. - Rename the config entry to PHY_ROCKCHIP_USB. - Fix coding style: both branches of the if() which only one branch of the conditional statement is a single statement should have braces. - No need to test dwc2->phy for NULL before calling generic phy APIs. Yunzhi Li (5): Documentation: bindings: add dt documentation for Rockchip usb PHY phy: add a driver for the Rockchip SoC internal USB2.0 PHY usb: dwc2: add generic PHY framework support for dwc2 usb controler platform driver. ARM: dts: rockchip: add rk3288 usb PHY ARM: dts: rockchip: Enable usb PHY on rk3288-evb board .../devicetree/bindings/phy/rockchip-usb-phy.txt | 37 + arch/arm/boot/dts/rk3288-evb.dtsi | 4 + arch/arm/boot/dts/rk3288.dtsi | 35 + drivers/phy/Kconfig| 7 + drivers/phy/Makefile | 1 + drivers/phy/phy-rockchip-usb.c | 158 + drivers/usb/dwc2/gadget.c | 33 ++--- drivers/usb/dwc2/platform.c| 36 - 8 files changed, 288 insertions(+), 23 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt create mode 100644 drivers/phy/phy-rockchip-usb.c -- 2.0.0 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v7 0/5] Patches to add support for Rockchip usb PHYs.
Patches to add support for Rockchip usb phys.Add a new Rockchip usb phy driver and modify dwc2 controller driver to make dwc2 platform devices support a generic PHY framework driver. This patch set has been tested on my rk3288-evb and power off the usb phys would reduce about 60mW power budget in total during sustem suspend. Changes in v7: - Update bindings doc - Accept Kishon's comments to use phandle args to find a phy struct directly and get rid of using a custom of_xlate function. - Update dtsi for new usb phy driver. Changes in v6: - Rename SIDDQ_MSK to SIDDQ_WRITE_ENA. Changes in v5: - Adjust entry order of example devicetree node in document. - reorder the phy dt node to a correct position. Changes in v4: - Updata description for phy device tree subnode. - Get number of PHYs from device tree. - Model each PHY as subnode of the phy provider node. - Add phy subnodes. Changes in v3: - Use BIT macro instead of bit shift ops. - Rename the config entry to PHY_ROCKCHIP_USB. - Fix coding style: both branches of the if() which only one branch of the conditional statement is a single statement should have braces. - No need to test dwc2-phy for NULL before calling generic phy APIs. Yunzhi Li (5): Documentation: bindings: add dt documentation for Rockchip usb PHY phy: add a driver for the Rockchip SoC internal USB2.0 PHY usb: dwc2: add generic PHY framework support for dwc2 usb controler platform driver. ARM: dts: rockchip: add rk3288 usb PHY ARM: dts: rockchip: Enable usb PHY on rk3288-evb board .../devicetree/bindings/phy/rockchip-usb-phy.txt | 37 + arch/arm/boot/dts/rk3288-evb.dtsi | 4 + arch/arm/boot/dts/rk3288.dtsi | 35 + drivers/phy/Kconfig| 7 + drivers/phy/Makefile | 1 + drivers/phy/phy-rockchip-usb.c | 158 + drivers/usb/dwc2/gadget.c | 33 ++--- drivers/usb/dwc2/platform.c| 36 - 8 files changed, 288 insertions(+), 23 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt create mode 100644 drivers/phy/phy-rockchip-usb.c -- 2.0.0 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v7 0/5] Patches to add support for Rockchip usb PHYs.
Patches to add support for Rockchip usb phys.Add a new Rockchip usb phy driver and modify dwc2 controller driver to make dwc2 platform devices support a generic PHY framework driver. This patch set has been tested on my rk3288-evb and power off the usb phys would reduce about 60mW power budget in total during sustem suspend. Changes in v7: - Update bindings doc - Accept Kishon's comments to use phandle args to find a phy struct directly and get rid of using a custom of_xlate function. - Update dtsi for new usb phy driver. Changes in v6: - Rename SIDDQ_MSK to SIDDQ_WRITE_ENA. Changes in v5: - Adjust entry order of example devicetree node in document. - reorder the phy dt node to a correct position. Changes in v4: - Updata description for phy device tree subnode. - Get number of PHYs from device tree. - Model each PHY as subnode of the phy provider node. - Add phy subnodes. Changes in v3: - Use BIT macro instead of bit shift ops. - Rename the config entry to PHY_ROCKCHIP_USB. - Fix coding style: both branches of the if() which only one branch of the conditional statement is a single statement should have braces. - No need to test dwc2-phy for NULL before calling generic phy APIs. Yunzhi Li (5): Documentation: bindings: add dt documentation for Rockchip usb PHY phy: add a driver for the Rockchip SoC internal USB2.0 PHY usb: dwc2: add generic PHY framework support for dwc2 usb controler platform driver. ARM: dts: rockchip: add rk3288 usb PHY ARM: dts: rockchip: Enable usb PHY on rk3288-evb board .../devicetree/bindings/phy/rockchip-usb-phy.txt | 37 + arch/arm/boot/dts/rk3288-evb.dtsi | 4 + arch/arm/boot/dts/rk3288.dtsi | 35 + drivers/phy/Kconfig| 7 + drivers/phy/Makefile | 1 + drivers/phy/phy-rockchip-usb.c | 158 + drivers/usb/dwc2/gadget.c | 33 ++--- drivers/usb/dwc2/platform.c| 36 - 8 files changed, 288 insertions(+), 23 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt create mode 100644 drivers/phy/phy-rockchip-usb.c -- 2.0.0 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v7 1/5] Documentation: bindings: add dt documentation for Rockchip usb PHY
This patch adds a binding that describes the Rockchip usb PHYs
found on Rockchip SoCs usb interface.
Signed-off-by: Yunzhi Li l...@rock-chips.com
---
Changes in v7:
- Update bindings doc
Changes in v6: None
Changes in v5:
- Adjust entry order of example devicetree node in document.
Changes in v4:
- Updata description for phy device tree subnode.
Changes in v3: None
.../devicetree/bindings/phy/rockchip-usb-phy.txt | 37 ++
1 file changed, 37 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
diff --git a/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
b/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
new file mode 100644
index 000..826454a
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
@@ -0,0 +1,37 @@
+ROCKCHIP USB2 PHY
+
+Required properties:
+ - compatible: rockchip,rk3288-usb-phy
+ - rockchip,grf : phandle to the syscon managing the general
+ register files
+ - #address-cells: should be 1
+ - #size-cells: should be 0
+
+Sub-nodes:
+Each PHY should be represented as a sub-node.
+
+Sub-nodes
+required properties:
+- #phy-cells: should be 0
+- reg: PHY configure reg address offset in GRF
+ 0x320 - for PHY attach to OTG controller
+ 0x334 - for PHY attach to HOST0 controller
+ 0x348 - for PHY attach to HOST1 controller
+
+Optional Properties:
+- clocks : phandle + clock specifier for the phy clocks
+- clock-names: string, clock name, must be phyclk
+
+Example:
+
+usbphy: phy {
+ compatible = rockchip,rk3288-usb-phy;
+ rockchip,grf = grf;
+ #address-cells = 1;
+ #size-cells = 0;
+
+ usbphy0: usb-phy0 {
+ #phy-cells = 0;
+ reg = 0x320;
+ };
+};
--
2.0.0
--
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the body of a message to majord...@vger.kernel.org
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Please read the FAQ at http://www.tux.org/lkml/
[PATCH v7 2/5] phy: add a driver for the Rockchip SoC internal USB2.0 PHY
This patch to add a generic PHY driver for ROCKCHIP usb PHYs,
currently this driver can support RK3288. The RK3288 SoC have
three independent USB PHY IPs which are all configured through a
set of registers located in the GRF (general register files)
module.
Signed-off-by: Yunzhi Li l...@rock-chips.com
---
Changes in v7:
- Accept Kishon's comments to use phandle args to find a phy
struct directly and get rid of using a custom of_xlate
function.
Changes in v6:
- Rename SIDDQ_MSK to SIDDQ_WRITE_ENA.
Changes in v5: None
Changes in v4:
- Get number of PHYs from device tree.
- Model each PHY as subnode of the phy provider node.
Changes in v3:
- Use BIT macro instead of bit shift ops.
- Rename the config entry to PHY_ROCKCHIP_USB.
drivers/phy/Kconfig| 7 ++
drivers/phy/Makefile | 1 +
drivers/phy/phy-rockchip-usb.c | 158 +
3 files changed, 166 insertions(+)
create mode 100644 drivers/phy/phy-rockchip-usb.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index ccad880..b24500a 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -239,6 +239,13 @@ config PHY_QCOM_IPQ806X_SATA
depends on OF
select GENERIC_PHY
+config PHY_ROCKCHIP_USB
+ tristate Rockchip USB2 PHY Driver
+ depends on ARCH_ROCKCHIP OF
+ select GENERIC_PHY
+ help
+ Enable this to support the Rockchip USB 2.0 PHY.
+
config PHY_ST_SPEAR1310_MIPHY
tristate ST SPEAR1310-MIPHY driver
select GENERIC_PHY
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index aa74f96..48bf5a1 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -28,6 +28,7 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2) +=
phy-exynos5250-usb2.o
phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2) += phy-s5pv210-usb2.o
obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o
obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)+= phy-qcom-apq8064-sata.o
+obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)+= phy-qcom-ipq806x-sata.o
obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY) += phy-spear1310-miphy.o
obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) += phy-spear1340-miphy.o
diff --git a/drivers/phy/phy-rockchip-usb.c b/drivers/phy/phy-rockchip-usb.c
new file mode 100644
index 000..22011c3
--- /dev/null
+++ b/drivers/phy/phy-rockchip-usb.c
@@ -0,0 +1,158 @@
+/*
+ * Rockchip usb PHY driver
+ *
+ * Copyright (C) 2014 Yunzhi Li l...@rock-chips.com
+ * Copyright (C) 2014 ROCKCHIP, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/clk.h
+#include linux/io.h
+#include linux/kernel.h
+#include linux/module.h
+#include linux/mutex.h
+#include linux/of.h
+#include linux/of_address.h
+#include linux/phy/phy.h
+#include linux/platform_device.h
+#include linux/regulator/consumer.h
+#include linux/reset.h
+#include linux/regmap.h
+#include linux/mfd/syscon.h
+
+/*
+ * The higher 16-bit of this register is used for write protection
+ * only if BIT(13 + 16) set to 1 the BIT(13) can be written.
+ */
+#define SIDDQ_WRITE_ENABIT(29)
+#define SIDDQ_ON BIT(13)
+#define SIDDQ_OFF (0 13)
+
+struct rockchip_usb_phy {
+ unsigned intreg_offset;
+ struct regmap *reg_base;
+ struct clk *clk;
+ struct phy *phy;
+};
+
+static int rockchip_usb_phy_power(struct rockchip_usb_phy *phy,
+ bool siddq)
+{
+ return regmap_write(phy-reg_base, phy-reg_offset,
+ SIDDQ_WRITE_ENA | (siddq ? SIDDQ_ON : SIDDQ_OFF));
+}
+
+static int rockchip_usb_phy_power_off(struct phy *_phy)
+{
+ struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
+ int ret = 0;
+
+ /* Power down usb phy analog blocks by set siddq 1 */
+ ret = rockchip_usb_phy_power(phy, 1);
+ if (ret)
+ return ret;
+
+ clk_disable_unprepare(phy-clk);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int rockchip_usb_phy_power_on(struct phy *_phy)
+{
+ struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
+ int ret = 0;
+
+ ret = clk_prepare_enable(phy-clk);
+ if (ret)
+ return ret;
+
+ /* Power up usb phy analog blocks by set siddq 0 */
+ ret = rockchip_usb_phy_power(phy, 0);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static struct phy_ops ops = {
+ .power_on = rockchip_usb_phy_power_on,
+ .power_off
[PATCH v7 3/5] usb: dwc2: add generic PHY framework support for dwc2 usb controler platform driver.
Get PHY parameters from devicetree and power off usb PHY during
system suspend.
Signed-off-by: Yunzhi Li l...@rock-chips.com
Acked-by: Paul Zimmerman pa...@synopsys.com
---
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3:
- Fix coding style: both branches of the if() which only one
branch of the conditional statement is a single statement
should have braces.
- No need to test dwc2-phy for NULL before calling generic phy
APIs.
drivers/usb/dwc2/gadget.c | 33 -
drivers/usb/dwc2/platform.c | 36 ++--
2 files changed, 46 insertions(+), 23 deletions(-)
diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c
index 200168e..2601c61 100644
--- a/drivers/usb/dwc2/gadget.c
+++ b/drivers/usb/dwc2/gadget.c
@@ -3410,8 +3410,6 @@ int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq)
{
struct device *dev = hsotg-dev;
struct s3c_hsotg_plat *plat = dev-platform_data;
- struct phy *phy;
- struct usb_phy *uphy;
struct s3c_hsotg_ep *eps;
int epnum;
int ret;
@@ -3421,30 +3419,23 @@ int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq)
hsotg-phyif = GUSBCFG_PHYIF16;
/*
-* Attempt to find a generic PHY, then look for an old style
-* USB PHY, finally fall back to pdata
+* If platform probe couldn't find a generic PHY or an old style
+* USB PHY, fall back to pdata
*/
- phy = devm_phy_get(dev, usb2-phy);
- if (IS_ERR(phy)) {
- uphy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
- if (IS_ERR(uphy)) {
- /* Fallback for pdata */
- plat = dev_get_platdata(dev);
- if (!plat) {
- dev_err(dev,
- no platform data or transceiver defined\n);
- return -EPROBE_DEFER;
- }
- hsotg-plat = plat;
- } else
- hsotg-uphy = uphy;
- } else {
- hsotg-phy = phy;
+ if (IS_ERR_OR_NULL(hsotg-phy) IS_ERR_OR_NULL(hsotg-uphy)) {
+ plat = dev_get_platdata(dev);
+ if (!plat) {
+ dev_err(dev,
+ no platform data or transceiver defined\n);
+ return -EPROBE_DEFER;
+ }
+ hsotg-plat = plat;
+ } else if (hsotg-phy) {
/*
* If using the generic PHY framework, check if the PHY bus
* width is 8-bit and set the phyif appropriately.
*/
- if (phy_get_bus_width(phy) == 8)
+ if (phy_get_bus_width(hsotg-phy) == 8)
hsotg-phyif = GUSBCFG_PHYIF8;
}
diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c
index 6a795aa..ae095f0 100644
--- a/drivers/usb/dwc2/platform.c
+++ b/drivers/usb/dwc2/platform.c
@@ -155,6 +155,8 @@ static int dwc2_driver_probe(struct platform_device *dev)
struct dwc2_core_params defparams;
struct dwc2_hsotg *hsotg;
struct resource *res;
+ struct phy *phy;
+ struct usb_phy *uphy;
int retval;
int irq;
@@ -212,6 +214,24 @@ static int dwc2_driver_probe(struct platform_device *dev)
hsotg-dr_mode = of_usb_get_dr_mode(dev-dev.of_node);
+ /*
+* Attempt to find a generic PHY, then look for an old style
+* USB PHY
+*/
+ phy = devm_phy_get(dev-dev, usb2-phy);
+ if (IS_ERR(phy)) {
+ hsotg-phy = NULL;
+ uphy = devm_usb_get_phy(dev-dev, USB_PHY_TYPE_USB2);
+ if (IS_ERR(uphy))
+ hsotg-uphy = NULL;
+ else
+ hsotg-uphy = uphy;
+ } else {
+ hsotg-phy = phy;
+ phy_power_on(hsotg-phy);
+ phy_init(hsotg-phy);
+ }
+
spin_lock_init(hsotg-lock);
mutex_init(hsotg-init_mutex);
retval = dwc2_gadget_init(hsotg, irq);
@@ -231,8 +251,15 @@ static int __maybe_unused dwc2_suspend(struct device *dev)
struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
int ret = 0;
- if (dwc2_is_device_mode(dwc2))
+ if (dwc2_is_device_mode(dwc2)) {
ret = s3c_hsotg_suspend(dwc2);
+ } else {
+ if (dwc2-lx_state == DWC2_L0)
+ return 0;
+ phy_exit(dwc2-phy);
+ phy_power_off(dwc2-phy);
+
+ }
return ret;
}
@@ -241,8 +268,13 @@ static int __maybe_unused dwc2_resume(struct device *dev)
struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
int ret = 0;
- if (dwc2_is_device_mode(dwc2))
+ if (dwc2_is_device_mode(dwc2)) {
ret = s3c_hsotg_resume(dwc2);
+ } else
[PATCH v7 4/5] ARM: dts: rockchip: add rk3288 usb PHY
This patch adds a device_node for RK3288 SoC usb phy. It also
defines the phy to be used by three usb controllers: usb_host0/1
and usb_otg.
Signed-off-by: Yunzhi Li l...@rock-chips.com
---
Changes in v7:
- Update dtsi for new usb phy driver.
Changes in v6: None
Changes in v5:
- reorder the phy dt node to a correct position.
Changes in v4:
- Add phy subnodes.
Changes in v3: None
arch/arm/boot/dts/rk3288.dtsi | 35 +++
1 file changed, 35 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 874e66d..2a9a029 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -335,6 +335,8 @@
interrupts = GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH;
clocks = cru HCLK_USBHOST0;
clock-names = usbhost;
+ phys = usbphy1;
+ phy-names = usb;
status = disabled;
};
@@ -347,6 +349,8 @@
interrupts = GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH;
clocks = cru HCLK_USBHOST1;
clock-names = otg;
+ phys = usbphy2;
+ phy-names = usb2-phy;
status = disabled;
};
@@ -357,6 +361,8 @@
interrupts = GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH;
clocks = cru HCLK_OTG0;
clock-names = otg;
+ phys = usbphy0;
+ phy-names = usb2-phy;
status = disabled;
};
@@ -497,6 +503,35 @@
interrupts = GIC_PPI 9 0xf04;
};
+ usbphy: phy {
+ compatible = rockchip,rk3288-usb-phy;
+ rockchip,grf = grf;
+ #address-cells = 1;
+ #size-cells = 0;
+ status = disabled;
+
+ usbphy0: usb-phy0 {
+ #phy-cells = 0;
+ reg = 0x320;
+ clocks = cru SCLK_OTGPHY0;
+ clock-names = phyclk;
+ };
+
+ usbphy1: usb-phy1 {
+ #phy-cells = 0;
+ reg = 0x334;
+ clocks = cru SCLK_OTGPHY1;
+ clock-names = phyclk;
+ };
+
+ usbphy2: usb-phy2 {
+ #phy-cells = 0;
+ reg = 0x348;
+ clocks = cru SCLK_OTGPHY2;
+ clock-names = phyclk;
+ };
+ };
+
pinctrl: pinctrl {
compatible = rockchip,rk3288-pinctrl;
rockchip,grf = grf;
--
2.0.0
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[PATCH v7 5/5] ARM: dts: rockchip: Enable usb PHY on rk3288-evb board
Enable usb PHY for all usb ports on rk3288-evb.
Signed-off-by: Yunzhi Li l...@rock-chips.com
---
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
arch/arm/boot/dts/rk3288-evb.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi
b/arch/arm/boot/dts/rk3288-evb.dtsi
index cb83cea..992f323 100644
--- a/arch/arm/boot/dts/rk3288-evb.dtsi
+++ b/arch/arm/boot/dts/rk3288-evb.dtsi
@@ -174,6 +174,10 @@
};
};
+usbphy {
+ status = okay;
+};
+
usb_host0_ehci {
status = okay;
};
--
2.0.0
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Re: [PATCH v6 1/5] phy: add a driver for the Rockchip SoC internal USB2.0 PHY
Hi Doug:
On 2014/12/12 2:09, Doug Anderson wrote:
Yunzhi,
On Thu, Dec 11, 2014 at 1:55 AM, Yunzhi Li wrote:
+ rk_phy->clk = of_clk_get(child, 0);
+ if (IS_ERR(rk_phy->clk)) {
+ dev_warn(dev, "failed to get clock\n");
+ rk_phy->clk = NULL;
+ }
The device tree bindings don't specify a clock and the "dtsi" added to
rk3288 don't reference a clock. Take that code out and avoid a
warning in the logs at bootup.
...or should there be a clock?
Actually, there is a clk gating control bit in CRU for each usb phy and I
think we should manage these clocks by the usb phy driver, so I will add
clock property to usb PHYs nodes in next version of patche set.
+ rk_phy->phy = devm_phy_create(dev, NULL, );
This has the wrong number of arguments. Even before the change that
added the 4th argument, this is still wrong because "ops" is supposed
to be the 2nd argument, not the 3rd.
...so I'm confused how this compiled for you. I think this ought to be:
rk_phy->phy = devm_phy_create(dev, child, , NULL);
...but please correct me if I'm mistaken!
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Re: [PATCH v6 1/5] phy: add a driver for the Rockchip SoC internal USB2.0 PHY
Hi Kishon:
On 2014/12/11 18:27, Kishon Vijay Abraham I wrote:
Hi,
On Thursday 11 December 2014 03:25 PM, Yunzhi Li wrote:
+
+static struct phy *rockchip_usb_phy_xlate(struct device *dev,
+ struct of_phandle_args *args)
+{
+ struct rockchip_usb_phy_priv *priv = dev_get_drvdata(dev);
+ unsigned int phy_id = args->args[0];
+
+ if (WARN_ON(phy_id < 0 || phy_id >= priv->nphys))
+ return ERR_PTR(-ENODEV);
+
+ return priv->phys[phy_id].phy;
I didn't mean that. You can get rid of this entire xlate stuff if you use
something like below
phy@xxx {
compatible = "";
phy1:usb_phy {
}
phy2:usb_phy {
};
};
usb@xx {
compatible = "";
phys = <>; //doesn't need xlate
/* this needs xlate
phys = < 1>;
*/
phy-names = "phy";
};
Thank you so much for your suggestion, but still have a question:
I have to add the #phy-cells property in each phy sub-node, otherwise
devm_get_phy() will fail and I get log info like
"/usb@ff50: could not get #phy-cells for /phy/usbp-phy1". So can the
#phy-cells property defines in patent node
also valid for it's child nodes like #address-cells ?
---
Yunzhi Li @ rockchip
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[PATCH v6 5/5] ARM: dts: rockchip: Enable usb PHY on rk3288-evb board
Enable usb PHY for all usb ports on rk3288-evb.
Signed-off-by: Yunzhi Li
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
arch/arm/boot/dts/rk3288-evb.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi
b/arch/arm/boot/dts/rk3288-evb.dtsi
index cb83cea..992f323 100644
--- a/arch/arm/boot/dts/rk3288-evb.dtsi
+++ b/arch/arm/boot/dts/rk3288-evb.dtsi
@@ -174,6 +174,10 @@
};
};
+ {
+ status = "okay";
+};
+
_host0_ehci {
status = "okay";
};
--
2.0.0
--
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[PATCH v6 4/5] ARM: dts: rockchip: add rk3288 usb PHY
This patch adds a device_node for RK3288 SoC usb phy. It also
defines the phy to be used by three usb controllers: usb_host0/1
and usb_otg.
Signed-off-by: Yunzhi Li
---
Changes in v6: None
Changes in v5:
- reorder the phy dt node to a correct position.
Changes in v4:
- Add phy subnodes.
Changes in v3: None
arch/arm/boot/dts/rk3288.dtsi | 27 +++
1 file changed, 27 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 874e66d..bd2a1e0 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -335,6 +335,8 @@
interrupts = ;
clocks = < HCLK_USBHOST0>;
clock-names = "usbhost";
+ phys = < 1>;
+ phy-names = "usb";
status = "disabled";
};
@@ -347,6 +349,8 @@
interrupts = ;
clocks = < HCLK_USBHOST1>;
clock-names = "otg";
+ phys = < 2>;
+ phy-names = "usb2-phy";
status = "disabled";
};
@@ -357,6 +361,8 @@
interrupts = ;
clocks = < HCLK_OTG0>;
clock-names = "otg";
+ phys = < 0>;
+ phy-names = "usb2-phy";
status = "disabled";
};
@@ -497,6 +503,27 @@
interrupts = ;
};
+ usbphy: phy {
+ compatible = "rockchip,rk3288-usb-phy";
+ rockchip,grf = <>;
+ #phy-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ usb-phy@0 {
+ reg = <0>;
+ };
+
+ usb-phy@1 {
+ reg = <1>;
+ };
+
+ usb-phy@2 {
+ reg = <2>;
+ };
+ };
+
pinctrl: pinctrl {
compatible = "rockchip,rk3288-pinctrl";
rockchip,grf = <>;
--
2.0.0
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[PATCH v6 3/5] usb: dwc2: add generic PHY framework support for dwc2 usb controler platform driver.
Get PHY parameters from devicetree and power off usb PHY during
system suspend.
Signed-off-by: Yunzhi Li
Acked-by: Paul Zimmerman
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3:
- Fix coding style: both branches of the if() which only one
branch of the conditional statement is a single statement
should have braces.
- No need to test dwc2->phy for NULL before calling generic phy
APIs.
drivers/usb/dwc2/gadget.c | 33 -
drivers/usb/dwc2/platform.c | 36 ++--
2 files changed, 46 insertions(+), 23 deletions(-)
diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c
index 200168e..2601c61 100644
--- a/drivers/usb/dwc2/gadget.c
+++ b/drivers/usb/dwc2/gadget.c
@@ -3410,8 +3410,6 @@ int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq)
{
struct device *dev = hsotg->dev;
struct s3c_hsotg_plat *plat = dev->platform_data;
- struct phy *phy;
- struct usb_phy *uphy;
struct s3c_hsotg_ep *eps;
int epnum;
int ret;
@@ -3421,30 +3419,23 @@ int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq)
hsotg->phyif = GUSBCFG_PHYIF16;
/*
-* Attempt to find a generic PHY, then look for an old style
-* USB PHY, finally fall back to pdata
+* If platform probe couldn't find a generic PHY or an old style
+* USB PHY, fall back to pdata
*/
- phy = devm_phy_get(dev, "usb2-phy");
- if (IS_ERR(phy)) {
- uphy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
- if (IS_ERR(uphy)) {
- /* Fallback for pdata */
- plat = dev_get_platdata(dev);
- if (!plat) {
- dev_err(dev,
- "no platform data or transceiver defined\n");
- return -EPROBE_DEFER;
- }
- hsotg->plat = plat;
- } else
- hsotg->uphy = uphy;
- } else {
- hsotg->phy = phy;
+ if (IS_ERR_OR_NULL(hsotg->phy) && IS_ERR_OR_NULL(hsotg->uphy)) {
+ plat = dev_get_platdata(dev);
+ if (!plat) {
+ dev_err(dev,
+ "no platform data or transceiver defined\n");
+ return -EPROBE_DEFER;
+ }
+ hsotg->plat = plat;
+ } else if (hsotg->phy) {
/*
* If using the generic PHY framework, check if the PHY bus
* width is 8-bit and set the phyif appropriately.
*/
- if (phy_get_bus_width(phy) == 8)
+ if (phy_get_bus_width(hsotg->phy) == 8)
hsotg->phyif = GUSBCFG_PHYIF8;
}
diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c
index 6a795aa..ae095f0 100644
--- a/drivers/usb/dwc2/platform.c
+++ b/drivers/usb/dwc2/platform.c
@@ -155,6 +155,8 @@ static int dwc2_driver_probe(struct platform_device *dev)
struct dwc2_core_params defparams;
struct dwc2_hsotg *hsotg;
struct resource *res;
+ struct phy *phy;
+ struct usb_phy *uphy;
int retval;
int irq;
@@ -212,6 +214,24 @@ static int dwc2_driver_probe(struct platform_device *dev)
hsotg->dr_mode = of_usb_get_dr_mode(dev->dev.of_node);
+ /*
+* Attempt to find a generic PHY, then look for an old style
+* USB PHY
+*/
+ phy = devm_phy_get(>dev, "usb2-phy");
+ if (IS_ERR(phy)) {
+ hsotg->phy = NULL;
+ uphy = devm_usb_get_phy(>dev, USB_PHY_TYPE_USB2);
+ if (IS_ERR(uphy))
+ hsotg->uphy = NULL;
+ else
+ hsotg->uphy = uphy;
+ } else {
+ hsotg->phy = phy;
+ phy_power_on(hsotg->phy);
+ phy_init(hsotg->phy);
+ }
+
spin_lock_init(>lock);
mutex_init(>init_mutex);
retval = dwc2_gadget_init(hsotg, irq);
@@ -231,8 +251,15 @@ static int __maybe_unused dwc2_suspend(struct device *dev)
struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
int ret = 0;
- if (dwc2_is_device_mode(dwc2))
+ if (dwc2_is_device_mode(dwc2)) {
ret = s3c_hsotg_suspend(dwc2);
+ } else {
+ if (dwc2->lx_state == DWC2_L0)
+ return 0;
+ phy_exit(dwc2->phy);
+ phy_power_off(dwc2->phy);
+
+ }
return ret;
}
@@ -241,8 +268,13 @@ static int __maybe_unused dwc2_resume(struct device *dev)
struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
int ret = 0;
- if (dwc2_is_device_mode(dwc2))
+ if
[PATCH v6 2/5] Documentation: bindings: add dt documentation for Rockchip usb PHY
This patch adds a binding that describes the Rockchip usb PHYs
found on Rockchip SoCs usb interface.
Signed-off-by: Yunzhi Li
---
Changes in v6: None
Changes in v5:
- Adjust entry order of example devicetree node in document.
Changes in v4:
- Updata description for phy device tree subnode.
Changes in v3: None
.../devicetree/bindings/phy/rockchip-usb-phy.txt | 32 ++
1 file changed, 32 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
diff --git a/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
b/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
new file mode 100644
index 000..e9500d9
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
@@ -0,0 +1,32 @@
+ROCKCHIP USB2 PHY
+
+Required properties:
+ - compatible: rockchip,rk3288-usb-phy
+ - rockchip,grf : phandle to the syscon managing the "general
+ register files"
+ - #phy-cells: should be 1
+ - #address-cells: should be 1
+ - #size-cells: should be 0
+
+Sub-nodes:
+Each PHY should be represented as a sub-node.
+
+Sub-nodes
+required properties:
+- reg: the PHY number
+ "0" - PHY connect to OTG controller
+ "1" - PHY connect to HOST0 controller
+ "2" - PHY connect to HOST1 controller
+
+Optional Properties:
+- clocks : phandle + clock specifier for the phy clocks
+
+Example:
+
+usbphy: phy {
+ compatible = "rockchip,rk3288-usb-phy";
+ rockchip,grf = <>;
+ #phy-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+};
--
2.0.0
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[PATCH v6 1/5] phy: add a driver for the Rockchip SoC internal USB2.0 PHY
This patch to add a generic PHY driver for ROCKCHIP usb PHYs,
currently this driver can support RK3288. The RK3288 SoC have
three independent USB PHY IPs which are all configured through a
set of registers located in the GRF (general register files)
module.
Signed-off-by: Yunzhi Li
---
Changes in v6:
- Rename SIDDQ_MSK to SIDDQ_WRITE_ENA.
- Use phandle args to find a phy struct directly.
Changes in v5: None
Changes in v4:
- Get number of PHYs from device tree.
- Model each PHY as subnode of the phy provider node.
Changes in v3:
- Use BIT macro instead of bit shift ops.
- Rename the config entry to PHY_ROCKCHIP_USB.
drivers/phy/Kconfig| 7 ++
drivers/phy/Makefile | 1 +
drivers/phy/phy-rockchip-usb.c | 198 +
3 files changed, 206 insertions(+)
create mode 100644 drivers/phy/phy-rockchip-usb.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index ccad880..b24500a 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -239,6 +239,13 @@ config PHY_QCOM_IPQ806X_SATA
depends on OF
select GENERIC_PHY
+config PHY_ROCKCHIP_USB
+ tristate "Rockchip USB2 PHY Driver"
+ depends on ARCH_ROCKCHIP && OF
+ select GENERIC_PHY
+ help
+ Enable this to support the Rockchip USB 2.0 PHY.
+
config PHY_ST_SPEAR1310_MIPHY
tristate "ST SPEAR1310-MIPHY driver"
select GENERIC_PHY
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index aa74f96..48bf5a1 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -28,6 +28,7 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2) +=
phy-exynos5250-usb2.o
phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2) += phy-s5pv210-usb2.o
obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o
obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)+= phy-qcom-apq8064-sata.o
+obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)+= phy-qcom-ipq806x-sata.o
obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY) += phy-spear1310-miphy.o
obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) += phy-spear1340-miphy.o
diff --git a/drivers/phy/phy-rockchip-usb.c b/drivers/phy/phy-rockchip-usb.c
new file mode 100644
index 000..dad5194
--- /dev/null
+++ b/drivers/phy/phy-rockchip-usb.c
@@ -0,0 +1,198 @@
+/*
+ * Rockchip usb PHY driver
+ *
+ * Copyright (C) 2014 Yunzhi Li
+ * Copyright (C) 2014 ROCKCHIP, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define ROCKCHIP_RK3288_UOC(n) (0x320 + n * 0x14)
+
+/*
+ * The higher 16-bit of this register is used for write protection
+ * only if BIT(13 + 16) set to 1 the BIT(13) can be written.
+ */
+#define SIDDQ_WRITE_ENABIT(29)
+#define SIDDQ_ON BIT(13)
+#define SIDDQ_OFF (0 << 13)
+
+struct rockchip_usb_phy {
+ struct regmap *reg_base;
+ unsigned intreg_offset;
+ struct clk *clk;
+ struct phy *phy;
+};
+
+struct rockchip_usb_phy_priv {
+ struct rockchip_usb_phy *phys;
+ unsignednphys;
+};
+
+static int rockchip_usb_phy_power(struct rockchip_usb_phy *phy,
+ bool siddq)
+{
+ return regmap_write(phy->reg_base, phy->reg_offset,
+ SIDDQ_WRITE_ENA | (siddq ? SIDDQ_ON : SIDDQ_OFF));
+}
+
+static int rockchip_usb_phy_power_off(struct phy *_phy)
+{
+ struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
+ int ret = 0;
+
+ /* Power down usb phy analog blocks by set siddq 1 */
+ ret = rockchip_usb_phy_power(phy, 1);
+ if (ret)
+ return ret;
+
+ clk_disable_unprepare(phy->clk);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int rockchip_usb_phy_power_on(struct phy *_phy)
+{
+ struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
+ int ret = 0;
+
+ ret = clk_prepare_enable(phy->clk);
+ if (ret)
+ return ret;
+
+ /* Power up usb phy analog blocks by set siddq 0 */
+ ret = rockchip_usb_phy_power(phy, 0);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static struct phy *rockchip_usb_phy_xlate(struct device *dev,
+ struct of_phandle_args *args)
+{
+ struct rockchip_usb_phy_priv *priv = dev_get_drvdata(dev);
+ unsigned int phy_id = a
[PATCH v6 0/5] Patches to add support for Rockchip usb PHYs.
Patches to add support for Rockchip usb phys.Add a new Rockchip usb phy driver and modify dwc2 controller driver to make dwc2 platform devices support a generic PHY framework driver. This patch set has been tested on my rk3288-evb and power off the usb phys would reduce about 60mW power budget in total during sustem suspend. Changes in v6: - Rename SIDDQ_MSK to SIDDQ_WRITE_ENA. - Use phandle args to find a phy struct directly. Changes in v5: - Adjust entry order of example devicetree node in document. - reorder the phy dt node to a correct position. Changes in v4: - Get number of PHYs from device tree. - Model each PHY as subnode of the phy provider node. - Updata description for phy device tree subnode. - Add phy subnodes. Changes in v3: - Use BIT macro instead of bit shift ops. - Rename the config entry to PHY_ROCKCHIP_USB. - Fix coding style: both branches of the if() which only one branch of the conditional statement is a single statement should have braces. - No need to test dwc2->phy for NULL before calling generic phy APIs. Yunzhi Li (5): phy: add a driver for the Rockchip SoC internal USB2.0 PHY Documentation: bindings: add dt documentation for Rockchip usb PHY usb: dwc2: add generic PHY framework support for dwc2 usb controler platform driver. ARM: dts: rockchip: add rk3288 usb PHY ARM: dts: rockchip: Enable usb PHY on rk3288-evb board .../devicetree/bindings/phy/rockchip-usb-phy.txt | 32 arch/arm/boot/dts/rk3288-evb.dtsi | 4 + arch/arm/boot/dts/rk3288.dtsi | 27 +++ drivers/phy/Kconfig| 7 + drivers/phy/Makefile | 1 + drivers/phy/phy-rockchip-usb.c | 198 + drivers/usb/dwc2/gadget.c | 33 ++-- drivers/usb/dwc2/platform.c| 36 +++- 8 files changed, 315 insertions(+), 23 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt create mode 100644 drivers/phy/phy-rockchip-usb.c -- 2.0.0 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v6 0/5] Patches to add support for Rockchip usb PHYs.
Patches to add support for Rockchip usb phys.Add a new Rockchip usb phy driver and modify dwc2 controller driver to make dwc2 platform devices support a generic PHY framework driver. This patch set has been tested on my rk3288-evb and power off the usb phys would reduce about 60mW power budget in total during sustem suspend. Changes in v6: - Rename SIDDQ_MSK to SIDDQ_WRITE_ENA. - Use phandle args to find a phy struct directly. Changes in v5: - Adjust entry order of example devicetree node in document. - reorder the phy dt node to a correct position. Changes in v4: - Get number of PHYs from device tree. - Model each PHY as subnode of the phy provider node. - Updata description for phy device tree subnode. - Add phy subnodes. Changes in v3: - Use BIT macro instead of bit shift ops. - Rename the config entry to PHY_ROCKCHIP_USB. - Fix coding style: both branches of the if() which only one branch of the conditional statement is a single statement should have braces. - No need to test dwc2-phy for NULL before calling generic phy APIs. Yunzhi Li (5): phy: add a driver for the Rockchip SoC internal USB2.0 PHY Documentation: bindings: add dt documentation for Rockchip usb PHY usb: dwc2: add generic PHY framework support for dwc2 usb controler platform driver. ARM: dts: rockchip: add rk3288 usb PHY ARM: dts: rockchip: Enable usb PHY on rk3288-evb board .../devicetree/bindings/phy/rockchip-usb-phy.txt | 32 arch/arm/boot/dts/rk3288-evb.dtsi | 4 + arch/arm/boot/dts/rk3288.dtsi | 27 +++ drivers/phy/Kconfig| 7 + drivers/phy/Makefile | 1 + drivers/phy/phy-rockchip-usb.c | 198 + drivers/usb/dwc2/gadget.c | 33 ++-- drivers/usb/dwc2/platform.c| 36 +++- 8 files changed, 315 insertions(+), 23 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt create mode 100644 drivers/phy/phy-rockchip-usb.c -- 2.0.0 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v6 1/5] phy: add a driver for the Rockchip SoC internal USB2.0 PHY
This patch to add a generic PHY driver for ROCKCHIP usb PHYs,
currently this driver can support RK3288. The RK3288 SoC have
three independent USB PHY IPs which are all configured through a
set of registers located in the GRF (general register files)
module.
Signed-off-by: Yunzhi Li l...@rock-chips.com
---
Changes in v6:
- Rename SIDDQ_MSK to SIDDQ_WRITE_ENA.
- Use phandle args to find a phy struct directly.
Changes in v5: None
Changes in v4:
- Get number of PHYs from device tree.
- Model each PHY as subnode of the phy provider node.
Changes in v3:
- Use BIT macro instead of bit shift ops.
- Rename the config entry to PHY_ROCKCHIP_USB.
drivers/phy/Kconfig| 7 ++
drivers/phy/Makefile | 1 +
drivers/phy/phy-rockchip-usb.c | 198 +
3 files changed, 206 insertions(+)
create mode 100644 drivers/phy/phy-rockchip-usb.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index ccad880..b24500a 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -239,6 +239,13 @@ config PHY_QCOM_IPQ806X_SATA
depends on OF
select GENERIC_PHY
+config PHY_ROCKCHIP_USB
+ tristate Rockchip USB2 PHY Driver
+ depends on ARCH_ROCKCHIP OF
+ select GENERIC_PHY
+ help
+ Enable this to support the Rockchip USB 2.0 PHY.
+
config PHY_ST_SPEAR1310_MIPHY
tristate ST SPEAR1310-MIPHY driver
select GENERIC_PHY
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index aa74f96..48bf5a1 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -28,6 +28,7 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2) +=
phy-exynos5250-usb2.o
phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2) += phy-s5pv210-usb2.o
obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o
obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)+= phy-qcom-apq8064-sata.o
+obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)+= phy-qcom-ipq806x-sata.o
obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY) += phy-spear1310-miphy.o
obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) += phy-spear1340-miphy.o
diff --git a/drivers/phy/phy-rockchip-usb.c b/drivers/phy/phy-rockchip-usb.c
new file mode 100644
index 000..dad5194
--- /dev/null
+++ b/drivers/phy/phy-rockchip-usb.c
@@ -0,0 +1,198 @@
+/*
+ * Rockchip usb PHY driver
+ *
+ * Copyright (C) 2014 Yunzhi Li l...@rock-chips.com
+ * Copyright (C) 2014 ROCKCHIP, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/clk.h
+#include linux/io.h
+#include linux/kernel.h
+#include linux/module.h
+#include linux/mutex.h
+#include linux/of.h
+#include linux/of_address.h
+#include linux/phy/phy.h
+#include linux/platform_device.h
+#include linux/regulator/consumer.h
+#include linux/reset.h
+#include linux/regmap.h
+#include linux/mfd/syscon.h
+
+#define ROCKCHIP_RK3288_UOC(n) (0x320 + n * 0x14)
+
+/*
+ * The higher 16-bit of this register is used for write protection
+ * only if BIT(13 + 16) set to 1 the BIT(13) can be written.
+ */
+#define SIDDQ_WRITE_ENABIT(29)
+#define SIDDQ_ON BIT(13)
+#define SIDDQ_OFF (0 13)
+
+struct rockchip_usb_phy {
+ struct regmap *reg_base;
+ unsigned intreg_offset;
+ struct clk *clk;
+ struct phy *phy;
+};
+
+struct rockchip_usb_phy_priv {
+ struct rockchip_usb_phy *phys;
+ unsignednphys;
+};
+
+static int rockchip_usb_phy_power(struct rockchip_usb_phy *phy,
+ bool siddq)
+{
+ return regmap_write(phy-reg_base, phy-reg_offset,
+ SIDDQ_WRITE_ENA | (siddq ? SIDDQ_ON : SIDDQ_OFF));
+}
+
+static int rockchip_usb_phy_power_off(struct phy *_phy)
+{
+ struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
+ int ret = 0;
+
+ /* Power down usb phy analog blocks by set siddq 1 */
+ ret = rockchip_usb_phy_power(phy, 1);
+ if (ret)
+ return ret;
+
+ clk_disable_unprepare(phy-clk);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int rockchip_usb_phy_power_on(struct phy *_phy)
+{
+ struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
+ int ret = 0;
+
+ ret = clk_prepare_enable(phy-clk);
+ if (ret)
+ return ret;
+
+ /* Power up usb phy analog blocks by set siddq 0 */
+ ret = rockchip_usb_phy_power(phy, 0);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static struct phy *rockchip_usb_phy_xlate(struct
[PATCH v6 2/5] Documentation: bindings: add dt documentation for Rockchip usb PHY
This patch adds a binding that describes the Rockchip usb PHYs
found on Rockchip SoCs usb interface.
Signed-off-by: Yunzhi Li l...@rock-chips.com
---
Changes in v6: None
Changes in v5:
- Adjust entry order of example devicetree node in document.
Changes in v4:
- Updata description for phy device tree subnode.
Changes in v3: None
.../devicetree/bindings/phy/rockchip-usb-phy.txt | 32 ++
1 file changed, 32 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
diff --git a/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
b/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
new file mode 100644
index 000..e9500d9
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
@@ -0,0 +1,32 @@
+ROCKCHIP USB2 PHY
+
+Required properties:
+ - compatible: rockchip,rk3288-usb-phy
+ - rockchip,grf : phandle to the syscon managing the general
+ register files
+ - #phy-cells: should be 1
+ - #address-cells: should be 1
+ - #size-cells: should be 0
+
+Sub-nodes:
+Each PHY should be represented as a sub-node.
+
+Sub-nodes
+required properties:
+- reg: the PHY number
+ 0 - PHY connect to OTG controller
+ 1 - PHY connect to HOST0 controller
+ 2 - PHY connect to HOST1 controller
+
+Optional Properties:
+- clocks : phandle + clock specifier for the phy clocks
+
+Example:
+
+usbphy: phy {
+ compatible = rockchip,rk3288-usb-phy;
+ rockchip,grf = grf;
+ #phy-cells = 1;
+ #address-cells = 1;
+ #size-cells = 0;
+};
--
2.0.0
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[PATCH v6 3/5] usb: dwc2: add generic PHY framework support for dwc2 usb controler platform driver.
Get PHY parameters from devicetree and power off usb PHY during
system suspend.
Signed-off-by: Yunzhi Li l...@rock-chips.com
Acked-by: Paul Zimmerman pa...@synopsys.com
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3:
- Fix coding style: both branches of the if() which only one
branch of the conditional statement is a single statement
should have braces.
- No need to test dwc2-phy for NULL before calling generic phy
APIs.
drivers/usb/dwc2/gadget.c | 33 -
drivers/usb/dwc2/platform.c | 36 ++--
2 files changed, 46 insertions(+), 23 deletions(-)
diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c
index 200168e..2601c61 100644
--- a/drivers/usb/dwc2/gadget.c
+++ b/drivers/usb/dwc2/gadget.c
@@ -3410,8 +3410,6 @@ int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq)
{
struct device *dev = hsotg-dev;
struct s3c_hsotg_plat *plat = dev-platform_data;
- struct phy *phy;
- struct usb_phy *uphy;
struct s3c_hsotg_ep *eps;
int epnum;
int ret;
@@ -3421,30 +3419,23 @@ int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq)
hsotg-phyif = GUSBCFG_PHYIF16;
/*
-* Attempt to find a generic PHY, then look for an old style
-* USB PHY, finally fall back to pdata
+* If platform probe couldn't find a generic PHY or an old style
+* USB PHY, fall back to pdata
*/
- phy = devm_phy_get(dev, usb2-phy);
- if (IS_ERR(phy)) {
- uphy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
- if (IS_ERR(uphy)) {
- /* Fallback for pdata */
- plat = dev_get_platdata(dev);
- if (!plat) {
- dev_err(dev,
- no platform data or transceiver defined\n);
- return -EPROBE_DEFER;
- }
- hsotg-plat = plat;
- } else
- hsotg-uphy = uphy;
- } else {
- hsotg-phy = phy;
+ if (IS_ERR_OR_NULL(hsotg-phy) IS_ERR_OR_NULL(hsotg-uphy)) {
+ plat = dev_get_platdata(dev);
+ if (!plat) {
+ dev_err(dev,
+ no platform data or transceiver defined\n);
+ return -EPROBE_DEFER;
+ }
+ hsotg-plat = plat;
+ } else if (hsotg-phy) {
/*
* If using the generic PHY framework, check if the PHY bus
* width is 8-bit and set the phyif appropriately.
*/
- if (phy_get_bus_width(phy) == 8)
+ if (phy_get_bus_width(hsotg-phy) == 8)
hsotg-phyif = GUSBCFG_PHYIF8;
}
diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c
index 6a795aa..ae095f0 100644
--- a/drivers/usb/dwc2/platform.c
+++ b/drivers/usb/dwc2/platform.c
@@ -155,6 +155,8 @@ static int dwc2_driver_probe(struct platform_device *dev)
struct dwc2_core_params defparams;
struct dwc2_hsotg *hsotg;
struct resource *res;
+ struct phy *phy;
+ struct usb_phy *uphy;
int retval;
int irq;
@@ -212,6 +214,24 @@ static int dwc2_driver_probe(struct platform_device *dev)
hsotg-dr_mode = of_usb_get_dr_mode(dev-dev.of_node);
+ /*
+* Attempt to find a generic PHY, then look for an old style
+* USB PHY
+*/
+ phy = devm_phy_get(dev-dev, usb2-phy);
+ if (IS_ERR(phy)) {
+ hsotg-phy = NULL;
+ uphy = devm_usb_get_phy(dev-dev, USB_PHY_TYPE_USB2);
+ if (IS_ERR(uphy))
+ hsotg-uphy = NULL;
+ else
+ hsotg-uphy = uphy;
+ } else {
+ hsotg-phy = phy;
+ phy_power_on(hsotg-phy);
+ phy_init(hsotg-phy);
+ }
+
spin_lock_init(hsotg-lock);
mutex_init(hsotg-init_mutex);
retval = dwc2_gadget_init(hsotg, irq);
@@ -231,8 +251,15 @@ static int __maybe_unused dwc2_suspend(struct device *dev)
struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
int ret = 0;
- if (dwc2_is_device_mode(dwc2))
+ if (dwc2_is_device_mode(dwc2)) {
ret = s3c_hsotg_suspend(dwc2);
+ } else {
+ if (dwc2-lx_state == DWC2_L0)
+ return 0;
+ phy_exit(dwc2-phy);
+ phy_power_off(dwc2-phy);
+
+ }
return ret;
}
@@ -241,8 +268,13 @@ static int __maybe_unused dwc2_resume(struct device *dev)
struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
int ret = 0;
- if (dwc2_is_device_mode(dwc2))
+ if (dwc2_is_device_mode(dwc2)) {
ret = s3c_hsotg_resume(dwc2);
+ } else
[PATCH v6 4/5] ARM: dts: rockchip: add rk3288 usb PHY
This patch adds a device_node for RK3288 SoC usb phy. It also
defines the phy to be used by three usb controllers: usb_host0/1
and usb_otg.
Signed-off-by: Yunzhi Li l...@rock-chips.com
---
Changes in v6: None
Changes in v5:
- reorder the phy dt node to a correct position.
Changes in v4:
- Add phy subnodes.
Changes in v3: None
arch/arm/boot/dts/rk3288.dtsi | 27 +++
1 file changed, 27 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 874e66d..bd2a1e0 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -335,6 +335,8 @@
interrupts = GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH;
clocks = cru HCLK_USBHOST0;
clock-names = usbhost;
+ phys = usbphy 1;
+ phy-names = usb;
status = disabled;
};
@@ -347,6 +349,8 @@
interrupts = GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH;
clocks = cru HCLK_USBHOST1;
clock-names = otg;
+ phys = usbphy 2;
+ phy-names = usb2-phy;
status = disabled;
};
@@ -357,6 +361,8 @@
interrupts = GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH;
clocks = cru HCLK_OTG0;
clock-names = otg;
+ phys = usbphy 0;
+ phy-names = usb2-phy;
status = disabled;
};
@@ -497,6 +503,27 @@
interrupts = GIC_PPI 9 0xf04;
};
+ usbphy: phy {
+ compatible = rockchip,rk3288-usb-phy;
+ rockchip,grf = grf;
+ #phy-cells = 1;
+ #address-cells = 1;
+ #size-cells = 0;
+ status = disabled;
+
+ usb-phy@0 {
+ reg = 0;
+ };
+
+ usb-phy@1 {
+ reg = 1;
+ };
+
+ usb-phy@2 {
+ reg = 2;
+ };
+ };
+
pinctrl: pinctrl {
compatible = rockchip,rk3288-pinctrl;
rockchip,grf = grf;
--
2.0.0
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[PATCH v6 5/5] ARM: dts: rockchip: Enable usb PHY on rk3288-evb board
Enable usb PHY for all usb ports on rk3288-evb.
Signed-off-by: Yunzhi Li l...@rock-chips.com
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
arch/arm/boot/dts/rk3288-evb.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi
b/arch/arm/boot/dts/rk3288-evb.dtsi
index cb83cea..992f323 100644
--- a/arch/arm/boot/dts/rk3288-evb.dtsi
+++ b/arch/arm/boot/dts/rk3288-evb.dtsi
@@ -174,6 +174,10 @@
};
};
+usbphy {
+ status = okay;
+};
+
usb_host0_ehci {
status = okay;
};
--
2.0.0
--
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Re: [PATCH v6 1/5] phy: add a driver for the Rockchip SoC internal USB2.0 PHY
Hi Kishon:
On 2014/12/11 18:27, Kishon Vijay Abraham I wrote:
Hi,
On Thursday 11 December 2014 03:25 PM, Yunzhi Li wrote:
+
+static struct phy *rockchip_usb_phy_xlate(struct device *dev,
+ struct of_phandle_args *args)
+{
+ struct rockchip_usb_phy_priv *priv = dev_get_drvdata(dev);
+ unsigned int phy_id = args-args[0];
+
+ if (WARN_ON(phy_id 0 || phy_id = priv-nphys))
+ return ERR_PTR(-ENODEV);
+
+ return priv-phys[phy_id].phy;
I didn't mean that. You can get rid of this entire xlate stuff if you use
something like below
phy@xxx {
compatible = ;
phy1:usb_phy {
}
phy2:usb_phy {
};
};
usb@xx {
compatible = ;
phys = phy1; //doesn't need xlate
/* this needs xlate
phys = phy 1;
*/
phy-names = phy;
};
Thank you so much for your suggestion, but still have a question:
I have to add the #phy-cells property in each phy sub-node, otherwise
devm_get_phy() will fail and I get log info like
/usb@ff50: could not get #phy-cells for /phy/usbp-phy1. So can the
#phy-cells property defines in patent node
also valid for it's child nodes like #address-cells ?
---
Yunzhi Li @ rockchip
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Re: [PATCH v6 1/5] phy: add a driver for the Rockchip SoC internal USB2.0 PHY
Hi Doug:
On 2014/12/12 2:09, Doug Anderson wrote:
Yunzhi,
On Thu, Dec 11, 2014 at 1:55 AM, Yunzhi Li l...@rock-chips.com wrote:
+ rk_phy-clk = of_clk_get(child, 0);
+ if (IS_ERR(rk_phy-clk)) {
+ dev_warn(dev, failed to get clock\n);
+ rk_phy-clk = NULL;
+ }
The device tree bindings don't specify a clock and the dtsi added to
rk3288 don't reference a clock. Take that code out and avoid a
warning in the logs at bootup.
...or should there be a clock?
Actually, there is a clk gating control bit in CRU for each usb phy and I
think we should manage these clocks by the usb phy driver, so I will add
clock property to usb PHYs nodes in next version of patche set.
+ rk_phy-phy = devm_phy_create(dev, NULL, ops);
This has the wrong number of arguments. Even before the change that
added the 4th argument, this is still wrong because ops is supposed
to be the 2nd argument, not the 3rd.
...so I'm confused how this compiled for you. I think this ought to be:
rk_phy-phy = devm_phy_create(dev, child, ops, NULL);
...but please correct me if I'm mistaken!
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Re: [PATCH v5 1/5] phy: add a driver for the Rockchip SoC internal USB2.0 PHY
Hi Kishon:
On 2014/12/11 14:02, Kishon Vijay Abraham I wrote:
Hi,
On Wednesday 10 December 2014 04:16 PM, Yunzhi Li wrote:
This patch to add a generic PHY driver for ROCKCHIP usb PHYs,
currently this driver can support RK3288. The RK3288 SoC have
three independent USB PHY IPs which are all configured through a
set of registers located in the GRF (general register files)
module.
Signed-off-by: Yunzhi Li
+
+#define ROCKCHIP_RK3288_UOC(n) (0x320 + n * 0x14)
+
+/*
+ * The higher 16-bit of this register is used for write protection
+ * only if BIT(13 + 16) set to 1 the BIT(13) can be written.
+ */
+#define SIDDQ_MSK BIT(13 + 16)
I think here the "MSK" is misleading. it should be something that refers write
protection?
So, #define SIDDQ_WRITE_ENA BIT(29) , could be ok ?
+#define SIDDQ_ON BIT(13)
+#define SIDDQ_OFF (0 << 13)
+
+struct rockchip_usb_phy {
+ struct regmap *reg_base;
+ unsigned intreg_offset;
+ struct clk *clk;
+ struct phy *phy;
+ unsignedindex;
+};
+
+struct rockchip_usb_phy_priv {
+ struct rockchip_usb_phy *phys;
+ unsignednphys;
+};
+
+static int rockchip_usb_phy_power(struct rockchip_usb_phy *phy,
+ bool siddq)
+{
+ return regmap_write(phy->reg_base, phy->reg_offset,
+ SIDDQ_MSK | (siddq ? SIDDQ_ON : SIDDQ_OFF));
Shouldn't we actually reset the bit for power off?
Sorry, which bit you refer to here and why should it be reset? could
you give more infomation.
---
Yunzhi Li @ rockchip
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Re: [PATCH v5 1/5] phy: add a driver for the Rockchip SoC internal USB2.0 PHY
On 2014/12/11 14:37, Joe Perches wrote: On Thu, 2014-12-11 at 11:57 +0530, Kishon Vijay Abraham I wrote: Hi, On Thursday 11 December 2014 11:42 AM, Joe Perches wrote: On Thu, 2014-12-11 at 11:32 +0530, Kishon Vijay Abraham I wrote: On Wednesday 10 December 2014 04:16 PM, Yunzhi Li wrote: diff --git a/drivers/phy/phy-rockchip-usb.c b/drivers/phy/phy-rockchip-usb.c [] +/* + * The higher 16-bit of this register is used for write protection + * only if BIT(13 + 16) set to 1 the BIT(13) can be written. + */ +#define SIDDQ_MSK BIT(13 + 16) huh? This #define looks _very_ odd. Is this supposed to be a single bit 29 or some range? From what I understood, the most significant 16 bits are write locks to the least significant 16 bits. So If I have to write something on bit 0, I have to set bit 16. If I have to write something on bit 1, I have to set bit 17. If I have to write something on bit 2, I have to set bit 18. and so on. To me it'd look better to use another << rather than a plus Like (BIT(13) << 16)? It looks strange, or could I just use ((1 << 13) << 16) to describe this bit ? --- Yunzhi Li @ rockchip -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v5 3/5] usb: dwc2: add generic PHY framework support for dwc2 usb controler platform driver.
Get PHY parameters from devicetree and power off usb PHY during
system suspend.
Signed-off-by: Yunzhi Li
Acked-by: Paul Zimmerman
---
Changes in v5: None
Changes in v4: None
Changes in v3:
- Fix coding style: both branches of the if() which only one
branch of the conditional statement is a single statement
should have braces.
- No need to test dwc2->phy for NULL before calling generic phy
APIs.
drivers/usb/dwc2/gadget.c | 33 -
drivers/usb/dwc2/platform.c | 36 ++--
2 files changed, 46 insertions(+), 23 deletions(-)
diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c
index 200168e..2601c61 100644
--- a/drivers/usb/dwc2/gadget.c
+++ b/drivers/usb/dwc2/gadget.c
@@ -3410,8 +3410,6 @@ int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq)
{
struct device *dev = hsotg->dev;
struct s3c_hsotg_plat *plat = dev->platform_data;
- struct phy *phy;
- struct usb_phy *uphy;
struct s3c_hsotg_ep *eps;
int epnum;
int ret;
@@ -3421,30 +3419,23 @@ int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq)
hsotg->phyif = GUSBCFG_PHYIF16;
/*
-* Attempt to find a generic PHY, then look for an old style
-* USB PHY, finally fall back to pdata
+* If platform probe couldn't find a generic PHY or an old style
+* USB PHY, fall back to pdata
*/
- phy = devm_phy_get(dev, "usb2-phy");
- if (IS_ERR(phy)) {
- uphy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
- if (IS_ERR(uphy)) {
- /* Fallback for pdata */
- plat = dev_get_platdata(dev);
- if (!plat) {
- dev_err(dev,
- "no platform data or transceiver defined\n");
- return -EPROBE_DEFER;
- }
- hsotg->plat = plat;
- } else
- hsotg->uphy = uphy;
- } else {
- hsotg->phy = phy;
+ if (IS_ERR_OR_NULL(hsotg->phy) && IS_ERR_OR_NULL(hsotg->uphy)) {
+ plat = dev_get_platdata(dev);
+ if (!plat) {
+ dev_err(dev,
+ "no platform data or transceiver defined\n");
+ return -EPROBE_DEFER;
+ }
+ hsotg->plat = plat;
+ } else if (hsotg->phy) {
/*
* If using the generic PHY framework, check if the PHY bus
* width is 8-bit and set the phyif appropriately.
*/
- if (phy_get_bus_width(phy) == 8)
+ if (phy_get_bus_width(hsotg->phy) == 8)
hsotg->phyif = GUSBCFG_PHYIF8;
}
diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c
index 6a795aa..ae095f0 100644
--- a/drivers/usb/dwc2/platform.c
+++ b/drivers/usb/dwc2/platform.c
@@ -155,6 +155,8 @@ static int dwc2_driver_probe(struct platform_device *dev)
struct dwc2_core_params defparams;
struct dwc2_hsotg *hsotg;
struct resource *res;
+ struct phy *phy;
+ struct usb_phy *uphy;
int retval;
int irq;
@@ -212,6 +214,24 @@ static int dwc2_driver_probe(struct platform_device *dev)
hsotg->dr_mode = of_usb_get_dr_mode(dev->dev.of_node);
+ /*
+* Attempt to find a generic PHY, then look for an old style
+* USB PHY
+*/
+ phy = devm_phy_get(>dev, "usb2-phy");
+ if (IS_ERR(phy)) {
+ hsotg->phy = NULL;
+ uphy = devm_usb_get_phy(>dev, USB_PHY_TYPE_USB2);
+ if (IS_ERR(uphy))
+ hsotg->uphy = NULL;
+ else
+ hsotg->uphy = uphy;
+ } else {
+ hsotg->phy = phy;
+ phy_power_on(hsotg->phy);
+ phy_init(hsotg->phy);
+ }
+
spin_lock_init(>lock);
mutex_init(>init_mutex);
retval = dwc2_gadget_init(hsotg, irq);
@@ -231,8 +251,15 @@ static int __maybe_unused dwc2_suspend(struct device *dev)
struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
int ret = 0;
- if (dwc2_is_device_mode(dwc2))
+ if (dwc2_is_device_mode(dwc2)) {
ret = s3c_hsotg_suspend(dwc2);
+ } else {
+ if (dwc2->lx_state == DWC2_L0)
+ return 0;
+ phy_exit(dwc2->phy);
+ phy_power_off(dwc2->phy);
+
+ }
return ret;
}
@@ -241,8 +268,13 @@ static int __maybe_unused dwc2_resume(struct device *dev)
struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
int ret = 0;
- if (dwc2_is_device_mode(dwc2))
+ if
[PATCH v5 4/5] ARM: dts: rockchip: add rk3288 usb PHY
This patch adds a device_node for RK3288 SoC usb phy. It also
defines the phy to be used by three usb controllers: usb_host0/1
and usb_otg.
Signed-off-by: Yunzhi Li
---
Changes in v5:
- reorder the phy dt node to a correct position.
Changes in v4:
- Add phy subnodes.
Changes in v3: None
arch/arm/boot/dts/rk3288.dtsi | 27 +++
1 file changed, 27 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 874e66d..bd2a1e0 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -335,6 +335,8 @@
interrupts = ;
clocks = < HCLK_USBHOST0>;
clock-names = "usbhost";
+ phys = < 1>;
+ phy-names = "usb";
status = "disabled";
};
@@ -347,6 +349,8 @@
interrupts = ;
clocks = < HCLK_USBHOST1>;
clock-names = "otg";
+ phys = < 2>;
+ phy-names = "usb2-phy";
status = "disabled";
};
@@ -357,6 +361,8 @@
interrupts = ;
clocks = < HCLK_OTG0>;
clock-names = "otg";
+ phys = < 0>;
+ phy-names = "usb2-phy";
status = "disabled";
};
@@ -497,6 +503,27 @@
interrupts = ;
};
+ usbphy: phy {
+ compatible = "rockchip,rk3288-usb-phy";
+ rockchip,grf = <>;
+ #phy-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ usb-phy@0 {
+ reg = <0>;
+ };
+
+ usb-phy@1 {
+ reg = <1>;
+ };
+
+ usb-phy@2 {
+ reg = <2>;
+ };
+ };
+
pinctrl: pinctrl {
compatible = "rockchip,rk3288-pinctrl";
rockchip,grf = <>;
--
2.0.0
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[PATCH v5 2/5] Documentation: bindings: add dt documentation for Rockchip usb PHY
This patch adds a binding that describes the Rockchip usb PHYs
found on Rockchip SoCs usb interface.
Signed-off-by: Yunzhi Li
---
Changes in v5:
- Adjust entry order of example devicetree node in document.
Changes in v4:
- Updata description for phy device tree subnode.
Changes in v3: None
.../devicetree/bindings/phy/rockchip-usb-phy.txt | 32 ++
1 file changed, 32 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
diff --git a/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
b/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
new file mode 100644
index 000..e9500d9
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
@@ -0,0 +1,32 @@
+ROCKCHIP USB2 PHY
+
+Required properties:
+ - compatible: rockchip,rk3288-usb-phy
+ - rockchip,grf : phandle to the syscon managing the "general
+ register files"
+ - #phy-cells: should be 1
+ - #address-cells: should be 1
+ - #size-cells: should be 0
+
+Sub-nodes:
+Each PHY should be represented as a sub-node.
+
+Sub-nodes
+required properties:
+- reg: the PHY number
+ "0" - PHY connect to OTG controller
+ "1" - PHY connect to HOST0 controller
+ "2" - PHY connect to HOST1 controller
+
+Optional Properties:
+- clocks : phandle + clock specifier for the phy clocks
+
+Example:
+
+usbphy: phy {
+ compatible = "rockchip,rk3288-usb-phy";
+ rockchip,grf = <>;
+ #phy-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+};
--
2.0.0
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[PATCH v5 1/5] phy: add a driver for the Rockchip SoC internal USB2.0 PHY
This patch to add a generic PHY driver for ROCKCHIP usb PHYs,
currently this driver can support RK3288. The RK3288 SoC have
three independent USB PHY IPs which are all configured through a
set of registers located in the GRF (general register files)
module.
Signed-off-by: Yunzhi Li
---
Changes in v5: None
Changes in v4:
- Get number of PHYs from device tree.
- Model each PHY as subnode of the phy provider node.
Changes in v3:
- Use BIT macro instead of bit shift ops.
- Rename the config entry to PHY_ROCKCHIP_USB.
drivers/phy/Kconfig| 7 ++
drivers/phy/Makefile | 1 +
drivers/phy/phy-rockchip-usb.c | 211 +
3 files changed, 219 insertions(+)
create mode 100644 drivers/phy/phy-rockchip-usb.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index ccad880..8a39d2a 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -239,6 +239,13 @@ config PHY_QCOM_IPQ806X_SATA
depends on OF
select GENERIC_PHY
+config PHY_ROCKCHIP_USB2
+ tristate "Rockchip USB2 PHY Driver"
+ depends on ARCH_ROCKCHIP && OF
+ select GENERIC_PHY
+ help
+ Enable this to support the Rockchip USB 2.0 PHY.
+
config PHY_ST_SPEAR1310_MIPHY
tristate "ST SPEAR1310-MIPHY driver"
select GENERIC_PHY
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index aa74f96..8a13f72 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -28,6 +28,7 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2) +=
phy-exynos5250-usb2.o
phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2) += phy-s5pv210-usb2.o
obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o
obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)+= phy-qcom-apq8064-sata.o
+obj-$(CONFIG_PHY_ROCKCHIP_USB2) += phy-rockchip-usb.o
obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)+= phy-qcom-ipq806x-sata.o
obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY) += phy-spear1310-miphy.o
obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) += phy-spear1340-miphy.o
diff --git a/drivers/phy/phy-rockchip-usb.c b/drivers/phy/phy-rockchip-usb.c
new file mode 100644
index 000..0317c21
--- /dev/null
+++ b/drivers/phy/phy-rockchip-usb.c
@@ -0,0 +1,211 @@
+/*
+ * Rockchip usb PHY driver
+ *
+ * Copyright (C) 2014 Yunzhi Li
+ * Copyright (C) 2014 ROCKCHIP, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define ROCKCHIP_RK3288_UOC(n) (0x320 + n * 0x14)
+
+/*
+ * The higher 16-bit of this register is used for write protection
+ * only if BIT(13 + 16) set to 1 the BIT(13) can be written.
+ */
+#define SIDDQ_MSK BIT(13 + 16)
+#define SIDDQ_ON BIT(13)
+#define SIDDQ_OFF (0 << 13)
+
+struct rockchip_usb_phy {
+ struct regmap *reg_base;
+ unsigned intreg_offset;
+ struct clk *clk;
+ struct phy *phy;
+ unsignedindex;
+};
+
+struct rockchip_usb_phy_priv {
+ struct rockchip_usb_phy *phys;
+ unsignednphys;
+};
+
+static int rockchip_usb_phy_power(struct rockchip_usb_phy *phy,
+ bool siddq)
+{
+ return regmap_write(phy->reg_base, phy->reg_offset,
+ SIDDQ_MSK | (siddq ? SIDDQ_ON : SIDDQ_OFF));
+}
+
+static int rockchip_usb_phy_power_off(struct phy *_phy)
+{
+ struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
+ int ret = 0;
+
+ /* Power down usb phy analog blocks by set siddq 1 */
+ ret = rockchip_usb_phy_power(phy, 1);
+ if (ret)
+ return ret;
+
+ clk_disable_unprepare(phy->clk);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int rockchip_usb_phy_power_on(struct phy *_phy)
+{
+ struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
+ int ret = 0;
+
+ ret = clk_prepare_enable(phy->clk);
+ if (ret)
+ return ret;
+
+ /* Power up usb phy analog blocks by set siddq 0 */
+ ret = rockchip_usb_phy_power(phy, 0);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static struct phy *rockchip_usb_phy_xlate(struct device *dev,
+ struct of_phandle_args *args)
+{
+ struct rockchip_usb_phy_priv *priv = dev_get_drvdata(dev);
+ int i;
+
+ if (WARN_ON(args->args[0] >= priv->nphys))
+ return ERR
[PATCH v5 0/5] Patches to add support for Rockchip usb PHYs.
Patches to add support for Rockchip usb phys.Add a new Rockchip usb phy driver and modify dwc2 controller driver to make dwc2 platform devices support a generic PHY framework driver. This patch set has been tested on my rk3288-evb and power off the usb phys would reduce about 60mW power budget in total during sustem suspend. Changes in v5: - Adjust entry order of example devicetree node in document. - reorder the phy dt node to a correct position. Changes in v4: - Get number of PHYs from device tree. - Model each PHY as subnode of the phy provider node. - Updata description for phy device tree subnode. - Add phy subnodes. Changes in v3: - Use BIT macro instead of bit shift ops. - Rename the config entry to PHY_ROCKCHIP_USB. - Fix coding style: both branches of the if() which only one branch of the conditional statement is a single statement should have braces. - No need to test dwc2->phy for NULL before calling generic phy APIs. Yunzhi Li (5): phy: add a driver for the Rockchip SoC internal USB2.0 PHY Documentation: bindings: add dt documentation for Rockchip usb PHY usb: dwc2: add generic PHY framework support for dwc2 usb controler platform driver. ARM: dts: rockchip: add rk3288 usb PHY ARM: dts: rockchip: Enable usb PHY on rk3288-evb board .../devicetree/bindings/phy/rockchip-usb-phy.txt | 32 arch/arm/boot/dts/rk3288-evb.dtsi | 4 + arch/arm/boot/dts/rk3288.dtsi | 27 +++ drivers/phy/Kconfig| 7 + drivers/phy/Makefile | 1 + drivers/phy/phy-rockchip-usb.c | 211 + drivers/usb/dwc2/gadget.c | 33 ++-- drivers/usb/dwc2/platform.c| 36 +++- 8 files changed, 328 insertions(+), 23 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt create mode 100644 drivers/phy/phy-rockchip-usb.c -- 2.0.0 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v4 1/5] phy: add a driver for the Rockchip SoC internal USB2.0 PHY
Hi Romain: On 2014/12/9 18:41, Romain Perier wrote: Hi, 2014-12-09 3:43 GMT+01:00 Yunzhi Li : Changes in v3: - Use BIT macro instead of bit shift ops. - Rename the config entry to PHY_ROCKCHIP_USB. Contradiction between this , [1] and [2] drivers/phy/Kconfig| 7 ++ drivers/phy/Makefile | 1 + drivers/phy/phy-rockchip-usb.c | 211 + 3 files changed, 219 insertions(+) create mode 100644 drivers/phy/phy-rockchip-usb.c diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index ccad880..8a39d2a 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -239,6 +239,13 @@ config PHY_QCOM_IPQ806X_SATA depends on OF select GENERIC_PHY +config PHY_ROCKCHIP_USB2 + tristate "Rockchip USB2 PHY Driver" + depends on ARCH_ROCKCHIP && OF + select GENERIC_PHY + help + Enable this to support the Rockchip USB 2.0 PHY. + 1. The config entry ends by "USB2". Explain that your driver is for usb 2.0 in the description is enough, imho. config PHY_ST_SPEAR1310_MIPHY tristate "ST SPEAR1310-MIPHY driver" select GENERIC_PHY diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index aa74f96..8a13f72 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -28,6 +28,7 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2) += phy-exynos5250-usb2.o phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2) += phy-s5pv210-usb2.o obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)+= phy-qcom-apq8064-sata.o +obj-$(CONFIG_PHY_ROCKCHIP_USB2) += phy-rockchip-usb.o 2. and... this :) So,do you mean that I should rename the C source file as phy-rockchip-usb2.c ? Romain -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v5 1/5] phy: add a driver for the Rockchip SoC internal USB2.0 PHY
On 2014/12/11 14:37, Joe Perches wrote: On Thu, 2014-12-11 at 11:57 +0530, Kishon Vijay Abraham I wrote: Hi, On Thursday 11 December 2014 11:42 AM, Joe Perches wrote: On Thu, 2014-12-11 at 11:32 +0530, Kishon Vijay Abraham I wrote: On Wednesday 10 December 2014 04:16 PM, Yunzhi Li wrote: diff --git a/drivers/phy/phy-rockchip-usb.c b/drivers/phy/phy-rockchip-usb.c [] +/* + * The higher 16-bit of this register is used for write protection + * only if BIT(13 + 16) set to 1 the BIT(13) can be written. + */ +#define SIDDQ_MSK BIT(13 + 16) huh? This #define looks _very_ odd. Is this supposed to be a single bit 29 or some range? From what I understood, the most significant 16 bits are write locks to the least significant 16 bits. So If I have to write something on bit 0, I have to set bit 16. If I have to write something on bit 1, I have to set bit 17. If I have to write something on bit 2, I have to set bit 18. and so on. To me it'd look better to use another rather than a plus Like (BIT(13) 16)? It looks strange, or could I just use ((1 13) 16) to describe this bit ? --- Yunzhi Li @ rockchip -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v5 1/5] phy: add a driver for the Rockchip SoC internal USB2.0 PHY
Hi Kishon:
On 2014/12/11 14:02, Kishon Vijay Abraham I wrote:
Hi,
On Wednesday 10 December 2014 04:16 PM, Yunzhi Li wrote:
This patch to add a generic PHY driver for ROCKCHIP usb PHYs,
currently this driver can support RK3288. The RK3288 SoC have
three independent USB PHY IPs which are all configured through a
set of registers located in the GRF (general register files)
module.
Signed-off-by: Yunzhi Li l...@rock-chips.com
+
+#define ROCKCHIP_RK3288_UOC(n) (0x320 + n * 0x14)
+
+/*
+ * The higher 16-bit of this register is used for write protection
+ * only if BIT(13 + 16) set to 1 the BIT(13) can be written.
+ */
+#define SIDDQ_MSK BIT(13 + 16)
I think here the MSK is misleading. it should be something that refers write
protection?
So, #define SIDDQ_WRITE_ENA BIT(29) , could be ok ?
+#define SIDDQ_ON BIT(13)
+#define SIDDQ_OFF (0 13)
+
+struct rockchip_usb_phy {
+ struct regmap *reg_base;
+ unsigned intreg_offset;
+ struct clk *clk;
+ struct phy *phy;
+ unsignedindex;
+};
+
+struct rockchip_usb_phy_priv {
+ struct rockchip_usb_phy *phys;
+ unsignednphys;
+};
+
+static int rockchip_usb_phy_power(struct rockchip_usb_phy *phy,
+ bool siddq)
+{
+ return regmap_write(phy-reg_base, phy-reg_offset,
+ SIDDQ_MSK | (siddq ? SIDDQ_ON : SIDDQ_OFF));
Shouldn't we actually reset the bit for power off?
Sorry, which bit you refer to here and why should it be reset? could
you give more infomation.
---
Yunzhi Li @ rockchip
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Re: [PATCH v4 1/5] phy: add a driver for the Rockchip SoC internal USB2.0 PHY
Hi Romain: On 2014/12/9 18:41, Romain Perier wrote: Hi, 2014-12-09 3:43 GMT+01:00 Yunzhi Li l...@rock-chips.com: Changes in v3: - Use BIT macro instead of bit shift ops. - Rename the config entry to PHY_ROCKCHIP_USB. Contradiction between this , [1] and [2] drivers/phy/Kconfig| 7 ++ drivers/phy/Makefile | 1 + drivers/phy/phy-rockchip-usb.c | 211 + 3 files changed, 219 insertions(+) create mode 100644 drivers/phy/phy-rockchip-usb.c diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index ccad880..8a39d2a 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -239,6 +239,13 @@ config PHY_QCOM_IPQ806X_SATA depends on OF select GENERIC_PHY +config PHY_ROCKCHIP_USB2 + tristate Rockchip USB2 PHY Driver + depends on ARCH_ROCKCHIP OF + select GENERIC_PHY + help + Enable this to support the Rockchip USB 2.0 PHY. + 1. The config entry ends by USB2. Explain that your driver is for usb 2.0 in the description is enough, imho. config PHY_ST_SPEAR1310_MIPHY tristate ST SPEAR1310-MIPHY driver select GENERIC_PHY diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index aa74f96..8a13f72 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -28,6 +28,7 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2) += phy-exynos5250-usb2.o phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2) += phy-s5pv210-usb2.o obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)+= phy-qcom-apq8064-sata.o +obj-$(CONFIG_PHY_ROCKCHIP_USB2) += phy-rockchip-usb.o 2. and... this :) So,do you mean that I should rename the C source file as phy-rockchip-usb2.c ? Romain -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v5 0/5] Patches to add support for Rockchip usb PHYs.
Patches to add support for Rockchip usb phys.Add a new Rockchip usb phy driver and modify dwc2 controller driver to make dwc2 platform devices support a generic PHY framework driver. This patch set has been tested on my rk3288-evb and power off the usb phys would reduce about 60mW power budget in total during sustem suspend. Changes in v5: - Adjust entry order of example devicetree node in document. - reorder the phy dt node to a correct position. Changes in v4: - Get number of PHYs from device tree. - Model each PHY as subnode of the phy provider node. - Updata description for phy device tree subnode. - Add phy subnodes. Changes in v3: - Use BIT macro instead of bit shift ops. - Rename the config entry to PHY_ROCKCHIP_USB. - Fix coding style: both branches of the if() which only one branch of the conditional statement is a single statement should have braces. - No need to test dwc2-phy for NULL before calling generic phy APIs. Yunzhi Li (5): phy: add a driver for the Rockchip SoC internal USB2.0 PHY Documentation: bindings: add dt documentation for Rockchip usb PHY usb: dwc2: add generic PHY framework support for dwc2 usb controler platform driver. ARM: dts: rockchip: add rk3288 usb PHY ARM: dts: rockchip: Enable usb PHY on rk3288-evb board .../devicetree/bindings/phy/rockchip-usb-phy.txt | 32 arch/arm/boot/dts/rk3288-evb.dtsi | 4 + arch/arm/boot/dts/rk3288.dtsi | 27 +++ drivers/phy/Kconfig| 7 + drivers/phy/Makefile | 1 + drivers/phy/phy-rockchip-usb.c | 211 + drivers/usb/dwc2/gadget.c | 33 ++-- drivers/usb/dwc2/platform.c| 36 +++- 8 files changed, 328 insertions(+), 23 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt create mode 100644 drivers/phy/phy-rockchip-usb.c -- 2.0.0 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v5 1/5] phy: add a driver for the Rockchip SoC internal USB2.0 PHY
This patch to add a generic PHY driver for ROCKCHIP usb PHYs,
currently this driver can support RK3288. The RK3288 SoC have
three independent USB PHY IPs which are all configured through a
set of registers located in the GRF (general register files)
module.
Signed-off-by: Yunzhi Li l...@rock-chips.com
---
Changes in v5: None
Changes in v4:
- Get number of PHYs from device tree.
- Model each PHY as subnode of the phy provider node.
Changes in v3:
- Use BIT macro instead of bit shift ops.
- Rename the config entry to PHY_ROCKCHIP_USB.
drivers/phy/Kconfig| 7 ++
drivers/phy/Makefile | 1 +
drivers/phy/phy-rockchip-usb.c | 211 +
3 files changed, 219 insertions(+)
create mode 100644 drivers/phy/phy-rockchip-usb.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index ccad880..8a39d2a 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -239,6 +239,13 @@ config PHY_QCOM_IPQ806X_SATA
depends on OF
select GENERIC_PHY
+config PHY_ROCKCHIP_USB2
+ tristate Rockchip USB2 PHY Driver
+ depends on ARCH_ROCKCHIP OF
+ select GENERIC_PHY
+ help
+ Enable this to support the Rockchip USB 2.0 PHY.
+
config PHY_ST_SPEAR1310_MIPHY
tristate ST SPEAR1310-MIPHY driver
select GENERIC_PHY
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index aa74f96..8a13f72 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -28,6 +28,7 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2) +=
phy-exynos5250-usb2.o
phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2) += phy-s5pv210-usb2.o
obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o
obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)+= phy-qcom-apq8064-sata.o
+obj-$(CONFIG_PHY_ROCKCHIP_USB2) += phy-rockchip-usb.o
obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)+= phy-qcom-ipq806x-sata.o
obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY) += phy-spear1310-miphy.o
obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) += phy-spear1340-miphy.o
diff --git a/drivers/phy/phy-rockchip-usb.c b/drivers/phy/phy-rockchip-usb.c
new file mode 100644
index 000..0317c21
--- /dev/null
+++ b/drivers/phy/phy-rockchip-usb.c
@@ -0,0 +1,211 @@
+/*
+ * Rockchip usb PHY driver
+ *
+ * Copyright (C) 2014 Yunzhi Li l...@rock-chips.com
+ * Copyright (C) 2014 ROCKCHIP, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/clk.h
+#include linux/io.h
+#include linux/kernel.h
+#include linux/module.h
+#include linux/mutex.h
+#include linux/of.h
+#include linux/of_address.h
+#include linux/phy/phy.h
+#include linux/platform_device.h
+#include linux/regulator/consumer.h
+#include linux/reset.h
+#include linux/regmap.h
+#include linux/mfd/syscon.h
+
+#define ROCKCHIP_RK3288_UOC(n) (0x320 + n * 0x14)
+
+/*
+ * The higher 16-bit of this register is used for write protection
+ * only if BIT(13 + 16) set to 1 the BIT(13) can be written.
+ */
+#define SIDDQ_MSK BIT(13 + 16)
+#define SIDDQ_ON BIT(13)
+#define SIDDQ_OFF (0 13)
+
+struct rockchip_usb_phy {
+ struct regmap *reg_base;
+ unsigned intreg_offset;
+ struct clk *clk;
+ struct phy *phy;
+ unsignedindex;
+};
+
+struct rockchip_usb_phy_priv {
+ struct rockchip_usb_phy *phys;
+ unsignednphys;
+};
+
+static int rockchip_usb_phy_power(struct rockchip_usb_phy *phy,
+ bool siddq)
+{
+ return regmap_write(phy-reg_base, phy-reg_offset,
+ SIDDQ_MSK | (siddq ? SIDDQ_ON : SIDDQ_OFF));
+}
+
+static int rockchip_usb_phy_power_off(struct phy *_phy)
+{
+ struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
+ int ret = 0;
+
+ /* Power down usb phy analog blocks by set siddq 1 */
+ ret = rockchip_usb_phy_power(phy, 1);
+ if (ret)
+ return ret;
+
+ clk_disable_unprepare(phy-clk);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int rockchip_usb_phy_power_on(struct phy *_phy)
+{
+ struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
+ int ret = 0;
+
+ ret = clk_prepare_enable(phy-clk);
+ if (ret)
+ return ret;
+
+ /* Power up usb phy analog blocks by set siddq 0 */
+ ret = rockchip_usb_phy_power(phy, 0);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static struct phy *rockchip_usb_phy_xlate(struct device *dev,
+ struct of_phandle_args
[PATCH v5 2/5] Documentation: bindings: add dt documentation for Rockchip usb PHY
This patch adds a binding that describes the Rockchip usb PHYs
found on Rockchip SoCs usb interface.
Signed-off-by: Yunzhi Li l...@rock-chips.com
---
Changes in v5:
- Adjust entry order of example devicetree node in document.
Changes in v4:
- Updata description for phy device tree subnode.
Changes in v3: None
.../devicetree/bindings/phy/rockchip-usb-phy.txt | 32 ++
1 file changed, 32 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
diff --git a/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
b/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
new file mode 100644
index 000..e9500d9
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
@@ -0,0 +1,32 @@
+ROCKCHIP USB2 PHY
+
+Required properties:
+ - compatible: rockchip,rk3288-usb-phy
+ - rockchip,grf : phandle to the syscon managing the general
+ register files
+ - #phy-cells: should be 1
+ - #address-cells: should be 1
+ - #size-cells: should be 0
+
+Sub-nodes:
+Each PHY should be represented as a sub-node.
+
+Sub-nodes
+required properties:
+- reg: the PHY number
+ 0 - PHY connect to OTG controller
+ 1 - PHY connect to HOST0 controller
+ 2 - PHY connect to HOST1 controller
+
+Optional Properties:
+- clocks : phandle + clock specifier for the phy clocks
+
+Example:
+
+usbphy: phy {
+ compatible = rockchip,rk3288-usb-phy;
+ rockchip,grf = grf;
+ #phy-cells = 1;
+ #address-cells = 1;
+ #size-cells = 0;
+};
--
2.0.0
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[PATCH v5 4/5] ARM: dts: rockchip: add rk3288 usb PHY
This patch adds a device_node for RK3288 SoC usb phy. It also
defines the phy to be used by three usb controllers: usb_host0/1
and usb_otg.
Signed-off-by: Yunzhi Li l...@rock-chips.com
---
Changes in v5:
- reorder the phy dt node to a correct position.
Changes in v4:
- Add phy subnodes.
Changes in v3: None
arch/arm/boot/dts/rk3288.dtsi | 27 +++
1 file changed, 27 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 874e66d..bd2a1e0 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -335,6 +335,8 @@
interrupts = GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH;
clocks = cru HCLK_USBHOST0;
clock-names = usbhost;
+ phys = usbphy 1;
+ phy-names = usb;
status = disabled;
};
@@ -347,6 +349,8 @@
interrupts = GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH;
clocks = cru HCLK_USBHOST1;
clock-names = otg;
+ phys = usbphy 2;
+ phy-names = usb2-phy;
status = disabled;
};
@@ -357,6 +361,8 @@
interrupts = GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH;
clocks = cru HCLK_OTG0;
clock-names = otg;
+ phys = usbphy 0;
+ phy-names = usb2-phy;
status = disabled;
};
@@ -497,6 +503,27 @@
interrupts = GIC_PPI 9 0xf04;
};
+ usbphy: phy {
+ compatible = rockchip,rk3288-usb-phy;
+ rockchip,grf = grf;
+ #phy-cells = 1;
+ #address-cells = 1;
+ #size-cells = 0;
+ status = disabled;
+
+ usb-phy@0 {
+ reg = 0;
+ };
+
+ usb-phy@1 {
+ reg = 1;
+ };
+
+ usb-phy@2 {
+ reg = 2;
+ };
+ };
+
pinctrl: pinctrl {
compatible = rockchip,rk3288-pinctrl;
rockchip,grf = grf;
--
2.0.0
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[PATCH v5 3/5] usb: dwc2: add generic PHY framework support for dwc2 usb controler platform driver.
Get PHY parameters from devicetree and power off usb PHY during
system suspend.
Signed-off-by: Yunzhi Li l...@rock-chips.com
Acked-by: Paul Zimmerman pa...@synopsys.com
---
Changes in v5: None
Changes in v4: None
Changes in v3:
- Fix coding style: both branches of the if() which only one
branch of the conditional statement is a single statement
should have braces.
- No need to test dwc2-phy for NULL before calling generic phy
APIs.
drivers/usb/dwc2/gadget.c | 33 -
drivers/usb/dwc2/platform.c | 36 ++--
2 files changed, 46 insertions(+), 23 deletions(-)
diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c
index 200168e..2601c61 100644
--- a/drivers/usb/dwc2/gadget.c
+++ b/drivers/usb/dwc2/gadget.c
@@ -3410,8 +3410,6 @@ int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq)
{
struct device *dev = hsotg-dev;
struct s3c_hsotg_plat *plat = dev-platform_data;
- struct phy *phy;
- struct usb_phy *uphy;
struct s3c_hsotg_ep *eps;
int epnum;
int ret;
@@ -3421,30 +3419,23 @@ int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq)
hsotg-phyif = GUSBCFG_PHYIF16;
/*
-* Attempt to find a generic PHY, then look for an old style
-* USB PHY, finally fall back to pdata
+* If platform probe couldn't find a generic PHY or an old style
+* USB PHY, fall back to pdata
*/
- phy = devm_phy_get(dev, usb2-phy);
- if (IS_ERR(phy)) {
- uphy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
- if (IS_ERR(uphy)) {
- /* Fallback for pdata */
- plat = dev_get_platdata(dev);
- if (!plat) {
- dev_err(dev,
- no platform data or transceiver defined\n);
- return -EPROBE_DEFER;
- }
- hsotg-plat = plat;
- } else
- hsotg-uphy = uphy;
- } else {
- hsotg-phy = phy;
+ if (IS_ERR_OR_NULL(hsotg-phy) IS_ERR_OR_NULL(hsotg-uphy)) {
+ plat = dev_get_platdata(dev);
+ if (!plat) {
+ dev_err(dev,
+ no platform data or transceiver defined\n);
+ return -EPROBE_DEFER;
+ }
+ hsotg-plat = plat;
+ } else if (hsotg-phy) {
/*
* If using the generic PHY framework, check if the PHY bus
* width is 8-bit and set the phyif appropriately.
*/
- if (phy_get_bus_width(phy) == 8)
+ if (phy_get_bus_width(hsotg-phy) == 8)
hsotg-phyif = GUSBCFG_PHYIF8;
}
diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c
index 6a795aa..ae095f0 100644
--- a/drivers/usb/dwc2/platform.c
+++ b/drivers/usb/dwc2/platform.c
@@ -155,6 +155,8 @@ static int dwc2_driver_probe(struct platform_device *dev)
struct dwc2_core_params defparams;
struct dwc2_hsotg *hsotg;
struct resource *res;
+ struct phy *phy;
+ struct usb_phy *uphy;
int retval;
int irq;
@@ -212,6 +214,24 @@ static int dwc2_driver_probe(struct platform_device *dev)
hsotg-dr_mode = of_usb_get_dr_mode(dev-dev.of_node);
+ /*
+* Attempt to find a generic PHY, then look for an old style
+* USB PHY
+*/
+ phy = devm_phy_get(dev-dev, usb2-phy);
+ if (IS_ERR(phy)) {
+ hsotg-phy = NULL;
+ uphy = devm_usb_get_phy(dev-dev, USB_PHY_TYPE_USB2);
+ if (IS_ERR(uphy))
+ hsotg-uphy = NULL;
+ else
+ hsotg-uphy = uphy;
+ } else {
+ hsotg-phy = phy;
+ phy_power_on(hsotg-phy);
+ phy_init(hsotg-phy);
+ }
+
spin_lock_init(hsotg-lock);
mutex_init(hsotg-init_mutex);
retval = dwc2_gadget_init(hsotg, irq);
@@ -231,8 +251,15 @@ static int __maybe_unused dwc2_suspend(struct device *dev)
struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
int ret = 0;
- if (dwc2_is_device_mode(dwc2))
+ if (dwc2_is_device_mode(dwc2)) {
ret = s3c_hsotg_suspend(dwc2);
+ } else {
+ if (dwc2-lx_state == DWC2_L0)
+ return 0;
+ phy_exit(dwc2-phy);
+ phy_power_off(dwc2-phy);
+
+ }
return ret;
}
@@ -241,8 +268,13 @@ static int __maybe_unused dwc2_resume(struct device *dev)
struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
int ret = 0;
- if (dwc2_is_device_mode(dwc2))
+ if (dwc2_is_device_mode(dwc2)) {
ret = s3c_hsotg_resume(dwc2);
+ } else {
+ phy_power_on(dwc2-phy
[Resend PATCH v4 3/5] usb: dwc2: add generic PHY
Get PHY parameters from devicetree and power off usb PHY during
system suspend.
Signed-off-by: Yunzhi Li
Acked-by: Paul Zimmerman
---
Hi Felipe,
Sorry for my mistake, I have fixed the commit log.
Changes in v4: None
Changes in v3:
- Fix coding style: both branches of the if() which only one
branch of the conditional statement is a single statement
should have braces.
- No need to test dwc2->phy for NULL before calling generic phy
APIs.
drivers/usb/dwc2/gadget.c | 33 -
drivers/usb/dwc2/platform.c | 36 ++--
2 files changed, 46 insertions(+), 23 deletions(-)
diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c
index 200168e..2601c61 100644
--- a/drivers/usb/dwc2/gadget.c
+++ b/drivers/usb/dwc2/gadget.c
@@ -3410,8 +3410,6 @@ int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq)
{
struct device *dev = hsotg->dev;
struct s3c_hsotg_plat *plat = dev->platform_data;
- struct phy *phy;
- struct usb_phy *uphy;
struct s3c_hsotg_ep *eps;
int epnum;
int ret;
@@ -3421,30 +3419,23 @@ int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq)
hsotg->phyif = GUSBCFG_PHYIF16;
/*
-* Attempt to find a generic PHY, then look for an old style
-* USB PHY, finally fall back to pdata
+* If platform probe couldn't find a generic PHY or an old style
+* USB PHY, fall back to pdata
*/
- phy = devm_phy_get(dev, "usb2-phy");
- if (IS_ERR(phy)) {
- uphy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
- if (IS_ERR(uphy)) {
- /* Fallback for pdata */
- plat = dev_get_platdata(dev);
- if (!plat) {
- dev_err(dev,
- "no platform data or transceiver defined\n");
- return -EPROBE_DEFER;
- }
- hsotg->plat = plat;
- } else
- hsotg->uphy = uphy;
- } else {
- hsotg->phy = phy;
+ if (IS_ERR_OR_NULL(hsotg->phy) && IS_ERR_OR_NULL(hsotg->uphy)) {
+ plat = dev_get_platdata(dev);
+ if (!plat) {
+ dev_err(dev,
+ "no platform data or transceiver defined\n");
+ return -EPROBE_DEFER;
+ }
+ hsotg->plat = plat;
+ } else if (hsotg->phy) {
/*
* If using the generic PHY framework, check if the PHY bus
* width is 8-bit and set the phyif appropriately.
*/
- if (phy_get_bus_width(phy) == 8)
+ if (phy_get_bus_width(hsotg->phy) == 8)
hsotg->phyif = GUSBCFG_PHYIF8;
}
diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c
index 6a795aa..ae095f0 100644
--- a/drivers/usb/dwc2/platform.c
+++ b/drivers/usb/dwc2/platform.c
@@ -155,6 +155,8 @@ static int dwc2_driver_probe(struct platform_device *dev)
struct dwc2_core_params defparams;
struct dwc2_hsotg *hsotg;
struct resource *res;
+ struct phy *phy;
+ struct usb_phy *uphy;
int retval;
int irq;
@@ -212,6 +214,24 @@ static int dwc2_driver_probe(struct platform_device *dev)
hsotg->dr_mode = of_usb_get_dr_mode(dev->dev.of_node);
+ /*
+* Attempt to find a generic PHY, then look for an old style
+* USB PHY
+*/
+ phy = devm_phy_get(>dev, "usb2-phy");
+ if (IS_ERR(phy)) {
+ hsotg->phy = NULL;
+ uphy = devm_usb_get_phy(>dev, USB_PHY_TYPE_USB2);
+ if (IS_ERR(uphy))
+ hsotg->uphy = NULL;
+ else
+ hsotg->uphy = uphy;
+ } else {
+ hsotg->phy = phy;
+ phy_power_on(hsotg->phy);
+ phy_init(hsotg->phy);
+ }
+
spin_lock_init(>lock);
mutex_init(>init_mutex);
retval = dwc2_gadget_init(hsotg, irq);
@@ -231,8 +251,15 @@ static int __maybe_unused dwc2_suspend(struct device *dev)
struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
int ret = 0;
- if (dwc2_is_device_mode(dwc2))
+ if (dwc2_is_device_mode(dwc2)) {
ret = s3c_hsotg_suspend(dwc2);
+ } else {
+ if (dwc2->lx_state == DWC2_L0)
+ return 0;
+ phy_exit(dwc2->phy);
+ phy_power_off(dwc2->phy);
+
+ }
return ret;
}
@@ -241,8 +268,13 @@ static int __maybe_unused dwc2_resume(struct device *dev)
struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
int ret = 0;
-
[PATCH v4 5/5] ARM: dts: Enable usb PHY on rk3288-evb board
Enable usb PHY for all usb ports on rk3288-evb.
Signed-off-by: Yunzhi Li
---
Changes in v4: None
Changes in v3: None
arch/arm/boot/dts/rk3288-evb.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi
b/arch/arm/boot/dts/rk3288-evb.dtsi
index cb83cea..992f323 100644
--- a/arch/arm/boot/dts/rk3288-evb.dtsi
+++ b/arch/arm/boot/dts/rk3288-evb.dtsi
@@ -174,6 +174,10 @@
};
};
+ {
+ status = "okay";
+};
+
_host0_ehci {
status = "okay";
};
--
2.0.0
--
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