Re: [RFC PATCH] drm/ttm: force cached mappings for system RAM on ARM
On 1/10/19 3:28 PM, Ard Biesheuvel wrote: ARM systems do not permit the use of anything other than cached mappings for system memory, since that memory may be mapped in the linear region as well, and the architecture does not permit aliases with mismatched attributes. So short-circuit the evaluation in ttm_io_prot() if the flags include TTM_PL_SYSTEM when running on ARM or arm64, and just return cached attributes immediately. It sounds a case for ARM system memory access from CPU only? If that always applies to ARM memory, suppose we should do that for TTM_PL_TT as well. While TTM_PL_TT | TTM_PL_FLAG_WC is likely to work as below mention. Regards, Jerry This fixes the radeon and amdgpu [TBC] drivers when running on arm64. Without this change, amdgpu does not start at all, and radeon only produces corrupt display output. Cc: Christian Koenig Cc: Huang Rui Cc: Junwei Zhang Cc: David Airlie Reported-by: Carsten Haitzler Signed-off-by: Ard Biesheuvel --- drivers/gpu/drm/ttm/ttm_bo_util.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c index 046a6dda690a..0c1eef5f7ae3 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_util.c +++ b/drivers/gpu/drm/ttm/ttm_bo_util.c @@ -530,6 +530,11 @@ pgprot_t ttm_io_prot(uint32_t caching_flags, pgprot_t tmp) if (caching_flags & TTM_PL_FLAG_CACHED) return tmp; +#if defined(__arm__) || defined(__aarch64__) + /* ARM only permits cached mappings of system memory */ + if (caching_flags & TTM_PL_SYSTEM) + return tmp; +#endif #if defined(__i386__) || defined(__x86_64__) if (caching_flags & TTM_PL_FLAG_WC) tmp = pgprot_writecombine(tmp);
Re: [PATCH] drm/ttm: Use drm_debug_printer for all ttm_bo_mem_space_debug output
> 在 2018年12月20日，19:22，Michel Dänzer 写道：
>
> From: Michel Dänzer
Reviewed-by: Junwei Zhang
>
> No need for pr_err here, the pr_err message in ttm_bo_evict is enough
> to draw attention to something not going as planned.
>
> Signed-off-by: Michel Dänzer
> ---
>
> Similar to a previous patch, but this one leaves the pr_err messages in
> ttm_bo_evict untouched.
>
> drivers/gpu/drm/ttm/ttm_bo.c | 33 +
> 1 file changed, 17 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
> index d87935bf8e30..0ec08394e17a 100644
> --- a/drivers/gpu/drm/ttm/ttm_bo.c
> +++ b/drivers/gpu/drm/ttm/ttm_bo.c
> @@ -77,38 +77,39 @@ static inline int ttm_mem_type_from_place(const struct
> ttm_place *place,
> return 0;
> }
>
> -static void ttm_mem_type_debug(struct ttm_bo_device *bdev, int mem_type)
> +static void ttm_mem_type_debug(struct ttm_bo_device *bdev, struct
> drm_printer *p,
> +int mem_type)
> {
> struct ttm_mem_type_manager *man = &bdev->man[mem_type];
> - struct drm_printer p = drm_debug_printer(TTM_PFX);
>
> - pr_err("has_type: %d\n", man->has_type);
> - pr_err("use_type: %d\n", man->use_type);
> - pr_err("flags: 0x%08X\n", man->flags);
> - pr_err("gpu_offset: 0x%08llX\n", man->gpu_offset);
> - pr_err("size: %llu\n", man->size);
> - pr_err("available_caching: 0x%08X\n", man->available_caching);
> - pr_err("default_caching: 0x%08X\n", man->default_caching);
> + drm_printf(p, "has_type: %d\n", man->has_type);
> + drm_printf(p, "use_type: %d\n", man->use_type);
> + drm_printf(p, "flags: 0x%08X\n", man->flags);
> + drm_printf(p, "gpu_offset: 0x%08llX\n", man->gpu_offset);
> + drm_printf(p, "size: %llu\n", man->size);
> + drm_printf(p, "available_caching: 0x%08X\n",
> man->available_caching);
> + drm_printf(p, "default_caching: 0x%08X\n", man->default_caching);
> if (mem_type != TTM_PL_SYSTEM)
> - (*man->func->debug)(man, &p);
> + (*man->func->debug)(man, p);
> }
>
> static void ttm_bo_mem_space_debug(struct ttm_buffer_object *bo,
> struct ttm_placement *placement)
> {
> + struct drm_printer p = drm_debug_printer(TTM_PFX);
> int i, ret, mem_type;
>
> - pr_err("No space for %p (%lu pages, %luK, %luM)\n",
> -bo, bo->mem.num_pages, bo->mem.size >> 10,
> -bo->mem.size >> 20);
> + drm_printf(&p, "No space for %p (%lu pages, %luK, %luM)\n",
> +bo, bo->mem.num_pages, bo->mem.size >> 10,
> +bo->mem.size >> 20);
> for (i = 0; i < placement->num_placement; i++) {
> ret = ttm_mem_type_from_place(&placement->placement[i],
> &mem_type);
> if (ret)
> return;
> - pr_err(" placement[%d]=0x%08X (%d)\n",
> -i, placement->placement[i].flags, mem_type);
> - ttm_mem_type_debug(bo->bdev, mem_type);
> + drm_printf(&p, " placement[%d]=0x%08X (%d)\n",
> +i, placement->placement[i].flags, mem_type);
> + ttm_mem_type_debug(bo->bdev, &p, mem_type);
> }
> }
>
> --
> 2.20.1
>
RE: [PATCH 4/4] drm/amdgpu: resize VRAM BAR for CPU access
Thanks for your info. I see. Regards, Jerry (Junwei Zhang) Linux Base Graphics SRDC Software Development _ > -Original Message- > From: Alex Deucher [mailto:alexdeuc...@gmail.com] > Sent: Thursday, March 16, 2017 10:25 > To: Zhang, Jerry > Cc: Christian König; Zhou, David(ChunMing); Ayyappa Ch; linux- > p...@vger.kernel.org; linux-kernel@vger.kernel.org; dri- > de...@lists.freedesktop.org; platform-driver-...@vger.kernel.org; > helg...@kernel.org; amd-...@lists.freedesktop.org > Subject: Re: [PATCH 4/4] drm/amdgpu: resize VRAM BAR for CPU access > > On Wed, Mar 15, 2017 at 10:19 PM, Zhang, Jerry wrote: > >> -Original Message- > >> From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On > >> Behalf Of Christian K?nig > >> Sent: Wednesday, March 15, 2017 17:29 > >> To: Zhou, David(ChunMing); Ayyappa Ch > >> Cc: linux-...@vger.kernel.org; linux-kernel@vger.kernel.org; amd- > >> g...@lists.freedesktop.org; platform-driver-...@vger.kernel.org; > >> helg...@kernel.org; dri-de...@lists.freedesktop.org > >> Subject: Re: [PATCH 4/4] drm/amdgpu: resize VRAM BAR for CPU access > >> > >> Yes, exactly that. > > > > (I'm not familiar with PCI too much.) > > Is there any restrict for PCI device? > > I'm concerning if any PCI couldn't support it on some motherboard. > > It depends on the PCI root bridge. This patch set only implements support for > AMD root bridges. Intel and other vendors would need similar code. > > Alex > > > > >> > >> Christian. > >> > >> Am 15.03.2017 um 09:25 schrieb Zhou, David(ChunMing): > >> > Does that means we don't need invisible vram later? > >> > > >> > David > >> > > >> > -Original Message- > >> > From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On > >> > Behalf Of Christian K?nig > >> > Sent: Wednesday, March 15, 2017 3:38 PM > >> > To: Ayyappa Ch > >> > Cc: linux-...@vger.kernel.org; linux-kernel@vger.kernel.org; > >> > amd-...@lists.freedesktop.org; platform-driver-...@vger.kernel.org; > >> > helg...@kernel.org; dri-de...@lists.freedesktop.org > >> > Subject: Re: [PATCH 4/4] drm/amdgpu: resize VRAM BAR for CPU access > >> > > >> > Carizzo is an APU and resizing BARs isn't needed nor supported there. > >> > The CPU can access the full stolen VRAM directly on that hardware. > >> > > >> > As far as I know ASICs with support for this are Tonga, Fiji and all > >> > Polaris > variants. > >> > > >> > Christian. > >> > > >> > Am 15.03.2017 um 08:23 schrieb Ayyappa Ch: > >> >> Is it possible on Carrizo asics? Or only supports on newer asics? > >> >> > >> >> On Mon, Mar 13, 2017 at 6:11 PM, Christian König > >> >> wrote: > >> >>> From: Christian König > >> >>> > >> >>> Try to resize BAR0 to let CPU access all of VRAM. > >> >>> > >> >>> Signed-off-by: Christian König > >> >>> --- > >> >>>drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 + > >> >>>drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 29 > >> + > >> >>>drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 8 +--- > >> >>>drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 8 +--- > >> >>>4 files changed, 40 insertions(+), 6 deletions(-) > >> >>> > >> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h > >> >>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h > >> >>> index 3b81ded..905ded9 100644 > >> >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h > >> >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h > >> >>> @@ -1719,6 +1719,7 @@ uint64_t amdgpu_ttm_tt_pte_flags(struct > >> amdgpu_device *adev, struct ttm_tt *ttm, > >> >>>struct ttm_mem_reg *mem); > >> >>>void amdgpu_vram_location(struct amdgpu_device *adev, struct > >> amdgpu_mc *mc, u64 base); > >> >>>void amdgpu_gtt_location(struct amdgpu_device *adev, struct > >> >>> amdgpu_mc *mc); > >> >>> +void amdgpu_resize_bar0(struct amdgpu_device *adev); > >> >>>void amdgpu_ttm_set_active_vram_size
RE: [PATCH 4/4] drm/amdgpu: resize VRAM BAR for CPU access
> -Original Message-
> From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On Behalf Of
> Christian K?nig
> Sent: Wednesday, March 15, 2017 17:29
> To: Zhou, David(ChunMing); Ayyappa Ch
> Cc: linux-...@vger.kernel.org; linux-kernel@vger.kernel.org; amd-
> g...@lists.freedesktop.org; platform-driver-...@vger.kernel.org;
> helg...@kernel.org; dri-de...@lists.freedesktop.org
> Subject: Re: [PATCH 4/4] drm/amdgpu: resize VRAM BAR for CPU access
>
> Yes, exactly that.
(I'm not familiar with PCI too much.)
Is there any restrict for PCI device?
I'm concerning if any PCI couldn't support it on some motherboard.
>
> Christian.
>
> Am 15.03.2017 um 09:25 schrieb Zhou, David(ChunMing):
> > Does that means we don't need invisible vram later?
> >
> > David
> >
> > -Original Message-
> > From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On
> > Behalf Of Christian K?nig
> > Sent: Wednesday, March 15, 2017 3:38 PM
> > To: Ayyappa Ch
> > Cc: linux-...@vger.kernel.org; linux-kernel@vger.kernel.org;
> > amd-...@lists.freedesktop.org; platform-driver-...@vger.kernel.org;
> > helg...@kernel.org; dri-de...@lists.freedesktop.org
> > Subject: Re: [PATCH 4/4] drm/amdgpu: resize VRAM BAR for CPU access
> >
> > Carizzo is an APU and resizing BARs isn't needed nor supported there.
> > The CPU can access the full stolen VRAM directly on that hardware.
> >
> > As far as I know ASICs with support for this are Tonga, Fiji and all
> > Polaris variants.
> >
> > Christian.
> >
> > Am 15.03.2017 um 08:23 schrieb Ayyappa Ch:
> >> Is it possible on Carrizo asics? Or only supports on newer asics?
> >>
> >> On Mon, Mar 13, 2017 at 6:11 PM, Christian König
> >> wrote:
> >>> From: Christian König
> >>>
> >>> Try to resize BAR0 to let CPU access all of VRAM.
> >>>
> >>> Signed-off-by: Christian König
> >>> ---
> >>>drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 +
> >>>drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 29
> +
> >>>drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 8 +---
> >>>drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 8 +---
> >>>4 files changed, 40 insertions(+), 6 deletions(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> >>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> >>> index 3b81ded..905ded9 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> >>> @@ -1719,6 +1719,7 @@ uint64_t amdgpu_ttm_tt_pte_flags(struct
> amdgpu_device *adev, struct ttm_tt *ttm,
> >>>struct ttm_mem_reg *mem);
> >>>void amdgpu_vram_location(struct amdgpu_device *adev, struct
> amdgpu_mc *mc, u64 base);
> >>>void amdgpu_gtt_location(struct amdgpu_device *adev, struct
> >>> amdgpu_mc *mc);
> >>> +void amdgpu_resize_bar0(struct amdgpu_device *adev);
> >>>void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev,
> u64 size);
> >>>int amdgpu_ttm_init(struct amdgpu_device *adev);
> >>>void amdgpu_ttm_fini(struct amdgpu_device *adev); diff --git
> >>> a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> >>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> >>> index 118f4e6..92955fe 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> >>> @@ -692,6 +692,35 @@ void amdgpu_gtt_location(struct amdgpu_device
> *adev, struct amdgpu_mc *mc)
> >>> mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
> >>>}
> >>>
> >>> +/**
> >>> + * amdgpu_resize_bar0 - try to resize BAR0
> >>> + *
> >>> + * @adev: amdgpu_device pointer
> >>> + *
> >>> + * Try to resize BAR0 to make all VRAM CPU accessible.
> >>> + */
> >>> +void amdgpu_resize_bar0(struct amdgpu_device *adev) {
> >>> + u32 size = max(ilog2(adev->mc.real_vram_size - 1) + 1, 20) - 20;
> >>> + int r;
> >>> +
> >>> + r = pci_resize_resource(adev->pdev, 0, size);
> >>> +
> >>> + if (r == -ENOTSUPP) {
> >>> + /* The hardware don't support the extension. */
> >>> + return;
> >>> +
> >>> + } else if (r == -ENOSPC) {
> >>> + DRM_INFO("Not enoigh PCI address space for a large BAR.");
> >>> + } else if (r) {
> >>> + DRM_ERROR("Problem resizing BAR0 (%d).", r);
> >>> + }
> >>> +
> >>> + /* Reinit the doorbell mapping, it is most likely moved as well */
> >>> + amdgpu_doorbell_fini(adev);
> >>> + BUG_ON(amdgpu_doorbell_init(adev));
> >>> +}
> >>> +
> >>>/*
> >>> * GPU helpers function.
> >>> */
> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> >>> b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> >>> index dc9b6d6..36a7aa5 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> >>> @@ -367,13 +367,15 @@ static int gmc_v7_0_mc_init(struct amdgpu_device
> *adev)
> >>> break;
> >>> }
> >>> adev->mc.vram_width =
RE: [PATCH 5/5] drm/amd/amdgpu : Remove unused variable
Reviewed-by: Junwei Zhang
Regards,
Jerry (Junwei Zhang)
SRDC SW Development
AMD Shanghai
_
> -Original Message-
> From: Muhammad Falak R Wani [mailto:falakre...@gmail.com]
> Sent: Tuesday, May 17, 2016 5:43 PM
> To: David Airlie
> Cc: Deucher, Alexander; Koenig, Christian; Zhou, Jammy; Dave Airlie; StDenis,
> Tom; Yang, Young; Zhang, Jerry; dri-de...@lists.freedesktop.org; linux-
> ker...@vger.kernel.org
> Subject: [PATCH 5/5] drm/amd/amdgpu : Remove unused variable
>
> Remove unused variable 'ret', and directly return 0.
>
> Signed-off-by: Muhammad Falak R Wani
> ---
> drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> index 55cdab8..cba951a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> @@ -99,7 +99,6 @@ static void tonga_ih_disable_interrupts(struct
> amdgpu_device *adev)
> */
> static int tonga_ih_irq_init(struct amdgpu_device *adev) {
> - int ret = 0;
> int rb_bufsz;
> u32 interrupt_cntl, ih_rb_cntl, ih_doorbell_rtpr;
> u64 wptr_off;
> @@ -165,7 +164,7 @@ static int tonga_ih_irq_init(struct amdgpu_device *adev)
> /* enable interrupts */
> tonga_ih_enable_interrupts(adev);
>
> - return ret;
> + return 0;
> }
>
> /**
> --
> 1.9.1
