[PATCH v3 4/5] arch/arm64: dts: add support for Marvell CP110 UTMI PHY
From: Konstantin Porotchkin
Add support for Marvell CP110 UTMI PHY in a CP11x DTSI
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
index 64179a372ecf..49f9d2cd8619 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
@@ -285,6 +285,25 @@
};
};
+ CP11X_LABEL(utmi): utmi@58 {
+ compatible = "marvell,cp110-utmi-phy";
+ reg = <0x58 0x2000>;
+ marvell,system-controller = <_LABEL(syscon0)>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ CP11X_LABEL(utmi0): usb-phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+
+ CP11X_LABEL(utmi1): usb-phy@1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ };
+ };
+
CP11X_LABEL(usb3_0): usb@50 {
compatible = "marvell,armada-8k-xhci",
"generic-xhci";
--
2.17.1
[PATCH v3 5/5] arch/arm64: dts: enable CP110 UTMI PHY usage
From: Konstantin Porotchkin
Enable support for CP110 UTMI PHY in Armada SoC family platform
device trees.
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/armada-7040-db.dts | 14 +
arch/arm64/boot/dts/marvell/armada-8040-db.dts | 21 ++--
arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi | 19 --
arch/arm64/boot/dts/marvell/cn9130-db.dts | 12 +--
arch/arm64/boot/dts/marvell/cn9131-db.dts | 9 +++--
arch/arm64/boot/dts/marvell/cn9132-db.dts | 11 --
6 files changed, 72 insertions(+), 14 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-7040-db.dts
b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
index a7eb4e7697a2..51f3e2907597 100644
--- a/arch/arm64/boot/dts/marvell/armada-7040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
@@ -218,6 +218,10 @@
};
};
+_utmi {
+ status = "okay";
+};
+
_comphy1 {
cp0_usbh0_con: connector {
compatible = "usb-a-connector";
@@ -226,8 +230,9 @@
};
_usb3_0 {
- phys = <_comphy1 0>;
- phy-names = "cp0-usb3h0-comphy";
+ phys = <_comphy1 0>, <_utmi0>;
+ phy-names = "cp0-usb3h0-comphy", "utmi";
+ dr_mode = "host";
status = "okay";
};
@@ -239,8 +244,9 @@
};
_usb3_1 {
- phys = <_comphy4 1>;
- phy-names = "cp0-usb3h1-comphy";
+ phys = <_comphy4 1>, <_utmi1>;
+ phy-names = "cp0-usb3h1-comphy", "utmi";
+ dr_mode = "host";
status = "okay";
};
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts
b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
index 09fb5256f1db..e39e1efc95b6 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
@@ -154,8 +154,15 @@
};
/* CON9 on CP0 expansion */
+_utmi {
+ status = "okay";
+};
+
_usb3_0 {
usb-phy = <_usb3_0_phy>;
+ phys = <_utmi0>;
+ phy-names = "utmi";
+ dr_mode = "host";
status = "okay";
};
@@ -168,8 +175,9 @@
/* CON10 on CP0 expansion */
_usb3_1 {
- phys = <_comphy4 1>;
- phy-names = "cp0-usb3h1-comphy";
+ phys = <_comphy4 1>, <_utmi1>;
+ phy-names = "usb", "utmi";
+ dr_mode = "host";
status = "okay";
};
@@ -306,14 +314,23 @@
};
};
+_utmi {
+ status = "okay";
+};
+
/* CON9 on CP1 expansion */
_usb3_0 {
usb-phy = <_usb3_0_phy>;
+ phys = <_utmi0>;
+ phy-names = "utmi";
+ dr_mode = "host";
status = "okay";
};
/* CON10 on CP1 expansion */
_usb3_1 {
+ phys = <_utmi1>;
+ phy-names = "utmi";
status = "okay";
};
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
index cbcb210cb6d8..adbfecc678b5 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
@@ -259,13 +259,23 @@
vqmmc-supply = <_3_3>;
};
+_utmi {
+ status = "okay";
+};
+
_usb3_0 {
/* J38? - USB2.0 only */
+ phys = <_utmi0>;
+ phy-names = "utmi";
+ dr_mode = "host";
status = "okay";
};
_usb3_1 {
/* J38? - USB2.0 only */
+ phys = <_utmi1>;
+ phy-names = "utmi";
+ dr_mode = "host";
status = "okay";
};
@@ -364,9 +374,14 @@
};
};
+_utmi {
+ status = "okay";
+};
+
_usb3_0 {
/* CPS Lane 2 - CON7 */
- phys = <_comphy2 0>;
- phy-names = "cp1-usb3h0-comphy";
+ phys = <_comphy2 0>, <_utmi0>;
+ phy-names = "cp1-usb3h0-comphy", "utmi";
+ dr_mode = "host";
status = "okay";
};
diff --git a/arch/arm64/boot/dts/marvell/cn9130-db.dts
b/arch/arm64/boot/dts/marvell/cn9130-db.dts
index 79020e6d2792..2c2af001619b 100644
--- a/arch/arm64/boot/dts/marvell/cn9130-db.dts
+++ b/arch/arm64/boot/dts/marvell/cn9130-db.dts
@@ -392,14 +392,22 @@
};
};
+_utmi {
+ status = "okay";
+};
+
_usb3_0 {
status = "okay";
usb-phy = <_usb3_0_phy0>;
- phy-names = "usb";
+ phys = <_utmi0>;
+ phy-names = "utmi";
+ dr_mode = "host";
};
_usb3_1 {
status = "okay";
usb-phy = <_usb3_0_phy1>;
- phy-names = "usb";
+ phys = <_utmi1>;
+ phy-names = "utmi";
+ dr_mode = "host";
};
diff --git a/arch/arm64/boot/dts/marvell/cn9131-db.dts
b/arch/arm64/boot/dts/marvell/cn9131-db.dts
index 3c975f98b2a3..ba2d4e1da159 100644
--- a/arch/arm64/boot/dts/marvell/cn9131-db.dts
+++ b/arch/arm64/boot/dts/marvell/cn9131-db.dts
@@ -193,10 +193,15 @@
};
/* CON58 */
+_utmi {
+ status = "okay";
+};
+
_usb3_1 {
status = "okay";
usb-phy = <_usb3_0_phy0>;
/* Generic PHY, providing serdes lanes */
- phys = <_comphy3 1>;
- phy-names = "usb";
+ phys = <_comphy3 1>, <_utmi1>;
+ phy-names = "usb", "utmi";
+ dr_mode =
[PATCH v3 2/5] dt-bindings: phy: convert phy-mvebu-utmi to YAML schema
From: Konstantin Porotchkin
The new file name is marvell,armada-3700-utmi-phy.yaml
Signed-off-by: Konstantin Porotchkin
---
Documentation/devicetree/bindings/phy/marvell,armada-3700-utmi-phy.yaml | 57
Documentation/devicetree/bindings/phy/phy-mvebu-utmi.txt| 38
-
2 files changed, 57 insertions(+), 38 deletions(-)
create mode 100644
Documentation/devicetree/bindings/phy/marvell,armada-3700-utmi-phy.yaml
delete mode 100644 Documentation/devicetree/bindings/phy/phy-mvebu-utmi.txt
diff --git
a/Documentation/devicetree/bindings/phy/marvell,armada-3700-utmi-phy.yaml
b/Documentation/devicetree/bindings/phy/marvell,armada-3700-utmi-phy.yaml
new file mode 100644
index ..2437c3683326
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/marvell,armada-3700-utmi-phy.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/phy/marvell,armada-3700-utmi-phy.yaml#;
+$schema: "http://devicetree.org/meta-schemas/core.yaml#;
+
+title: Marvell Armada UTMI/UTMI+ PHY
+
+maintainers:
+ - Miquel Raynal
+
+description:
+ On Armada 3700, there are two USB controllers, one is compatible with
+ the USB2 and USB3 specifications and supports OTG. The other one is USB2
+ compliant and only supports host mode. Both of these controllers come with
+ a slightly different UTMI PHY.
+
+properties:
+ compatible:
+enum:
+ - marvell,a3700-utmi-host-phy
+ - marvell,a3700-utmi-otg-phy
+ reg:
+maxItems: 1
+
+ "#phy-cells":
+const: 0
+
+ marvell,usb-misc-reg:
+description:
+ Phandle on the "USB miscellaneous registers" shared region
+ covering registers related to both the host controller and
+ the PHY.
+$ref: /schemas/types.yaml#/definitions/phandle
+
+required:
+ - compatible
+ - reg
+ - "#phy-cells"
+ - marvell,usb-misc-reg
+
+additionalProperties: false
+
+examples:
+ - |
+usb2_utmi_host_phy: phy@5f000 {
+ compatible = "marvell,armada-3700-utmi-host-phy";
+ reg = <0x5f000 0x800>;
+ marvell,usb-misc-reg = <_syscon>;
+ #phy-cells = <0>;
+};
+
+usb2_syscon: system-controller@5f800 {
+ compatible = "marvell,armada-3700-usb2-host-misc", "syscon";
+ reg = <0x5f800 0x800>;
+};
diff --git a/Documentation/devicetree/bindings/phy/phy-mvebu-utmi.txt
b/Documentation/devicetree/bindings/phy/phy-mvebu-utmi.txt
deleted file mode 100644
index aa99ceec73b0..
--- a/Documentation/devicetree/bindings/phy/phy-mvebu-utmi.txt
+++ /dev/null
@@ -1,38 +0,0 @@
-MVEBU A3700 UTMI PHY
-
-
-USB2 UTMI+ PHY controllers can be found on the following Marvell MVEBU SoCs:
-* Armada 3700
-
-On Armada 3700, there are two USB controllers, one is compatible with the USB2
-and USB3 specifications and supports OTG. The other one is USB2 compliant and
-only supports host mode. Both of these controllers come with a slightly
-different UTMI PHY.
-
-Required Properties:
-
-- compatible: Should be one of:
- * "marvell,a3700-utmi-host-phy" for the PHY connected to
- the USB2 host-only controller.
- * "marvell,a3700-utmi-otg-phy" for the PHY connected to
- the USB3 and USB2 OTG capable controller.
-- reg: PHY IP register range.
-- marvell,usb-misc-reg: handle on the "USB miscellaneous registers" shared
- region covering registers related to both the host
- controller and the PHY.
-- #phy-cells: Standard property (Documentation: phy-bindings.txt) Should be 0.
-
-
-Example:
-
- usb2_utmi_host_phy: phy@5f000 {
- compatible = "marvell,armada-3700-utmi-host-phy";
- reg = <0x5f000 0x800>;
- marvell,usb-misc-reg = <_syscon>;
- #phy-cells = <0>;
- };
-
- usb2_syscon: system-controller@5f800 {
- compatible = "marvell,armada-3700-usb2-host-misc", "syscon";
- reg = <0x5f800 0x800>;
- };
--
2.17.1
[PATCH v3 4/5] arch/arm64: dts: add support for Marvell CP110 UTMI driver
From: Konstantin Porotchkin
Add support for Marvell CP110 UTMI PHY in a common DTSI
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
index 64179a372ecf..49f9d2cd8619 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
@@ -285,6 +285,25 @@
};
};
+ CP11X_LABEL(utmi): utmi@58 {
+ compatible = "marvell,cp110-utmi-phy";
+ reg = <0x58 0x2000>;
+ marvell,system-controller = <_LABEL(syscon0)>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ CP11X_LABEL(utmi0): usb-phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+
+ CP11X_LABEL(utmi1): usb-phy@1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ };
+ };
+
CP11X_LABEL(usb3_0): usb@50 {
compatible = "marvell,armada-8k-xhci",
"generic-xhci";
--
2.17.1
[PATCH v3 3/5] devicetree/bindings: add support for CP110 UTMI PHY
From: Konstantin Porotchkin
Add DTS binding for Marvell CP110 UTMI PHY
Signed-off-by: Konstantin Porotchkin
---
Documentation/devicetree/bindings/phy/marvell,armada-cp110-utmi-phy.yaml | 109
1 file changed, 109 insertions(+)
create mode 100644
Documentation/devicetree/bindings/phy/marvell,armada-cp110-utmi-phy.yaml
diff --git
a/Documentation/devicetree/bindings/phy/marvell,armada-cp110-utmi-phy.yaml
b/Documentation/devicetree/bindings/phy/marvell,armada-cp110-utmi-phy.yaml
new file mode 100644
index ..30f3b5f32a95
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/marvell,armada-cp110-utmi-phy.yaml
@@ -0,0 +1,109 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/phy/marvell,armada-cp110-utmi-phy.yaml#;
+$schema: "http://devicetree.org/meta-schemas/core.yaml#;
+
+title: Marvell Armada CP110/CP115 UTMI PHY
+
+maintainers:
+ - Konstantin Porotchkin
+
+description:
+ On Armada 7k/8k and CN913x, there are two host and one device USB
controllers.
+ Each of two exiting UTMI PHYs could be connected to either USB host or USB
device
+ controller.
+ The USB device controller can only be connected to a single UTMI PHY port
+ 0.H- USB HOST0
+ UTMI PHY0 /
+ 0.D-0
+ \-- USB DEVICE
+ 1.D-1
+ UTMI PHY1 \
+ 1.H- USB HOST1
+
+properties:
+ compatible:
+const: marvell,cp110-utmi-phy
+
+ reg:
+maxItems: 1
+
+ "#address-cells":
+const: 1
+
+ "#size-cells":
+const: 0
+
+ marvell,system-controller:
+description:
+ Phandle to the system controller node
+$ref: /schemas/types.yaml#/definitions/phandle
+
+#Required child nodes:
+
+patternProperties:
+ "^usb-phy@[0|1]$":
+type: object
+description:
+ Each UTMI PHY port must be represented as a sub-node.
+
+properties:
+ reg:
+description: phy port index.
+maxItems: 1
+
+ "#phy-cells":
+const: 0
+
+required:
+ - reg
+ - "#phy-cells"
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - "#address-cells"
+ - "#size-cells"
+ - marvell,system-controller
+
+additionalProperties: false
+
+examples:
+ - |
+cp0_utmi: utmi@58 {
+ compatible = "marvell,cp110-utmi-phy";
+ reg = <0x58 0x2000>;
+ marvell,system-controller = <_syscon0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cp0_utmi0: usb-phy@0 {
+reg = <0>;
+#phy-cells = <0>;
+ };
+
+ cp0_utmi1: usb-phy@1 {
+reg = <1>;
+#phy-cells = <0>;
+ };
+};
+
+cp0_usb3_0 {
+ usb-phy = <_usb3_0_phy0>;
+ phys = <_utmi0>;
+ phy-names = "utmi";
+ /* UTMI0 is connected to USB host controller (default mode) */
+ dr_mode = "host";
+};
+
+cp0_usb3_1 {
+ usb-phy = <_usb3_0_phy1>;
+ phys = <_utmi1>;
+ phy-names = "utmi";
+ /* UTMI1 is connected to USB device controller */
+ dr_mode = "peripheral";
+};
--
2.17.1
[PATCH v3 0/5] Add support for CP110 UTMI PHY
From: Konstantin Porotchkin This series of patches adds a new PHY driver for supporting CP110 UTMI PHY in Linux. Currently the functionality of USB ports connected to this PHY depends on boot loader setup. The new driver eliminates kernel configuration dependency from the boot loader. v3: - rebase on top of Linux 5.12-rc2 - convert Armada 3700 UTMI PHY DT binding document to YAML schema - create a separate DT binding for Armada CP11x UTMI PHY in YAML format - change UTMI PHY port node names from "phy" to "usb-phy" v2: - extend the comment about reference clock - fix driver probe function, add some prints - move to usage of dr_mode from connected USB controller instead of dedicated device tree property Konstantin Porotchkin (5): drivers: phy: add support for Armada CP110 UTMI PHY dt-bindings: phy: convert phy-mvebu-utmi to YAML schema devicetree/bindings: add support for CP110 UTMI PHY arch/arm64: dts: add support for Marvell CP110 UTMI PHY arch/arm64: dts: enable CP110 UTMI PHY usage .../phy/marvell,armada-3700-utmi-phy.yaml | 57 +++ .../phy/marvell,armada-cp110-utmi-phy.yaml| 109 + .../bindings/phy/phy-mvebu-utmi.txt | 38 -- .../arm64/boot/dts/marvell/armada-7040-db.dts | 14 +- .../arm64/boot/dts/marvell/armada-8040-db.dts | 21 +- .../boot/dts/marvell/armada-8040-mcbin.dtsi | 19 +- arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 19 + arch/arm64/boot/dts/marvell/cn9130-db.dts | 12 +- arch/arm64/boot/dts/marvell/cn9131-db.dts | 9 +- arch/arm64/boot/dts/marvell/cn9132-db.dts | 11 +- drivers/phy/marvell/Kconfig | 8 + drivers/phy/marvell/Makefile | 1 + drivers/phy/marvell/phy-mvebu-cp110-utmi.c| 384 ++ 13 files changed, 650 insertions(+), 52 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/marvell,armada-3700-utmi-phy.yaml create mode 100644 Documentation/devicetree/bindings/phy/marvell,armada-cp110-utmi-phy.yaml delete mode 100644 Documentation/devicetree/bindings/phy/phy-mvebu-utmi.txt create mode 100644 drivers/phy/marvell/phy-mvebu-cp110-utmi.c -- 2.17.1
[PATCH v3 1/5] drivers: phy: add support for Armada CP110 UTMI PHY
From: Konstantin Porotchkin Add support for Marvell CP110 UTMI PHY driver allowing the USB2 port configuration independently from the boot loader setup. The CP110/CP115 dies have 2 UTMI PHYs that could be connected to two USB host controllers or to single USB device controller. Since there is only one USB device controller on die, only one of the UTMI PHYs could work in USB device mode. The CONFIG_PHY_MVEBU_CP110_UTMI should be enabled for usage of this driver. Signed-off-by: Konstantin Porotchkin --- drivers/phy/marvell/Kconfig| 8 + drivers/phy/marvell/Makefile | 1 + drivers/phy/marvell/phy-mvebu-cp110-utmi.c | 384 3 files changed, 393 insertions(+) create mode 100644 drivers/phy/marvell/phy-mvebu-cp110-utmi.c diff --git a/drivers/phy/marvell/Kconfig b/drivers/phy/marvell/Kconfig index 6c96f2bf5266..9208839019bd 100644 --- a/drivers/phy/marvell/Kconfig +++ b/drivers/phy/marvell/Kconfig @@ -67,6 +67,14 @@ config PHY_MVEBU_CP110_COMPHY lanes can be used by various controllers (Ethernet, sata, usb, PCIe...). +config PHY_MVEBU_CP110_UTMI + tristate "Marvell CP110 UTMI driver" + depends on ARCH_MVEBU || COMPILE_TEST + depends on OF + select GENERIC_PHY + help + Enable this to support Marvell CP110 UTMI PHY driver. + config PHY_MVEBU_SATA def_bool y depends on ARCH_DOVE || MACH_DOVE || MACH_KIRKWOOD diff --git a/drivers/phy/marvell/Makefile b/drivers/phy/marvell/Makefile index 7f296ef02829..90862c4daa26 100644 --- a/drivers/phy/marvell/Makefile +++ b/drivers/phy/marvell/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_PHY_MVEBU_A3700_COMPHY)+= phy-mvebu-a3700-comphy.o obj-$(CONFIG_PHY_MVEBU_A3700_UTMI) += phy-mvebu-a3700-utmi.o obj-$(CONFIG_PHY_MVEBU_A38X_COMPHY)+= phy-armada38x-comphy.o obj-$(CONFIG_PHY_MVEBU_CP110_COMPHY) += phy-mvebu-cp110-comphy.o +obj-$(CONFIG_PHY_MVEBU_CP110_UTMI) += phy-mvebu-cp110-utmi.o obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o obj-$(CONFIG_PHY_PXA_28NM_HSIC)+= phy-pxa-28nm-hsic.o obj-$(CONFIG_PHY_PXA_28NM_USB2)+= phy-pxa-28nm-usb2.o diff --git a/drivers/phy/marvell/phy-mvebu-cp110-utmi.c b/drivers/phy/marvell/phy-mvebu-cp110-utmi.c new file mode 100644 index ..08d178a4dc13 --- /dev/null +++ b/drivers/phy/marvell/phy-mvebu-cp110-utmi.c @@ -0,0 +1,384 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Marvell + * + * Authors: + * Konstantin Porotchkin + * + * Marvell CP110 UTMI PHY driver + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define UTMI_PHY_PORTS 2 + +/* CP110 UTMI register macro definetions */ +#define SYSCON_USB_CFG_REG 0x420 +#define USB_CFG_DEVICE_EN_MASK BIT(0) +#define USB_CFG_DEVICE_MUX_OFFSET1 +#define USB_CFG_DEVICE_MUX_MASK BIT(1) +#define USB_CFG_PLL_MASK BIT(25) + +#define SYSCON_UTMI_CFG_REG(id)(0x440 + (id) * 4) +#define UTMI_PHY_CFG_PU_MASK BIT(5) + +#define UTMI_PLL_CTRL_REG 0x0 +#define PLL_REFDIV_OFFSET0 +#define PLL_REFDIV_MASK GENMASK(6, 0) +#define PLL_REFDIV_VAL 0x5 +#define PLL_FBDIV_OFFSET 16 +#define PLL_FBDIV_MASK GENMASK(24, 16) +#define PLL_FBDIV_VAL0x60 +#define PLL_SEL_LPFR_MASKGENMASK(29, 28) +#define PLL_RDY BIT(31) +#define UTMI_CAL_CTRL_REG 0x8 +#define IMPCAL_VTH_OFFSET8 +#define IMPCAL_VTH_MASK GENMASK(10, 8) +#define IMPCAL_VTH_VAL 0x7 +#define IMPCAL_DONE BIT(23) +#define PLLCAL_DONE BIT(31) +#define UTMI_TX_CH_CTRL_REG0xC +#define DRV_EN_LS_OFFSET 12 +#define DRV_EN_LS_MASK GENMASK(15, 12) +#define IMP_SEL_LS_OFFSET16 +#define IMP_SEL_LS_MASK GENMASK(19, 16) +#define TX_AMP_OFFSET20 +#define TX_AMP_MASK GENMASK(22, 20) +#define TX_AMP_VAL 0x4 +#define UTMI_RX_CH_CTRL0_REG 0x14 +#define SQ_DET_ENBIT(15) +#define SQ_ANA_DTC_SEL BIT(28) +#define UTMI_RX_CH_CTRL1_REG 0x18 +#define SQ_AMP_CAL_OFFSET0 +#define SQ_AMP_CAL_MASK GENMASK(2, 0) +#define SQ_AMP_CAL_VAL 1 +#define SQ_AMP_CAL_ENBIT(3) +#define UTMI_CTRL_STATUS0_REG
[PATCH 2/2] drivers/pinctrl: armada-cp110 - fix MPP54/MPP55 functions
From: Konstantin Porotchkin
The function name is used for selecting MPP functionality and
should be unique within function names of the same pin.
This patch fixes function names for MPP54 and MPP55 that
have two different functions named the same.
Signed-off-by: Konstantin Porotchkin
---
drivers/pinctrl/mvebu/pinctrl-armada-cp110.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-cp110.c
b/drivers/pinctrl/mvebu/pinctrl-armada-cp110.c
index 17491b27e487..8ba8f3e9121f 100644
--- a/drivers/pinctrl/mvebu/pinctrl-armada-cp110.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-cp110.c
@@ -519,13 +519,13 @@ static struct mvebu_mpp_mode armada_cp110_mpp_modes[] = {
MPP_FUNCTION(4,"synce1", "clk"),
MPP_FUNCTION(8,"led", "data"),
MPP_FUNCTION(10, "sdio", "hw_rst"),
-MPP_FUNCTION(11, "sdio", "wr_protect")),
+MPP_FUNCTION(11, "sdio_wp", "wr_protect")),
MPP_MODE(55,
MPP_FUNCTION(0,"gpio", NULL),
MPP_FUNCTION(1,"ge1", "rxctl_rxdv"),
MPP_FUNCTION(3,"ptp", "pulse"),
MPP_FUNCTION(10, "sdio", "led"),
-MPP_FUNCTION(11, "sdio", "card_detect")),
+MPP_FUNCTION(11, "sdio_cd", "card_detect")),
MPP_MODE(56,
MPP_FUNCTION(0,"gpio", NULL),
MPP_FUNCTION(4,"tdm", "drx"),
--
2.17.1
[PATCH 0/2] Fix Marvell CP110 pin control finction names
From: Konstantin Porotchkin These patches are fixing the CP110 pin control driver and the related documentation. Current CP110 pin control driver uses two different MPP functions named the same (sdio) in MPP54 and MPP55 definitions. Since these names are used for the MPP functionality selection, all function names within single MPP group should be unique. This patches series fixes function names in MPP54 and MPP55 pin definitions. Konstantin Porotchkin (2): doc: cp110-system-controller: fix the pin function names drivers/pinctrl: armada-cp110 - fix MPP54/MPP55 functions .../bindings/arm/marvell/cp110-system-controller.txt | 4 ++-- drivers/pinctrl/mvebu/pinctrl-armada-cp110.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) -- 2.17.1
[PATCH 1/2] doc: cp110-system-controller: fix the pin function names
From: Konstantin Porotchkin Fix the pin function names for MPP54 and MPP55. Signed-off-by: Konstantin Porotchkin --- Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt b/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt index a21f7709596c..0705e765f432 100644 --- a/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt +++ b/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt @@ -142,8 +142,8 @@ mpp50 50 gpio, ge1(rxclk), mss_i2c(sda), spi1(csn0), uart2(txd), uart0(rxd), xg( mpp51 51 gpio, ge1(rxd0), mss_i2c(sck), spi1(csn1), uart2(rxd), uart0(cts), sdio(pwr10) mpp52 52 gpio, ge1(rxd1), synce1(clk), synce2(clk), spi1(csn2), uart1(cts), led(clk), pcie(rstoutn), pcie0(clkreq) mpp53 53 gpio, ge1(rxd2), ptp(clk), spi1(csn3), uart1(rxd), led(stb), sdio(led) -mpp54 54 gpio, ge1(rxd3), synce2(clk), ptp(pclk_out), synce1(clk), led(data), sdio(hw_rst), sdio(wr_protect) -mpp55 55 gpio, ge1(rxctl_rxdv), ptp(pulse), sdio(led), sdio(card_detect) +mpp54 54 gpio, ge1(rxd3), synce2(clk), ptp(pclk_out), synce1(clk), led(data), sdio(hw_rst), sdio_wp(wr_protect) +mpp55 55 gpio, ge1(rxctl_rxdv), ptp(pulse), sdio(led), sdio_cd(card_detect) mpp56 56 gpio, tdm(drx), au(i2sdo_spdifo), spi0(clk), uart1(rxd), sata1(present_act), sdio(clk) mpp57 57 gpio, mss_i2c(sda), ptp(pclk_out), tdm(intn), au(i2sbclk), spi0(mosi), uart1(txd), sata0(present_act), sdio(cmd) mpp58 58 gpio, mss_i2c(sck), ptp(clk), tdm(rstn), au(i2sdi), spi0(miso), uart1(cts), led(clk), sdio(d0) -- 2.17.1
[PATCH v2 2/4] devicetree/bindings: add support for CP110 UTMI driver
From: Konstantin Porotchkin
Add DTS binding for Marvell CP110 UTMI driver
Signed-off-by: Konstantin Porotchkin
---
Documentation/devicetree/bindings/phy/phy-mvebu-utmi.txt | 78
++--
1 file changed, 72 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/phy-mvebu-utmi.txt
b/Documentation/devicetree/bindings/phy/phy-mvebu-utmi.txt
index aa99ceec73b0..b66066249861 100644
--- a/Documentation/devicetree/bindings/phy/phy-mvebu-utmi.txt
+++ b/Documentation/devicetree/bindings/phy/phy-mvebu-utmi.txt
@@ -1,30 +1,56 @@
-MVEBU A3700 UTMI PHY
-
+MVEBU UTMI PHY
+---
USB2 UTMI+ PHY controllers can be found on the following Marvell MVEBU SoCs:
* Armada 3700
+* Armada 7k/8k (on the CP110)
+* Armada CN913x (on the CP115)
On Armada 3700, there are two USB controllers, one is compatible with the USB2
and USB3 specifications and supports OTG. The other one is USB2 compliant and
only supports host mode. Both of these controllers come with a slightly
different UTMI PHY.
+On Armada 7k/8k and CN913x, there are two host and one device USB controllers.
+Each of two exiting UTMI PHYs could be connected to either USB host or USB
device
+controller.
+The USB device controller can only be connected to a single UTMI PHY port:
+0.H- USB HOST0
+UTMI PHY0 /
+0.D-0
+ \-- USB DEVICE
+1.D-1
+UTMI PHY1 \
+1.H- USB HOST1
+
+
Required Properties:
- compatible: Should be one of:
* "marvell,a3700-utmi-host-phy" for the PHY connected to
- the USB2 host-only controller.
+ the USB2 host-only controller (for Armada3700 only).
* "marvell,a3700-utmi-otg-phy" for the PHY connected to
- the USB3 and USB2 OTG capable controller.
+ the USB3 and USB2 OTG capable controller (for Armada3700 only.
+ * "marvell,cp110-utmi-phy" (for Armada 7k/8k or CN913x only).
- reg: PHY IP register range.
- marvell,usb-misc-reg: handle on the "USB miscellaneous registers" shared
region covering registers related to both the host
- controller and the PHY.
-- #phy-cells: Standard property (Documentation: phy-bindings.txt) Should be 0.
+ controller and the PHY (for Armada3700 only).
+- marvell,system-controller: should contain a phandle to the system
+controller node (for Armada 7k/8k or CN913x only)
+- #phy-cells: Standard property (Documentation: phy-bindings.txt.
+ Should be 0 (for Armada3700 only).
+
+
+Required properties (child nodes, for Armada 7k/8k/CN913x only):
+
+- reg: UTMI PHY port ID (0 or 1).
+- #phy-cells : Should be 0.
Example:
+Armada3700
usb2_utmi_host_phy: phy@5f000 {
compatible = "marvell,armada-3700-utmi-host-phy";
reg = <0x5f000 0x800>;
@@ -36,3 +62,43 @@ Example:
compatible = "marvell,armada-3700-usb2-host-misc", "syscon";
reg = <0x5f800 0x800>;
};
+
+Armada 7k/8k/CN913x
+
+ cp0_utmi: utmi@58 {
+ compatible = "marvell,cp110-utmi-phy";
+ reg = <0x58 0x2000>;
+ marvell,system-controller = <_syscon0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ cp0_utmi0: phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+
+ cp0_utmi1: phy@1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ };
+ };
+
+ cp0_usb3_0 {
+ status = "okay";
+ usb-phy = <_usb3_0_phy0>;
+ phys = <_utmi0>;
+ phy-names = "utmi";
+ /* UTMI0 is connected to USB host controller (default mode) */
+ dr_mode = "host";
+ };
+
+ cp0_usb3_1 {
+ status = "okay";
+ usb-phy = <_usb3_0_phy1>;
+ phys = <_utmi1>;
+ phy-names = "utmi";
+ /* UTMI1 is connected to USB device controller */
+ dr_mode = "peripheral";
+ };
+
--
2.17.1
[PATCH v2 4/4] arch/arm64: dts: enable CP110 UTMI driver
From: Konstantin Porotchkin
Enable support for CP110 UTMI driver in Armada SoC family platform
device trees.
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/armada-7040-db.dts | 14 +
arch/arm64/boot/dts/marvell/armada-8040-db.dts | 21 ++--
arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi | 19 --
arch/arm64/boot/dts/marvell/cn9130-db.dts | 12 +--
arch/arm64/boot/dts/marvell/cn9131-db.dts | 9 +++--
arch/arm64/boot/dts/marvell/cn9132-db.dts | 11 --
6 files changed, 72 insertions(+), 14 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-7040-db.dts
b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
index a7eb4e7697a2..51f3e2907597 100644
--- a/arch/arm64/boot/dts/marvell/armada-7040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
@@ -218,6 +218,10 @@
};
};
+_utmi {
+ status = "okay";
+};
+
_comphy1 {
cp0_usbh0_con: connector {
compatible = "usb-a-connector";
@@ -226,8 +230,9 @@
};
_usb3_0 {
- phys = <_comphy1 0>;
- phy-names = "cp0-usb3h0-comphy";
+ phys = <_comphy1 0>, <_utmi0>;
+ phy-names = "cp0-usb3h0-comphy", "utmi";
+ dr_mode = "host";
status = "okay";
};
@@ -239,8 +244,9 @@
};
_usb3_1 {
- phys = <_comphy4 1>;
- phy-names = "cp0-usb3h1-comphy";
+ phys = <_comphy4 1>, <_utmi1>;
+ phy-names = "cp0-usb3h1-comphy", "utmi";
+ dr_mode = "host";
status = "okay";
};
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts
b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
index 09fb5256f1db..e39e1efc95b6 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
@@ -154,8 +154,15 @@
};
/* CON9 on CP0 expansion */
+_utmi {
+ status = "okay";
+};
+
_usb3_0 {
usb-phy = <_usb3_0_phy>;
+ phys = <_utmi0>;
+ phy-names = "utmi";
+ dr_mode = "host";
status = "okay";
};
@@ -168,8 +175,9 @@
/* CON10 on CP0 expansion */
_usb3_1 {
- phys = <_comphy4 1>;
- phy-names = "cp0-usb3h1-comphy";
+ phys = <_comphy4 1>, <_utmi1>;
+ phy-names = "usb", "utmi";
+ dr_mode = "host";
status = "okay";
};
@@ -306,14 +314,23 @@
};
};
+_utmi {
+ status = "okay";
+};
+
/* CON9 on CP1 expansion */
_usb3_0 {
usb-phy = <_usb3_0_phy>;
+ phys = <_utmi0>;
+ phy-names = "utmi";
+ dr_mode = "host";
status = "okay";
};
/* CON10 on CP1 expansion */
_usb3_1 {
+ phys = <_utmi1>;
+ phy-names = "utmi";
status = "okay";
};
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
index cbcb210cb6d8..adbfecc678b5 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
@@ -259,13 +259,23 @@
vqmmc-supply = <_3_3>;
};
+_utmi {
+ status = "okay";
+};
+
_usb3_0 {
/* J38? - USB2.0 only */
+ phys = <_utmi0>;
+ phy-names = "utmi";
+ dr_mode = "host";
status = "okay";
};
_usb3_1 {
/* J38? - USB2.0 only */
+ phys = <_utmi1>;
+ phy-names = "utmi";
+ dr_mode = "host";
status = "okay";
};
@@ -364,9 +374,14 @@
};
};
+_utmi {
+ status = "okay";
+};
+
_usb3_0 {
/* CPS Lane 2 - CON7 */
- phys = <_comphy2 0>;
- phy-names = "cp1-usb3h0-comphy";
+ phys = <_comphy2 0>, <_utmi0>;
+ phy-names = "cp1-usb3h0-comphy", "utmi";
+ dr_mode = "host";
status = "okay";
};
diff --git a/arch/arm64/boot/dts/marvell/cn9130-db.dts
b/arch/arm64/boot/dts/marvell/cn9130-db.dts
index ce49a70d88a0..62fa6ecc0acd 100644
--- a/arch/arm64/boot/dts/marvell/cn9130-db.dts
+++ b/arch/arm64/boot/dts/marvell/cn9130-db.dts
@@ -390,14 +390,22 @@
};
};
+_utmi {
+ status = "okay";
+};
+
_usb3_0 {
status = "okay";
usb-phy = <_usb3_0_phy0>;
- phy-names = "usb";
+ phys = <_utmi0>;
+ phy-names = "utmi";
+ dr_mode = "host";
};
_usb3_1 {
status = "okay";
usb-phy = <_usb3_0_phy1>;
- phy-names = "usb";
+ phys = <_utmi1>;
+ phy-names = "utmi";
+ dr_mode = "host";
};
diff --git a/arch/arm64/boot/dts/marvell/cn9131-db.dts
b/arch/arm64/boot/dts/marvell/cn9131-db.dts
index 3c975f98b2a3..ba2d4e1da159 100644
--- a/arch/arm64/boot/dts/marvell/cn9131-db.dts
+++ b/arch/arm64/boot/dts/marvell/cn9131-db.dts
@@ -193,10 +193,15 @@
};
/* CON58 */
+_utmi {
+ status = "okay";
+};
+
_usb3_1 {
status = "okay";
usb-phy = <_usb3_0_phy0>;
/* Generic PHY, providing serdes lanes */
- phys = <_comphy3 1>;
- phy-names = "usb";
+ phys = <_comphy3 1>, <_utmi1>;
+ phy-names = "usb", "utmi";
+
[PATCH v2 3/4] arch/arm64: dts: add support for Marvell CP110 UTMI driver
From: Konstantin Porotchkin
Add support for Marvell CP110 UTMI driver in a common DTSI
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
index 994a2fce449a..5f1f5d51c881 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
@@ -275,6 +275,25 @@
};
};
+ CP11X_LABEL(utmi): utmi@58 {
+ compatible = "marvell,cp110-utmi-phy";
+ reg = <0x58 0x2000>;
+ marvell,system-controller = <_LABEL(syscon0)>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ CP11X_LABEL(utmi0): phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+
+ CP11X_LABEL(utmi1): phy@1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ };
+ };
+
CP11X_LABEL(usb3_0): usb@50 {
compatible = "marvell,armada-8k-xhci",
"generic-xhci";
--
2.17.1
[PATCH v2 0/4] Add support for CP110 UTMI PHY
From: Konstantin Porotchkin This series of patches adds a new PHY driver for supporting CP110 UTMI PHY in Linux. Currently the functionality of USB ports connected to this PHY depends on boot loader setup. The new driver eliminates kernel configuration dependency from the boot loader. v2: - extend the comment about reference clock - fix driver probe function, add some prints - move to usage of dr_mode from connected USB controller instead of dedicated device tree property Konstantin Porotchkin (4): drivers: phy: add support for Armada CP110 UTMI PHY devicetree/bindings: add support for CP110 UTMI driver arch/arm64: dts: add support for Marvell CP110 UTMI driver arch/arm64: dts: enable CP110 UTMI driver .../bindings/phy/phy-mvebu-utmi.txt | 78 +++- .../arm64/boot/dts/marvell/armada-7040-db.dts | 14 +- .../arm64/boot/dts/marvell/armada-8040-db.dts | 21 +- .../boot/dts/marvell/armada-8040-mcbin.dtsi | 19 +- arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 19 + arch/arm64/boot/dts/marvell/cn9130-db.dts | 12 +- arch/arm64/boot/dts/marvell/cn9131-db.dts | 9 +- arch/arm64/boot/dts/marvell/cn9132-db.dts | 11 +- drivers/phy/marvell/Kconfig | 8 + drivers/phy/marvell/Makefile | 1 + drivers/phy/marvell/phy-mvebu-cp110-utmi.c| 384 ++ 11 files changed, 556 insertions(+), 20 deletions(-) create mode 100644 drivers/phy/marvell/phy-mvebu-cp110-utmi.c -- 2.17.1
[PATCH v2 1/4] drivers: phy: add support for Armada CP110 UTMI PHY
From: Konstantin Porotchkin Add support for Marvell CP110 UTMI PHY driver allowing the USB2 port configuration independently from the boot loader setup. The CP110/CP115 dies have 2 UTMI PHYs that could be connected to two USB host controllers or to single USB device controller. Since there is only one USB device controller on die, only one of the UTMI PHYs could work in USB device mode. The CONFIG_PHY_MVEBU_CP110_UTMI should be enabled for usage of this driver. Signed-off-by: Konstantin Porotchkin --- drivers/phy/marvell/Kconfig| 8 + drivers/phy/marvell/Makefile | 1 + drivers/phy/marvell/phy-mvebu-cp110-utmi.c | 384 3 files changed, 393 insertions(+) create mode 100644 drivers/phy/marvell/phy-mvebu-cp110-utmi.c diff --git a/drivers/phy/marvell/Kconfig b/drivers/phy/marvell/Kconfig index 6c96f2bf5266..9208839019bd 100644 --- a/drivers/phy/marvell/Kconfig +++ b/drivers/phy/marvell/Kconfig @@ -67,6 +67,14 @@ config PHY_MVEBU_CP110_COMPHY lanes can be used by various controllers (Ethernet, sata, usb, PCIe...). +config PHY_MVEBU_CP110_UTMI + tristate "Marvell CP110 UTMI driver" + depends on ARCH_MVEBU || COMPILE_TEST + depends on OF + select GENERIC_PHY + help + Enable this to support Marvell CP110 UTMI PHY driver. + config PHY_MVEBU_SATA def_bool y depends on ARCH_DOVE || MACH_DOVE || MACH_KIRKWOOD diff --git a/drivers/phy/marvell/Makefile b/drivers/phy/marvell/Makefile index 7f296ef02829..90862c4daa26 100644 --- a/drivers/phy/marvell/Makefile +++ b/drivers/phy/marvell/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_PHY_MVEBU_A3700_COMPHY)+= phy-mvebu-a3700-comphy.o obj-$(CONFIG_PHY_MVEBU_A3700_UTMI) += phy-mvebu-a3700-utmi.o obj-$(CONFIG_PHY_MVEBU_A38X_COMPHY)+= phy-armada38x-comphy.o obj-$(CONFIG_PHY_MVEBU_CP110_COMPHY) += phy-mvebu-cp110-comphy.o +obj-$(CONFIG_PHY_MVEBU_CP110_UTMI) += phy-mvebu-cp110-utmi.o obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o obj-$(CONFIG_PHY_PXA_28NM_HSIC)+= phy-pxa-28nm-hsic.o obj-$(CONFIG_PHY_PXA_28NM_USB2)+= phy-pxa-28nm-usb2.o diff --git a/drivers/phy/marvell/phy-mvebu-cp110-utmi.c b/drivers/phy/marvell/phy-mvebu-cp110-utmi.c new file mode 100644 index ..08d178a4dc13 --- /dev/null +++ b/drivers/phy/marvell/phy-mvebu-cp110-utmi.c @@ -0,0 +1,384 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Marvell + * + * Authors: + * Konstantin Porotchkin + * + * Marvell CP110 UTMI PHY driver + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define UTMI_PHY_PORTS 2 + +/* CP110 UTMI register macro definetions */ +#define SYSCON_USB_CFG_REG 0x420 +#define USB_CFG_DEVICE_EN_MASK BIT(0) +#define USB_CFG_DEVICE_MUX_OFFSET1 +#define USB_CFG_DEVICE_MUX_MASK BIT(1) +#define USB_CFG_PLL_MASK BIT(25) + +#define SYSCON_UTMI_CFG_REG(id)(0x440 + (id) * 4) +#define UTMI_PHY_CFG_PU_MASK BIT(5) + +#define UTMI_PLL_CTRL_REG 0x0 +#define PLL_REFDIV_OFFSET0 +#define PLL_REFDIV_MASK GENMASK(6, 0) +#define PLL_REFDIV_VAL 0x5 +#define PLL_FBDIV_OFFSET 16 +#define PLL_FBDIV_MASK GENMASK(24, 16) +#define PLL_FBDIV_VAL0x60 +#define PLL_SEL_LPFR_MASKGENMASK(29, 28) +#define PLL_RDY BIT(31) +#define UTMI_CAL_CTRL_REG 0x8 +#define IMPCAL_VTH_OFFSET8 +#define IMPCAL_VTH_MASK GENMASK(10, 8) +#define IMPCAL_VTH_VAL 0x7 +#define IMPCAL_DONE BIT(23) +#define PLLCAL_DONE BIT(31) +#define UTMI_TX_CH_CTRL_REG0xC +#define DRV_EN_LS_OFFSET 12 +#define DRV_EN_LS_MASK GENMASK(15, 12) +#define IMP_SEL_LS_OFFSET16 +#define IMP_SEL_LS_MASK GENMASK(19, 16) +#define TX_AMP_OFFSET20 +#define TX_AMP_MASK GENMASK(22, 20) +#define TX_AMP_VAL 0x4 +#define UTMI_RX_CH_CTRL0_REG 0x14 +#define SQ_DET_ENBIT(15) +#define SQ_ANA_DTC_SEL BIT(28) +#define UTMI_RX_CH_CTRL1_REG 0x18 +#define SQ_AMP_CAL_OFFSET0 +#define SQ_AMP_CAL_MASK GENMASK(2, 0) +#define SQ_AMP_CAL_VAL 1 +#define SQ_AMP_CAL_ENBIT(3) +#define UTMI_CTRL_STATUS0_REG
[PATCH v3 2/2] clk: mvebu: use firmware SiP service for accessing dfx register set
From: Grzegorz Jaszczyk
This patch introduces support for cpu clk driver in case when SoC
DFX region is marked as secure by the firmware. In such case accessing
cpu clk registers, which are part of dfx register set, will not be
possible from non-secure world.
The ARM Trusted Firmware exposes SiP service which allows to read/write
some dfx registers (white-listed in firmware). This allows Linux cpu clk
driver to set_rate and recalc_rate with use of SMC calls.
If during cpu clk operation the SMC is unhandled (old fw case), fallback
to regmap handling.
Signed-off-by: Grzegorz Jaszczyk
Signed-off-by: Konstantin Porotchkin
---
drivers/clk/mvebu/ap-cpu-clk.c| 174 ++--
include/soc/marvell/armada8k/fw.h | 3 +
2 files changed, 161 insertions(+), 16 deletions(-)
diff --git a/drivers/clk/mvebu/ap-cpu-clk.c b/drivers/clk/mvebu/ap-cpu-clk.c
index b4259b60dcfd..9ddfa3f8a32d 100644
--- a/drivers/clk/mvebu/ap-cpu-clk.c
+++ b/drivers/clk/mvebu/ap-cpu-clk.c
@@ -10,6 +10,7 @@
#define pr_fmt(fmt) "ap-cpu-clk: " fmt
+#include
#include
#include
#include
@@ -19,6 +20,7 @@
#include
#include
#include "armada_ap_cp_helper.h"
+#include "soc/marvell/armada8k/fw.h"
#define AP806_CPU_CLUSTER0 0
#define AP806_CPU_CLUSTER1 1
@@ -139,8 +141,122 @@ struct ap_cpu_clk {
struct clk_hw hw;
struct regmap *pll_cr_base;
const struct cpu_dfs_regs *pll_regs;
+ phys_addr_t phys;
+ int (*clk_regmap_read)(struct ap_cpu_clk *clk, unsigned int reg,
+ unsigned int *val);
+ int (*clk_regmap_write)(struct ap_cpu_clk *clk, unsigned int reg,
+ unsigned int val);
+ int (*clk_regmap_update_bits)(struct ap_cpu_clk *clk, unsigned int reg,
+ unsigned int mask, unsigned int val);
+ int (*clk_regmap_read_poll_timeout)(struct ap_cpu_clk *clk, unsigned
int reg,
+ unsigned int stable_bit);
+
};
+static int dfx_sread_smc(unsigned long addr, unsigned int *reg)
+{
+ struct arm_smccc_res res;
+
+ arm_smccc_smc(MV_SIP_DFX, MV_SIP_DFX_SREAD, addr, 0, 0, 0, 0, 0, );
+
+ if (res.a0 == 0 && reg != NULL)
+ *reg = res.a1;
+
+ return res.a0;
+}
+
+static int dfx_swrite_smc(unsigned long addr, unsigned long val)
+{
+ struct arm_smccc_res res;
+
+ arm_smccc_smc(MV_SIP_DFX, MV_SIP_DFX_SWRITE, addr, val,
+ 0, 0, 0, 0, );
+
+ return res.a0;
+}
+
+static int smc_regmap_read(struct ap_cpu_clk *clk, unsigned int reg,
+ unsigned int *val)
+{
+ return dfx_sread_smc(clk->phys + reg, val);
+}
+
+static int legacy_regmap_read(struct ap_cpu_clk *clk, unsigned int reg,
+ unsigned int *val)
+{
+ return regmap_read(clk->pll_cr_base, reg, val);
+}
+
+static int smc_regmap_write(struct ap_cpu_clk *clk, unsigned int reg,
+ unsigned int val)
+{
+ return dfx_swrite_smc(clk->phys + reg, val);
+}
+
+static int legacy_regmap_write(struct ap_cpu_clk *clk, unsigned int reg,
+ unsigned int val)
+{
+ return regmap_write(clk->pll_cr_base, reg, val);
+}
+
+static int smc_regmap_update_bits(struct ap_cpu_clk *clk, unsigned int reg,
+ unsigned int mask, unsigned int val)
+{
+ int ret;
+ unsigned int tmp;
+
+ ret = dfx_sread_smc(clk->phys + reg, );
+ if (ret != SMCCC_RET_SUCCESS)
+ return ret;
+
+ tmp &= ~mask;
+ tmp |= val & mask;
+
+ return dfx_swrite_smc(clk->phys + reg, tmp);
+}
+
+static int legacy_regmap_update_bits(struct ap_cpu_clk *clk, unsigned int reg,
+unsigned int mask, unsigned int val)
+{
+ return regmap_update_bits(clk->pll_cr_base, reg, mask, val);
+}
+
+static int smc_regmap_read_poll_timeout(struct ap_cpu_clk *clk,
+ unsigned int reg,
+ unsigned int stable_bit)
+{
+ int ret;
+ u32 val;
+ ktime_t timeout;
+
+ timeout = ktime_add_us(ktime_get(), STATUS_POLL_TIMEOUT_US);
+ do {
+ ret = dfx_sread_smc(clk->phys + reg, );
+ if (ret || (val & stable_bit))
+ break;
+
+ usleep_range((STATUS_POLL_PERIOD_US >> 2) + 1,
+STATUS_POLL_PERIOD_US);
+
+ } while (ktime_before(ktime_get(), timeout));
+
+ if (ret == SMCCC_RET_SUCCESS)
+ return (val & stable_bit) ? 0 : -ETIMEDOUT;
+
+ return ret;
+}
+
+static int legacy_regmap_read_poll_timeout(struct ap_cpu_clk *clk,
+ unsigned int reg,
+ unsigned int stable_bit)
+{
+ u32 val;
+
+ return regmap_read_poll_timeout(clk->pll_cr_base,
+
[PATCH v3 1/2] thermal: armada: ap806: use firmware SiP services for thermal operations
From: Grzegorz Jaszczyk
This patch introduces support for ap806 thermal driver in case when SoC
DFX region is marked as secure by the firmware. In such case accessing
thermal registers, which are part of dfx register set, will not be
possible from non-secure world. Due to above the ARM Trusted Firmware
exposes thermal driver as a SiP service. This allows Linux thermal
driver to initialise and perform various operations on thermal sensor
with use of SMC calls.
If during ap806 thermal initialisation the SMC is unhandled (old fw
case), fallback to regmap handling.
Signed-off-by: Grzegorz Jaszczyk
Signed-off-by: Konstantin Porotchkin
---
drivers/thermal/armada_thermal.c | 125 +++-
include/soc/marvell/armada8k/fw.h | 19 +++
2 files changed, 141 insertions(+), 3 deletions(-)
create mode 100644 include/soc/marvell/armada8k/fw.h
diff --git a/drivers/thermal/armada_thermal.c b/drivers/thermal/armada_thermal.c
index c2ebfb5be4b3..ec077e834c85 100644
--- a/drivers/thermal/armada_thermal.c
+++ b/drivers/thermal/armada_thermal.c
@@ -4,6 +4,7 @@
*
* Copyright (C) 2013 Marvell
*/
+#include
#include
#include
#include
@@ -18,6 +19,8 @@
#include
#include
#include
+#include
+#include "soc/marvell/armada8k/fw.h"
#include "thermal_core.h"
@@ -62,6 +65,8 @@
#define STATUS_POLL_TIMEOUT_US 10
#define OVERHEAT_INT_POLL_DELAY_MS 1000
+#define THERMAL_SUPPORTED_IN_FIRMWARE(priv) (priv->data->is_smc_supported)
+
struct armada_thermal_data;
/* Marvell EBU Thermal Sensor Dev Structure */
@@ -111,6 +116,12 @@ struct armada_thermal_data {
/* One sensor is in the thermal IC, the others are in the CPUs if any */
unsigned int cpu_nr;
+
+ /*
+* Thermal sensor operations exposed as firmware SIP services and
+* accessed via SMC
+*/
+ bool is_smc_supported;
};
struct armada_drvdata {
@@ -135,6 +146,18 @@ struct armada_thermal_sensor {
int id;
};
+static int thermal_smc(u32 addr, u32 *reg, u32 val1, u32 val2)
+{
+ struct arm_smccc_res res;
+
+ arm_smccc_smc(MV_SIP_DFX, addr, val1, val2, 0, 0, 0, 0, );
+
+ if (res.a0 == 0 && reg != NULL)
+ *reg = res.a1;
+
+ return res.a0;
+}
+
static void armadaxp_init(struct platform_device *pdev,
struct armada_thermal_priv *priv)
{
@@ -206,6 +229,27 @@ static void armada375_init(struct platform_device *pdev,
static int armada_wait_sensor_validity(struct armada_thermal_priv *priv)
{
u32 reg;
+ int ret;
+ ktime_t timeout;
+
+ if (THERMAL_SUPPORTED_IN_FIRMWARE(priv)) {
+ timeout = ktime_add_us(ktime_get(), STATUS_POLL_TIMEOUT_US);
+ do {
+ ret = thermal_smc(MV_SIP_DFX_THERMAL_IS_VALID,
+ , 0, 0);
+ if (ret || reg)
+ break;
+
+ usleep_range((STATUS_POLL_PERIOD_US >> 2) + 1,
+STATUS_POLL_PERIOD_US);
+
+ } while (ktime_before(ktime_get(), timeout));
+
+ if (ret == SMCCC_RET_SUCCESS)
+ return reg ? 0 : -ETIMEDOUT;
+
+ return ret;
+ }
return regmap_read_poll_timeout(priv->syscon,
priv->data->syscon_status_off, reg,
@@ -238,6 +282,22 @@ static void armada_ap806_init(struct platform_device *pdev,
{
struct armada_thermal_data *data = priv->data;
u32 reg;
+ int ret;
+
+ /*
+* The ap806 thermal sensor registers are part of DFX which is secured
+* by latest firmware, therefore accessing relevant registers from
+* not-secure world will not be possible. In that case Arm Trusted
+* Firmware exposes thermal operations as firmware run-time service. If
+* SMC initialization succeeds, perform other thermal operations using
+* SMC, otherwise (old fw case) fallback to regmap handling.
+*/
+ ret = thermal_smc(MV_SIP_DFX_THERMAL_INIT, 0x0, 0, 0);
+ if (ret == SMCCC_RET_SUCCESS) {
+ dev_info(>dev, "firmware support\n");
+ THERMAL_SUPPORTED_IN_FIRMWARE(priv) = true;
+ return;
+ }
regmap_read(priv->syscon, data->syscon_control0_off, );
reg &= ~CONTROL0_TSEN_RESET;
@@ -274,11 +334,17 @@ static void armada_cp110_init(struct platform_device
*pdev,
static bool armada_is_valid(struct armada_thermal_priv *priv)
{
+ int ret;
u32 reg;
if (!priv->data->is_valid_bit)
return true;
+ if (THERMAL_SUPPORTED_IN_FIRMWARE(priv)) {
+ ret = thermal_smc(MV_SIP_DFX_THERMAL_IS_VALID, , 0, 0);
+ return ret ? false : reg;
+ }
+
regmap_read(priv->syscon, priv->data->syscon_status_off, );
return reg & priv->data->is_valid_bit;
@@ -324,6 +390,7 @@
[PATCH v3 0/2] Enable usage of Marvell FW SIP services
From: Konstantin Porotchkin These patches enable usage of Arm Trusted Firmware SIP services on Marvell Armada plaforms for accessing system registers that are not normally accessible from kernel or user space (EL1/EL0), like DFX registers group. v2: * use separate legacy/smc regmap functions registered at ap-cpu clock driver probe according to FW response v3: * fix build errors and rebase on top of clk-next branch Grzegorz Jaszczyk (2): thermal: armada: ap806: use firmware SiP services for thermal operations clk: mvebu: use firmware SiP service for accessing dfx register set drivers/clk/mvebu/ap-cpu-clk.c| 174 ++-- drivers/thermal/armada_thermal.c | 125 +- include/soc/marvell/armada8k/fw.h | 22 +++ 3 files changed, 302 insertions(+), 19 deletions(-) create mode 100644 include/soc/marvell/armada8k/fw.h -- 2.17.1
[PATCH 2/2] clk: mvebu: use firmware SiP service for accessing dfx register set
From: Grzegorz Jaszczyk
This patch introduces support for cpu clk driver in case when SoC
DFX region is marked as secure by the firmware. In such case accessing
cpu clk registers, which are part of dfx register set, will not be
possible from non-secure world.
The ARM Trusted Firmware exposes SiP service which allows to read/write
some dfx registers (white-listed in firmware). This allows Linux cpu clk
driver to set_rate and recalc_rate with use of SMC calls.
If during cpu clk operation the SMC is unhandled (old fw case), fallback
to regmap handling.
Signed-off-by: Grzegorz Jaszczyk
Signed-off-by: Konstantin Porotchkin
---
drivers/clk/mvebu/ap-cpu-clk.c| 174 ++--
include/soc/marvell/armada8k/fw.h | 3 +
2 files changed, 161 insertions(+), 16 deletions(-)
diff --git a/drivers/clk/mvebu/ap-cpu-clk.c b/drivers/clk/mvebu/ap-cpu-clk.c
index b4259b60dcfd..9ddfa3f8a32d 100644
--- a/drivers/clk/mvebu/ap-cpu-clk.c
+++ b/drivers/clk/mvebu/ap-cpu-clk.c
@@ -10,6 +10,7 @@
#define pr_fmt(fmt) "ap-cpu-clk: " fmt
+#include
#include
#include
#include
@@ -19,6 +20,7 @@
#include
#include
#include "armada_ap_cp_helper.h"
+#include "soc/marvell/armada8k/fw.h"
#define AP806_CPU_CLUSTER0 0
#define AP806_CPU_CLUSTER1 1
@@ -139,8 +141,122 @@ struct ap_cpu_clk {
struct clk_hw hw;
struct regmap *pll_cr_base;
const struct cpu_dfs_regs *pll_regs;
+ phys_addr_t phys;
+ int (*clk_regmap_read)(struct ap_cpu_clk *clk, unsigned int reg,
+ unsigned int *val);
+ int (*clk_regmap_write)(struct ap_cpu_clk *clk, unsigned int reg,
+ unsigned int val);
+ int (*clk_regmap_update_bits)(struct ap_cpu_clk *clk, unsigned int reg,
+ unsigned int mask, unsigned int val);
+ int (*clk_regmap_read_poll_timeout)(struct ap_cpu_clk *clk, unsigned
int reg,
+ unsigned int stable_bit);
+
};
+static int dfx_sread_smc(unsigned long addr, unsigned int *reg)
+{
+ struct arm_smccc_res res;
+
+ arm_smccc_smc(MV_SIP_DFX, MV_SIP_DFX_SREAD, addr, 0, 0, 0, 0, 0, );
+
+ if (res.a0 == 0 && reg != NULL)
+ *reg = res.a1;
+
+ return res.a0;
+}
+
+static int dfx_swrite_smc(unsigned long addr, unsigned long val)
+{
+ struct arm_smccc_res res;
+
+ arm_smccc_smc(MV_SIP_DFX, MV_SIP_DFX_SWRITE, addr, val,
+ 0, 0, 0, 0, );
+
+ return res.a0;
+}
+
+static int smc_regmap_read(struct ap_cpu_clk *clk, unsigned int reg,
+ unsigned int *val)
+{
+ return dfx_sread_smc(clk->phys + reg, val);
+}
+
+static int legacy_regmap_read(struct ap_cpu_clk *clk, unsigned int reg,
+ unsigned int *val)
+{
+ return regmap_read(clk->pll_cr_base, reg, val);
+}
+
+static int smc_regmap_write(struct ap_cpu_clk *clk, unsigned int reg,
+ unsigned int val)
+{
+ return dfx_swrite_smc(clk->phys + reg, val);
+}
+
+static int legacy_regmap_write(struct ap_cpu_clk *clk, unsigned int reg,
+ unsigned int val)
+{
+ return regmap_write(clk->pll_cr_base, reg, val);
+}
+
+static int smc_regmap_update_bits(struct ap_cpu_clk *clk, unsigned int reg,
+ unsigned int mask, unsigned int val)
+{
+ int ret;
+ unsigned int tmp;
+
+ ret = dfx_sread_smc(clk->phys + reg, );
+ if (ret != SMCCC_RET_SUCCESS)
+ return ret;
+
+ tmp &= ~mask;
+ tmp |= val & mask;
+
+ return dfx_swrite_smc(clk->phys + reg, tmp);
+}
+
+static int legacy_regmap_update_bits(struct ap_cpu_clk *clk, unsigned int reg,
+unsigned int mask, unsigned int val)
+{
+ return regmap_update_bits(clk->pll_cr_base, reg, mask, val);
+}
+
+static int smc_regmap_read_poll_timeout(struct ap_cpu_clk *clk,
+ unsigned int reg,
+ unsigned int stable_bit)
+{
+ int ret;
+ u32 val;
+ ktime_t timeout;
+
+ timeout = ktime_add_us(ktime_get(), STATUS_POLL_TIMEOUT_US);
+ do {
+ ret = dfx_sread_smc(clk->phys + reg, );
+ if (ret || (val & stable_bit))
+ break;
+
+ usleep_range((STATUS_POLL_PERIOD_US >> 2) + 1,
+STATUS_POLL_PERIOD_US);
+
+ } while (ktime_before(ktime_get(), timeout));
+
+ if (ret == SMCCC_RET_SUCCESS)
+ return (val & stable_bit) ? 0 : -ETIMEDOUT;
+
+ return ret;
+}
+
+static int legacy_regmap_read_poll_timeout(struct ap_cpu_clk *clk,
+ unsigned int reg,
+ unsigned int stable_bit)
+{
+ u32 val;
+
+ return regmap_read_poll_timeout(clk->pll_cr_base,
+
[PATCH 1/2] thermal: armada: ap806: use firmware SiP services for thermal operations
From: Grzegorz Jaszczyk
This patch introduces support for ap806 thermal driver in case when SoC
DFX region is marked as secure by the firmware. In such case accessing
thermal registers, which are part of dfx register set, will not be
possible from non-secure world. Due to above the ARM Trusted Firmware
exposes thermal driver as a SiP service. This allows Linux thermal
driver to initialise and perform various operations on thermal sensor
with use of SMC calls.
If during ap806 thermal initialisation the SMC is unhandled (old fw
case), fallback to regmap handling.
Signed-off-by: Grzegorz Jaszczyk
Signed-off-by: Konstantin Porotchkin
---
drivers/thermal/armada_thermal.c | 125 +++-
include/soc/marvell/armada8k/fw.h | 19 +++
2 files changed, 141 insertions(+), 3 deletions(-)
create mode 100644 include/soc/marvell/armada8k/fw.h
diff --git a/drivers/thermal/armada_thermal.c b/drivers/thermal/armada_thermal.c
index c2ebfb5be4b3..ec077e834c85 100644
--- a/drivers/thermal/armada_thermal.c
+++ b/drivers/thermal/armada_thermal.c
@@ -4,6 +4,7 @@
*
* Copyright (C) 2013 Marvell
*/
+#include
#include
#include
#include
@@ -18,6 +19,8 @@
#include
#include
#include
+#include
+#include "soc/marvell/armada8k/fw.h"
#include "thermal_core.h"
@@ -62,6 +65,8 @@
#define STATUS_POLL_TIMEOUT_US 10
#define OVERHEAT_INT_POLL_DELAY_MS 1000
+#define THERMAL_SUPPORTED_IN_FIRMWARE(priv) (priv->data->is_smc_supported)
+
struct armada_thermal_data;
/* Marvell EBU Thermal Sensor Dev Structure */
@@ -111,6 +116,12 @@ struct armada_thermal_data {
/* One sensor is in the thermal IC, the others are in the CPUs if any */
unsigned int cpu_nr;
+
+ /*
+* Thermal sensor operations exposed as firmware SIP services and
+* accessed via SMC
+*/
+ bool is_smc_supported;
};
struct armada_drvdata {
@@ -135,6 +146,18 @@ struct armada_thermal_sensor {
int id;
};
+static int thermal_smc(u32 addr, u32 *reg, u32 val1, u32 val2)
+{
+ struct arm_smccc_res res;
+
+ arm_smccc_smc(MV_SIP_DFX, addr, val1, val2, 0, 0, 0, 0, );
+
+ if (res.a0 == 0 && reg != NULL)
+ *reg = res.a1;
+
+ return res.a0;
+}
+
static void armadaxp_init(struct platform_device *pdev,
struct armada_thermal_priv *priv)
{
@@ -206,6 +229,27 @@ static void armada375_init(struct platform_device *pdev,
static int armada_wait_sensor_validity(struct armada_thermal_priv *priv)
{
u32 reg;
+ int ret;
+ ktime_t timeout;
+
+ if (THERMAL_SUPPORTED_IN_FIRMWARE(priv)) {
+ timeout = ktime_add_us(ktime_get(), STATUS_POLL_TIMEOUT_US);
+ do {
+ ret = thermal_smc(MV_SIP_DFX_THERMAL_IS_VALID,
+ , 0, 0);
+ if (ret || reg)
+ break;
+
+ usleep_range((STATUS_POLL_PERIOD_US >> 2) + 1,
+STATUS_POLL_PERIOD_US);
+
+ } while (ktime_before(ktime_get(), timeout));
+
+ if (ret == SMCCC_RET_SUCCESS)
+ return reg ? 0 : -ETIMEDOUT;
+
+ return ret;
+ }
return regmap_read_poll_timeout(priv->syscon,
priv->data->syscon_status_off, reg,
@@ -238,6 +282,22 @@ static void armada_ap806_init(struct platform_device *pdev,
{
struct armada_thermal_data *data = priv->data;
u32 reg;
+ int ret;
+
+ /*
+* The ap806 thermal sensor registers are part of DFX which is secured
+* by latest firmware, therefore accessing relevant registers from
+* not-secure world will not be possible. In that case Arm Trusted
+* Firmware exposes thermal operations as firmware run-time service. If
+* SMC initialization succeeds, perform other thermal operations using
+* SMC, otherwise (old fw case) fallback to regmap handling.
+*/
+ ret = thermal_smc(MV_SIP_DFX_THERMAL_INIT, 0x0, 0, 0);
+ if (ret == SMCCC_RET_SUCCESS) {
+ dev_info(>dev, "firmware support\n");
+ THERMAL_SUPPORTED_IN_FIRMWARE(priv) = true;
+ return;
+ }
regmap_read(priv->syscon, data->syscon_control0_off, );
reg &= ~CONTROL0_TSEN_RESET;
@@ -274,11 +334,17 @@ static void armada_cp110_init(struct platform_device
*pdev,
static bool armada_is_valid(struct armada_thermal_priv *priv)
{
+ int ret;
u32 reg;
if (!priv->data->is_valid_bit)
return true;
+ if (THERMAL_SUPPORTED_IN_FIRMWARE(priv)) {
+ ret = thermal_smc(MV_SIP_DFX_THERMAL_IS_VALID, , 0, 0);
+ return ret ? false : reg;
+ }
+
regmap_read(priv->syscon, priv->data->syscon_status_off, );
return reg & priv->data->is_valid_bit;
@@ -324,6 +390,7 @@
[PATCH 0/2] Enable usage of Marvell FW SIP services
From: Konstantin Porotchkin These patches enable usage of Arm Trusted Firmware SIP services on Marvell Armada plaforms for accessing system registers that are not normally accessible from kernel or user space (EL1/EL0), like DFX registers group. v2: * use separate legacy/smc regmap functions registered at ap-cpu clock driver probe according to FW response v3: * fix build errors and rebase on clk-next branch Grzegorz Jaszczyk (2): thermal: armada: ap806: use firmware SiP services for thermal operations clk: mvebu: use firmware SiP service for accessing dfx register set drivers/clk/mvebu/ap-cpu-clk.c| 174 ++-- drivers/thermal/armada_thermal.c | 125 +- include/soc/marvell/armada8k/fw.h | 22 +++ 3 files changed, 302 insertions(+), 19 deletions(-) create mode 100644 include/soc/marvell/armada8k/fw.h -- 2.17.1
[PATCH v2 12/12] arm64: dts: fix the Armada 8040 DB AP SDHCI bus width
From: Konstantin Porotchkin
The AP SDHCI on Armada 8040 DB board utilizes 8-bit data lines.
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/armada-8040-db.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts
b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
index 0a3b3afe0e9c..7559f901ffae 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
@@ -373,7 +373,7 @@
_sdhci0 {
status = "okay";
- bus-width = <4>;
+ bus-width = <8>;
non-removable;
};
--
2.17.1
[PATCH v2 11/12] dts: marvell: add 2 eeprom properties to A7K DB device tree
From: Ben Peled
Add on-board i2c EEPROMs U37 and U38
Signed-off-by: Ben Peled
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/armada-7040-db.dts | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-7040-db.dts
b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
index 39f1d393664f..c8258defa9e5 100644
--- a/arch/arm64/boot/dts/marvell/armada-7040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
@@ -152,6 +152,20 @@
* IO0_7: IO1_7: SDIO_Vcntrl
*/
};
+
+ /* U38 */
+ eeprom0: eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ pagesize = <0x20>;
+ };
+
+ /* U37 */
+ eeprom1: eeprom@57 {
+ compatible = "atmel,24c64";
+ reg = <0x57>;
+ pagesize = <0x20>;
+ };
};
_nand_controller {
--
2.17.1
[PATCH v2 10/12] dts: marvell: add 2 eeprom properties to A8K DB device tree
From: Ben Peled
Add on-board i2c EEPROMs U41 and U51
Signed-off-by: Ben Peled
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/armada-8040-db.dts | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts
b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
index 372eda1f8898..0a3b3afe0e9c 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
@@ -150,6 +150,19 @@
reg = <0x25>;
};
+ /* U51 */
+ eeprom0: eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ pagesize = <0x20>;
+ };
+
+ /* U41 */
+ eeprom1: eeprom@57 {
+ compatible = "atmel,24c64";
+ reg = <0x57>;
+ pagesize = <0x20>;
+ };
};
/* CON4 on CP0 expansion */
--
2.17.1
[PATCH v2 09/12] dts: a3700: enable dma coherence
From: Stefan Chulski
Enable dma coherence for PCIe and memory-mapped devices
on A3700 platform
Signed-off-by: Stefan Chulski
Signed-off-by: Marcin Wojtas
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
index d5b6c0a1c54a..c01351172875 100644
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
@@ -71,6 +71,7 @@
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
+ dma-coherent;
ranges;
internal-regs@d000 {
@@ -486,6 +487,7 @@
#interrupt-cells = <1>;
msi-parent = <>;
msi-controller;
+ dma-coherent;
ranges = <0x8200 0 0xe800 0 0xe800 0
0x100 /* Port 0 MEM */
0x8100 0 0xe900 0 0xe900 0
0x1>; /* Port 0 IO*/
interrupt-map-mask = <0 0 0 7>;
--
2.17.1
[PATCH v2 08/12] arm64: dts: marvell: armada-3720-db: add eeprom description
From: Grzegorz Jaszczyk
On Armada 3720 board there is serial emprom M24C64 at address 0x57,
reflect it in device-tree.
Signed-off-by: Grzegorz Jaszczyk
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/armada-3720-db.dts | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-db.dts
b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
index 15e923f945d4..f2435537c1d3 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
@@ -113,6 +113,12 @@
compatible = "dallas,ds1337";
reg = <0x68>;
};
+
+ eeprom@57 {
+ compatible = "atmel,24c64";
+ reg = <0x57>;
+ pagesize = <32>;
+ };
};
{
--
2.17.1
[PATCH v2 06/12] arm64: dts: marvell: armada-3270-espressobin: add comphy references
From: Grzegorz Jaszczyk
Add "phys" entries pointing to COMPHYs to PCIe and USB3 nodes
Signed-off-by: Grzegorz Jaszczyk
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi
b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi
index daffe136c523..bbd955909813 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi
@@ -59,6 +59,8 @@
/* J9 */
{
status = "okay";
+ /* Generic PHY, providing serdes lanes */
+ phys = < 0>;
pinctrl-names = "default";
pinctrl-0 = <_reset_pins _clkreq_pins>;
reset-gpios = < 3 GPIO_ACTIVE_LOW>;
@@ -139,6 +141,9 @@
/* J7 */
{
status = "okay";
+ /* Generic PHY, providing serdes lanes */
+ phys = < 0>;
+ phy-names = "usb";
};
/* J8 */
--
2.17.1
[PATCH v2 05/12] arm64: dts: marvell: armada-3720-db: add comphy references
From: Grzegorz Jaszczyk
Adding phy description to pcie, sata and usb will allow appropriate drivers
to configure marvell comphy-a3700 accordingly.
Signed-off-by: Grzegorz Jaszczyk
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/armada-3720-db.dts | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-db.dts
b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
index 3e5789f37206..15e923f945d4 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
@@ -132,11 +132,15 @@
pinctrl-0 = <_reset_pins _clkreq_pins>;
reset-gpios = < 3 GPIO_ACTIVE_LOW>;
status = "okay";
+ /* Generic PHY, providing serdes lanes */
+ phys = < 0>;
};
/* CON3 */
{
status = "okay";
+ /* Generic PHY, providing serdes lanes */
+ phys = < 0>;
};
{
@@ -217,4 +221,7 @@
{
status = "okay";
usb-phy = <_phy>;
+ /* Generic PHY, providing serdes lanes */
+ phys = < 0>;
+ phy-names = "usb";
};
--
2.17.1
[PATCH v2 07/12] fix: ARM64: dts: cp110: Switch to 8-bit ECC NAND setting
From: Konstantin Porotchkin
All A7K/A8K boards are using NAND chip that supports
8 bit ECC strength. Using lower ECC strength is not recommended
by the flash manufacturer and may cause data corruption.
This patch changes the nand-ecc-strength value from 4 to 8.
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/armada-7040-db.dts | 2 +-
arch/arm64/boot/dts/marvell/armada-8040-db.dts | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-7040-db.dts
b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
index f8179cadc610..39f1d393664f 100644
--- a/arch/arm64/boot/dts/marvell/armada-7040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
@@ -169,7 +169,7 @@
label = "pxa3xx_nand-0";
nand-rb = <0>;
nand-on-flash-bbt;
- nand-ecc-strength = <4>;
+ nand-ecc-strength = <8>;
nand-ecc-step-size = <512>;
partitions {
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts
b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
index 790c7ab0b816..372eda1f8898 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
@@ -281,7 +281,7 @@
reg = <0>;
nand-rb = <0>;
nand-on-flash-bbt;
- nand-ecc-strength = <4>;
+ nand-ecc-strength = <8>;
nand-ecc-step-size = <512>;
partitions {
--
2.17.1
[PATCH v2 03/12] dts: mvebu: Add pin control definitions for SDIO interafce
From: Konstantin Porotchkin
Add SDIO mode pin control configuration for CP0 in Armada
70x0 and 80x0 SoCs.
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/armada-70x0.dtsi | 6 ++
arch/arm64/boot/dts/marvell/armada-80x0.dtsi | 6 ++
2 files changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
index 293403a1a333..f22b6b8f5086 100644
--- a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
@@ -47,6 +47,12 @@
cp0_pinctrl: pinctrl {
compatible = "marvell,armada-7k-pinctrl";
+ sdhci_pins: sdhci-pins {
+ marvell,pins = "mpp56", "mpp57", "mpp58",
+ "mpp59", "mpp60", "mpp61", "mpp62";
+ marvell,function = "sdio";
+ };
+
nand_pins: nand-pins {
marvell,pins =
"mpp15", "mpp16", "mpp17", "mpp18",
diff --git a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
index ee67c70bf02e..04a6142a0286 100644
--- a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
@@ -70,6 +70,12 @@
_syscon0 {
cp0_pinctrl: pinctrl {
compatible = "marvell,armada-8k-cpm-pinctrl";
+
+ sdhci_pins: sdhci-pins {
+ marvell,pins = "mpp56", "mpp57", "mpp58",
+ "mpp59", "mpp60", "mpp61", "mpp62";
+ marvell,function = "sdio";
+ };
};
};
--
2.17.1
[PATCH v2 04/12] fix: dts: a8k: Add CP eMMC regulator and update device parameters
From: Konstantin Porotchkin
Add GPIO regulator for controlling CP0 eMMC voltage (3.3V/1.8V)
Update CP0 SDHCI parameters in A7K/A8K boards DTS files.
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/armada-7040-db.dts | 17 -
arch/arm64/boot/dts/marvell/armada-8040-db.dts | 18 +-
2 files changed, 33 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-7040-db.dts
b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
index a7eb4e7697a2..f8179cadc610 100644
--- a/arch/arm64/boot/dts/marvell/armada-7040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
@@ -28,6 +28,19 @@
ethernet2 = _eth2;
};
+ cp0_vccq_sd0_reg: cp0_vccq_sd0 {
+ compatible = "regulator-gpio";
+ regulator-name = "cp0-vccq-sd0";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <330>;
+ regulator-boot-on;
+ gpios = < 15 GPIO_ACTIVE_HIGH>;
+ gpios-states = <0>;
+ states = <180 0x1
+ 330 0x0>;
+ enable-active-high;
+ };
+
cp0_exp_usb3_0_current_regulator: gpio-regulator {
compatible = "regulator-gpio";
regulator-name = "cp0-usb3-0-current-regulator";
@@ -253,8 +266,10 @@
_sdhci0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
bus-width = <4>;
- no-1-8-v;
+ vqmmc-supply = <_vccq_sd0_reg>;
cd-gpios = < 12 GPIO_ACTIVE_LOW>;
};
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts
b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
index 09fb5256f1db..790c7ab0b816 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
@@ -31,6 +31,19 @@
i2c2 = _i2c0;
};
+ cp0_vccq_sd0_reg: cp0_vccq_sd0 {
+ compatible = "regulator-gpio";
+ regulator-name = "cp0-vccq-sd0";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <330>;
+ regulator-boot-on;
+ gpios = < 15 GPIO_ACTIVE_HIGH>;
+ gpios-states = <0>;
+ states = <180 0x1
+ 330 0x0>;
+ enable-active-high;
+ };
+
cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus {
compatible = "regulator-fixed";
regulator-name = "cp0-usb3h0-vbus";
@@ -353,6 +366,9 @@
_sdhci0 {
status = "okay";
- bus-width = <8>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+ bus-width = <4>;
+ vqmmc-supply = <_vccq_sd0_reg>;
non-removable;
};
--
2.17.1
[PATCH v2 02/12] dts: mvebu: Update A8K AP806/AP807 SDHCI settings
From: Konstantin Porotchkin
Select the AP SDHCI PHY slow mode for AP806 die only (move it
from armada-ap80x.dtsi to armada-ap806.dtsi). This will allow
running AP807 based devices at HS400 speed.
Remove Ap SDHCI slow mode property from MacchiatoBin board DTS
since it is already selected on the SoC level.
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi | 5 -
arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 12
arch/arm64/boot/dts/marvell/armada-ap80x.dtsi | 1 -
3 files changed, 12 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
index 73733b4126e2..69653de998e2 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
@@ -109,11 +109,6 @@
_sdhci0 {
bus-width = <8>;
- /*
-* Not stable in HS modes - phy needs "more calibration", so add
-* the "slow-mode" and disable SDR104, SDR50 and DDR50 modes.
-*/
- marvell,xenon-phy-slow-mode;
no-1-8-v;
no-sd;
no-sdio;
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
index 866628679ac7..828cd539173b 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
@@ -28,3 +28,15 @@
reg = <0x278 0xa30>;
};
};
+
+_sdhci0 {
+ /*
+* SoC based on AP806 revision A0, A1 and A2 should use slow mode
+* settings for Ap SDHCI due to HW Erratum HWE-7296210
+* AP806 revesion B0 and later has this erratum fixed and the slow
+* mode could be removed in board DTS:
+* /delete-property/marvell,xenon-phy-slow-mode;
+* Starting from B0 revision, the AP SDHCI can run with HS400 timing.
+*/
+ marvell,xenon-phy-slow-mode;
+};
diff --git a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
index 12e477f1aeb9..edd6131a0587 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
@@ -257,7 +257,6 @@
clock-names = "core";
clocks = <_clk 4>;
dma-coherent;
- marvell,xenon-phy-slow-mode;
status = "disabled";
};
--
2.17.1
[PATCH v2 00/12] Device tree fixes for Armada family
From: Konstantin Porotchkin This set of patches include various device tree additions and fixes for Marvell Armada SoC families A3700/A7K/A8K. These changes are ported from Marvell SDK release files. v2: - Rebase on top of Linus master branch 5.11-rc7 - Move AP SDHCI "slow-mode" property from AP80x DTSI to AP806 DTSI - move AP SDHCI bus width change for A8040-DB to a separatye patch - fix typos in pin control definitions patch - fix patch description for pin control definitions patch Ben Peled (2): dts: marvell: add 2 eeprom properties to A8K DB device tree dts: marvell: add 2 eeprom properties to A7K DB device tree Grzegorz Jaszczyk (3): arm64: dts: marvell: armada-3720-db: add comphy references arm64: dts: marvell: armada-3270-espressobin: add comphy references arm64: dts: marvell: armada-3720-db: add eeprom description Konstantin Porotchkin (6): fix: arm64: dts: replace wrong regulator on ap emmc dts: mvebu: Update A8K AP806/AP807 SDHCI settings dts: mvebu: Add pin control definitions for SDIO interafce fix: dts: a8k: Add CP eMMC regulator and update device parameters fix: ARM64: dts: cp110: Switch to 8-bit ECC NAND setting arm64: dts: fix the Armada 8040 DB AP SDHCI bus width Stefan Chulski (1): dts: a3700: enable dma coherence .../arm64/boot/dts/marvell/armada-3720-db.dts | 13 +++ .../dts/marvell/armada-3720-espressobin.dtsi | 5 +++ arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 2 ++ .../arm64/boot/dts/marvell/armada-7040-db.dts | 33 +++-- arch/arm64/boot/dts/marvell/armada-70x0.dtsi | 6 .../arm64/boot/dts/marvell/armada-8040-db.dts | 35 +-- .../boot/dts/marvell/armada-8040-mcbin.dtsi | 7 +--- arch/arm64/boot/dts/marvell/armada-80x0.dtsi | 6 arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 12 +++ arch/arm64/boot/dts/marvell/armada-ap80x.dtsi | 1 - 10 files changed, 108 insertions(+), 12 deletions(-) -- 2.17.1
[PATCH v2 01/12] fix: arm64: dts: replace wrong regulator on ap emmc
From: Konstantin Porotchkin
Replace wrong regulator in AP0 eMMC definition on MacchiatoBIN
board with 3.3V regulator.
The MacchiatoBIN board has no 1.8V regulator connected to AP0
eMMC (ap0_sdhci0) interface.
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
index cbcb210cb6d8..73733b4126e2 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
@@ -119,7 +119,7 @@
no-sdio;
non-removable;
status = "okay";
- vqmmc-supply = <_vddo_h>;
+ vqmmc-supply = <_3_3>;
};
_i2c0 {
--
2.17.1
[PATCH v5 5/5] arm64: dts: add support for Marvell cn9130-crb platform
From: Konstantin Porotchkin
The Marvell reference platform CN9130-CRB is a small form factor
board in a metal case. The platform is based on CN9130 SoC with
addition of 8 Gigabit ports SOHO Ethernet switch.
The reference platform features the following:
* Up to 4 CPU cores ARMv8 Cortex-A72 CPU
* CPU core operating speed of up to 2.2GHz
* DDR4 DIMM – 8GB 64bit+ECC @ 2400Mhz.
* 1x eMMC 8GB device
* 1x uSD card 4 bits port on CP
* 1x 128MB SPI NOR flash memory
* 1x USB 3.0 Host port (Type A)
* 1x SATA Gen3 via M.2
* 1x USB 3.0 via M.2
* 1x SIM card slot
* 1x 1G Ethernet port via RGMII
* 1x 10G switch port over SFP+ connector
* 8x 1G ports through 88E6393X switch via XFI
* 1x 2.5G/1G/100M/10M port via HS_SGMII
* 1x PCI Express (PCIe)x1 Gen 3.0
* 1x PCI Express (PCIe)x4 Gen 3.0 via NVMe M.2
* JTAG port
The CRB board uses MCP23017 i2c pin controller that drives the
onboard eMMC abd USB 3,0 port power lines.
The following configuration should be enabled for this controller
support:
CONFIG_PINCTRL_MCP23S08=y
The plaform supports two HW configurations - "A" and "B"
CN9130-CRB-A
* AP-MPP configuration: SDIO, UART
* CP0 Serdes configuration:
* Lane0-3: NVMe (PCIe x4)
* Lane4: XFI
* Lane5: HS_SGMII
2. CN9130-CRB-B
* AP-MPP configuration: SDIO, UART
* CP0-MPP configuration: RGMII, SDIO, I2C0, I2C1, SMI, XSMI
* CP0 Serdes configuration:
* Lane0: PCIe x1
* Lane1: USB3_0 x1
* Lane2: SATA x1
* Lane3: USB3_1 x1
* Lane4: XFI
* Lane5: HS_SGMII
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/Makefile | 2 +
arch/arm64/boot/dts/marvell/cn9130-crb-A.dts | 38
arch/arm64/boot/dts/marvell/cn9130-crb-B.dts | 46
arch/arm64/boot/dts/marvell/cn9130-crb.dtsi | 222
4 files changed, 308 insertions(+)
create mode 100644 arch/arm64/boot/dts/marvell/cn9130-crb-A.dts
create mode 100644 arch/arm64/boot/dts/marvell/cn9130-crb-B.dts
create mode 100644 arch/arm64/boot/dts/marvell/cn9130-crb.dtsi
diff --git a/arch/arm64/boot/dts/marvell/Makefile
b/arch/arm64/boot/dts/marvell/Makefile
index 5e39f9774e68..c686a8dd3ca5 100644
--- a/arch/arm64/boot/dts/marvell/Makefile
+++ b/arch/arm64/boot/dts/marvell/Makefile
@@ -21,3 +21,5 @@ dtb-$(CONFIG_ARCH_MVEBU) += cn9131-db.dtb
dtb-$(CONFIG_ARCH_MVEBU) += cn9131-db-B.dtb
dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db.dtb
dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db-B.dtb
+dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-A.dtb
+dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-B.dtb
diff --git a/arch/arm64/boot/dts/marvell/cn9130-crb-A.dts
b/arch/arm64/boot/dts/marvell/cn9130-crb-A.dts
new file mode 100644
index ..a7b6dfba8af5
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/cn9130-crb-A.dts
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ */
+
+#include "cn9130-crb.dtsi"
+
+/ {
+ model = "Marvell Armada CN9130-CRB-A";
+};
+
+_pcie0 {
+ status = "okay";
+ num-lanes = <4>;
+ num-viewport = <8>;
+ /* Generic PHY, providing serdes lanes */
+ phys = <_comphy0 0
+ _comphy1 0
+ _comphy2 0
+ _comphy3 0>;
+ iommu-map =
+ <0x00x480 0x20>,
+ <0x100 0x4a0 0x20>,
+ <0x200 0x4c0 0x20>;
+ iommu-map-mask = <0x031f>;
+};
+
+_usb3_0 {
+ status = "okay";
+ usb-phy = <_usb3_0_phy0>;
+ phy-names = "usb";
+};
+
+_usb3_1 {
+ status = "okay";
+ usb-phy = <_usb3_0_phy1>;
+ phy-names = "usb";
+};
diff --git a/arch/arm64/boot/dts/marvell/cn9130-crb-B.dts
b/arch/arm64/boot/dts/marvell/cn9130-crb-B.dts
new file mode 100644
index ..0904cb0309ae
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/cn9130-crb-B.dts
@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ */
+
+#include "cn9130-crb.dtsi"
+
+/ {
+ model = "Marvell Armada CN9130-CRB-B";
+};
+
+_pcie0 {
+ status = "okay";
+ num-lanes = <1>;
+ num-viewport = <8>;
+ /* Generic PHY, providing serdes lanes */
+ phys = <_comphy0 0>;
+ iommu-map =
+ <0x00x480 0x20>,
+ <0x100 0x4a0 0x20>,
+ <0x200 0x4c0 0x20>;
+ iommu-map-mask = <0x031f>;
+};
+
+_sata0 {
+ status = "okay";
+ sata-port@0 {
+ status = "okay";
+ /* Generic PHY, providing serdes lanes */
+ phys = <_comphy2 0>;
+ };
+};
+
+_usb3_0 {
+ status = "okay";
+ usb-phy = <_usb3_0_phy0>;
+ phy-names = "usb";
+ phys = <_comphy1 0>;
+};
+
+_usb3_1 {
+ status = "okay";
+ usb-phy = <_usb3_0_phy1>;
+ phy-names = "usb";
+ phys = <_comphy3 1>;
+};
diff --git a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi
b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi
new file mode 100644
index ..75933477324a
--- /dev/null
[PATCH v5 3/5] arm64: dts: cn913x: add device trees for topology B boards
From: Konstantin Porotchkin
The CN913x DB with topology B is similar to a regular setup (A)
boards, but uses NAND flash as a boot device, while topology A
boards are booting from SPI flash.
Since NAND and SPI on CN913x DB boards share some wires, they
cannot be activated simultaneously.
The DTS files for setup "B" are based on setup "A", in which the
CP0 NAND controller enabled and CP0 SPI1 disabled.
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/Makefile| 3 +
arch/arm64/boot/dts/marvell/cn9130-db-B.dts | 22 ++
arch/arm64/boot/dts/marvell/cn9130-db.dts | 393 +--
arch/arm64/boot/dts/marvell/cn9130-db.dtsi | 402
arch/arm64/boot/dts/marvell/cn9131-db-B.dts | 22 ++
arch/arm64/boot/dts/marvell/cn9131-db.dts | 192 +-
arch/arm64/boot/dts/marvell/cn9131-db.dtsi | 201 ++
arch/arm64/boot/dts/marvell/cn9132-db-B.dts | 22 ++
arch/arm64/boot/dts/marvell/cn9132-db.dts | 211 +-
arch/arm64/boot/dts/marvell/cn9132-db.dtsi | 220 +++
10 files changed, 910 insertions(+), 778 deletions(-)
create mode 100644 arch/arm64/boot/dts/marvell/cn9130-db-B.dts
create mode 100644 arch/arm64/boot/dts/marvell/cn9130-db.dtsi
create mode 100644 arch/arm64/boot/dts/marvell/cn9131-db-B.dts
create mode 100644 arch/arm64/boot/dts/marvell/cn9131-db.dtsi
create mode 100644 arch/arm64/boot/dts/marvell/cn9132-db-B.dts
create mode 100644 arch/arm64/boot/dts/marvell/cn9132-db.dtsi
diff --git a/arch/arm64/boot/dts/marvell/Makefile
b/arch/arm64/boot/dts/marvell/Makefile
index 34efe0fb6f37..5e39f9774e68 100644
--- a/arch/arm64/boot/dts/marvell/Makefile
+++ b/arch/arm64/boot/dts/marvell/Makefile
@@ -16,5 +16,8 @@ dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-mcbin-singleshot.dtb
dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-puzzle-m801.dtb
dtb-$(CONFIG_ARCH_MVEBU) += armada-8080-db.dtb
dtb-$(CONFIG_ARCH_MVEBU) += cn9130-db.dtb
+dtb-$(CONFIG_ARCH_MVEBU) += cn9130-db-B.dtb
dtb-$(CONFIG_ARCH_MVEBU) += cn9131-db.dtb
+dtb-$(CONFIG_ARCH_MVEBU) += cn9131-db-B.dtb
dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db.dtb
+dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db-B.dtb
diff --git a/arch/arm64/boot/dts/marvell/cn9130-db-B.dts
b/arch/arm64/boot/dts/marvell/cn9130-db-B.dts
new file mode 100644
index ..57e41cacd483
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/cn9130-db-B.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ *
+ * Device tree for the CN9130-DB board (setup "B").
+ */
+
+#include "cn9130-db.dtsi"
+
+/ {
+ model = "Marvell Armada CN9130-DB setup B";
+};
+
+/* Setup B has NAND flash as a boot device, while regular setup uses SPI flash.
+ * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
+ * simultaneously. When NAND controller is enabled, SPI1 should be disabled.
+ */
+
+_nand_controller {
+ status = "okay";
+};
+
diff --git a/arch/arm64/boot/dts/marvell/cn9130-db.dts
b/arch/arm64/boot/dts/marvell/cn9130-db.dts
index d24294888400..994f347f2973 100644
--- a/arch/arm64/boot/dts/marvell/cn9130-db.dts
+++ b/arch/arm64/boot/dts/marvell/cn9130-db.dts
@@ -5,399 +5,18 @@
* Device tree for the CN9130-DB board.
*/
-#include "cn9130.dtsi"
-
-#include
+#include "cn9130-db.dtsi"
/ {
- model = "Marvell Armada CN9130-DB";
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- aliases {
- gpio1 = _gpio1;
- gpio2 = _gpio2;
- i2c0 = _i2c0;
- ethernet0 = _eth0;
- ethernet1 = _eth1;
- ethernet2 = _eth2;
- spi1 = _spi0;
- spi2 = _spi1;
- };
-
- memory@ {
- device_type = "memory";
- reg = <0x0 0x0 0x0 0x8000>;
- };
-
- ap0_reg_sd_vccq: ap0_sd_vccq@0 {
- compatible = "regulator-gpio";
- regulator-name = "ap0_sd_vccq";
- regulator-min-microvolt = <180>;
- regulator-max-microvolt = <330>;
- gpios = < 8 GPIO_ACTIVE_HIGH>;
- states = <180 0x1 330 0x0>;
- };
-
- cp0_reg_usb3_vbus0: cp0_usb3_vbus@0 {
- compatible = "regulator-fixed";
- regulator-name = "cp0-xhci0-vbus";
- regulator-min-microvolt = <500>;
- regulator-max-microvolt = <500>;
- enable-active-high;
- gpio = < 0 GPIO_ACTIVE_HIGH>;
- };
-
- cp0_usb3_0_phy0: cp0_usb3_phy@0 {
- compatible = "usb-nop-xceiv";
- vcc-supply = <_reg_usb3_vbus0>;
- };
-
- cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 {
- compatible = "regulator-fixed";
- regulator-name = "cp0-xhci1-vbus";
- regulator-min-microvolt = <500>;
- regulator-max-microvolt = <500>;
-
[PATCH v5 4/5] dts: marvell: Enable 10G interfaces on 9130-DB and 9131-DB boards
From: Stefan Chulski
This patch enables eth0 10G interface on CN9130-DB paltforms and
eth0 10G and eth3 10G interfaces on CN9131-DB.
Signed-off-by: Stefan Chulski
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/cn9130-db.dtsi | 2 +-
arch/arm64/boot/dts/marvell/cn9131-db.dtsi | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/cn9130-db.dtsi
b/arch/arm64/boot/dts/marvell/cn9130-db.dtsi
index 8de3a552b806..97c74b81fd78 100644
--- a/arch/arm64/boot/dts/marvell/cn9130-db.dtsi
+++ b/arch/arm64/boot/dts/marvell/cn9130-db.dtsi
@@ -125,7 +125,7 @@
/* SLM-1521-V2, CON9 */
_eth0 {
- status = "disabled";
+ status = "okay";
phy-mode = "10gbase-kr";
/* Generic PHY, providing serdes lanes */
phys = <_comphy4 0>;
diff --git a/arch/arm64/boot/dts/marvell/cn9131-db.dtsi
b/arch/arm64/boot/dts/marvell/cn9131-db.dtsi
index 82471a83ad6d..f2e4d3a6a4f8 100644
--- a/arch/arm64/boot/dts/marvell/cn9131-db.dtsi
+++ b/arch/arm64/boot/dts/marvell/cn9131-db.dtsi
@@ -84,7 +84,7 @@
/* CON50 */
_eth0 {
- status = "disabled";
+ status = "okay";
phy-mode = "10gbase-kr";
/* Generic PHY, providing serdes lanes */
phys = <_comphy4 0>;
--
2.17.1
[PATCH v5 2/5] arch/arm64/boot/dts/marvell: fix NAND partitioning scheme
From: Konstantin Porotchkin
Eliminate 1MB gap between Linux and filesystem partitions.
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/cn9130-db.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/marvell/cn9130-db.dts
b/arch/arm64/boot/dts/marvell/cn9130-db.dts
index ce49a70d88a0..d24294888400 100644
--- a/arch/arm64/boot/dts/marvell/cn9130-db.dts
+++ b/arch/arm64/boot/dts/marvell/cn9130-db.dts
@@ -258,7 +258,7 @@
};
partition@20 {
label = "Linux";
- reg = <0x20 0xd0>;
+ reg = <0x20 0xe0>;
};
partition@100 {
label = "Filesystem";
--
2.17.1
[PATCH v5 0/5] DTS updates for Marvell Armada CN913x platforms
From: Konstantin Porotchkin This patch series contains the following changes/fixes: 1. Add support for Armada CN913x Development Board topology "B" 2. Add support for Armada CN913x Reference Design boards (CRB) 3. Fixes the CP11X references in PHY binding document 4. Fixes the NAND paritioninig scheme in DTS eliminating gap between consecutive partitions All above changes are already intergated into Marvell official SDK sources v2: - extract common nodes from DB boards to separate DTSI files - disable eth2 on CRB boards until the required phy mode support is added - mention the switch part ID in CRB board description v3: - do not rename setup A DTS files for DB variants - fix a couple of wrong include names v4: - Rebase on top of Linus master branch (v5.11-rc7) - Remove HS400 timing from CRB AP SDHCI (not supported by connected eMMC) - Add cd-gpio entry to CP0 SDHCI for SD card support - Add a comment to CN9130-CRB patch about the required defconfig changes for supporting the onboard i2c expander - Add Stefan's patch to enable 10G port on CN9130-DB platforms v5: - Extend enablement of 10G port to CN9131-DB platform Grzegorz Jaszczyk (1): Documentation/bindings: phy: update references to cp11x Konstantin Porotchkin (3): arch/arm64/boot/dts/marvell: fix NAND partitioning scheme arm64: dts: cn913x: add device trees for topology B boards arm64: dts: add support for Marvell cn9130-crb platform Stefan Chulski (1): dts: marvell: Enable 10G interfaces on 9130-DB and 9131-DB boards .../bindings/phy/phy-mvebu-comphy.txt | 12 +- arch/arm64/boot/dts/marvell/Makefile | 5 + arch/arm64/boot/dts/marvell/cn9130-crb-A.dts | 38 ++ arch/arm64/boot/dts/marvell/cn9130-crb-B.dts | 46 ++ arch/arm64/boot/dts/marvell/cn9130-crb.dtsi | 222 ++ arch/arm64/boot/dts/marvell/cn9130-db-B.dts | 22 + arch/arm64/boot/dts/marvell/cn9130-db.dts | 393 + arch/arm64/boot/dts/marvell/cn9130-db.dtsi| 402 ++ arch/arm64/boot/dts/marvell/cn9131-db-B.dts | 22 + arch/arm64/boot/dts/marvell/cn9131-db.dts | 192 + arch/arm64/boot/dts/marvell/cn9131-db.dtsi| 201 + arch/arm64/boot/dts/marvell/cn9132-db-B.dts | 22 + arch/arm64/boot/dts/marvell/cn9132-db.dts | 211 + arch/arm64/boot/dts/marvell/cn9132-db.dtsi| 220 ++ 14 files changed, 1224 insertions(+), 784 deletions(-) create mode 100644 arch/arm64/boot/dts/marvell/cn9130-crb-A.dts create mode 100644 arch/arm64/boot/dts/marvell/cn9130-crb-B.dts create mode 100644 arch/arm64/boot/dts/marvell/cn9130-crb.dtsi create mode 100644 arch/arm64/boot/dts/marvell/cn9130-db-B.dts create mode 100644 arch/arm64/boot/dts/marvell/cn9130-db.dtsi create mode 100644 arch/arm64/boot/dts/marvell/cn9131-db-B.dts create mode 100644 arch/arm64/boot/dts/marvell/cn9131-db.dtsi create mode 100644 arch/arm64/boot/dts/marvell/cn9132-db-B.dts create mode 100644 arch/arm64/boot/dts/marvell/cn9132-db.dtsi -- 2.17.1
[PATCH v5 1/5] Documentation/bindings: phy: update references to cp11x
From: Grzegorz Jaszczyk
The cp11x references in dts has changed, reflect it in comphy
documentation.
Signed-off-by: Grzegorz Jaszczyk
Signed-off-by: Konstantin Porotchkin
---
Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt
b/Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt
index 8c60e6985950..5ffd0f55d010 100644
--- a/Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt
+++ b/Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt
@@ -42,22 +42,22 @@ Required properties (child nodes):
Examples:
- cpm_comphy: phy@12 {
+ CP11X_LABEL(comphy): phy@12 {
compatible = "marvell,comphy-cp110";
reg = <0x12 0x6000>;
- marvell,system-controller = <_syscon0>;
- clocks = <_LABEL(clk) 1 5>, <_LABEL(clk) 1 6>,
-<_LABEL(clk) 1 18>;
+ marvell,system-controller = <_LABEL(syscon0)>;
+ clocks = <_LABEL(clk) 1 5>, <_LABEL(clk) 1 6>,
+<_LABEL(clk) 1 18>;
clock-names = "mg_clk", "mg_core_clk", "axi_clk";
#address-cells = <1>;
#size-cells = <0>;
- cpm_comphy0: phy@0 {
+ CP11X_LABEL(comphy0): phy@0 {
reg = <0>;
#phy-cells = <1>;
};
- cpm_comphy1: phy@1 {
+ CP11X_LABEL(comphy1): phy@1 {
reg = <1>;
#phy-cells = <1>;
};
--
2.17.1
[PATCH v4 3/5] arm64: dts: cn913x: add device trees for topology B boards
From: Konstantin Porotchkin
The CN913x DB with topology B is similar to a regular setup (A)
boards, but uses NAND flash as a boot device, while topology A
boards are booting from SPI flash.
Since NAND and SPI on CN913x DB boards share some wires, they
cannot be activated simultaneously.
The DTS files for setup "B" are based on setup "A", in which the
CP0 NAND controller enabled and CP0 SPI1 disabled.
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/Makefile| 3 +
arch/arm64/boot/dts/marvell/cn9130-db-B.dts | 22 ++
arch/arm64/boot/dts/marvell/cn9130-db.dts | 393 +--
arch/arm64/boot/dts/marvell/cn9130-db.dtsi | 402
arch/arm64/boot/dts/marvell/cn9131-db-B.dts | 22 ++
arch/arm64/boot/dts/marvell/cn9131-db.dts | 192 +-
arch/arm64/boot/dts/marvell/cn9131-db.dtsi | 201 ++
arch/arm64/boot/dts/marvell/cn9132-db-B.dts | 22 ++
arch/arm64/boot/dts/marvell/cn9132-db.dts | 211 +-
arch/arm64/boot/dts/marvell/cn9132-db.dtsi | 220 +++
10 files changed, 910 insertions(+), 778 deletions(-)
create mode 100644 arch/arm64/boot/dts/marvell/cn9130-db-B.dts
create mode 100644 arch/arm64/boot/dts/marvell/cn9130-db.dtsi
create mode 100644 arch/arm64/boot/dts/marvell/cn9131-db-B.dts
create mode 100644 arch/arm64/boot/dts/marvell/cn9131-db.dtsi
create mode 100644 arch/arm64/boot/dts/marvell/cn9132-db-B.dts
create mode 100644 arch/arm64/boot/dts/marvell/cn9132-db.dtsi
diff --git a/arch/arm64/boot/dts/marvell/Makefile
b/arch/arm64/boot/dts/marvell/Makefile
index 34efe0fb6f37..5e39f9774e68 100644
--- a/arch/arm64/boot/dts/marvell/Makefile
+++ b/arch/arm64/boot/dts/marvell/Makefile
@@ -16,5 +16,8 @@ dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-mcbin-singleshot.dtb
dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-puzzle-m801.dtb
dtb-$(CONFIG_ARCH_MVEBU) += armada-8080-db.dtb
dtb-$(CONFIG_ARCH_MVEBU) += cn9130-db.dtb
+dtb-$(CONFIG_ARCH_MVEBU) += cn9130-db-B.dtb
dtb-$(CONFIG_ARCH_MVEBU) += cn9131-db.dtb
+dtb-$(CONFIG_ARCH_MVEBU) += cn9131-db-B.dtb
dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db.dtb
+dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db-B.dtb
diff --git a/arch/arm64/boot/dts/marvell/cn9130-db-B.dts
b/arch/arm64/boot/dts/marvell/cn9130-db-B.dts
new file mode 100644
index ..57e41cacd483
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/cn9130-db-B.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ *
+ * Device tree for the CN9130-DB board (setup "B").
+ */
+
+#include "cn9130-db.dtsi"
+
+/ {
+ model = "Marvell Armada CN9130-DB setup B";
+};
+
+/* Setup B has NAND flash as a boot device, while regular setup uses SPI flash.
+ * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
+ * simultaneously. When NAND controller is enabled, SPI1 should be disabled.
+ */
+
+_nand_controller {
+ status = "okay";
+};
+
diff --git a/arch/arm64/boot/dts/marvell/cn9130-db.dts
b/arch/arm64/boot/dts/marvell/cn9130-db.dts
index d24294888400..994f347f2973 100644
--- a/arch/arm64/boot/dts/marvell/cn9130-db.dts
+++ b/arch/arm64/boot/dts/marvell/cn9130-db.dts
@@ -5,399 +5,18 @@
* Device tree for the CN9130-DB board.
*/
-#include "cn9130.dtsi"
-
-#include
+#include "cn9130-db.dtsi"
/ {
- model = "Marvell Armada CN9130-DB";
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- aliases {
- gpio1 = _gpio1;
- gpio2 = _gpio2;
- i2c0 = _i2c0;
- ethernet0 = _eth0;
- ethernet1 = _eth1;
- ethernet2 = _eth2;
- spi1 = _spi0;
- spi2 = _spi1;
- };
-
- memory@ {
- device_type = "memory";
- reg = <0x0 0x0 0x0 0x8000>;
- };
-
- ap0_reg_sd_vccq: ap0_sd_vccq@0 {
- compatible = "regulator-gpio";
- regulator-name = "ap0_sd_vccq";
- regulator-min-microvolt = <180>;
- regulator-max-microvolt = <330>;
- gpios = < 8 GPIO_ACTIVE_HIGH>;
- states = <180 0x1 330 0x0>;
- };
-
- cp0_reg_usb3_vbus0: cp0_usb3_vbus@0 {
- compatible = "regulator-fixed";
- regulator-name = "cp0-xhci0-vbus";
- regulator-min-microvolt = <500>;
- regulator-max-microvolt = <500>;
- enable-active-high;
- gpio = < 0 GPIO_ACTIVE_HIGH>;
- };
-
- cp0_usb3_0_phy0: cp0_usb3_phy@0 {
- compatible = "usb-nop-xceiv";
- vcc-supply = <_reg_usb3_vbus0>;
- };
-
- cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 {
- compatible = "regulator-fixed";
- regulator-name = "cp0-xhci1-vbus";
- regulator-min-microvolt = <500>;
- regulator-max-microvolt = <500>;
-
[PATCH v4 5/5] arm64: dts: add support for Marvell cn9130-crb platform
From: Konstantin Porotchkin
The Marvell reference platform CN9130-CRB is a small form factor
board in a metal case. The platform is based on CN9130 SoC with
addition of 8 Gigabit ports SOHO Ethernet switch.
The reference platform features the following:
* Up to 4 CPU cores ARMv8 Cortex-A72 CPU
* CPU core operating speed of up to 2.2GHz
* DDR4 DIMM – 8GB 64bit+ECC @ 2400Mhz.
* 1x eMMC 8GB device
* 1x uSD card 4 bits port on CP
* 1x 128MB SPI NOR flash memory
* 1x USB 3.0 Host port (Type A)
* 1x SATA Gen3 via M.2
* 1x USB 3.0 via M.2
* 1x SIM card slot
* 1x 1G Ethernet port via RGMII
* 1x 10G switch port over SFP+ connector
* 8x 1G ports through 88E6393X switch via XFI
* 1x 2.5G/1G/100M/10M port via HS_SGMII
* 1x PCI Express (PCIe)x1 Gen 3.0
* 1x PCI Express (PCIe)x4 Gen 3.0 via NVMe M.2
* JTAG port
The CRB board uses MCP23017 i2c pin controller that drives the
onboard eMMC abd USB 3,0 port power lines.
The following configuration should be enabled for this controller
support:
CONFIG_PINCTRL_MCP23S08=y
The plaform supports two HW configurations - "A" and "B"
CN9130-CRB-A
* AP-MPP configuration: SDIO, UART
* CP0 Serdes configuration:
* Lane0-3: NVMe (PCIe x4)
* Lane4: XFI
* Lane5: HS_SGMII
2. CN9130-CRB-B
* AP-MPP configuration: SDIO, UART
* CP0-MPP configuration: RGMII, SDIO, I2C0, I2C1, SMI, XSMI
* CP0 Serdes configuration:
* Lane0: PCIe x1
* Lane1: USB3_0 x1
* Lane2: SATA x1
* Lane3: USB3_1 x1
* Lane4: XFI
* Lane5: HS_SGMII
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/Makefile | 2 +
arch/arm64/boot/dts/marvell/cn9130-crb-A.dts | 38
arch/arm64/boot/dts/marvell/cn9130-crb-B.dts | 46
arch/arm64/boot/dts/marvell/cn9130-crb.dtsi | 222
4 files changed, 308 insertions(+)
create mode 100644 arch/arm64/boot/dts/marvell/cn9130-crb-A.dts
create mode 100644 arch/arm64/boot/dts/marvell/cn9130-crb-B.dts
create mode 100644 arch/arm64/boot/dts/marvell/cn9130-crb.dtsi
diff --git a/arch/arm64/boot/dts/marvell/Makefile
b/arch/arm64/boot/dts/marvell/Makefile
index 5e39f9774e68..c686a8dd3ca5 100644
--- a/arch/arm64/boot/dts/marvell/Makefile
+++ b/arch/arm64/boot/dts/marvell/Makefile
@@ -21,3 +21,5 @@ dtb-$(CONFIG_ARCH_MVEBU) += cn9131-db.dtb
dtb-$(CONFIG_ARCH_MVEBU) += cn9131-db-B.dtb
dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db.dtb
dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db-B.dtb
+dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-A.dtb
+dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-B.dtb
diff --git a/arch/arm64/boot/dts/marvell/cn9130-crb-A.dts
b/arch/arm64/boot/dts/marvell/cn9130-crb-A.dts
new file mode 100644
index ..a7b6dfba8af5
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/cn9130-crb-A.dts
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ */
+
+#include "cn9130-crb.dtsi"
+
+/ {
+ model = "Marvell Armada CN9130-CRB-A";
+};
+
+_pcie0 {
+ status = "okay";
+ num-lanes = <4>;
+ num-viewport = <8>;
+ /* Generic PHY, providing serdes lanes */
+ phys = <_comphy0 0
+ _comphy1 0
+ _comphy2 0
+ _comphy3 0>;
+ iommu-map =
+ <0x00x480 0x20>,
+ <0x100 0x4a0 0x20>,
+ <0x200 0x4c0 0x20>;
+ iommu-map-mask = <0x031f>;
+};
+
+_usb3_0 {
+ status = "okay";
+ usb-phy = <_usb3_0_phy0>;
+ phy-names = "usb";
+};
+
+_usb3_1 {
+ status = "okay";
+ usb-phy = <_usb3_0_phy1>;
+ phy-names = "usb";
+};
diff --git a/arch/arm64/boot/dts/marvell/cn9130-crb-B.dts
b/arch/arm64/boot/dts/marvell/cn9130-crb-B.dts
new file mode 100644
index ..0904cb0309ae
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/cn9130-crb-B.dts
@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ */
+
+#include "cn9130-crb.dtsi"
+
+/ {
+ model = "Marvell Armada CN9130-CRB-B";
+};
+
+_pcie0 {
+ status = "okay";
+ num-lanes = <1>;
+ num-viewport = <8>;
+ /* Generic PHY, providing serdes lanes */
+ phys = <_comphy0 0>;
+ iommu-map =
+ <0x00x480 0x20>,
+ <0x100 0x4a0 0x20>,
+ <0x200 0x4c0 0x20>;
+ iommu-map-mask = <0x031f>;
+};
+
+_sata0 {
+ status = "okay";
+ sata-port@0 {
+ status = "okay";
+ /* Generic PHY, providing serdes lanes */
+ phys = <_comphy2 0>;
+ };
+};
+
+_usb3_0 {
+ status = "okay";
+ usb-phy = <_usb3_0_phy0>;
+ phy-names = "usb";
+ phys = <_comphy1 0>;
+};
+
+_usb3_1 {
+ status = "okay";
+ usb-phy = <_usb3_0_phy1>;
+ phy-names = "usb";
+ phys = <_comphy3 1>;
+};
diff --git a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi
b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi
new file mode 100644
index ..75933477324a
--- /dev/null
[PATCH v4 4/5] dts: marvell: Enable 10G interface on 9130-DB board
From: Stefan Chulski
This patch enables eth0 10G interface on CN9130-DB paltforms.
Signed-off-by: Stefan Chulski
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/cn9130-db.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/marvell/cn9130-db.dtsi
b/arch/arm64/boot/dts/marvell/cn9130-db.dtsi
index 8de3a552b806..97c74b81fd78 100644
--- a/arch/arm64/boot/dts/marvell/cn9130-db.dtsi
+++ b/arch/arm64/boot/dts/marvell/cn9130-db.dtsi
@@ -125,7 +125,7 @@
/* SLM-1521-V2, CON9 */
_eth0 {
- status = "disabled";
+ status = "okay";
phy-mode = "10gbase-kr";
/* Generic PHY, providing serdes lanes */
phys = <_comphy4 0>;
--
2.17.1
[PATCH v4 1/5] Documentation/bindings: phy: update references to cp11x
From: Grzegorz Jaszczyk
The cp11x references in dts has changed, reflect it in comphy
documentation.
Signed-off-by: Grzegorz Jaszczyk
Signed-off-by: Konstantin Porotchkin
---
Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt
b/Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt
index 8c60e6985950..5ffd0f55d010 100644
--- a/Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt
+++ b/Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt
@@ -42,22 +42,22 @@ Required properties (child nodes):
Examples:
- cpm_comphy: phy@12 {
+ CP11X_LABEL(comphy): phy@12 {
compatible = "marvell,comphy-cp110";
reg = <0x12 0x6000>;
- marvell,system-controller = <_syscon0>;
- clocks = <_LABEL(clk) 1 5>, <_LABEL(clk) 1 6>,
-<_LABEL(clk) 1 18>;
+ marvell,system-controller = <_LABEL(syscon0)>;
+ clocks = <_LABEL(clk) 1 5>, <_LABEL(clk) 1 6>,
+<_LABEL(clk) 1 18>;
clock-names = "mg_clk", "mg_core_clk", "axi_clk";
#address-cells = <1>;
#size-cells = <0>;
- cpm_comphy0: phy@0 {
+ CP11X_LABEL(comphy0): phy@0 {
reg = <0>;
#phy-cells = <1>;
};
- cpm_comphy1: phy@1 {
+ CP11X_LABEL(comphy1): phy@1 {
reg = <1>;
#phy-cells = <1>;
};
--
2.17.1
[PATCH v4 0/5] DTS updates for Marvell Armada CN913x platforms
From: Konstantin Porotchkin This patch series contains the following changes/fixes: 1. Add support for Armada CN913x Development Board topology "B" 2. Add support for Armada CN913x Reference Design boards (CRB) 3. Fixes the CP11X references in PHY binding document 4. Fixes the NAND paritioninig scheme in DTS eliminating gap between consecutive partitions All above changes are already intergated into Marvell official SDK sources v2: - extract common nodes from DB boards to separate DTSI files - disable eth2 on CRB boards until the required phy mode support is added - mention the switch part ID in CRB board description v3: - do not rename setup A DTS files for DB variants - fix a couple of wrong include names v4: - Rebase on top of Linus master branch (v5.11-rc7) - Remove HS400 timing from CRB AP SDHCI (not supported by connected eMMC) - Add cd-gpio entry to CP0 SDHCI for SD card support - Add a comment to CN9130-CRB patch about the required defconfig changes for supporting the onboard i2c expander - Add Stefan's patch to enable 10G port on CN9130-DB platforms Grzegorz Jaszczyk (1): Documentation/bindings: phy: update references to cp11x Konstantin Porotchkin (3): arch/arm64/boot/dts/marvell: fix NAND partitioning scheme arm64: dts: cn913x: add device trees for topology B boards arm64: dts: add support for Marvell cn9130-crb platform Stefan Chulski (1): dts: marvell: Enable 10G interface on 9130-DB board .../bindings/phy/phy-mvebu-comphy.txt | 12 +- arch/arm64/boot/dts/marvell/Makefile | 5 + arch/arm64/boot/dts/marvell/cn9130-crb-A.dts | 38 ++ arch/arm64/boot/dts/marvell/cn9130-crb-B.dts | 46 ++ arch/arm64/boot/dts/marvell/cn9130-crb.dtsi | 221 ++ arch/arm64/boot/dts/marvell/cn9130-db-B.dts | 22 + arch/arm64/boot/dts/marvell/cn9130-db.dts | 393 + arch/arm64/boot/dts/marvell/cn9130-db.dtsi| 402 ++ arch/arm64/boot/dts/marvell/cn9131-db-B.dts | 22 + arch/arm64/boot/dts/marvell/cn9131-db.dts | 192 + arch/arm64/boot/dts/marvell/cn9131-db.dtsi| 201 + arch/arm64/boot/dts/marvell/cn9132-db-B.dts | 22 + arch/arm64/boot/dts/marvell/cn9132-db.dts | 211 + arch/arm64/boot/dts/marvell/cn9132-db.dtsi| 220 ++ 14 files changed, 1223 insertions(+), 784 deletions(-) create mode 100644 arch/arm64/boot/dts/marvell/cn9130-crb-A.dts create mode 100644 arch/arm64/boot/dts/marvell/cn9130-crb-B.dts create mode 100644 arch/arm64/boot/dts/marvell/cn9130-crb.dtsi create mode 100644 arch/arm64/boot/dts/marvell/cn9130-db-B.dts create mode 100644 arch/arm64/boot/dts/marvell/cn9130-db.dtsi create mode 100644 arch/arm64/boot/dts/marvell/cn9131-db-B.dts create mode 100644 arch/arm64/boot/dts/marvell/cn9131-db.dtsi create mode 100644 arch/arm64/boot/dts/marvell/cn9132-db-B.dts create mode 100644 arch/arm64/boot/dts/marvell/cn9132-db.dtsi -- 2.17.1
[PATCH v4 2/5] arch/arm64/boot/dts/marvell: fix NAND partitioning scheme
From: Konstantin Porotchkin
Eliminate 1MB gap between Linux and filesystem partitions.
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/cn9130-db.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/marvell/cn9130-db.dts
b/arch/arm64/boot/dts/marvell/cn9130-db.dts
index ce49a70d88a0..d24294888400 100644
--- a/arch/arm64/boot/dts/marvell/cn9130-db.dts
+++ b/arch/arm64/boot/dts/marvell/cn9130-db.dts
@@ -258,7 +258,7 @@
};
partition@20 {
label = "Linux";
- reg = <0x20 0xd0>;
+ reg = <0x20 0xe0>;
};
partition@100 {
label = "Filesystem";
--
2.17.1
[PATCH 02/11] dts: mvebu: Update A8K AP806 SDHCI settings
From: Konstantin Porotchkin
Update the settings for AP806 SDHCI interface according to
latest Xenon drivers changes.
- no need to select the PHY slow mode anymore
- recommended to add HS400 support at 1.8V signalling on AP806-B0
- fix the bus witdth for A8040 DB from 4 to 8 bits.
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/armada-8040-db.dts | 11 ++-
arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi | 5 -
arch/arm64/boot/dts/marvell/armada-ap80x.dtsi | 1 -
3 files changed, 10 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts
b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
index 09fb5256f1db..6362e654a823 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
@@ -347,7 +347,16 @@
_sdhci0 {
status = "okay";
- bus-width = <4>;
+ bus-width = <8>;
+ /* The below property should be added to boards with AP806-B0
+* for enabling HS400 speed mode. Otherwise the device highest
+* speed mode will be HS200.
+* Should not be added to boards with earlier release of AP806
+* since it will cause SDHCI driver to fail upon initialization.
+* Reference - HWE-7296210 (errata for releases A0/A1/A2)
+*
+* mmc-hs400-1_8v;
+*/
non-removable;
};
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
index 73733b4126e2..69653de998e2 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
@@ -109,11 +109,6 @@
_sdhci0 {
bus-width = <8>;
- /*
-* Not stable in HS modes - phy needs "more calibration", so add
-* the "slow-mode" and disable SDR104, SDR50 and DDR50 modes.
-*/
- marvell,xenon-phy-slow-mode;
no-1-8-v;
no-sd;
no-sdio;
diff --git a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
index 12e477f1aeb9..edd6131a0587 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
@@ -257,7 +257,6 @@
clock-names = "core";
clocks = <_clk 4>;
dma-coherent;
- marvell,xenon-phy-slow-mode;
status = "disabled";
};
--
2.17.1
[PATCH 05/11] arm64: dts: marvell: armada-3720-db: add comphy references
From: Grzegorz Jaszczyk
Adding phy description to pcie, sata and usb will allow appropriate drivers
to configure marvell comphy-a3700 accordingly.
Signed-off-by: Grzegorz Jaszczyk
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/armada-3720-db.dts | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-db.dts
b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
index 3e5789f37206..15e923f945d4 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
@@ -132,11 +132,15 @@
pinctrl-0 = <_reset_pins _clkreq_pins>;
reset-gpios = < 3 GPIO_ACTIVE_LOW>;
status = "okay";
+ /* Generic PHY, providing serdes lanes */
+ phys = < 0>;
};
/* CON3 */
{
status = "okay";
+ /* Generic PHY, providing serdes lanes */
+ phys = < 0>;
};
{
@@ -217,4 +221,7 @@
{
status = "okay";
usb-phy = <_phy>;
+ /* Generic PHY, providing serdes lanes */
+ phys = < 0>;
+ phy-names = "usb";
};
--
2.17.1
[PATCH 00/11] Device tree fixes for Armada family
From: Konstantin Porotchkin This set of patches include various device tree additions and fixes for Marvell Armada SoC families A3700/A7K/A8K. These changes are ported from Marvell SDK release files. Ben Peled (2): dts: marvell: add 2 eeprom properties to A8K DB device tree dts: marvell: add 2 eeprom properties to A7K DB device tree Grzegorz Jaszczyk (3): arm64: dts: marvell: armada-3720-db: add comphy references arm64: dts: marvell: armada-3270-espressobin: add comphy references arm64: dts: marvell: armada-3720-db: add eeprom description Konstantin Porotchkin (5): fix: arm64: dts: replace wrong regulator on ap emmc dts: mvebu: Update A8K AP806 SDHCI settings dts: mvebu: Add pin control definitions for SDIO interafce fix: dts: a8k: Add CP eMMC regulator and update device parameters fix: ARM64: dts: cp110: Switch to 8-bit ECC NAND setting Stefan Chulski (1): dts: a3700: enable dma coherence for PCIE interface .../arm64/boot/dts/marvell/armada-3720-db.dts | 13 ++ .../dts/marvell/armada-3720-espressobin.dtsi | 5 +++ arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 1 + .../arm64/boot/dts/marvell/armada-7040-db.dts | 33 +- arch/arm64/boot/dts/marvell/armada-70x0.dtsi | 6 +++ .../arm64/boot/dts/marvell/armada-8040-db.dts | 44 +-- .../boot/dts/marvell/armada-8040-mcbin.dtsi | 7 +-- arch/arm64/boot/dts/marvell/armada-80x0.dtsi | 6 +++ arch/arm64/boot/dts/marvell/armada-ap80x.dtsi | 1 - 9 files changed, 104 insertions(+), 12 deletions(-) -- 2.17.1
[PATCH 04/11] fix: dts: a8k: Add CP eMMC regulator and update device parameters
From: Konstantin Porotchkin
Add GPIO regulator for controlling CP0 eMMC voltage (3.3V/1.8V)
Update CP0 SDHCI parameters in A7K/A8K boards DTS files.
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/armada-7040-db.dts | 17 -
arch/arm64/boot/dts/marvell/armada-8040-db.dts | 18 +-
2 files changed, 33 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-7040-db.dts
b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
index a7eb4e7697a2..f8179cadc610 100644
--- a/arch/arm64/boot/dts/marvell/armada-7040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
@@ -28,6 +28,19 @@
ethernet2 = _eth2;
};
+ cp0_vccq_sd0_reg: cp0_vccq_sd0 {
+ compatible = "regulator-gpio";
+ regulator-name = "cp0-vccq-sd0";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <330>;
+ regulator-boot-on;
+ gpios = < 15 GPIO_ACTIVE_HIGH>;
+ gpios-states = <0>;
+ states = <180 0x1
+ 330 0x0>;
+ enable-active-high;
+ };
+
cp0_exp_usb3_0_current_regulator: gpio-regulator {
compatible = "regulator-gpio";
regulator-name = "cp0-usb3-0-current-regulator";
@@ -253,8 +266,10 @@
_sdhci0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
bus-width = <4>;
- no-1-8-v;
+ vqmmc-supply = <_vccq_sd0_reg>;
cd-gpios = < 12 GPIO_ACTIVE_LOW>;
};
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts
b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
index 6362e654a823..d96aa9e9e61c 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
@@ -31,6 +31,19 @@
i2c2 = _i2c0;
};
+ cp0_vccq_sd0_reg: cp0_vccq_sd0 {
+ compatible = "regulator-gpio";
+ regulator-name = "cp0-vccq-sd0";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <330>;
+ regulator-boot-on;
+ gpios = < 15 GPIO_ACTIVE_HIGH>;
+ gpios-states = <0>;
+ states = <180 0x1
+ 330 0x0>;
+ enable-active-high;
+ };
+
cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus {
compatible = "regulator-fixed";
regulator-name = "cp0-usb3h0-vbus";
@@ -362,6 +375,9 @@
_sdhci0 {
status = "okay";
- bus-width = <8>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+ bus-width = <4>;
+ vqmmc-supply = <_vccq_sd0_reg>;
non-removable;
};
--
2.17.1
[PATCH 06/11] arm64: dts: marvell: armada-3270-espressobin: add comphy references
From: Grzegorz Jaszczyk
Add "phys" entries pointing to COMPHYs to PCIe and USB3 nodes
Signed-off-by: Grzegorz Jaszczyk
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi
b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi
index daffe136c523..bbd955909813 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi
@@ -59,6 +59,8 @@
/* J9 */
{
status = "okay";
+ /* Generic PHY, providing serdes lanes */
+ phys = < 0>;
pinctrl-names = "default";
pinctrl-0 = <_reset_pins _clkreq_pins>;
reset-gpios = < 3 GPIO_ACTIVE_LOW>;
@@ -139,6 +141,9 @@
/* J7 */
{
status = "okay";
+ /* Generic PHY, providing serdes lanes */
+ phys = < 0>;
+ phy-names = "usb";
};
/* J8 */
--
2.17.1
[PATCH 11/11] dts: marvell: add 2 eeprom properties to A7K DB device tree
From: Ben Peled
Add on-board i2c EEPROMs U37 and U38
Signed-off-by: Ben Peled
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/armada-7040-db.dts | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-7040-db.dts
b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
index 39f1d393664f..c8258defa9e5 100644
--- a/arch/arm64/boot/dts/marvell/armada-7040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
@@ -152,6 +152,20 @@
* IO0_7: IO1_7: SDIO_Vcntrl
*/
};
+
+ /* U38 */
+ eeprom0: eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ pagesize = <0x20>;
+ };
+
+ /* U37 */
+ eeprom1: eeprom@57 {
+ compatible = "atmel,24c64";
+ reg = <0x57>;
+ pagesize = <0x20>;
+ };
};
_nand_controller {
--
2.17.1
[PATCH 07/11] fix: ARM64: dts: cp110: Switch to 8-bit ECC NAND setting
From: Konstantin Porotchkin
All A7K/A8K boards are using NAND chip that supports
8 bit ECC strength. Using lower ECC strength is not recommended
by the flash manufacturer and may cause data corruption.
This patch changes the nand-ecc-strength value from 4 to 8.
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/armada-7040-db.dts | 2 +-
arch/arm64/boot/dts/marvell/armada-8040-db.dts | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-7040-db.dts
b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
index f8179cadc610..39f1d393664f 100644
--- a/arch/arm64/boot/dts/marvell/armada-7040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
@@ -169,7 +169,7 @@
label = "pxa3xx_nand-0";
nand-rb = <0>;
nand-on-flash-bbt;
- nand-ecc-strength = <4>;
+ nand-ecc-strength = <8>;
nand-ecc-step-size = <512>;
partitions {
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts
b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
index d96aa9e9e61c..04241dba189e 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
@@ -281,7 +281,7 @@
reg = <0>;
nand-rb = <0>;
nand-on-flash-bbt;
- nand-ecc-strength = <4>;
+ nand-ecc-strength = <8>;
nand-ecc-step-size = <512>;
partitions {
--
2.17.1
[PATCH 08/11] arm64: dts: marvell: armada-3720-db: add eeprom description
From: Grzegorz Jaszczyk
On Armada 3720 board there is serial emprom M24C64 at address 0x57,
reflect it in device-tree.
Signed-off-by: Grzegorz Jaszczyk
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/armada-3720-db.dts | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-db.dts
b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
index 15e923f945d4..f2435537c1d3 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
@@ -113,6 +113,12 @@
compatible = "dallas,ds1337";
reg = <0x68>;
};
+
+ eeprom@57 {
+ compatible = "atmel,24c64";
+ reg = <0x57>;
+ pagesize = <32>;
+ };
};
{
--
2.17.1
[PATCH 09/11] dts: a3700: enable dma coherence for PCIE interface
From: Stefan Chulski Enavble PCIe dma coherence for A3700 platform Signed-off-by: Stefan Chulski Signed-off-by: Konstantin Porotchkin --- arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index d5b6c0a1c54a..5c0df06bc707 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -486,6 +486,7 @@ #interrupt-cells = <1>; msi-parent = <>; msi-controller; + dma-coherent; ranges = <0x8200 0 0xe800 0 0xe800 0 0x100 /* Port 0 MEM */ 0x8100 0 0xe900 0 0xe900 0 0x1>; /* Port 0 IO*/ interrupt-map-mask = <0 0 0 7>; -- 2.17.1
[PATCH 10/11] dts: marvell: add 2 eeprom properties to A8K DB device tree
From: Ben Peled
Add on-board i2c EEPROMs U41 and U51
Signed-off-by: Ben Peled
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/armada-8040-db.dts | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts
b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
index 04241dba189e..13964193fb77 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
@@ -150,6 +150,19 @@
reg = <0x25>;
};
+ /* U51 */
+ eeprom0: eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ pagesize = <0x20>;
+ };
+
+ /* U41 */
+ eeprom1: eeprom@57 {
+ compatible = "atmel,24c64";
+ reg = <0x57>;
+ pagesize = <0x20>;
+ };
};
/* CON4 on CP0 expansion */
--
2.17.1
[PATCH 03/11] dts: mvebu: Add pin control definitions for SDIO interafce
From: Konstantin Porotchkin
Add SDIO mode pin control configration for CP0 on A8K DB.
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/armada-70x0.dtsi | 6 ++
arch/arm64/boot/dts/marvell/armada-80x0.dtsi | 6 ++
2 files changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
index 293403a1a333..179218774ba9 100644
--- a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
@@ -47,6 +47,12 @@
cp0_pinctrl: pinctrl {
compatible = "marvell,armada-7k-pinctrl";
+ sdhci_pins: sdhi-pins {
+ marvell,pins = "mpp56", "mpp57", "mpp58",
+ "mpp59", "mpp60", "mpp61", "mpp62";
+ marvell,function = "sdio";
+ };
+
nand_pins: nand-pins {
marvell,pins =
"mpp15", "mpp16", "mpp17", "mpp18",
diff --git a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
index ee67c70bf02e..64100ae204da 100644
--- a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
@@ -70,6 +70,12 @@
_syscon0 {
cp0_pinctrl: pinctrl {
compatible = "marvell,armada-8k-cpm-pinctrl";
+
+ sdhci_pins: sdhi-pins {
+ marvell,pins = "mpp56", "mpp57", "mpp58",
+ "mpp59", "mpp60", "mpp61", "mpp62";
+ marvell,function = "sdio";
+ };
};
};
--
2.17.1
[PATCH 01/11] fix: arm64: dts: replace wrong regulator on ap emmc
From: Konstantin Porotchkin
Replace wrong regulator in AP0 eMMC definition on MacchiatoBIN
board with 3.3V regulator.
The MacchiatoBIN board has no 1.8V regulator connected to AP0
eMMC (ap0_sdhci0) interface.
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
index cbcb210cb6d8..73733b4126e2 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
@@ -119,7 +119,7 @@
no-sdio;
non-removable;
status = "okay";
- vqmmc-supply = <_vddo_h>;
+ vqmmc-supply = <_3_3>;
};
_i2c0 {
--
2.17.1
[PATCH 2/4] devicetree/bindings: add support for CP110 UTMI driver
From: Konstantin Porotchkin
Add DTS binding for Marvell CP110 UTMI driver
Signed-off-by: Konstantin Porotchkin
---
Documentation/devicetree/bindings/phy/phy-mvebu-utmi.txt | 69
++--
1 file changed, 63 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/phy-mvebu-utmi.txt
b/Documentation/devicetree/bindings/phy/phy-mvebu-utmi.txt
index aa99ceec73b0..109888ba9d2d 100644
--- a/Documentation/devicetree/bindings/phy/phy-mvebu-utmi.txt
+++ b/Documentation/devicetree/bindings/phy/phy-mvebu-utmi.txt
@@ -1,30 +1,61 @@
-MVEBU A3700 UTMI PHY
-
+MVEBU UTMI PHY
+---
USB2 UTMI+ PHY controllers can be found on the following Marvell MVEBU SoCs:
* Armada 3700
+* Armada 7k/8k (on the CP110)
+* Armada CN913x (on the CP115)
On Armada 3700, there are two USB controllers, one is compatible with the USB2
and USB3 specifications and supports OTG. The other one is USB2 compliant and
only supports host mode. Both of these controllers come with a slightly
different UTMI PHY.
+On Armada 7k/8k and CN913x, there are two host and one device USB controllers.
+Each of two exiting UTMI PHYs could be connected to either USB host or USB
device
+controller.
+The USB device controller can only be connected to a single UTMI PHY port:
+0.H- USB HOST0
+UTMI PHY0 /
+0.D-0
+ \-- USB DEVICE
+1.D-1
+UTMI PHY1 \
+1.H- USB HOST1
+
+
Required Properties:
- compatible: Should be one of:
* "marvell,a3700-utmi-host-phy" for the PHY connected to
- the USB2 host-only controller.
+ the USB2 host-only controller (for Armada3700 only).
* "marvell,a3700-utmi-otg-phy" for the PHY connected to
- the USB3 and USB2 OTG capable controller.
+ the USB3 and USB2 OTG capable controller (for Armada3700 only.
+ * "marvell,cp110-utmi-phy" (for Armada 7k/8k or CN913x only).
- reg: PHY IP register range.
- marvell,usb-misc-reg: handle on the "USB miscellaneous registers" shared
region covering registers related to both the host
- controller and the PHY.
-- #phy-cells: Standard property (Documentation: phy-bindings.txt) Should be 0.
+ controller and the PHY (for Armada3700 only).
+- marvell,system-controller: should contain a phandle to the system
+controller node (for Armada 7k/8k or CN913x only)
+- #phy-cells: Standard property (Documentation: phy-bindings.txt.
+ Should be 0 (for Armada3700 only).
+
+
+Required properties (child nodes, for Armada 7k/8k/CN913x only):
+
+- reg: UTMI PHY port ID (0 or 1).
+- #phy-cells : Should be 0.
+
+
+Optional Properties (child nodes, for Armada 7k/8k/CN913x only)::
+- marvell,cp110-utmi-device-mode: request the driver to connect the UTMI PHY
+ port to USB device controller.
Example:
+Armada3700
usb2_utmi_host_phy: phy@5f000 {
compatible = "marvell,armada-3700-utmi-host-phy";
reg = <0x5f000 0x800>;
@@ -36,3 +67,29 @@ Example:
compatible = "marvell,armada-3700-usb2-host-misc", "syscon";
reg = <0x5f800 0x800>;
};
+
+Armada 7k/8k/CN913x
+
+ CP11X_LABEL(utmi): utmi@58 {
+ compatible = "marvell,cp110-utmi-phy";
+ reg = <0x58 0x2000>;
+ marvell,system-controller = <_LABEL(syscon0)>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ CP11X_LABEL(utmi0): phy@0 {
+ /* UTMI PHY port-0 is connected to USB Host
controller-0 */
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+
+ CP11X_LABEL(utmi1): phy@1 {
+ /* UTMI PHY port-1 is connected to USB device
controller */
+ reg = <1>;
+ #phy-cells = <0>;
+ marvell,cp110-utmi-device-mode;
+ };
+ };
+
+
--
2.17.1
[PATCH 3/4] arch/arm64: dts: add support for Marvell CP110 UTMI driver
From: Konstantin Porotchkin
Add support for Marvell CP110 UTMI driver in a common DTSI
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
index 994a2fce449a..5f1f5d51c881 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
@@ -275,6 +275,25 @@
};
};
+ CP11X_LABEL(utmi): utmi@58 {
+ compatible = "marvell,cp110-utmi-phy";
+ reg = <0x58 0x2000>;
+ marvell,system-controller = <_LABEL(syscon0)>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ CP11X_LABEL(utmi0): phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+
+ CP11X_LABEL(utmi1): phy@1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ };
+ };
+
CP11X_LABEL(usb3_0): usb@50 {
compatible = "marvell,armada-8k-xhci",
"generic-xhci";
--
2.17.1
[PATCH 1/4] drivers: phy: add support for Armada CP110 UTMI PHY
From: Konstantin Porotchkin Add support for Marvell CP110 UTMI PHY driver allowing the USB2 port configuration independently from the boot loader setup. The CP110/CP115 dies have 2 UTMI PHYs that could be connected to two USB host controllers or to single USB device controller. Since there is only one USB device controller on die, only one of the UTMI PHYs could work in USB device mode. Signed-off-by: Konstantin Porotchkin --- drivers/phy/marvell/Kconfig| 8 + drivers/phy/marvell/Makefile | 1 + drivers/phy/marvell/phy-mvebu-cp110-utmi.c | 372 3 files changed, 381 insertions(+) create mode 100644 drivers/phy/marvell/phy-mvebu-cp110-utmi.c diff --git a/drivers/phy/marvell/Kconfig b/drivers/phy/marvell/Kconfig index 6c96f2bf5266..9208839019bd 100644 --- a/drivers/phy/marvell/Kconfig +++ b/drivers/phy/marvell/Kconfig @@ -67,6 +67,14 @@ config PHY_MVEBU_CP110_COMPHY lanes can be used by various controllers (Ethernet, sata, usb, PCIe...). +config PHY_MVEBU_CP110_UTMI + tristate "Marvell CP110 UTMI driver" + depends on ARCH_MVEBU || COMPILE_TEST + depends on OF + select GENERIC_PHY + help + Enable this to support Marvell CP110 UTMI PHY driver. + config PHY_MVEBU_SATA def_bool y depends on ARCH_DOVE || MACH_DOVE || MACH_KIRKWOOD diff --git a/drivers/phy/marvell/Makefile b/drivers/phy/marvell/Makefile index 7f296ef02829..90862c4daa26 100644 --- a/drivers/phy/marvell/Makefile +++ b/drivers/phy/marvell/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_PHY_MVEBU_A3700_COMPHY)+= phy-mvebu-a3700-comphy.o obj-$(CONFIG_PHY_MVEBU_A3700_UTMI) += phy-mvebu-a3700-utmi.o obj-$(CONFIG_PHY_MVEBU_A38X_COMPHY)+= phy-armada38x-comphy.o obj-$(CONFIG_PHY_MVEBU_CP110_COMPHY) += phy-mvebu-cp110-comphy.o +obj-$(CONFIG_PHY_MVEBU_CP110_UTMI) += phy-mvebu-cp110-utmi.o obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o obj-$(CONFIG_PHY_PXA_28NM_HSIC)+= phy-pxa-28nm-hsic.o obj-$(CONFIG_PHY_PXA_28NM_USB2)+= phy-pxa-28nm-usb2.o diff --git a/drivers/phy/marvell/phy-mvebu-cp110-utmi.c b/drivers/phy/marvell/phy-mvebu-cp110-utmi.c new file mode 100644 index ..3a7499b24671 --- /dev/null +++ b/drivers/phy/marvell/phy-mvebu-cp110-utmi.c @@ -0,0 +1,372 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Marvell + * + * Authors: + * Konstantin Porotchkin + * + * Marvell CP110 UTMI PHY driver + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define UTMI_PHY_PORTS 2 + +/* CP110 UTMI register macro definetions */ +#define SYSCON_USB_CFG_REG 0x420 +#define USB_CFG_DEVICE_EN_MASK BIT(0) +#define USB_CFG_DEVICE_MUX_OFFSET1 +#define USB_CFG_DEVICE_MUX_MASK BIT(1) +#define USB_CFG_PLL_MASK BIT(25) + +#define SYSCON_UTMI_CFG_REG(id)(0x440 + (id) * 4) +#define UTMI_PHY_CFG_PU_MASK BIT(5) + +#define UTMI_PLL_CTRL_REG 0x0 +#define PLL_REFDIV_OFFSET0 +#define PLL_REFDIV_MASK GENMASK(6, 0) +#define PLL_REFDIV_VAL 0x5 +#define PLL_FBDIV_OFFSET 16 +#define PLL_FBDIV_MASK GENMASK(24, 16) +#define PLL_FBDIV_VAL0x60 +#define PLL_SEL_LPFR_MASKGENMASK(29, 28) +#define PLL_RDY BIT(31) +#define UTMI_CAL_CTRL_REG 0x8 +#define IMPCAL_VTH_OFFSET8 +#define IMPCAL_VTH_MASK GENMASK(10, 8) +#define IMPCAL_VTH_VAL 0x7 +#define IMPCAL_DONE BIT(23) +#define PLLCAL_DONE BIT(31) +#define UTMI_TX_CH_CTRL_REG0xC +#define DRV_EN_LS_OFFSET 12 +#define DRV_EN_LS_MASK GENMASK(15, 12) +#define IMP_SEL_LS_OFFSET16 +#define IMP_SEL_LS_MASK GENMASK(19, 16) +#define TX_AMP_OFFSET20 +#define TX_AMP_MASK GENMASK(22, 20) +#define TX_AMP_VAL 0x4 +#define UTMI_RX_CH_CTRL0_REG 0x14 +#define SQ_DET_ENBIT(15) +#define SQ_ANA_DTC_SEL BIT(28) +#define UTMI_RX_CH_CTRL1_REG 0x18 +#define SQ_AMP_CAL_OFFSET0 +#define SQ_AMP_CAL_MASK GENMASK(2, 0) +#define SQ_AMP_CAL_VAL 1 +#define SQ_AMP_CAL_ENBIT(3) +#define UTMI_CTRL_STATUS0_REG 0x24 +#define SUSPENDM BIT(22) +#define TEST_SEL
[PATCH 4/4] arch/arm64: dts: enable CP110 UTMI driver
From: Konstantin Porotchkin
Enable support for CP110 UTMI driver in Armada SoC family platform
device trees.
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/armada-7040-db.dts | 12
arch/arm64/boot/dts/marvell/armada-8040-db.dts | 18 --
arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi | 16 ++--
arch/arm64/boot/dts/marvell/cn9130-db.dts | 10 --
arch/arm64/boot/dts/marvell/cn9131-db.dts | 8 ++--
arch/arm64/boot/dts/marvell/cn9132-db.dts | 9 +++--
6 files changed, 59 insertions(+), 14 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-7040-db.dts
b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
index a7eb4e7697a2..ef792b932912 100644
--- a/arch/arm64/boot/dts/marvell/armada-7040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
@@ -218,6 +218,10 @@
};
};
+_utmi {
+ status = "okay";
+};
+
_comphy1 {
cp0_usbh0_con: connector {
compatible = "usb-a-connector";
@@ -226,8 +230,8 @@
};
_usb3_0 {
- phys = <_comphy1 0>;
- phy-names = "cp0-usb3h0-comphy";
+ phys = <_comphy1 0>, <_utmi0>;
+ phy-names = "cp0-usb3h0-comphy", "utmi";
status = "okay";
};
@@ -239,8 +243,8 @@
};
_usb3_1 {
- phys = <_comphy4 1>;
- phy-names = "cp0-usb3h1-comphy";
+ phys = <_comphy4 1>, <_utmi1>;
+ phy-names = "cp0-usb3h1-comphy", "utmi";
status = "okay";
};
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts
b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
index 09fb5256f1db..f1af6beeb9f9 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
@@ -154,8 +154,14 @@
};
/* CON9 on CP0 expansion */
+_utmi {
+ status = "okay";
+};
+
_usb3_0 {
usb-phy = <_usb3_0_phy>;
+ phys = <_utmi0>;
+ phy-names = "utmi";
status = "okay";
};
@@ -168,8 +174,8 @@
/* CON10 on CP0 expansion */
_usb3_1 {
- phys = <_comphy4 1>;
- phy-names = "cp0-usb3h1-comphy";
+ phys = <_comphy4 1>, <_utmi1>;
+ phy-names = "usb", "utmi";
status = "okay";
};
@@ -306,14 +312,22 @@
};
};
+_utmi {
+ status = "okay";
+};
+
/* CON9 on CP1 expansion */
_usb3_0 {
usb-phy = <_usb3_0_phy>;
+ phys = <_utmi0>;
+ phy-names = "utmi";
status = "okay";
};
/* CON10 on CP1 expansion */
_usb3_1 {
+ phys = <_utmi1>;
+ phy-names = "utmi";
status = "okay";
};
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
index cbcb210cb6d8..b3258a3984a3 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
@@ -259,13 +259,21 @@
vqmmc-supply = <_3_3>;
};
+_utmi {
+ status = "okay";
+};
+
_usb3_0 {
/* J38? - USB2.0 only */
+ phys = <_utmi0>;
+ phy-names = "utmi";
status = "okay";
};
_usb3_1 {
/* J38? - USB2.0 only */
+ phys = <_utmi1>;
+ phy-names = "utmi";
status = "okay";
};
@@ -364,9 +372,13 @@
};
};
+_utmi {
+ status = "okay";
+};
+
_usb3_0 {
/* CPS Lane 2 - CON7 */
- phys = <_comphy2 0>;
- phy-names = "cp1-usb3h0-comphy";
+ phys = <_comphy2 0>, <_utmi0>;
+ phy-names = "cp1-usb3h0-comphy", "utmi";
status = "okay";
};
diff --git a/arch/arm64/boot/dts/marvell/cn9130-db.dts
b/arch/arm64/boot/dts/marvell/cn9130-db.dts
index ce49a70d88a0..02218422509c 100644
--- a/arch/arm64/boot/dts/marvell/cn9130-db.dts
+++ b/arch/arm64/boot/dts/marvell/cn9130-db.dts
@@ -390,14 +390,20 @@
};
};
+_utmi {
+ status = "okay";
+};
+
_usb3_0 {
status = "okay";
usb-phy = <_usb3_0_phy0>;
- phy-names = "usb";
+ phys = <_utmi0>;
+ phy-names = "utmi";
};
_usb3_1 {
status = "okay";
usb-phy = <_usb3_0_phy1>;
- phy-names = "usb";
+ phys = <_utmi1>;
+ phy-names = "utmi";
};
diff --git a/arch/arm64/boot/dts/marvell/cn9131-db.dts
b/arch/arm64/boot/dts/marvell/cn9131-db.dts
index 3c975f98b2a3..17e189875182 100644
--- a/arch/arm64/boot/dts/marvell/cn9131-db.dts
+++ b/arch/arm64/boot/dts/marvell/cn9131-db.dts
@@ -193,10 +193,14 @@
};
/* CON58 */
+_utmi {
+ status = "okay";
+};
+
_usb3_1 {
status = "okay";
usb-phy = <_usb3_0_phy0>;
/* Generic PHY, providing serdes lanes */
- phys = <_comphy3 1>;
- phy-names = "usb";
+ phys = <_comphy3 1>, <_utmi1>;
+ phy-names = "usb", "utmi";
};
diff --git a/arch/arm64/boot/dts/marvell/cn9132-db.dts
b/arch/arm64/boot/dts/marvell/cn9132-db.dts
index 4ef0df3097ca..87da1dc3707c 100644
--- a/arch/arm64/boot/dts/marvell/cn9132-db.dts
+++ b/arch/arm64/boot/dts/marvell/cn9132-db.dts
@@ -205,9 +205,14 @@
};
};
[PATCH 0/4] Add support for CP110 UTMI PHY
From: Konstantin Porotchkin This series of patches adds a new PHY driver for supporting CP110 UTMI PHY in Linux. Currently the functionality of USB ports connected to this PHY depends on boot loader setup. The new driver eliminates kernel configuration dependency from the boot loader. Konstantin Porotchkin (4): drivers: phy: add support for Armada CP110 UTMI PHY devicetree/bindings: add support for CP110 UTMI driver arch/arm64: dts: add support for Marvell CP110 UTMI driver arch/arm64: dts: enable CP110 UTMI driver .../bindings/phy/phy-mvebu-utmi.txt | 69 +++- .../arm64/boot/dts/marvell/armada-7040-db.dts | 12 +- .../arm64/boot/dts/marvell/armada-8040-db.dts | 18 +- .../boot/dts/marvell/armada-8040-mcbin.dtsi | 16 +- arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 19 + arch/arm64/boot/dts/marvell/cn9130-db.dts | 10 +- arch/arm64/boot/dts/marvell/cn9131-db.dts | 8 +- arch/arm64/boot/dts/marvell/cn9132-db.dts | 9 +- drivers/phy/marvell/Kconfig | 8 + drivers/phy/marvell/Makefile | 1 + drivers/phy/marvell/phy-mvebu-cp110-utmi.c| 372 ++ 11 files changed, 522 insertions(+), 20 deletions(-) create mode 100644 drivers/phy/marvell/phy-mvebu-cp110-utmi.c -- 2.17.1
