[GIT PULL] clk fixes for v4.19-rc8
From: Stephen Boyd The following changes since commit bded6c03e398dc6e862dc8301fb9a60175740653: clk: x86: Set default parent to 48Mhz (2018-08-30 14:47:41 -0700) are available in the Git repository at: https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-fixes-for-linus for you to fetch changes up to 02621216e1d8a13abf1d040ff3b7ccf41b2df578: Merge tag 'sunxi-clk-fixes-for-4.19' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-fixes (2018-10-01 15:22:25 -0700) One fix for the Allwinner A10 SoC's audio PLL that wasn't properly set and generating noise. Chen-Yu Tsai (1): clk: sunxi-ng: sun4i: Set VCO and PLL bias current to lowest setting Stephen Boyd (1): Merge tag 'sunxi-clk-fixes-for-4.19' of https://git.kernel.org/.../sunxi/linux into clk-fixes drivers/clk/sunxi-ng/ccu-sun4i-a10.c | 10 +- 1 file changed, 9 insertions(+), 1 deletion(-)
[GIT PULL] clk fixes for v4.19-rc1
From: Stephen Boyd The following changes since commit 5b394b2ddf0347bef56e50c69a58773c94343ff3: Linux 4.19-rc1 (2018-08-26 14:11:59 -0700) are available in the Git repository at: https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git tags/clk-fixes-for-linus for you to fetch changes up to bded6c03e398dc6e862dc8301fb9a60175740653: clk: x86: Set default parent to 48Mhz (2018-08-30 14:47:41 -0700) Two small fixes, one for the x86 Stoney SoC to get a more accurate clk frequency and the other to fix a bad allocation in the Nuvoton NPCM7XX driver. Akshu Agrawal (1): clk: x86: Set default parent to 48Mhz Gustavo A. R. Silva (1): clk: npcm7xx: fix memory allocation drivers/clk/clk-npcm7xx.c | 4 ++-- drivers/clk/x86/clk-st.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) -- Sent by a computer through tubes
[GIT PULL] clk changes for v4.19
From: Stephen Boyd The following changes since commit 55c5e0c602c20cb6f350e5ae357cfd7e04ebb189: dt-bindings: clock: imx6ul: Do not change the clock definition order (2018-06-29 11:40:20 -0700) are available in the Git repository at: https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git tags/clk-for-linus for you to fetch changes up to ac7da1b787d9ea43680c487613269742c48d8747: Merge branches 'clk-actions-s700', 'clk-exynos-unused', 'clk-qcom-dispcc-845', 'clk-scmi-round' and 'clk-cs2000-spdx' into clk-next (2018-08-14 23:00:15 -0700) The new and exciting feature this time around is in the clk core. We've added duty cycle support to the clk API so that clk signal duty cycle ratios can be adjusted while taking into account things like clk dividers and clk tree hierarchy. So far only one SoC has implemented support for this, but I expect there will be more to come in the future. Outside of the core, we have the usual pile of clk driver updates and additions. The Amlogic meson driver got the most lines in the diffstat this time around because it added support for a whole bunch of hardware and duty cycle configuration. After that the Rockchip PX30, Qualcomm SDM845, and Renesas SoC drivers fill in a majority of the diff. We're left with the collection of non-critical fixes after that. Overall it looks pretty quiet this time. Core: - Clk duty cycle support - Proper CLK_SET_RATE_GATE support throughout the tree New Drivers: - Actions Semi Owl series S700 SoC clk driver - Qualcomm SDM845 display clock controller - i.MX6SX ocram_s clk support - Uniphier NAND, USB3 PHY, and SPI clk support - Qualcomm RPMh clk driver - i.MX7D mailbox clk support - Maxim 9485 Programmable Clock Generator - Expose 32 kHz PLL on PXA SoCs - imx6sll GPIO clk gate support - Atmel at91 I2S audio clk support - SI544/SI514 clk on/off support - i.MX6UL GPIO clock gates in CCM CCGR - Renesas Crypto Engine clocks on R-Car H3 - Renesas clk support for the new RZ/N1D SoC - Allwinner A64 display engine clock support - Support for Rockchip's PX30 SoC - Amlogic Meson axg PCIe and audio clocks - Amlogic Meson GEN CLK on gxbb, gxl and axg Updates: - Remove an unused variable from Exynos4412 ISP driver - Fix a thinko bug in SCMI clk division logic - Add missing of_node_put()s in some i.MX clk drivers - Tegra SDMMC clk jitter improvements with high speed signaling modes - SPDX tagging for qcom and cs2000-cp drivers - Stop leaking con ids in __clk_put() - Fix a corner case in fixed factor clk probing where node is in DT but parent clk is registered much later - Marvell Armada 3700 clk_pm_cpu_get_parent() had an invalid return value - i.MX clk init arrays removed in place of CLK_IS_CRITICAL - Convert to CLK_IS_CRITICAL for i.MX51/53 driver - Fix Tegra BPMP driver oops when xlating a NULL clk - Proper default configuration for vic03 and vde clks on Tegra124 - Mark Tegra memory controller clks as critical - Fix array bounds clamp in Tegra's emc determine_rate() op - Ingenic i2s bit update and allow UDC clk to gate - Fix name of aspeed SDC clk define to have only one 'CLK' - Fix i.MX6QDL video clk parent - Critical clk markings for qcom SDM845 - Fix Stratix10 mpu_free_clk and sdmmc_free_clk parents - Mark Rockchip's pclk_rkpwm_pmu as critical clock, due to it supplying the pwm used to drive the logic supply of the rk3399 core. Aapo Vienamo (1): clk: tegra: Fix includes required by fence_udelay() Alberto Panizzo (1): clk: rockchip: fix clk_i2sout parent selection bits on rk3399 Amit Daniel Kachhap (1): clk: scmi: Fix the rounding of clock rate Amit Nischal (1): clk: qcom: Enable clocks which needs to be always on for SDM845 Anders Roxell (1): clk: mvebu: armada-37xx-periph: Remove unused var num_parents Anson Huang (7): clk: imx6q: remove clks_init_on array clk: imx6sl: remove clks_init_on array clk: imx6sx: remove clks_init_on array clk: imx6ul: add GPIO clock gates clk: imx6ul: remove clks_init_on array clk: imx6sll: add GPIO LPCGs clk: imx: add ocram_s clock for i.mx6sx Codrin Ciubotariu (2): dt-bindings: clk: at91: add an I2S mux clock clk: at91: add I2S clock mux driver Daniel Mack (2): dts: clk: add devicetree bindings for MAX9485 clk: Add driver for MAX9485 Dinh Nguyen (2): clk: socfpga: stratix10: fix the parents of mpu_free_clk clk: socfpga: stratix10: fix the sdmmc_free_clk mux Dmitry Osipenko (2): clk: tegra: Mark Memory Controller clock as critical clk: tegra: emc: Avoid out-of-bounds bug Elaine Zhang (4): clk: rockchip: add dt-binding header for px30 dt-bindings: add bindings for px30 clock controller clk: rockchip: add support for half divider clk: rockchip: add clock controller for px30 Fabio
[GIT PULL] clk fixes for v4.18-rc6
From: Stephen Boyd The following changes since commit 9cc63791fad6d2624878c93f3415da77780e68a7: Merge branch 'clk-fix-imx6ul-defs' into clk-fixes (2018-06-29 11:40:29 -0700) are available in the Git repository at: https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git tags/clk-fixes-for-linus for you to fetch changes up to 565b9937f44d5ab7956339b6c105c03471ce3243: clk: aspeed: Support HPLL strapping on ast2400 (2018-07-11 09:34:25 -0700) One more round of updates for problems seen this -rc series. Drivers fixes are: - Amlogic Meson audio divider fix and CPU clk critical marking - Qualcomm multimedia GDSC marked as 'always on' to keep display working - Aspeed fixes for critical clks, resets causing clks to stay disabled, and an incorrect HPLL frequency calculation - Marvell Armada 3700 cpu clks would undervolt when switching from low frequencies to high frequencies because the voltage didn't stabilize in time so now we switch to an intermediate frequency Plus we have a core framework thinko that messed up the debugfs flag printing logic to make it not very useful. Benjamin Herrenschmidt (1): clk: aspeed: Treat a gate in reset as disabled Geert Uytterhoeven (1): clk: Really show symbolic clock flags in debugfs Gregory CLEMENT (1): clk: mvebu: armada-37xx-periph: Fix switching CPU rate from 300Mhz to 1.2GHz Jerome Brunet (1): clk: meson: audio-divider is one based Joel Stanley (2): clk: aspeed: Mark bclk (PCIe) and dclk (VGA) as critical clk: aspeed: Support HPLL strapping on ast2400 Neil Armstrong (1): clk: meson-gxbb: set fclk_div2 as CLK_IS_CRITICAL Stephen Boyd (1): Merge tag 'meson-clk-fixes-4.18-1' of https://github.com/BayLibre/clk-meson into clk-fixes Vinod Koul (1): clk: qcom: gcc-msm8996: Disable halt check on UFS tx clock Vivek Gautam (1): clk/mmcc-msm8996: Make mmagic_bimc_gdsc ALWAYS_ON drivers/clk/clk-aspeed.c | 59 +- drivers/clk/clk.c | 3 +- drivers/clk/meson/clk-audio-divider.c | 2 +- drivers/clk/meson/gxbb.c | 1 + drivers/clk/mvebu/armada-37xx-periph.c | 38 ++ drivers/clk/qcom/gcc-msm8996.c | 1 + drivers/clk/qcom/mmcc-msm8996.c| 1 + 7 files changed, 87 insertions(+), 18 deletions(-) -- Sent by a computer through tubes
[GIT PULL] clk fixes for v4.18-rc3
From: Stephen Boyd The following changes since commit ce397d215ccd07b8ae3f71db689aedb85d56ab40: Linux 4.18-rc1 (2018-06-17 08:04:49 +0900) are available in the Git repository at: https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git tags/clk-fixes-for-linus for you to fetch changes up to 9cc63791fad6d2624878c93f3415da77780e68a7: Merge branch 'clk-fix-imx6ul-defs' into clk-fixes (2018-06-29 11:40:29 -0700) The usual collection of driver fixlets: - Build cleanup/fix for the sunxi makefile that tried to save size but failed and prevented dead code elimination from working - Two Davinci clk driver fixes for a typo causing build failures in different configurations and an error check that checks the wrong variable. - Undo the DT ABI breaking imx6ul binding header shuffle that got merged this cycle. Bartosz Golaszewski (1): clk: davinci: fix a typo (which leads to build failures) Dan Carpenter (1): clk: davinci: cfgchip: testing the wrong variable Fabio Estevam (1): dt-bindings: clock: imx6ul: Do not change the clock definition order Masahiro Yamada (1): clk: sunxi-ng: replace lib-y with obj-y Stephen Boyd (2): Merge tag 'clk-davinci-fixes-4.18' of https://github.com/dlech/linux into clk-fixes Merge branch 'clk-fix-imx6ul-defs' into clk-fixes drivers/clk/Makefile | 2 +- drivers/clk/davinci/da8xx-cfgchip.c | 2 +- drivers/clk/davinci/psc.h| 2 +- drivers/clk/sunxi-ng/Makefile| 39 --- include/dt-bindings/clock/imx6ul-clock.h | 40 +++- 5 files changed, 37 insertions(+), 48 deletions(-) -- Sent by a computer through tubes
[PATCH] clk: qcom: Export clk_fabia_pll_configure()
From: Stephen Boyd
This is used by the video clk driver on sdm845 and that's a module.
Export it to prevent module build failures.
Cc: Amit Nischal
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/clk-alpha-pll.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index 9722b701fbdb..3c49a60072f1 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -885,6 +885,7 @@ void clk_fabia_pll_configure(struct clk_alpha_pll *pll,
struct regmap *regmap,
regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
}
+EXPORT_SYMBOL_GPL(clk_fabia_pll_configure);
static int alpha_pll_fabia_enable(struct clk_hw *hw)
{
--
Sent by a computer through tubes
[PATCH] clk: Return void from debug_init op
From: Stephen Boyd
We only have two users of the debug_init hook, and we recently stopped
caring about the return value from that op. Finish that off by changing
the clk_op to return void instead of int because it doesn't matter if
debugfs fails or not.
Cc: Eric Anholt
Cc: David Lechner
Cc: Sekhar Nori
Cc: Greg Kroah-Hartman
Signed-off-by: Stephen Boyd
---
Documentation/clk.txt | 2 +-
drivers/clk/bcm/clk-bcm2835.c | 25 +++--
drivers/clk/davinci/pll.c | 8 +++-
include/linux/clk-provider.h | 2 +-
4 files changed, 16 insertions(+), 21 deletions(-)
diff --git a/Documentation/clk.txt b/Documentation/clk.txt
index 511628bb3d3a..593cca5058b1 100644
--- a/Documentation/clk.txt
+++ b/Documentation/clk.txt
@@ -96,7 +96,7 @@ the operations defined in clk-provider.h::
int (*get_phase)(struct clk_hw *hw);
int (*set_phase)(struct clk_hw *hw, int degrees);
void(*init)(struct clk_hw *hw);
- int (*debug_init)(struct clk_hw *hw,
+ void(*debug_init)(struct clk_hw *hw,
struct dentry *dentry);
};
diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
index 1329440af59f..0bd62efc07f8 100644
--- a/drivers/clk/bcm/clk-bcm2835.c
+++ b/drivers/clk/bcm/clk-bcm2835.c
@@ -394,7 +394,7 @@ static unsigned long bcm2835_measure_tcnt_mux(struct
bcm2835_cprman *cprman,
return count * 1000;
}
-static int bcm2835_debugfs_regset(struct bcm2835_cprman *cprman, u32 base,
+static void bcm2835_debugfs_regset(struct bcm2835_cprman *cprman, u32 base,
struct debugfs_reg32 *regs, size_t nregs,
struct dentry *dentry)
{
@@ -402,15 +402,13 @@ static int bcm2835_debugfs_regset(struct bcm2835_cprman
*cprman, u32 base,
regset = devm_kzalloc(cprman->dev, sizeof(*regset), GFP_KERNEL);
if (!regset)
- return -ENOMEM;
+ return;
regset->regs = regs;
regset->nregs = nregs;
regset->base = cprman->regs + base;
debugfs_create_regset32("regdump", S_IRUGO, dentry, regset);
-
- return 0;
}
struct bcm2835_pll_data {
@@ -728,7 +726,7 @@ static int bcm2835_pll_set_rate(struct clk_hw *hw,
return 0;
}
-static int bcm2835_pll_debug_init(struct clk_hw *hw,
+static void bcm2835_pll_debug_init(struct clk_hw *hw,
struct dentry *dentry)
{
struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
@@ -738,7 +736,7 @@ static int bcm2835_pll_debug_init(struct clk_hw *hw,
regs = devm_kzalloc(cprman->dev, 7 * sizeof(*regs), GFP_KERNEL);
if (!regs)
- return -ENOMEM;
+ return;
regs[0].name = "cm_ctrl";
regs[0].offset = data->cm_ctrl_reg;
@@ -755,7 +753,7 @@ static int bcm2835_pll_debug_init(struct clk_hw *hw,
regs[6].name = "ana3";
regs[6].offset = data->ana_reg_base + 3 * 4;
- return bcm2835_debugfs_regset(cprman, 0, regs, 7, dentry);
+ bcm2835_debugfs_regset(cprman, 0, regs, 7, dentry);
}
static const struct clk_ops bcm2835_pll_clk_ops = {
@@ -859,8 +857,8 @@ static int bcm2835_pll_divider_set_rate(struct clk_hw *hw,
return 0;
}
-static int bcm2835_pll_divider_debug_init(struct clk_hw *hw,
- struct dentry *dentry)
+static void bcm2835_pll_divider_debug_init(struct clk_hw *hw,
+ struct dentry *dentry)
{
struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
struct bcm2835_cprman *cprman = divider->cprman;
@@ -869,14 +867,14 @@ static int bcm2835_pll_divider_debug_init(struct clk_hw
*hw,
regs = devm_kzalloc(cprman->dev, 7 * sizeof(*regs), GFP_KERNEL);
if (!regs)
- return -ENOMEM;
+ return;
regs[0].name = "cm";
regs[0].offset = data->cm_reg;
regs[1].name = "a2w";
regs[1].offset = data->a2w_reg;
- return bcm2835_debugfs_regset(cprman, 0, regs, 2, dentry);
+ bcm2835_debugfs_regset(cprman, 0, regs, 2, dentry);
}
static const struct clk_ops bcm2835_pll_divider_clk_ops = {
@@ -1252,15 +1250,14 @@ static struct debugfs_reg32
bcm2835_debugfs_clock_reg32[] = {
},
};
-static int bcm2835_clock_debug_init(struct clk_hw *hw,
+static void bcm2835_clock_debug_init(struct clk_hw *hw,
struct dentry *dentry)
{
struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
struct bcm2835_cprman *cprman = clock->cprman;
const struct bcm2835_clock_data *data = clock->data;
- return bcm2835_debugfs_regset(
- cprman, data->ctl_reg,
+ bcm2835_debugfs_regset(cprman, data->ctl_reg,
bcm2835_debug
[GIT PULL] clk fixes for v4.17-rc5
From: Stephen Boyd The following changes since commit c964cfc612b59910593fa10ee1c2673db274c9c7: Merge tag 'meson-clk-fixes-4.17-1' of https://github.com/BayLibre/clk-meson into clk-fixes (2018-05-01 14:44:16 -0700) are available in the Git repository at: https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git tags/clk-fixes-for-linus for you to fetch changes up to 9a160601f3fb6ffa196b87d1b5643646be486405: clk: stm32: fix: stm32 clock drivers are not compiled by default (2018-05-15 15:47:03 -0700) A modified revert of a patch that made new choices come out for a couple stm32 clk drivers that really always need to be there when that particular machine is compiled in and boot fix on i.MX for Stefan who noticed odd behavior from the critical flag patch that came in during the merge window. Gabriel Fernandez (1): clk: stm32: fix: stm32 clock drivers are not compiled by default Stefan Agner (1): clk: imx6ull: use OSC clock during AXI rate change drivers/clk/Kconfig | 6 ++ drivers/clk/imx/clk-imx6ul.c | 2 +- 2 files changed, 3 insertions(+), 5 deletions(-) -- Sent by a computer through tubes
[GIT PULL] clk fixes for v4.17-rc3
From: Stephen Boyd The following changes since commit 60cc43fc888428bb2f18f08997432d426a243338: Linux 4.17-rc1 (2018-04-15 18:24:20 -0700) are available in the Git repository at: https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git tags/clk-fixes-for-linus for you to fetch changes up to c964cfc612b59910593fa10ee1c2673db274c9c7: Merge tag 'meson-clk-fixes-4.17-1' of https://github.com/BayLibre/clk-meson into clk-fixes (2018-05-01 14:44:16 -0700) A handful of fixes for the stm32mp1 clk driver came in during the merge window for the driver that got merged in the merge window. Plus a warning fix for unused PM ops and a couple fixes for the meson clk driver clk names that went unnoticed with the regmap rework. There's also another fix in here for the mux rounding flag which wasn't doing what it said it did, but now it does. Arnd Bergmann (1): clk: cs2000: mark resume function as __maybe_unused Gabriel Fernandez (6): clk: stm32mp1: add missing static clk: stm32mp1: remove unused dfsdm_src[] const clk: stm32mp1: fix SAI3 & SAI4 clocks clk: stm32mp1: add missing tzc2 clock clk: stm32mp1: set stgen_k clock as critical clk: stm32mp1: remove ck_apb_dbg clock Jerome Brunet (2): clk: honor CLK_MUX_ROUND_CLOSEST in generic clk mux clk: meson: honor CLK_MUX_ROUND_CLOSEST in clk_regmap Martin Blumenstingl (2): clk: meson: meson8b: fix meson8b_fclk_div3_div clock name clk: meson: meson8b: fix meson8b_cpu_clk parent clock name Stephen Boyd (2): Merge branch 'clk-stm32mp1' into clk-fixes Merge tag 'meson-clk-fixes-4.17-1' of https://github.com/BayLibre/clk-meson into clk-fixes Yixun Lan (1): clk: meson: drop meson_aoclk_gate_regmap_ops drivers/clk/clk-cs2000-cp.c | 2 +- drivers/clk/clk-mux.c | 10 +- drivers/clk/clk-stm32mp1.c| 54 +-- drivers/clk/clk.c | 7 ++-- drivers/clk/meson/clk-regmap.c| 11 ++- drivers/clk/meson/gxbb-aoclk.h| 2 -- drivers/clk/meson/meson8b.c | 5 +-- include/dt-bindings/clock/stm32mp1-clks.h | 4 +-- include/linux/clk-provider.h | 3 ++ 9 files changed, 55 insertions(+), 43 deletions(-) -- Sent by a computer through tubes
[GIT PULL] clk changes for v4.17
From: Stephen Boyd The following changes since commit e2749bb998701e21cdb8b34486b82fc1c051ab41: reset: modify the way reset lookup works for board files (2018-03-27 10:39:47 +0200) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git tags/clk-for-linus for you to fetch changes up to b44c4ddf4a15c42a91a88aaa32b7d53cf43391cb: Merge branch 'clk-davinci' into clk-next (2018-04-06 13:38:08 -0700) The large diff this time around is from the addition of a new clk driver for the TI Davinci family of SoCs. So far those clks have been supported with a custom implementation of the clk API in the arch port instead of in the CCF. With this driver merged we're one step closer to having a single clk API implementation. The other large diff is from the Amlogic clk driver that underwent some major surgery to use regmap. Beyond that, the biggest hitter is Samsung which needed some reworks to properly handle clk provider power domains and a bunch of PLL rate updates. The core framework was fairly quiet this round, just getting some cleanups and small fixes for some of the more esoteric features. And the usual set of driver non-critical fixes, cleanups, and minor additions are here as well. Core: - Rejig clk_ops::init() to be a little earlier for phase/accuracy ops - debugfs ops macroized to shave some lines of boilerplate code - Always calculate the phase instead of caching it in clk_get_phase() - More __must_check on bulk clk APIs New Drivers: - TI's Davinci family of SoCs - Intel's Stratix10 SoC - stm32mp157 SoC - Allwinner H6 CCU - Silicon Labs SI544 clock generator chip - Renesas R-Car M3-N and V3H SoCs - i.MX6SLL SoCs Removed Drivers: - ST-Ericsson AB8540/9540 Updates: - Mediatek MT2701 and MT7622 audsys support and MT2712 updates - STM32F469 DSI and STM32F769 sdmmc2 support - GPIO clks can sleep now - Spreadtrum SC9860 RTC clks - Nvidia Tegra MBIST workarounds and various minor fixes - Rockchip phase handling fixes and a memory leak plugged - Renesas drivers switch to readl/writel from clk_readl/clk_writel - Renesas gained CPU (Z/Z2) and watchdog support - Rockchip rk3328 display clks and rk3399 1.6GHz PLL support - Qualcomm PM8921 PMIC XO buffers - Amlogic migrates to regmap APIs - TI Keystone clk latching support - Allwinner H3 and H5 video clk fixes - Broadcom BCM2835 PLLs needed another bit to enable - i.MX6SX CKO mux fix and i.MX7D Video PLL divider fix - i.MX6UL/ULL epdc_podf support - Hi3798CV200 COMBPHY0 and USB2_OTG_UTMI and phase support for eMMC Andrzej Hajda (7): clk: samsung: exynos3250: Fix PLL rates clk: samsung: exynos5250: Fix PLL rates clk: samsung: exynos5260: Fix PLL rates clk: samsung: exynos5433: Fix PLL rates clk: samsung: exynos7: Fix PLL rates clk: samsung: s3c2410: Fix PLL rates clk: samsung: Add compile time PLL rate validators Andy Shevchenko (1): clk: Re-use DEFINE_SHOW_ATTRIBUTE() macro Anson Huang (4): clk: imx: imx6sx: update cko mux options clk: imx: imx7d: correct video pll clock tree clk: imx7d: Correct dram pll type clk: imx7d: Correct ahb clk parent select Arnd Bergmann (2): clk: fix false-positive Wmaybe-uninitialized warning clk: hisilicon: mark wdt_mux_p[] as const Bai Ping (4): clk: imx: Add CLK_IS_CRITICAL flag for busy divider and busy mux clk: imx: add new gate/gate2 wrapper funtion dt-bindings: imx: update clock doc for imx6sll clk: imx: add clock driver for imx6sll Bartosz Golaszewski (1): clk: davinci: add a reset lookup table for psc0 Benjamin Gaignard (1): clk: stm32: add configuration flags for each of the stm32 drivers Boris Brezillon (1): clk: bcm2835: De-assert/assert PLL reset signal when appropriate Brian Starkey (1): clk: versatile: Remove WARNs in ->round_rate() Chanwoo Choi (1): clk: samsung: s3c: Remove unneeded enumeration Chunyan Zhang (2): dt-bindings: clocks: add APB RTC gate for SC9860 clk: sprd: add RTC gate for SC9860 Corentin Labbe (1): clk: sunxi-ng: remove select on obsolete SUNXI_CCU_X kconfig name David Lechner (19): dt-bindings: clock: Add new bindings for TI Davinci PLL clocks clk: davinci: New driver for davinci PLL clocks clk: davinci: Add platform information for TI DA830 PLL clk: davinci: Add platform information for TI DA850 PLL clk: davinci: Add platform information for TI DM355 PLL clk: davinci: Add platform information for TI DM365 PLL clk: davinci: Add platform information for TI DM644x PLL clk: davinci: Add platform information for TI DM646x PLL dt-bindings: clock: New bindings for TI Davinci PSC clk: davinci: New driver for davinci PSC clocks clk: davinci: Add platform information fo
[GIT PULL] clk fixes for v4.16-rc6
From: Stephen Boyd The following changes since commit 7928b2cbe55b2a410a0f5c1f154610059c57b1b2: Linux 4.16-rc1 (2018-02-11 15:04:29 -0800) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git tags/clk-fixes-for-linus for you to fetch changes up to 7997f3b2df751aab0b8e60149b226a32966c41ac: clk: bcm2835: Protect sections updating shared registers (2018-03-19 09:27:37 -0700) A late collection of fixes for regressions seen this release cycle. Normally I send this earlier than now but real life got in the way. Things are back to normal now. There's the normal set of SoC driver fixes: i.MX boot warning, TI display clks, allwinner clk ops being wrong (fun), driver probe badness on error paths, correctness fix for the new aspeed driver, and even a fix for a race condition in the bcm2835 clk driver. At the core framework level we also got some fixes for the clk phase API caching at the wrong time, better handling of the enabled state of orphan clks, and a fix for a newly introduced bug in how we handle rate calculations for pass-through clks. Boris Brezillon (2): clk: bcm2835: Fix ana->maskX definitions clk: bcm2835: Protect sections updating shared registers Chen-Yu Tsai (1): clk: sunxi-ng: a31: Fix CLK_OUT_* clock ops Eddie James (2): clk: aspeed: Fix is_enabled for certain clocks clk: aspeed: Prevent reset if clock is enabled Fabio Estevam (1): clk: imx51-imx53: Fix UART4/5 registration on i.MX50 and i.MX53 Jerome Brunet (2): clk: migrate the count of orphaned clocks at init clk: fix determine rate error with pass-through clock Shawn Lin (1): clk: update cached phase to respect the fact when setting phase Stephen Boyd (5): Merge tag 'sunxi-clk-fixes-for-4.16' of https://git.kernel.org/.../sunxi/linux into clk-fixes Merge tag 'clk-imx-fixes-4.16' of git://git.kernel.org/.../shawnguo/linux into clk-fixes Merge tag 'ti-clk-fixes-4.16' of https://github.com/t-kristo/linux-pm into clk-fixes Merge branch 'clk-phase' into clk-fixes Merge branch 'clk-helpers' (early part) into clk-fixes Tero Kristo (3): clk: ti: clkctrl: add support for CLK_SET_RATE_PARENT flag clk: ti: am33xx: add set-rate-parent support for display clkctrl clock clk: ti: am43xx: add set-rate-parent support for display clkctrl clock Wei Yongjun (2): clk: hisilicon: hi3660ï¼Fix potential NULL dereference in hi3660_stub_clk_probe() clk: qcom: msm8916: Fix return value check in qcom_apcs_msm8916_clk_probe() drivers/clk/bcm/clk-bcm2835.c | 12 ++--- drivers/clk/clk-aspeed.c| 28 drivers/clk/clk.c | 46 - drivers/clk/hisilicon/clk-hi3660-stub.c | 2 ++ drivers/clk/imx/clk-imx51-imx53.c | 20 +++--- drivers/clk/qcom/apcs-msm8916.c | 5 ++-- drivers/clk/sunxi-ng/ccu-sun6i-a31.c| 6 ++--- drivers/clk/ti/clk-33xx.c | 2 +- drivers/clk/ti/clk-43xx.c | 2 +- drivers/clk/ti/clkctrl.c| 2 ++ 10 files changed, 81 insertions(+), 44 deletions(-) --
