[PATCH 1/1] dmaengine: mediatek-cqdma: fix wrong register usage in mtk_cqdma_start
From: Shun-Chih Yu
This patch fixes wrong register usage in the mtk_cqdma_start. The
destination register should be MTK_CQDMA_DST2 instead.
Fixes: b1f01e48df5a ("dmaengine: mediatek: Add MediaTek Command-Queue DMA
controller for MT6765 SoC")
Signed-off-by: Shun-Chih Yu
---
drivers/dma/mediatek/mtk-cqdma.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/dma/mediatek/mtk-cqdma.c b/drivers/dma/mediatek/mtk-cqdma.c
index 131f397..8148538 100644
--- a/drivers/dma/mediatek/mtk-cqdma.c
+++ b/drivers/dma/mediatek/mtk-cqdma.c
@@ -253,7 +253,7 @@ static void mtk_cqdma_start(struct mtk_cqdma_pchan *pc,
#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
mtk_dma_set(pc, MTK_CQDMA_DST2, cvd->dest >> MTK_CQDMA_ADDR2_SHFIT);
#else
- mtk_dma_set(pc, MTK_CQDMA_SRC2, 0);
+ mtk_dma_set(pc, MTK_CQDMA_DST2, 0);
#endif
/* setup the length */
--
1.7.9.5
[PATCH v2] dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings
Add document the devicetree bindings for MediaTek Command-Queue DMA controller. Changes since v1: 1. fix wrong description and tags in the earlier patch
[PATCH v2 1/1] dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings
From: Shun-Chih Yu
Document the devicetree bindings for MediaTek Command-Queue DMA controller
which could be found on MT6765 SoC or other similar Mediatek SoCs.
Signed-off-by: Shun-Chih Yu
Reviewed-by: Rob Herring
Acked-by: Sean Wang
---
.../devicetree/bindings/dma/mtk-cqdma.txt | 31
1 file changed, 31 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/mtk-cqdma.txt
diff --git a/Documentation/devicetree/bindings/dma/mtk-cqdma.txt
b/Documentation/devicetree/bindings/dma/mtk-cqdma.txt
new file mode 100644
index 000..fb12927
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/mtk-cqdma.txt
@@ -0,0 +1,31 @@
+MediaTek Command-Queue DMA Controller
+==
+
+Required properties:
+
+- compatible: Must be "mediatek,mt6765-cqdma" for MT6765.
+- reg: Should contain the base address and length for each channel.
+- interrupts: Should contain references to the interrupts for each channel.
+- clocks: Should be the clock specifiers corresponding to the entry in
+ clock-names property.
+- clock-names: Should contain "cqdma" entries.
+- dma-channels: The number of DMA channels supported by the controller.
+- dma-requests: The number of DMA request supported by the controller.
+- #dma-cells: The length of the DMA specifier, must be <1>. This one cell
+ in dmas property of a client device represents the channel
+ number.
+Example:
+
+cqdma: dma-controller@10212000 {
+ compatible = "mediatek,mt6765-cqdma";
+ reg = <0 0x10212000 0 0x1000>;
+ interrupts = ,
+ ;
+ clocks = < CLK_IFR_CQ_DMA>;
+ clock-names = "cqdma";
+ dma-channels = <2>;
+ dma-requests = <32>;
+ #dma-cells = <1>;
+ };
+
+DMA clients must use the format described in dma/dma.txt file.
--
1.7.9.5
[PATCH 1/1] dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings
From: Shun-Chih Yu
Document the devicetree bindings for MediaTek Command-Queue DMA controller
which could be found on MT6765 SoC or other similar Mediatek SoCs.
Change-Id: I9736c8cac9be160358feeab935fabaffc5730519
Signed-off-by: Shun-Chih Yu
---
.../devicetree/bindings/dma/mtk-cqdma.txt | 31
1 file changed, 31 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/mtk-cqdma.txt
diff --git a/Documentation/devicetree/bindings/dma/mtk-cqdma.txt
b/Documentation/devicetree/bindings/dma/mtk-cqdma.txt
new file mode 100644
index 000..fb12927
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/mtk-cqdma.txt
@@ -0,0 +1,31 @@
+MediaTek Command-Queue DMA Controller
+==
+
+Required properties:
+
+- compatible: Must be "mediatek,mt6765-cqdma" for MT6765.
+- reg: Should contain the base address and length for each channel.
+- interrupts: Should contain references to the interrupts for each channel.
+- clocks: Should be the clock specifiers corresponding to the entry in
+ clock-names property.
+- clock-names: Should contain "cqdma" entries.
+- dma-channels: The number of DMA channels supported by the controller.
+- dma-requests: The number of DMA request supported by the controller.
+- #dma-cells: The length of the DMA specifier, must be <1>. This one cell
+ in dmas property of a client device represents the channel
+ number.
+Example:
+
+cqdma: dma-controller@10212000 {
+ compatible = "mediatek,mt6765-cqdma";
+ reg = <0 0x10212000 0 0x1000>;
+ interrupts = ,
+ ;
+ clocks = < CLK_IFR_CQ_DMA>;
+ clock-names = "cqdma";
+ dma-channels = <2>;
+ dma-requests = <32>;
+ #dma-cells = <1>;
+ };
+
+DMA clients must use the format described in dma/dma.txt file.
--
1.7.9.5
[PATCH] dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings
Add document the devicetree bindings for MediaTek Command-Queue DMA controller.
[PATCH 1/2] dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings
From: Shun-Chih Yu
Document the devicetree bindings for MediaTek Command-Queue DMA controller
which could be found on MT6765 SoC or other similar Mediatek SoCs.
Signed-off-by: Shun-Chih Yu
Reviewed-by: Rob Herring
---
.../devicetree/bindings/dma/mtk-cqdma.txt | 31
1 file changed, 31 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/mtk-cqdma.txt
diff --git a/Documentation/devicetree/bindings/dma/mtk-cqdma.txt
b/Documentation/devicetree/bindings/dma/mtk-cqdma.txt
new file mode 100644
index 000..fb12927
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/mtk-cqdma.txt
@@ -0,0 +1,31 @@
+MediaTek Command-Queue DMA Controller
+==
+
+Required properties:
+
+- compatible: Must be "mediatek,mt6765-cqdma" for MT6765.
+- reg: Should contain the base address and length for each channel.
+- interrupts: Should contain references to the interrupts for each channel.
+- clocks: Should be the clock specifiers corresponding to the entry in
+ clock-names property.
+- clock-names: Should contain "cqdma" entries.
+- dma-channels: The number of DMA channels supported by the controller.
+- dma-requests: The number of DMA request supported by the controller.
+- #dma-cells: The length of the DMA specifier, must be <1>. This one cell
+ in dmas property of a client device represents the channel
+ number.
+Example:
+
+cqdma: dma-controller@10212000 {
+ compatible = "mediatek,mt6765-cqdma";
+ reg = <0 0x10212000 0 0x1000>;
+ interrupts = ,
+ ;
+ clocks = < CLK_IFR_CQ_DMA>;
+ clock-names = "cqdma";
+ dma-channels = <2>;
+ dma-requests = <32>;
+ #dma-cells = <1>;
+ };
+
+DMA clients must use the format described in dma/dma.txt file.
--
1.7.9.5
[PATCH] remove redundant queue structure for Mediatek Command-Queue DMA controller
This patchset introduces support for MediaTek Command-Queue DMA controller in dt-bindings, and simplifies the controller by removing redundant structures. Main changes to the initial version: - remove redundant queue structure in mtk_cqdma_pchan - remove redundant completion management - remove redundant tasklet management - fix wrong residue assignment in mtk_cqdma_tx_status - fix typos The result of dmatest shown below: dmatest: dma0chan0-copy2: summary 5000 tests, 0 failures 3500 iops 28037 KB/s dmatest: dma0chan0-copy4: summary 5000 tests, 0 failures 3494 iops 27612 KB/s dmatest: dma0chan0-copy1: summary 5000 tests, 0 failures 3491 iops 27749 KB/s dmatest: dma0chan0-copy7: summary 5000 tests, 0 failures 3673 iops 29092 KB/s dmatest: dma0chan0-copy6: summary 5000 tests, 0 failures 3763 iops 30237 KB/s dmatest: dma0chan0-copy0: summary 5000 tests, 0 failures 3730 iops 30131 KB/s dmatest: dma0chan0-copy3: summary 5000 tests, 0 failures 3717 iops 29569 KB/s dmatest: dma0chan0-copy5: summary 5000 tests, 0 failures 3699 iops 29302 KB/s Shun-Chih Yu (2): dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings dmaengine: mediatek-cqdma: remove redundant queue structure .../devicetree/bindings/dma/mtk-cqdma.txt | 31 ++ drivers/dma/mediatek/mtk-cqdma.c | 399 +--- 2 files changed, 129 insertions(+), 301 deletions(-) create mode 100644 Documentation/devicetree/bindings/dma/mtk-cqdma.txt
[PATCH 2/2] dmaengine: mediatek-cqdma: remove redundant queue structure
From: Shun-Chih Yu
This patch introduces active_vdec to indicate the virtual descriptor
under processing by the CQDMA dmaengine, and simplify the control logic
by removing redundant queue structure, tasklets, and completion
management.
Also, wrong residue assignment in mtk_cqdma_tx_status and typos are
fixed.
Signed-off-by: Shun-Chih Yu
---
drivers/dma/mediatek/mtk-cqdma.c | 399 ++
1 file changed, 98 insertions(+), 301 deletions(-)
diff --git a/drivers/dma/mediatek/mtk-cqdma.c b/drivers/dma/mediatek/mtk-cqdma.c
index 131f397..387781b 100644
--- a/drivers/dma/mediatek/mtk-cqdma.c
+++ b/drivers/dma/mediatek/mtk-cqdma.c
@@ -22,6 +22,7 @@
#include
#include
#include
+#include
#include
#include
@@ -47,7 +48,6 @@
#define MTK_CQDMA_SRC 0x1c
#define MTK_CQDMA_DST 0x20
#define MTK_CQDMA_LEN1 0x24
-#define MTK_CQDMA_LEN2 0x28
#define MTK_CQDMA_SRC2 0x60
#define MTK_CQDMA_DST2 0x64
@@ -69,45 +69,32 @@
* descriptor (CVD)
* @vd:An instance for struct virt_dma_desc
* @len: The total data size device wants to move
- * @residue: The remaining data size device will move
* @dest: The destination address device wants to move to
* @src: The source address device wants to move from
* @ch:The pointer to the corresponding dma channel
- * @node: The lise_head struct to build link-list for VDs
- * @parent:The pointer to the parent CVD
*/
struct mtk_cqdma_vdesc {
struct virt_dma_desc vd;
size_t len;
- size_t residue;
dma_addr_t dest;
dma_addr_t src;
struct dma_chan *ch;
-
- struct list_head node;
- struct mtk_cqdma_vdesc *parent;
};
/**
* struct mtk_cqdma_pchan - The struct holding info describing physical
* channel (PC)
- * @queue: Queue for the PDs issued to this PC
+ * @active_vdesc: The pointer to the CVD which is under processing
* @base: The mapped register I/O base of this PC
* @irq: The IRQ that this PC are using
* @refcnt:Track how many VCs are using this PC
- * @tasklet: Tasklet for this PC
* @lock: Lock protect agaisting multiple VCs access PC
*/
struct mtk_cqdma_pchan {
- struct list_head queue;
+ struct mtk_cqdma_vdesc *active_vdesc;
void __iomem *base;
u32 irq;
-
refcount_t refcnt;
-
- struct tasklet_struct tasklet;
-
- /* lock to protect PC */
spinlock_t lock;
};
@@ -116,14 +103,10 @@ struct mtk_cqdma_pchan {
* channel (VC)
* @vc:An instance for struct virt_dma_chan
* @pc:The pointer to the underlying PC
- * @issue_completion: The wait for all issued descriptors completited
- * @issue_synchronize:Bool indicating channel synchronization starts
*/
struct mtk_cqdma_vchan {
struct virt_dma_chan vc;
struct mtk_cqdma_pchan *pc;
- struct completion issue_completion;
- bool issue_synchronize;
};
/**
@@ -168,7 +151,7 @@ static struct device *cqdma2dev(struct mtk_cqdma_device
*cqdma)
static u32 mtk_dma_read(struct mtk_cqdma_pchan *pc, u32 reg)
{
- return readl(pc->base + reg);
+ return readl_relaxed(pc->base + reg);
}
static void mtk_dma_write(struct mtk_cqdma_pchan *pc, u32 reg, u32 val)
@@ -202,22 +185,22 @@ static void mtk_cqdma_vdesc_free(struct virt_dma_desc *vd)
kfree(to_cqdma_vdesc(vd));
}
-static int mtk_cqdma_poll_engine_done(struct mtk_cqdma_pchan *pc, bool atomic)
+static int mtk_cqdma_poll_engine_done(struct mtk_cqdma_pchan *pc)
{
u32 status = 0;
- if (!atomic)
+ if (!in_task())
return readl_poll_timeout(pc->base + MTK_CQDMA_EN,
status,
!(status & MTK_CQDMA_EN_BIT),
MTK_CQDMA_USEC_POLL,
MTK_CQDMA_TIMEOUT_POLL);
-
- return readl_poll_timeout_atomic(pc->base + MTK_CQDMA_EN,
-status,
-!(status & MTK_CQDMA_EN_BIT),
-MTK_CQDMA_USEC_POLL,
-MTK_CQDMA_TIMEOUT_POLL);
+ else
+ return readl_poll_timeout_atomic(pc->base + MTK_CQDMA_EN,
+status,
+!(status & MTK_CQDMA_EN_BIT),
+MTK_CQDMA_USEC_POLL,
+
[PATCH v5] add support for Mediatek Command-Queue DMA controller on MT6765 SoC
This patchset introduces support for MediaTek Command-Queue DMA controller. MediaTek Command-Queue DMA controller (CQDMA) on MT6765 SoC is dedicated to memory-to-memory transfer through queue-based descriptor management. There are only 3 physical channels inside CQDMA, while the driver is extended to support 32 virtual channels for multiple dma users to issue dma requests onto the CQDMA simultaneously. dmatest result: dmatest: dma0chan0-copy2: summary 5000 tests, 0 failures 3500 iops 28037 KB/s (0) dmatest: dma0chan0-copy4: summary 5000 tests, 0 failures 3494 iops 27612 KB/s (0) dmatest: dma0chan0-copy1: summary 5000 tests, 0 failures 3491 iops 27749 KB/s (0) dmatest: dma0chan0-copy7: summary 5000 tests, 0 failures 3673 iops 29092 KB/s (0) dmatest: dma0chan0-copy6: summary 5000 tests, 0 failures 3763 iops 30237 KB/s (0) dmatest: dma0chan0-copy0: summary 5000 tests, 0 failures 3730 iops 30131 KB/s (0) dmatest: dma0chan0-copy3: summary 5000 tests, 0 failures 3717 iops 29569 KB/s (0) dmatest: dma0chan0-copy5: summary 5000 tests, 0 failures 3699 iops 29302 KB/s (0) Changes since v4: - remove redundant queue structure in mtk_cqdma_pchan - remove redundant completion management - fix wrong residue assignment in mtk_cqdma_tx_status - fix typos Changes since v3: - simplify the ISR and management on descriptors by removing tasklet and ASYNC_TX_ENABLE_CHANNEL_SWITCH - remove useless field in mtk_cqdma_vdesc structure - change dev_info to dev_dbg - fix typos Changes since v2: - fix build warning for kernel with DMA address in 32-bit Changes since v1: - remove unused macros, typos - leverage ASYNC_TX_ENABLE_CHANNEL_SWITCH to maintain DMA descriptor list Shun-Chih Yu (2): dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings dmaengine: mediatek: Add MediaTek Command-Queue DMA controller for MT6765 SoC .../devicetree/bindings/dma/mtk-cqdma.txt | 31 + drivers/dma/mediatek/Kconfig | 12 + drivers/dma/mediatek/Makefile |1 + drivers/dma/mediatek/mtk-cqdma.c | 748 4 files changed, 792 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/mtk-cqdma.txt create mode 100644 drivers/dma/mediatek/mtk-cqdma.c
[PATCH v5 2/2] dmaengine: mediatek: Add MediaTek Command-Queue DMA controller for MT6765 SoC
From: Shun-Chih Yu
MediaTek Command-Queue DMA controller (CQDMA) on MT6765 SoC is dedicated
to memory-to-memory transfer through queue based descriptor management.
There are only 3 physical channels inside CQDMA, while the driver is
extended to support 32 virtual channels for multiple dma users to issue
dma requests onto the CQDMA simultaneously.
Signed-off-by: Shun-Chih Yu
---
drivers/dma/mediatek/Kconfig | 12 +
drivers/dma/mediatek/Makefile|1 +
drivers/dma/mediatek/mtk-cqdma.c | 748 ++
3 files changed, 761 insertions(+)
create mode 100644 drivers/dma/mediatek/mtk-cqdma.c
diff --git a/drivers/dma/mediatek/Kconfig b/drivers/dma/mediatek/Kconfig
index 27bac0b..4a1582d 100644
--- a/drivers/dma/mediatek/Kconfig
+++ b/drivers/dma/mediatek/Kconfig
@@ -11,3 +11,15 @@ config MTK_HSDMA
This controller provides the channels which is dedicated to
memory-to-memory transfer to offload from CPU through ring-
based descriptor management.
+
+config MTK_CQDMA
+ tristate "MediaTek Command-Queue DMA controller support"
+ depends on ARCH_MEDIATEK || COMPILE_TEST
+ select DMA_ENGINE
+ select DMA_VIRTUAL_CHANNELS
+ help
+ Enable support for Command-Queue DMA controller on MediaTek
+ SoCs.
+
+ This controller provides the channels which is dedicated to
+ memory-to-memory transfer to offload from CPU.
diff --git a/drivers/dma/mediatek/Makefile b/drivers/dma/mediatek/Makefile
index 6e778f8..41bb381 100644
--- a/drivers/dma/mediatek/Makefile
+++ b/drivers/dma/mediatek/Makefile
@@ -1 +1,2 @@
obj-$(CONFIG_MTK_HSDMA) += mtk-hsdma.o
+obj-$(CONFIG_MTK_CQDMA) += mtk-cqdma.o
diff --git a/drivers/dma/mediatek/mtk-cqdma.c b/drivers/dma/mediatek/mtk-cqdma.c
new file mode 100644
index 000..0009260
--- /dev/null
+++ b/drivers/dma/mediatek/mtk-cqdma.c
@@ -0,0 +1,748 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018-2019 MediaTek Inc.
+
+/*
+ * Driver for MediaTek Command-Queue DMA Controller
+ *
+ * Author: Shun-Chih Yu
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "../virt-dma.h"
+
+#define MTK_CQDMA_USEC_POLL10
+#define MTK_CQDMA_TIMEOUT_POLL 1000
+#define MTK_CQDMA_DMA_BUSWIDTHSBIT(DMA_SLAVE_BUSWIDTH_4_BYTES)
+#define MTK_CQDMA_ALIGN_SIZE 1
+
+/* The default number of virtual channel */
+#define MTK_CQDMA_NR_VCHANS32
+
+/* The default number of physical channel */
+#define MTK_CQDMA_NR_PCHANS3
+
+/* Registers for underlying dma manipulation */
+#define MTK_CQDMA_INT_FLAG 0x0
+#define MTK_CQDMA_INT_EN 0x4
+#define MTK_CQDMA_EN 0x8
+#define MTK_CQDMA_RESET0xc
+#define MTK_CQDMA_FLUSH0x14
+#define MTK_CQDMA_SRC 0x1c
+#define MTK_CQDMA_DST 0x20
+#define MTK_CQDMA_LEN1 0x24
+#define MTK_CQDMA_SRC2 0x60
+#define MTK_CQDMA_DST2 0x64
+
+/* Registers setting */
+#define MTK_CQDMA_EN_BIT BIT(0)
+#define MTK_CQDMA_INT_FLAG_BIT BIT(0)
+#define MTK_CQDMA_INT_EN_BIT BIT(0)
+#define MTK_CQDMA_FLUSH_BITBIT(0)
+
+#define MTK_CQDMA_WARM_RST_BIT BIT(0)
+#define MTK_CQDMA_HARD_RST_BIT BIT(1)
+
+#define MTK_CQDMA_MAX_LEN GENMASK(27, 0)
+#define MTK_CQDMA_ADDR_LIMIT GENMASK(31, 0)
+#define MTK_CQDMA_ADDR2_SHFIT (32)
+
+/**
+ * struct mtk_cqdma_vdesc - The struct holding info describing virtual
+ * descriptor (CVD)
+ * @vd:An instance for struct virt_dma_desc
+ * @len: The total data size device wants to move
+ * @dest: The destination address device wants to move to
+ * @src: The source address device wants to move from
+ * @ch:The pointer to the corresponding dma channel
+ */
+struct mtk_cqdma_vdesc {
+ struct virt_dma_desc vd;
+ size_t len;
+ dma_addr_t dest;
+ dma_addr_t src;
+ struct dma_chan *ch;
+};
+
+/**
+ * struct mtk_cqdma_pchan - The struct holding info describing physical
+ * channel (PC)
+ * @active_vdesc: Pointer to the CVD which is under hardware
processing
+ * @base: The mapped register I/O base of this PC
+ * @irq: The IRQ that this PC are using
+ * @refcnt:Track how many VCs are using this PC
+ * @lock: Lock protect agaisting multiple VCs access PC
+ */
+struct mtk_cqdma_pchan {
+ struct mtk_cqdma_vdesc *active_vdesc;
+ void __iomem *base;
+ u32 irq;
+ refcount_t refcnt;
+ spinlock_t lock;
+};
+
+/**
+ *
[PATCH v5 1/2] dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings
From: Shun-Chih Yu
Document the devicetree bindings for MediaTek Command-Queue DMA controller
which could be found on MT6765 SoC or other similar Mediatek SoCs.
Signed-off-by: Shun-Chih Yu
Reviewed-by: Rob Herring
---
.../devicetree/bindings/dma/mtk-cqdma.txt | 31
1 file changed, 31 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/mtk-cqdma.txt
diff --git a/Documentation/devicetree/bindings/dma/mtk-cqdma.txt
b/Documentation/devicetree/bindings/dma/mtk-cqdma.txt
new file mode 100644
index 000..fb12927
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/mtk-cqdma.txt
@@ -0,0 +1,31 @@
+MediaTek Command-Queue DMA Controller
+==
+
+Required properties:
+
+- compatible: Must be "mediatek,mt6765-cqdma" for MT6765.
+- reg: Should contain the base address and length for each channel.
+- interrupts: Should contain references to the interrupts for each channel.
+- clocks: Should be the clock specifiers corresponding to the entry in
+ clock-names property.
+- clock-names: Should contain "cqdma" entries.
+- dma-channels: The number of DMA channels supported by the controller.
+- dma-requests: The number of DMA request supported by the controller.
+- #dma-cells: The length of the DMA specifier, must be <1>. This one cell
+ in dmas property of a client device represents the channel
+ number.
+Example:
+
+cqdma: dma-controller@10212000 {
+ compatible = "mediatek,mt6765-cqdma";
+ reg = <0 0x10212000 0 0x1000>;
+ interrupts = ,
+ ;
+ clocks = < CLK_IFR_CQ_DMA>;
+ clock-names = "cqdma";
+ dma-channels = <2>;
+ dma-requests = <32>;
+ #dma-cells = <1>;
+ };
+
+DMA clients must use the format described in dma/dma.txt file.
--
1.7.9.5
[PATCH 2/2] dmaengine: mediatek: Add MediaTek Command-Queue DMA controller for MT6765 SoC
From: Shun-Chih Yu
MediaTek Command-Queue DMA controller (CQDMA) on MT6765 SoC is dedicated
to memory-to-memory transfer through queue based descriptor management.
There are only 3 physical channels inside CQDMA, while the driver is
extended to support 32 virtual channels for multiple dma users to issue
dma requests onto the CQDMA simultaneously.
Change-Id: I1e8d116c5ecbbc49190ffc925cb59a0d035d886b
Signed-off-by: Shun-Chih Yu
Reviewed-by: Vinod Koul
---
drivers/dma/mediatek/Kconfig | 12 +
drivers/dma/mediatek/Makefile|1 +
drivers/dma/mediatek/mtk-cqdma.c | 867 ++
3 files changed, 880 insertions(+)
create mode 100644 drivers/dma/mediatek/mtk-cqdma.c
diff --git a/drivers/dma/mediatek/Kconfig b/drivers/dma/mediatek/Kconfig
index 27bac0b..4a1582d 100644
--- a/drivers/dma/mediatek/Kconfig
+++ b/drivers/dma/mediatek/Kconfig
@@ -11,3 +11,15 @@ config MTK_HSDMA
This controller provides the channels which is dedicated to
memory-to-memory transfer to offload from CPU through ring-
based descriptor management.
+
+config MTK_CQDMA
+ tristate "MediaTek Command-Queue DMA controller support"
+ depends on ARCH_MEDIATEK || COMPILE_TEST
+ select DMA_ENGINE
+ select DMA_VIRTUAL_CHANNELS
+ help
+ Enable support for Command-Queue DMA controller on MediaTek
+ SoCs.
+
+ This controller provides the channels which is dedicated to
+ memory-to-memory transfer to offload from CPU.
diff --git a/drivers/dma/mediatek/Makefile b/drivers/dma/mediatek/Makefile
index 6e778f8..41bb381 100644
--- a/drivers/dma/mediatek/Makefile
+++ b/drivers/dma/mediatek/Makefile
@@ -1 +1,2 @@
obj-$(CONFIG_MTK_HSDMA) += mtk-hsdma.o
+obj-$(CONFIG_MTK_CQDMA) += mtk-cqdma.o
diff --git a/drivers/dma/mediatek/mtk-cqdma.c b/drivers/dma/mediatek/mtk-cqdma.c
new file mode 100644
index 000..304eb0a
--- /dev/null
+++ b/drivers/dma/mediatek/mtk-cqdma.c
@@ -0,0 +1,867 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018-2019 MediaTek Inc.
+
+/*
+ * Driver for MediaTek Command-Queue DMA Controller
+ *
+ * Author: Shun-Chih Yu
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "../virt-dma.h"
+
+#define MTK_CQDMA_USEC_POLL10
+#define MTK_CQDMA_TIMEOUT_POLL 1000
+#define MTK_CQDMA_DMA_BUSWIDTHSBIT(DMA_SLAVE_BUSWIDTH_4_BYTES)
+#define MTK_CQDMA_ALIGN_SIZE 1
+
+/* The default number of virtual channel */
+#define MTK_CQDMA_NR_VCHANS32
+
+/* The default number of physical channel */
+#define MTK_CQDMA_NR_PCHANS3
+
+/* Registers for underlying dma manipulation */
+#define MTK_CQDMA_INT_FLAG 0x0
+#define MTK_CQDMA_INT_EN 0x4
+#define MTK_CQDMA_EN 0x8
+#define MTK_CQDMA_RESET0xc
+#define MTK_CQDMA_FLUSH0x14
+#define MTK_CQDMA_SRC 0x1c
+#define MTK_CQDMA_DST 0x20
+#define MTK_CQDMA_LEN1 0x24
+#define MTK_CQDMA_LEN2 0x28
+#define MTK_CQDMA_SRC2 0x60
+#define MTK_CQDMA_DST2 0x64
+
+/* Registers setting */
+#define MTK_CQDMA_EN_BIT BIT(0)
+#define MTK_CQDMA_INT_FLAG_BIT BIT(0)
+#define MTK_CQDMA_INT_EN_BIT BIT(0)
+#define MTK_CQDMA_FLUSH_BITBIT(0)
+
+#define MTK_CQDMA_WARM_RST_BIT BIT(0)
+#define MTK_CQDMA_HARD_RST_BIT BIT(1)
+
+#define MTK_CQDMA_MAX_LEN GENMASK(27, 0)
+#define MTK_CQDMA_ADDR_LIMIT GENMASK(31, 0)
+#define MTK_CQDMA_ADDR2_SHFIT (32)
+
+/**
+ * struct mtk_cqdma_vdesc - The struct holding info describing virtual
+ * descriptor (CVD)
+ * @vd:An instance for struct virt_dma_desc
+ * @len: The total data size device wants to move
+ * @dest: The destination address device wants to move to
+ * @src: The source address device wants to move from
+ * @ch:The pointer to the corresponding dma channel
+ * @node: To build linked-list for PC queue
+ */
+struct mtk_cqdma_vdesc {
+ struct virt_dma_desc vd;
+ size_t len;
+ dma_addr_t dest;
+ dma_addr_t src;
+ struct dma_chan *ch;
+
+ /* protected by pc.lock */
+ struct list_head node;
+};
+
+/**
+ * struct mtk_cqdma_pchan - The struct holding info describing physical
+ * channel (PC)
+ * @queue: Queue for the CVDs issued to this PC
+ * @base: The mapped register I/O base of this PC
+ * @irq: The IRQ that this PC are using
+ * @refcnt:Track how many VCs are using this PC
+ * @lock: Lock protect
[PATCH v4] add support for Mediatek Command-Queue DMA controller on MT6765 SoC
Changes since v3: - simplify the ISR and management on descriptors by removing tasklet and ASYNC_TX_ENABLE_CHANNEL_SWITCH - remove useless field in mtk_cqdma_vdesc structure - change dev_info to dev_dbg - fix typos Changes since v2: - fix build warning for kernel with DMA address in 32-bit Changes since v1: - remove unused macros, typos - leverage ASYNC_TX_ENABLE_CHANNEL_SWITCH to maintain DMA descriptor list Shun-Chih Yu (2): dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings dmaengine: mediatek: Add MediaTek Command-Queue DMA controller for MT6765 SoC .../devicetree/bindings/dma/mtk-cqdma.txt | 31 + drivers/dma/mediatek/Kconfig | 12 + drivers/dma/mediatek/Makefile | 1 + drivers/dma/mediatek/mtk-cqdma.c | 867 ++ 4 files changed, 911 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/mtk-cqdma.txt create mode 100644 drivers/dma/mediatek/mtk-cqdma.c
[PATCH 1/2] dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings
From: Shun-Chih Yu
Document the devicetree bindings for MediaTek Command-Queue DMA controller
which could be found on MT6765 SoC or other similar Mediatek SoCs.
Change-Id: I9736c8cac9be160358feeab935fabaffc5730519
Signed-off-by: Shun-Chih Yu
Reviewed-by: Rob Herring
---
.../devicetree/bindings/dma/mtk-cqdma.txt | 31
1 file changed, 31 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/mtk-cqdma.txt
diff --git a/Documentation/devicetree/bindings/dma/mtk-cqdma.txt
b/Documentation/devicetree/bindings/dma/mtk-cqdma.txt
new file mode 100644
index 000..fb12927
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/mtk-cqdma.txt
@@ -0,0 +1,31 @@
+MediaTek Command-Queue DMA Controller
+==
+
+Required properties:
+
+- compatible: Must be "mediatek,mt6765-cqdma" for MT6765.
+- reg: Should contain the base address and length for each channel.
+- interrupts: Should contain references to the interrupts for each channel.
+- clocks: Should be the clock specifiers corresponding to the entry in
+ clock-names property.
+- clock-names: Should contain "cqdma" entries.
+- dma-channels: The number of DMA channels supported by the controller.
+- dma-requests: The number of DMA request supported by the controller.
+- #dma-cells: The length of the DMA specifier, must be <1>. This one cell
+ in dmas property of a client device represents the channel
+ number.
+Example:
+
+cqdma: dma-controller@10212000 {
+ compatible = "mediatek,mt6765-cqdma";
+ reg = <0 0x10212000 0 0x1000>;
+ interrupts = ,
+ ;
+ clocks = < CLK_IFR_CQ_DMA>;
+ clock-names = "cqdma";
+ dma-channels = <2>;
+ dma-requests = <32>;
+ #dma-cells = <1>;
+ };
+
+DMA clients must use the format described in dma/dma.txt file.
--
1.7.9.5
[PATCH 1/2] dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings
From: Shun-Chih Yu
Document the devicetree bindings for MediaTek Command-Queue DMA controller
which could be found on MT6765 SoC or other similar Mediatek SoCs.
Signed-off-by: Shun-Chih Yu
Reviewed-by: Rob Herring
---
.../devicetree/bindings/dma/mtk-cqdma.txt | 31
1 file changed, 31 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/mtk-cqdma.txt
diff --git a/Documentation/devicetree/bindings/dma/mtk-cqdma.txt
b/Documentation/devicetree/bindings/dma/mtk-cqdma.txt
new file mode 100644
index 000..fb12927
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/mtk-cqdma.txt
@@ -0,0 +1,31 @@
+MediaTek Command-Queue DMA Controller
+==
+
+Required properties:
+
+- compatible: Must be "mediatek,mt6765-cqdma" for MT6765.
+- reg: Should contain the base address and length for each channel.
+- interrupts: Should contain references to the interrupts for each channel.
+- clocks: Should be the clock specifiers corresponding to the entry in
+ clock-names property.
+- clock-names: Should contain "cqdma" entries.
+- dma-channels: The number of DMA channels supported by the controller.
+- dma-requests: The number of DMA request supported by the controller.
+- #dma-cells: The length of the DMA specifier, must be <1>. This one cell
+ in dmas property of a client device represents the channel
+ number.
+Example:
+
+cqdma: dma-controller@10212000 {
+ compatible = "mediatek,mt6765-cqdma";
+ reg = <0 0x10212000 0 0x1000>;
+ interrupts = ,
+ ;
+ clocks = < CLK_IFR_CQ_DMA>;
+ clock-names = "cqdma";
+ dma-channels = <2>;
+ dma-requests = <32>;
+ #dma-cells = <1>;
+ };
+
+DMA clients must use the format described in dma/dma.txt file.
--
1.7.9.5
[PATCH 1/2] dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings
From: Shun-Chih Yu
Document the devicetree bindings for MediaTek Command-Queue DMA controller
which could be found on MT6765 SoC or other similar Mediatek SoCs.
Signed-off-by: Shun-Chih Yu
Reviewed-by: Rob Herring
---
.../devicetree/bindings/dma/mtk-cqdma.txt | 31
1 file changed, 31 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/mtk-cqdma.txt
diff --git a/Documentation/devicetree/bindings/dma/mtk-cqdma.txt
b/Documentation/devicetree/bindings/dma/mtk-cqdma.txt
new file mode 100644
index 000..fb12927
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/mtk-cqdma.txt
@@ -0,0 +1,31 @@
+MediaTek Command-Queue DMA Controller
+==
+
+Required properties:
+
+- compatible: Must be "mediatek,mt6765-cqdma" for MT6765.
+- reg: Should contain the base address and length for each channel.
+- interrupts: Should contain references to the interrupts for each channel.
+- clocks: Should be the clock specifiers corresponding to the entry in
+ clock-names property.
+- clock-names: Should contain "cqdma" entries.
+- dma-channels: The number of DMA channels supported by the controller.
+- dma-requests: The number of DMA request supported by the controller.
+- #dma-cells: The length of the DMA specifier, must be <1>. This one cell
+ in dmas property of a client device represents the channel
+ number.
+Example:
+
+cqdma: dma-controller@10212000 {
+ compatible = "mediatek,mt6765-cqdma";
+ reg = <0 0x10212000 0 0x1000>;
+ interrupts = ,
+ ;
+ clocks = < CLK_IFR_CQ_DMA>;
+ clock-names = "cqdma";
+ dma-channels = <2>;
+ dma-requests = <32>;
+ #dma-cells = <1>;
+ };
+
+DMA clients must use the format described in dma/dma.txt file.
--
1.7.9.5
[PATCH 2/2] dmaengine: mediatek: Add MediaTek Command-Queue DMA controller for MT6765 SoC
From: Shun-Chih Yu
MediaTek Command-Queue DMA controller (CQDMA) on MT6765 SoC is dedicated
to memory-to-memory transfer through queue based descriptor management.
There are only 3 physical channels inside CQDMA, while the driver is
extended to support 32 virtual channels for multiple dma users to issue
dma requests onto the CQDMA simultaneously.
Signed-off-by: Shun-Chih Yu
---
drivers/dma/mediatek/Kconfig | 13 +
drivers/dma/mediatek/Makefile|1 +
drivers/dma/mediatek/mtk-cqdma.c | 951 ++
3 files changed, 965 insertions(+)
create mode 100644 drivers/dma/mediatek/mtk-cqdma.c
diff --git a/drivers/dma/mediatek/Kconfig b/drivers/dma/mediatek/Kconfig
index 27bac0b..680fc05 100644
--- a/drivers/dma/mediatek/Kconfig
+++ b/drivers/dma/mediatek/Kconfig
@@ -11,3 +11,16 @@ config MTK_HSDMA
This controller provides the channels which is dedicated to
memory-to-memory transfer to offload from CPU through ring-
based descriptor management.
+
+config MTK_CQDMA
+ tristate "MediaTek Command-Queue DMA controller support"
+ depends on ARCH_MEDIATEK || COMPILE_TEST
+ select DMA_ENGINE
+ select DMA_VIRTUAL_CHANNELS
+ select ASYNC_TX_ENABLE_CHANNEL_SWITCH
+ help
+ Enable support for Command-Queue DMA controller on MediaTek
+ SoCs.
+
+ This controller provides the channels which is dedicated to
+ memory-to-memory transfer to offload from CPU.
diff --git a/drivers/dma/mediatek/Makefile b/drivers/dma/mediatek/Makefile
index 6e778f8..41bb381 100644
--- a/drivers/dma/mediatek/Makefile
+++ b/drivers/dma/mediatek/Makefile
@@ -1 +1,2 @@
obj-$(CONFIG_MTK_HSDMA) += mtk-hsdma.o
+obj-$(CONFIG_MTK_CQDMA) += mtk-cqdma.o
diff --git a/drivers/dma/mediatek/mtk-cqdma.c b/drivers/dma/mediatek/mtk-cqdma.c
new file mode 100644
index 000..131f397
--- /dev/null
+++ b/drivers/dma/mediatek/mtk-cqdma.c
@@ -0,0 +1,951 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018-2019 MediaTek Inc.
+
+/*
+ * Driver for MediaTek Command-Queue DMA Controller
+ *
+ * Author: Shun-Chih Yu
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "../virt-dma.h"
+
+#define MTK_CQDMA_USEC_POLL10
+#define MTK_CQDMA_TIMEOUT_POLL 1000
+#define MTK_CQDMA_DMA_BUSWIDTHSBIT(DMA_SLAVE_BUSWIDTH_4_BYTES)
+#define MTK_CQDMA_ALIGN_SIZE 1
+
+/* The default number of virtual channel */
+#define MTK_CQDMA_NR_VCHANS32
+
+/* The default number of physical channel */
+#define MTK_CQDMA_NR_PCHANS3
+
+/* Registers for underlying dma manipulation */
+#define MTK_CQDMA_INT_FLAG 0x0
+#define MTK_CQDMA_INT_EN 0x4
+#define MTK_CQDMA_EN 0x8
+#define MTK_CQDMA_RESET0xc
+#define MTK_CQDMA_FLUSH0x14
+#define MTK_CQDMA_SRC 0x1c
+#define MTK_CQDMA_DST 0x20
+#define MTK_CQDMA_LEN1 0x24
+#define MTK_CQDMA_LEN2 0x28
+#define MTK_CQDMA_SRC2 0x60
+#define MTK_CQDMA_DST2 0x64
+
+/* Registers setting */
+#define MTK_CQDMA_EN_BIT BIT(0)
+#define MTK_CQDMA_INT_FLAG_BIT BIT(0)
+#define MTK_CQDMA_INT_EN_BIT BIT(0)
+#define MTK_CQDMA_FLUSH_BITBIT(0)
+
+#define MTK_CQDMA_WARM_RST_BIT BIT(0)
+#define MTK_CQDMA_HARD_RST_BIT BIT(1)
+
+#define MTK_CQDMA_MAX_LEN GENMASK(27, 0)
+#define MTK_CQDMA_ADDR_LIMIT GENMASK(31, 0)
+#define MTK_CQDMA_ADDR2_SHFIT (32)
+
+/**
+ * struct mtk_cqdma_vdesc - The struct holding info describing virtual
+ * descriptor (CVD)
+ * @vd:An instance for struct virt_dma_desc
+ * @len: The total data size device wants to move
+ * @residue: The remaining data size device will move
+ * @dest: The destination address device wants to move to
+ * @src: The source address device wants to move from
+ * @ch:The pointer to the corresponding dma channel
+ * @node: The lise_head struct to build link-list for VDs
+ * @parent:The pointer to the parent CVD
+ */
+struct mtk_cqdma_vdesc {
+ struct virt_dma_desc vd;
+ size_t len;
+ size_t residue;
+ dma_addr_t dest;
+ dma_addr_t src;
+ struct dma_chan *ch;
+
+ struct list_head node;
+ struct mtk_cqdma_vdesc *parent;
+};
+
+/**
+ * struct mtk_cqdma_pchan - The struct holding info describing physical
+ * channel (PC)
+ * @queue: Queue for the PDs issued to this PC
+ * @base: The mapped register I/O base of this PC
+ * @irq: The
[PATCH v3] add support for Mediatek Command-Queue DMA controller on MT6765 SoC
Changes since v2: - fix build warning for kernel with DMA address in 32-bit Changes since v1: - remove unused macros, typos - leverage ASYNC_TX_ENABLE_CHANNEL_SWITCH to maintain DMA descriptor list Shun-Chih Yu (2): dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings dmaengine: mediatek: Add MediaTek Command-Queue DMA controller for MT6765 SoC .../devicetree/bindings/dma/mtk-cqdma.txt | 31 + drivers/dma/mediatek/Kconfig | 13 + drivers/dma/mediatek/Makefile |1 + drivers/dma/mediatek/mtk-cqdma.c | 951 4 files changed, 996 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/mtk-cqdma.txt create mode 100644 drivers/dma/mediatek/mtk-cqdma.c
[PATCH 2/2] dmaengine: mediatek: Add MediaTek Command-Queue DMA controller for MT6765 SoC
From: Shun-Chih Yu
MediaTek Command-Queue DMA controller (CQDMA) on MT6765 SoC is dedicated
to memory-to-memory transfer through queue based descriptor management.
There are only 3 physical channels inside CQDMA, while the driver is
extended to support 32 virtual channels for multiple dma users to issue
dma requests onto the CQDMA simultaneously.
Signed-off-by: Shun-Chih Yu
---
drivers/dma/mediatek/Kconfig | 13 +
drivers/dma/mediatek/Makefile|1 +
drivers/dma/mediatek/mtk-cqdma.c | 951 ++
3 files changed, 965 insertions(+)
create mode 100644 drivers/dma/mediatek/mtk-cqdma.c
diff --git a/drivers/dma/mediatek/Kconfig b/drivers/dma/mediatek/Kconfig
index 27bac0b..680fc05 100644
--- a/drivers/dma/mediatek/Kconfig
+++ b/drivers/dma/mediatek/Kconfig
@@ -11,3 +11,16 @@ config MTK_HSDMA
This controller provides the channels which is dedicated to
memory-to-memory transfer to offload from CPU through ring-
based descriptor management.
+
+config MTK_CQDMA
+ tristate "MediaTek Command-Queue DMA controller support"
+ depends on ARCH_MEDIATEK || COMPILE_TEST
+ select DMA_ENGINE
+ select DMA_VIRTUAL_CHANNELS
+ select ASYNC_TX_ENABLE_CHANNEL_SWITCH
+ help
+ Enable support for Command-Queue DMA controller on MediaTek
+ SoCs.
+
+ This controller provides the channels which is dedicated to
+ memory-to-memory transfer to offload from CPU.
diff --git a/drivers/dma/mediatek/Makefile b/drivers/dma/mediatek/Makefile
index 6e778f8..41bb381 100644
--- a/drivers/dma/mediatek/Makefile
+++ b/drivers/dma/mediatek/Makefile
@@ -1 +1,2 @@
obj-$(CONFIG_MTK_HSDMA) += mtk-hsdma.o
+obj-$(CONFIG_MTK_CQDMA) += mtk-cqdma.o
diff --git a/drivers/dma/mediatek/mtk-cqdma.c b/drivers/dma/mediatek/mtk-cqdma.c
new file mode 100644
index 000..131f397
--- /dev/null
+++ b/drivers/dma/mediatek/mtk-cqdma.c
@@ -0,0 +1,951 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018-2019 MediaTek Inc.
+
+/*
+ * Driver for MediaTek Command-Queue DMA Controller
+ *
+ * Author: Shun-Chih Yu
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "../virt-dma.h"
+
+#define MTK_CQDMA_USEC_POLL10
+#define MTK_CQDMA_TIMEOUT_POLL 1000
+#define MTK_CQDMA_DMA_BUSWIDTHSBIT(DMA_SLAVE_BUSWIDTH_4_BYTES)
+#define MTK_CQDMA_ALIGN_SIZE 1
+
+/* The default number of virtual channel */
+#define MTK_CQDMA_NR_VCHANS32
+
+/* The default number of physical channel */
+#define MTK_CQDMA_NR_PCHANS3
+
+/* Registers for underlying dma manipulation */
+#define MTK_CQDMA_INT_FLAG 0x0
+#define MTK_CQDMA_INT_EN 0x4
+#define MTK_CQDMA_EN 0x8
+#define MTK_CQDMA_RESET0xc
+#define MTK_CQDMA_FLUSH0x14
+#define MTK_CQDMA_SRC 0x1c
+#define MTK_CQDMA_DST 0x20
+#define MTK_CQDMA_LEN1 0x24
+#define MTK_CQDMA_LEN2 0x28
+#define MTK_CQDMA_SRC2 0x60
+#define MTK_CQDMA_DST2 0x64
+
+/* Registers setting */
+#define MTK_CQDMA_EN_BIT BIT(0)
+#define MTK_CQDMA_INT_FLAG_BIT BIT(0)
+#define MTK_CQDMA_INT_EN_BIT BIT(0)
+#define MTK_CQDMA_FLUSH_BITBIT(0)
+
+#define MTK_CQDMA_WARM_RST_BIT BIT(0)
+#define MTK_CQDMA_HARD_RST_BIT BIT(1)
+
+#define MTK_CQDMA_MAX_LEN GENMASK(27, 0)
+#define MTK_CQDMA_ADDR_LIMIT GENMASK(31, 0)
+#define MTK_CQDMA_ADDR2_SHFIT (32)
+
+/**
+ * struct mtk_cqdma_vdesc - The struct holding info describing virtual
+ * descriptor (CVD)
+ * @vd:An instance for struct virt_dma_desc
+ * @len: The total data size device wants to move
+ * @residue: The remaining data size device will move
+ * @dest: The destination address device wants to move to
+ * @src: The source address device wants to move from
+ * @ch:The pointer to the corresponding dma channel
+ * @node: The lise_head struct to build link-list for VDs
+ * @parent:The pointer to the parent CVD
+ */
+struct mtk_cqdma_vdesc {
+ struct virt_dma_desc vd;
+ size_t len;
+ size_t residue;
+ dma_addr_t dest;
+ dma_addr_t src;
+ struct dma_chan *ch;
+
+ struct list_head node;
+ struct mtk_cqdma_vdesc *parent;
+};
+
+/**
+ * struct mtk_cqdma_pchan - The struct holding info describing physical
+ * channel (PC)
+ * @queue: Queue for the PDs issued to this PC
+ * @base: The mapped register I/O base of this PC
+ * @irq: The
[PATCH v3] add support for Mediatek Command-Queue DMA controller on MT6765 SoC
Changes since v2: - fix build warning for kernel with DMA address in 32-bit Changes since v1: - remove unused macros, typos - leverage ASYNC_TX_ENABLE_CHANNEL_SWITCH to maintain DMA descriptor list Shun-Chih Yu (2): dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings dmaengine: mediatek: Add MediaTek Command-Queue DMA controller for MT6765 SoC .../devicetree/bindings/dma/mtk-cqdma.txt | 31 + drivers/dma/mediatek/Kconfig | 13 + drivers/dma/mediatek/Makefile |1 + drivers/dma/mediatek/mtk-cqdma.c | 951 4 files changed, 996 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/mtk-cqdma.txt create mode 100644 drivers/dma/mediatek/mtk-cqdma.c
[PATCH 1/2] dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings
From: Shun-Chih Yu
Document the devicetree bindings for MediaTek Command-Queue DMA controller
which could be found on MT6765 SoC or other similar Mediatek SoCs.
Signed-off-by: Shun-Chih Yu
Reviewed-by: Rob Herring
---
.../devicetree/bindings/dma/mtk-cqdma.txt | 31
1 file changed, 31 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/mtk-cqdma.txt
diff --git a/Documentation/devicetree/bindings/dma/mtk-cqdma.txt
b/Documentation/devicetree/bindings/dma/mtk-cqdma.txt
new file mode 100644
index 000..fb12927
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/mtk-cqdma.txt
@@ -0,0 +1,31 @@
+MediaTek Command-Queue DMA Controller
+==
+
+Required properties:
+
+- compatible: Must be "mediatek,mt6765-cqdma" for MT6765.
+- reg: Should contain the base address and length for each channel.
+- interrupts: Should contain references to the interrupts for each channel.
+- clocks: Should be the clock specifiers corresponding to the entry in
+ clock-names property.
+- clock-names: Should contain "cqdma" entries.
+- dma-channels: The number of DMA channels supported by the controller.
+- dma-requests: The number of DMA request supported by the controller.
+- #dma-cells: The length of the DMA specifier, must be <1>. This one cell
+ in dmas property of a client device represents the channel
+ number.
+Example:
+
+cqdma: dma-controller@10212000 {
+ compatible = "mediatek,mt6765-cqdma";
+ reg = <0 0x10212000 0 0x1000>;
+ interrupts = ,
+ ;
+ clocks = < CLK_IFR_CQ_DMA>;
+ clock-names = "cqdma";
+ dma-channels = <2>;
+ dma-requests = <32>;
+ #dma-cells = <1>;
+ };
+
+DMA clients must use the format described in dma/dma.txt file.
--
1.7.9.5
[PATCH v2] add support for Mediatek Command-Queue DMA controller on MT6765 SoC
Changes since v1: - remove unused macros, typos - leverage ASYNC_TX_ENABLE_CHANNEL_SWITCH to maintain DMA descriptor list This patchset introduces support for MediaTek Command-Queue DMA controller. MediaTek Command-Queue DMA controller (CQDMA) on MT6765 SoC is dedicated to memory-to-memory transfer through queue-based descriptor management. There are only 3 physical channels inside CQDMA, while the driver is extended to support 32 virtual channels for multiple dma users to issue dma requests onto the CQDMA simultaneously. Shun-Chih Yu (2): dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings dmaengine: mediatek: Add MediaTek Command-Queue DMA controller for MT6765 SoC .../devicetree/bindings/dma/mtk-cqdma.txt | 31 + drivers/dma/mediatek/Kconfig | 13 + drivers/dma/mediatek/Makefile |1 + drivers/dma/mediatek/mtk-cqdma.c | 943 4 files changed, 988 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/mtk-cqdma.txt create mode 100644 drivers/dma/mediatek/mtk-cqdma.c
[PATCH 1/2] dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings
From: Shun-Chih Yu
Document the devicetree bindings for MediaTek Command-Queue DMA controller
which could be found on MT6765 SoC or other similar Mediatek SoCs.
Signed-off-by: Shun-Chih Yu
Reviewed-by: Rob Herring
---
.../devicetree/bindings/dma/mtk-cqdma.txt | 31
1 file changed, 31 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/mtk-cqdma.txt
diff --git a/Documentation/devicetree/bindings/dma/mtk-cqdma.txt
b/Documentation/devicetree/bindings/dma/mtk-cqdma.txt
new file mode 100644
index 000..fb12927
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/mtk-cqdma.txt
@@ -0,0 +1,31 @@
+MediaTek Command-Queue DMA Controller
+==
+
+Required properties:
+
+- compatible: Must be "mediatek,mt6765-cqdma" for MT6765.
+- reg: Should contain the base address and length for each channel.
+- interrupts: Should contain references to the interrupts for each channel.
+- clocks: Should be the clock specifiers corresponding to the entry in
+ clock-names property.
+- clock-names: Should contain "cqdma" entries.
+- dma-channels: The number of DMA channels supported by the controller.
+- dma-requests: The number of DMA request supported by the controller.
+- #dma-cells: The length of the DMA specifier, must be <1>. This one cell
+ in dmas property of a client device represents the channel
+ number.
+Example:
+
+cqdma: dma-controller@10212000 {
+ compatible = "mediatek,mt6765-cqdma";
+ reg = <0 0x10212000 0 0x1000>;
+ interrupts = ,
+ ;
+ clocks = < CLK_IFR_CQ_DMA>;
+ clock-names = "cqdma";
+ dma-channels = <2>;
+ dma-requests = <32>;
+ #dma-cells = <1>;
+ };
+
+DMA clients must use the format described in dma/dma.txt file.
--
1.7.9.5
[PATCH v2] add support for Mediatek Command-Queue DMA controller on MT6765 SoC
Changes since v1: - remove unused macros, typos - leverage ASYNC_TX_ENABLE_CHANNEL_SWITCH to maintain DMA descriptor list This patchset introduces support for MediaTek Command-Queue DMA controller. MediaTek Command-Queue DMA controller (CQDMA) on MT6765 SoC is dedicated to memory-to-memory transfer through queue-based descriptor management. There are only 3 physical channels inside CQDMA, while the driver is extended to support 32 virtual channels for multiple dma users to issue dma requests onto the CQDMA simultaneously. Shun-Chih Yu (2): dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings dmaengine: mediatek: Add MediaTek Command-Queue DMA controller for MT6765 SoC .../devicetree/bindings/dma/mtk-cqdma.txt | 31 + drivers/dma/mediatek/Kconfig | 13 + drivers/dma/mediatek/Makefile |1 + drivers/dma/mediatek/mtk-cqdma.c | 943 4 files changed, 988 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/mtk-cqdma.txt create mode 100644 drivers/dma/mediatek/mtk-cqdma.c
[PATCH 2/2] dmaengine: mediatek: Add MediaTek Command-Queue DMA controller for MT6765 SoC
From: Shun-Chih Yu
MediaTek Command-Queue DMA controller (CQDMA) on MT6765 SoC is dedicated
to memory-to-memory transfer through queue based descriptor management.
There are only 3 physical channels inside CQDMA, while the driver is
extended to support 32 virtual channels for multiple dma users to issue
dma requests onto the CQDMA simultaneously.
Signed-off-by: Shun-Chih Yu
---
drivers/dma/mediatek/Kconfig | 13 +
drivers/dma/mediatek/Makefile|1 +
drivers/dma/mediatek/mtk-cqdma.c | 943 ++
3 files changed, 957 insertions(+)
create mode 100644 drivers/dma/mediatek/mtk-cqdma.c
diff --git a/drivers/dma/mediatek/Kconfig b/drivers/dma/mediatek/Kconfig
index 27bac0b..680fc05 100644
--- a/drivers/dma/mediatek/Kconfig
+++ b/drivers/dma/mediatek/Kconfig
@@ -11,3 +11,16 @@ config MTK_HSDMA
This controller provides the channels which is dedicated to
memory-to-memory transfer to offload from CPU through ring-
based descriptor management.
+
+config MTK_CQDMA
+ tristate "MediaTek Command-Queue DMA controller support"
+ depends on ARCH_MEDIATEK || COMPILE_TEST
+ select DMA_ENGINE
+ select DMA_VIRTUAL_CHANNELS
+ select ASYNC_TX_ENABLE_CHANNEL_SWITCH
+ help
+ Enable support for Command-Queue DMA controller on MediaTek
+ SoCs.
+
+ This controller provides the channels which is dedicated to
+ memory-to-memory transfer to offload from CPU.
diff --git a/drivers/dma/mediatek/Makefile b/drivers/dma/mediatek/Makefile
index 6e778f8..41bb381 100644
--- a/drivers/dma/mediatek/Makefile
+++ b/drivers/dma/mediatek/Makefile
@@ -1 +1,2 @@
obj-$(CONFIG_MTK_HSDMA) += mtk-hsdma.o
+obj-$(CONFIG_MTK_CQDMA) += mtk-cqdma.o
diff --git a/drivers/dma/mediatek/mtk-cqdma.c b/drivers/dma/mediatek/mtk-cqdma.c
new file mode 100644
index 000..310ecc5
--- /dev/null
+++ b/drivers/dma/mediatek/mtk-cqdma.c
@@ -0,0 +1,943 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018-2019 MediaTek Inc.
+
+/*
+ * Driver for MediaTek Command-Queue DMA Controller
+ *
+ * Author: Shun-Chih Yu
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "../virt-dma.h"
+
+#define MTK_CQDMA_USEC_POLL10
+#define MTK_CQDMA_TIMEOUT_POLL 1000
+#define MTK_CQDMA_DMA_BUSWIDTHSBIT(DMA_SLAVE_BUSWIDTH_4_BYTES)
+#define MTK_CQDMA_ALIGN_SIZE 1
+
+/* The default number of virtual channel */
+#define MTK_CQDMA_NR_VCHANS32
+
+/* The default number of physical channel */
+#define MTK_CQDMA_NR_PCHANS3
+
+/* Registers for underlying dma manipulation */
+#define MTK_CQDMA_INT_FLAG 0x0
+#define MTK_CQDMA_INT_EN 0x4
+#define MTK_CQDMA_EN 0x8
+#define MTK_CQDMA_RESET0xc
+#define MTK_CQDMA_FLUSH0x14
+#define MTK_CQDMA_SRC 0x1c
+#define MTK_CQDMA_DST 0x20
+#define MTK_CQDMA_LEN1 0x24
+#define MTK_CQDMA_LEN2 0x28
+#define MTK_CQDMA_SRC2 0x60
+#define MTK_CQDMA_DST2 0x64
+
+/* Registers setting */
+#define MTK_CQDMA_EN_BIT BIT(0)
+#define MTK_CQDMA_INT_FLAG_BIT BIT(0)
+#define MTK_CQDMA_INT_EN_BIT BIT(0)
+#define MTK_CQDMA_FLUSH_BITBIT(0)
+
+#define MTK_CQDMA_WARM_RST_BIT BIT(0)
+#define MTK_CQDMA_HARD_RST_BIT BIT(1)
+
+#define MTK_CQDMA_MAX_LEN GENMASK(27, 0)
+#define MTK_CQDMA_ADDR_LIMIT GENMASK(31, 0)
+#define MTK_CQDMA_ADDR2_SHFIT (32)
+
+/**
+ * struct mtk_cqdma_vdesc - The struct holding info describing virtual
+ * descriptor (CVD)
+ * @vd:An instance for struct virt_dma_desc
+ * @len: The total data size device wants to move
+ * @residue: The remaining data size device will move
+ * @dest: The destination address device wants to move to
+ * @src: The source address device wants to move from
+ * @ch:The pointer to the corresponding dma channel
+ * @node: The lise_head struct to build link-list for VDs
+ * @parent:The pointer to the parent CVD
+ */
+struct mtk_cqdma_vdesc {
+ struct virt_dma_desc vd;
+ size_t len;
+ size_t residue;
+ dma_addr_t dest;
+ dma_addr_t src;
+ struct dma_chan *ch;
+
+ struct list_head node;
+ struct mtk_cqdma_vdesc *parent;
+};
+
+/**
+ * struct mtk_cqdma_pchan - The struct holding info describing physical
+ * channel (PC)
+ * @queue: Queue for the PDs issued to this PC
+ * @base: The mapped register I/O base of this PC
+ * @irq: The
[PATCH 2/2] dmaengine: mediatek: Add MediaTek Command-Queue DMA controller for MT6765 SoC
From: Shun-Chih Yu
MediaTek Command-Queue DMA controller (CQDMA) on MT6765 SoC is dedicated
to memory-to-memory transfer through queue based descriptor management.
There are only 3 physical channels inside CQDMA, while the driver is
extended to support 32 virtual channels for multiple dma users to issue
dma requests onto the CQDMA simultaneously.
Signed-off-by: Shun-Chih Yu
---
drivers/dma/mediatek/Kconfig | 13 +
drivers/dma/mediatek/Makefile|1 +
drivers/dma/mediatek/mtk-cqdma.c | 943 ++
3 files changed, 957 insertions(+)
create mode 100644 drivers/dma/mediatek/mtk-cqdma.c
diff --git a/drivers/dma/mediatek/Kconfig b/drivers/dma/mediatek/Kconfig
index 27bac0b..680fc05 100644
--- a/drivers/dma/mediatek/Kconfig
+++ b/drivers/dma/mediatek/Kconfig
@@ -11,3 +11,16 @@ config MTK_HSDMA
This controller provides the channels which is dedicated to
memory-to-memory transfer to offload from CPU through ring-
based descriptor management.
+
+config MTK_CQDMA
+ tristate "MediaTek Command-Queue DMA controller support"
+ depends on ARCH_MEDIATEK || COMPILE_TEST
+ select DMA_ENGINE
+ select DMA_VIRTUAL_CHANNELS
+ select ASYNC_TX_ENABLE_CHANNEL_SWITCH
+ help
+ Enable support for Command-Queue DMA controller on MediaTek
+ SoCs.
+
+ This controller provides the channels which is dedicated to
+ memory-to-memory transfer to offload from CPU.
diff --git a/drivers/dma/mediatek/Makefile b/drivers/dma/mediatek/Makefile
index 6e778f8..41bb381 100644
--- a/drivers/dma/mediatek/Makefile
+++ b/drivers/dma/mediatek/Makefile
@@ -1 +1,2 @@
obj-$(CONFIG_MTK_HSDMA) += mtk-hsdma.o
+obj-$(CONFIG_MTK_CQDMA) += mtk-cqdma.o
diff --git a/drivers/dma/mediatek/mtk-cqdma.c b/drivers/dma/mediatek/mtk-cqdma.c
new file mode 100644
index 000..310ecc5
--- /dev/null
+++ b/drivers/dma/mediatek/mtk-cqdma.c
@@ -0,0 +1,943 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018-2019 MediaTek Inc.
+
+/*
+ * Driver for MediaTek Command-Queue DMA Controller
+ *
+ * Author: Shun-Chih Yu
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "../virt-dma.h"
+
+#define MTK_CQDMA_USEC_POLL10
+#define MTK_CQDMA_TIMEOUT_POLL 1000
+#define MTK_CQDMA_DMA_BUSWIDTHSBIT(DMA_SLAVE_BUSWIDTH_4_BYTES)
+#define MTK_CQDMA_ALIGN_SIZE 1
+
+/* The default number of virtual channel */
+#define MTK_CQDMA_NR_VCHANS32
+
+/* The default number of physical channel */
+#define MTK_CQDMA_NR_PCHANS3
+
+/* Registers for underlying dma manipulation */
+#define MTK_CQDMA_INT_FLAG 0x0
+#define MTK_CQDMA_INT_EN 0x4
+#define MTK_CQDMA_EN 0x8
+#define MTK_CQDMA_RESET0xc
+#define MTK_CQDMA_FLUSH0x14
+#define MTK_CQDMA_SRC 0x1c
+#define MTK_CQDMA_DST 0x20
+#define MTK_CQDMA_LEN1 0x24
+#define MTK_CQDMA_LEN2 0x28
+#define MTK_CQDMA_SRC2 0x60
+#define MTK_CQDMA_DST2 0x64
+
+/* Registers setting */
+#define MTK_CQDMA_EN_BIT BIT(0)
+#define MTK_CQDMA_INT_FLAG_BIT BIT(0)
+#define MTK_CQDMA_INT_EN_BIT BIT(0)
+#define MTK_CQDMA_FLUSH_BITBIT(0)
+
+#define MTK_CQDMA_WARM_RST_BIT BIT(0)
+#define MTK_CQDMA_HARD_RST_BIT BIT(1)
+
+#define MTK_CQDMA_MAX_LEN GENMASK(27, 0)
+#define MTK_CQDMA_ADDR_LIMIT GENMASK(31, 0)
+#define MTK_CQDMA_ADDR2_SHFIT (32)
+
+/**
+ * struct mtk_cqdma_vdesc - The struct holding info describing virtual
+ * descriptor (CVD)
+ * @vd:An instance for struct virt_dma_desc
+ * @len: The total data size device wants to move
+ * @residue: The remaining data size device will move
+ * @dest: The destination address device wants to move to
+ * @src: The source address device wants to move from
+ * @ch:The pointer to the corresponding dma channel
+ * @node: The lise_head struct to build link-list for VDs
+ * @parent:The pointer to the parent CVD
+ */
+struct mtk_cqdma_vdesc {
+ struct virt_dma_desc vd;
+ size_t len;
+ size_t residue;
+ dma_addr_t dest;
+ dma_addr_t src;
+ struct dma_chan *ch;
+
+ struct list_head node;
+ struct mtk_cqdma_vdesc *parent;
+};
+
+/**
+ * struct mtk_cqdma_pchan - The struct holding info describing physical
+ * channel (PC)
+ * @queue: Queue for the PDs issued to this PC
+ * @base: The mapped register I/O base of this PC
+ * @irq: The
[PATCH 2/2] dmaengine: mediatek: Add MediaTek Command-Queue DMA controller for MT6765 SoC
From: Shun-Chih Yu
MediaTek Command-Queue DMA controller (CQDMA) on MT6765 SoC is dedicated
to memory-to-memory transfer through queue based descriptor management.
There are only 3 physical channels inside CQDMA, while the driver is
extended to support 32 virtual channels for multiple dma users to issue
dma requests onto the CQDMA simultaneously.
Signed-off-by: Shun-Chih Yu
---
drivers/dma/mediatek/Kconfig | 12 +
drivers/dma/mediatek/Makefile|1 +
drivers/dma/mediatek/mtk-cqdma.c | 952 ++
3 files changed, 965 insertions(+)
create mode 100644 drivers/dma/mediatek/mtk-cqdma.c
diff --git a/drivers/dma/mediatek/Kconfig b/drivers/dma/mediatek/Kconfig
index 27bac0b..4a1582d 100644
--- a/drivers/dma/mediatek/Kconfig
+++ b/drivers/dma/mediatek/Kconfig
@@ -11,3 +11,15 @@ config MTK_HSDMA
This controller provides the channels which is dedicated to
memory-to-memory transfer to offload from CPU through ring-
based descriptor management.
+
+config MTK_CQDMA
+ tristate "MediaTek Command-Queue DMA controller support"
+ depends on ARCH_MEDIATEK || COMPILE_TEST
+ select DMA_ENGINE
+ select DMA_VIRTUAL_CHANNELS
+ help
+ Enable support for Command-Queue DMA controller on MediaTek
+ SoCs.
+
+ This controller provides the channels which is dedicated to
+ memory-to-memory transfer to offload from CPU.
diff --git a/drivers/dma/mediatek/Makefile b/drivers/dma/mediatek/Makefile
index 6e778f8..41bb381 100644
--- a/drivers/dma/mediatek/Makefile
+++ b/drivers/dma/mediatek/Makefile
@@ -1 +1,2 @@
obj-$(CONFIG_MTK_HSDMA) += mtk-hsdma.o
+obj-$(CONFIG_MTK_CQDMA) += mtk-cqdma.o
diff --git a/drivers/dma/mediatek/mtk-cqdma.c b/drivers/dma/mediatek/mtk-cqdma.c
new file mode 100644
index 000..c74aaa3
--- /dev/null
+++ b/drivers/dma/mediatek/mtk-cqdma.c
@@ -0,0 +1,952 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018-2019 MediaTek Inc.
+
+/*
+ * Driver for MediaTek Command-Queue DMA Controller
+ *
+ * Author: Shun-Chih Yu
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "../virt-dma.h"
+
+#define MTK_CQDMA_USEC_POLL10
+#define MTK_CQDMA_TIMEOUT_POLL 1000
+#define MTK_CQDMA_DMA_BUSWIDTHSBIT(DMA_SLAVE_BUSWIDTH_4_BYTES)
+#define MTK_CQDMA_ALIGN_SIZE 1
+
+/* The default number of virtual channel */
+#define MTK_CQDMA_NR_VCHANS3
+
+/* The default number of physical channel */
+#define MTK_CQDMA_NR_PCHANS3
+
+/* Registers for underlying dma manipulation */
+#define MTK_CQDMA_INT_FLAG 0x0
+#define MTK_CQDMA_INT_EN 0x4
+#define MTK_CQDMA_EN 0x8
+#define MTK_CQDMA_RESET0xc
+#define MTK_CQDMA_STOP 0x10
+#define MTK_CQDMA_FLUSH0x14
+#define MTK_CQDMA_SRC 0x1c
+#define MTK_CQDMA_DST 0x20
+#define MTK_CQDMA_LEN1 0x24
+#define MTK_CQDMA_LEN2 0x28
+#define MTK_CQDMA_SRC2 0x60
+#define MTK_CQDMA_DST2 0x64
+
+/* Registers setting */
+#define MTK_CQDMA_EN_BIT BIT(0)
+#define MTK_CQDMA_INT_FLAG_BIT BIT(0)
+#define MTK_CQDMA_INT_EN_BIT BIT(0)
+#define MTK_CQDMA_FLUSH_BITBIT(0)
+
+#define MTK_CQDMA_WARM_RST_BIT BIT(0)
+#define MTK_CQDMA_HARD_RST_BIT BIT(1)
+
+#define MTK_CQDMA_MAX_LEN (0xfff)
+#define MTK_CQDMA_ADDR_LIMIT (0x)
+#define MTK_CQDMA_ADDR2_SHFIT (32)
+
+/**
+ * struct mtk_cqdma_vdesc - The struct holding info describing physical
+ * descriptor (PD)
+ * @len: The total data size device wants to move
+ * @src: The source address device wants to move from
+ * @dest: The destination address device wants to move to
+ */
+struct mtk_cqdma_pdesc {
+ size_t len;
+ dma_addr_t src;
+ dma_addr_t dest;
+};
+
+/**
+ * struct mtk_cqdma_vdesc - The struct holding info describing virtual
+ * descriptor (VD)
+ * @vd:An instance for struct virt_dma_desc
+ * @len: The total data size device wants to move
+ * @residue: The remaining data size device will move
+ * @dest: The destination address device wants to move to
+ * @src: The source address device wants to move from
+ * @ch:The pointer to the corresponding dma channel
+ * @pd_list The array for PDs
+ * @pd_list_len The size of PD list
+ * @pd_list_ptrThe index of the PD being processed
+ * @node The lise_head struct to build link-list for VDs
+ */
+struct
[PATCH 2/2] dmaengine: mediatek: Add MediaTek Command-Queue DMA controller for MT6765 SoC
From: Shun-Chih Yu
MediaTek Command-Queue DMA controller (CQDMA) on MT6765 SoC is dedicated
to memory-to-memory transfer through queue based descriptor management.
There are only 3 physical channels inside CQDMA, while the driver is
extended to support 32 virtual channels for multiple dma users to issue
dma requests onto the CQDMA simultaneously.
Signed-off-by: Shun-Chih Yu
---
drivers/dma/mediatek/Kconfig | 12 +
drivers/dma/mediatek/Makefile|1 +
drivers/dma/mediatek/mtk-cqdma.c | 952 ++
3 files changed, 965 insertions(+)
create mode 100644 drivers/dma/mediatek/mtk-cqdma.c
diff --git a/drivers/dma/mediatek/Kconfig b/drivers/dma/mediatek/Kconfig
index 27bac0b..4a1582d 100644
--- a/drivers/dma/mediatek/Kconfig
+++ b/drivers/dma/mediatek/Kconfig
@@ -11,3 +11,15 @@ config MTK_HSDMA
This controller provides the channels which is dedicated to
memory-to-memory transfer to offload from CPU through ring-
based descriptor management.
+
+config MTK_CQDMA
+ tristate "MediaTek Command-Queue DMA controller support"
+ depends on ARCH_MEDIATEK || COMPILE_TEST
+ select DMA_ENGINE
+ select DMA_VIRTUAL_CHANNELS
+ help
+ Enable support for Command-Queue DMA controller on MediaTek
+ SoCs.
+
+ This controller provides the channels which is dedicated to
+ memory-to-memory transfer to offload from CPU.
diff --git a/drivers/dma/mediatek/Makefile b/drivers/dma/mediatek/Makefile
index 6e778f8..41bb381 100644
--- a/drivers/dma/mediatek/Makefile
+++ b/drivers/dma/mediatek/Makefile
@@ -1 +1,2 @@
obj-$(CONFIG_MTK_HSDMA) += mtk-hsdma.o
+obj-$(CONFIG_MTK_CQDMA) += mtk-cqdma.o
diff --git a/drivers/dma/mediatek/mtk-cqdma.c b/drivers/dma/mediatek/mtk-cqdma.c
new file mode 100644
index 000..c74aaa3
--- /dev/null
+++ b/drivers/dma/mediatek/mtk-cqdma.c
@@ -0,0 +1,952 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018-2019 MediaTek Inc.
+
+/*
+ * Driver for MediaTek Command-Queue DMA Controller
+ *
+ * Author: Shun-Chih Yu
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "../virt-dma.h"
+
+#define MTK_CQDMA_USEC_POLL10
+#define MTK_CQDMA_TIMEOUT_POLL 1000
+#define MTK_CQDMA_DMA_BUSWIDTHSBIT(DMA_SLAVE_BUSWIDTH_4_BYTES)
+#define MTK_CQDMA_ALIGN_SIZE 1
+
+/* The default number of virtual channel */
+#define MTK_CQDMA_NR_VCHANS3
+
+/* The default number of physical channel */
+#define MTK_CQDMA_NR_PCHANS3
+
+/* Registers for underlying dma manipulation */
+#define MTK_CQDMA_INT_FLAG 0x0
+#define MTK_CQDMA_INT_EN 0x4
+#define MTK_CQDMA_EN 0x8
+#define MTK_CQDMA_RESET0xc
+#define MTK_CQDMA_STOP 0x10
+#define MTK_CQDMA_FLUSH0x14
+#define MTK_CQDMA_SRC 0x1c
+#define MTK_CQDMA_DST 0x20
+#define MTK_CQDMA_LEN1 0x24
+#define MTK_CQDMA_LEN2 0x28
+#define MTK_CQDMA_SRC2 0x60
+#define MTK_CQDMA_DST2 0x64
+
+/* Registers setting */
+#define MTK_CQDMA_EN_BIT BIT(0)
+#define MTK_CQDMA_INT_FLAG_BIT BIT(0)
+#define MTK_CQDMA_INT_EN_BIT BIT(0)
+#define MTK_CQDMA_FLUSH_BITBIT(0)
+
+#define MTK_CQDMA_WARM_RST_BIT BIT(0)
+#define MTK_CQDMA_HARD_RST_BIT BIT(1)
+
+#define MTK_CQDMA_MAX_LEN (0xfff)
+#define MTK_CQDMA_ADDR_LIMIT (0x)
+#define MTK_CQDMA_ADDR2_SHFIT (32)
+
+/**
+ * struct mtk_cqdma_vdesc - The struct holding info describing physical
+ * descriptor (PD)
+ * @len: The total data size device wants to move
+ * @src: The source address device wants to move from
+ * @dest: The destination address device wants to move to
+ */
+struct mtk_cqdma_pdesc {
+ size_t len;
+ dma_addr_t src;
+ dma_addr_t dest;
+};
+
+/**
+ * struct mtk_cqdma_vdesc - The struct holding info describing virtual
+ * descriptor (VD)
+ * @vd:An instance for struct virt_dma_desc
+ * @len: The total data size device wants to move
+ * @residue: The remaining data size device will move
+ * @dest: The destination address device wants to move to
+ * @src: The source address device wants to move from
+ * @ch:The pointer to the corresponding dma channel
+ * @pd_list The array for PDs
+ * @pd_list_len The size of PD list
+ * @pd_list_ptrThe index of the PD being processed
+ * @node The lise_head struct to build link-list for VDs
+ */
+struct
[PATCH 1/2] dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings
From: Shun-Chih Yu
Document the devicetree bindings for MediaTek Command-Queue DMA controller
which could be found on MT6765 SoC or other similar Mediatek SoCs.
Signed-off-by: Shun-Chih Yu
---
.../devicetree/bindings/dma/mtk-cqdma.txt | 31
1 file changed, 31 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/mtk-cqdma.txt
diff --git a/Documentation/devicetree/bindings/dma/mtk-cqdma.txt
b/Documentation/devicetree/bindings/dma/mtk-cqdma.txt
new file mode 100644
index 000..fb12927
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/mtk-cqdma.txt
@@ -0,0 +1,31 @@
+MediaTek Command-Queue DMA Controller
+==
+
+Required properties:
+
+- compatible: Must be "mediatek,mt6765-cqdma" for MT6765.
+- reg: Should contain the base address and length for each channel.
+- interrupts: Should contain references to the interrupts for each channel.
+- clocks: Should be the clock specifiers corresponding to the entry in
+ clock-names property.
+- clock-names: Should contain "cqdma" entries.
+- dma-channels: The number of DMA channels supported by the controller.
+- dma-requests: The number of DMA request supported by the controller.
+- #dma-cells: The length of the DMA specifier, must be <1>. This one cell
+ in dmas property of a client device represents the channel
+ number.
+Example:
+
+cqdma: dma-controller@10212000 {
+ compatible = "mediatek,mt6765-cqdma";
+ reg = <0 0x10212000 0 0x1000>;
+ interrupts = ,
+ ;
+ clocks = < CLK_IFR_CQ_DMA>;
+ clock-names = "cqdma";
+ dma-channels = <2>;
+ dma-requests = <32>;
+ #dma-cells = <1>;
+ };
+
+DMA clients must use the format described in dma/dma.txt file.
--
1.7.9.5
[PATCH] add support for Mediatek Command-Queue DMA controller on MT6765 SoC
This patchset introduces support for MediaTek Command-Queue DMA controller. MediaTek Command-Queue DMA controller (CQDMA) on MT6765 SoC is dedicated to memory-to-memory transfer through queue-based descriptor management. There are only 3 physical channels inside CQDMA, while the driver is extended to support 32 virtual channels for multiple dma users to issue dma requests onto the CQDMA simultaneously. Shun-Chih Yu (2): dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings dmaengine: mediatek: Add MediaTek Command-Queue DMA controller for MT6765 SoC .../devicetree/bindings/dma/mtk-cqdma.txt | 31 + drivers/dma/mediatek/Kconfig | 12 + drivers/dma/mediatek/Makefile | 1 + drivers/dma/mediatek/mtk-cqdma.c | 952 + 4 files changed, 996 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/mtk-cqdma.txt create mode 100644 drivers/dma/mediatek/mtk-cqdma.c
[PATCH 1/2] dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings
From: Shun-Chih Yu
Document the devicetree bindings for MediaTek Command-Queue DMA controller
which could be found on MT6765 SoC or other similar Mediatek SoCs.
Signed-off-by: Shun-Chih Yu
---
.../devicetree/bindings/dma/mtk-cqdma.txt | 31
1 file changed, 31 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/mtk-cqdma.txt
diff --git a/Documentation/devicetree/bindings/dma/mtk-cqdma.txt
b/Documentation/devicetree/bindings/dma/mtk-cqdma.txt
new file mode 100644
index 000..fb12927
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/mtk-cqdma.txt
@@ -0,0 +1,31 @@
+MediaTek Command-Queue DMA Controller
+==
+
+Required properties:
+
+- compatible: Must be "mediatek,mt6765-cqdma" for MT6765.
+- reg: Should contain the base address and length for each channel.
+- interrupts: Should contain references to the interrupts for each channel.
+- clocks: Should be the clock specifiers corresponding to the entry in
+ clock-names property.
+- clock-names: Should contain "cqdma" entries.
+- dma-channels: The number of DMA channels supported by the controller.
+- dma-requests: The number of DMA request supported by the controller.
+- #dma-cells: The length of the DMA specifier, must be <1>. This one cell
+ in dmas property of a client device represents the channel
+ number.
+Example:
+
+cqdma: dma-controller@10212000 {
+ compatible = "mediatek,mt6765-cqdma";
+ reg = <0 0x10212000 0 0x1000>;
+ interrupts = ,
+ ;
+ clocks = < CLK_IFR_CQ_DMA>;
+ clock-names = "cqdma";
+ dma-channels = <2>;
+ dma-requests = <32>;
+ #dma-cells = <1>;
+ };
+
+DMA clients must use the format described in dma/dma.txt file.
--
1.7.9.5
[PATCH] add support for Mediatek Command-Queue DMA controller on MT6765 SoC
This patchset introduces support for MediaTek Command-Queue DMA controller. MediaTek Command-Queue DMA controller (CQDMA) on MT6765 SoC is dedicated to memory-to-memory transfer through queue-based descriptor management. There are only 3 physical channels inside CQDMA, while the driver is extended to support 32 virtual channels for multiple dma users to issue dma requests onto the CQDMA simultaneously. Shun-Chih Yu (2): dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings dmaengine: mediatek: Add MediaTek Command-Queue DMA controller for MT6765 SoC .../devicetree/bindings/dma/mtk-cqdma.txt | 31 + drivers/dma/mediatek/Kconfig | 12 + drivers/dma/mediatek/Makefile | 1 + drivers/dma/mediatek/mtk-cqdma.c | 952 + 4 files changed, 996 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/mtk-cqdma.txt create mode 100644 drivers/dma/mediatek/mtk-cqdma.c
