.dtsi | 167 +
drivers/phy/qualcomm/phy-qcom-qmp.c| 102 +
drivers/phy/qualcomm/phy-qcom-qusb2.c | 3 +
6 files changed, 299 insertions(+)
Tested this series on hk01.c1 for USB mass storage.
Tested-by: Sricharan R
[] = {
{
+ .compatible = "qcom,ipq8074-qusb2-phy",
+ .data = _phy_cfg,
+ }, {
.compatible = "qcom,msm8996-qusb2-phy",
.data = _phy_cfg,
}, {
Reviewed-by: Sricharan R
Regards,
Sricharan
Signed-off-by: Sricharan R
---
drivers/dma/qcom/bam_dma.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/dma/qcom/bam_dma.c b/drivers/dma/qcom/bam_dma.c
index 4b43844..8e90a40 100644
--- a/drivers/dma/qcom/bam_dma.c
+++ b/drivers/dma/qcom/bam_dma.c
@@ -799,6 +799,9 @@ static u32
Hi Christian,
On 6/20/2019 9:02 PM, Christian Lamparter wrote:
> Hello Sricharan,
>
> On Wednesday, June 19, 2019 4:42:11 PM CEST Sricharan R wrote:
>> On 6/15/2019 2:11 AM, Christian Lamparter wrote:
>>> On Wednesday, June 12, 2019 11:48:48 AM CEST Sricharan R
Hi Srini,
On 6/18/2019 10:20 PM, Srinivas Kandagatla wrote:
>
>
> On 18/06/2019 17:27, Sricharan R wrote:
>> The Macro's expect that buffer size is power of 2. So we are infact
>> passing the actual correct
>> size ( MAX_DESCRIPTORS + 1 = 4096)
> This will m
Hi Christian,
On 6/15/2019 2:11 AM, Christian Lamparter wrote:
> On Wednesday, June 12, 2019 11:48:48 AM CEST Sricharan R wrote:
>> Hi Christian,
>>
>> On 6/10/2019 5:45 PM, Christian Lamparter wrote:
>>> On Monday, June 10, 2019 12:09:56 PM CEST Sricha
On 6/18/2019 8:42 PM, Srinivas Kandagatla wrote:
>
>
> On 18/06/2019 15:56, Sricharan R wrote:
>> So MAX_DESCRIPTORS is used in driver for masking head/tail pointers.
>> That's why we have to pass MAX_DESCRIPTORS + 1 so that it works
>> when the Mac
Hi Srini,
On 6/18/2019 8:20 PM, Srinivas Kandagatla wrote:
> Hi Sricharan,
>
> On 18/06/2019 08:13, Sricharan R wrote:
>> Hi Srini,
>>
>> On 6/14/2019 7:50 PM, Srinivas Kandagatla wrote:
>>> For some reason arguments to most of the circular buffers
>>
f(struct bam_desc_hw) -
1)
CIRC_CNT/SPACE macros also does a size - 1, so would it not be a problem if we
just pass MAX_DESCRIPTORS ?
Regards,
Sricharan
> list_for_each_entry_safe(async_desc, tmp,
>>desc_list, desc_nod
Hi Christian,
On 6/10/2019 5:45 PM, Christian Lamparter wrote:
> On Monday, June 10, 2019 12:09:56 PM CEST Sricharan R wrote:
>> Hi Christian,
>>
>> On 6/6/2019 2:11 AM, Christian Lamparter wrote:
>>> On Wed, Jun 5, 2019 at 7:16 PM Sricharan R wrote:
>>>
Hi Bjorn,
On 6/8/2019 9:18 AM, Bjorn Andersson wrote:
> On Wed 05 Jun 10:16 PDT 2019, Sricharan R wrote:
>
>> Add initial device tree support for the Qualcomm IPQ6018 SoC and
>> CP01 evaluation board.
>>
>> Signed-off-by: Sricharan R
>> Signed-off-by: Abhi
Hi Bjorn,
On 6/8/2019 9:02 AM, Bjorn Andersson wrote:
> On Wed 05 Jun 10:15 PDT 2019, Sricharan R wrote:
>
>> This patch adds support for the global clock controller found on
>> the ipq6018 based devices.
>>
>> Signed-off-by: Sricharan R
>> Signed-off-by: anu
On 6/8/2019 8:57 AM, Bjorn Andersson wrote:
> On Wed 05 Jun 10:15 PDT 2019, Sricharan R wrote:
>
>> Signed-off-by: Sricharan R
>> Signed-off-by: speriaka
>> ---
>> Documentation/devicetree/bindings/arm/qcom.yaml | 2 ++
>> 1 file changed, 2 insertions
Hi Bjorn,
On 6/8/2019 8:56 AM, Bjorn Andersson wrote:
> On Wed 05 Jun 10:15 PDT 2019, Sricharan R wrote:
>
>> Add initial pinctrl driver to support pin configuration with
>> pinctrl framework for ipq6018.
>>
>> Signed-off-by: Sricharan R
>> Signed-off-
Hi Christian,
On 6/6/2019 2:11 AM, Christian Lamparter wrote:
> On Wed, Jun 5, 2019 at 7:16 PM Sricharan R wrote:
>>
>> Add initial device tree support for the Qualcomm IPQ6018 SoC and
>> CP01 evaluation board.
>>
>> Signed-off-by: Sricharan R
>> Signed-
Hi Sudeep,
On 6/5/2019 11:04 PM, Sudeep Holla wrote:
> On Wed, Jun 05, 2019 at 10:58:57PM +0530, Sricharan R wrote:
>> Add initial device tree support for the Qualcomm IPQ6018 SoC and
>> CP01 evaluation board.
>>
>> Signed-off-by: Sricharan R
>> Signed-off-b
Hi Marc,
On 6/5/2019 10:56 PM, Marc Zyngier wrote:
> On 05/06/2019 18:16, Sricharan R wrote:
>> Add initial device tree support for the Qualcomm IPQ6018 SoC and
>> CP01 evaluation board.
>>
>> Signed-off-by: Sricharan R
>> Signed-off-by: Abhishek Sahu
&g
This patch adds support for the global clock controller found on
the ipq6018 based devices.
Signed-off-by: Sricharan R
Signed-off-by: anusha
Signed-off-by: Abhishek Sahu
---
drivers/clk/qcom/Kconfig |9 +
drivers/clk/qcom/Makefile |1 +
drivers/clk/qcom/gcc-ipq6018.c | 5267
Signed-off-by: Sricharan R
Signed-off-by: speriaka
---
Documentation/devicetree/bindings/arm/qcom.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml
b/Documentation/devicetree/bindings/arm/qcom.yaml
index f6316ab..7b19028 100644
These configs are required for booting kernel in qcom
ipq6018 boards.
Signed-off-by: Sricharan R
---
arch/arm64/configs/defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 4d58351..abf64ee 100644
--- a/arch/arm64
Add initial pinctrl driver to support pin configuration with
pinctrl framework for ipq6018.
Signed-off-by: Sricharan R
Signed-off-by: Rajkumar Ayyasamy
Signed-off-by: speriaka
---
.../bindings/pinctrl/qcom,ipq6018-pinctrl.txt | 186 +++
drivers/pinctrl/qcom/Kconfig
Add initial device tree support for the Qualcomm IPQ6018 SoC and
CP01 evaluation board.
Signed-off-by: Sricharan R
Signed-off-by: Abhishek Sahu
---
arch/arm64/boot/dts/qcom/Makefile| 1 +
arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 35
arch/arm64/boot/dts/qcom/ipq6018
Add the compatible strings and the include file for ipq6018
gcc clock controller.
Signed-off-by: Sricharan R
Signed-off-by: anusha
Signed-off-by: Abhishek Sahu
---
.../devicetree/bindings/clock/qcom,gcc.txt | 1 +
include/dt-bindings/clock/qcom,gcc-ipq6018.h | 405
The IPQ6018 is Qualcomm’s 802.11ax SoC for Routers,
Gateways and Access Points.
This series adds minimal board boot support for ipq6018-cp01
board.
Sricharan R (6):
pinctrl: qcom: Add ipq6018 pinctrl driver
dt-bindings: qcom: Add ipq6018 bindings
clk: qcom: Add DT bindings for ipq6018 gcc
Sorry, Got sb...@codeaurora.org wrong. Will fix and repost
Regards,
Sricharan
On 6/5/2019 10:45 PM, Sricharan R wrote:
> The IPQ6018 is Qualcomm’s 802.11ax SoC for Routers,
> Gateways and Access Points.
>
> This series adds minimal board boot support for ipq6018-cp01
> board.
&
This patch adds support for the global clock controller found on
the ipq6018 based devices.
Signed-off-by: Sricharan R
Signed-off-by: anusha
Signed-off-by: Abhishek Sahu
---
drivers/clk/qcom/Kconfig |9 +
drivers/clk/qcom/Makefile |1 +
drivers/clk/qcom/gcc-ipq6018.c | 5267
These configs are required for booting kernel in qcom
ipq6018 boards.
Signed-off-by: Sricharan R
---
arch/arm64/configs/defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 4d58351..abf64ee 100644
--- a/arch/arm64
Add initial device tree support for the Qualcomm IPQ6018 SoC and
CP01 evaluation board.
Signed-off-by: Sricharan R
Signed-off-by: Abhishek Sahu
---
arch/arm64/boot/dts/qcom/Makefile| 1 +
arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 35
arch/arm64/boot/dts/qcom/ipq6018
Add the compatible strings and the include file for ipq6018
gcc clock controller.
Signed-off-by: Sricharan R
Signed-off-by: anusha
Signed-off-by: Abhishek Sahu
---
.../devicetree/bindings/clock/qcom,gcc.txt | 1 +
include/dt-bindings/clock/qcom,gcc-ipq6018.h | 405
Signed-off-by: Sricharan R
Signed-off-by: speriaka
---
Documentation/devicetree/bindings/arm/qcom.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml
b/Documentation/devicetree/bindings/arm/qcom.yaml
index f6316ab..7b19028 100644
Add initial pinctrl driver to support pin configuration with
pinctrl framework for ipq6018.
Signed-off-by: Sricharan R
Signed-off-by: Rajkumar Ayyasamy
Signed-off-by: speriaka
---
.../bindings/pinctrl/qcom,ipq6018-pinctrl.txt | 186 +++
drivers/pinctrl/qcom/Kconfig
The IPQ6018 is Qualcomm’s 802.11ax SoC for Routers,
Gateways and Access Points.
This series adds minimal board boot support for ipq6018-cp01
board.
Sricharan R (6):
pinctrl: qcom: Add ipq6018 pinctrl driver
dt-bindings: qcom: Add ipq6018 bindings
clk: qcom: Add DT bindings for ipq6018 gcc
Hi Niklas,
On 4/4/2019 10:39 AM, Niklas Cassel wrote:
> From: Sricharan R
>
> The kryo cpufreq driver reads the nvmem cell and uses that data to
> populate the opps. There are other qcom cpufreq socs like krait which
> does similar thing. Except for the interpretation of the re
Hi Niklas,
On 10/22/2018 9:00 PM, Niklas Cassel wrote:
> On Mon, Oct 22, 2018 at 09:39:03AM +0530, Sricharan R wrote:
>> Hi Stephen,
>>
>> On 10/18/2018 1:46 AM, Stephen Boyd wrote:
>>> Quoting Stephen Boyd (2018-10-17 08:44:12)
>>>>
Hi Niklas,
On 10/22/2018 9:00 PM, Niklas Cassel wrote:
> On Mon, Oct 22, 2018 at 09:39:03AM +0530, Sricharan R wrote:
>> Hi Stephen,
>>
>> On 10/18/2018 1:46 AM, Stephen Boyd wrote:
>>> Quoting Stephen Boyd (2018-10-17 08:44:12)
>>>>
Hi Stephen,
On 10/18/2018 1:46 AM, Stephen Boyd wrote:
> Quoting Stephen Boyd (2018-10-17 08:44:12)
>> Quoting Sricharan R (2018-09-20 06:03:31)
>>>
>>>
>>> On 9/20/2018 1:54 AM, Craig wrote:
>>>> Yup, this patch seems to have fixed the hi
Hi Stephen,
On 10/18/2018 1:46 AM, Stephen Boyd wrote:
> Quoting Stephen Boyd (2018-10-17 08:44:12)
>> Quoting Sricharan R (2018-09-20 06:03:31)
>>>
>>>
>>> On 9/20/2018 1:54 AM, Craig wrote:
>>>> Yup, this patch seems to have fixed the hi
On 9/20/2018 1:54 AM, Craig wrote:
> Yup, this patch seems to have fixed the higher frequencies from the quick
> test I did.
>
Thanks !!. Can i take that as
Tested-by: Craig Tatlor ?
Regards,
Sricharan
> On 7 September 2018 15:28:53 BST, Craig T
On 9/20/2018 1:54 AM, Craig wrote:
> Yup, this patch seems to have fixed the higher frequencies from the quick
> test I did.
>
Thanks !!. Can i take that as
Tested-by: Craig Tatlor ?
Regards,
Sricharan
> On 7 September 2018 15:28:53 BST, Craig T
On 9/20/2018 1:54 AM, Craig wrote:
> Yup, this patch seems to have fixed the higher frequencies from the quick
> test I did.
>
Thanks !!. Can i take that as Craig Tatlor ?
Regards,
Sricharan
tested-by:
> On 7 September 2018 15:28:53 BST, Craig Tatlor wrote:
&
On 9/20/2018 1:54 AM, Craig wrote:
> Yup, this patch seems to have fixed the higher frequencies from the quick
> test I did.
>
Thanks !!. Can i take that as Craig Tatlor ?
Regards,
Sricharan
tested-by:
> On 7 September 2018 15:28:53 BST, Craig Tatlor wrote:
&
fine ?
> Sorry, i could not get hold of a 8974 device. So in-case if you still
> have the issues with higher frequencies, can you give a quick debug
> and report. That would be of great help.
>
Ping on this ..
Regards,
Sricharan
> Regards,
> Sricharan
>
fine ?
> Sorry, i could not get hold of a 8974 device. So in-case if you still
> have the issues with higher frequencies, can you give a quick debug
> and report. That would be of great help.
>
Ping on this ..
Regards,
Sricharan
> Regards,
> Sricharan
>
Hi Rob,
On 8/17/2018 8:39 PM, Rob Herring wrote:
> Hi, this email is from Rob's (experimental) review bot. I found a couple
> of common problems with your patch. Please see below.
>
> On Tue, 14 Aug 2018 17:42:32 +0530, Sricharan R wrote:
>> The kryo cpufreq driver reads the n
Hi Rob,
On 8/17/2018 8:39 PM, Rob Herring wrote:
> Hi, this email is from Rob's (experimental) review bot. I found a couple
> of common problems with your patch. Please see below.
>
> On Tue, 14 Aug 2018 17:42:32 +0530, Sricharan R wrote:
>> The kryo cpufreq driver reads the n
Hi Craig,
On 8/14/2018 5:42 PM, Sricharan R wrote:
> [v12]
> * Added my signed-off that was missing in some patches.
> * Added Bjorn's acked that i missed earlier.
>
Can you give this a try on your 8974 device and check if the
pvs version reporting, scaling for higher
Hi Craig,
On 8/14/2018 5:42 PM, Sricharan R wrote:
> [v12]
> * Added my signed-off that was missing in some patches.
> * Added Bjorn's acked that i missed earlier.
>
Can you give this a try on your 8974 device and check if the
pvs version reporting, scaling for higher
From: Stephen Boyd
Describe the HFPLLs present on IPQ806X devices.
Signed-off-by: Stephen Boyd
Signed-off-by: Sricharan R
---
drivers/clk/qcom/gcc-ipq806x.c | 82 ++
1 file changed, 82 insertions(+)
diff --git a/drivers/clk/qcom/gcc-ipq806x.c b
From: Stephen Boyd
Describe the HFPLLs present on IPQ806X devices.
Signed-off-by: Stephen Boyd
Signed-off-by: Sricharan R
---
drivers/clk/qcom/gcc-ipq806x.c | 82 ++
1 file changed, 82 insertions(+)
diff --git a/drivers/clk/qcom/gcc-ipq806x.c b
these clocks.
Signed-off-by: Stephen Boyd
Signed-off-by: Sricharan R
---
drivers/clk/qcom/Kconfig | 4 ++
drivers/clk/qcom/Makefile| 1 +
drivers/clk/qcom/clk-krait.c | 124 +++
drivers/clk/qcom/clk-krait.h | 37 +
4 files changed, 166
.
Signed-off-by: Sricharan R
---
.../{kryo-cpufreq.txt => qcom-nvmem-cpufreq.txt} | 6 +-
drivers/cpufreq/Kconfig.arm| 4 +-
drivers/cpufreq/Makefile | 2 +-
.../{qcom-cpufreq-kryo.c => qcom-cpufreq-nvmem.c} | 124 -
4
to the safe parent in the PRE_RATE_CHANGE notifier
and back to the original parent in the POST_RATE_CHANGE notifier.
Signed-off-by: Sricharan R
---
drivers/clk/qcom/clk-krait.c | 2 ++
drivers/clk/qcom/clk-krait.h | 3 +++
drivers/clk/qcom/krait-cc.c | 56
these clocks.
Signed-off-by: Stephen Boyd
Signed-off-by: Sricharan R
---
drivers/clk/qcom/Kconfig | 4 ++
drivers/clk/qcom/Makefile| 1 +
drivers/clk/qcom/clk-krait.c | 124 +++
drivers/clk/qcom/clk-krait.h | 37 +
4 files changed, 166
.
Signed-off-by: Sricharan R
---
.../{kryo-cpufreq.txt => qcom-nvmem-cpufreq.txt} | 6 +-
drivers/cpufreq/Kconfig.arm| 4 +-
drivers/cpufreq/Makefile | 2 +-
.../{qcom-cpufreq-kryo.c => qcom-cpufreq-nvmem.c} | 124 -
4
to the safe parent in the PRE_RATE_CHANGE notifier
and back to the original parent in the POST_RATE_CHANGE notifier.
Signed-off-by: Sricharan R
---
drivers/clk/qcom/clk-krait.c | 2 ++
drivers/clk/qcom/clk-krait.h | 3 +++
drivers/clk/qcom/krait-cc.c | 56
From: Stephen Boyd
The ACC and GCC regions present in KPSSv1 contain registers to
control clocks and power to each Krait CPU and L2. Documenting
the bindings here.
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
Signed-off-by: Sricharan R
---
.../devicetree/bindings/arm/msm/qcom,kpss
From: Stephen Boyd
The ACC and GCC regions present in KPSSv1 contain registers to
control clocks and power to each Krait CPU and L2. Documenting
the bindings here.
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
Signed-off-by: Sricharan R
---
.../devicetree/bindings/arm/msm/qcom,kpss
adding support for krait cores here.
Signed-off-by: Sricharan R
---
.../devicetree/bindings/opp/qcom-nvmem-cpufreq.txt | 3 +-
drivers/cpufreq/Kconfig.arm| 2 +-
drivers/cpufreq/cpufreq-dt-platdev.c | 5 +
drivers/cpufreq/qcom-cpufreq-nvmem.c
-off-by: Stephen Boyd
Signed-off-by: Sricharan R
---
drivers/clk/qcom/Kconfig | 8 +
drivers/clk/qcom/Makefile| 1 +
drivers/clk/qcom/clk-krait.c | 4 +-
drivers/clk/qcom/krait-cc.c | 341 +++
4 files changed, 352 insertions(+), 2 deletions
adding support for krait cores here.
Signed-off-by: Sricharan R
---
.../devicetree/bindings/opp/qcom-nvmem-cpufreq.txt | 3 +-
drivers/cpufreq/Kconfig.arm| 2 +-
drivers/cpufreq/cpufreq-dt-platdev.c | 5 +
drivers/cpufreq/qcom-cpufreq-nvmem.c
-off-by: Stephen Boyd
Signed-off-by: Sricharan R
---
drivers/clk/qcom/Kconfig | 8 +
drivers/clk/qcom/Makefile| 1 +
drivers/clk/qcom/clk-krait.c | 4 +-
drivers/clk/qcom/krait-cc.c | 341 +++
4 files changed, 352 insertions(+), 2 deletions
From: Stephen Boyd
The ACC and GCC regions present in KPSSv1 contain registers to
control clocks and power to each Krait CPU and L2. For CPUfreq
purposes probe these devices and expose a mux clock that chooses
between PXO and PLL8.
Cc:
Signed-off-by: Stephen Boyd
Signed-off-by: Sricharan R
From: Stephen Boyd
The ACC and GCC regions present in KPSSv1 contain registers to
control clocks and power to each Krait CPU and L2. For CPUfreq
purposes probe these devices and expose a mux clock that chooses
between PXO and PLL8.
Cc:
Signed-off-by: Stephen Boyd
Signed-off-by: Sricharan R
From: Stephen Boyd
The Krait clock controller controls the krait CPU and the L2 clocks
consisting a primary mux and secondary mux. Add document for that.
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
Signed-off-by: Sricharan R
---
.../devicetree/bindings/clock/qcom,krait-cc.txt
From: Stephen Boyd
The Krait clock controller controls the krait CPU and the L2 clocks
consisting a primary mux and secondary mux. Add document for that.
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
Signed-off-by: Sricharan R
---
.../devicetree/bindings/clock/qcom,krait-cc.txt
From: Stephen Boyd
Adds bindings document for qcom,hfpll instantiated within
the Krait processor subsystem as separate register region.
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
Signed-off-by: Sricharan R
---
.../devicetree/bindings/clock/qcom,hfpll.txt | 60
' register to do what you want. The
l2cpselr register is not banked per-cpu so we must lock around
accesses to it to prevent other CPUs from re-pointing l2cpdr
underneath us.
Cc: Mark Rutland
Cc: Russell King
Acked-by: Bjorn Andersson
Signed-off-by: Stephen Boyd
Signed-off-by: Sricharan R
---
arch
From: Stephen Boyd
Describe the HFPLLs present on MSM8960 and APQ8064 devices.
Acked-by: Rob Herring (bindings)
Signed-off-by: Stephen Boyd
Signed-off-by: Sricharan R
---
drivers/clk/qcom/gcc-msm8960.c | 172 +++
include/dt-bindings/clock/qcom,gcc
From: Stephen Boyd
Adds bindings document for qcom,hfpll instantiated within
the Krait processor subsystem as separate register region.
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
Signed-off-by: Sricharan R
---
.../devicetree/bindings/clock/qcom,hfpll.txt | 60
' register to do what you want. The
l2cpselr register is not banked per-cpu so we must lock around
accesses to it to prevent other CPUs from re-pointing l2cpdr
underneath us.
Cc: Mark Rutland
Cc: Russell King
Acked-by: Bjorn Andersson
Signed-off-by: Stephen Boyd
Signed-off-by: Sricharan R
---
arch
From: Stephen Boyd
Describe the HFPLLs present on MSM8960 and APQ8064 devices.
Acked-by: Rob Herring (bindings)
Signed-off-by: Stephen Boyd
Signed-off-by: Sricharan R
---
drivers/clk/qcom/gcc-msm8960.c | 172 +++
include/dt-bindings/clock/qcom,gcc
-by: Sricharan R
---
drivers/clk/qcom/Kconfig | 8
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/hfpll.c | 96 +++
3 files changed, 105 insertions(+)
create mode 100644 drivers/clk/qcom/hfpll.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom
From: Stephen Boyd
HFPLLs are the main frequency source for Krait CPU clocks. Add
support for changing the rate of these PLLs.
Signed-off-by: Stephen Boyd
Signed-off-by: Sricharan R
---
drivers/clk/qcom/Makefile| 1 +
drivers/clk/qcom/clk-hfpll.c | 244
inux-arm-kernel/2015-March/332615.html
[3] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/332608.html
[4] https://lwn.net/Articles/740994/
[5] https://lkml.org/lkml/2017/12/19/537
Sricharan R (3):
clk: qcom: Add safe switch hook for krait mux clocks
cpufreq: qcom: Re-o
-by: Sricharan R
---
drivers/clk/qcom/Kconfig | 8
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/hfpll.c | 96 +++
3 files changed, 105 insertions(+)
create mode 100644 drivers/clk/qcom/hfpll.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom
From: Stephen Boyd
HFPLLs are the main frequency source for Krait CPU clocks. Add
support for changing the rate of these PLLs.
Signed-off-by: Stephen Boyd
Signed-off-by: Sricharan R
---
drivers/clk/qcom/Makefile| 1 +
drivers/clk/qcom/clk-hfpll.c | 244
inux-arm-kernel/2015-March/332615.html
[3] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/332608.html
[4] https://lwn.net/Articles/740994/
[5] https://lkml.org/lkml/2017/12/19/537
Sricharan R (3):
clk: qcom: Add safe switch hook for krait mux clocks
cpufreq: qcom: Re-o
.
Signed-off-by: Sricharan R
---
.../{kryo-cpufreq.txt => qcom-nvmem-cpufreq.txt} | 6 +-
drivers/cpufreq/Kconfig.arm| 4 +-
drivers/cpufreq/Makefile | 2 +-
.../{qcom-cpufreq-kryo.c => qcom-cpufreq-nvmem.c} | 124 -
4
.
Signed-off-by: Sricharan R
---
.../{kryo-cpufreq.txt => qcom-nvmem-cpufreq.txt} | 6 +-
drivers/cpufreq/Kconfig.arm| 4 +-
drivers/cpufreq/Makefile | 2 +-
.../{qcom-cpufreq-kryo.c => qcom-cpufreq-nvmem.c} | 124 -
4
adding support for krait cores here.
Signed-off-by: Sricharan R
---
.../devicetree/bindings/opp/qcom-nvmem-cpufreq.txt | 3 +-
drivers/cpufreq/Kconfig.arm| 2 +-
drivers/cpufreq/cpufreq-dt-platdev.c | 5 +
drivers/cpufreq/qcom-cpufreq-nvmem.c
adding support for krait cores here.
Signed-off-by: Sricharan R
---
.../devicetree/bindings/opp/qcom-nvmem-cpufreq.txt | 3 +-
drivers/cpufreq/Kconfig.arm| 2 +-
drivers/cpufreq/cpufreq-dt-platdev.c | 5 +
drivers/cpufreq/qcom-cpufreq-nvmem.c
to the safe parent in the PRE_RATE_CHANGE notifier
and back to the original parent in the POST_RATE_CHANGE notifier.
Signed-off-by: Sricharan R
---
drivers/clk/qcom/clk-krait.c | 2 ++
drivers/clk/qcom/clk-krait.h | 3 +++
drivers/clk/qcom/krait-cc.c | 56
to the safe parent in the PRE_RATE_CHANGE notifier
and back to the original parent in the POST_RATE_CHANGE notifier.
Signed-off-by: Sricharan R
---
drivers/clk/qcom/clk-krait.c | 2 ++
drivers/clk/qcom/clk-krait.h | 3 +++
drivers/clk/qcom/krait-cc.c | 56
From: Stephen Boyd
The Krait clock controller controls the krait CPU and the L2 clocks
consisting a primary mux and secondary mux. Add document for that.
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
---
.../devicetree/bindings/clock/qcom,krait-cc.txt| 34 ++
1
From: Stephen Boyd
The Krait CPU clocks are made up of a primary mux and secondary
mux for each CPU and the L2, controlled via cp15 accessors. For
Kraits within KPSSv1 each secondary mux accepts a different aux
source, but on KPSSv2 each secondary mux accepts the same aux
source.
Cc:
From: Stephen Boyd
The Krait clock controller controls the krait CPU and the L2 clocks
consisting a primary mux and secondary mux. Add document for that.
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
---
.../devicetree/bindings/clock/qcom,krait-cc.txt| 34 ++
1
From: Stephen Boyd
The Krait CPU clocks are made up of a primary mux and secondary
mux for each CPU and the L2, controlled via cp15 accessors. For
Kraits within KPSSv1 each secondary mux accepts a different aux
source, but on KPSSv2 each secondary mux accepts the same aux
source.
Cc:
From: Stephen Boyd
Adds bindings document for qcom,hfpll instantiated within
the Krait processor subsystem as separate register region.
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
---
.../devicetree/bindings/clock/qcom,hfpll.txt | 60 ++
1 file changed, 60
From: Stephen Boyd
Adds bindings document for qcom,hfpll instantiated within
the Krait processor subsystem as separate register region.
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
---
.../devicetree/bindings/clock/qcom,hfpll.txt | 60 ++
1 file changed, 60
From: Stephen Boyd
The ACC and GCC regions present in KPSSv1 contain registers to
control clocks and power to each Krait CPU and L2. For CPUfreq
purposes probe these devices and expose a mux clock that chooses
between PXO and PLL8.
Cc:
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/Kconfig
From: Stephen Boyd
The Krait clocks are made up of a series of muxes and a divider
that choose between a fixed rate clock and dedicated HFPLLs for
each CPU. Instead of using mmio accesses to remux parents, the
Krait implementation exposes the remux control via cp15
registers. Support these
From: Stephen Boyd
Describe the HFPLLs present on MSM8960 and APQ8064 devices.
Acked-by: Rob Herring (bindings)
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/gcc-msm8960.c | 172 +++
include/dt-bindings/clock/qcom,gcc-msm8960.h | 2 +
2 files
From: Stephen Boyd
Describe the HFPLLs present on IPQ806X devices.
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/gcc-ipq806x.c | 82 ++
1 file changed, 82 insertions(+)
diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
From: Stephen Boyd
Describe the HFPLLs present on MSM8960 and APQ8064 devices.
Acked-by: Rob Herring (bindings)
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/gcc-msm8960.c | 172 +++
include/dt-bindings/clock/qcom,gcc-msm8960.h | 2 +
2 files
From: Stephen Boyd
The ACC and GCC regions present in KPSSv1 contain registers to
control clocks and power to each Krait CPU and L2. For CPUfreq
purposes probe these devices and expose a mux clock that chooses
between PXO and PLL8.
Cc:
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/Kconfig
From: Stephen Boyd
The Krait clocks are made up of a series of muxes and a divider
that choose between a fixed rate clock and dedicated HFPLLs for
each CPU. Instead of using mmio accesses to remux parents, the
Krait implementation exposes the remux control via cp15
registers. Support these
From: Stephen Boyd
Describe the HFPLLs present on IPQ806X devices.
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/gcc-ipq806x.c | 82 ++
1 file changed, 82 insertions(+)
diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
From: Stephen Boyd
The ACC and GCC regions present in KPSSv1 contain registers to
control clocks and power to each Krait CPU and L2. Documenting
the bindings here.
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
---
.../devicetree/bindings/arm/msm/qcom,kpss-acc.txt | 19 ++
From: Stephen Boyd
The ACC and GCC regions present in KPSSv1 contain registers to
control clocks and power to each Krait CPU and L2. Documenting
the bindings here.
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
---
.../devicetree/bindings/arm/msm/qcom,kpss-acc.txt | 19 ++
From: Stephen Boyd
On some devices (MSM8974 for example), the HFPLLs are
instantiated within the Krait processor subsystem as separate
register regions. Add a driver for these PLLs so that we can
provide HFPLL clocks for use by the system.
Cc:
Signed-off-by: Stephen Boyd
---
1 - 100 of 1933 matches
Mail list logo
