From: Vincent Cheng
Code clean-up.
Signed-off-by: Vincent Cheng
---
drivers/ptp/ptp_clockmatrix.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/ptp/ptp_clockmatrix.c b/drivers/ptp/ptp_clockmatrix.c
index 241bff0..dc42c36 100644
---
From: Vincent Cheng
This series fixes a race condition that may result in the output clock
not aligned to internal 1 PPS clock.
Part of device initialization is to align the rising edge of output
clocks to the internal rising edge of the 1 PPS clock. If the system
APLL and DPLL are not locked
From: Vincent Cheng
When enabling output using PTP_CLK_REQ_PEROUT, need to align the output
clock to the internal 1 PPS clock.
Signed-off-by: Vincent Cheng
Acked-by: Richard Cochran
---
drivers/ptp/ptp_clockmatrix.c | 16 +---
1 file changed, 13 insertions(+), 3 deletions(-)
From: Vincent Cheng
Code clean-up.
* Remove unnecessary \n termination from dev_*() messages.
* Remove 'char *fmt' to define strings to stay within 80 column
limit. Not needed since coding guidelines increased to
100 columns limit.
Keeping format in place allows static code checkers to
From: Vincent Cheng
Code clean-up.
* Remove blank line between variable declarations.
* Remove blank line between:
err = blah(...)
if (err)
...
* Remove unnecessary blank line before/after loop constructs.
Signed-off-by: Vincent Cheng
---
From: Vincent Cheng
Part of the device initialization aligns the rising edge of the output
clock to the internal 1 PPS clock. If the system APLL and DPLL is not
locked, then the alignment will fail and there will be a fixed offset
between the internal 1 PPS clock and the output clock.
After
From: Vincent Cheng
Removed unused header declarations.
Signed-off-by: Vincent Cheng
---
drivers/ptp/ptp_clockmatrix.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/ptp/ptp_clockmatrix.h b/drivers/ptp/ptp_clockmatrix.h
index 0233236..fb32327 100644
---
From: Vincent Cheng
Code clean-up.
Signed-off-by: Vincent Cheng
---
drivers/ptp/ptp_clockmatrix.c | 18 --
1 file changed, 8 insertions(+), 10 deletions(-)
diff --git a/drivers/ptp/ptp_clockmatrix.c b/drivers/ptp/ptp_clockmatrix.c
index dc42c36..75463c2 100644
---
From: Vincent Cheng
Removed unused header declarations.
Signed-off-by: Vincent Cheng
---
drivers/ptp/ptp_clockmatrix.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/ptp/ptp_clockmatrix.h b/drivers/ptp/ptp_clockmatrix.h
index 0233236..fb32327 100644
---
From: Vincent Cheng
Part of the device initialization aligns the rising edge of the output
clock to the internal 1 PPS clock. If the system APLL and DPLL is not
locked, then the alignment will fail and there will be a fixed offset
between the internal 1 PPS clock and the output clock.
After
From: Vincent Cheng
This series fixes a race condition that may result in the output clock
not aligned to internal 1 PPS clock.
Part of device initialization is to align the rising edge of output
clocks to the internal rising edge of the 1 PPS clock. If the system
APLL and DPLL are not locked
From: Vincent Cheng
When enabling output using PTP_CLK_REQ_PEROUT, need to align the output
clock to the internal 1 PPS clock.
Signed-off-by: Vincent Cheng
Acked-by: Richard Cochran
---
drivers/ptp/ptp_clockmatrix.c | 16 +---
1 file changed, 13 insertions(+), 3 deletions(-)
From: Vincent Cheng
Part of the device initialization aligns the rising edge of the output
clock to the internal 1 PPS clock. If the system APLL and DPLL is not
locked, then the alignment will fail and there will be a fixed offset
between the internal 1 PPS clock and the output clock.
After
From: Vincent Cheng
When enabling output using PTP_CLK_REQ_PEROUT, need to align the output
clock to the internal 1 PPS clock.
Signed-off-by: Vincent Cheng
---
drivers/ptp/ptp_clockmatrix.c | 16 +---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git
From: Vincent Cheng
This series fixes a race condition that may result in the output clock
not aligned to internal 1 PPS clock.
Part of device initialization is to align the rising edge of output
clocks to the internal rising edge of the 1 PPS clock. If the system
APLL and DPLL are not locked
From: Vincent Cheng
This series adds adjust phase to the PTP Hardware Clock device interface.
Some PTP hardware clocks have a write phase mode that has
a built-in hardware filtering capability. The write phase mode
utilizes a phase offset control word instead of a frequency offset
control
From: Vincent Cheng
Adds adjust phase function to take advantage of a PHC
clock's hardware filtering capability that uses phase offset
control word instead of frequency offset control word.
Signed-off-by: Vincent Cheng
---
drivers/ptp/ptp_clock.c | 3 +++
From: Vincent Cheng
Add adjust_phase to ptp_clock_caps capability to allow
user to query if a PHC driver supports adjust phase with
ioctl PTP_CLOCK_GETCAPS command.
Signed-off-by: Vincent Cheng
Reviewed-by: Richard Cochran
---
drivers/ptp/ptp_chardev.c | 1 +
From: Vincent Cheng
Add idtcm_adjphase() to support PHC write phase mode.
Signed-off-by: Vincent Cheng
---
drivers/ptp/ptp_clockmatrix.c | 92 +++
drivers/ptp/ptp_clockmatrix.h | 8 +++-
2 files changed, 98 insertions(+), 2 deletions(-)
diff --git
From: Vincent Cheng
Add idtcm_adjphase() to support PHC write phase mode.
Signed-off-by: Vincent Cheng
---
drivers/ptp/ptp_clockmatrix.c | 123 ++
drivers/ptp/ptp_clockmatrix.h | 11 +++-
2 files changed, 132 insertions(+), 2 deletions(-)
diff --git
From: Vincent Cheng
Adds adjust phase function to take advantage of a PHC
clock's hardware filtering capability that uses phase offset
control word instead of frequency offset control word.
Signed-off-by: Vincent Cheng
---
drivers/ptp/ptp_clock.c | 2 ++
From: Vincent Cheng
Add adjust_phase to ptp_clock_caps capability to allow
user to query if a PHC driver supports adjust phase with
ioctl PTP_CLOCK_GETCAPS command.
Signed-off-by: Vincent Cheng
---
drivers/ptp/ptp_chardev.c | 1 +
include/uapi/linux/ptp_clock.h| 4 +++-
From: Vincent Cheng
This series adds adjust phase to the PTP Hardware Clock device interface.
Some PTP hardware clocks have a write phase mode that has
a built-in hardware filtering capability. The write phase mode
utilizes a phase offset control word instead of a frequency offset
control
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