Hi, Dann,
On 04/21/2017 04:57 AM, dann frazier wrote:
> On Thu, Mar 30, 2017 at 9:26 AM, zhichang.yuan
> wrote:
>> On some platforms(such as Hip06/Hip07), the legacy ISA/LPC devices access I/O
>> with some special host-local I/O ports known on x86. To access the I/O
>>
is patch revises iommu_bus_notifier() to return NOTIFY_DONE when some errors
heppened in ops->add_device().
Signed-off-by: zhichang.yuan
---
drivers/iommu/iommu.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c
index 3b67
:58 PM, kbuild test robot wrote:
> Hi zhichang.yuan,
>
> [auto build test ERROR on linus/master]
> [also build test ERROR on v4.11-rc4 next-20170331]
> [if your patch is applied to the wrong git tree, please drop us a note to
> help improve the system]
>
> url:
> ht
On 04/01/2017 07:02 AM, Rafael J. Wysocki wrote:
> On Fri, Mar 31, 2017 at 8:52 AM, zhichang.yuan
> wrote:
>> Hi, Rafael,
>>
>> Thanks for reviewing this!
>>
>> On 2017/3/31 4:31, Rafael J. Wysocki wrote:
>>> On Thursday, March 30, 2017 11:26:58 P
Hi, Rafael,
Thanks for reviewing this!
On 2017/3/31 4:31, Rafael J. Wysocki wrote:
> On Thursday, March 30, 2017 11:26:58 PM zhichang.yuan wrote:
>> On some platforms(such as Hip06/Hip07), the legacy ISA/LPC devices access I/O
>> with some special host-local I/O ports known on x86
Hi, Dann,
Many thanks for your tests!
Best,
Zhichang
On 2017/3/31 5:42, dann frazier wrote:
> On Thu, Mar 30, 2017 at 9:26 AM, zhichang.yuan
> wrote:
>> This patchset supports the IPMI-bt device attached to the Low-Pin-Count
>> interface implemented on Hisilic
Based on the provious patches, this patch supports the ACPI LPC host on
Hip06/Hip07.
Signed-off-by: zhichang.yuan
Signed-off-by: John Garry
---
drivers/bus/hisi_lpc.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/bus/hisi_lpc.c b/drivers/bus
After introducing the new generic I/O space management(LIBIO), the original PCI
MMIO relevant helpers need to be updated based on the new interfaces defined in
LOGIC_IO.
This patch adapts the corresponding code to match the changes introduced by
LOGIC_IO.
Signed-off-by: zhichang.yuan
Signed-off
evice category. Through the
handler attach callback, the indirect-IO hosts I/O registration is done and
all peripherals' I/O resources are translated into logic/fake PIO before
starting the enumeration.
Signed-off-by: zhichang.yuan
Signed-off-by: Gabriele Paoloni
---
drivers/acpi/Makefile
peripherals
can be unified into the existing I/O accessors defined in asm-generic/io.h and
be redirected to the right device-specific hooks based on the input logical PIO.
Signed-off-by: zhichang.yuan
Signed-off-by: Gabriele Paoloni
---
include/asm-generic/io.h | 50 ++
include/linux/logic_pio.h
from that one of PCI MMIO.
In this way, the I/O 'reg' property of the special ISA/LPC devices will be
parsed correctly.
Signed-off-by: zhichang.yuan
Signed-off-by: Gabriele Paoloni
Signed-off-by: Arnd Bergmann #earlier draft
Acked-by: Rob Herring
t. So
this driver applies the indirect-IO introduced in the previous patch after
registering an indirect-IO node to the indirect-IO devices list which will be
searched in the I/O accessors to retrieve the host-local I/O port.
Signed-off-by: zhichang.yuan
Signed-off-by: Gabriele Paoloni
Acked-by: R
thread here: https://lkml.org/lkml/2015/12/29/154
Signed-off-by: Zhichang Yuan
zhichang.yuan (6):
LIBIO: Introduce a generic PIO mapping method
PCI: Apply the new generic I/O management on PCI IO hosts
OF: Add missing I/O range exception for indirect-IO devices
LPC: Support the device-tre
Hi, Arnd,
On 03/16/2017 06:13 PM, Arnd Bergmann wrote:
> On Thu, Mar 16, 2017 at 3:21 AM, zhichang.yuan
> wrote:
>> Hi, Rafael,
>>
>> Thanks for your review!
>>
>> On 2017/3/14 5:24, Rafael J. Wysocki wrote:
>>> On Monday, March 13, 2017 10
Hi, Rafael,
Thanks for your review!
On 2017/3/14 5:24, Rafael J. Wysocki wrote:
> On Monday, March 13, 2017 10:42:41 AM zhichang.yuan wrote:
>> In commit 40e7fcb1929(ACPI: Add _DEP support to fix battery issue on Asus
>> T100TA), the '_DEP' was supported to solve the d
Hi, Arnd,
Many thanks for your review!
On 2017/3/14 16:39, Arnd Bergmann wrote:
> On Mon, Mar 13, 2017 at 3:42 AM, zhichang.yuan
> wrote:
>> This patchset supports the IPMI-bt device attached to the Low-Pin-Count
>> interface implemented on Hisilic
c: Julia Lawall
> Subject: Re: [PATCH V7 4/7] LPC: Support the device-tree LPC host on
> Hip06/Hip07
>
> Hi zhichang.yuan,
>
> [auto build test WARNING on linus/master]
> [also build test WARNING on v4.11-rc2 next-20170310]
> [if your patch is applied to the wrong git
accessors
defined asm-generic/io.h and be redirected to the right device-specific hooks
based on the input logical PIO.
Signed-off-by: zhichang.yuan
Signed-off-by: Gabriele Paoloni
---
include/asm-generic/io.h | 50
include/linux/io.h | 1 +
include/linux/libio.h| 94
layed till all dependency master finish their work.
This patch adds the dependency checking in ACPI enumeration, also the
corresponding handling to retrigger the Hip06 LPC peripherals' scanning.
Signed-off-by: zhichang.yuan
---
drivers/acpi/battery.c | 3 ---
drivers/acpi/scan.c| 3 +
from that one of PCI MMIO.
In this way, the I/O 'reg' property of the special ISA/LPC devices will be
parsed correctly.
Signed-off-by: zhichang.yuan
Signed-off-by: Gabriele Paoloni
Signed-off-by: Arnd Bergmann #earlier draft
Acked-by: Rob Herring
implements the interfaces in LIBIO to perform the host local I/O
translation and set the logical IO mapped as ACPI I/O resources.
Signed-off-by: zhichang.yuan
Signed-off-by: Gabriele Paoloni
---
include/linux/libio.h | 4 +
lib/libio.c | 224
After introducing the new generic I/O space management(LIBIO), the original PCI
MMIO relevant helpers need to be updated based on the new interfaces defined in
LIBIO.
This patch adapts the corresponding code to match the changes introduced by
LIBIO.
Signed-off-by: zhichang.yuan
Signed-off-by
tration is finished before all the LPC
children scanning. That is why an arch_init() hook was added in this patch.
Signed-off-by: zhichang.yuan
Signed-off-by: Gabriele Paoloni
Acked-by: Rob Herring #dts part
---
.../arm/hisilicon/hisilicon-low-pin-count.txt | 33 ++
M
kml/2016/10/20/149
v3 thread here: https://lkml.org/lkml/2016/9/14/326
v2 thread here: https://lkml.org/lkml/2016/9/7/356
v1 thread here: https://lkml.org/lkml/2015/12/29/154
Signed-off-by: Zhichang Yuan
zhichang.yuan (7):
LIBIO: Introduce a generic PIO mapping method
PCI: Apply the new generic
The patch update the _CRS of LPC children based on the relevant LIBIO
interfaces. Then the ACPI platform device enumeration for LPC can apply the
right I/O resource to request the system I/O space from ioport_resource and
ensure the LPC peripherals work well.
Signed-off-by: zhichang.yuan
Signed
Hi, Alex,
On 2017/2/15 19:53, Alexander Graf wrote:
>
>
> On 15/02/2017 12:35, zhichang.yuan wrote:
>> Hi, Alex,
>>
>>
>> On 2017/2/14 21:29, Alexander Graf wrote:
>>>
>>>
>>> On 13/02/2017 15:39, zhichang.yuan wrote:
>>>>
Hi, Alex,
On 2017/2/14 21:29, Alexander Graf wrote:
>
>
> On 13/02/2017 15:39, zhichang.yuan wrote:
>> Hi, Alex,
>>
>> Thanks for your review!
>>
>> John had replied most of your comments, I only mentioned those which haven't
>> made clear
Hi, Alex,
Thanks for your review!
John had replied most of your comments, I only mentioned those which haven't
made clear.
On 2017/1/31 4:08, Alexander Graf wrote:
>
>
> On 24/01/2017 08:05, zhichang.yuan wrote:
>> The low-pin-count(LPC) interface of Hip06/Hip07 accesse
Hi, Alex,
On 2017/2/1 3:37, Alexander Graf wrote:
>
>
> On 31/01/2017 14:32, John Garry wrote:
>> On 30/01/2017 17:12, Alexander Graf wrote:
>>> On 01/24/2017 08:05 AM, zhichang.yuan wrote:
>>>> Low-pin-count interface is integrated into some SoCs. The acc
.
But when I started the work on V7, met somethings need to clarify with you.
Please kindly check the below.
On 2017/1/31 1:12, Alexander Graf wrote:
> On 01/24/2017 08:05 AM, zhichang.yuan wrote:
>> Low-pin-count interface is integrated into some SoCs. The accesses to those
>> p
from that one of PCI MMIO.
In this way, the I/O 'reg' property of the special ISA/LPC devices will be
parsed correctly.
Signed-off-by: zhichang.yuan
Signed-off-by: Gabriele Paoloni
Signed-off-by: Arnd Bergmann
---
drivers/of/address.c | 87 ++
upper layer drivers which depend on in/out() can work well
without any extra work or any changes.
Signed-off-by: zhichang.yuan
Signed-off-by: Gabriele Paoloni
Signed-off-by: John Garry
---
include/asm-generic/io.h | 50
include/linux/extio.h| 85
arlycon;
v5 thread here: https://lkml.org/lkml/2016/11/7/955
v4 thread here: https://lkml.org/lkml/2016/10/20/149
v3 thread here: https://lkml.org/lkml/2016/9/14/326
v2 thread here: https://lkml.org/lkml/2016/9/7/356
v1 thread here: https://lkml.org/lkml/2015/12/29/154
Signed-off-by: Zhichang Yu
een device-local I/O range and sytem
logical I/O range.
Signed-off-by: zhichang.yuan
Signed-off-by: Gabriele Paoloni
Signed-off-by: Arnd Bergmann
---
drivers/acpi/pci_root.c | 12 +---
drivers/of/address.c| 8 ++--
drivers/pci/pci.c
tration is finished before all the LPC
children scanning. That is why an arch_init() hook was added in this patch.
Signed-off-by: zhichang.yuan
Signed-off-by: Gabriele Paoloni
---
.../arm/hisilicon/hisilicon-low-pin-count.txt | 33 ++
MAINTAINERS|
The patch update the _CRS of LPC children with the system logical I/O resource
after the translation from LPC-local I/O. Then the ACPI platform device
enumeration for LPC can apply the right I/O resource to request the system I/O
space.
Signed-off-by: zhichang.yuan
---
drivers/bus/hisi_lpc.c
Hi，Ming,
On 2016/12/22 16:15, Ming Lei wrote:
> Hi Guys,
>
> On Tue, Nov 8, 2016 at 11:47 AM, zhichang.yuan
> wrote:
>> For arm64, there is no I/O space as other architectural platforms, such as
>> X86. Most I/O accesses are achieved based on MMIO. But for some arm6
Hi, Arnd,
Thanks you very much!
To understand your idea more clear, I have some questions on your patch sketch.
Please check it below.
On 2016/11/24 7:23, Arnd Bergmann wrote:
> On Wednesday, November 23, 2016 6:07:11 PM CET Arnd Bergmann wrote:
>> On Wednesday, November 23, 2016 3:22:33 PM CET
Hi, Arnd,
On 2016/11/18 17:20, Arnd Bergmann wrote:
> On Friday, November 11, 2016 6:07:07 PM CET zhichang.yuan wrote:
>>
>> I have similar idea as your PPC MMIO.
>>
>> We notice the prototype of {in/out()} is something like that:
>>
>> static inline u8 i
Hi, Liviu,
On 11/11/2016 10:45 PM, liviu.du...@arm.com wrote:
> On Fri, Nov 11, 2016 at 01:39:35PM +, Gabriele Paoloni wrote:
>> Hi Arnd
>>
>>> -Original Message-
>>> From: Arnd Bergmann [mailto:a...@arndb.de]
>>> Sent: 10 November 2016 16:07
>>> To: Gabriele Paoloni
>>> Cc: linux-arm
Hi, Arnd,
On 2016/11/11 0:07, Arnd Bergmann wrote:
> On Thursday, November 10, 2016 3:36:49 PM CET Gabriele Paoloni wrote:
>>
>> Where should we get the range from? For LPC we know that it is going
>> Work on anything that is not used by PCI I/O space, and this is
>> why we use [0, PCIBIOS_MIN_IO
Hi, Ben, Mark,
Thanks for your comments! These are helpful!
On 2016/11/11 3:32, Benjamin Herrenschmidt wrote:
> On Thu, 2016-11-10 at 11:22 +, Mark Rutland wrote:
>> On POWER8, our PCIe doesn't do IO at all, but we have an LPC bus behind
>>> firmware calls ;-) We use that infrastructure to p
Hi, Arnd,
On 2016/11/10 17:12, Arnd Bergmann wrote:
> On Thursday, November 10, 2016 2:40:26 PM CET zhichang.yuan wrote:
>> On 2016/11/10 5:34, Arnd Bergmann wrote:
>>> On Wednesday, November 9, 2016 12:10:43 PM CET Gabriele Paoloni wrote:
>>>>> On Tuesday,
Hi, Ben,
On 2016/11/9 7:16, Benjamin Herrenschmidt wrote:
> On Tue, 2016-11-08 at 12:03 +, Mark Rutland wrote:
>> On Tue, Nov 08, 2016 at 11:47:07AM +0800, zhichang.yuan wrote:
>>>
>>> For arm64, there is no I/O space as other architectural platforms, such as
>
Hi, Arnd,
On 2016/11/10 5:34, Arnd Bergmann wrote:
> On Wednesday, November 9, 2016 12:10:43 PM CET Gabriele Paoloni wrote:
>>> On Tuesday, November 8, 2016 11:47:09 AM CET zhichang.yuan wrote:
>>>> + /*
>>>> +* The first PCIBIOS_MIN_IO is rese
Hi,Liviu,
Thanks for your comments!
On 2016/11/10 0:50, liviu.du...@arm.com wrote:
> On Wed, Nov 09, 2016 at 04:16:17PM +, Gabriele Paoloni wrote:
>> Hi Liviu
>>
>> Thanks for reviewing
>>
>
> [removed some irrelevant part of discussion, avoid crazy formatting]
>
+/**
+ * addr_is
for Hip06 LPC. Cooperating with
indirect-IO, ipmi messages is in service without any changes on ipmi driver.
Signed-off-by: zhichang.yuan
Signed-off-by: Gabriele Paoloni
---
MAINTAINERS| 8 +
drivers/bus/Kconfig| 8 +
drivers/bus/Makefile | 1 +
drivers/bus/hisi_lpc.c | 501
ices, a I/O port address below
PCIBIOS_MIN_IO is needed by in*/out*(). Which means there is conflict risk
between I/O range of [0, PCIBIOS_MIN_IO) and PCI/PCIE legacy I/O range of [0,
IO_SPACE_LIMIT).
To avoid the I/O conflict, this patch reserve the I/O range below
PCIBIOS_MIN_IO.
Signed-off-by
he dts LPC driver in ISA compatible mode;
- Reserve the IO range below 4K in avoid the possible conflict with PCI host
IO ranges;
- Support the LPC uart and relevant earlycon;
Signed-off-by: Zhichang Yuan
zhichang.yuan (3):
ARM64 LPC: Indirect ISA port IO introduced
ARM64 LPC: Add mis
Signed-off-by: zhichang.yuan
Signed-off-by: Gabriele Paoloni
---
arch/arm64/Kconfig | 6 +++
arch/arm64/include/asm/extio.h | 94 ++
arch/arm64/include/asm/io.h| 29 +
arch/arm64/kernel/Makefile | 1 +
arch/arm64/kernel/extio.c
on in of_translate_one to return
the cpu address if the range property is not there. The exception
checks if the parent bus is ISA and if the special accessors are
defined.
Cc: Bjorn Helgaas
Cc: Rob Herring
Signed-off-by: zhichang.yuan
Signed-off-by: Gabriele Paoloni
---
arch/arm64/include/asm/io.h
ort the LPC uart and relevant earlycon;
Signed-off-by: Zhichang Yuan
zhichang.yuan (3):
ARM64 LPC: Indirect ISA port IO introduced
ARM64 LPC: Add missing range exception for special ISA
ARM64 LPC: LPC driver implementation on Hip06
.../arm/hisilicon/hisilicon-low-pin-count.txt |
Signed-off-by: zhichang.yuan
Signed-off-by: Gabriele Paoloni
---
arch/arm64/Kconfig | 6 +++
arch/arm64/include/asm/extio.h | 94 ++
arch/arm64/include/asm/io.h| 29 +
arch/arm64/kernel/Makefile | 1 +
arch/arm64/kernel/extio.c
for Hip06 LPC. Cooperating with
indirect-IO, ipmi messages is in service without any changes on ipmi driver.
Cc: Mark Rutland
Signed-off-by: zhichang.yuan
Signed-off-by: Gabriele Paoloni
---
.../arm/hisilicon/hisilicon-low-pin-count.txt | 31 ++
MAINTAINERS
Hi, Rob,
Thanks for your comments!
Please check the response blow.
BTW, Are there any comments from other maintainers/hackers??
Thanks in advance!
On 2016/10/27 6:25, Rob Herring wrote:
> On Thu, Oct 20, 2016 at 05:15:39PM +0800, zhichang.yuan wrote:
>> Currently if the range proper
/out with those known legacy port
addresses to access the peripherals, the hooking functions corrresponding to
those target peripherals will be called. Through this way, those upper layer
drivers which depend on in/out can run on Hip06 without any changes.
Signed-off-by: zhichang.yuan
Signed-off-by
for Hip06 LPC. Cooperating with
indirect-IO, ipmi messages is in service without any changes on ipmi driver.
Signed-off-by: zhichang.yuan
Signed-off-by: Gabriele Paoloni
---
.../arm/hisilicon/hisilicon-low-pin-count.txt | 31 ++
MAINTAINERS| 8
on in of_translate_one to return
the cpu address if the range property is not there. The exception
checks if the parent bus is ISA and if the special accessors are
defined.
Signed-off-by: zhichang.yuan
Signed-off-by: Gabriele Paoloni
---
arch/arm64/include/asm/io.h | 7 +++
arch/arm64/kernel/extio.c
ort the LPC uart and relevant earlycon;
Signed-off-by: Zhichang Yuan
zhichang.yuan (3):
ARM64 LPC: Indirect ISA port IO introduced
ARM64 LPC: Add missing range exception for special ISA
ARM64 LPC: LPC driver implementation on Hip06
.../arm/hisilicon/hisilicon-low-pin-count.txt |
On 09/22/2016 08:14 PM, Arnd Bergmann wrote:
On Thursday, September 22, 2016 11:55:45 AM CEST Gabriele Paoloni wrote:
I think extending of_empty_ranges_quirk() may be a reasonable
solution.
What do you think Arnd?
I don't really like that idea, that quirk is meant to work around
broken DTs,
On 09/22/2016 11:20 PM, Gabriele Paoloni wrote:
-Original Message-
From: Arnd Bergmann [mailto:a...@arndb.de]
Sent: 22 September 2016 15:59
To: Gabriele Paoloni
Cc: zhichang; linux-arm-ker...@lists.infradead.org;
devicet...@vger.kernel.org; lorenzo.pieral...@arm.com; miny...@acm.org;
l
On 2016/9/14 20:33, Arnd Bergmann wrote:
> On Wednesday, September 14, 2016 8:15:52 PM CEST Zhichang Yuan wrote:
>
>> +Required properties:
>> +- compatible: should be "hisilicon,low-pin-count"
>> +- #address-cells: must be 2 which stick to the ISA/EISA binding doc.
>> +- #size-cells: must be 1
On 2016/9/14 20:25, Arnd Bergmann wrote:
> On Wednesday, September 14, 2016 8:15:53 PM CEST Zhichang Yuan wrote:
>> From: "zhichang.yuan"
>>
>> On Hip06 platform, a 16550 compatible UART is connected to low-pin-count and
>> controlled through the LPC I/O c
Hi, Arnd
On 2016/9/14 20:24, Arnd Bergmann wrote:
> On Wednesday, September 14, 2016 8:15:51 PM CEST Zhichang Yuan wrote:
>> From: "zhichang.yuan"
>>
>> For arm64, there is no I/O space as other architectural platforms, such as
>> X86. Most I/O accesses are
On 2016/9/8 17:58, Arnd Bergmann wrote:
> On Thursday, September 8, 2016 5:51:25 PM CEST zhichang wrote:
>> On 2016年09月07日 22:50, Arnd Bergmann wrote:
>>> On Wednesday, September 7, 2016 9:33:52 PM CEST Zhichang Yuan wrote:
>>>> From: "zhichang.yuan&quo
Hi, Arnd
On 2016/9/7 23:27, Arnd Bergmann wrote:
> On Wednesday, September 7, 2016 9:33:51 PM CEST Zhichang Yuan wrote:
>
>> +
>> +struct hisilpc_dev;
>> +
>> +/* This flag is specific to differentiate earlycon operations and the
>> others */
>> +#define FG_EARLYCON_LPC (0x01U << 0)
Hi, Arnd,
Thanks for your remarks!
On 2016/9/7 23:06, Arnd Bergmann wrote:
> On Wednesday, September 7, 2016 9:33:50 PM CEST Zhichang Yuan wrote:
>> +#ifdef CONFIG_ARM64_INDIRECT_PIO
>> +
>> +typedef u64 (*inhook)(void *devobj, unsigned long ptaddr, void *inbuf,
>> +
On 2014年11月25日 01:17, Catalin Marinas wrote:
> Hi,
>
> I'm trying to make some sense of this patch, so questions below:
>
> On Wed, Nov 19, 2014 at 02:21:55PM +, zhichang.y...@linaro.org wrote:
>> From: "zhichang.yuan"
>>
>> This patch make t
Hi Catalin, Will,
I am working to implement the DEBUG_PAGEALLOC on ARMv8.
After i investigated the DEBUG_PAGEALLOC implementation on x86 arch, some
questions are standing in the way to
start coding.
1. How to handle the large page when DEBUG_PAGEALLOC is enabled
In ARMv8, the kernel direct memor
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