RE: [PATCH 3/4] x86/insn: perf tools: Add new SHA instructions

2015-08-31 Thread 平松雅巳 / HIRAMATU，MASAMI 
> From: Adrian Hunter [mailto:adrian.hun...@intel.com]
> 
> Intel SHA Extensions are explained in the Intel Architecture
> Instruction Set Extensions Programing Reference (Oct 2014).
> There are 7 new instructions.  Add them to the op code map
> and the perf tools new instructions test. e.g.
> 
> $ tools/perf/perf test list 2>&1 | grep "x86 ins"
> 39: Test x86 instruction decoder - new instructions
> $ tools/perf/perf test 39
> 39: Test x86 instruction decoder - new instructions  : Ok
> 
> Or to see the details:
> 
> $ tools/perf/perf test -v 39 2>&1 | grep sha

OK, looks fine to me :)

Acked-by: Masami Hiramatsu 

Thanks!

> 
> Signed-off-by: Adrian Hunter 
> ---
>  arch/x86/lib/x86-opcode-map.txt|   7 +
>  tools/perf/tests/insn-x86-dat-32.c | 294 
>  tools/perf/tests/insn-x86-dat-64.c | 364 
>  tools/perf/tests/insn-x86-dat-src.c| 373 
> +
>  .../perf/util/intel-pt-decoder/x86-opcode-map.txt  |   7 +
>  5 files changed, 1045 insertions(+)
> 
> diff --git a/arch/x86/lib/x86-opcode-map.txt b/arch/x86/lib/x86-opcode-map.txt
> index a02a195d219c..25dad388b371 100644
> --- a/arch/x86/lib/x86-opcode-map.txt
> +++ b/arch/x86/lib/x86-opcode-map.txt
> @@ -736,6 +736,12 @@ bd: vfnmadd231ss/d Vx,Hx,Wx (66),(v),(v1)
>  be: vfnmsub231ps/d Vx,Hx,Wx (66),(v)
>  bf: vfnmsub231ss/d Vx,Hx,Wx (66),(v),(v1)
>  # 0x0f 0x38 0xc0-0xff
> +c8: sha1nexte Vdq,Wdq
> +c9: sha1msg1 Vdq,Wdq
> +ca: sha1msg2 Vdq,Wdq
> +cb: sha256rnds2 Vdq,Wdq
> +cc: sha256msg1 Vdq,Wdq
> +cd: sha256msg2 Vdq,Wdq
>  db: VAESIMC Vdq,Wdq (66),(v1)
>  dc: VAESENC Vdq,Hdq,Wdq (66),(v1)
>  dd: VAESENCLAST Vdq,Hdq,Wdq (66),(v1)
> @@ -794,6 +800,7 @@ AVXcode: 3
>  61: vpcmpestri Vdq,Wdq,Ib (66),(v1)
>  62: vpcmpistrm Vdq,Wdq,Ib (66),(v1)
>  63: vpcmpistri Vdq,Wdq,Ib (66),(v1)
> +cc: sha1rnds4 Vdq,Wdq,Ib
>  df: VAESKEYGEN Vdq,Wdq,Ib (66),(v1)
>  f0: RORX Gy,Ey,Ib (F2),(v)
>  EndTable
> diff --git a/tools/perf/tests/insn-x86-dat-32.c 
> b/tools/perf/tests/insn-x86-dat-32.c
> index 6a38a34a5a49..83f5078e74e1 100644
> --- a/tools/perf/tests/insn-x86-dat-32.c
> +++ b/tools/perf/tests/insn-x86-dat-32.c
> @@ -322,3 +322,297 @@
>  "f2 ff 21 \tbnd jmp *(%ecx)",},
>  {{0xf2, 0x0f, 0x85, 0xfc, 0xff, 0xff, 0xff, }, 7, 0xfffc, "jcc", 
> "conditional",
>  "f2 0f 85 fc ff ff ff \tbnd jne 3de ",},
> +{{0x0f, 0x3a, 0xcc, 0xc1, 0x00, }, 5, 0, "", "",
> +"0f 3a cc c1 00   \tsha1rnds4 $0x0,%xmm1,%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0xd7, 0x91, }, 5, 0, "", "",
> +"0f 3a cc d7 91   \tsha1rnds4 $0x91,%xmm7,%xmm2",},
> +{{0x0f, 0x3a, 0xcc, 0x00, 0x91, }, 5, 0, "", "",
> +"0f 3a cc 00 91   \tsha1rnds4 $0x91,(%eax),%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0x05, 0x78, 0x56, 0x34, 0x12, 0x91, }, 9, 0, "", "",
> +"0f 3a cc 05 78 56 34 12 91 \tsha1rnds4 $0x91,0x12345678,%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0x18, 0x91, }, 5, 0, "", "",
> +"0f 3a cc 18 91   \tsha1rnds4 $0x91,(%eax),%xmm3",},
> +{{0x0f, 0x3a, 0xcc, 0x04, 0x01, 0x91, }, 6, 0, "", "",
> +"0f 3a cc 04 01 91\tsha1rnds4 $0x91,(%ecx,%eax,1),%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, 0x91, }, 10, 0, "", 
> "",
> +"0f 3a cc 04 05 78 56 34 12 91 \tsha1rnds4 
> $0x91,0x12345678(,%eax,1),%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0x04, 0x08, 0x91, }, 6, 0, "", "",
> +"0f 3a cc 04 08 91\tsha1rnds4 $0x91,(%eax,%ecx,1),%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0x04, 0xc8, 0x91, }, 6, 0, "", "",
> +"0f 3a cc 04 c8 91\tsha1rnds4 $0x91,(%eax,%ecx,8),%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0x40, 0x12, 0x91, }, 6, 0, "", "",
> +"0f 3a cc 40 12 91\tsha1rnds4 $0x91,0x12(%eax),%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0x45, 0x12, 0x91, }, 6, 0, "", "",
> +"0f 3a cc 45 12 91\tsha1rnds4 $0x91,0x12(%ebp),%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0x44, 0x01, 0x12, 0x91, }, 7, 0, "", "",
> +"0f 3a cc 44 01 12 91 \tsha1rnds4 $0x91,0x12(%ecx,%eax,1),%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0x44, 0x05, 0x12, 0x91, }, 7, 0, "", "",
> +"0f 3a cc 44 05 12 91 \tsha1rnds4 $0x91,0x12(%ebp,%eax,1),%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0x44, 0x08, 0x12, 0x91, }, 7, 0, "", "",
> +"0f 3a cc 44 08 12 91 \tsha1rnds4 $0x91,0x12(%eax,%ecx,1),%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0x44, 0xc8, 0x12, 0x91, }, 7, 0, "", "",
> +"0f 3a cc 44 c8 12 91 \tsha1rnds4 $0x91,0x12(%eax,%ecx,8),%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0x80, 0x78, 0x56, 0x34, 0x12, 0x91, }, 9, 0, "", "",
> +"0f 3a cc 80 78 56 34 12 91 \tsha1rnds4 $0x91,0x12345678(%eax),%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0x85, 0x78, 0x56, 0x34, 0x12, 0x91, }, 9, 0, "", "",
> +"0f 3a cc 85 78 56 34 12 91 \tsha1rnds4 $0x91,0x12345678(%ebp),%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, 0x91, }, 10, 0, "", 
> "",
> +"0f 3a cc 84 01 78 56 34 12 91 \tsha1rnds4 
> $0x91,0x12345678(%ecx,%eax,1),%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, 0x91, }, 10, 0, "", 
> "",
> +"0f 3a cc 84 05 78 56 34 12 91 \tsha1rnds4 
>

Re: [PATCH 3/4] x86/insn: perf tools: Add new SHA instructions

2015-08-31 Thread Adrian Hunter 

On 31/08/2015 5:50 p.m., Arnaldo Carvalho de Melo wrote:

Em Mon, Aug 31, 2015 at 04:58:41PM +0300, Adrian Hunter escreveu:

Intel SHA Extensions are explained in the Intel Architecture
Instruction Set Extensions Programing Reference (Oct 2014).
There are 7 new instructions.  Add them to the op code map
and the perf tools new instructions test. e.g.

 $ tools/perf/perf test list 2>&1 | grep "x86 ins"


I.e., one could short circuit the 'perf test list' step and use:

perf test "x86 ins" straight away:

[root@zoo linux]# perf test "syscall event"
  2: detect openat syscall event  : Ok
  3: detect openat syscall event on all cpus  : Ok
[root@zoo linux]#


Cool, I'll update the commit messages in V2




 39: Test x86 instruction decoder - new instructions
 $ tools/perf/perf test 39
 39: Test x86 instruction decoder - new instructions  : Ok

Or to see the details:

 $ tools/perf/perf test -v 39 2>&1 | grep sha

Signed-off-by: Adrian Hunter 
---
  arch/x86/lib/x86-opcode-map.txt|   7 +
  tools/perf/tests/insn-x86-dat-32.c | 294 
  tools/perf/tests/insn-x86-dat-64.c | 364 
  tools/perf/tests/insn-x86-dat-src.c| 373 +
  .../perf/util/intel-pt-decoder/x86-opcode-map.txt  |   7 +
  5 files changed, 1045 insertions(+)

diff --git a/arch/x86/lib/x86-opcode-map.txt b/arch/x86/lib/x86-opcode-map.txt
index a02a195d219c..25dad388b371 100644
--- a/arch/x86/lib/x86-opcode-map.txt
+++ b/arch/x86/lib/x86-opcode-map.txt
@@ -736,6 +736,12 @@ bd: vfnmadd231ss/d Vx,Hx,Wx (66),(v),(v1)
  be: vfnmsub231ps/d Vx,Hx,Wx (66),(v)
  bf: vfnmsub231ss/d Vx,Hx,Wx (66),(v),(v1)
  # 0x0f 0x38 0xc0-0xff
+c8: sha1nexte Vdq,Wdq
+c9: sha1msg1 Vdq,Wdq
+ca: sha1msg2 Vdq,Wdq
+cb: sha256rnds2 Vdq,Wdq
+cc: sha256msg1 Vdq,Wdq
+cd: sha256msg2 Vdq,Wdq
  db: VAESIMC Vdq,Wdq (66),(v1)
  dc: VAESENC Vdq,Hdq,Wdq (66),(v1)
  dd: VAESENCLAST Vdq,Hdq,Wdq (66),(v1)
@@ -794,6 +800,7 @@ AVXcode: 3
  61: vpcmpestri Vdq,Wdq,Ib (66),(v1)
  62: vpcmpistrm Vdq,Wdq,Ib (66),(v1)
  63: vpcmpistri Vdq,Wdq,Ib (66),(v1)
+cc: sha1rnds4 Vdq,Wdq,Ib
  df: VAESKEYGEN Vdq,Wdq,Ib (66),(v1)
  f0: RORX Gy,Ey,Ib (F2),(v)
  EndTable
diff --git a/tools/perf/tests/insn-x86-dat-32.c 
b/tools/perf/tests/insn-x86-dat-32.c
index 6a38a34a5a49..83f5078e74e1 100644
--- a/tools/perf/tests/insn-x86-dat-32.c
+++ b/tools/perf/tests/insn-x86-dat-32.c
@@ -322,3 +322,297 @@
  "f2 ff 21 \tbnd jmp *(%ecx)",},
  {{0xf2, 0x0f, 0x85, 0xfc, 0xff, 0xff, 0xff, }, 7, 0xfffc, "jcc", 
"conditional",
  "f2 0f 85 fc ff ff ff \tbnd jne 3de ",},
+{{0x0f, 0x3a, 0xcc, 0xc1, 0x00, }, 5, 0, "", "",
+"0f 3a cc c1 00   \tsha1rnds4 $0x0,%xmm1,%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0xd7, 0x91, }, 5, 0, "", "",
+"0f 3a cc d7 91   \tsha1rnds4 $0x91,%xmm7,%xmm2",},
+{{0x0f, 0x3a, 0xcc, 0x00, 0x91, }, 5, 0, "", "",
+"0f 3a cc 00 91   \tsha1rnds4 $0x91,(%eax),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x05, 0x78, 0x56, 0x34, 0x12, 0x91, }, 9, 0, "", "",
+"0f 3a cc 05 78 56 34 12 91 \tsha1rnds4 $0x91,0x12345678,%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x18, 0x91, }, 5, 0, "", "",
+"0f 3a cc 18 91   \tsha1rnds4 $0x91,(%eax),%xmm3",},
+{{0x0f, 0x3a, 0xcc, 0x04, 0x01, 0x91, }, 6, 0, "", "",
+"0f 3a cc 04 01 91\tsha1rnds4 $0x91,(%ecx,%eax,1),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, 0x91, }, 10, 0, "", "",
+"0f 3a cc 04 05 78 56 34 12 91 \tsha1rnds4 $0x91,0x12345678(,%eax,1),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x04, 0x08, 0x91, }, 6, 0, "", "",
+"0f 3a cc 04 08 91\tsha1rnds4 $0x91,(%eax,%ecx,1),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x04, 0xc8, 0x91, }, 6, 0, "", "",
+"0f 3a cc 04 c8 91\tsha1rnds4 $0x91,(%eax,%ecx,8),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x40, 0x12, 0x91, }, 6, 0, "", "",
+"0f 3a cc 40 12 91\tsha1rnds4 $0x91,0x12(%eax),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x45, 0x12, 0x91, }, 6, 0, "", "",
+"0f 3a cc 45 12 91\tsha1rnds4 $0x91,0x12(%ebp),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x44, 0x01, 0x12, 0x91, }, 7, 0, "", "",
+"0f 3a cc 44 01 12 91 \tsha1rnds4 $0x91,0x12(%ecx,%eax,1),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x44, 0x05, 0x12, 0x91, }, 7, 0, "", "",
+"0f 3a cc 44 05 12 91 \tsha1rnds4 $0x91,0x12(%ebp,%eax,1),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x44, 0x08, 0x12, 0x91, }, 7, 0, "", "",
+"0f 3a cc 44 08 12 91 \tsha1rnds4 $0x91,0x12(%eax,%ecx,1),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x44, 0xc8, 0x12, 0x91, }, 7, 0, "", "",
+"0f 3a cc 44 c8 12 91 \tsha1rnds4 $0x91,0x12(%eax,%ecx,8),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x80, 0x78, 0x56, 0x34, 0x12, 0x91, }, 9, 0, "", "",
+"0f 3a cc 80 78 56 34 12 91 \tsha1rnds4 $0x91,0x12345678(%eax),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x85, 0x78, 0x56, 0x34, 0x12, 0x91, }, 9, 0, "", "",
+"0f 3a cc 85 78 56 34 12 91 \tsha1rnds4 $0x91,0x12345678(%ebp),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, 0x91, }, 10, 0, "", "",
+"0f 3a cc 84 01 78 56 34 12 91 \tsha1rnds4

Re: [PATCH 3/4] x86/insn: perf tools: Add new SHA instructions

2015-08-31 Thread Arnaldo Carvalho de Melo 
Em Mon, Aug 31, 2015 at 04:58:41PM +0300, Adrian Hunter escreveu:
> Intel SHA Extensions are explained in the Intel Architecture
> Instruction Set Extensions Programing Reference (Oct 2014).
> There are 7 new instructions.  Add them to the op code map
> and the perf tools new instructions test. e.g.
> 
> $ tools/perf/perf test list 2>&1 | grep "x86 ins"

I.e., one could short circuit the 'perf test list' step and use:

perf test "x86 ins" straight away:

[root@zoo linux]# perf test "syscall event"
 2: detect openat syscall event  : Ok
 3: detect openat syscall event on all cpus  : Ok
[root@zoo linux]#

> 39: Test x86 instruction decoder - new instructions
> $ tools/perf/perf test 39
> 39: Test x86 instruction decoder - new instructions  : Ok
> 
> Or to see the details:
> 
> $ tools/perf/perf test -v 39 2>&1 | grep sha
> 
> Signed-off-by: Adrian Hunter 
> ---
>  arch/x86/lib/x86-opcode-map.txt|   7 +
>  tools/perf/tests/insn-x86-dat-32.c | 294 
>  tools/perf/tests/insn-x86-dat-64.c | 364 
>  tools/perf/tests/insn-x86-dat-src.c| 373 
> +
>  .../perf/util/intel-pt-decoder/x86-opcode-map.txt  |   7 +
>  5 files changed, 1045 insertions(+)
> 
> diff --git a/arch/x86/lib/x86-opcode-map.txt b/arch/x86/lib/x86-opcode-map.txt
> index a02a195d219c..25dad388b371 100644
> --- a/arch/x86/lib/x86-opcode-map.txt
> +++ b/arch/x86/lib/x86-opcode-map.txt
> @@ -736,6 +736,12 @@ bd: vfnmadd231ss/d Vx,Hx,Wx (66),(v),(v1)
>  be: vfnmsub231ps/d Vx,Hx,Wx (66),(v)
>  bf: vfnmsub231ss/d Vx,Hx,Wx (66),(v),(v1)
>  # 0x0f 0x38 0xc0-0xff
> +c8: sha1nexte Vdq,Wdq
> +c9: sha1msg1 Vdq,Wdq
> +ca: sha1msg2 Vdq,Wdq
> +cb: sha256rnds2 Vdq,Wdq
> +cc: sha256msg1 Vdq,Wdq
> +cd: sha256msg2 Vdq,Wdq
>  db: VAESIMC Vdq,Wdq (66),(v1)
>  dc: VAESENC Vdq,Hdq,Wdq (66),(v1)
>  dd: VAESENCLAST Vdq,Hdq,Wdq (66),(v1)
> @@ -794,6 +800,7 @@ AVXcode: 3
>  61: vpcmpestri Vdq,Wdq,Ib (66),(v1)
>  62: vpcmpistrm Vdq,Wdq,Ib (66),(v1)
>  63: vpcmpistri Vdq,Wdq,Ib (66),(v1)
> +cc: sha1rnds4 Vdq,Wdq,Ib
>  df: VAESKEYGEN Vdq,Wdq,Ib (66),(v1)
>  f0: RORX Gy,Ey,Ib (F2),(v)
>  EndTable
> diff --git a/tools/perf/tests/insn-x86-dat-32.c 
> b/tools/perf/tests/insn-x86-dat-32.c
> index 6a38a34a5a49..83f5078e74e1 100644
> --- a/tools/perf/tests/insn-x86-dat-32.c
> +++ b/tools/perf/tests/insn-x86-dat-32.c
> @@ -322,3 +322,297 @@
>  "f2 ff 21 \tbnd jmp *(%ecx)",},
>  {{0xf2, 0x0f, 0x85, 0xfc, 0xff, 0xff, 0xff, }, 7, 0xfffc, "jcc", 
> "conditional",
>  "f2 0f 85 fc ff ff ff \tbnd jne 3de ",},
> +{{0x0f, 0x3a, 0xcc, 0xc1, 0x00, }, 5, 0, "", "",
> +"0f 3a cc c1 00   \tsha1rnds4 $0x0,%xmm1,%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0xd7, 0x91, }, 5, 0, "", "",
> +"0f 3a cc d7 91   \tsha1rnds4 $0x91,%xmm7,%xmm2",},
> +{{0x0f, 0x3a, 0xcc, 0x00, 0x91, }, 5, 0, "", "",
> +"0f 3a cc 00 91   \tsha1rnds4 $0x91,(%eax),%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0x05, 0x78, 0x56, 0x34, 0x12, 0x91, }, 9, 0, "", "",
> +"0f 3a cc 05 78 56 34 12 91 \tsha1rnds4 $0x91,0x12345678,%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0x18, 0x91, }, 5, 0, "", "",
> +"0f 3a cc 18 91   \tsha1rnds4 $0x91,(%eax),%xmm3",},
> +{{0x0f, 0x3a, 0xcc, 0x04, 0x01, 0x91, }, 6, 0, "", "",
> +"0f 3a cc 04 01 91\tsha1rnds4 $0x91,(%ecx,%eax,1),%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, 0x91, }, 10, 0, "", 
> "",
> +"0f 3a cc 04 05 78 56 34 12 91 \tsha1rnds4 
> $0x91,0x12345678(,%eax,1),%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0x04, 0x08, 0x91, }, 6, 0, "", "",
> +"0f 3a cc 04 08 91\tsha1rnds4 $0x91,(%eax,%ecx,1),%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0x04, 0xc8, 0x91, }, 6, 0, "", "",
> +"0f 3a cc 04 c8 91\tsha1rnds4 $0x91,(%eax,%ecx,8),%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0x40, 0x12, 0x91, }, 6, 0, "", "",
> +"0f 3a cc 40 12 91\tsha1rnds4 $0x91,0x12(%eax),%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0x45, 0x12, 0x91, }, 6, 0, "", "",
> +"0f 3a cc 45 12 91\tsha1rnds4 $0x91,0x12(%ebp),%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0x44, 0x01, 0x12, 0x91, }, 7, 0, "", "",
> +"0f 3a cc 44 01 12 91 \tsha1rnds4 $0x91,0x12(%ecx,%eax,1),%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0x44, 0x05, 0x12, 0x91, }, 7, 0, "", "",
> +"0f 3a cc 44 05 12 91 \tsha1rnds4 $0x91,0x12(%ebp,%eax,1),%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0x44, 0x08, 0x12, 0x91, }, 7, 0, "", "",
> +"0f 3a cc 44 08 12 91 \tsha1rnds4 $0x91,0x12(%eax,%ecx,1),%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0x44, 0xc8, 0x12, 0x91, }, 7, 0, "", "",
> +"0f 3a cc 44 c8 12 91 \tsha1rnds4 $0x91,0x12(%eax,%ecx,8),%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0x80, 0x78, 0x56, 0x34, 0x12, 0x91, }, 9, 0, "", "",
> +"0f 3a cc 80 78 56 34 12 91 \tsha1rnds4 $0x91,0x12345678(%eax),%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0x85, 0x78, 0x56, 0x34, 0x12, 0x91, }, 9, 0, "", "",
> +"0f 3a cc 85 78 56 34 12 91 \tsha1rnds4 $0x91,0x12345678(%ebp),%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, 0x91, }, 10, 0, "", 
> "",
>

[PATCH 3/4] x86/insn: perf tools: Add new SHA instructions

2015-08-31 Thread Adrian Hunter 
Intel SHA Extensions are explained in the Intel Architecture
Instruction Set Extensions Programing Reference (Oct 2014).
There are 7 new instructions.  Add them to the op code map
and the perf tools new instructions test. e.g.

$ tools/perf/perf test list 2>&1 | grep "x86 ins"
39: Test x86 instruction decoder - new instructions
$ tools/perf/perf test 39
39: Test x86 instruction decoder - new instructions  : Ok

Or to see the details:

$ tools/perf/perf test -v 39 2>&1 | grep sha

Signed-off-by: Adrian Hunter 
---
 arch/x86/lib/x86-opcode-map.txt|   7 +
 tools/perf/tests/insn-x86-dat-32.c | 294 
 tools/perf/tests/insn-x86-dat-64.c | 364 
 tools/perf/tests/insn-x86-dat-src.c| 373 +
 .../perf/util/intel-pt-decoder/x86-opcode-map.txt  |   7 +
 5 files changed, 1045 insertions(+)

diff --git a/arch/x86/lib/x86-opcode-map.txt b/arch/x86/lib/x86-opcode-map.txt
index a02a195d219c..25dad388b371 100644
--- a/arch/x86/lib/x86-opcode-map.txt
+++ b/arch/x86/lib/x86-opcode-map.txt
@@ -736,6 +736,12 @@ bd: vfnmadd231ss/d Vx,Hx,Wx (66),(v),(v1)
 be: vfnmsub231ps/d Vx,Hx,Wx (66),(v)
 bf: vfnmsub231ss/d Vx,Hx,Wx (66),(v),(v1)
 # 0x0f 0x38 0xc0-0xff
+c8: sha1nexte Vdq,Wdq
+c9: sha1msg1 Vdq,Wdq
+ca: sha1msg2 Vdq,Wdq
+cb: sha256rnds2 Vdq,Wdq
+cc: sha256msg1 Vdq,Wdq
+cd: sha256msg2 Vdq,Wdq
 db: VAESIMC Vdq,Wdq (66),(v1)
 dc: VAESENC Vdq,Hdq,Wdq (66),(v1)
 dd: VAESENCLAST Vdq,Hdq,Wdq (66),(v1)
@@ -794,6 +800,7 @@ AVXcode: 3
 61: vpcmpestri Vdq,Wdq,Ib (66),(v1)
 62: vpcmpistrm Vdq,Wdq,Ib (66),(v1)
 63: vpcmpistri Vdq,Wdq,Ib (66),(v1)
+cc: sha1rnds4 Vdq,Wdq,Ib
 df: VAESKEYGEN Vdq,Wdq,Ib (66),(v1)
 f0: RORX Gy,Ey,Ib (F2),(v)
 EndTable
diff --git a/tools/perf/tests/insn-x86-dat-32.c 
b/tools/perf/tests/insn-x86-dat-32.c
index 6a38a34a5a49..83f5078e74e1 100644
--- a/tools/perf/tests/insn-x86-dat-32.c
+++ b/tools/perf/tests/insn-x86-dat-32.c
@@ -322,3 +322,297 @@
 "f2 ff 21 \tbnd jmp *(%ecx)",},
 {{0xf2, 0x0f, 0x85, 0xfc, 0xff, 0xff, 0xff, }, 7, 0xfffc, "jcc", 
"conditional",
 "f2 0f 85 fc ff ff ff \tbnd jne 3de ",},
+{{0x0f, 0x3a, 0xcc, 0xc1, 0x00, }, 5, 0, "", "",
+"0f 3a cc c1 00   \tsha1rnds4 $0x0,%xmm1,%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0xd7, 0x91, }, 5, 0, "", "",
+"0f 3a cc d7 91   \tsha1rnds4 $0x91,%xmm7,%xmm2",},
+{{0x0f, 0x3a, 0xcc, 0x00, 0x91, }, 5, 0, "", "",
+"0f 3a cc 00 91   \tsha1rnds4 $0x91,(%eax),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x05, 0x78, 0x56, 0x34, 0x12, 0x91, }, 9, 0, "", "",
+"0f 3a cc 05 78 56 34 12 91 \tsha1rnds4 $0x91,0x12345678,%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x18, 0x91, }, 5, 0, "", "",
+"0f 3a cc 18 91   \tsha1rnds4 $0x91,(%eax),%xmm3",},
+{{0x0f, 0x3a, 0xcc, 0x04, 0x01, 0x91, }, 6, 0, "", "",
+"0f 3a cc 04 01 91\tsha1rnds4 $0x91,(%ecx,%eax,1),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, 0x91, }, 10, 0, "", "",
+"0f 3a cc 04 05 78 56 34 12 91 \tsha1rnds4 $0x91,0x12345678(,%eax,1),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x04, 0x08, 0x91, }, 6, 0, "", "",
+"0f 3a cc 04 08 91\tsha1rnds4 $0x91,(%eax,%ecx,1),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x04, 0xc8, 0x91, }, 6, 0, "", "",
+"0f 3a cc 04 c8 91\tsha1rnds4 $0x91,(%eax,%ecx,8),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x40, 0x12, 0x91, }, 6, 0, "", "",
+"0f 3a cc 40 12 91\tsha1rnds4 $0x91,0x12(%eax),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x45, 0x12, 0x91, }, 6, 0, "", "",
+"0f 3a cc 45 12 91\tsha1rnds4 $0x91,0x12(%ebp),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x44, 0x01, 0x12, 0x91, }, 7, 0, "", "",
+"0f 3a cc 44 01 12 91 \tsha1rnds4 $0x91,0x12(%ecx,%eax,1),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x44, 0x05, 0x12, 0x91, }, 7, 0, "", "",
+"0f 3a cc 44 05 12 91 \tsha1rnds4 $0x91,0x12(%ebp,%eax,1),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x44, 0x08, 0x12, 0x91, }, 7, 0, "", "",
+"0f 3a cc 44 08 12 91 \tsha1rnds4 $0x91,0x12(%eax,%ecx,1),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x44, 0xc8, 0x12, 0x91, }, 7, 0, "", "",
+"0f 3a cc 44 c8 12 91 \tsha1rnds4 $0x91,0x12(%eax,%ecx,8),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x80, 0x78, 0x56, 0x34, 0x12, 0x91, }, 9, 0, "", "",
+"0f 3a cc 80 78 56 34 12 91 \tsha1rnds4 $0x91,0x12345678(%eax),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x85, 0x78, 0x56, 0x34, 0x12, 0x91, }, 9, 0, "", "",
+"0f 3a cc 85 78 56 34 12 91 \tsha1rnds4 $0x91,0x12345678(%ebp),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, 0x91, }, 10, 0, "", "",
+"0f 3a cc 84 01 78 56 34 12 91 \tsha1rnds4 
$0x91,0x12345678(%ecx,%eax,1),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, 0x91, }, 10, 0, "", "",
+"0f 3a cc 84 05 78 56 34 12 91 \tsha1rnds4 
$0x91,0x12345678(%ebp,%eax,1),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, 0x91, }, 10, 0, "", "",
+"0f 3a cc 84 08 78 56 34 12 91 \tsha1rnds4 
$0x91,0x12345678(%eax,%ecx,1),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, 0x91, }, 10, 0, "", "",
+"0f 3a cc 84 c8 78 56 34 12 91 \tsha1rnds4

Re: [PATCH 3/4] x86/insn: perf tools: Add new SHA instructions

2015-08-31 Thread Arnaldo Carvalho de Melo 
Em Mon, Aug 31, 2015 at 04:58:41PM +0300, Adrian Hunter escreveu:
> Intel SHA Extensions are explained in the Intel Architecture
> Instruction Set Extensions Programing Reference (Oct 2014).
> There are 7 new instructions.  Add them to the op code map
> and the perf tools new instructions test. e.g.
> 
> $ tools/perf/perf test list 2>&1 | grep "x86 ins"

I.e., one could short circuit the 'perf test list' step and use:

perf test "x86 ins" straight away:

[root@zoo linux]# perf test "syscall event"
 2: detect openat syscall event  : Ok
 3: detect openat syscall event on all cpus  : Ok
[root@zoo linux]#

> 39: Test x86 instruction decoder - new instructions
> $ tools/perf/perf test 39
> 39: Test x86 instruction decoder - new instructions  : Ok
> 
> Or to see the details:
> 
> $ tools/perf/perf test -v 39 2>&1 | grep sha
> 
> Signed-off-by: Adrian Hunter 
> ---
>  arch/x86/lib/x86-opcode-map.txt|   7 +
>  tools/perf/tests/insn-x86-dat-32.c | 294 
>  tools/perf/tests/insn-x86-dat-64.c | 364 
>  tools/perf/tests/insn-x86-dat-src.c| 373 
> +
>  .../perf/util/intel-pt-decoder/x86-opcode-map.txt  |   7 +
>  5 files changed, 1045 insertions(+)
> 
> diff --git a/arch/x86/lib/x86-opcode-map.txt b/arch/x86/lib/x86-opcode-map.txt
> index a02a195d219c..25dad388b371 100644
> --- a/arch/x86/lib/x86-opcode-map.txt
> +++ b/arch/x86/lib/x86-opcode-map.txt
> @@ -736,6 +736,12 @@ bd: vfnmadd231ss/d Vx,Hx,Wx (66),(v),(v1)
>  be: vfnmsub231ps/d Vx,Hx,Wx (66),(v)
>  bf: vfnmsub231ss/d Vx,Hx,Wx (66),(v),(v1)
>  # 0x0f 0x38 0xc0-0xff
> +c8: sha1nexte Vdq,Wdq
> +c9: sha1msg1 Vdq,Wdq
> +ca: sha1msg2 Vdq,Wdq
> +cb: sha256rnds2 Vdq,Wdq
> +cc: sha256msg1 Vdq,Wdq
> +cd: sha256msg2 Vdq,Wdq
>  db: VAESIMC Vdq,Wdq (66),(v1)
>  dc: VAESENC Vdq,Hdq,Wdq (66),(v1)
>  dd: VAESENCLAST Vdq,Hdq,Wdq (66),(v1)
> @@ -794,6 +800,7 @@ AVXcode: 3
>  61: vpcmpestri Vdq,Wdq,Ib (66),(v1)
>  62: vpcmpistrm Vdq,Wdq,Ib (66),(v1)
>  63: vpcmpistri Vdq,Wdq,Ib (66),(v1)
> +cc: sha1rnds4 Vdq,Wdq,Ib
>  df: VAESKEYGEN Vdq,Wdq,Ib (66),(v1)
>  f0: RORX Gy,Ey,Ib (F2),(v)
>  EndTable
> diff --git a/tools/perf/tests/insn-x86-dat-32.c 
> b/tools/perf/tests/insn-x86-dat-32.c
> index 6a38a34a5a49..83f5078e74e1 100644
> --- a/tools/perf/tests/insn-x86-dat-32.c
> +++ b/tools/perf/tests/insn-x86-dat-32.c
> @@ -322,3 +322,297 @@
>  "f2 ff 21 \tbnd jmp *(%ecx)",},
>  {{0xf2, 0x0f, 0x85, 0xfc, 0xff, 0xff, 0xff, }, 7, 0xfffc, "jcc", 
> "conditional",
>  "f2 0f 85 fc ff ff ff \tbnd jne 3de ",},
> +{{0x0f, 0x3a, 0xcc, 0xc1, 0x00, }, 5, 0, "", "",
> +"0f 3a cc c1 00   \tsha1rnds4 $0x0,%xmm1,%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0xd7, 0x91, }, 5, 0, "", "",
> +"0f 3a cc d7 91   \tsha1rnds4 $0x91,%xmm7,%xmm2",},
> +{{0x0f, 0x3a, 0xcc, 0x00, 0x91, }, 5, 0, "", "",
> +"0f 3a cc 00 91   \tsha1rnds4 $0x91,(%eax),%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0x05, 0x78, 0x56, 0x34, 0x12, 0x91, }, 9, 0, "", "",
> +"0f 3a cc 05 78 56 34 12 91 \tsha1rnds4 $0x91,0x12345678,%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0x18, 0x91, }, 5, 0, "", "",
> +"0f 3a cc 18 91   \tsha1rnds4 $0x91,(%eax),%xmm3",},
> +{{0x0f, 0x3a, 0xcc, 0x04, 0x01, 0x91, }, 6, 0, "", "",
> +"0f 3a cc 04 01 91\tsha1rnds4 $0x91,(%ecx,%eax,1),%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, 0x91, }, 10, 0, "", 
> "",
> +"0f 3a cc 04 05 78 56 34 12 91 \tsha1rnds4 
> $0x91,0x12345678(,%eax,1),%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0x04, 0x08, 0x91, }, 6, 0, "", "",
> +"0f 3a cc 04 08 91\tsha1rnds4 $0x91,(%eax,%ecx,1),%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0x04, 0xc8, 0x91, }, 6, 0, "", "",
> +"0f 3a cc 04 c8 91\tsha1rnds4 $0x91,(%eax,%ecx,8),%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0x40, 0x12, 0x91, }, 6, 0, "", "",
> +"0f 3a cc 40 12 91\tsha1rnds4 $0x91,0x12(%eax),%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0x45, 0x12, 0x91, }, 6, 0, "", "",
> +"0f 3a cc 45 12 91\tsha1rnds4 $0x91,0x12(%ebp),%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0x44, 0x01, 0x12, 0x91, }, 7, 0, "", "",
> +"0f 3a cc 44 01 12 91 \tsha1rnds4 $0x91,0x12(%ecx,%eax,1),%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0x44, 0x05, 0x12, 0x91, }, 7, 0, "", "",
> +"0f 3a cc 44 05 12 91 \tsha1rnds4 $0x91,0x12(%ebp,%eax,1),%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0x44, 0x08, 0x12, 0x91, }, 7, 0, "", "",
> +"0f 3a cc 44 08 12 91 \tsha1rnds4 $0x91,0x12(%eax,%ecx,1),%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0x44, 0xc8, 0x12, 0x91, }, 7, 0, "", "",
> +"0f 3a cc 44 c8 12 91 \tsha1rnds4 $0x91,0x12(%eax,%ecx,8),%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0x80, 0x78, 0x56, 0x34, 0x12, 0x91, }, 9, 0, "", "",
> +"0f 3a cc 80 78 56 34 12 91 \tsha1rnds4 $0x91,0x12345678(%eax),%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0x85, 0x78, 0x56, 0x34, 0x12, 0x91, }, 9, 0, "", "",
> +"0f 3a cc 85 78 56 34 12 91 \tsha1rnds4 $0x91,0x12345678(%ebp),%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0x84, 0x01, 0x78, 0x56, 0x34,

Re: [PATCH 3/4] x86/insn: perf tools: Add new SHA instructions

2015-08-31 Thread Adrian Hunter 

On 31/08/2015 5:50 p.m., Arnaldo Carvalho de Melo wrote:

Em Mon, Aug 31, 2015 at 04:58:41PM +0300, Adrian Hunter escreveu:

Intel SHA Extensions are explained in the Intel Architecture
Instruction Set Extensions Programing Reference (Oct 2014).
There are 7 new instructions.  Add them to the op code map
and the perf tools new instructions test. e.g.

 $ tools/perf/perf test list 2>&1 | grep "x86 ins"


I.e., one could short circuit the 'perf test list' step and use:

perf test "x86 ins" straight away:

[root@zoo linux]# perf test "syscall event"
  2: detect openat syscall event  : Ok
  3: detect openat syscall event on all cpus  : Ok
[root@zoo linux]#


Cool, I'll update the commit messages in V2




 39: Test x86 instruction decoder - new instructions
 $ tools/perf/perf test 39
 39: Test x86 instruction decoder - new instructions  : Ok

Or to see the details:

 $ tools/perf/perf test -v 39 2>&1 | grep sha

Signed-off-by: Adrian Hunter 
---
  arch/x86/lib/x86-opcode-map.txt|   7 +
  tools/perf/tests/insn-x86-dat-32.c | 294 
  tools/perf/tests/insn-x86-dat-64.c | 364 
  tools/perf/tests/insn-x86-dat-src.c| 373 +
  .../perf/util/intel-pt-decoder/x86-opcode-map.txt  |   7 +
  5 files changed, 1045 insertions(+)

diff --git a/arch/x86/lib/x86-opcode-map.txt b/arch/x86/lib/x86-opcode-map.txt
index a02a195d219c..25dad388b371 100644
--- a/arch/x86/lib/x86-opcode-map.txt
+++ b/arch/x86/lib/x86-opcode-map.txt
@@ -736,6 +736,12 @@ bd: vfnmadd231ss/d Vx,Hx,Wx (66),(v),(v1)
  be: vfnmsub231ps/d Vx,Hx,Wx (66),(v)
  bf: vfnmsub231ss/d Vx,Hx,Wx (66),(v),(v1)
  # 0x0f 0x38 0xc0-0xff
+c8: sha1nexte Vdq,Wdq
+c9: sha1msg1 Vdq,Wdq
+ca: sha1msg2 Vdq,Wdq
+cb: sha256rnds2 Vdq,Wdq
+cc: sha256msg1 Vdq,Wdq
+cd: sha256msg2 Vdq,Wdq
  db: VAESIMC Vdq,Wdq (66),(v1)
  dc: VAESENC Vdq,Hdq,Wdq (66),(v1)
  dd: VAESENCLAST Vdq,Hdq,Wdq (66),(v1)
@@ -794,6 +800,7 @@ AVXcode: 3
  61: vpcmpestri Vdq,Wdq,Ib (66),(v1)
  62: vpcmpistrm Vdq,Wdq,Ib (66),(v1)
  63: vpcmpistri Vdq,Wdq,Ib (66),(v1)
+cc: sha1rnds4 Vdq,Wdq,Ib
  df: VAESKEYGEN Vdq,Wdq,Ib (66),(v1)
  f0: RORX Gy,Ey,Ib (F2),(v)
  EndTable
diff --git a/tools/perf/tests/insn-x86-dat-32.c 
b/tools/perf/tests/insn-x86-dat-32.c
index 6a38a34a5a49..83f5078e74e1 100644
--- a/tools/perf/tests/insn-x86-dat-32.c
+++ b/tools/perf/tests/insn-x86-dat-32.c
@@ -322,3 +322,297 @@
  "f2 ff 21 \tbnd jmp *(%ecx)",},
  {{0xf2, 0x0f, 0x85, 0xfc, 0xff, 0xff, 0xff, }, 7, 0xfffc, "jcc", 
"conditional",
  "f2 0f 85 fc ff ff ff \tbnd jne 3de ",},
+{{0x0f, 0x3a, 0xcc, 0xc1, 0x00, }, 5, 0, "", "",
+"0f 3a cc c1 00   \tsha1rnds4 $0x0,%xmm1,%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0xd7, 0x91, }, 5, 0, "", "",
+"0f 3a cc d7 91   \tsha1rnds4 $0x91,%xmm7,%xmm2",},
+{{0x0f, 0x3a, 0xcc, 0x00, 0x91, }, 5, 0, "", "",
+"0f 3a cc 00 91   \tsha1rnds4 $0x91,(%eax),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x05, 0x78, 0x56, 0x34, 0x12, 0x91, }, 9, 0, "", "",
+"0f 3a cc 05 78 56 34 12 91 \tsha1rnds4 $0x91,0x12345678,%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x18, 0x91, }, 5, 0, "", "",
+"0f 3a cc 18 91   \tsha1rnds4 $0x91,(%eax),%xmm3",},
+{{0x0f, 0x3a, 0xcc, 0x04, 0x01, 0x91, }, 6, 0, "", "",
+"0f 3a cc 04 01 91\tsha1rnds4 $0x91,(%ecx,%eax,1),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, 0x91, }, 10, 0, "", "",
+"0f 3a cc 04 05 78 56 34 12 91 \tsha1rnds4 $0x91,0x12345678(,%eax,1),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x04, 0x08, 0x91, }, 6, 0, "", "",
+"0f 3a cc 04 08 91\tsha1rnds4 $0x91,(%eax,%ecx,1),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x04, 0xc8, 0x91, }, 6, 0, "", "",
+"0f 3a cc 04 c8 91\tsha1rnds4 $0x91,(%eax,%ecx,8),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x40, 0x12, 0x91, }, 6, 0, "", "",
+"0f 3a cc 40 12 91\tsha1rnds4 $0x91,0x12(%eax),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x45, 0x12, 0x91, }, 6, 0, "", "",
+"0f 3a cc 45 12 91\tsha1rnds4 $0x91,0x12(%ebp),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x44, 0x01, 0x12, 0x91, }, 7, 0, "", "",
+"0f 3a cc 44 01 12 91 \tsha1rnds4 $0x91,0x12(%ecx,%eax,1),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x44, 0x05, 0x12, 0x91, }, 7, 0, "", "",
+"0f 3a cc 44 05 12 91 \tsha1rnds4 $0x91,0x12(%ebp,%eax,1),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x44, 0x08, 0x12, 0x91, }, 7, 0, "", "",
+"0f 3a cc 44 08 12 91 \tsha1rnds4 $0x91,0x12(%eax,%ecx,1),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x44, 0xc8, 0x12, 0x91, }, 7, 0, "", "",
+"0f 3a cc 44 c8 12 91 \tsha1rnds4 $0x91,0x12(%eax,%ecx,8),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x80, 0x78, 0x56, 0x34, 0x12, 0x91, }, 9, 0, "", "",
+"0f 3a cc 80 78 56 34 12 91 \tsha1rnds4 $0x91,0x12345678(%eax),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x85, 0x78, 0x56, 0x34, 0x12, 0x91, }, 9, 0, "", "",
+"0f 3a cc 85 78 56 34 12 91 \tsha1rnds4 $0x91,0x12345678(%ebp),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, 0x91, }, 10, 0, "", "",
+"0f 3a cc 84 01 78 56 34

RE: [PATCH 3/4] x86/insn: perf tools: Add new SHA instructions

2015-08-31 Thread 平松雅巳 / HIRAMATU，MASAMI 
> From: Adrian Hunter [mailto:adrian.hun...@intel.com]
> 
> Intel SHA Extensions are explained in the Intel Architecture
> Instruction Set Extensions Programing Reference (Oct 2014).
> There are 7 new instructions.  Add them to the op code map
> and the perf tools new instructions test. e.g.
> 
> $ tools/perf/perf test list 2>&1 | grep "x86 ins"
> 39: Test x86 instruction decoder - new instructions
> $ tools/perf/perf test 39
> 39: Test x86 instruction decoder - new instructions  : Ok
> 
> Or to see the details:
> 
> $ tools/perf/perf test -v 39 2>&1 | grep sha

OK, looks fine to me :)

Acked-by: Masami Hiramatsu 

Thanks!

> 
> Signed-off-by: Adrian Hunter 
> ---
>  arch/x86/lib/x86-opcode-map.txt|   7 +
>  tools/perf/tests/insn-x86-dat-32.c | 294 
>  tools/perf/tests/insn-x86-dat-64.c | 364 
>  tools/perf/tests/insn-x86-dat-src.c| 373 
> +
>  .../perf/util/intel-pt-decoder/x86-opcode-map.txt  |   7 +
>  5 files changed, 1045 insertions(+)
> 
> diff --git a/arch/x86/lib/x86-opcode-map.txt b/arch/x86/lib/x86-opcode-map.txt
> index a02a195d219c..25dad388b371 100644
> --- a/arch/x86/lib/x86-opcode-map.txt
> +++ b/arch/x86/lib/x86-opcode-map.txt
> @@ -736,6 +736,12 @@ bd: vfnmadd231ss/d Vx,Hx,Wx (66),(v),(v1)
>  be: vfnmsub231ps/d Vx,Hx,Wx (66),(v)
>  bf: vfnmsub231ss/d Vx,Hx,Wx (66),(v),(v1)
>  # 0x0f 0x38 0xc0-0xff
> +c8: sha1nexte Vdq,Wdq
> +c9: sha1msg1 Vdq,Wdq
> +ca: sha1msg2 Vdq,Wdq
> +cb: sha256rnds2 Vdq,Wdq
> +cc: sha256msg1 Vdq,Wdq
> +cd: sha256msg2 Vdq,Wdq
>  db: VAESIMC Vdq,Wdq (66),(v1)
>  dc: VAESENC Vdq,Hdq,Wdq (66),(v1)
>  dd: VAESENCLAST Vdq,Hdq,Wdq (66),(v1)
> @@ -794,6 +800,7 @@ AVXcode: 3
>  61: vpcmpestri Vdq,Wdq,Ib (66),(v1)
>  62: vpcmpistrm Vdq,Wdq,Ib (66),(v1)
>  63: vpcmpistri Vdq,Wdq,Ib (66),(v1)
> +cc: sha1rnds4 Vdq,Wdq,Ib
>  df: VAESKEYGEN Vdq,Wdq,Ib (66),(v1)
>  f0: RORX Gy,Ey,Ib (F2),(v)
>  EndTable
> diff --git a/tools/perf/tests/insn-x86-dat-32.c 
> b/tools/perf/tests/insn-x86-dat-32.c
> index 6a38a34a5a49..83f5078e74e1 100644
> --- a/tools/perf/tests/insn-x86-dat-32.c
> +++ b/tools/perf/tests/insn-x86-dat-32.c
> @@ -322,3 +322,297 @@
>  "f2 ff 21 \tbnd jmp *(%ecx)",},
>  {{0xf2, 0x0f, 0x85, 0xfc, 0xff, 0xff, 0xff, }, 7, 0xfffc, "jcc", 
> "conditional",
>  "f2 0f 85 fc ff ff ff \tbnd jne 3de ",},
> +{{0x0f, 0x3a, 0xcc, 0xc1, 0x00, }, 5, 0, "", "",
> +"0f 3a cc c1 00   \tsha1rnds4 $0x0,%xmm1,%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0xd7, 0x91, }, 5, 0, "", "",
> +"0f 3a cc d7 91   \tsha1rnds4 $0x91,%xmm7,%xmm2",},
> +{{0x0f, 0x3a, 0xcc, 0x00, 0x91, }, 5, 0, "", "",
> +"0f 3a cc 00 91   \tsha1rnds4 $0x91,(%eax),%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0x05, 0x78, 0x56, 0x34, 0x12, 0x91, }, 9, 0, "", "",
> +"0f 3a cc 05 78 56 34 12 91 \tsha1rnds4 $0x91,0x12345678,%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0x18, 0x91, }, 5, 0, "", "",
> +"0f 3a cc 18 91   \tsha1rnds4 $0x91,(%eax),%xmm3",},
> +{{0x0f, 0x3a, 0xcc, 0x04, 0x01, 0x91, }, 6, 0, "", "",
> +"0f 3a cc 04 01 91\tsha1rnds4 $0x91,(%ecx,%eax,1),%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, 0x91, }, 10, 0, "", 
> "",
> +"0f 3a cc 04 05 78 56 34 12 91 \tsha1rnds4 
> $0x91,0x12345678(,%eax,1),%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0x04, 0x08, 0x91, }, 6, 0, "", "",
> +"0f 3a cc 04 08 91\tsha1rnds4 $0x91,(%eax,%ecx,1),%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0x04, 0xc8, 0x91, }, 6, 0, "", "",
> +"0f 3a cc 04 c8 91\tsha1rnds4 $0x91,(%eax,%ecx,8),%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0x40, 0x12, 0x91, }, 6, 0, "", "",
> +"0f 3a cc 40 12 91\tsha1rnds4 $0x91,0x12(%eax),%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0x45, 0x12, 0x91, }, 6, 0, "", "",
> +"0f 3a cc 45 12 91\tsha1rnds4 $0x91,0x12(%ebp),%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0x44, 0x01, 0x12, 0x91, }, 7, 0, "", "",
> +"0f 3a cc 44 01 12 91 \tsha1rnds4 $0x91,0x12(%ecx,%eax,1),%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0x44, 0x05, 0x12, 0x91, }, 7, 0, "", "",
> +"0f 3a cc 44 05 12 91 \tsha1rnds4 $0x91,0x12(%ebp,%eax,1),%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0x44, 0x08, 0x12, 0x91, }, 7, 0, "", "",
> +"0f 3a cc 44 08 12 91 \tsha1rnds4 $0x91,0x12(%eax,%ecx,1),%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0x44, 0xc8, 0x12, 0x91, }, 7, 0, "", "",
> +"0f 3a cc 44 c8 12 91 \tsha1rnds4 $0x91,0x12(%eax,%ecx,8),%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0x80, 0x78, 0x56, 0x34, 0x12, 0x91, }, 9, 0, "", "",
> +"0f 3a cc 80 78 56 34 12 91 \tsha1rnds4 $0x91,0x12345678(%eax),%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0x85, 0x78, 0x56, 0x34, 0x12, 0x91, }, 9, 0, "", "",
> +"0f 3a cc 85 78 56 34 12 91 \tsha1rnds4 $0x91,0x12345678(%ebp),%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, 0x91, }, 10, 0, "", 
> "",
> +"0f 3a cc 84 01 78 56 34 12 91 \tsha1rnds4 
> $0x91,0x12345678(%ecx,%eax,1),%xmm0",},
> +{{0x0f, 0x3a, 0xcc, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, 0x91, }, 10, 0, "", 
> "",
> +"0f 3a

[PATCH 3/4] x86/insn: perf tools: Add new SHA instructions

2015-08-31 Thread Adrian Hunter 
Intel SHA Extensions are explained in the Intel Architecture
Instruction Set Extensions Programing Reference (Oct 2014).
There are 7 new instructions.  Add them to the op code map
and the perf tools new instructions test. e.g.

$ tools/perf/perf test list 2>&1 | grep "x86 ins"
39: Test x86 instruction decoder - new instructions
$ tools/perf/perf test 39
39: Test x86 instruction decoder - new instructions  : Ok

Or to see the details:

$ tools/perf/perf test -v 39 2>&1 | grep sha

Signed-off-by: Adrian Hunter 
---
 arch/x86/lib/x86-opcode-map.txt|   7 +
 tools/perf/tests/insn-x86-dat-32.c | 294 
 tools/perf/tests/insn-x86-dat-64.c | 364 
 tools/perf/tests/insn-x86-dat-src.c| 373 +
 .../perf/util/intel-pt-decoder/x86-opcode-map.txt  |   7 +
 5 files changed, 1045 insertions(+)

diff --git a/arch/x86/lib/x86-opcode-map.txt b/arch/x86/lib/x86-opcode-map.txt
index a02a195d219c..25dad388b371 100644
--- a/arch/x86/lib/x86-opcode-map.txt
+++ b/arch/x86/lib/x86-opcode-map.txt
@@ -736,6 +736,12 @@ bd: vfnmadd231ss/d Vx,Hx,Wx (66),(v),(v1)
 be: vfnmsub231ps/d Vx,Hx,Wx (66),(v)
 bf: vfnmsub231ss/d Vx,Hx,Wx (66),(v),(v1)
 # 0x0f 0x38 0xc0-0xff
+c8: sha1nexte Vdq,Wdq
+c9: sha1msg1 Vdq,Wdq
+ca: sha1msg2 Vdq,Wdq
+cb: sha256rnds2 Vdq,Wdq
+cc: sha256msg1 Vdq,Wdq
+cd: sha256msg2 Vdq,Wdq
 db: VAESIMC Vdq,Wdq (66),(v1)
 dc: VAESENC Vdq,Hdq,Wdq (66),(v1)
 dd: VAESENCLAST Vdq,Hdq,Wdq (66),(v1)
@@ -794,6 +800,7 @@ AVXcode: 3
 61: vpcmpestri Vdq,Wdq,Ib (66),(v1)
 62: vpcmpistrm Vdq,Wdq,Ib (66),(v1)
 63: vpcmpistri Vdq,Wdq,Ib (66),(v1)
+cc: sha1rnds4 Vdq,Wdq,Ib
 df: VAESKEYGEN Vdq,Wdq,Ib (66),(v1)
 f0: RORX Gy,Ey,Ib (F2),(v)
 EndTable
diff --git a/tools/perf/tests/insn-x86-dat-32.c 
b/tools/perf/tests/insn-x86-dat-32.c
index 6a38a34a5a49..83f5078e74e1 100644
--- a/tools/perf/tests/insn-x86-dat-32.c
+++ b/tools/perf/tests/insn-x86-dat-32.c
@@ -322,3 +322,297 @@
 "f2 ff 21 \tbnd jmp *(%ecx)",},
 {{0xf2, 0x0f, 0x85, 0xfc, 0xff, 0xff, 0xff, }, 7, 0xfffc, "jcc", 
"conditional",
 "f2 0f 85 fc ff ff ff \tbnd jne 3de ",},
+{{0x0f, 0x3a, 0xcc, 0xc1, 0x00, }, 5, 0, "", "",
+"0f 3a cc c1 00   \tsha1rnds4 $0x0,%xmm1,%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0xd7, 0x91, }, 5, 0, "", "",
+"0f 3a cc d7 91   \tsha1rnds4 $0x91,%xmm7,%xmm2",},
+{{0x0f, 0x3a, 0xcc, 0x00, 0x91, }, 5, 0, "", "",
+"0f 3a cc 00 91   \tsha1rnds4 $0x91,(%eax),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x05, 0x78, 0x56, 0x34, 0x12, 0x91, }, 9, 0, "", "",
+"0f 3a cc 05 78 56 34 12 91 \tsha1rnds4 $0x91,0x12345678,%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x18, 0x91, }, 5, 0, "", "",
+"0f 3a cc 18 91   \tsha1rnds4 $0x91,(%eax),%xmm3",},
+{{0x0f, 0x3a, 0xcc, 0x04, 0x01, 0x91, }, 6, 0, "", "",
+"0f 3a cc 04 01 91\tsha1rnds4 $0x91,(%ecx,%eax,1),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, 0x91, }, 10, 0, "", "",
+"0f 3a cc 04 05 78 56 34 12 91 \tsha1rnds4 $0x91,0x12345678(,%eax,1),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x04, 0x08, 0x91, }, 6, 0, "", "",
+"0f 3a cc 04 08 91\tsha1rnds4 $0x91,(%eax,%ecx,1),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x04, 0xc8, 0x91, }, 6, 0, "", "",
+"0f 3a cc 04 c8 91\tsha1rnds4 $0x91,(%eax,%ecx,8),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x40, 0x12, 0x91, }, 6, 0, "", "",
+"0f 3a cc 40 12 91\tsha1rnds4 $0x91,0x12(%eax),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x45, 0x12, 0x91, }, 6, 0, "", "",
+"0f 3a cc 45 12 91\tsha1rnds4 $0x91,0x12(%ebp),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x44, 0x01, 0x12, 0x91, }, 7, 0, "", "",
+"0f 3a cc 44 01 12 91 \tsha1rnds4 $0x91,0x12(%ecx,%eax,1),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x44, 0x05, 0x12, 0x91, }, 7, 0, "", "",
+"0f 3a cc 44 05 12 91 \tsha1rnds4 $0x91,0x12(%ebp,%eax,1),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x44, 0x08, 0x12, 0x91, }, 7, 0, "", "",
+"0f 3a cc 44 08 12 91 \tsha1rnds4 $0x91,0x12(%eax,%ecx,1),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x44, 0xc8, 0x12, 0x91, }, 7, 0, "", "",
+"0f 3a cc 44 c8 12 91 \tsha1rnds4 $0x91,0x12(%eax,%ecx,8),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x80, 0x78, 0x56, 0x34, 0x12, 0x91, }, 9, 0, "", "",
+"0f 3a cc 80 78 56 34 12 91 \tsha1rnds4 $0x91,0x12345678(%eax),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x85, 0x78, 0x56, 0x34, 0x12, 0x91, }, 9, 0, "", "",
+"0f 3a cc 85 78 56 34 12 91 \tsha1rnds4 $0x91,0x12345678(%ebp),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, 0x91, }, 10, 0, "", "",
+"0f 3a cc 84 01 78 56 34 12 91 \tsha1rnds4 
$0x91,0x12345678(%ecx,%eax,1),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, 0x91, }, 10, 0, "", "",
+"0f 3a cc 84 05 78 56 34 12 91 \tsha1rnds4 
$0x91,0x12345678(%ebp,%eax,1),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, 0x91, }, 10, 0, "", "",
+"0f 3a cc 84 08 78 56 34 12 91 \tsha1rnds4 
$0x91,0x12345678(%eax,%ecx,1),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, 0x91, }, 10, 0, "", "",
+"0f 3a cc 84 c8 78 56 34 12 91