Re: [PATCH 3/5] Documentation: bindings: add dt documentation for rk3399 dmc

[Chanwoo Choi]

On 2016년 09월 02일 07:31, Lin Huang wrote:
> This patch adds the documentation for rockchip rk3399 dmc driver.
> 
> Signed-off-by: Lin Huang 
> ---
> Changes in v8:
> - add ddr timing properties
> 
> Changes in v7:
> -None
> 
> Changes in v6:
> -Add more detail in Documentation
> 
> Changes in v5:
> -None
> 
> Changes in v4:
> -None
> 
> Changes in v3:
> -None
> 
> Changes in v2:
> -None 
> 
> Changes in v1:
> -None
> 
>  .../devicetree/bindings/devfreq/rk3399_dmc.txt | 173 
> +
>  1 file changed, 173 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
> 
> diff --git a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt 
> b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
> new file mode 100644
> index 000..1f39b5cb
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
> @@ -0,0 +1,173 @@
> +* Rockchip rk3399 DMC(Dynamic Memory Controller) device
> +
> +Required properties:
> +- compatible: Must be "rockchip,rk3399-dmc".
> +- devfreq-events: Node to get DDR loading, Refer to
> +  Documentation/devicetree/bindings/devfreq/
> +  rockchip-dfi.txt
> +- interrupts: The interrupt number to the CPU. The interrupt
> +  specifier format depends on the interrupt controller.
> +  It should be DCF interrupts, when DDR dvfs finish,
> +  it will happen.
> +- clocks: Phandles for clock specified in "clock-names" property
> +- clock-names :   The name of clock used by the DFI, must be
> +  "pclk_ddr_mon";
> +- operating-points-v2:Refer to 
> Documentation/devicetree/bindings/power/opp.txt
> +  for details.
> +- center-supply:  DMC supply node.
> +- status: Marks the node enabled/disabled.
> +
> +Following properties are ddr timing:
> +
> +- dram_speed_bin :Value is defined at include/dt-bindings/clock/ddr.h,
> +  it select ddr3 cl-trp-trcd type, default value
> +  "DDR3_DEFAULT".it must selected according to
> +  "Speed Bin" in ddr3 datasheet, DO NOT use smaller
> +  "Speed Bin" than ddr3 exactly is.
> +
> +- pd_idle :   Config the PD_IDLE value, defined the power-down idle
> +  period, memories are places into power-down mode if
> +  bus is idle for PD_IDLE DFI clocks.
> +
> +- sr_idle :   Configure the SR_IDLE value, defined the selfrefresh
> +  idle period, memories are places into self-refresh
> +  mode if bus is idle for SR_IDLE*1024 DFI clocks
> +  (DFI clocks freq is half of dram's clocks), defaule
> +  value is "0".
> +
> +- sr_mc_gate_idle :   Defined the self-refresh with memory and controller
> +  clock gating idle period, memories are places into
> +  self-refresh mode and memory controller clock arg
> +  gating if bus is idle for sr_mc_gate_idle*1024 DFI
> +  clocks.
> +
> +- srpd_lite_idle :Defined the self-refresh power down idle period,
> +  memories are places into self-refresh power down
> +  mode if bus is idle for srpd_lite_idle*1024 DFI
> +  clocks. This parameter is for LPDDR4 only.
> +
> +- standby_idle :  Defined the standby idle period, memories are places
> +  into self-refresh than controller, pi, phy and dram
> +  clock will gating if bus is idle for
> +  standby_idle * DFI clocks.
> +
> +- dram_dll_disb_freq :It's defined the DDR3 dll bypass frequency in 
> MHz
> +  when ddr freq less than DRAM_DLL_DISB_FREQ, ddr3
> +  dll will bypssed note: if dll was bypassed, the
> +  odt also stop working.
> +
> +- phy_dll_disb_freq : Defined the PHY dll bypass frequency in MHz 
> (Mega Hz),
> +  when ddr freq less than DRAM_DLL_DISB_FREQ, phy dll
> +  will bypssed. note: phy dll and phy odt are
> +  independent
> +
> +- ddr3_odt_disb_freq :When dram type is DDR3, this parameter defined 
> the
> +  odt disable frequency in MHz (Mega Hz), when ddr
> +  frequency less then ddr3_odt_disb_freq, the odt
> +  on dram side and controller side are both disabled.
> +
> +- ddr3_drv :  When dram type is DDR3, this parameter define the
> +  dram side driver stength in ohm, default value is
> +  DDR3_DS_40ohm.
> +
> +- ddr3_odt :  When dram type is DDR3, this parameter define the
> +  

Re: [PATCH 3/5] Documentation: bindings: add dt documentation for rk3399 dmc

[Chanwoo Choi]

On 2016년 09월 02일 07:31, Lin Huang wrote:
> This patch adds the documentation for rockchip rk3399 dmc driver.
> 
> Signed-off-by: Lin Huang 
> ---
> Changes in v8:
> - add ddr timing properties
> 
> Changes in v7:
> -None
> 
> Changes in v6:
> -Add more detail in Documentation
> 
> Changes in v5:
> -None
> 
> Changes in v4:
> -None
> 
> Changes in v3:
> -None
> 
> Changes in v2:
> -None 
> 
> Changes in v1:
> -None
> 
>  .../devicetree/bindings/devfreq/rk3399_dmc.txt | 173 
> +
>  1 file changed, 173 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
> 
> diff --git a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt 
> b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
> new file mode 100644
> index 000..1f39b5cb
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
> @@ -0,0 +1,173 @@
> +* Rockchip rk3399 DMC(Dynamic Memory Controller) device
> +
> +Required properties:
> +- compatible: Must be "rockchip,rk3399-dmc".
> +- devfreq-events: Node to get DDR loading, Refer to
> +  Documentation/devicetree/bindings/devfreq/
> +  rockchip-dfi.txt
> +- interrupts: The interrupt number to the CPU. The interrupt
> +  specifier format depends on the interrupt controller.
> +  It should be DCF interrupts, when DDR dvfs finish,
> +  it will happen.
> +- clocks: Phandles for clock specified in "clock-names" property
> +- clock-names :   The name of clock used by the DFI, must be
> +  "pclk_ddr_mon";
> +- operating-points-v2:Refer to 
> Documentation/devicetree/bindings/power/opp.txt
> +  for details.
> +- center-supply:  DMC supply node.
> +- status: Marks the node enabled/disabled.
> +
> +Following properties are ddr timing:
> +
> +- dram_speed_bin :Value is defined at include/dt-bindings/clock/ddr.h,
> +  it select ddr3 cl-trp-trcd type, default value
> +  "DDR3_DEFAULT".it must selected according to
> +  "Speed Bin" in ddr3 datasheet, DO NOT use smaller
> +  "Speed Bin" than ddr3 exactly is.
> +
> +- pd_idle :   Config the PD_IDLE value, defined the power-down idle
> +  period, memories are places into power-down mode if
> +  bus is idle for PD_IDLE DFI clocks.
> +
> +- sr_idle :   Configure the SR_IDLE value, defined the selfrefresh
> +  idle period, memories are places into self-refresh
> +  mode if bus is idle for SR_IDLE*1024 DFI clocks
> +  (DFI clocks freq is half of dram's clocks), defaule
> +  value is "0".
> +
> +- sr_mc_gate_idle :   Defined the self-refresh with memory and controller
> +  clock gating idle period, memories are places into
> +  self-refresh mode and memory controller clock arg
> +  gating if bus is idle for sr_mc_gate_idle*1024 DFI
> +  clocks.
> +
> +- srpd_lite_idle :Defined the self-refresh power down idle period,
> +  memories are places into self-refresh power down
> +  mode if bus is idle for srpd_lite_idle*1024 DFI
> +  clocks. This parameter is for LPDDR4 only.
> +
> +- standby_idle :  Defined the standby idle period, memories are places
> +  into self-refresh than controller, pi, phy and dram
> +  clock will gating if bus is idle for
> +  standby_idle * DFI clocks.
> +
> +- dram_dll_disb_freq :It's defined the DDR3 dll bypass frequency in 
> MHz
> +  when ddr freq less than DRAM_DLL_DISB_FREQ, ddr3
> +  dll will bypssed note: if dll was bypassed, the
> +  odt also stop working.
> +
> +- phy_dll_disb_freq : Defined the PHY dll bypass frequency in MHz 
> (Mega Hz),
> +  when ddr freq less than DRAM_DLL_DISB_FREQ, phy dll
> +  will bypssed. note: phy dll and phy odt are
> +  independent
> +
> +- ddr3_odt_disb_freq :When dram type is DDR3, this parameter defined 
> the
> +  odt disable frequency in MHz (Mega Hz), when ddr
> +  frequency less then ddr3_odt_disb_freq, the odt
> +  on dram side and controller side are both disabled.
> +
> +- ddr3_drv :  When dram type is DDR3, this parameter define the
> +  dram side driver stength in ohm, default value is
> +  DDR3_DS_40ohm.
> +
> +- ddr3_odt :  When dram type is DDR3, this parameter define the
> +  dram side 

[PATCH 3/5] Documentation: bindings: add dt documentation for rk3399 dmc

[Lin Huang]

This patch adds the documentation for rockchip rk3399 dmc driver.

Signed-off-by: Lin Huang 
---
Changes in v8:
- add ddr timing properties

Changes in v7:
-None

Changes in v6:
-Add more detail in Documentation

Changes in v5:
-None

Changes in v4:
-None

Changes in v3:
-None

Changes in v2:
-None 

Changes in v1:
-None

 .../devicetree/bindings/devfreq/rk3399_dmc.txt | 173 +
 1 file changed, 173 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt

diff --git a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt 
b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
new file mode 100644
index 000..1f39b5cb
--- /dev/null
+++ b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
@@ -0,0 +1,173 @@
+* Rockchip rk3399 DMC(Dynamic Memory Controller) device
+
+Required properties:
+- compatible:   Must be "rockchip,rk3399-dmc".
+- devfreq-events:   Node to get DDR loading, Refer to
+Documentation/devicetree/bindings/devfreq/
+rockchip-dfi.txt
+- interrupts:   The interrupt number to the CPU. The interrupt
+specifier format depends on the interrupt controller.
+It should be DCF interrupts, when DDR dvfs finish,
+it will happen.
+- clocks:   Phandles for clock specified in "clock-names" property
+- clock-names : The name of clock used by the DFI, must be
+"pclk_ddr_mon";
+- operating-points-v2:  Refer to 
Documentation/devicetree/bindings/power/opp.txt
+for details.
+- center-supply:DMC supply node.
+- status:   Marks the node enabled/disabled.
+
+Following properties are ddr timing:
+
+- dram_speed_bin :  Value is defined at include/dt-bindings/clock/ddr.h,
+it select ddr3 cl-trp-trcd type, default value
+"DDR3_DEFAULT".it must selected according to
+"Speed Bin" in ddr3 datasheet, DO NOT use smaller
+"Speed Bin" than ddr3 exactly is.
+
+- pd_idle : Config the PD_IDLE value, defined the power-down idle
+period, memories are places into power-down mode if
+bus is idle for PD_IDLE DFI clocks.
+
+- sr_idle : Configure the SR_IDLE value, defined the selfrefresh
+idle period, memories are places into self-refresh
+mode if bus is idle for SR_IDLE*1024 DFI clocks
+(DFI clocks freq is half of dram's clocks), defaule
+value is "0".
+
+- sr_mc_gate_idle : Defined the self-refresh with memory and controller
+clock gating idle period, memories are places into
+self-refresh mode and memory controller clock arg
+gating if bus is idle for sr_mc_gate_idle*1024 DFI
+clocks.
+
+- srpd_lite_idle :  Defined the self-refresh power down idle period,
+memories are places into self-refresh power down
+mode if bus is idle for srpd_lite_idle*1024 DFI
+clocks. This parameter is for LPDDR4 only.
+
+- standby_idle :Defined the standby idle period, memories are places
+into self-refresh than controller, pi, phy and dram
+clock will gating if bus is idle for
+standby_idle * DFI clocks.
+
+- dram_dll_disb_freq :  It's defined the DDR3 dll bypass frequency in MHz
+when ddr freq less than DRAM_DLL_DISB_FREQ, ddr3
+dll will bypssed note: if dll was bypassed, the
+odt also stop working.
+
+- phy_dll_disb_freq :   Defined the PHY dll bypass frequency in MHz (Mega Hz),
+when ddr freq less than DRAM_DLL_DISB_FREQ, phy dll
+will bypssed. note: phy dll and phy odt are
+independent
+
+- ddr3_odt_disb_freq :  When dram type is DDR3, this parameter defined the
+odt disable frequency in MHz (Mega Hz), when ddr
+frequency less then ddr3_odt_disb_freq, the odt
+on dram side and controller side are both disabled.
+
+- ddr3_drv :When dram type is DDR3, this parameter define the
+dram side driver stength in ohm, default value is
+DDR3_DS_40ohm.
+
+- ddr3_odt :When dram type is DDR3, this parameter define the
+dram side ODT stength in ohm, default value is
+DDR3_ODT_120ohm.
+
+- phy_ddr3_ca_drv : When dram type is DDR3, this parameter define the phy
+side CA 

[PATCH 3/5] Documentation: bindings: add dt documentation for rk3399 dmc

[Lin Huang]

This patch adds the documentation for rockchip rk3399 dmc driver.

Signed-off-by: Lin Huang 
---
Changes in v8:
- add ddr timing properties

Changes in v7:
-None

Changes in v6:
-Add more detail in Documentation

Changes in v5:
-None

Changes in v4:
-None

Changes in v3:
-None

Changes in v2:
-None 

Changes in v1:
-None

 .../devicetree/bindings/devfreq/rk3399_dmc.txt | 173 +
 1 file changed, 173 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt

diff --git a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt 
b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
new file mode 100644
index 000..1f39b5cb
--- /dev/null
+++ b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
@@ -0,0 +1,173 @@
+* Rockchip rk3399 DMC(Dynamic Memory Controller) device
+
+Required properties:
+- compatible:   Must be "rockchip,rk3399-dmc".
+- devfreq-events:   Node to get DDR loading, Refer to
+Documentation/devicetree/bindings/devfreq/
+rockchip-dfi.txt
+- interrupts:   The interrupt number to the CPU. The interrupt
+specifier format depends on the interrupt controller.
+It should be DCF interrupts, when DDR dvfs finish,
+it will happen.
+- clocks:   Phandles for clock specified in "clock-names" property
+- clock-names : The name of clock used by the DFI, must be
+"pclk_ddr_mon";
+- operating-points-v2:  Refer to 
Documentation/devicetree/bindings/power/opp.txt
+for details.
+- center-supply:DMC supply node.
+- status:   Marks the node enabled/disabled.
+
+Following properties are ddr timing:
+
+- dram_speed_bin :  Value is defined at include/dt-bindings/clock/ddr.h,
+it select ddr3 cl-trp-trcd type, default value
+"DDR3_DEFAULT".it must selected according to
+"Speed Bin" in ddr3 datasheet, DO NOT use smaller
+"Speed Bin" than ddr3 exactly is.
+
+- pd_idle : Config the PD_IDLE value, defined the power-down idle
+period, memories are places into power-down mode if
+bus is idle for PD_IDLE DFI clocks.
+
+- sr_idle : Configure the SR_IDLE value, defined the selfrefresh
+idle period, memories are places into self-refresh
+mode if bus is idle for SR_IDLE*1024 DFI clocks
+(DFI clocks freq is half of dram's clocks), defaule
+value is "0".
+
+- sr_mc_gate_idle : Defined the self-refresh with memory and controller
+clock gating idle period, memories are places into
+self-refresh mode and memory controller clock arg
+gating if bus is idle for sr_mc_gate_idle*1024 DFI
+clocks.
+
+- srpd_lite_idle :  Defined the self-refresh power down idle period,
+memories are places into self-refresh power down
+mode if bus is idle for srpd_lite_idle*1024 DFI
+clocks. This parameter is for LPDDR4 only.
+
+- standby_idle :Defined the standby idle period, memories are places
+into self-refresh than controller, pi, phy and dram
+clock will gating if bus is idle for
+standby_idle * DFI clocks.
+
+- dram_dll_disb_freq :  It's defined the DDR3 dll bypass frequency in MHz
+when ddr freq less than DRAM_DLL_DISB_FREQ, ddr3
+dll will bypssed note: if dll was bypassed, the
+odt also stop working.
+
+- phy_dll_disb_freq :   Defined the PHY dll bypass frequency in MHz (Mega Hz),
+when ddr freq less than DRAM_DLL_DISB_FREQ, phy dll
+will bypssed. note: phy dll and phy odt are
+independent
+
+- ddr3_odt_disb_freq :  When dram type is DDR3, this parameter defined the
+odt disable frequency in MHz (Mega Hz), when ddr
+frequency less then ddr3_odt_disb_freq, the odt
+on dram side and controller side are both disabled.
+
+- ddr3_drv :When dram type is DDR3, this parameter define the
+dram side driver stength in ohm, default value is
+DDR3_DS_40ohm.
+
+- ddr3_odt :When dram type is DDR3, this parameter define the
+dram side ODT stength in ohm, default value is
+DDR3_ODT_120ohm.
+
+- phy_ddr3_ca_drv : When dram type is DDR3, this parameter define the phy
+side CA line(incluing command