Re: [PATCH V3] gpio: New driver for LSI ZEVIO SoCs
On 08/25/2013 01:44 PM, Fabian Vogt wrote: > Hi, > >> On 08/07/2013 06:53 AM, Fabian Vogt wrote: >>> This driver supports the GPIO controller found in LSI ZEVIO SoCs. >>> It has been successfully tested on a TI nspire CX calculator. >> >>> diff --git a/Documentation/devicetree/bindings/gpio/gpio-zevio.txt >>> b/Documentation/devicetree/bindings/gpio/gpio-zevio.txt >> >>> +Zevio GPIO controller >>> + >>> +Required properties: >>> +- compatible = "lsi,zevio-gpio" >> >> Is there only one zevio chip, or a series? Is "zevio" the full name of >> the chip, including any version number? > > We don't know, it's a relableled chip with > TI-NSPIRE / L9A0702 / TI-NS2006A-0 / LSI LOGIC / ZEVIO / U 0714 / > WYJ14052-1 > on it. But this driver should match the other drivers (lsi,zevio-intc, > lsi,zevio-timer). OK, I guess that's fine then. I suppose if we find "zevio2" chips, we can always use that for the compatible value later. >>> +- reg = >>> +- #gpio-cells = <2> >>> +- gpio-controller; >>> + >>> +Optional: >>> +- #ngpios = <32>: Number of GPIOs. Defaults to 32 if absent >> >> Perhaps one can derive that from the compatible value? The fact this >> property exists implies there's more than one zevio chip, so perhaps >> each should have an explicit compatible value described above? > > I added it just for someone who maybe needs it. It's only two lines and > maybe > it'll be helpful for someone. We don't know whether some similiar or > this controller > exist in different configurations (pin count, section sice, register > layout). > Also I hate hardcoded values which require a recompile to change.. If there's no reason for this property, I think we should remove it. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH V3] gpio: New driver for LSI ZEVIO SoCs
On 08/25/2013 01:44 PM, Fabian Vogt wrote: Hi, On 08/07/2013 06:53 AM, Fabian Vogt wrote: This driver supports the GPIO controller found in LSI ZEVIO SoCs. It has been successfully tested on a TI nspire CX calculator. diff --git a/Documentation/devicetree/bindings/gpio/gpio-zevio.txt b/Documentation/devicetree/bindings/gpio/gpio-zevio.txt +Zevio GPIO controller + +Required properties: +- compatible = lsi,zevio-gpio Is there only one zevio chip, or a series? Is zevio the full name of the chip, including any version number? We don't know, it's a relableled chip with TI-NSPIRE / L9A0702 / TI-NS2006A-0 / LSI LOGIC / ZEVIO / U 0714 / WYJ14052-1 on it. But this driver should match the other drivers (lsi,zevio-intc, lsi,zevio-timer). OK, I guess that's fine then. I suppose if we find zevio2 chips, we can always use that for the compatible value later. +- reg = BASEADDR SIZE +- #gpio-cells = 2 +- gpio-controller; + +Optional: +- #ngpios = 32: Number of GPIOs. Defaults to 32 if absent Perhaps one can derive that from the compatible value? The fact this property exists implies there's more than one zevio chip, so perhaps each should have an explicit compatible value described above? I added it just for someone who maybe needs it. It's only two lines and maybe it'll be helpful for someone. We don't know whether some similiar or this controller exist in different configurations (pin count, section sice, register layout). Also I hate hardcoded values which require a recompile to change.. If there's no reason for this property, I think we should remove it. -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH V3] gpio: New driver for LSI ZEVIO SoCs
Hi, On 08/07/2013 06:53 AM, Fabian Vogt wrote: This driver supports the GPIO controller found in LSI ZEVIO SoCs. It has been successfully tested on a TI nspire CX calculator. diff --git a/Documentation/devicetree/bindings/gpio/gpio-zevio.txt b/Documentation/devicetree/bindings/gpio/gpio-zevio.txt +Zevio GPIO controller + +Required properties: +- compatible = "lsi,zevio-gpio" Is there only one zevio chip, or a series? Is "zevio" the full name of the chip, including any version number? We don't know, it's a relableled chip with TI-NSPIRE / L9A0702 / TI-NS2006A-0 / LSI LOGIC / ZEVIO / U 0714 / WYJ14052-1 on it. But this driver should match the other drivers (lsi,zevio-intc, lsi,zevio-timer). +- reg = +- #gpio-cells = <2> +- gpio-controller; + +Optional: +- #ngpios = <32>: Number of GPIOs. Defaults to 32 if absent Perhaps one can derive that from the compatible value? The fact this property exists implies there's more than one zevio chip, so perhaps each should have an explicit compatible value described above? I added it just for someone who maybe needs it. It's only two lines and maybe it'll be helpful for someone. We don't know whether some similiar or this controller exist in different configurations (pin count, section sice, register layout). Also I hate hardcoded values which require a recompile to change.. Is the GPIO block not also an interrupt source/controller? I see the following in the patch, and references to some IRQ registers... + select GENERIC_IRQ_CHIP I forgot to remove this line after testing the interrupts, the tests went horribly (hard lockups)... V4 should be underway soon. Bye, Fabian -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH V3] gpio: New driver for LSI ZEVIO SoCs
Hi, On 08/07/2013 06:53 AM, Fabian Vogt wrote: This driver supports the GPIO controller found in LSI ZEVIO SoCs. It has been successfully tested on a TI nspire CX calculator. diff --git a/Documentation/devicetree/bindings/gpio/gpio-zevio.txt b/Documentation/devicetree/bindings/gpio/gpio-zevio.txt +Zevio GPIO controller + +Required properties: +- compatible = lsi,zevio-gpio Is there only one zevio chip, or a series? Is zevio the full name of the chip, including any version number? We don't know, it's a relableled chip with TI-NSPIRE / L9A0702 / TI-NS2006A-0 / LSI LOGIC / ZEVIO / U 0714 / WYJ14052-1 on it. But this driver should match the other drivers (lsi,zevio-intc, lsi,zevio-timer). +- reg = BASEADDR SIZE +- #gpio-cells = 2 +- gpio-controller; + +Optional: +- #ngpios = 32: Number of GPIOs. Defaults to 32 if absent Perhaps one can derive that from the compatible value? The fact this property exists implies there's more than one zevio chip, so perhaps each should have an explicit compatible value described above? I added it just for someone who maybe needs it. It's only two lines and maybe it'll be helpful for someone. We don't know whether some similiar or this controller exist in different configurations (pin count, section sice, register layout). Also I hate hardcoded values which require a recompile to change.. Is the GPIO block not also an interrupt source/controller? I see the following in the patch, and references to some IRQ registers... + select GENERIC_IRQ_CHIP I forgot to remove this line after testing the interrupts, the tests went horribly (hard lockups)... V4 should be underway soon. Bye, Fabian -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH V3] gpio: New driver for LSI ZEVIO SoCs
On 08/07/2013 06:53 AM, Fabian Vogt wrote: > This driver supports the GPIO controller found in LSI ZEVIO SoCs. > It has been successfully tested on a TI nspire CX calculator. > diff --git a/Documentation/devicetree/bindings/gpio/gpio-zevio.txt > b/Documentation/devicetree/bindings/gpio/gpio-zevio.txt > +Zevio GPIO controller > + > +Required properties: > +- compatible = "lsi,zevio-gpio" Is there only one zevio chip, or a series? Is "zevio" the full name of the chip, including any version number? > +- reg = > +- #gpio-cells = <2> > +- gpio-controller; > + > +Optional: > +- #ngpios = <32>: Number of GPIOs. Defaults to 32 if absent Perhaps one can derive that from the compatible value? The fact this property exists implies there's more than one zevio chip, so perhaps each should have an explicit compatible value described above? Is the GPIO block not also an interrupt source/controller? I see the following in the patch, and references to some IRQ registers... > + select GENERIC_IRQ_CHIP -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH V3] gpio: New driver for LSI ZEVIO SoCs
On 08/07/2013 06:53 AM, Fabian Vogt wrote: This driver supports the GPIO controller found in LSI ZEVIO SoCs. It has been successfully tested on a TI nspire CX calculator. diff --git a/Documentation/devicetree/bindings/gpio/gpio-zevio.txt b/Documentation/devicetree/bindings/gpio/gpio-zevio.txt +Zevio GPIO controller + +Required properties: +- compatible = lsi,zevio-gpio Is there only one zevio chip, or a series? Is zevio the full name of the chip, including any version number? +- reg = BASEADDR SIZE +- #gpio-cells = 2 +- gpio-controller; + +Optional: +- #ngpios = 32: Number of GPIOs. Defaults to 32 if absent Perhaps one can derive that from the compatible value? The fact this property exists implies there's more than one zevio chip, so perhaps each should have an explicit compatible value described above? Is the GPIO block not also an interrupt source/controller? I see the following in the patch, and references to some IRQ registers... + select GENERIC_IRQ_CHIP -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH V3] gpio: New driver for LSI ZEVIO SoCs
This driver supports the GPIO controller found in LSI ZEVIO SoCs.
It has been successfully tested on a TI nspire CX calculator.
---
.../devicetree/bindings/gpio/gpio-zevio.txt| 18 ++
drivers/gpio/Kconfig | 7 +
drivers/gpio/Makefile | 1 +
drivers/gpio/gpio-zevio.c | 212 +
4 files changed, 238 insertions(+)
create mode 100644 Documentation/devicetree/bindings/gpio/gpio-zevio.txt
create mode 100644 drivers/gpio/gpio-zevio.c
diff --git a/Documentation/devicetree/bindings/gpio/gpio-zevio.txt
b/Documentation/devicetree/bindings/gpio/gpio-zevio.txt
new file mode 100644
index 000..892f953
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio-zevio.txt
@@ -0,0 +1,18 @@
+Zevio GPIO controller
+
+Required properties:
+- compatible = "lsi,zevio-gpio"
+- reg =
+- #gpio-cells = <2>
+- gpio-controller;
+
+Optional:
+- #ngpios = <32>: Number of GPIOs. Defaults to 32 if absent
+
+Example:
+ gpio: gpio@9000 {
+ compatible = "lsi,zevio-gpio";
+ reg = <0x9000 0x1000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index b2450ba..ba8c357 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -138,6 +138,13 @@ config GPIO_EP93XX
depends on ARCH_EP93XX
select GPIO_GENERIC
+config GPIO_ZEVIO
+ bool "LSI ZEVIO SoC memory mapped GPIOs"
+ depends on ARCH_NSPIRE
+ select GENERIC_IRQ_CHIP
+ help
+ Say yes here to support the GPIO controller in LSI ZEVIO SoCs.
+
config GPIO_MM_LANTIQ
bool "Lantiq Memory mapped GPIOs"
depends on LANTIQ && SOC_XWAY
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index ef3e983..b70cb1b 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -87,3 +87,4 @@ obj-$(CONFIG_GPIO_WM831X) += gpio-wm831x.o
obj-$(CONFIG_GPIO_WM8350) += gpio-wm8350.o
obj-$(CONFIG_GPIO_WM8994) += gpio-wm8994.o
obj-$(CONFIG_GPIO_XILINX) += gpio-xilinx.o
+obj-$(CONFIG_GPIO_ZEVIO) += gpio-zevio.o
diff --git a/drivers/gpio/gpio-zevio.c b/drivers/gpio/gpio-zevio.c
new file mode 100644
index 000..e4d5fd7
--- /dev/null
+++ b/drivers/gpio/gpio-zevio.c
@@ -0,0 +1,212 @@
+/*
+ * GPIO controller in LSI ZEVIO SoCs.
+ *
+ * Author: Fabian Vogt
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/*
+ * Memory layout:
+ * This chip has four gpio sections, each controls 8 GPIOs.
+ * Bit 0 in section 0 is GPIO 0, bit 2 in section 1 is GPIO 10.
+ * Disclaimer: Reverse engineered!
+ * For more information refer to:
+ *
http://hackspire.unsads.com/wiki/index.php/Memory-mapped_I/O_ports#9000_-_General_Purpose_I.2FO_.28GPIO.29
+ *
+ * 0x00-0x3F: Section 0
+ * +0x00: Masked interrupt status (read-only)
+ * +0x04: R: Interrupt status W: Reset interrupt status
+ * +0x08: R: Interrupt mask W: Mask interrupt
+ * +0x0C: W: Unmask interrupt (write-only)
+ * +0x10: Direction: I/O=1/0
+ * +0x14: Output
+ * +0x18: Input (read-only)
+ * +0x20: R: Sticky interrupts W: Set sticky interrupt
+ * 0x40-0x7F: Section 1
+ * 0x80-0xBF: Section 2
+ * 0xC0-0xFF: Section 3
+ */
+
+#define ZEVIO_GPIO_SECTION_SIZE0x40
+
+#define ZEVIO_GPIO_INT_MASKED_STATUS_OFFSET0x00
+#define ZEVIO_GPIO_INT_STATUS_OFFSET 0x04
+#define ZEVIO_GPIO_INT_UNMASK_OFFSET 0x08
+#define ZEVIO_GPIO_INT_MASK_OFFSET 0x0C
+#define ZEVIO_GPIO_DIRECTION_OFFSET0x10
+#define ZEVIO_GPIO_OUTPUT_OFFSET 0x14
+#define ZEVIO_GPIO_INPUT_OFFSET0x18
+#define ZEVIO_GPIO_INT_STICKY_OFFSET 0x20
+
+#define to_zevio_gpio(chip) container_of(to_of_mm_gpio_chip(chip), \
+ struct zevio_gpio, chip)
+
+/* Bit of GPIO in section */
+#define ZEVIO_GPIO_BIT(gpio) (gpio&7)
+/* Offset to section of GPIO relative to base */
+#define ZEVIO_GPIO_SECTION_OFFSET(gpio) (((gpio>>3)&3)*ZEVIO_GPIO_SECTION_SIZE)
+/* Address of register, which is responsible for given GPIO */
+#define ZEVIO_GPIO(cntrlr, gpio, reg) IOMEM(cntrlr->chip.regs + \
+ ZEVIO_GPIO_SECTION_OFFSET(gpio) + ZEVIO_GPIO_##reg##_OFFSET)
+
+struct zevio_gpio {
+ spinlock_t lock;
+ struct of_mm_gpio_chip chip;
+};
+
+/* Functions for struct gpio_chip */
+static int zevio_gpio_get(struct gpio_chip *chip, unsigned pin)
+{
+ struct zevio_gpio *controller = to_zevio_gpio(chip);
+
+ /* Only reading allowed, so no spinlock needed */
+ uint16_t val = readw(ZEVIO_GPIO(controller, pin, INPUT));
+
+ return (val >>
[PATCH V3] gpio: New driver for LSI ZEVIO SoCs
This driver supports the GPIO controller found in LSI ZEVIO SoCs.
It has been successfully tested on a TI nspire CX calculator.
---
.../devicetree/bindings/gpio/gpio-zevio.txt| 18 ++
drivers/gpio/Kconfig | 7 +
drivers/gpio/Makefile | 1 +
drivers/gpio/gpio-zevio.c | 212 +
4 files changed, 238 insertions(+)
create mode 100644 Documentation/devicetree/bindings/gpio/gpio-zevio.txt
create mode 100644 drivers/gpio/gpio-zevio.c
diff --git a/Documentation/devicetree/bindings/gpio/gpio-zevio.txt
b/Documentation/devicetree/bindings/gpio/gpio-zevio.txt
new file mode 100644
index 000..892f953
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio-zevio.txt
@@ -0,0 +1,18 @@
+Zevio GPIO controller
+
+Required properties:
+- compatible = lsi,zevio-gpio
+- reg = BASEADDR SIZE
+- #gpio-cells = 2
+- gpio-controller;
+
+Optional:
+- #ngpios = 32: Number of GPIOs. Defaults to 32 if absent
+
+Example:
+ gpio: gpio@9000 {
+ compatible = lsi,zevio-gpio;
+ reg = 0x9000 0x1000;
+ gpio-controller;
+ #gpio-cells = 2;
+ };
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index b2450ba..ba8c357 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -138,6 +138,13 @@ config GPIO_EP93XX
depends on ARCH_EP93XX
select GPIO_GENERIC
+config GPIO_ZEVIO
+ bool LSI ZEVIO SoC memory mapped GPIOs
+ depends on ARCH_NSPIRE
+ select GENERIC_IRQ_CHIP
+ help
+ Say yes here to support the GPIO controller in LSI ZEVIO SoCs.
+
config GPIO_MM_LANTIQ
bool Lantiq Memory mapped GPIOs
depends on LANTIQ SOC_XWAY
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index ef3e983..b70cb1b 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -87,3 +87,4 @@ obj-$(CONFIG_GPIO_WM831X) += gpio-wm831x.o
obj-$(CONFIG_GPIO_WM8350) += gpio-wm8350.o
obj-$(CONFIG_GPIO_WM8994) += gpio-wm8994.o
obj-$(CONFIG_GPIO_XILINX) += gpio-xilinx.o
+obj-$(CONFIG_GPIO_ZEVIO) += gpio-zevio.o
diff --git a/drivers/gpio/gpio-zevio.c b/drivers/gpio/gpio-zevio.c
new file mode 100644
index 000..e4d5fd7
--- /dev/null
+++ b/drivers/gpio/gpio-zevio.c
@@ -0,0 +1,212 @@
+/*
+ * GPIO controller in LSI ZEVIO SoCs.
+ *
+ * Author: Fabian Vogt fab...@ritter-vogt.de
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/spinlock.h
+#include linux/errno.h
+#include linux/module.h
+#include linux/io.h
+#include linux/of_device.h
+#include linux/of_gpio.h
+#include linux/slab.h
+#include linux/gpio.h
+
+/*
+ * Memory layout:
+ * This chip has four gpio sections, each controls 8 GPIOs.
+ * Bit 0 in section 0 is GPIO 0, bit 2 in section 1 is GPIO 10.
+ * Disclaimer: Reverse engineered!
+ * For more information refer to:
+ *
http://hackspire.unsads.com/wiki/index.php/Memory-mapped_I/O_ports#9000_-_General_Purpose_I.2FO_.28GPIO.29
+ *
+ * 0x00-0x3F: Section 0
+ * +0x00: Masked interrupt status (read-only)
+ * +0x04: R: Interrupt status W: Reset interrupt status
+ * +0x08: R: Interrupt mask W: Mask interrupt
+ * +0x0C: W: Unmask interrupt (write-only)
+ * +0x10: Direction: I/O=1/0
+ * +0x14: Output
+ * +0x18: Input (read-only)
+ * +0x20: R: Sticky interrupts W: Set sticky interrupt
+ * 0x40-0x7F: Section 1
+ * 0x80-0xBF: Section 2
+ * 0xC0-0xFF: Section 3
+ */
+
+#define ZEVIO_GPIO_SECTION_SIZE0x40
+
+#define ZEVIO_GPIO_INT_MASKED_STATUS_OFFSET0x00
+#define ZEVIO_GPIO_INT_STATUS_OFFSET 0x04
+#define ZEVIO_GPIO_INT_UNMASK_OFFSET 0x08
+#define ZEVIO_GPIO_INT_MASK_OFFSET 0x0C
+#define ZEVIO_GPIO_DIRECTION_OFFSET0x10
+#define ZEVIO_GPIO_OUTPUT_OFFSET 0x14
+#define ZEVIO_GPIO_INPUT_OFFSET0x18
+#define ZEVIO_GPIO_INT_STICKY_OFFSET 0x20
+
+#define to_zevio_gpio(chip) container_of(to_of_mm_gpio_chip(chip), \
+ struct zevio_gpio, chip)
+
+/* Bit of GPIO in section */
+#define ZEVIO_GPIO_BIT(gpio) (gpio7)
+/* Offset to section of GPIO relative to base */
+#define ZEVIO_GPIO_SECTION_OFFSET(gpio) (((gpio3)3)*ZEVIO_GPIO_SECTION_SIZE)
+/* Address of register, which is responsible for given GPIO */
+#define ZEVIO_GPIO(cntrlr, gpio, reg) IOMEM(cntrlr-chip.regs + \
+ ZEVIO_GPIO_SECTION_OFFSET(gpio) + ZEVIO_GPIO_##reg##_OFFSET)
+
+struct zevio_gpio {
+ spinlock_t lock;
+ struct of_mm_gpio_chip chip;
+};
+
+/* Functions for struct gpio_chip */
+static int zevio_gpio_get(struct gpio_chip *chip, unsigned pin)
+{
+ struct zevio_gpio *controller = to_zevio_gpio(chip);
+
+ /* Only reading
