subject:"\[PATCH v1\] arm\: dts\: mt7623\: add PCIe related nodes"

Re: [PATCH v1] arm: dts: mt7623: add PCIe related nodes

2018-03-18 Thread Matthias Brugger



On 02/14/2018 04:27 AM, Ryder Lee wrote:
> This patch adds some device nodes for the PCIe function block and updates
> related pinmux.
> 
> Moreover, we add interrupt-map properties in both parent and children as
> the chip only has one IRQ per slot that is connected to all INTx and get
> propagated through the bridges and it also represents the root ports own
> interrupts.
> 
> Signed-off-by: Ryder Lee 
> Cc: Benjamin Herrenschmidt 
> Cc: Arnd Bergmann 

Applied now to v4.16-next/dts32

Thanks!

> ---
> 
> Sorry to send v1 in such a rush. Somehow I forgot to add something in 
> previous version.
> 
> changes since v1:
>  - enable device nodes - pcie0_phy & pcie2_phy
>  - fix dtc warning: Warning (pci_bridge): Node /pcie-controller@1a14 node 
> name is not "pci" or "pcie"
> ---
>  arch/arm/boot/dts/mt7623.dtsi | 105 
> ++
>  arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts |  30 
>  2 files changed, 135 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
> index 629c92b..137ce99 100644
> --- a/arch/arm/boot/dts/mt7623.dtsi
> +++ b/arch/arm/boot/dts/mt7623.dtsi
> @@ -667,6 +667,111 @@
>   #reset-cells = <1>;
>   };
>  
> + pcie: pcie@1a14 {
> + compatible = "mediatek,mt7623-pcie";
> + device_type = "pci";
> + reg = <0 0x1a14 0 0x1000>, /* PCIe shared registers */
> +   <0 0x1a142000 0 0x1000>, /* Port0 registers */
> +   <0 0x1a143000 0 0x1000>, /* Port1 registers */
> +   <0 0x1a144000 0 0x1000>; /* Port2 registers */
> + reg-names = "subsys", "port0", "port1", "port2";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0xf800 0 0 0>;
> + interrupt-map = <0x 0 0 0  GIC_SPI 193 
> IRQ_TYPE_LEVEL_LOW>,
> + <0x0800 0 0 0  GIC_SPI 194 
> IRQ_TYPE_LEVEL_LOW>,
> + <0x1000 0 0 0  GIC_SPI 195 
> IRQ_TYPE_LEVEL_LOW>;
> + clocks = < CLK_TOP_ETHIF_SEL>,
> +  < CLK_HIFSYS_PCIE0>,
> +  < CLK_HIFSYS_PCIE1>,
> +  < CLK_HIFSYS_PCIE2>;
> + clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
> + resets = < MT2701_HIFSYS_PCIE0_RST>,
> +  < MT2701_HIFSYS_PCIE1_RST>,
> +  < MT2701_HIFSYS_PCIE2_RST>;
> + reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
> + phys = <_port PHY_TYPE_PCIE>,
> +<_port PHY_TYPE_PCIE>,
> +< PHY_TYPE_PCIE>;
> + phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
> + power-domains = < MT2701_POWER_DOMAIN_HIF>;
> + bus-range = <0x00 0xff>;
> + status = "disabled";
> + ranges = <0x8100 0 0x1a16 0 0x1a16 0 0x0001
> +   0x8300 0 0x6000 0 0x6000 0 0x1000>;
> +
> + pcie@0,0 {
> + reg = <0x 0 0 0 0>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0>;
> + interrupt-map = <0 0 0 0  GIC_SPI 193 
> IRQ_TYPE_LEVEL_LOW>;
> + ranges;
> + num-lanes = <1>;
> + status = "disabled";
> + };
> +
> + pcie@1,0 {
> + reg = <0x0800 0 0 0 0>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0>;
> + interrupt-map = <0 0 0 0  GIC_SPI 194 
> IRQ_TYPE_LEVEL_LOW>;
> + ranges;
> + num-lanes = <1>;
> + status = "disabled";
> + };
> +
> + pcie@2,0 {
> + reg = <0x1000 0 0 0 0>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0>;
> + interrupt-map = <0 0 0 0  GIC_SPI 195 
> IRQ_TYPE_LEVEL_LOW>;
> + ranges;
> + num-lanes = <1>;
> + status = "disabled";
> + };
> + };
> +
> + pcie0_phy: pcie-phy@1a149000 {
> + compatible = "mediatek,generic-tphy-v1";
> + reg = <0 0x1a149000 0 0x0700>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + status = "disabled";
> +
> + pcie0_port: pcie-phy@1a149900

Re: [PATCH v1] arm: dts: mt7623: add PCIe related nodes

2018-03-18 Thread Matthias Brugger



On 02/14/2018 04:27 AM, Ryder Lee wrote:
> This patch adds some device nodes for the PCIe function block and updates
> related pinmux.
> 
> Moreover, we add interrupt-map properties in both parent and children as
> the chip only has one IRQ per slot that is connected to all INTx and get
> propagated through the bridges and it also represents the root ports own
> interrupts.
> 
> Signed-off-by: Ryder Lee 
> Cc: Benjamin Herrenschmidt 
> Cc: Arnd Bergmann 

Applied now to v4.16-next/dts32

Thanks!

> ---
> 
> Sorry to send v1 in such a rush. Somehow I forgot to add something in 
> previous version.
> 
> changes since v1:
>  - enable device nodes - pcie0_phy & pcie2_phy
>  - fix dtc warning: Warning (pci_bridge): Node /pcie-controller@1a14 node 
> name is not "pci" or "pcie"
> ---
>  arch/arm/boot/dts/mt7623.dtsi | 105 
> ++
>  arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts |  30 
>  2 files changed, 135 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
> index 629c92b..137ce99 100644
> --- a/arch/arm/boot/dts/mt7623.dtsi
> +++ b/arch/arm/boot/dts/mt7623.dtsi
> @@ -667,6 +667,111 @@
>   #reset-cells = <1>;
>   };
>  
> + pcie: pcie@1a14 {
> + compatible = "mediatek,mt7623-pcie";
> + device_type = "pci";
> + reg = <0 0x1a14 0 0x1000>, /* PCIe shared registers */
> +   <0 0x1a142000 0 0x1000>, /* Port0 registers */
> +   <0 0x1a143000 0 0x1000>, /* Port1 registers */
> +   <0 0x1a144000 0 0x1000>; /* Port2 registers */
> + reg-names = "subsys", "port0", "port1", "port2";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0xf800 0 0 0>;
> + interrupt-map = <0x 0 0 0  GIC_SPI 193 
> IRQ_TYPE_LEVEL_LOW>,
> + <0x0800 0 0 0  GIC_SPI 194 
> IRQ_TYPE_LEVEL_LOW>,
> + <0x1000 0 0 0  GIC_SPI 195 
> IRQ_TYPE_LEVEL_LOW>;
> + clocks = < CLK_TOP_ETHIF_SEL>,
> +  < CLK_HIFSYS_PCIE0>,
> +  < CLK_HIFSYS_PCIE1>,
> +  < CLK_HIFSYS_PCIE2>;
> + clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
> + resets = < MT2701_HIFSYS_PCIE0_RST>,
> +  < MT2701_HIFSYS_PCIE1_RST>,
> +  < MT2701_HIFSYS_PCIE2_RST>;
> + reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
> + phys = <_port PHY_TYPE_PCIE>,
> +<_port PHY_TYPE_PCIE>,
> +< PHY_TYPE_PCIE>;
> + phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
> + power-domains = < MT2701_POWER_DOMAIN_HIF>;
> + bus-range = <0x00 0xff>;
> + status = "disabled";
> + ranges = <0x8100 0 0x1a16 0 0x1a16 0 0x0001
> +   0x8300 0 0x6000 0 0x6000 0 0x1000>;
> +
> + pcie@0,0 {
> + reg = <0x 0 0 0 0>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0>;
> + interrupt-map = <0 0 0 0  GIC_SPI 193 
> IRQ_TYPE_LEVEL_LOW>;
> + ranges;
> + num-lanes = <1>;
> + status = "disabled";
> + };
> +
> + pcie@1,0 {
> + reg = <0x0800 0 0 0 0>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0>;
> + interrupt-map = <0 0 0 0  GIC_SPI 194 
> IRQ_TYPE_LEVEL_LOW>;
> + ranges;
> + num-lanes = <1>;
> + status = "disabled";
> + };
> +
> + pcie@2,0 {
> + reg = <0x1000 0 0 0 0>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0>;
> + interrupt-map = <0 0 0 0  GIC_SPI 195 
> IRQ_TYPE_LEVEL_LOW>;
> + ranges;
> + num-lanes = <1>;
> + status = "disabled";
> + };
> + };
> +
> + pcie0_phy: pcie-phy@1a149000 {
> + compatible = "mediatek,generic-tphy-v1";
> + reg = <0 0x1a149000 0 0x0700>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + status = "disabled";
> +
> + pcie0_port: pcie-phy@1a149900 {
> + reg = <0 0x1a149900 0 0x0700>;
> +

Re: [PATCH v1] arm: dts: mt7623: add PCIe related nodes

2018-03-13 Thread Ryder Lee

Hi Matthias,

Just a gentle ping on this patch.

Thanks

On Wed, 2018-02-14 at 11:27 +0800, Ryder Lee (李庚諺) wrote:
> This patch adds some device nodes for the PCIe function block and updates
> related pinmux.
> 
> Moreover, we add interrupt-map properties in both parent and children as
> the chip only has one IRQ per slot that is connected to all INTx and get
> propagated through the bridges and it also represents the root ports own
> interrupts.
> 
> Signed-off-by: Ryder Lee 
> Cc: Benjamin Herrenschmidt 
> Cc: Arnd Bergmann 
> ---
> 
> Sorry to send v1 in such a rush. Somehow I forgot to add something in 
> previous version.
> 
> changes since v1:
>  - enable device nodes - pcie0_phy & pcie2_phy
>  - fix dtc warning: Warning (pci_bridge): Node /pcie-controller@1a14 node 
> name is not "pci" or "pcie"
> ---
>  arch/arm/boot/dts/mt7623.dtsi | 105 
> ++
>  arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts |  30 
>  2 files changed, 135 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
> index 629c92b..137ce99 100644
> --- a/arch/arm/boot/dts/mt7623.dtsi
> +++ b/arch/arm/boot/dts/mt7623.dtsi
> @@ -667,6 +667,111 @@
> #reset-cells = <1>;
> };
> 
> +   pcie: pcie@1a14 {
> +   compatible = "mediatek,mt7623-pcie";
> +   device_type = "pci";
> +   reg = <0 0x1a14 0 0x1000>, /* PCIe shared registers */
> + <0 0x1a142000 0 0x1000>, /* Port0 registers */
> + <0 0x1a143000 0 0x1000>, /* Port1 registers */
> + <0 0x1a144000 0 0x1000>; /* Port2 registers */
> +   reg-names = "subsys", "port0", "port1", "port2";
> +   #address-cells = <3>;
> +   #size-cells = <2>;
> +   #interrupt-cells = <1>;
> +   interrupt-map-mask = <0xf800 0 0 0>;
> +   interrupt-map = <0x 0 0 0  GIC_SPI 193 
> IRQ_TYPE_LEVEL_LOW>,
> +   <0x0800 0 0 0  GIC_SPI 194 
> IRQ_TYPE_LEVEL_LOW>,
> +   <0x1000 0 0 0  GIC_SPI 195 
> IRQ_TYPE_LEVEL_LOW>;
> +   clocks = < CLK_TOP_ETHIF_SEL>,
> +< CLK_HIFSYS_PCIE0>,
> +< CLK_HIFSYS_PCIE1>,
> +< CLK_HIFSYS_PCIE2>;
> +   clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
> +   resets = < MT2701_HIFSYS_PCIE0_RST>,
> +< MT2701_HIFSYS_PCIE1_RST>,
> +< MT2701_HIFSYS_PCIE2_RST>;
> +   reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
> +   phys = <_port PHY_TYPE_PCIE>,
> +  <_port PHY_TYPE_PCIE>,
> +  < PHY_TYPE_PCIE>;
> +   phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
> +   power-domains = < MT2701_POWER_DOMAIN_HIF>;
> +   bus-range = <0x00 0xff>;
> +   status = "disabled";
> +   ranges = <0x8100 0 0x1a16 0 0x1a16 0 0x0001
> + 0x8300 0 0x6000 0 0x6000 0 0x1000>;
> +
> +   pcie@0,0 {
> +   reg = <0x 0 0 0 0>;
> +   #address-cells = <3>;
> +   #size-cells = <2>;
> +   #interrupt-cells = <1>;
> +   interrupt-map-mask = <0 0 0 0>;
> +   interrupt-map = <0 0 0 0  GIC_SPI 193 
> IRQ_TYPE_LEVEL_LOW>;
> +   ranges;
> +   num-lanes = <1>;
> +   status = "disabled";
> +   };
> +
> +   pcie@1,0 {
> +   reg = <0x0800 0 0 0 0>;
> +   #address-cells = <3>;
> +   #size-cells = <2>;
> +   #interrupt-cells = <1>;
> +   interrupt-map-mask = <0 0 0 0>;
> +   interrupt-map = <0 0 0 0  GIC_SPI 194 
> IRQ_TYPE_LEVEL_LOW>;
> +   ranges;
> +   num-lanes = <1>;
> +   status = "disabled";
> +   };
> +
> +   pcie@2,0 {
> +   reg = <0x1000 0 0 0 0>;
> +   #address-cells = <3>;
> +   #size-cells = <2>;
> +   #interrupt-cells = <1>;
> +   interrupt-map-mask = <0 0 0 0>;
> +   interrupt-map = <0 0 0 0  GIC_SPI 195 
> IRQ_TYPE_LEVEL_LOW>;
> +   ranges;
> +   num-lanes = <1>;
> +   status = "disabled";
> +   };
> +   };
> +
> +   pcie0_phy: pcie-phy@1a149000 {
> +   compatible = "mediatek,generic-tphy-v1";
> +   reg = <0 0x1a149000 0 0x0700>;
> +

Re: [PATCH v1] arm: dts: mt7623: add PCIe related nodes

2018-03-13 Thread Ryder Lee

Hi Matthias,

Just a gentle ping on this patch.

Thanks

On Wed, 2018-02-14 at 11:27 +0800, Ryder Lee (李庚諺) wrote:
> This patch adds some device nodes for the PCIe function block and updates
> related pinmux.
> 
> Moreover, we add interrupt-map properties in both parent and children as
> the chip only has one IRQ per slot that is connected to all INTx and get
> propagated through the bridges and it also represents the root ports own
> interrupts.
> 
> Signed-off-by: Ryder Lee 
> Cc: Benjamin Herrenschmidt 
> Cc: Arnd Bergmann 
> ---
> 
> Sorry to send v1 in such a rush. Somehow I forgot to add something in 
> previous version.
> 
> changes since v1:
>  - enable device nodes - pcie0_phy & pcie2_phy
>  - fix dtc warning: Warning (pci_bridge): Node /pcie-controller@1a14 node 
> name is not "pci" or "pcie"
> ---
>  arch/arm/boot/dts/mt7623.dtsi | 105 
> ++
>  arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts |  30 
>  2 files changed, 135 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
> index 629c92b..137ce99 100644
> --- a/arch/arm/boot/dts/mt7623.dtsi
> +++ b/arch/arm/boot/dts/mt7623.dtsi
> @@ -667,6 +667,111 @@
> #reset-cells = <1>;
> };
> 
> +   pcie: pcie@1a14 {
> +   compatible = "mediatek,mt7623-pcie";
> +   device_type = "pci";
> +   reg = <0 0x1a14 0 0x1000>, /* PCIe shared registers */
> + <0 0x1a142000 0 0x1000>, /* Port0 registers */
> + <0 0x1a143000 0 0x1000>, /* Port1 registers */
> + <0 0x1a144000 0 0x1000>; /* Port2 registers */
> +   reg-names = "subsys", "port0", "port1", "port2";
> +   #address-cells = <3>;
> +   #size-cells = <2>;
> +   #interrupt-cells = <1>;
> +   interrupt-map-mask = <0xf800 0 0 0>;
> +   interrupt-map = <0x 0 0 0  GIC_SPI 193 
> IRQ_TYPE_LEVEL_LOW>,
> +   <0x0800 0 0 0  GIC_SPI 194 
> IRQ_TYPE_LEVEL_LOW>,
> +   <0x1000 0 0 0  GIC_SPI 195 
> IRQ_TYPE_LEVEL_LOW>;
> +   clocks = < CLK_TOP_ETHIF_SEL>,
> +< CLK_HIFSYS_PCIE0>,
> +< CLK_HIFSYS_PCIE1>,
> +< CLK_HIFSYS_PCIE2>;
> +   clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
> +   resets = < MT2701_HIFSYS_PCIE0_RST>,
> +< MT2701_HIFSYS_PCIE1_RST>,
> +< MT2701_HIFSYS_PCIE2_RST>;
> +   reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
> +   phys = <_port PHY_TYPE_PCIE>,
> +  <_port PHY_TYPE_PCIE>,
> +  < PHY_TYPE_PCIE>;
> +   phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
> +   power-domains = < MT2701_POWER_DOMAIN_HIF>;
> +   bus-range = <0x00 0xff>;
> +   status = "disabled";
> +   ranges = <0x8100 0 0x1a16 0 0x1a16 0 0x0001
> + 0x8300 0 0x6000 0 0x6000 0 0x1000>;
> +
> +   pcie@0,0 {
> +   reg = <0x 0 0 0 0>;
> +   #address-cells = <3>;
> +   #size-cells = <2>;
> +   #interrupt-cells = <1>;
> +   interrupt-map-mask = <0 0 0 0>;
> +   interrupt-map = <0 0 0 0  GIC_SPI 193 
> IRQ_TYPE_LEVEL_LOW>;
> +   ranges;
> +   num-lanes = <1>;
> +   status = "disabled";
> +   };
> +
> +   pcie@1,0 {
> +   reg = <0x0800 0 0 0 0>;
> +   #address-cells = <3>;
> +   #size-cells = <2>;
> +   #interrupt-cells = <1>;
> +   interrupt-map-mask = <0 0 0 0>;
> +   interrupt-map = <0 0 0 0  GIC_SPI 194 
> IRQ_TYPE_LEVEL_LOW>;
> +   ranges;
> +   num-lanes = <1>;
> +   status = "disabled";
> +   };
> +
> +   pcie@2,0 {
> +   reg = <0x1000 0 0 0 0>;
> +   #address-cells = <3>;
> +   #size-cells = <2>;
> +   #interrupt-cells = <1>;
> +   interrupt-map-mask = <0 0 0 0>;
> +   interrupt-map = <0 0 0 0  GIC_SPI 195 
> IRQ_TYPE_LEVEL_LOW>;
> +   ranges;
> +   num-lanes = <1>;
> +   status = "disabled";
> +   };
> +   };
> +
> +   pcie0_phy: pcie-phy@1a149000 {
> +   compatible = "mediatek,generic-tphy-v1";
> +   reg = <0 0x1a149000 0 0x0700>;
> +   #address-cells = <2>;
> +   #size-cells = <2>;

[PATCH v1] arm: dts: mt7623: add PCIe related nodes

2018-02-13 Thread Ryder Lee

This patch adds some device nodes for the PCIe function block and updates
related pinmux.

Moreover, we add interrupt-map properties in both parent and children as
the chip only has one IRQ per slot that is connected to all INTx and get
propagated through the bridges and it also represents the root ports own
interrupts.

Signed-off-by: Ryder Lee 
Cc: Benjamin Herrenschmidt 
Cc: Arnd Bergmann 
---

Sorry to send v1 in such a rush. Somehow I forgot to add something in previous 
version.

changes since v1:
 - enable device nodes - pcie0_phy & pcie2_phy
 - fix dtc warning: Warning (pci_bridge): Node /pcie-controller@1a14 node 
name is not "pci" or "pcie"
---
 arch/arm/boot/dts/mt7623.dtsi | 105 ++
 arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts |  30 
 2 files changed, 135 insertions(+)

diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
index 629c92b..137ce99 100644
--- a/arch/arm/boot/dts/mt7623.dtsi
+++ b/arch/arm/boot/dts/mt7623.dtsi
@@ -667,6 +667,111 @@
#reset-cells = <1>;
};
 
+   pcie: pcie@1a14 {
+   compatible = "mediatek,mt7623-pcie";
+   device_type = "pci";
+   reg = <0 0x1a14 0 0x1000>, /* PCIe shared registers */
+ <0 0x1a142000 0 0x1000>, /* Port0 registers */
+ <0 0x1a143000 0 0x1000>, /* Port1 registers */
+ <0 0x1a144000 0 0x1000>; /* Port2 registers */
+   reg-names = "subsys", "port0", "port1", "port2";
+   #address-cells = <3>;
+   #size-cells = <2>;
+   #interrupt-cells = <1>;
+   interrupt-map-mask = <0xf800 0 0 0>;
+   interrupt-map = <0x 0 0 0  GIC_SPI 193 
IRQ_TYPE_LEVEL_LOW>,
+   <0x0800 0 0 0  GIC_SPI 194 
IRQ_TYPE_LEVEL_LOW>,
+   <0x1000 0 0 0  GIC_SPI 195 
IRQ_TYPE_LEVEL_LOW>;
+   clocks = < CLK_TOP_ETHIF_SEL>,
+< CLK_HIFSYS_PCIE0>,
+< CLK_HIFSYS_PCIE1>,
+< CLK_HIFSYS_PCIE2>;
+   clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
+   resets = < MT2701_HIFSYS_PCIE0_RST>,
+< MT2701_HIFSYS_PCIE1_RST>,
+< MT2701_HIFSYS_PCIE2_RST>;
+   reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
+   phys = <_port PHY_TYPE_PCIE>,
+  <_port PHY_TYPE_PCIE>,
+  < PHY_TYPE_PCIE>;
+   phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
+   power-domains = < MT2701_POWER_DOMAIN_HIF>;
+   bus-range = <0x00 0xff>;
+   status = "disabled";
+   ranges = <0x8100 0 0x1a16 0 0x1a16 0 0x0001
+ 0x8300 0 0x6000 0 0x6000 0 0x1000>;
+
+   pcie@0,0 {
+   reg = <0x 0 0 0 0>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   #interrupt-cells = <1>;
+   interrupt-map-mask = <0 0 0 0>;
+   interrupt-map = <0 0 0 0  GIC_SPI 193 
IRQ_TYPE_LEVEL_LOW>;
+   ranges;
+   num-lanes = <1>;
+   status = "disabled";
+   };
+
+   pcie@1,0 {
+   reg = <0x0800 0 0 0 0>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   #interrupt-cells = <1>;
+   interrupt-map-mask = <0 0 0 0>;
+   interrupt-map = <0 0 0 0  GIC_SPI 194 
IRQ_TYPE_LEVEL_LOW>;
+   ranges;
+   num-lanes = <1>;
+   status = "disabled";
+   };
+
+   pcie@2,0 {
+   reg = <0x1000 0 0 0 0>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   #interrupt-cells = <1>;
+   interrupt-map-mask = <0 0 0 0>;
+   interrupt-map = <0 0 0 0  GIC_SPI 195 
IRQ_TYPE_LEVEL_LOW>;
+   ranges;
+   num-lanes = <1>;
+   status = "disabled";
+   };
+   };
+
+   pcie0_phy: pcie-phy@1a149000 {
+   compatible = "mediatek,generic-tphy-v1";
+   reg = <0 0x1a149000 0 0x0700>;
+   #address-cells = <2>;
+   #size-cells = <2>;
+   ranges;
+   status = "disabled";
+
+   pcie0_port: pcie-phy@1a149900 {
+   reg = <0 0x1a149900 0 0x0700>;
+   clocks = <>;
+   clock-names = "ref";
+   #phy-cells

[PATCH v1] arm: dts: mt7623: add PCIe related nodes

2018-02-13 Thread Ryder Lee

This patch adds some device nodes for the PCIe function block and updates
related pinmux.

Moreover, we add interrupt-map properties in both parent and children as
the chip only has one IRQ per slot that is connected to all INTx and get
propagated through the bridges and it also represents the root ports own
interrupts.

Signed-off-by: Ryder Lee 
Cc: Benjamin Herrenschmidt 
Cc: Arnd Bergmann 
---

Sorry to send v1 in such a rush. Somehow I forgot to add something in previous 
version.

changes since v1:
 - enable device nodes - pcie0_phy & pcie2_phy
 - fix dtc warning: Warning (pci_bridge): Node /pcie-controller@1a14 node 
name is not "pci" or "pcie"
---
 arch/arm/boot/dts/mt7623.dtsi | 105 ++
 arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts |  30 
 2 files changed, 135 insertions(+)

diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
index 629c92b..137ce99 100644
--- a/arch/arm/boot/dts/mt7623.dtsi
+++ b/arch/arm/boot/dts/mt7623.dtsi
@@ -667,6 +667,111 @@
#reset-cells = <1>;
};
 
+   pcie: pcie@1a14 {
+   compatible = "mediatek,mt7623-pcie";
+   device_type = "pci";
+   reg = <0 0x1a14 0 0x1000>, /* PCIe shared registers */
+ <0 0x1a142000 0 0x1000>, /* Port0 registers */
+ <0 0x1a143000 0 0x1000>, /* Port1 registers */
+ <0 0x1a144000 0 0x1000>; /* Port2 registers */
+   reg-names = "subsys", "port0", "port1", "port2";
+   #address-cells = <3>;
+   #size-cells = <2>;
+   #interrupt-cells = <1>;
+   interrupt-map-mask = <0xf800 0 0 0>;
+   interrupt-map = <0x 0 0 0  GIC_SPI 193 
IRQ_TYPE_LEVEL_LOW>,
+   <0x0800 0 0 0  GIC_SPI 194 
IRQ_TYPE_LEVEL_LOW>,
+   <0x1000 0 0 0  GIC_SPI 195 
IRQ_TYPE_LEVEL_LOW>;
+   clocks = < CLK_TOP_ETHIF_SEL>,
+< CLK_HIFSYS_PCIE0>,
+< CLK_HIFSYS_PCIE1>,
+< CLK_HIFSYS_PCIE2>;
+   clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
+   resets = < MT2701_HIFSYS_PCIE0_RST>,
+< MT2701_HIFSYS_PCIE1_RST>,
+< MT2701_HIFSYS_PCIE2_RST>;
+   reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
+   phys = <_port PHY_TYPE_PCIE>,
+  <_port PHY_TYPE_PCIE>,
+  < PHY_TYPE_PCIE>;
+   phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
+   power-domains = < MT2701_POWER_DOMAIN_HIF>;
+   bus-range = <0x00 0xff>;
+   status = "disabled";
+   ranges = <0x8100 0 0x1a16 0 0x1a16 0 0x0001
+ 0x8300 0 0x6000 0 0x6000 0 0x1000>;
+
+   pcie@0,0 {
+   reg = <0x 0 0 0 0>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   #interrupt-cells = <1>;
+   interrupt-map-mask = <0 0 0 0>;
+   interrupt-map = <0 0 0 0  GIC_SPI 193 
IRQ_TYPE_LEVEL_LOW>;
+   ranges;
+   num-lanes = <1>;
+   status = "disabled";
+   };
+
+   pcie@1,0 {
+   reg = <0x0800 0 0 0 0>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   #interrupt-cells = <1>;
+   interrupt-map-mask = <0 0 0 0>;
+   interrupt-map = <0 0 0 0  GIC_SPI 194 
IRQ_TYPE_LEVEL_LOW>;
+   ranges;
+   num-lanes = <1>;
+   status = "disabled";
+   };
+
+   pcie@2,0 {
+   reg = <0x1000 0 0 0 0>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   #interrupt-cells = <1>;
+   interrupt-map-mask = <0 0 0 0>;
+   interrupt-map = <0 0 0 0  GIC_SPI 195 
IRQ_TYPE_LEVEL_LOW>;
+   ranges;
+   num-lanes = <1>;
+   status = "disabled";
+   };
+   };
+
+   pcie0_phy: pcie-phy@1a149000 {
+   compatible = "mediatek,generic-tphy-v1";
+   reg = <0 0x1a149000 0 0x0700>;
+   #address-cells = <2>;
+   #size-cells = <2>;
+   ranges;
+   status = "disabled";
+
+   pcie0_port: pcie-phy@1a149900 {
+   reg = <0 0x1a149900 0 0x0700>;
+   clocks = <>;
+   clock-names = "ref";
+   #phy-cells = <1>;
+   status = "okay";
+

Re: [PATCH v1] arm: dts: mt7623: add PCIe related nodes

Re: [PATCH v1] arm: dts: mt7623: add PCIe related nodes

Re: [PATCH v1] arm: dts: mt7623: add PCIe related nodes

Re: [PATCH v1] arm: dts: mt7623: add PCIe related nodes

[PATCH v1] arm: dts: mt7623: add PCIe related nodes

[PATCH v1] arm: dts: mt7623: add PCIe related nodes

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