Re: [PATCH v1 2/2] dt-bindings: pcie: Add documentation for Mediatek PCIe

[Ryder Lee]

On Fri, 2017-04-28 at 16:09 -0500, Rob Herring wrote:
> On Fri, Apr 28, 2017 at 05:10:34PM +0800, Ryder Lee wrote:
> > Add binding document for Mediatek PCIe Gen2 v1 host controller driver.
> > 
> > Signed-off-by: Ryder Lee 
> > ---
> >  .../bindings/pci/mediatek,gen2v1-pcie.txt  | 174 
> > +
> >  1 file changed, 174 insertions(+)
> >  create mode 100644 
> > Documentation/devicetree/bindings/pci/mediatek,gen2v1-pcie.txt
> > 
> > diff --git a/Documentation/devicetree/bindings/pci/mediatek,gen2v1-pcie.txt 
> > b/Documentation/devicetree/bindings/pci/mediatek,gen2v1-pcie.txt
> > new file mode 100644
> > index 000..545d8cf
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pci/mediatek,gen2v1-pcie.txt
> > @@ -0,0 +1,174 @@
> > +Mediatek Gen2 V1 PCIe controller
> > +
> > +PCIe subsys supports single root complex (RC) with 3 Root Ports. Each root
> > +ports supports a Gen2 1-lane Link. It includes one Host/PCI bridge and 3
> > +PCIe MAC. Each port has PIPE interface to PHY. There are 3 bus master for
> > +data access and 1 bus slave for Configuration and Status Register access.
> > +
> > +This controller is available on MT7623 series SoCs.
> > +  
> > +Required properties:
> > +- compatible: Should contain "mediatek,gen2v1-pcie".
> > +- device_type: Must be "pci"
> > +- reg: Base addresses and lengths of the PCIe controller.
> > +- #address-cells: Address representation for root ports (must be 3)
> > +  - cell 0 specifies the bus and device numbers of the root port:
> > +[23:16]: bus number
> > +[15:11]: device number
> > +  - cell 1 denotes the upper 32 address bits and should be 0
> > +  - cell 2 contains the lower 32 address bits and is used to translate to 
> > the
> > +CPU address space
> 
> This is all standard PCI bus binding. You don't need to define it here. 
> "must be 3" is sufficient.

Okay.

> > +- #size-cells: Size representation for root ports (must be 2)
> > +- #interrupt-cells: Size representation for interrupts (must be 1)
> > +- interrupts: Three interrupt outputs of the controller. Must contain an
> > +  entry for each entry in the interrupt-names property.
> 
> Where's interrupt-names?

I will add it.

> > +- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
> > +  Please refer to the standard PCI bus binding document for a more detailed
> > +  explanation.
> > +- clocks: Must contain an entry for each entry in clock-names.
> > +  See ../clocks/clock-bindings.txt for details.
> > +- clock-names: Must include the following entries:
> > +  - free_ck:for reference clock of PCIe subsys
> > +  - sys_ck0:for clock of Port0 MAC
> > +  - sys_ck1:for clock of Port1 MAC
> > +  - sys_ck2:for clock of Port2 MAC
> > +- resets: Must contain an entry for each entry in reset-names.
> > +  See ../reset/reset.txt for details.
> > +- reset-names: Must include the following entries:
> > +  - pcie-rst0  :port0 reset
> > +  - pcie-rst1  :port1 reset
> > +  - pcie-rst2  :port2 reset
> > +- phys: list of PHY specifiers (used by generic PHY framework)
> > +- phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
> > +  number of PHYs as specified in *phys* property.
> > +- power-domains: A phandle and power domain specifier pair to the power 
> > domain
> > +  which is responsible for collapsing and restoring power to the peripheral
> > +- bus-range: Range of bus numbers associated with this controller
> > +- ranges: Describes the translation of addresses for root ports and 
> > standard
> > +  PCI regions. The entries must be 6 cells each, where the first three 
> > cells
> > +  correspond to the address as described for the #address-cells property
> > +  above, the fourth cell is the physical CPU address to translate to and 
> > the
> > +  fifth and six cells are as described for the #size-cells property above.
> 
> Don't need to define what ranges is here, just what the entries should 
> be:

Okay.
> > +  - The first three entries are expected to translate the addresses for 
> > the root
> > +port registers, which are referenced by the assigned-addresses 
> > property of
> > +the root port nodes (see below).
> > +  - The remaining entries setup the mapping for the standard I/O and memory
> > +   regions.
> > +  Please refer to the standard PCI bus binding document for a more detailed
> > +  explanation.
> > +
> > +In addition, the device tree node must have sub-nodes describing each
> > +PCIe port interface, having the following mandatory properties:
> > +
> > +Required properties:
> > +- device_type: Must be "pci"
> > +- assigned-addresses: Address and size of the port configuration registers
> > +- reg: Only the first four bytes are used to refer to the correct bus 
> > number
> > +  and device number.
> > +- #address-cells: Must be 3
> > +- #size-cells: Must be 2
> > +- #interrupt-cells: Size representation for interrupts (must be 1)
> > 

Re: [PATCH v1 2/2] dt-bindings: pcie: Add documentation for Mediatek PCIe

[Ryder Lee]

On Fri, 2017-04-28 at 16:09 -0500, Rob Herring wrote:
> On Fri, Apr 28, 2017 at 05:10:34PM +0800, Ryder Lee wrote:
> > Add binding document for Mediatek PCIe Gen2 v1 host controller driver.
> > 
> > Signed-off-by: Ryder Lee 
> > ---
> >  .../bindings/pci/mediatek,gen2v1-pcie.txt  | 174 
> > +
> >  1 file changed, 174 insertions(+)
> >  create mode 100644 
> > Documentation/devicetree/bindings/pci/mediatek,gen2v1-pcie.txt
> > 
> > diff --git a/Documentation/devicetree/bindings/pci/mediatek,gen2v1-pcie.txt 
> > b/Documentation/devicetree/bindings/pci/mediatek,gen2v1-pcie.txt
> > new file mode 100644
> > index 000..545d8cf
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pci/mediatek,gen2v1-pcie.txt
> > @@ -0,0 +1,174 @@
> > +Mediatek Gen2 V1 PCIe controller
> > +
> > +PCIe subsys supports single root complex (RC) with 3 Root Ports. Each root
> > +ports supports a Gen2 1-lane Link. It includes one Host/PCI bridge and 3
> > +PCIe MAC. Each port has PIPE interface to PHY. There are 3 bus master for
> > +data access and 1 bus slave for Configuration and Status Register access.
> > +
> > +This controller is available on MT7623 series SoCs.
> > +  
> > +Required properties:
> > +- compatible: Should contain "mediatek,gen2v1-pcie".
> > +- device_type: Must be "pci"
> > +- reg: Base addresses and lengths of the PCIe controller.
> > +- #address-cells: Address representation for root ports (must be 3)
> > +  - cell 0 specifies the bus and device numbers of the root port:
> > +[23:16]: bus number
> > +[15:11]: device number
> > +  - cell 1 denotes the upper 32 address bits and should be 0
> > +  - cell 2 contains the lower 32 address bits and is used to translate to 
> > the
> > +CPU address space
> 
> This is all standard PCI bus binding. You don't need to define it here. 
> "must be 3" is sufficient.

Okay.

> > +- #size-cells: Size representation for root ports (must be 2)
> > +- #interrupt-cells: Size representation for interrupts (must be 1)
> > +- interrupts: Three interrupt outputs of the controller. Must contain an
> > +  entry for each entry in the interrupt-names property.
> 
> Where's interrupt-names?

I will add it.

> > +- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
> > +  Please refer to the standard PCI bus binding document for a more detailed
> > +  explanation.
> > +- clocks: Must contain an entry for each entry in clock-names.
> > +  See ../clocks/clock-bindings.txt for details.
> > +- clock-names: Must include the following entries:
> > +  - free_ck:for reference clock of PCIe subsys
> > +  - sys_ck0:for clock of Port0 MAC
> > +  - sys_ck1:for clock of Port1 MAC
> > +  - sys_ck2:for clock of Port2 MAC
> > +- resets: Must contain an entry for each entry in reset-names.
> > +  See ../reset/reset.txt for details.
> > +- reset-names: Must include the following entries:
> > +  - pcie-rst0  :port0 reset
> > +  - pcie-rst1  :port1 reset
> > +  - pcie-rst2  :port2 reset
> > +- phys: list of PHY specifiers (used by generic PHY framework)
> > +- phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
> > +  number of PHYs as specified in *phys* property.
> > +- power-domains: A phandle and power domain specifier pair to the power 
> > domain
> > +  which is responsible for collapsing and restoring power to the peripheral
> > +- bus-range: Range of bus numbers associated with this controller
> > +- ranges: Describes the translation of addresses for root ports and 
> > standard
> > +  PCI regions. The entries must be 6 cells each, where the first three 
> > cells
> > +  correspond to the address as described for the #address-cells property
> > +  above, the fourth cell is the physical CPU address to translate to and 
> > the
> > +  fifth and six cells are as described for the #size-cells property above.
> 
> Don't need to define what ranges is here, just what the entries should 
> be:

Okay.
> > +  - The first three entries are expected to translate the addresses for 
> > the root
> > +port registers, which are referenced by the assigned-addresses 
> > property of
> > +the root port nodes (see below).
> > +  - The remaining entries setup the mapping for the standard I/O and memory
> > +   regions.
> > +  Please refer to the standard PCI bus binding document for a more detailed
> > +  explanation.
> > +
> > +In addition, the device tree node must have sub-nodes describing each
> > +PCIe port interface, having the following mandatory properties:
> > +
> > +Required properties:
> > +- device_type: Must be "pci"
> > +- assigned-addresses: Address and size of the port configuration registers
> > +- reg: Only the first four bytes are used to refer to the correct bus 
> > number
> > +  and device number.
> > +- #address-cells: Must be 3
> > +- #size-cells: Must be 2
> > +- #interrupt-cells: Size representation for interrupts (must be 1)
> > +- interrupt-map-mask 

Re: [PATCH v1 2/2] dt-bindings: pcie: Add documentation for Mediatek PCIe

[Rob Herring]

On Fri, Apr 28, 2017 at 05:10:34PM +0800, Ryder Lee wrote:
> Add binding document for Mediatek PCIe Gen2 v1 host controller driver.
> 
> Signed-off-by: Ryder Lee 
> ---
>  .../bindings/pci/mediatek,gen2v1-pcie.txt  | 174 
> +
>  1 file changed, 174 insertions(+)
>  create mode 100644 
> Documentation/devicetree/bindings/pci/mediatek,gen2v1-pcie.txt
> 
> diff --git a/Documentation/devicetree/bindings/pci/mediatek,gen2v1-pcie.txt 
> b/Documentation/devicetree/bindings/pci/mediatek,gen2v1-pcie.txt
> new file mode 100644
> index 000..545d8cf
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/mediatek,gen2v1-pcie.txt
> @@ -0,0 +1,174 @@
> +Mediatek Gen2 V1 PCIe controller
> +
> +PCIe subsys supports single root complex (RC) with 3 Root Ports. Each root
> +ports supports a Gen2 1-lane Link. It includes one Host/PCI bridge and 3
> +PCIe MAC. Each port has PIPE interface to PHY. There are 3 bus master for
> +data access and 1 bus slave for Configuration and Status Register access.
> +
> +This controller is available on MT7623 series SoCs.
> +  
> +Required properties:
> +- compatible: Should contain "mediatek,gen2v1-pcie".
> +- device_type: Must be "pci"
> +- reg: Base addresses and lengths of the PCIe controller.
> +- #address-cells: Address representation for root ports (must be 3)
> +  - cell 0 specifies the bus and device numbers of the root port:
> +[23:16]: bus number
> +[15:11]: device number
> +  - cell 1 denotes the upper 32 address bits and should be 0
> +  - cell 2 contains the lower 32 address bits and is used to translate to the
> +CPU address space

This is all standard PCI bus binding. You don't need to define it here. 
"must be 3" is sufficient.

> +- #size-cells: Size representation for root ports (must be 2)
> +- #interrupt-cells: Size representation for interrupts (must be 1)
> +- interrupts: Three interrupt outputs of the controller. Must contain an
> +  entry for each entry in the interrupt-names property.

Where's interrupt-names?

> +- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
> +  Please refer to the standard PCI bus binding document for a more detailed
> +  explanation.
> +- clocks: Must contain an entry for each entry in clock-names.
> +  See ../clocks/clock-bindings.txt for details.
> +- clock-names: Must include the following entries:
> +  - free_ck  :for reference clock of PCIe subsys
> +  - sys_ck0  :for clock of Port0 MAC
> +  - sys_ck1  :for clock of Port1 MAC
> +  - sys_ck2  :for clock of Port2 MAC
> +- resets: Must contain an entry for each entry in reset-names.
> +  See ../reset/reset.txt for details.
> +- reset-names: Must include the following entries:
> +  - pcie-rst0:port0 reset
> +  - pcie-rst1:port1 reset
> +  - pcie-rst2:port2 reset
> +- phys: list of PHY specifiers (used by generic PHY framework)
> +- phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
> +  number of PHYs as specified in *phys* property.
> +- power-domains: A phandle and power domain specifier pair to the power 
> domain
> +  which is responsible for collapsing and restoring power to the peripheral
> +- bus-range: Range of bus numbers associated with this controller
> +- ranges: Describes the translation of addresses for root ports and standard
> +  PCI regions. The entries must be 6 cells each, where the first three cells
> +  correspond to the address as described for the #address-cells property
> +  above, the fourth cell is the physical CPU address to translate to and the
> +  fifth and six cells are as described for the #size-cells property above.

Don't need to define what ranges is here, just what the entries should 
be:

> +  - The first three entries are expected to translate the addresses for the 
> root
> +port registers, which are referenced by the assigned-addresses property 
> of
> +the root port nodes (see below).
> +  - The remaining entries setup the mapping for the standard I/O and memory
> + regions.
> +  Please refer to the standard PCI bus binding document for a more detailed
> +  explanation.
> +
> +In addition, the device tree node must have sub-nodes describing each
> +PCIe port interface, having the following mandatory properties:
> +
> +Required properties:
> +- device_type: Must be "pci"
> +- assigned-addresses: Address and size of the port configuration registers
> +- reg: Only the first four bytes are used to refer to the correct bus number
> +  and device number.
> +- #address-cells: Must be 3
> +- #size-cells: Must be 2
> +- #interrupt-cells: Size representation for interrupts (must be 1)
> +- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
> +  Please refer to the standard PCI bus binding document for a more detailed
> +  explanation.
> +- ranges: Sub-ranges distributed from the PCIe controller node. An empty
> +  property is sufficient.
> +- num-lanes: Number of lanes to use for 

Re: [PATCH v1 2/2] dt-bindings: pcie: Add documentation for Mediatek PCIe

[Rob Herring]

On Fri, Apr 28, 2017 at 05:10:34PM +0800, Ryder Lee wrote:
> Add binding document for Mediatek PCIe Gen2 v1 host controller driver.
> 
> Signed-off-by: Ryder Lee 
> ---
>  .../bindings/pci/mediatek,gen2v1-pcie.txt  | 174 
> +
>  1 file changed, 174 insertions(+)
>  create mode 100644 
> Documentation/devicetree/bindings/pci/mediatek,gen2v1-pcie.txt
> 
> diff --git a/Documentation/devicetree/bindings/pci/mediatek,gen2v1-pcie.txt 
> b/Documentation/devicetree/bindings/pci/mediatek,gen2v1-pcie.txt
> new file mode 100644
> index 000..545d8cf
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/mediatek,gen2v1-pcie.txt
> @@ -0,0 +1,174 @@
> +Mediatek Gen2 V1 PCIe controller
> +
> +PCIe subsys supports single root complex (RC) with 3 Root Ports. Each root
> +ports supports a Gen2 1-lane Link. It includes one Host/PCI bridge and 3
> +PCIe MAC. Each port has PIPE interface to PHY. There are 3 bus master for
> +data access and 1 bus slave for Configuration and Status Register access.
> +
> +This controller is available on MT7623 series SoCs.
> +  
> +Required properties:
> +- compatible: Should contain "mediatek,gen2v1-pcie".
> +- device_type: Must be "pci"
> +- reg: Base addresses and lengths of the PCIe controller.
> +- #address-cells: Address representation for root ports (must be 3)
> +  - cell 0 specifies the bus and device numbers of the root port:
> +[23:16]: bus number
> +[15:11]: device number
> +  - cell 1 denotes the upper 32 address bits and should be 0
> +  - cell 2 contains the lower 32 address bits and is used to translate to the
> +CPU address space

This is all standard PCI bus binding. You don't need to define it here. 
"must be 3" is sufficient.

> +- #size-cells: Size representation for root ports (must be 2)
> +- #interrupt-cells: Size representation for interrupts (must be 1)
> +- interrupts: Three interrupt outputs of the controller. Must contain an
> +  entry for each entry in the interrupt-names property.

Where's interrupt-names?

> +- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
> +  Please refer to the standard PCI bus binding document for a more detailed
> +  explanation.
> +- clocks: Must contain an entry for each entry in clock-names.
> +  See ../clocks/clock-bindings.txt for details.
> +- clock-names: Must include the following entries:
> +  - free_ck  :for reference clock of PCIe subsys
> +  - sys_ck0  :for clock of Port0 MAC
> +  - sys_ck1  :for clock of Port1 MAC
> +  - sys_ck2  :for clock of Port2 MAC
> +- resets: Must contain an entry for each entry in reset-names.
> +  See ../reset/reset.txt for details.
> +- reset-names: Must include the following entries:
> +  - pcie-rst0:port0 reset
> +  - pcie-rst1:port1 reset
> +  - pcie-rst2:port2 reset
> +- phys: list of PHY specifiers (used by generic PHY framework)
> +- phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
> +  number of PHYs as specified in *phys* property.
> +- power-domains: A phandle and power domain specifier pair to the power 
> domain
> +  which is responsible for collapsing and restoring power to the peripheral
> +- bus-range: Range of bus numbers associated with this controller
> +- ranges: Describes the translation of addresses for root ports and standard
> +  PCI regions. The entries must be 6 cells each, where the first three cells
> +  correspond to the address as described for the #address-cells property
> +  above, the fourth cell is the physical CPU address to translate to and the
> +  fifth and six cells are as described for the #size-cells property above.

Don't need to define what ranges is here, just what the entries should 
be:

> +  - The first three entries are expected to translate the addresses for the 
> root
> +port registers, which are referenced by the assigned-addresses property 
> of
> +the root port nodes (see below).
> +  - The remaining entries setup the mapping for the standard I/O and memory
> + regions.
> +  Please refer to the standard PCI bus binding document for a more detailed
> +  explanation.
> +
> +In addition, the device tree node must have sub-nodes describing each
> +PCIe port interface, having the following mandatory properties:
> +
> +Required properties:
> +- device_type: Must be "pci"
> +- assigned-addresses: Address and size of the port configuration registers
> +- reg: Only the first four bytes are used to refer to the correct bus number
> +  and device number.
> +- #address-cells: Must be 3
> +- #size-cells: Must be 2
> +- #interrupt-cells: Size representation for interrupts (must be 1)
> +- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
> +  Please refer to the standard PCI bus binding document for a more detailed
> +  explanation.
> +- ranges: Sub-ranges distributed from the PCIe controller node. An empty
> +  property is sufficient.
> +- num-lanes: Number of lanes to use for this port.
> +
> 

[PATCH v1 2/2] dt-bindings: pcie: Add documentation for Mediatek PCIe

[Ryder Lee]

Add binding document for Mediatek PCIe Gen2 v1 host controller driver.

Signed-off-by: Ryder Lee 
---
 .../bindings/pci/mediatek,gen2v1-pcie.txt  | 174 +
 1 file changed, 174 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/pci/mediatek,gen2v1-pcie.txt

diff --git a/Documentation/devicetree/bindings/pci/mediatek,gen2v1-pcie.txt 
b/Documentation/devicetree/bindings/pci/mediatek,gen2v1-pcie.txt
new file mode 100644
index 000..545d8cf
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/mediatek,gen2v1-pcie.txt
@@ -0,0 +1,174 @@
+Mediatek Gen2 V1 PCIe controller
+
+PCIe subsys supports single root complex (RC) with 3 Root Ports. Each root
+ports supports a Gen2 1-lane Link. It includes one Host/PCI bridge and 3
+PCIe MAC. Each port has PIPE interface to PHY. There are 3 bus master for
+data access and 1 bus slave for Configuration and Status Register access.
+
+This controller is available on MT7623 series SoCs.
+  
+Required properties:
+- compatible: Should contain "mediatek,gen2v1-pcie".
+- device_type: Must be "pci"
+- reg: Base addresses and lengths of the PCIe controller.
+- #address-cells: Address representation for root ports (must be 3)
+  - cell 0 specifies the bus and device numbers of the root port:
+[23:16]: bus number
+[15:11]: device number
+  - cell 1 denotes the upper 32 address bits and should be 0
+  - cell 2 contains the lower 32 address bits and is used to translate to the
+CPU address space
+- #size-cells: Size representation for root ports (must be 2)
+- #interrupt-cells: Size representation for interrupts (must be 1)
+- interrupts: Three interrupt outputs of the controller. Must contain an
+  entry for each entry in the interrupt-names property.
+- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
+  Please refer to the standard PCI bus binding document for a more detailed
+  explanation.
+- clocks: Must contain an entry for each entry in clock-names.
+  See ../clocks/clock-bindings.txt for details.
+- clock-names: Must include the following entries:
+  - free_ck:for reference clock of PCIe subsys
+  - sys_ck0:for clock of Port0 MAC
+  - sys_ck1:for clock of Port1 MAC
+  - sys_ck2:for clock of Port2 MAC
+- resets: Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names: Must include the following entries:
+  - pcie-rst0  :port0 reset
+  - pcie-rst1  :port1 reset
+  - pcie-rst2  :port2 reset
+- phys: list of PHY specifiers (used by generic PHY framework)
+- phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
+  number of PHYs as specified in *phys* property.
+- power-domains: A phandle and power domain specifier pair to the power domain
+  which is responsible for collapsing and restoring power to the peripheral
+- bus-range: Range of bus numbers associated with this controller
+- ranges: Describes the translation of addresses for root ports and standard
+  PCI regions. The entries must be 6 cells each, where the first three cells
+  correspond to the address as described for the #address-cells property
+  above, the fourth cell is the physical CPU address to translate to and the
+  fifth and six cells are as described for the #size-cells property above.
+  - The first three entries are expected to translate the addresses for the 
root
+port registers, which are referenced by the assigned-addresses property of
+the root port nodes (see below).
+  - The remaining entries setup the mapping for the standard I/O and memory
+   regions.
+  Please refer to the standard PCI bus binding document for a more detailed
+  explanation.
+
+In addition, the device tree node must have sub-nodes describing each
+PCIe port interface, having the following mandatory properties:
+
+Required properties:
+- device_type: Must be "pci"
+- assigned-addresses: Address and size of the port configuration registers
+- reg: Only the first four bytes are used to refer to the correct bus number
+  and device number.
+- #address-cells: Must be 3
+- #size-cells: Must be 2
+- #interrupt-cells: Size representation for interrupts (must be 1)
+- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
+  Please refer to the standard PCI bus binding document for a more detailed
+  explanation.
+- ranges: Sub-ranges distributed from the PCIe controller node. An empty
+  property is sufficient.
+- num-lanes: Number of lanes to use for this port.
+
+Examples:
+
+SoC dtsi:
+
+   hifsys: syscon@1a00 {
+   compatible = "mediatek,mt7623-hifsys", "syscon";
+   reg = <0 0x1a00 0 0x1000>;
+   #clock-cells = <1>;
+   #reset-cells = <1>;
+   };
+
+   pcie: pcie-controller@1a14 {
+   compatible = "mediatek,gen2v1-pcie";
+   device_type = "pci";
+   reg = <0 0x1a14 0 0x1000>; /* PCIe shared 

[PATCH v1 2/2] dt-bindings: pcie: Add documentation for Mediatek PCIe

[Ryder Lee]

Add binding document for Mediatek PCIe Gen2 v1 host controller driver.

Signed-off-by: Ryder Lee 
---
 .../bindings/pci/mediatek,gen2v1-pcie.txt  | 174 +
 1 file changed, 174 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/pci/mediatek,gen2v1-pcie.txt

diff --git a/Documentation/devicetree/bindings/pci/mediatek,gen2v1-pcie.txt 
b/Documentation/devicetree/bindings/pci/mediatek,gen2v1-pcie.txt
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+Mediatek Gen2 V1 PCIe controller
+
+PCIe subsys supports single root complex (RC) with 3 Root Ports. Each root
+ports supports a Gen2 1-lane Link. It includes one Host/PCI bridge and 3
+PCIe MAC. Each port has PIPE interface to PHY. There are 3 bus master for
+data access and 1 bus slave for Configuration and Status Register access.
+
+This controller is available on MT7623 series SoCs.
+  
+Required properties:
+- compatible: Should contain "mediatek,gen2v1-pcie".
+- device_type: Must be "pci"
+- reg: Base addresses and lengths of the PCIe controller.
+- #address-cells: Address representation for root ports (must be 3)
+  - cell 0 specifies the bus and device numbers of the root port:
+[23:16]: bus number
+[15:11]: device number
+  - cell 1 denotes the upper 32 address bits and should be 0
+  - cell 2 contains the lower 32 address bits and is used to translate to the
+CPU address space
+- #size-cells: Size representation for root ports (must be 2)
+- #interrupt-cells: Size representation for interrupts (must be 1)
+- interrupts: Three interrupt outputs of the controller. Must contain an
+  entry for each entry in the interrupt-names property.
+- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
+  Please refer to the standard PCI bus binding document for a more detailed
+  explanation.
+- clocks: Must contain an entry for each entry in clock-names.
+  See ../clocks/clock-bindings.txt for details.
+- clock-names: Must include the following entries:
+  - free_ck:for reference clock of PCIe subsys
+  - sys_ck0:for clock of Port0 MAC
+  - sys_ck1:for clock of Port1 MAC
+  - sys_ck2:for clock of Port2 MAC
+- resets: Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names: Must include the following entries:
+  - pcie-rst0  :port0 reset
+  - pcie-rst1  :port1 reset
+  - pcie-rst2  :port2 reset
+- phys: list of PHY specifiers (used by generic PHY framework)
+- phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
+  number of PHYs as specified in *phys* property.
+- power-domains: A phandle and power domain specifier pair to the power domain
+  which is responsible for collapsing and restoring power to the peripheral
+- bus-range: Range of bus numbers associated with this controller
+- ranges: Describes the translation of addresses for root ports and standard
+  PCI regions. The entries must be 6 cells each, where the first three cells
+  correspond to the address as described for the #address-cells property
+  above, the fourth cell is the physical CPU address to translate to and the
+  fifth and six cells are as described for the #size-cells property above.
+  - The first three entries are expected to translate the addresses for the 
root
+port registers, which are referenced by the assigned-addresses property of
+the root port nodes (see below).
+  - The remaining entries setup the mapping for the standard I/O and memory
+   regions.
+  Please refer to the standard PCI bus binding document for a more detailed
+  explanation.
+
+In addition, the device tree node must have sub-nodes describing each
+PCIe port interface, having the following mandatory properties:
+
+Required properties:
+- device_type: Must be "pci"
+- assigned-addresses: Address and size of the port configuration registers
+- reg: Only the first four bytes are used to refer to the correct bus number
+  and device number.
+- #address-cells: Must be 3
+- #size-cells: Must be 2
+- #interrupt-cells: Size representation for interrupts (must be 1)
+- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
+  Please refer to the standard PCI bus binding document for a more detailed
+  explanation.
+- ranges: Sub-ranges distributed from the PCIe controller node. An empty
+  property is sufficient.
+- num-lanes: Number of lanes to use for this port.
+
+Examples:
+
+SoC dtsi:
+
+   hifsys: syscon@1a00 {
+   compatible = "mediatek,mt7623-hifsys", "syscon";
+   reg = <0 0x1a00 0 0x1000>;
+   #clock-cells = <1>;
+   #reset-cells = <1>;
+   };
+
+   pcie: pcie-controller@1a14 {
+   compatible = "mediatek,gen2v1-pcie";
+   device_type = "pci";
+   reg = <0 0x1a14 0 0x1000>; /* PCIe shared registers */
+