[PATCH v2 06/19] clk: meson: switch gxbb ao_clk to clk_regmap

[Jerome Brunet]

Drop the gxbb ao specific regmap based clock and use the
meson clk_regmap based clock instead.

Signed-off-by: Jerome Brunet 
---
 drivers/clk/meson/Kconfig  |  1 +
 drivers/clk/meson/Makefile |  2 +-
 drivers/clk/meson/gxbb-aoclk.c | 20 ++--
 drivers/clk/meson/gxbb-aoclk.h |  1 -
 4 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index e97e85077da1..33d148e19066 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -20,6 +20,7 @@ config COMMON_CLK_GXBB
bool
depends on COMMON_CLK_AMLOGIC
select RESET_CONTROLLER
+   select COMMON_CLK_REGMAP_MESON
help
  Support for the clock controller on AmLogic S905 devices, aka gxbb.
  Say Y if you want peripherals and CPU frequency scaling to work.
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index 11a5058a..465086118d62 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -4,6 +4,6 @@
 
 obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-cpu.o clk-mpll.o 
clk-audio-divider.o
 obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
-obj-$(CONFIG_COMMON_CLK_GXBB)   += gxbb.o gxbb-aoclk.o gxbb-aoclk-regmap.o 
gxbb-aoclk-32k.o
+obj-$(CONFIG_COMMON_CLK_GXBB)   += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
 obj-$(CONFIG_COMMON_CLK_AXG)+= axg.o
 obj-$(CONFIG_COMMON_CLK_REGMAP_MESON)  += clk-regmap.o
diff --git a/drivers/clk/meson/gxbb-aoclk.c b/drivers/clk/meson/gxbb-aoclk.c
index 6c161e0a8e59..9ec23ae9a219 100644
--- a/drivers/clk/meson/gxbb-aoclk.c
+++ b/drivers/clk/meson/gxbb-aoclk.c
@@ -62,10 +62,9 @@
 #include 
 #include 
 #include 
+#include "clk-regmap.h"
 #include "gxbb-aoclk.h"
 
-static DEFINE_SPINLOCK(gxbb_aoclk_lock);
-
 struct gxbb_aoclk_reset_controller {
struct reset_controller_dev reset;
unsigned int *data;
@@ -87,12 +86,14 @@ static const struct reset_control_ops gxbb_aoclk_reset_ops 
= {
 };
 
 #define GXBB_AO_GATE(_name, _bit)  \
-static struct aoclk_gate_regmap _name##_ao = { \
-   .bit_idx = (_bit),  \
-   .lock = _aoclk_lock,   \
+static struct clk_regmap _name##_ao = {
\
+   .data = &(struct clk_regmap_gate_data) {\
+   .offset = AO_RTI_GEN_CNTL_REG0, \
+   .bit_idx = (_bit),  \
+   },  \
.hw.init = &(struct clk_init_data) {\
.name = #_name "_ao",   \
-   .ops = _aoclk_gate_regmap_ops,\
+   .ops = _regmap_gate_ops,\
.parent_names = (const char *[]){ "clk81" },\
.num_parents = 1,   \
.flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), \
@@ -107,7 +108,6 @@ GXBB_AO_GATE(uart2, 5);
 GXBB_AO_GATE(ir_blaster, 6);
 
 static struct aoclk_cec_32k cec_32k_ao = {
-   .lock = _aoclk_lock,
.hw.init = &(struct clk_init_data) {
.name = "cec_32k_ao",
.ops = _aoclk_cec_32k_ops,
@@ -126,7 +126,7 @@ static unsigned int gxbb_aoclk_reset[] = {
[RESET_AO_IR_BLASTER] = 23,
 };
 
-static struct aoclk_gate_regmap *gxbb_aoclk_gate[] = {
+static struct clk_regmap *gxbb_aoclk_gate[] = {
[CLKID_AO_REMOTE] = _ao,
[CLKID_AO_I2C_MASTER] = _master_ao,
[CLKID_AO_I2C_SLAVE] = _slave_ao,
@@ -177,10 +177,10 @@ static int gxbb_aoclkc_probe(struct platform_device *pdev)
 * Populate regmap and register all clks
 */
for (clkid = 0; clkid < ARRAY_SIZE(gxbb_aoclk_gate); clkid++) {
-   gxbb_aoclk_gate[clkid]->regmap = regmap;
+   gxbb_aoclk_gate[clkid]->map = regmap;
 
ret = devm_clk_hw_register(dev,
-   gxbb_aoclk_onecell_data.hws[clkid]);
+  gxbb_aoclk_onecell_data.hws[clkid]);
if (ret)
return ret;
}
diff --git a/drivers/clk/meson/gxbb-aoclk.h b/drivers/clk/meson/gxbb-aoclk.h
index e8604c8f7eee..127d58954cca 100644
--- a/drivers/clk/meson/gxbb-aoclk.h
+++ b/drivers/clk/meson/gxbb-aoclk.h
@@ -32,7 +32,6 @@ extern const struct clk_ops meson_aoclk_gate_regmap_ops;
 struct aoclk_cec_32k {
struct clk_hw hw;
struct regmap *regmap;
-   spinlock_t *lock;
 };
 
 #define to_aoclk_cec_32k(_hw) container_of(_hw, struct aoclk_cec_32k, hw)
-- 
2.14.3

[PATCH v2 06/19] clk: meson: switch gxbb ao_clk to clk_regmap

[Jerome Brunet]

Drop the gxbb ao specific regmap based clock and use the
meson clk_regmap based clock instead.

Signed-off-by: Jerome Brunet 
---
 drivers/clk/meson/Kconfig  |  1 +
 drivers/clk/meson/Makefile |  2 +-
 drivers/clk/meson/gxbb-aoclk.c | 20 ++--
 drivers/clk/meson/gxbb-aoclk.h |  1 -
 4 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index e97e85077da1..33d148e19066 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -20,6 +20,7 @@ config COMMON_CLK_GXBB
bool
depends on COMMON_CLK_AMLOGIC
select RESET_CONTROLLER
+   select COMMON_CLK_REGMAP_MESON
help
  Support for the clock controller on AmLogic S905 devices, aka gxbb.
  Say Y if you want peripherals and CPU frequency scaling to work.
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index 11a5058a..465086118d62 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -4,6 +4,6 @@
 
 obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-cpu.o clk-mpll.o 
clk-audio-divider.o
 obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
-obj-$(CONFIG_COMMON_CLK_GXBB)   += gxbb.o gxbb-aoclk.o gxbb-aoclk-regmap.o 
gxbb-aoclk-32k.o
+obj-$(CONFIG_COMMON_CLK_GXBB)   += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
 obj-$(CONFIG_COMMON_CLK_AXG)+= axg.o
 obj-$(CONFIG_COMMON_CLK_REGMAP_MESON)  += clk-regmap.o
diff --git a/drivers/clk/meson/gxbb-aoclk.c b/drivers/clk/meson/gxbb-aoclk.c
index 6c161e0a8e59..9ec23ae9a219 100644
--- a/drivers/clk/meson/gxbb-aoclk.c
+++ b/drivers/clk/meson/gxbb-aoclk.c
@@ -62,10 +62,9 @@
 #include 
 #include 
 #include 
+#include "clk-regmap.h"
 #include "gxbb-aoclk.h"
 
-static DEFINE_SPINLOCK(gxbb_aoclk_lock);
-
 struct gxbb_aoclk_reset_controller {
struct reset_controller_dev reset;
unsigned int *data;
@@ -87,12 +86,14 @@ static const struct reset_control_ops gxbb_aoclk_reset_ops 
= {
 };
 
 #define GXBB_AO_GATE(_name, _bit)  \
-static struct aoclk_gate_regmap _name##_ao = { \
-   .bit_idx = (_bit),  \
-   .lock = _aoclk_lock,   \
+static struct clk_regmap _name##_ao = {
\
+   .data = &(struct clk_regmap_gate_data) {\
+   .offset = AO_RTI_GEN_CNTL_REG0, \
+   .bit_idx = (_bit),  \
+   },  \
.hw.init = &(struct clk_init_data) {\
.name = #_name "_ao",   \
-   .ops = _aoclk_gate_regmap_ops,\
+   .ops = _regmap_gate_ops,\
.parent_names = (const char *[]){ "clk81" },\
.num_parents = 1,   \
.flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), \
@@ -107,7 +108,6 @@ GXBB_AO_GATE(uart2, 5);
 GXBB_AO_GATE(ir_blaster, 6);
 
 static struct aoclk_cec_32k cec_32k_ao = {
-   .lock = _aoclk_lock,
.hw.init = &(struct clk_init_data) {
.name = "cec_32k_ao",
.ops = _aoclk_cec_32k_ops,
@@ -126,7 +126,7 @@ static unsigned int gxbb_aoclk_reset[] = {
[RESET_AO_IR_BLASTER] = 23,
 };
 
-static struct aoclk_gate_regmap *gxbb_aoclk_gate[] = {
+static struct clk_regmap *gxbb_aoclk_gate[] = {
[CLKID_AO_REMOTE] = _ao,
[CLKID_AO_I2C_MASTER] = _master_ao,
[CLKID_AO_I2C_SLAVE] = _slave_ao,
@@ -177,10 +177,10 @@ static int gxbb_aoclkc_probe(struct platform_device *pdev)
 * Populate regmap and register all clks
 */
for (clkid = 0; clkid < ARRAY_SIZE(gxbb_aoclk_gate); clkid++) {
-   gxbb_aoclk_gate[clkid]->regmap = regmap;
+   gxbb_aoclk_gate[clkid]->map = regmap;
 
ret = devm_clk_hw_register(dev,
-   gxbb_aoclk_onecell_data.hws[clkid]);
+  gxbb_aoclk_onecell_data.hws[clkid]);
if (ret)
return ret;
}
diff --git a/drivers/clk/meson/gxbb-aoclk.h b/drivers/clk/meson/gxbb-aoclk.h
index e8604c8f7eee..127d58954cca 100644
--- a/drivers/clk/meson/gxbb-aoclk.h
+++ b/drivers/clk/meson/gxbb-aoclk.h
@@ -32,7 +32,6 @@ extern const struct clk_ops meson_aoclk_gate_regmap_ops;
 struct aoclk_cec_32k {
struct clk_hw hw;
struct regmap *regmap;
-   spinlock_t *lock;
 };
 
 #define to_aoclk_cec_32k(_hw) container_of(_hw, struct aoclk_cec_32k, hw)
-- 
2.14.3